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-rw-r--r--arch/arm/Kconfig2
-rw-r--r--arch/arm/dts/Makefile2
-rw-r--r--arch/arm/dts/versal-mini-ospi-single.dts16
-rw-r--r--arch/arm/dts/versal-mini-ospi.dtsi77
-rw-r--r--arch/arm/dts/versal-mini-qspi-single.dts16
-rw-r--r--arch/arm/dts/versal-mini-qspi.dtsi72
-rw-r--r--arch/arm/dts/zynq-7000.dtsi2
-rw-r--r--arch/arm/dts/zynqmp-zcu106-revA.dts19
-rw-r--r--arch/arm/mach-versal-net/cpu.c5
-rw-r--r--arch/arm/mach-zynq/include/mach/sys_proto.h2
-rw-r--r--arch/arm/mach-zynqmp/include/mach/sys_proto.h1
11 files changed, 203 insertions, 11 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 7866e8f..f95ed71 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1230,7 +1230,7 @@ config ARCH_VERSAL
imply ENV_VARS_UBOOT_RUNTIME_CONFIG
config ARCH_VERSAL_NET
- bool "Support Xilinx Keystone Platform"
+ bool "Support Xilinx Versal NET Platform"
select ARM64
select CLK
select DM
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index e89598a..43951a7 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -383,6 +383,8 @@ dtb-$(CONFIG_ARCH_VERSAL) += \
versal-mini.dtb \
versal-mini-emmc0.dtb \
versal-mini-emmc1.dtb \
+ versal-mini-ospi-single.dtb \
+ versal-mini-qspi-single.dtb \
xilinx-versal-virt.dtb
dtb-$(CONFIG_ARCH_VERSAL_NET) += \
versal-net-mini.dtb \
diff --git a/arch/arm/dts/versal-mini-ospi-single.dts b/arch/arm/dts/versal-mini-ospi-single.dts
new file mode 100644
index 0000000..23f6e47
--- /dev/null
+++ b/arch/arm/dts/versal-mini-ospi-single.dts
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Xilinx Versal QSPI single DTS
+ *
+ * Copyright (C) 2018-2020 Xilinx, Inc.
+ */
+
+#include "versal-mini-ospi.dtsi"
+
+/ {
+ model = "Xilinx Versal MINI OSPI SINGLE";
+};
+
+&flash0 {
+ spi-rx-bus-width = <8>;
+};
diff --git a/arch/arm/dts/versal-mini-ospi.dtsi b/arch/arm/dts/versal-mini-ospi.dtsi
new file mode 100644
index 0000000..a4b76e2
--- /dev/null
+++ b/arch/arm/dts/versal-mini-ospi.dtsi
@@ -0,0 +1,77 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx Versal Mini OSPI Configuration
+ *
+ * (C) Copyright 2018-2019, Xilinx, Inc.
+ *
+ * Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+
+/dts-v1/;
+
+/ {
+ compatible = "xlnx,versal";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ model = "Xilinx Versal MINI OSPI";
+
+ clk125: clk125 {
+ compatible = "fixed-clock";
+ #clock-cells = <0x0>;
+ clock-frequency = <125000000>;
+ };
+
+ dcc: dcc {
+ compatible = "arm,dcc";
+ status = "okay";
+ u-boot,dm-pre-reloc;
+ };
+
+ amba: amba {
+ u-boot,dm-pre-reloc;
+ compatible = "simple-bus";
+ #address-cells = <0x2>;
+ #size-cells = <0x2>;
+ ranges;
+
+ ospi: spi@f1010000 {
+ compatible = "cadence,qspi", "cdns,qspi-nor";
+ status = "okay";
+ reg = <0 0xf1010000 0 0x10000 0 0xc0000000 0 0x20000000>;
+ clock-names = "ref_clk", "pclk";
+ clocks = <&clk125 &clk125>;
+ bus-num = <2>;
+ num-cs = <1>;
+ cdns,fifo-depth = <256>;
+ cdns,fifo-width = <4>;
+ cdns,is-dma = <1>;
+ cdns,trigger-address = <0xc0000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ flash0: flash@0 {
+ compatible = "n25q512a", "micron,m25p80",
+ "jedec,spi-nor";
+ reg = <0x0>;
+ spi-tx-bus-width = <8>;
+ spi-rx-bus-width = <8>;
+ spi-max-frequency = <20000000>;
+ };
+ };
+ };
+
+ aliases {
+ serial0 = &dcc;
+ spi0 = &ospi;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200";
+ };
+
+ memory@fffc0000 {
+ device_type = "memory";
+ reg = <0x0 0xfffc0000 0x0 0x40000>;
+ };
+};
diff --git a/arch/arm/dts/versal-mini-qspi-single.dts b/arch/arm/dts/versal-mini-qspi-single.dts
new file mode 100644
index 0000000..ee518d5
--- /dev/null
+++ b/arch/arm/dts/versal-mini-qspi-single.dts
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Xilinx Versal QSPI single DTS
+ *
+ * Copyright (C) 2018-2019 Xilinx, Inc.
+ */
+
+#include "versal-mini-qspi.dtsi"
+
+/ {
+ model = "Xilinx Versal MINI QSPI SINGLE";
+};
+
+&flash0 {
+ spi-rx-bus-width = <4>;
+};
diff --git a/arch/arm/dts/versal-mini-qspi.dtsi b/arch/arm/dts/versal-mini-qspi.dtsi
new file mode 100644
index 0000000..71d0ba5
--- /dev/null
+++ b/arch/arm/dts/versal-mini-qspi.dtsi
@@ -0,0 +1,72 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx Versal Mini QSPI Configuration
+ *
+ * (C) Copyright 2018-2019, Xilinx, Inc.
+ *
+ * Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+
+/dts-v1/;
+
+/ {
+ compatible = "xlnx,versal";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ model = "Xilinx Versal MINI QSPI";
+
+ clk150: clk150 {
+ compatible = "fixed-clock";
+ #clock-cells = <0x0>;
+ clock-frequency = <150000000>;
+ };
+
+ dcc: dcc {
+ compatible = "arm,dcc";
+ status = "okay";
+ u-boot,dm-pre-reloc;
+ };
+
+ amba: amba {
+ u-boot,dm-pre-reloc;
+ compatible = "simple-bus";
+ #address-cells = <0x2>;
+ #size-cells = <0x2>;
+ ranges;
+
+ qspi: spi@f1030000 {
+ compatible = "xlnx,versal-qspi-1.0";
+ status = "okay";
+ clock-names = "ref_clk", "pclk";
+ num-cs = <0x1>;
+ reg = <0x0 0xf1030000 0x0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk150 &clk150>;
+
+ flash0: flash@0 {
+ compatible = "n25q512a", "micron,m25p80",
+ "jedec,spi-nor";
+ reg = <0x0>;
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+ spi-max-frequency = <20000000>;
+ };
+ };
+ };
+
+ aliases {
+ serial0 = &dcc;
+ spi0 = &qspi;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200";
+ };
+
+ memory@fffc0000 {
+ device_type = "memory";
+ reg = <0x0 0xfffc0000 0x0 0x40000>;
+ };
+};
diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi
index edc147d..f72ef52 100644
--- a/arch/arm/dts/zynq-7000.dtsi
+++ b/arch/arm/dts/zynq-7000.dtsi
@@ -340,7 +340,7 @@
u-boot,dm-pre-reloc;
#clock-cells = <1>;
compatible = "xlnx,ps7-clkc";
- fclk-enable = <0>;
+ fclk-enable = <0xf>;
clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
"cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
"dci", "lqspi", "smc", "pcap", "gem0", "gem1",
diff --git a/arch/arm/dts/zynqmp-zcu106-revA.dts b/arch/arm/dts/zynqmp-zcu106-revA.dts
index 3e13767..4858b4d 100644
--- a/arch/arm/dts/zynqmp-zcu106-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu106-revA.dts
@@ -200,12 +200,19 @@
phy-mode = "rgmii-id";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gem3_default>;
- phy0: ethernet-phy@c {
- reg = <0xc>;
- ti,rx-internal-delay = <0x8>;
- ti,tx-internal-delay = <0xa>;
- ti,fifo-depth = <0x1>;
- ti,dp83867-rxctrl-strap-quirk;
+ mdio: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ phy0: ethernet-phy@c {
+ #phy-cells = <1>;
+ reg = <0xc>;
+ compatible = "ethernet-phy-id2000.a231";
+ ti,rx-internal-delay = <0x8>;
+ ti,tx-internal-delay = <0xa>;
+ ti,fifo-depth = <0x1>;
+ ti,dp83867-rxctrl-strap-quirk;
+ reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>;
+ };
};
};
diff --git a/arch/arm/mach-versal-net/cpu.c b/arch/arm/mach-versal-net/cpu.c
index 4c9b154..a82741e 100644
--- a/arch/arm/mach-versal-net/cpu.c
+++ b/arch/arm/mach-versal-net/cpu.c
@@ -15,6 +15,7 @@
#include <asm/arch/hardware.h>
#include <asm/arch/sys_proto.h>
#include <asm/cache.h>
+#include <dm/platdata.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -87,3 +88,7 @@ u64 get_page_table_size(void)
{
return 0x14000;
}
+
+U_BOOT_DRVINFO(soc_xilinx_versal_net) = {
+ .name = "soc_xilinx_versal_net",
+};
diff --git a/arch/arm/mach-zynq/include/mach/sys_proto.h b/arch/arm/mach-zynq/include/mach/sys_proto.h
index 1dc16d4..268ec50 100644
--- a/arch/arm/mach-zynq/include/mach/sys_proto.h
+++ b/arch/arm/mach-zynq/include/mach/sys_proto.h
@@ -17,6 +17,4 @@ extern int zynq_slcr_get_mio_pin_status(const char *periph);
extern void zynq_ddrc_init(void);
extern unsigned int zynq_get_silicon_version(void);
-int zynq_board_read_rom_ethaddr(unsigned char *ethaddr);
-
#endif /* _SYS_PROTO_H_ */
diff --git a/arch/arm/mach-zynqmp/include/mach/sys_proto.h b/arch/arm/mach-zynqmp/include/mach/sys_proto.h
index 9fffb4e..c6733ed 100644
--- a/arch/arm/mach-zynqmp/include/mach/sys_proto.h
+++ b/arch/arm/mach-zynqmp/include/mach/sys_proto.h
@@ -46,7 +46,6 @@ enum {
TCM_SPLIT,
};
-int zynq_board_read_rom_ethaddr(unsigned char *ethaddr);
unsigned int zynqmp_get_silicon_version(void);
int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value);
generated by cgit v1.1 at 2024-09-17 08:27:50 +0000