1 files changed, 27 insertions, 67 deletions
diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_arria10.h b/arch/arm/mach-socfpga/include/mach/system_manager_arria10.h
index 14052b9..e4fc6d2 100644
--- a/arch/arm/mach-socfpga/include/mach/system_manager_arria10.h
+++ b/arch/arm/mach-socfpga/include/mach/system_manager_arria10.h
@@ -6,73 +6,33 @@
 #ifndef _SYSTEM_MANAGER_ARRIA10_H_
 #define _SYSTEM_MANAGER_ARRIA10_H_
 
-struct socfpga_system_manager {
-	u32  siliconid1;
-	u32  siliconid2;
-	u32  wddbg;
-	u32  bootinfo;
-	u32  mpu_ctrl_l2_ecc;
-	u32  _pad_0x14_0x1f[3];
-	u32  dma;
-	u32  dma_periph;
-	u32  sdmmcgrp_ctrl;
-	u32  sdmmc_l3master;
-	u32  nand_bootstrap;
-	u32  nand_l3master;
-	u32  usb0_l3master;
-	u32  usb1_l3master;
-	u32  emac_global;
-	u32  emac[3];
-	u32  _pad_0x50_0x5f[4];
-	u32  fpgaintf_en_global;
-	u32  fpgaintf_en_0;
-	u32  fpgaintf_en_1;
-	u32  fpgaintf_en_2;
-	u32  fpgaintf_en_3;
-	u32  _pad_0x74_0x7f[3];
-	u32  noc_addr_remap_value;
-	u32  noc_addr_remap_set;
-	u32  noc_addr_remap_clear;
-	u32  _pad_0x8c_0x8f;
-	u32  ecc_intmask_value;
-	u32  ecc_intmask_set;
-	u32  ecc_intmask_clr;
-	u32  ecc_intstatus_serr;
-	u32  ecc_intstatus_derr;
-	u32  mpu_status_l2_ecc;
-	u32  mpu_clear_l2_ecc;
-	u32  mpu_status_l1_parity;
-	u32  mpu_clear_l1_parity;
-	u32  mpu_set_l1_parity;
-	u32  _pad_0xb8_0xbf[2];
-	u32  noc_timeout;
-	u32  noc_idlereq_set;
-	u32  noc_idlereq_clr;
-	u32  noc_idlereq_value;
-	u32  noc_idleack;
-	u32  noc_idlestatus;
-	u32  fpga2soc_ctrl;
-	u32  _pad_0xdc_0xff[9];
-	u32  tsmc_tsel_0;
-	u32  tsmc_tsel_1;
-	u32  tsmc_tsel_2;
-	u32  tsmc_tsel_3;
-	u32  _pad_0x110_0x200[60];
-	u32  romhw_ctrl;
-	u32  romcode_ctrl;
-	u32  romcode_cpu1startaddr;
-	u32  romcode_initswstate;
-	u32  romcode_initswlastld;
-	u32  _pad_0x214_0x217;
-	u32  warmram_enable;
-	u32  warmram_datastart;
-	u32  warmram_length;
-	u32  warmram_execution;
-	u32  warmram_crc;
-	u32  _pad_0x22c_0x22f;
-	u32  isw_handoff[8];
-	u32  romcode_bootromswstate[8];
-};
+#define SYSMGR_A10_WDDBG			0x08
+#define SYSMGR_A10_BOOTINFO			0x0c
+#define SYSMGR_A10_DMA				0x20
+#define SYSMGR_A10_DMA_PERIPH			0x24
+#define SYSMGR_A10_SDMMC			0x28
+#define SYSMGR_A10_SDMMC_L3MASTER		0x2c
+#define SYSMGR_A10_EMAC_GLOBAL			0x40
+#define SYSMGR_A10_EMAC0			0x44
+#define SYSMGR_A10_EMAC1			0x48
+#define SYSMGR_A10_EMAC2			0x4c
+#define SYSMGR_A10_FPGAINTF_EN_GLOBAL		0x60
+#define SYSMGR_A10_FPGAINTF_EN0			0x64
+#define SYSMGR_A10_FPGAINTF_EN1			0x68
+#define SYSMGR_A10_FPGAINTF_EN2			0x6c
+#define SYSMGR_A10_FPGAINTF_EN3			0x70
+#define SYSMGR_A10_ECC_INTMASK_VAL		0x90
+#define SYSMGR_A10_ECC_INTMASK_SET		0x94
+#define SYSMGR_A10_ECC_INTMASK_CLR		0x98
+#define SYSMGR_A10_NOC_TIMEOUT			0xc0
+#define SYSMGR_A10_NOC_IDLEREQ_SET		0xc4
+#define SYSMGR_A10_NOC_IDLEREQ_CLR		0xc8
+#define SYSMGR_A10_NOC_IDLEREQ_VAL		0xcc
+#define SYSMGR_A10_NOC_IDLEACK			0xd0
+#define SYSMGR_A10_NOC_IDLESTATUS		0xd4
+#define SYSMGR_A10_FPGA2SOC_CTRL		0xd8
+
+#define SYSMGR_SDMMC				SYSMGR_A10_SDMMC
 
 #define SYSMGR_SDMMC_SMPLSEL_SHIFT	4
 #define SYSMGR_BOOTINFO_BSEL_SHIFT	12