diff options
Diffstat (limited to 'arch/arm/include/asm')
-rw-r--r-- | arch/arm/include/asm/arch-armada100/mfp.h | 2 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-mx25/imx-regs.h | 22 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-mx5/imx-regs.h | 4 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-mx6/mx6_plugin.S | 4 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-mx7/mx7_plugin.S | 2 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-mx7ulp/mx7ulp_plugin.S | 2 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-rockchip/cru_rk3368.h | 16 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-vf610/iomux-vf610.h | 8 | ||||
-rw-r--r-- | arch/arm/include/asm/macro.h | 2 | ||||
-rw-r--r-- | arch/arm/include/asm/ti-common/davinci_nand.h | 6 |
10 files changed, 34 insertions, 34 deletions
diff --git a/arch/arm/include/asm/arch-armada100/mfp.h b/arch/arm/include/asm/arch-armada100/mfp.h index a808ee8..cd837ea 100644 --- a/arch/arm/include/asm/arch-armada100/mfp.h +++ b/arch/arm/include/asm/arch-armada100/mfp.h @@ -17,7 +17,7 @@ /* * Frequently used MFP Configuration macros for all ARMADA100 family of SoCs * - * offset, pull,pF, drv,dF, edge,eF ,afn,aF + * offset, pull,pF, drv,dF, edge,eF ,afn,aF */ /* UART1 */ #define MFP107_UART1_TXD (MFP_REG(0x01ac) | MFP_AF1 | MFP_DRIVE_FAST) diff --git a/arch/arm/include/asm/arch-mx25/imx-regs.h b/arch/arm/include/asm/arch-mx25/imx-regs.h index 5780969..d5ea868 100644 --- a/arch/arm/include/asm/arch-mx25/imx-regs.h +++ b/arch/arm/include/asm/arch-mx25/imx-regs.h @@ -50,11 +50,11 @@ struct ccm_regs { /* Enhanced SDRAM Controller (ESDRAMC) registers */ struct esdramc_regs { - u32 ctl0; /* control 0 */ - u32 cfg0; /* configuration 0 */ - u32 ctl1; /* control 1 */ - u32 cfg1; /* configuration 1 */ - u32 misc; /* miscellaneous */ + u32 ctl0; /* control 0 */ + u32 cfg0; /* configuration 0 */ + u32 ctl1; /* control 1 */ + u32 cfg1; /* configuration 1 */ + u32 misc; /* miscellaneous */ u32 pad[3]; u32 cdly1; /* Delay Line 1 configuration debug */ u32 cdly2; /* delay line 2 configuration debug */ @@ -66,11 +66,11 @@ struct esdramc_regs { /* General Purpose Timer (GPT) registers */ struct gpt_regs { - u32 ctrl; /* control */ - u32 pre; /* prescaler */ - u32 stat; /* status */ - u32 intr; /* interrupt */ - u32 cmp[3]; /* output compare 1-3 */ + u32 ctrl; /* control */ + u32 pre; /* prescaler */ + u32 stat; /* status */ + u32 intr; /* interrupt */ + u32 cmp[3]; /* output compare 1-3 */ u32 capt[2]; /* input capture 1-2 */ u32 counter; /* counter */ }; @@ -456,7 +456,7 @@ struct epit_regs { #define GPT_CTRL_TEN 1 /* Timer enable */ /* WDOG enable */ -#define WCR_WDE 0x04 +#define WCR_WDE 0x04 #define WSR_UNLOCK1 0x5555 #define WSR_UNLOCK2 0xAAAA diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h index 2731b7f..f763749 100644 --- a/arch/arm/include/asm/arch-mx5/imx-regs.h +++ b/arch/arm/include/asm/arch-mx5/imx-regs.h @@ -43,7 +43,7 @@ #define MMC_SDHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00004000) #define MMC_SDHC2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00008000) #define UART3_BASE (SPBA0_BASE_ADDR + 0x0000C000) -#define CSPI1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00010000) +#define CSPI1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00010000) #define SSI2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00014000) #define MMC_SDHC3_BASE_ADDR (SPBA0_BASE_ADDR + 0x00020000) #define MMC_SDHC4_BASE_ADDR (SPBA0_BASE_ADDR + 0x00024000) @@ -97,7 +97,7 @@ #define IIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x00098000) #define CSU_BASE_ADDR (AIPS2_BASE_ADDR + 0x0009C000) #define ARM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A0000) -#define OWIRE_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A4000) +#define OWIRE_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A4000) #define FIRI_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A8000) #define CSPI2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AC000) #define SDMA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B0000) diff --git a/arch/arm/include/asm/arch-mx6/mx6_plugin.S b/arch/arm/include/asm/arch-mx6/mx6_plugin.S index 7e61d22..4d12c68 100644 --- a/arch/arm/include/asm/arch-mx6/mx6_plugin.S +++ b/arch/arm/include/asm/arch-mx6/mx6_plugin.S @@ -7,10 +7,10 @@ #ifdef CONFIG_ROM_UNIFIED_SECTIONS #define ROM_API_TABLE_BASE_ADDR_LEGACY 0x180 -#define ROM_VERSION_OFFSET 0x80 +#define ROM_VERSION_OFFSET 0x80 #else #define ROM_API_TABLE_BASE_ADDR_LEGACY 0xC0 -#define ROM_VERSION_OFFSET 0x48 +#define ROM_VERSION_OFFSET 0x48 #endif #define ROM_API_TABLE_BASE_ADDR_MX6DQ_TO15 0xC4 #define ROM_API_TABLE_BASE_ADDR_MX6DL_TO12 0xC4 diff --git a/arch/arm/include/asm/arch-mx7/mx7_plugin.S b/arch/arm/include/asm/arch-mx7/mx7_plugin.S index c7a84e8..b552542 100644 --- a/arch/arm/include/asm/arch-mx7/mx7_plugin.S +++ b/arch/arm/include/asm/arch-mx7/mx7_plugin.S @@ -6,7 +6,7 @@ #include <config.h> #define ROM_API_TABLE_BASE_ADDR_LEGACY 0x180 -#define ROM_VERSION_OFFSET 0x80 +#define ROM_VERSION_OFFSET 0x80 #define ROM_API_HWCNFG_SETUP_OFFSET 0x08 plugin_start: diff --git a/arch/arm/include/asm/arch-mx7ulp/mx7ulp_plugin.S b/arch/arm/include/asm/arch-mx7ulp/mx7ulp_plugin.S index bcc804b..5089b1d 100644 --- a/arch/arm/include/asm/arch-mx7ulp/mx7ulp_plugin.S +++ b/arch/arm/include/asm/arch-mx7ulp/mx7ulp_plugin.S @@ -6,7 +6,7 @@ #include <config.h> #define ROM_API_TABLE_BASE_ADDR_LEGACY 0x180 -#define ROM_VERSION_OFFSET 0x80 +#define ROM_VERSION_OFFSET 0x80 #define ROM_API_HWCNFG_SETUP_OFFSET 0x08 plugin_start: diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3368.h b/arch/arm/include/asm/arch-rockchip/cru_rk3368.h index 316c67c..ed2a612 100644 --- a/arch/arm/include/asm/arch-rockchip/cru_rk3368.h +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3368.h @@ -126,17 +126,17 @@ enum { /* GLB_RST_CON */ PMU_GLB_SRST_CTRL_SHIFT = 2, PMU_GLB_SRST_CTRL_MASK = GENMASK(3, 2), - PMU_RST_BY_FST_GLB_SRST = 0, - PMU_RST_BY_SND_GLB_SRST = 1, + PMU_RST_BY_FST_GLB_SRST = 0, + PMU_RST_BY_SND_GLB_SRST = 1, PMU_RST_DISABLE = 2, WDT_GLB_SRST_CTRL_SHIFT = 1, WDT_GLB_SRST_CTRL_MASK = BIT(1), - WDT_TRIGGER_SND_GLB_SRST = 0, - WDT_TRIGGER_FST_GLB_SRST = 1, - TSADC_GLB_SRST_CTRL_SHIFT = 0, - TSADC_GLB_SRST_CTRL_MASK = BIT(0), - TSADC_TRIGGER_SND_GLB_SRST = 0, - TSADC_TRIGGER_FST_GLB_SRST = 1, + WDT_TRIGGER_SND_GLB_SRST = 0, + WDT_TRIGGER_FST_GLB_SRST = 1, + TSADC_GLB_SRST_CTRL_SHIFT = 0, + TSADC_GLB_SRST_CTRL_MASK = BIT(0), + TSADC_TRIGGER_SND_GLB_SRST = 0, + TSADC_TRIGGER_FST_GLB_SRST = 1, }; #endif diff --git a/arch/arm/include/asm/arch-vf610/iomux-vf610.h b/arch/arm/include/asm/arch-vf610/iomux-vf610.h index 8ba03e5..94ab059 100644 --- a/arch/arm/include/asm/arch-vf610/iomux-vf610.h +++ b/arch/arm/include/asm/arch-vf610/iomux-vf610.h @@ -163,13 +163,13 @@ enum { VF610_PAD_PTB24__NF_WE_B = IOMUX_PAD(0x0178, 0x0178, 5, __NA_, 0, VF610_NFC_CN_PAD_CTRL), VF610_PAD_PTB25__NF_CE0_B = IOMUX_PAD(0x017c, 0x017c, 5, __NA_, 0, VF610_NFC_CN_PAD_CTRL), - VF610_PAD_PTB27__NF_RE_B = IOMUX_PAD(0x0184, 0x0184, 6, __NA_, 0, VF610_NFC_CN_PAD_CTRL), + VF610_PAD_PTB27__NF_RE_B = IOMUX_PAD(0x0184, 0x0184, 6, __NA_, 0, VF610_NFC_CN_PAD_CTRL), - VF610_PAD_PTC26__NF_RB_B = IOMUX_PAD(0x018C, 0x018C, 5, __NA_, 0, VF610_NFC_RB_PAD_CTRL), + VF610_PAD_PTC26__NF_RB_B = IOMUX_PAD(0x018C, 0x018C, 5, __NA_, 0, VF610_NFC_RB_PAD_CTRL), - VF610_PAD_PTC27__NF_ALE = IOMUX_PAD(0x0190, 0x0190, 6, __NA_, 0, VF610_NFC_CN_PAD_CTRL), + VF610_PAD_PTC27__NF_ALE = IOMUX_PAD(0x0190, 0x0190, 6, __NA_, 0, VF610_NFC_CN_PAD_CTRL), - VF610_PAD_PTC28__NF_CLE = IOMUX_PAD(0x0194, 0x0194, 6, __NA_, 0, VF610_NFC_CN_PAD_CTRL), + VF610_PAD_PTC28__NF_CLE = IOMUX_PAD(0x0194, 0x0194, 6, __NA_, 0, VF610_NFC_CN_PAD_CTRL), VF610_PAD_PTE0__DCU0_HSYNC = IOMUX_PAD(0x01a4, 0x01a4, 1, __NA_, 0, VF610_DCU_PAD_CTRL), VF610_PAD_PTE1__DCU0_VSYNC = IOMUX_PAD(0x01a8, 0x01a8, 1, __NA_, 0, VF610_DCU_PAD_CTRL), diff --git a/arch/arm/include/asm/macro.h b/arch/arm/include/asm/macro.h index e1eefc2..ec0171e 100644 --- a/arch/arm/include/asm/macro.h +++ b/arch/arm/include/asm/macro.h @@ -154,7 +154,7 @@ lr .req x30 orr \xreg1, \xreg1, \xreg2 cbz \xreg1, \master_label #else - b \master_label + b \master_label #endif .endm diff --git a/arch/arm/include/asm/ti-common/davinci_nand.h b/arch/arm/include/asm/ti-common/davinci_nand.h index 28842c3..ffaac68 100644 --- a/arch/arm/include/asm/ti-common/davinci_nand.h +++ b/arch/arm/include/asm/ti-common/davinci_nand.h @@ -12,9 +12,9 @@ #include <linux/mtd/rawnand.h> #include <asm/arch/hardware.h> -#define NAND_READ_START 0x00 -#define NAND_READ_END 0x30 -#define NAND_STATUS 0x70 +#define NAND_READ_START 0x00 +#define NAND_READ_END 0x30 +#define NAND_STATUS 0x70 #define MASK_CLE 0x10 #define MASK_ALE 0x08 |