aboutsummaryrefslogtreecommitdiff
path: root/arch/arm/dts
diff options
context:
space:
mode:
Diffstat (limited to 'arch/arm/dts')
-rw-r--r--arch/arm/dts/fsl-ls1028a-qds-1xxx-sch-30842.dtsi2
-rw-r--r--arch/arm/dts/fsl-ls1028a-qds-6xxx-sch-30842.dtsi4
-rw-r--r--arch/arm/dts/fsl-ls1028a-qds-7777-sch-30841.dtsi10
-rw-r--r--arch/arm/dts/fsl-ls1028a-qds-7xx7-sch-30841R.dtsi6
-rw-r--r--arch/arm/dts/fsl-ls1028a-qds-8xxx-sch-24801.dtsi2
-rw-r--r--arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801-LBRW.dtsi2
-rw-r--r--arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801.dtsi2
-rw-r--r--arch/arm/dts/fsl-ls1028a-qds-x3xx-sch-30841-LBRW.dtsi2
-rw-r--r--arch/arm/dts/fsl-ls1028a-qds-x5xx-sch-28021-LBRW.dtsi2
-rw-r--r--arch/arm/dts/fsl-ls1028a-qds-x7xx-sch-30842.dtsi4
-rw-r--r--arch/arm/dts/fsl-ls1028a-qds-xx7x-sch-30842.dtsi4
-rw-r--r--arch/arm/dts/fsl-ls1088a-qds-sd1-21.dtsi4
-rw-r--r--arch/arm/dts/fsl-ls1088a-qds-sd1-29.dtsi4
-rw-r--r--arch/arm/dts/fsl-ls2080a-qds-sd1-42.dtsi16
-rw-r--r--arch/arm/dts/fsl-ls2088a-rdb-qspi.dts16
-rw-r--r--arch/arm/dts/fsl-sch-24801.dtsi2
-rw-r--r--arch/arm/dts/fsl-sch-28021.dtsi2
-rw-r--r--arch/arm/dts/fsl-sch-30841.dtsi4
-rw-r--r--arch/arm/dts/fsl-sch-30842.dtsi4
-rw-r--r--arch/arm/dts/ls1021a-tsn.dts2
20 files changed, 47 insertions, 47 deletions
diff --git a/arch/arm/dts/fsl-ls1028a-qds-1xxx-sch-30842.dtsi b/arch/arm/dts/fsl-ls1028a-qds-1xxx-sch-30842.dtsi
index 23816da..4063d9a 100644
--- a/arch/arm/dts/fsl-ls1028a-qds-1xxx-sch-30842.dtsi
+++ b/arch/arm/dts/fsl-ls1028a-qds-1xxx-sch-30842.dtsi
@@ -2,7 +2,7 @@
/*
* NXP LS1028A-QDS device tree fragment for RCW 1xxx
*
- * Copyright 2019-2021 NXP Semiconductors
+ * Copyright 2019-2021 NXP
*/
/*
diff --git a/arch/arm/dts/fsl-ls1028a-qds-6xxx-sch-30842.dtsi b/arch/arm/dts/fsl-ls1028a-qds-6xxx-sch-30842.dtsi
index c6558ae..548ab2b 100644
--- a/arch/arm/dts/fsl-ls1028a-qds-6xxx-sch-30842.dtsi
+++ b/arch/arm/dts/fsl-ls1028a-qds-6xxx-sch-30842.dtsi
@@ -2,7 +2,7 @@
/*
* NXP LS1028A-QDS device tree fragment for RCW 6xxx
*
- * Copyright 2019-2021 NXP Semiconductors
+ * Copyright 2019-2021 NXP
*/
/*
@@ -14,6 +14,6 @@
&enetc0 {
status = "okay";
- phy-mode = "sgmii-2500";
+ phy-mode = "2500base-x";
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@02}>;
};
diff --git a/arch/arm/dts/fsl-ls1028a-qds-7777-sch-30841.dtsi b/arch/arm/dts/fsl-ls1028a-qds-7777-sch-30841.dtsi
index 5a0f060..3991fb7 100644
--- a/arch/arm/dts/fsl-ls1028a-qds-7777-sch-30841.dtsi
+++ b/arch/arm/dts/fsl-ls1028a-qds-7777-sch-30841.dtsi
@@ -2,7 +2,7 @@
/*
* NXP LS1028A-QDS device tree fragment for RCW 7777
*
- * Copyright 2019-2021 NXP Semiconductors
+ * Copyright 2019-2021 NXP
*/
/*
@@ -30,25 +30,25 @@
&mscc_felix_port0 {
status = "okay";
- phy-mode = "sgmii-2500";
+ phy-mode = "2500base-x";
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@00}>;
};
&mscc_felix_port1 {
status = "okay";
- phy-mode = "sgmii-2500";
+ phy-mode = "2500base-x";
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@01}>;
};
&mscc_felix_port2 {
status = "okay";
- phy-mode = "sgmii-2500";
+ phy-mode = "2500base-x";
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@02}>;
};
&mscc_felix_port3 {
status = "okay";
- phy-mode = "sgmii-2500";
+ phy-mode = "2500base-x";
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@03}>;
};
diff --git a/arch/arm/dts/fsl-ls1028a-qds-7xx7-sch-30841R.dtsi b/arch/arm/dts/fsl-ls1028a-qds-7xx7-sch-30841R.dtsi
index 39a83e1..d68c8c2 100644
--- a/arch/arm/dts/fsl-ls1028a-qds-7xx7-sch-30841R.dtsi
+++ b/arch/arm/dts/fsl-ls1028a-qds-7xx7-sch-30841R.dtsi
@@ -2,7 +2,7 @@
/*
* NXP LS1028A-QDS device tree fragment for RCW 7xx7
*
- * Copyright 2019-2021 NXP Semiconductors
+ * Copyright 2019-2021 NXP
*/
&slot1 {
@@ -19,13 +19,13 @@
&mscc_felix_port0 {
status = "okay";
- phy-mode = "sgmii-2500";
+ phy-mode = "2500base-x";
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@02}>;
};
&mscc_felix_port3 {
status = "okay";
- phy-mode = "sgmii-2500";
+ phy-mode = "2500base-x";
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@03}>;
};
diff --git a/arch/arm/dts/fsl-ls1028a-qds-8xxx-sch-24801.dtsi b/arch/arm/dts/fsl-ls1028a-qds-8xxx-sch-24801.dtsi
index 7d4702e..94b5081 100644
--- a/arch/arm/dts/fsl-ls1028a-qds-8xxx-sch-24801.dtsi
+++ b/arch/arm/dts/fsl-ls1028a-qds-8xxx-sch-24801.dtsi
@@ -2,7 +2,7 @@
/*
* NXP LS1028A-QDS device tree fragment for RCW 8xxx
*
- * Copyright 2019-2021 NXP Semiconductors
+ * Copyright 2019-2021 NXP
*/
/*
diff --git a/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801-LBRW.dtsi b/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801-LBRW.dtsi
index 021fe3f..3b85026 100644
--- a/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801-LBRW.dtsi
+++ b/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801-LBRW.dtsi
@@ -2,7 +2,7 @@
/*
* NXP LS1028A-QDS device tree fragment for RCW 9999
*
- * Copyright 2019-2021 NXP Semiconductors
+ * Copyright 2019-2021 NXP
*/
/*
diff --git a/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801.dtsi b/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801.dtsi
index b6704d8..eb63214 100644
--- a/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801.dtsi
+++ b/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801.dtsi
@@ -2,7 +2,7 @@
/*
* NXP LS1028A-QDS device tree fragment for RCW 9999
*
- * Copyright 2019-2021 NXP Semiconductors
+ * Copyright 2019-2021 NXP
*
*/
diff --git a/arch/arm/dts/fsl-ls1028a-qds-x3xx-sch-30841-LBRW.dtsi b/arch/arm/dts/fsl-ls1028a-qds-x3xx-sch-30841-LBRW.dtsi
index 8c10897..ed86da6 100644
--- a/arch/arm/dts/fsl-ls1028a-qds-x3xx-sch-30841-LBRW.dtsi
+++ b/arch/arm/dts/fsl-ls1028a-qds-x3xx-sch-30841-LBRW.dtsi
@@ -2,7 +2,7 @@
/*
* NXP LS1028A-QDS device tree fragment for RCW x3xx
*
- * Copyright 2019-2021 NXP Semiconductors
+ * Copyright 2019-2021 NXP
*/
/*
diff --git a/arch/arm/dts/fsl-ls1028a-qds-x5xx-sch-28021-LBRW.dtsi b/arch/arm/dts/fsl-ls1028a-qds-x5xx-sch-28021-LBRW.dtsi
index 1d800da..c9de4ec 100644
--- a/arch/arm/dts/fsl-ls1028a-qds-x5xx-sch-28021-LBRW.dtsi
+++ b/arch/arm/dts/fsl-ls1028a-qds-x5xx-sch-28021-LBRW.dtsi
@@ -2,7 +2,7 @@
/*
* NXP LS1028A-QDS device tree fragment for RCW x5xx
*
- * Copyright 2019-2021 NXP Semiconductors
+ * Copyright 2019-2021 NXP
*/
/*
diff --git a/arch/arm/dts/fsl-ls1028a-qds-x7xx-sch-30842.dtsi b/arch/arm/dts/fsl-ls1028a-qds-x7xx-sch-30842.dtsi
index 1fb2cdf..7f78550 100644
--- a/arch/arm/dts/fsl-ls1028a-qds-x7xx-sch-30842.dtsi
+++ b/arch/arm/dts/fsl-ls1028a-qds-x7xx-sch-30842.dtsi
@@ -2,7 +2,7 @@
/*
* NXP LS1028A-QDS device tree fragment for RCW 7777
*
- * Copyright 2019-2021 NXP Semiconductors
+ * Copyright 2019-2021 NXP
*/
&slot2 {
@@ -19,7 +19,7 @@
&mscc_felix_port1 {
status = "okay";
- phy-mode = "sgmii-2500";
+ phy-mode = "2500base-x";
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@02}>;
};
diff --git a/arch/arm/dts/fsl-ls1028a-qds-xx7x-sch-30842.dtsi b/arch/arm/dts/fsl-ls1028a-qds-xx7x-sch-30842.dtsi
index 2333f74..0fbe772 100644
--- a/arch/arm/dts/fsl-ls1028a-qds-xx7x-sch-30842.dtsi
+++ b/arch/arm/dts/fsl-ls1028a-qds-xx7x-sch-30842.dtsi
@@ -2,7 +2,7 @@
/*
* NXP LS1028A-QDS device tree fragment for RCW 7777
*
- * Copyright 2019-2021 NXP Semiconductors
+ * Copyright 2019-2021 NXP
*/
&slot3 {
@@ -19,7 +19,7 @@
&mscc_felix_port2 {
status = "okay";
- phy-mode = "sgmii-2500";
+ phy-mode = "2500base-x";
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@60/phy@02}>;
};
diff --git a/arch/arm/dts/fsl-ls1088a-qds-sd1-21.dtsi b/arch/arm/dts/fsl-ls1088a-qds-sd1-21.dtsi
index e0a6c04..df39cca 100644
--- a/arch/arm/dts/fsl-ls1088a-qds-sd1-21.dtsi
+++ b/arch/arm/dts/fsl-ls1088a-qds-sd1-21.dtsi
@@ -9,12 +9,12 @@
&dpmac1 {
status = "okay";
- phy-connection-type = "xfi";
+ phy-connection-type = "10gbase-r";
};
&dpmac2 {
status = "okay";
- phy-connection-type = "xfi";
+ phy-connection-type = "10gbase-r";
};
&dpmac4 {
diff --git a/arch/arm/dts/fsl-ls1088a-qds-sd1-29.dtsi b/arch/arm/dts/fsl-ls1088a-qds-sd1-29.dtsi
index 65e9530..99f74c2 100644
--- a/arch/arm/dts/fsl-ls1088a-qds-sd1-29.dtsi
+++ b/arch/arm/dts/fsl-ls1088a-qds-sd1-29.dtsi
@@ -9,10 +9,10 @@
&dpmac1 {
status = "okay";
- phy-connection-type = "xfi";
+ phy-connection-type = "10gbase-r";
};
&dpmac2 {
status = "okay";
- phy-connection-type = "xfi";
+ phy-connection-type = "10gbase-r";
};
diff --git a/arch/arm/dts/fsl-ls2080a-qds-sd1-42.dtsi b/arch/arm/dts/fsl-ls2080a-qds-sd1-42.dtsi
index ccbb5de..72297f4 100644
--- a/arch/arm/dts/fsl-ls2080a-qds-sd1-42.dtsi
+++ b/arch/arm/dts/fsl-ls2080a-qds-sd1-42.dtsi
@@ -9,40 +9,40 @@
&dpmac1 {
status = "okay";
- phy-connection-type = "xfi";
+ phy-connection-type = "10gbase-r";
};
&dpmac2 {
status = "okay";
- phy-connection-type = "xfi";
+ phy-connection-type = "10gbase-r";
};
&dpmac3 {
status = "okay";
- phy-connection-type = "xfi";
+ phy-connection-type = "10gbase-r";
};
&dpmac4 {
status = "okay";
- phy-connection-type = "xfi";
+ phy-connection-type = "10gbase-r";
};
&dpmac5 {
status = "okay";
- phy-connection-type = "xfi";
+ phy-connection-type = "10gbase-r";
};
&dpmac6 {
status = "okay";
- phy-connection-type = "xfi";
+ phy-connection-type = "10gbase-r";
};
&dpmac7 {
status = "okay";
- phy-connection-type = "xfi";
+ phy-connection-type = "10gbase-r";
};
&dpmac8 {
status = "okay";
- phy-connection-type = "xfi";
+ phy-connection-type = "10gbase-r";
};
diff --git a/arch/arm/dts/fsl-ls2088a-rdb-qspi.dts b/arch/arm/dts/fsl-ls2088a-rdb-qspi.dts
index 179ed19..9e68c14 100644
--- a/arch/arm/dts/fsl-ls2088a-rdb-qspi.dts
+++ b/arch/arm/dts/fsl-ls2088a-rdb-qspi.dts
@@ -24,49 +24,49 @@
&dpmac1 {
status = "okay";
phy-handle = <&mdio1_phy1>;
- phy-connection-type = "xfi";
+ phy-connection-type = "10gbase-r";
};
&dpmac2 {
status = "okay";
phy-handle = <&mdio1_phy2>;
- phy-connection-type = "xfi";
+ phy-connection-type = "10gbase-r";
};
&dpmac3 {
status = "okay";
phy-handle = <&mdio1_phy3>;
- phy-connection-type = "xfi";
+ phy-connection-type = "10gbase-r";
};
&dpmac4 {
status = "okay";
phy-handle = <&mdio1_phy4>;
- phy-connection-type = "xfi";
+ phy-connection-type = "10gbase-r";
};
&dpmac5 {
status = "okay";
phy-handle = <&mdio2_phy1>;
- phy-connection-type = "xfi";
+ phy-connection-type = "10gbase-r";
};
&dpmac6 {
status = "okay";
phy-handle = <&mdio2_phy2>;
- phy-connection-type = "xfi";
+ phy-connection-type = "10gbase-r";
};
&dpmac7 {
status = "okay";
phy-handle = <&mdio2_phy3>;
- phy-connection-type = "xfi";
+ phy-connection-type = "10gbase-r";
};
&dpmac8 {
status = "okay";
phy-handle = <&mdio2_phy4>;
- phy-connection-type = "xfi";
+ phy-connection-type = "10gbase-r";
};
&emdio1 {
diff --git a/arch/arm/dts/fsl-sch-24801.dtsi b/arch/arm/dts/fsl-sch-24801.dtsi
index 304afda..d1b43aa 100644
--- a/arch/arm/dts/fsl-sch-24801.dtsi
+++ b/arch/arm/dts/fsl-sch-24801.dtsi
@@ -2,7 +2,7 @@
/*
* Device tree fragment for RCW SCH-24801 card
*
- * Copyright 2019-2021 NXP Semiconductors
+ * Copyright 2019-2021 NXP
*/
/*
diff --git a/arch/arm/dts/fsl-sch-28021.dtsi b/arch/arm/dts/fsl-sch-28021.dtsi
index 584f3fa..6124528 100644
--- a/arch/arm/dts/fsl-sch-28021.dtsi
+++ b/arch/arm/dts/fsl-sch-28021.dtsi
@@ -2,7 +2,7 @@
/*
* Device tree fragment for RCW SCH-28021 card
*
- * Copyright 2019-2021 NXP Semiconductors
+ * Copyright 2019-2021 NXP
*/
/*
diff --git a/arch/arm/dts/fsl-sch-30841.dtsi b/arch/arm/dts/fsl-sch-30841.dtsi
index ca437d1..28b1bec 100644
--- a/arch/arm/dts/fsl-sch-30841.dtsi
+++ b/arch/arm/dts/fsl-sch-30841.dtsi
@@ -2,14 +2,14 @@
/*
* Device tree fragment for RCW SCH-30841 card
*
- * Copyright 2019-2021 NXP Semiconductors
+ * Copyright 2019-2021 NXP
*/
/*
* SCH-30841 is a 4 port add-on card used with various FSL QDS boards.
* It integrates a AQR412C quad PHY which supports 4 interfaces either muxed
* together on a single lane or mapped 1:1 to serdes lanes.
- * It supports several protocols - SGMII, SGMII-2500, USXGMII, M-USX, XFI.
+ * It supports several protocols - SGMII, 2500base-X, USXGMII, M-USX, 10GBase-R.
* PHY addresses are 0x00 - 0x03.
* On the card the first port is the bottom port (closest to PEX connector).
*/
diff --git a/arch/arm/dts/fsl-sch-30842.dtsi b/arch/arm/dts/fsl-sch-30842.dtsi
index fa0f2cd..bff9e76 100644
--- a/arch/arm/dts/fsl-sch-30842.dtsi
+++ b/arch/arm/dts/fsl-sch-30842.dtsi
@@ -2,13 +2,13 @@
/*
* Device tree fragment for RCW SCH-30842 card
*
- * Copyright 2019-2021 NXP Semiconductors
+ * Copyright 2019-2021 NXP
*/
/*
* SCH-30842 is a single port add-on card used with various FSL QDS boards.
* It integrates a AQR112 PHY, which supports several protocols - SGMII,
- * SGMII-2500, USXGMII, XFI.
+ * 2500base-x, USXGMII, 10GBase-R.
* PHY address is 0x02.
*/
phy@02 {
diff --git a/arch/arm/dts/ls1021a-tsn.dts b/arch/arm/dts/ls1021a-tsn.dts
index f633074..8e0f4ea 100644
--- a/arch/arm/dts/ls1021a-tsn.dts
+++ b/arch/arm/dts/ls1021a-tsn.dts
@@ -1,5 +1,5 @@
// SPDX-License-Identifier: GPL-2.0
-/* Copyright 2016-2018 NXP Semiconductors
+/* Copyright 2016-2018 NXP
* Copyright 2019 Vladimir Oltean <olteanv@gmail.com>
*/