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-rw-r--r--arch/arm/dts/r8a7795-h3ulcb-u-boot.dts10
-rw-r--r--arch/arm/dts/r8a7795-salvator-x-u-boot.dts10
-rw-r--r--arch/arm/dts/r8a7795-u-boot.dtsi13
-rw-r--r--arch/arm/dts/r8a7795.dtsi5
-rw-r--r--arch/arm/dts/r8a7796-m3ulcb-u-boot.dts10
-rw-r--r--arch/arm/dts/r8a7796-salvator-x-u-boot.dts10
-rw-r--r--arch/arm/dts/r8a7796-u-boot.dtsi13
-rw-r--r--arch/arm/dts/r8a7796.dtsi5
-rw-r--r--arch/arm/dts/r8a77970-eagle-u-boot.dts10
-rw-r--r--arch/arm/dts/r8a77970-u-boot.dtsi13
-rw-r--r--arch/arm/dts/r8a77970.dtsi5
-rw-r--r--arch/arm/dts/r8a77995-draak-u-boot.dts10
-rw-r--r--arch/arm/dts/r8a77995-u-boot.dtsi9
-rw-r--r--arch/arm/dts/r8a77995.dtsi4
-rw-r--r--arch/arm/dts/r8a779x-u-boot.dtsi25
15 files changed, 133 insertions, 19 deletions
diff --git a/arch/arm/dts/r8a7795-h3ulcb-u-boot.dts b/arch/arm/dts/r8a7795-h3ulcb-u-boot.dts
new file mode 100644
index 0000000..56b1721
--- /dev/null
+++ b/arch/arm/dts/r8a7795-h3ulcb-u-boot.dts
@@ -0,0 +1,10 @@
+/*
+ * Device Tree Source extras for U-Boot for the ULCB board
+ *
+ * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include "r8a7795-h3ulcb.dts"
+#include "r8a7795-u-boot.dtsi"
diff --git a/arch/arm/dts/r8a7795-salvator-x-u-boot.dts b/arch/arm/dts/r8a7795-salvator-x-u-boot.dts
new file mode 100644
index 0000000..f2c10ed
--- /dev/null
+++ b/arch/arm/dts/r8a7795-salvator-x-u-boot.dts
@@ -0,0 +1,10 @@
+/*
+ * Device Tree Source extras for U-Boot for the Salvator-X board
+ *
+ * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include "r8a7795-salvator-x.dts"
+#include "r8a7795-u-boot.dtsi"
diff --git a/arch/arm/dts/r8a7795-u-boot.dtsi b/arch/arm/dts/r8a7795-u-boot.dtsi
new file mode 100644
index 0000000..41a6ef4
--- /dev/null
+++ b/arch/arm/dts/r8a7795-u-boot.dtsi
@@ -0,0 +1,13 @@
+/*
+ * Device Tree Source extras for U-Boot on RCar R8A7795 SoC
+ *
+ * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include "r8a779x-u-boot.dtsi"
+
+&extalr_clk {
+ u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/r8a7795.dtsi b/arch/arm/dts/r8a7795.dtsi
index d9f5567..f7dc147 100644
--- a/arch/arm/dts/r8a7795.dtsi
+++ b/arch/arm/dts/r8a7795.dtsi
@@ -129,7 +129,6 @@
#clock-cells = <0>;
/* This value must be overridden by the board */
clock-frequency = <0>;
- u-boot,dm-pre-reloc;
};
extalr_clk: extalr {
@@ -137,7 +136,6 @@
#clock-cells = <0>;
/* This value must be overridden by the board */
clock-frequency = <0>;
- u-boot,dm-pre-reloc;
};
/*
@@ -191,7 +189,6 @@
#address-cells = <2>;
#size-cells = <2>;
ranges;
- u-boot,dm-pre-reloc;
gic: interrupt-controller@f1010000 {
compatible = "arm,gic-400";
@@ -383,7 +380,6 @@
#clock-cells = <2>;
#power-domain-cells = <0>;
#reset-cells = <1>;
- u-boot,dm-pre-reloc;
};
rst: reset-controller@e6160000 {
@@ -394,7 +390,6 @@
prr: chipid@fff00044 {
compatible = "renesas,prr";
reg = <0 0xfff00044 0 4>;
- u-boot,dm-pre-reloc;
};
sysc: system-controller@e6180000 {
diff --git a/arch/arm/dts/r8a7796-m3ulcb-u-boot.dts b/arch/arm/dts/r8a7796-m3ulcb-u-boot.dts
new file mode 100644
index 0000000..a8cb425
--- /dev/null
+++ b/arch/arm/dts/r8a7796-m3ulcb-u-boot.dts
@@ -0,0 +1,10 @@
+/*
+ * Device Tree Source extras for U-Boot for the ULCB board
+ *
+ * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include "r8a7796-m3ulcb.dts"
+#include "r8a7796-u-boot.dtsi"
diff --git a/arch/arm/dts/r8a7796-salvator-x-u-boot.dts b/arch/arm/dts/r8a7796-salvator-x-u-boot.dts
new file mode 100644
index 0000000..1e28d93
--- /dev/null
+++ b/arch/arm/dts/r8a7796-salvator-x-u-boot.dts
@@ -0,0 +1,10 @@
+/*
+ * Device Tree Source extras for U-Boot for the Salvator-X board
+ *
+ * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include "r8a7796-salvator-x.dts"
+#include "r8a7796-u-boot.dtsi"
diff --git a/arch/arm/dts/r8a7796-u-boot.dtsi b/arch/arm/dts/r8a7796-u-boot.dtsi
new file mode 100644
index 0000000..daece95
--- /dev/null
+++ b/arch/arm/dts/r8a7796-u-boot.dtsi
@@ -0,0 +1,13 @@
+/*
+ * Device Tree Source extras for U-Boot on RCar R8A7796 SoC
+ *
+ * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include "r8a779x-u-boot.dtsi"
+
+&extalr_clk {
+ u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/r8a7796.dtsi b/arch/arm/dts/r8a7796.dtsi
index ed758d1..83faabe 100644
--- a/arch/arm/dts/r8a7796.dtsi
+++ b/arch/arm/dts/r8a7796.dtsi
@@ -111,7 +111,6 @@
#clock-cells = <0>;
/* This value must be overridden by the board */
clock-frequency = <0>;
- u-boot,dm-pre-reloc;
};
extalr_clk: extalr {
@@ -119,7 +118,6 @@
#clock-cells = <0>;
/* This value must be overridden by the board */
clock-frequency = <0>;
- u-boot,dm-pre-reloc;
};
/*
@@ -172,7 +170,6 @@
#address-cells = <2>;
#size-cells = <2>;
ranges;
- u-boot,dm-pre-reloc;
gic: interrupt-controller@f1010000 {
compatible = "arm,gic-400";
@@ -366,7 +363,6 @@
#clock-cells = <2>;
#power-domain-cells = <0>;
#reset-cells = <1>;
- u-boot,dm-pre-reloc;
};
rst: reset-controller@e6160000 {
@@ -377,7 +373,6 @@
prr: chipid@fff00044 {
compatible = "renesas,prr";
reg = <0 0xfff00044 0 4>;
- u-boot,dm-pre-reloc;
};
sysc: system-controller@e6180000 {
diff --git a/arch/arm/dts/r8a77970-eagle-u-boot.dts b/arch/arm/dts/r8a77970-eagle-u-boot.dts
new file mode 100644
index 0000000..1c9dd25
--- /dev/null
+++ b/arch/arm/dts/r8a77970-eagle-u-boot.dts
@@ -0,0 +1,10 @@
+/*
+ * Device Tree Source extras for U-Boot for the Eagle board
+ *
+ * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include "r8a77970-eagle.dts"
+#include "r8a77970-u-boot.dtsi"
diff --git a/arch/arm/dts/r8a77970-u-boot.dtsi b/arch/arm/dts/r8a77970-u-boot.dtsi
new file mode 100644
index 0000000..db121a1
--- /dev/null
+++ b/arch/arm/dts/r8a77970-u-boot.dtsi
@@ -0,0 +1,13 @@
+/*
+ * Device Tree Source extras for U-Boot on RCar R8A77970 SoC
+ *
+ * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include "r8a779x-u-boot.dtsi"
+
+&extalr_clk {
+ u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/r8a77970.dtsi b/arch/arm/dts/r8a77970.dtsi
index f022702..78e6f89 100644
--- a/arch/arm/dts/r8a77970.dtsi
+++ b/arch/arm/dts/r8a77970.dtsi
@@ -48,7 +48,6 @@
#clock-cells = <0>;
/* This value must be overridden by the board */
clock-frequency = <0>;
- u-boot,dm-pre-reloc;
};
extalr_clk: extalr {
@@ -56,7 +55,6 @@
#clock-cells = <0>;
/* This value must be overridden by the board */
clock-frequency = <0>;
- u-boot,dm-pre-reloc;
};
/* External SCIF clock - to be overridden by boards that provide it */
@@ -73,7 +71,6 @@
#address-cells = <2>;
#size-cells = <2>;
ranges;
- u-boot,dm-pre-reloc;
gic: interrupt-controller@f1010000 {
compatible = "arm,gic-400";
@@ -112,7 +109,6 @@
#clock-cells = <2>;
#power-domain-cells = <0>;
#reset-cells = <1>;
- u-boot,dm-pre-reloc;
};
rst: reset-controller@e6160000 {
@@ -150,7 +146,6 @@
prr: chipid@fff00044 {
compatible = "renesas,prr";
reg = <0 0xfff00044 0 4>;
- u-boot,dm-pre-reloc;
};
dmac1: dma-controller@e7300000 {
diff --git a/arch/arm/dts/r8a77995-draak-u-boot.dts b/arch/arm/dts/r8a77995-draak-u-boot.dts
new file mode 100644
index 0000000..4f4aa4d
--- /dev/null
+++ b/arch/arm/dts/r8a77995-draak-u-boot.dts
@@ -0,0 +1,10 @@
+/*
+ * Device Tree Source extras for U-Boot for the Draak board
+ *
+ * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include "r8a77995-draak.dts"
+#include "r8a77995-u-boot.dtsi"
diff --git a/arch/arm/dts/r8a77995-u-boot.dtsi b/arch/arm/dts/r8a77995-u-boot.dtsi
new file mode 100644
index 0000000..6a944dd
--- /dev/null
+++ b/arch/arm/dts/r8a77995-u-boot.dtsi
@@ -0,0 +1,9 @@
+/*
+ * Device Tree Source extras for U-Boot on RCar R8A77995 SoC
+ *
+ * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include "r8a779x-u-boot.dtsi"
diff --git a/arch/arm/dts/r8a77995.dtsi b/arch/arm/dts/r8a77995.dtsi
index ae164a0..d1a03cf 100644
--- a/arch/arm/dts/r8a77995.dtsi
+++ b/arch/arm/dts/r8a77995.dtsi
@@ -47,7 +47,6 @@
#clock-cells = <0>;
/* This value must be overridden by the board */
clock-frequency = <0>;
- u-boot,dm-pre-reloc;
};
scif_clk: scif {
@@ -62,7 +61,6 @@
#address-cells = <2>;
#size-cells = <2>;
ranges;
- u-boot,dm-pre-reloc;
gic: interrupt-controller@f1010000 {
compatible = "arm,gic-400";
@@ -116,7 +114,6 @@
#clock-cells = <2>;
#power-domain-cells = <0>;
#reset-cells = <1>;
- u-boot,dm-pre-reloc;
};
rst: reset-controller@e6160000 {
@@ -132,7 +129,6 @@
prr: chipid@fff00044 {
compatible = "renesas,prr";
reg = <0 0xfff00044 0 4>;
- u-boot,dm-pre-reloc;
};
sysc: system-controller@e6180000 {
diff --git a/arch/arm/dts/r8a779x-u-boot.dtsi b/arch/arm/dts/r8a779x-u-boot.dtsi
new file mode 100644
index 0000000..0baac1d
--- /dev/null
+++ b/arch/arm/dts/r8a779x-u-boot.dtsi
@@ -0,0 +1,25 @@
+/*
+ * Device Tree Source extras for U-Boot on RCar Gen3
+ *
+ * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+/ {
+ soc {
+ u-boot,dm-pre-reloc;
+ };
+};
+
+&cpg {
+ u-boot,dm-pre-reloc;
+};
+
+&extal_clk {
+ u-boot,dm-pre-reloc;
+};
+
+&prr {
+ u-boot,dm-pre-reloc;
+};
generated by cgit v1.1 at 2024-07-14 14:25:24 +0000