aboutsummaryrefslogtreecommitdiff
path: root/arch/arm/cpu/armv7/am33xx/board.c
diff options
context:
space:
mode:
Diffstat (limited to 'arch/arm/cpu/armv7/am33xx/board.c')
-rw-r--r--arch/arm/cpu/armv7/am33xx/board.c66
1 files changed, 66 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c
new file mode 100644
index 0000000..2d6d359
--- /dev/null
+++ b/arch/arm/cpu/armv7/am33xx/board.c
@@ -0,0 +1,66 @@
+/*
+ * board.c
+ *
+ * Common board functions for AM33XX based boards
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/clock.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
+struct timer_reg *timerreg = (struct timer_reg *)DM_TIMER2_BASE;
+
+/*
+ * early system init of muxing and clocks.
+ */
+void s_init(u32 in_ddr)
+{
+ /* WDT1 is already running when the bootloader gets control
+ * Disable it to avoid "random" resets
+ */
+ writel(0xAAAA, &wdtimer->wdtwspr);
+ while (readl(&wdtimer->wdtwwps) != 0x0)
+ ;
+ writel(0x5555, &wdtimer->wdtwspr);
+ while (readl(&wdtimer->wdtwwps) != 0x0)
+ ;
+
+ /* Setup the PLLs and the clocks for the peripherals */
+#ifdef CONFIG_SETUP_PLL
+ pll_init();
+#endif
+ if (!in_ddr)
+ config_ddr();
+}
+
+/* Initialize timer */
+void init_timer(void)
+{
+ /* Reset the Timer */
+ writel(0x2, (&timerreg->tsicrreg));
+
+ /* Wait until the reset is done */
+ while (readl(&timerreg->tiocpcfgreg) & 1)
+ ;
+
+ /* Start the Timer */
+ writel(0x1, (&timerreg->tclrreg));
+}