diff options
Diffstat (limited to 'README')
| -rw-r--r-- | README | 180 |
1 files changed, 1 insertions, 179 deletions
@@ -300,7 +300,6 @@ board_init_r(): - loads U-Boot or (in falcon mode) Linux - Configuration Options: ---------------------- @@ -465,10 +464,6 @@ The following options need to be configured: Board config to use DDR3L. It can be enabled for SoCs with DDR3L controllers. - CONFIG_SYS_FSL_DDR4 - Board config to use DDR4. It can be enabled for SoCs with - DDR4 controllers. - CONFIG_SYS_FSL_IFC_BE Defines the IFC controller register space as Big Endian @@ -481,15 +476,6 @@ The following options need to be configured: CONFIG_SYS_FSL_LBC_CLK_DIV Defines divider of platform clock(clock input to eLBC controller). - CONFIG_SYS_FSL_PBL_PBI - It enables addition of RCW (Power on reset configuration) in built image. - Please refer doc/README.pblimage for more details - - CONFIG_SYS_FSL_PBL_RCW - It adds PBI(pre-boot instructions) commands in u-boot build image. - PBI commands can be used to configure SoC before it starts the execution. - Please refer doc/README.pblimage for more details - CONFIG_SYS_FSL_DDR_BE Defines the DDR controller register space as Big Endian @@ -599,16 +585,6 @@ The following options need to be configured: crash. This is needed for buggy hardware (uc101) where no pull down resistor is connected to the signal IDE5V_DD7. - CONFIG_MACH_TYPE [relevant for ARM only][mandatory] - - This setting is mandatory for all boards that have only one - machine type and must be used to specify the machine type - number as it appears in the ARM machine registry - (see https://www.arm.linux.org.uk/developer/machines/). - Only boards that have multiple machine types supported - in a single configuration file and the machine type is - runtime discoverable, do not have to use this setting. - - vxWorks boot parameters: bootvx constructs a valid bootline using the following @@ -671,11 +647,6 @@ The following options need to be configured: time on others. This setting #define's the initial value of the "loads_echo" environment variable. -- Kgdb Serial Baudrate: (if CONFIG_CMD_KGDB is defined) - CONFIG_KGDB_BAUDRATE - Select one of the baudrates listed in - CONFIG_SYS_BAUDRATE_TABLE, see below. - - Removal of commands If no commands are needed to boot, you can disable CONFIG_CMDLINE to remove them. In this case, the command line @@ -879,17 +850,6 @@ The following options need to be configured: Support for National dp8382[01] gigabit chips. - NETWORK Support (other): - - CONFIG_DRIVER_AT91EMAC - Support for AT91RM9200 EMAC. - - CONFIG_RMII - Define this to use reduced MII inteface - - CONFIG_DRIVER_AT91EMAC_QUIET - If this defined, the driver is quiet. - The driver doen't show link status messages. - CONFIG_CALXEDA_XGMAC Support for the Calxeda XGMAC device @@ -1461,129 +1421,7 @@ The following options need to be configured: In such cases CONFIG_GPIO_LED_INVERTED_TABLE may be defined with a list of GPIO LEDs that have inverted polarity. -- I2C Support: CONFIG_SYS_I2C_LEGACY - - Note: This is deprecated in favour of driver model. Use - CONFIG_DM_I2C instead. - - This enable the legacy i2c subsystem, and will allow you to use - i2c commands at the u-boot command line (as long as you set - CONFIG_SYS_I2C_SOFT_SPEED and CONFIG_SYS_I2C_SOFT_SLAVE - for defining speed and slave address - - activate second bus with I2C_SOFT_DECLARATIONS2 define - CONFIG_SYS_I2C_SOFT_SPEED_2 and CONFIG_SYS_I2C_SOFT_SLAVE_2 - for defining speed and slave address - - activate third bus with I2C_SOFT_DECLARATIONS3 define - CONFIG_SYS_I2C_SOFT_SPEED_3 and CONFIG_SYS_I2C_SOFT_SLAVE_3 - for defining speed and slave address - - activate fourth bus with I2C_SOFT_DECLARATIONS4 define - CONFIG_SYS_I2C_SOFT_SPEED_4 and CONFIG_SYS_I2C_SOFT_SLAVE_4 - for defining speed and slave address - - - drivers/i2c/fsl_i2c.c: - - activate i2c driver with CONFIG_SYS_I2C_FSL - define CONFIG_SYS_FSL_I2C_OFFSET for setting the register - offset CONFIG_SYS_FSL_I2C_SPEED for the i2c speed and - CONFIG_SYS_FSL_I2C_SLAVE for the slave addr of the first - bus. - - If your board supports a second fsl i2c bus, define - CONFIG_SYS_FSL_I2C2_OFFSET for the register offset - CONFIG_SYS_FSL_I2C2_SPEED for the speed and - CONFIG_SYS_FSL_I2C2_SLAVE for the slave address of the - second bus. - - - drivers/i2c/tegra_i2c.c: - - activate this driver with CONFIG_SYS_I2C_TEGRA - - This driver adds 4 i2c buses with a fix speed from - 100000 and the slave addr 0! - - - drivers/i2c/ppc4xx_i2c.c - - activate this driver with CONFIG_SYS_I2C_PPC4XX - - CONFIG_SYS_I2C_PPC4XX_CH0 activate hardware channel 0 - - CONFIG_SYS_I2C_PPC4XX_CH1 activate hardware channel 1 - - - drivers/i2c/i2c_mxc.c - - activate this driver with CONFIG_SYS_I2C_MXC - - enable bus 1 with CONFIG_SYS_I2C_MXC_I2C1 - - enable bus 2 with CONFIG_SYS_I2C_MXC_I2C2 - - enable bus 3 with CONFIG_SYS_I2C_MXC_I2C3 - - enable bus 4 with CONFIG_SYS_I2C_MXC_I2C4 - - define speed for bus 1 with CONFIG_SYS_MXC_I2C1_SPEED - - define slave for bus 1 with CONFIG_SYS_MXC_I2C1_SLAVE - - define speed for bus 2 with CONFIG_SYS_MXC_I2C2_SPEED - - define slave for bus 2 with CONFIG_SYS_MXC_I2C2_SLAVE - - define speed for bus 3 with CONFIG_SYS_MXC_I2C3_SPEED - - define slave for bus 3 with CONFIG_SYS_MXC_I2C3_SLAVE - - define speed for bus 4 with CONFIG_SYS_MXC_I2C4_SPEED - - define slave for bus 4 with CONFIG_SYS_MXC_I2C4_SLAVE - If those defines are not set, default value is 100000 - for speed, and 0 for slave. - - - drivers/i2c/rcar_i2c.c: - - activate this driver with CONFIG_SYS_I2C_RCAR - - This driver adds 4 i2c buses - - - drivers/i2c/sh_i2c.c: - - activate this driver with CONFIG_SYS_I2C_SH - - This driver adds from 2 to 5 i2c buses - - - CONFIG_SYS_I2C_SH_BASE0 for setting the register channel 0 - - CONFIG_SYS_I2C_SH_SPEED0 for for the speed channel 0 - - CONFIG_SYS_I2C_SH_BASE1 for setting the register channel 1 - - CONFIG_SYS_I2C_SH_SPEED1 for for the speed channel 1 - - CONFIG_SYS_I2C_SH_BASE2 for setting the register channel 2 - - CONFIG_SYS_I2C_SH_SPEED2 for for the speed channel 2 - - CONFIG_SYS_I2C_SH_BASE3 for setting the register channel 3 - - CONFIG_SYS_I2C_SH_SPEED3 for for the speed channel 3 - - CONFIG_SYS_I2C_SH_BASE4 for setting the register channel 4 - - CONFIG_SYS_I2C_SH_SPEED4 for for the speed channel 4 - - CONFIG_SYS_I2C_SH_NUM_CONTROLLERS for number of i2c buses - - - drivers/i2c/omap24xx_i2c.c - - activate this driver with CONFIG_SYS_I2C_OMAP24XX - - CONFIG_SYS_OMAP24_I2C_SPEED speed channel 0 - - CONFIG_SYS_OMAP24_I2C_SLAVE slave addr channel 0 - - CONFIG_SYS_OMAP24_I2C_SPEED1 speed channel 1 - - CONFIG_SYS_OMAP24_I2C_SLAVE1 slave addr channel 1 - - CONFIG_SYS_OMAP24_I2C_SPEED2 speed channel 2 - - CONFIG_SYS_OMAP24_I2C_SLAVE2 slave addr channel 2 - - CONFIG_SYS_OMAP24_I2C_SPEED3 speed channel 3 - - CONFIG_SYS_OMAP24_I2C_SLAVE3 slave addr channel 3 - - CONFIG_SYS_OMAP24_I2C_SPEED4 speed channel 4 - - CONFIG_SYS_OMAP24_I2C_SLAVE4 slave addr channel 4 - - - drivers/i2c/s3c24x0_i2c.c: - - activate this driver with CONFIG_SYS_I2C_S3C24X0 - - This driver adds i2c buses (11 for Exynos5250, Exynos5420 - 9 i2c buses for Exynos4 and 1 for S3C24X0 SoCs from Samsung) - with a fix speed from 100000 and the slave addr 0! - - - drivers/i2c/ihs_i2c.c - - activate this driver with CONFIG_SYS_I2C_IHS - - CONFIG_SYS_I2C_IHS_CH0 activate hardware channel 0 - - CONFIG_SYS_I2C_IHS_SPEED_0 speed channel 0 - - CONFIG_SYS_I2C_IHS_SLAVE_0 slave addr channel 0 - - CONFIG_SYS_I2C_IHS_CH1 activate hardware channel 1 - - CONFIG_SYS_I2C_IHS_SPEED_1 speed channel 1 - - CONFIG_SYS_I2C_IHS_SLAVE_1 slave addr channel 1 - - CONFIG_SYS_I2C_IHS_CH2 activate hardware channel 2 - - CONFIG_SYS_I2C_IHS_SPEED_2 speed channel 2 - - CONFIG_SYS_I2C_IHS_SLAVE_2 slave addr channel 2 - - CONFIG_SYS_I2C_IHS_CH3 activate hardware channel 3 - - CONFIG_SYS_I2C_IHS_SPEED_3 speed channel 3 - - CONFIG_SYS_I2C_IHS_SLAVE_3 slave addr channel 3 - - activate dual channel with CONFIG_SYS_I2C_IHS_DUAL - - CONFIG_SYS_I2C_IHS_SPEED_0_1 speed channel 0_1 - - CONFIG_SYS_I2C_IHS_SLAVE_0_1 slave addr channel 0_1 - - CONFIG_SYS_I2C_IHS_SPEED_1_1 speed channel 1_1 - - CONFIG_SYS_I2C_IHS_SLAVE_1_1 slave addr channel 1_1 - - CONFIG_SYS_I2C_IHS_SPEED_2_1 speed channel 2_1 - - CONFIG_SYS_I2C_IHS_SLAVE_2_1 slave addr channel 2_1 - - CONFIG_SYS_I2C_IHS_SPEED_3_1 speed channel 3_1 - - CONFIG_SYS_I2C_IHS_SLAVE_3_1 slave addr channel 3_1 - - additional defines: - +- I2C Support: CONFIG_SYS_NUM_I2C_BUSES Hold the number of i2c buses you want to use. @@ -2873,22 +2711,6 @@ Low Level (hardware related) configuration options: This only takes effect if the memory commands are activated globally (CONFIG_CMD_MEMORY). -- CONFIG_SKIP_LOWLEVEL_INIT - [ARM, NDS32, MIPS, RISC-V only] If this variable is defined, then certain - low level initializations (like setting up the memory - controller) are omitted and/or U-Boot does not - relocate itself into RAM. - - Normally this variable MUST NOT be defined. The only - exception is when U-Boot is loaded (to RAM) by some - other boot loader or by a debugger which performs - these initializations itself. - -- CONFIG_SKIP_LOWLEVEL_INIT_ONLY - [ARM926EJ-S only] This allows just the call to lowlevel_init() - to be skipped. The normal CP15 init (such as enabling the - instruction cache) is still performed. - - CONFIG_SPL_BUILD Set when the currently-running compilation is for an artifact that will end up in the SPL (as opposed to the TPL or U-Boot |