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Diffstat (limited to 'Bindings/clock/mobileye,eyeq5-clk.yaml')
-rw-r--r-- | Bindings/clock/mobileye,eyeq5-clk.yaml | 51 |
1 files changed, 51 insertions, 0 deletions
diff --git a/Bindings/clock/mobileye,eyeq5-clk.yaml b/Bindings/clock/mobileye,eyeq5-clk.yaml new file mode 100644 index 0000000..2d4f2cd --- /dev/null +++ b/Bindings/clock/mobileye,eyeq5-clk.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/mobileye,eyeq5-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mobileye EyeQ5 clock controller + +description: + The EyeQ5 clock controller handles 10 read-only PLLs derived from the main + crystal clock. It also exposes one divider clock, a child of one of the PLLs. + Its registers live in a shared region called OLB. + +maintainers: + - Grégory Clement <gregory.clement@bootlin.com> + - Théo Lebrun <theo.lebrun@bootlin.com> + - Vladimir Kondratiev <vladimir.kondratiev@mobileye.com> + +properties: + compatible: + const: mobileye,eyeq5-clk + + reg: + maxItems: 2 + + reg-names: + items: + - const: plls + - const: ospi + + "#clock-cells": + const: 1 + + clocks: + maxItems: 1 + description: + Input parent clock to all PLLs. Expected to be the main crystal. + + clock-names: + items: + - const: ref + +required: + - compatible + - reg + - reg-names + - "#clock-cells" + - clocks + - clock-names + +additionalProperties: false |