diff options
| -rw-r--r-- | arch/mips/Kconfig | 2 | ||||
| -rw-r--r-- | arch/mips/mach-mtmips/cpu.c | 15 |
2 files changed, 1 insertions, 16 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 9cf8e98..5cb9bdf 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -84,13 +84,13 @@ config ARCH_MTMIPS select DM_SERIAL imply DM_SPI imply DM_SPI_FLASH - select ARCH_MISC_INIT select MIPS_TUNE_24KC select OF_CONTROL select ROM_EXCEPTION_VECTORS select SUPPORTS_CPU_MIPS32_R1 select SUPPORTS_CPU_MIPS32_R2 select SUPPORTS_LITTLE_ENDIAN + select SYS_MALLOC_CLEAR_ON_INIT select SYSRESET config ARCH_JZ47XX diff --git a/arch/mips/mach-mtmips/cpu.c b/arch/mips/mach-mtmips/cpu.c index fcd0484..b0a6397 100644 --- a/arch/mips/mach-mtmips/cpu.c +++ b/arch/mips/mach-mtmips/cpu.c @@ -68,18 +68,3 @@ int print_cpuinfo(void) return 0; } - -int arch_misc_init(void) -{ - /* - * It has been noticed, that sometimes the d-cache is not in a - * "clean-state" when U-Boot is running on MT7688. This was - * detected when using the ethernet driver (which uses d-cache) - * and a TFTP command does not complete. Flushing the complete - * d-cache (again?) here seems to fix this issue. - */ - flush_dcache_range(gd->bd->bi_memstart, - gd->bd->bi_memstart + gd->ram_size - 1); - - return 0; -} |