diff options
79 files changed, 948 insertions, 5829 deletions
diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig index 9f0fb36..199335c 100644 --- a/arch/arm/cpu/armv8/Kconfig +++ b/arch/arm/cpu/armv8/Kconfig @@ -191,6 +191,14 @@ config ARMV8_EA_EL3_FIRST Exception handling at all exception levels for External Abort and SError interrupt exception are taken in EL3. +config ARMV8_UDELAY_EVENT_STREAM + bool "Use the event stream for udelay" + default y if ARCH_VEXPRESS64 + help + Use the event stream provided by the AArch64 architectural timer for + delays. This is more efficient than the default polling + implementation. + menuconfig ARMV8_CRYPTO bool "ARM64 Accelerated Cryptographic Algorithms" diff --git a/arch/arm/cpu/armv8/generic_timer.c b/arch/arm/cpu/armv8/generic_timer.c index e4aa5a4..1de7ec5 100644 --- a/arch/arm/cpu/armv8/generic_timer.c +++ b/arch/arm/cpu/armv8/generic_timer.c @@ -114,3 +114,30 @@ ulong timer_get_boot_us(void) return val / get_tbclk(); } + +#if CONFIG_IS_ENABLED(ARMV8_UDELAY_EVENT_STREAM) +void __udelay(unsigned long usec) +{ + u64 target = get_ticks() + usec_to_tick(usec); + + /* At EL2 or above, use the event stream to avoid polling CNTPCT_EL0 so often */ + if (current_el() >= 2) { + u32 cnthctl_val; + const u8 event_period = 0x7; + + asm volatile("mrs %0, cnthctl_el2" : "=r" (cnthctl_val)); + asm volatile("msr cnthctl_el2, %0" : : "r" + (cnthctl_val | CNTHCTL_EL2_EVNT_EN | CNTHCTL_EL2_EVNT_I(event_period))); + + while (get_ticks() + (1ULL << event_period) <= target) + wfe(); + + /* Reset the event stream */ + asm volatile("msr cnthctl_el2, %0" : : "r" (cnthctl_val)); + } + + /* Fall back to polling CNTPCT_EL0 */ + while (get_ticks() <= target) + ; +} +#endif diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index c9f1b25..60660f2 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1331,9 +1331,7 @@ dtb-$(CONFIG_SOC_K3_J721E) += k3-j721e-common-proc-board.dtb \ k3-j721e-beagleboneai64.dtb \ k3-j721e-r5-beagleboneai64.dtb -dtb-$(CONFIG_SOC_K3_J721S2) += k3-am68-sk-base-board.dtb\ - k3-am68-sk-r5-base-board.dtb\ - k3-j721s2-common-proc-board.dtb\ +dtb-$(CONFIG_SOC_K3_J721S2) += k3-am68-sk-r5-base-board.dtb\ k3-j721s2-r5-common-proc-board.dtb dtb-$(CONFIG_SOC_K3_J784S4) += k3-am69-r5-sk.dtb \ diff --git a/arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi b/arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi index 54a7702..9ac4a82 100644 --- a/arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi +++ b/arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi @@ -54,6 +54,15 @@ >; }; +&usbss0 { + bootph-all; +}; + +&usb0 { + dr_mode = "peripheral"; + bootph-all; +}; + #ifdef CONFIG_TARGET_AM625_A53_BEAGLEPLAY #define SPL_NODTB "spl/u-boot-spl-nodtb.bin" diff --git a/arch/arm/dts/k3-am625-sk-u-boot.dtsi b/arch/arm/dts/k3-am625-sk-u-boot.dtsi index fa778b0..1fc0d40 100644 --- a/arch/arm/dts/k3-am625-sk-u-boot.dtsi +++ b/arch/arm/dts/k3-am625-sk-u-boot.dtsi @@ -46,3 +46,12 @@ &cpsw_port2 { status = "disabled"; }; + +&usbss0 { + bootph-all; +}; + +&usb0 { + dr_mode = "peripheral"; + bootph-all; +}; diff --git a/arch/arm/dts/k3-am68-sk-base-board-u-boot.dtsi b/arch/arm/dts/k3-am68-sk-base-board-u-boot.dtsi index b8fc62f..4b8d73a 100644 --- a/arch/arm/dts/k3-am68-sk-base-board-u-boot.dtsi +++ b/arch/arm/dts/k3-am68-sk-base-board-u-boot.dtsi @@ -19,10 +19,14 @@ &cbass_mcu_wakeup { bootph-all; +}; + +&wkup_conf { + bootph-all; +}; - chipid@43000014 { - bootph-all; - }; +&chipid { + bootph-all; }; &mcu_navss { @@ -34,14 +38,6 @@ }; &mcu_udmap { - reg = <0x0 0x285c0000 0x0 0x100>, - <0x0 0x284c0000 0x0 0x4000>, - <0x0 0x2a800000 0x0 0x40000>, - <0x0 0x284a0000 0x0 0x4000>, - <0x0 0x2aa00000 0x0 0x40000>, - <0x0 0x28400000 0x0 0x2000>; - reg-names = "gcfg", "rchan", "rchanrt", "tchan", - "tchanrt", "rflow"; bootph-all; }; @@ -129,3 +125,26 @@ dr_mode = "peripheral"; bootph-all; }; + +#ifdef CONFIG_TARGET_J721S2_A72_EVM + +#define SPL_AM68_SK_DTB "spl/dts/ti/k3-am68-sk-base-board.dtb" +#define AM68_SK_DTB "u-boot.dtb" + +&spl_j721s2_evm_dtb { + filename = SPL_AM68_SK_DTB; +}; + +&j721s2_evm_dtb { + filename = AM68_SK_DTB; +}; + +&spl_j721s2_evm_dtb_unsigned { + filename = SPL_AM68_SK_DTB; +}; + +&j721s2_evm_dtb_unsigned { + filename = AM68_SK_DTB; +}; + +#endif diff --git a/arch/arm/dts/k3-am68-sk-base-board.dts b/arch/arm/dts/k3-am68-sk-base-board.dts deleted file mode 100644 index 1e1a82f..0000000 --- a/arch/arm/dts/k3-am68-sk-base-board.dts +++ /dev/null @@ -1,611 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ - * - * Base Board: https://www.ti.com/lit/zip/SPRR463 - */ - -/dts-v1/; - -#include "k3-am68-sk-som.dtsi" -#include <dt-bindings/net/ti-dp83867.h> -#include <dt-bindings/phy/phy-cadence.h> -#include <dt-bindings/phy/phy.h> - -#include "k3-serdes.h" - -/ { - compatible = "ti,am68-sk", "ti,j721s2"; - model = "Texas Instruments AM68 SK"; - - chosen { - stdout-path = "serial2:115200n8"; - }; - - aliases { - serial0 = &wkup_uart0; - serial1 = &mcu_uart0; - serial2 = &main_uart8; - mmc1 = &main_sdhci1; - can0 = &mcu_mcan0; - can1 = &mcu_mcan1; - can2 = &main_mcan6; - can3 = &main_mcan7; - }; - - vusb_main: regulator-vusb-main5v0 { - /* USB MAIN INPUT 5V DC */ - compatible = "regulator-fixed"; - regulator-name = "vusb-main5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - vsys_3v3: regulator-vsys3v3 { - /* Output of LM5141 */ - compatible = "regulator-fixed"; - regulator-name = "vsys_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vusb_main>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_mmc1: regulator-sd { - /* Output of TPS22918 */ - compatible = "regulator-fixed"; - regulator-name = "vdd_mmc1"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - enable-active-high; - vin-supply = <&vsys_3v3>; - gpio = <&exp1 8 GPIO_ACTIVE_HIGH>; - }; - - vdd_sd_dv: regulator-tlv71033 { - /* Output of TLV71033 */ - compatible = "regulator-gpio"; - regulator-name = "tlv71033"; - pinctrl-names = "default"; - pinctrl-0 = <&vdd_sd_dv_pins_default>; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - vin-supply = <&vsys_3v3>; - gpios = <&main_gpio0 49 GPIO_ACTIVE_HIGH>; - states = <1800000 0x0>, - <3300000 0x1>; - }; - - vsys_io_1v8: regulator-vsys-io-1v8 { - compatible = "regulator-fixed"; - regulator-name = "vsys_io_1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - vsys_io_1v2: regulator-vsys-io-1v2 { - compatible = "regulator-fixed"; - regulator-name = "vsys_io_1v2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-boot-on; - }; - - transceiver1: can-phy0 { - compatible = "ti,tcan1042"; - #phy-cells = <0>; - max-bitrate = <5000000>; - }; - - transceiver2: can-phy1 { - compatible = "ti,tcan1042"; - #phy-cells = <0>; - max-bitrate = <5000000>; - }; - - transceiver3: can-phy2 { - compatible = "ti,tcan1042"; - #phy-cells = <0>; - max-bitrate = <5000000>; - }; - - transceiver4: can-phy3 { - compatible = "ti,tcan1042"; - #phy-cells = <0>; - max-bitrate = <5000000>; - }; - - connector-hdmi { - compatible = "hdmi-connector"; - label = "hdmi"; - type = "a"; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_hpd_pins_default>; - ddc-i2c-bus = <&mcu_i2c1>; - /* HDMI_HPD */ - hpd-gpios = <&main_gpio0 0 GPIO_ACTIVE_HIGH>; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&tfp410_out>; - }; - }; - }; - - bridge-dvi { - compatible = "ti,tfp410"; - /* HDMI_PDn */ - powerdown-gpios = <&exp2 0 GPIO_ACTIVE_LOW>; - ti,deskew = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - tfp410_in: endpoint { - remote-endpoint = <&dpi_out0>; - pclk-sample = <1>; - }; - }; - - port@1 { - reg = <1>; - - tfp410_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; - }; - }; - }; -}; - -&main_pmx0 { - main_uart8_pins_default: main-uart8-default-pins { - pinctrl-single,pins = < - J721S2_IOPAD(0x0d0, PIN_INPUT, 11) /* (AF26) SPI0_CS1.UART8_RXD */ - J721S2_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AH27) SPI0_CLK.UART8_TXD */ - >; - }; - - main_i2c0_pins_default: main-i2c0-default-pins { - pinctrl-single,pins = < - J721S2_IOPAD(0x0e0, PIN_INPUT, 0) /* (AH25) I2C0_SCL */ - J721S2_IOPAD(0x0e4, PIN_INPUT, 0) /* (AE24) I2C0_SDA */ - >; - }; - - main_mmc1_pins_default: main-mmc1-default-pins { - pinctrl-single,pins = < - J721S2_IOPAD(0x104, PIN_INPUT, 0) /* (P23) MMC1_CLK */ - J721S2_IOPAD(0x108, PIN_INPUT, 0) /* (N24) MMC1_CMD */ - J721S2_IOPAD(0x0fc, PIN_INPUT, 0) /* (M23) MMC1_DAT0 */ - J721S2_IOPAD(0x0f8, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */ - J721S2_IOPAD(0x0f4, PIN_INPUT, 0) /* (R24) MMC1_DAT2 */ - J721S2_IOPAD(0x0f0, PIN_INPUT, 0) /* (R22) MMC1_DAT3 */ - J721S2_IOPAD(0x0e8, PIN_INPUT, 8) /* (AE25) TIMER_IO0.MMC1_SDCD */ - >; - }; - - vdd_sd_dv_pins_default: vdd-sd-dv-default-pins { - pinctrl-single,pins = < - J721S2_IOPAD(0x0c4, PIN_INPUT, 7) /* (AB26) ECAP0_IN_APWM_OUT.GPIO0_49 */ - >; - }; - - main_usbss0_pins_default: main-usbss0-default-pins { - pinctrl-single,pins = < - J721S2_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AG25) TIMER_IO1.USB0_DRVVBUS */ - >; - }; - - main_mcan6_pins_default: main-mcan6-default-pins { - pinctrl-single,pins = < - J721S2_IOPAD(0x098, PIN_INPUT, 0) /* (V25) MCASP0_AXR10.MCAN6_RX */ - J721S2_IOPAD(0x094, PIN_INPUT, 0) /* (AA25) MCASP0_AXR9.MCAN6_TX */ - >; - }; - - main_mcan7_pins_default: main-mcan7-default-pins { - pinctrl-single,pins = < - J721S2_IOPAD(0x0a0, PIN_INPUT, 0) /* (AB25) MCASP0_AXR12.MCAN7_RX */ - J721S2_IOPAD(0x09c, PIN_INPUT, 0) /* (T24) MCASP0_AXR11.MCAN7_TX */ - >; - }; - - main_i2c4_pins_default: main-i2c4-default-pins { - pinctrl-single,pins = < - J721S2_IOPAD(0x010, PIN_INPUT_PULLUP, 8) /* (AF28) MCAN13_RX.I2C4_SDA */ - J721S2_IOPAD(0x014, PIN_INPUT_PULLUP, 8) /* (AD25) MCAN14_TX.I2C4_SCL */ - >; - }; - - rpi_header_gpio0_pins_default: rpi-header-gpio0-default-pins { - pinctrl-single,pins = < - J721S2_IOPAD(0x0a8, PIN_INPUT, 7) /* (U24) MCASP0_AXR14.GPIO0_42 */ - J721S2_IOPAD(0x090, PIN_INPUT, 7) /* (W24) MCASP0_AXR8.GPIO0_36 */ - J721S2_IOPAD(0x0bc, PIN_INPUT, 7) /* (V28) MCASP1_AFSX.GPIO0_47 */ - J721S2_IOPAD(0x06c, PIN_INPUT, 7) /* (V26) MCAN1_TX.GPIO0_27 */ - J721S2_IOPAD(0x004, PIN_INPUT, 7) /* (W25) MCAN12_TX.GPIO0_1 */ - J721S2_IOPAD(0x008, PIN_INPUT, 7) /* (AC24) MCAN12_RX.GPIO0_2 */ - J721S2_IOPAD(0x0b8, PIN_INPUT, 7) /* (AA24) MCASP1_ACLKX.GPIO0_46 */ - J721S2_IOPAD(0x00c, PIN_INPUT, 7) /* (AE28) MCAN13_TX.GPIO0_3 */ - J721S2_IOPAD(0x034, PIN_INPUT, 7) /* (AD24) PMIC_WAKE0.GPIO0_13 */ - J721S2_IOPAD(0x0a4, PIN_INPUT, 7) /* (T23) MCASP0_AXR13.GPIO0_41 */ - J721S2_IOPAD(0x0c0, PIN_INPUT, 7) /* (T28) MCASP1_AXR0.GPIO0_48 */ - J721S2_IOPAD(0x0b4, PIN_INPUT, 7) /* (U25) MCASP1_AXR4.GPIO0_45 */ - J721S2_IOPAD(0x0cc, PIN_INPUT, 7) /* (AE27) SPI0_CS0.GPIO0_51 */ - J721S2_IOPAD(0x08c, PIN_INPUT, 7) /* (T25) MCASP0_AXR7.GPIO0_35 */ - >; - }; - - dss_vout0_pins_default: dss-vout0-default-pins { - pinctrl-single,pins = < - J721S2_IOPAD(0x074, PIN_OUTPUT, 2) /* (R28) MCAN2_TX.VOUT0_DATA0 */ - J721S2_IOPAD(0x070, PIN_OUTPUT, 2) /* (R27) MCAN1_RX.VOUT0_DATA1 */ - J721S2_IOPAD(0x04c, PIN_OUTPUT, 2) /* (V27) MCASP1_AXR1.VOUT0_DATA10 */ - J721S2_IOPAD(0x048, PIN_OUTPUT, 2) /* (AB27) MCASP0_AXR2.VOUT0_DATA11 */ - J721S2_IOPAD(0x044, PIN_OUTPUT, 2) /* (Y26) MCASP0_AXR1.VOUT0_DATA12 */ - J721S2_IOPAD(0x040, PIN_OUTPUT, 2) /* (AC28) MCASP0_AXR0.VOUT0_DATA13 */ - J721S2_IOPAD(0x03c, PIN_OUTPUT, 2) /* (U27) MCASP0_AFSX.VOUT0_DATA14 */ - J721S2_IOPAD(0x038, PIN_OUTPUT, 2) /* (AB28) MCASP0_ACLKX.VOUT0_DATA15 */ - J721S2_IOPAD(0x0c8, PIN_OUTPUT, 2) /* (AD28) EXT_REFCLK1.VOUT0_DATA16 */ - J721S2_IOPAD(0x030, PIN_OUTPUT, 2) /* (T26) GPIO0_12.VOUT0_DATA17 */ - J721S2_IOPAD(0x02c, PIN_OUTPUT, 2) /* (V23) GPIO0_11.VOUT0_DATA18 */ - J721S2_IOPAD(0x028, PIN_OUTPUT, 2) /* (AB24) MCAN16_RX.VOUT0_DATA19 */ - J721S2_IOPAD(0x07c, PIN_OUTPUT, 2) /* (T27) MCASP0_AXR3.VOUT0_DATA2 */ - J721S2_IOPAD(0x024, PIN_OUTPUT, 2) /* (Y28) MCAN16_TX.VOUT0_DATA20 */ - J721S2_IOPAD(0x020, PIN_OUTPUT, 2) /* (AA23) MCAN15_RX.VOUT0_DATA21 */ - J721S2_IOPAD(0x01c, PIN_OUTPUT, 2) /* (Y24) MCAN15_TX.VOUT0_DATA22 */ - J721S2_IOPAD(0x018, PIN_OUTPUT, 2) /* (W23) MCAN14_RX.VOUT0_DATA23 */ - J721S2_IOPAD(0x068, PIN_OUTPUT, 2) /* (U28) MCAN0_RX.VOUT0_DATA3 */ - J721S2_IOPAD(0x064, PIN_OUTPUT, 2) /* (W28) MCAN0_TX.VOUT0_DATA4 */ - J721S2_IOPAD(0x060, PIN_OUTPUT, 2) /* (AC27) MCASP2_AXR1.VOUT0_DATA5 */ - J721S2_IOPAD(0x05c, PIN_OUTPUT, 2) /* (AA26) MCASP2_AXR0.VOUT0_DATA6 */ - J721S2_IOPAD(0x058, PIN_OUTPUT, 2) /* (AA27) MCASP2_AFSX.VOUT0_DATA7 */ - J721S2_IOPAD(0x054, PIN_OUTPUT, 2) /* (Y27) MCASP2_ACLKX.VOUT0_DATA8 */ - J721S2_IOPAD(0x050, PIN_OUTPUT, 2) /* (W27) MCASP1_AXR2.VOUT0_DATA9 */ - J721S2_IOPAD(0x084, PIN_OUTPUT, 2) /* (AA28) MCASP0_AXR5.VOUT0_DE */ - J721S2_IOPAD(0x080, PIN_OUTPUT, 2) /* (U26) MCASP0_AXR4.VOUT0_HSYNC */ - J721S2_IOPAD(0x078, PIN_OUTPUT, 2) /* (Y25) MCAN2_RX.VOUT0_PCLK */ - J721S2_IOPAD(0x088, PIN_OUTPUT, 2) /* (AD27) MCASP0_AXR6.VOUT0_VP0_VSYNC */ - >; - }; - - hdmi_hpd_pins_default: hdmi-hpd-default-pins { - pinctrl-single,pins = < - J721S2_IOPAD(0x000, PIN_INPUT, 7) /* (AG24) EXTINTN.GPIO0_0 */ - >; - }; -}; - -&wkup_pmx2 { - wkup_uart0_pins_default: wkup-uart0-default-pins { - pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x070, PIN_INPUT, 0) /* (E25) WKUP_GPIO0_6.WKUP_UART0_CTSn */ - J721S2_WKUP_IOPAD(0x074, PIN_OUTPUT, 0) /* (F28) WKUP_GPIO0_7.WKUP_UART0_RTSn */ - J721S2_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (D28) WKUP_UART0_RXD */ - J721S2_WKUP_IOPAD(0x04c, PIN_OUTPUT, 0) /* (D27) WKUP_UART0_TXD */ - >; - }; - - mcu_cpsw_pins_default: mcu-cpsw-default-pins { - pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x02C, PIN_INPUT, 0) /* (B22) MCU_RGMII1_RD0 */ - J721S2_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (B21) MCU_RGMII1_RD1 */ - J721S2_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (C22) MCU_RGMII1_RD2 */ - J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D23) MCU_RGMII1_RD3 */ - J721S2_WKUP_IOPAD(0x01C, PIN_INPUT, 0) /* (D22) MCU_RGMII1_RXC */ - J721S2_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (E23) MCU_RGMII1_RX_CTL */ - J721S2_WKUP_IOPAD(0x014, PIN_OUTPUT, 0) /* (F23) MCU_RGMII1_TD0 */ - J721S2_WKUP_IOPAD(0x010, PIN_OUTPUT, 0) /* (G22) MCU_RGMII1_TD1 */ - J721S2_WKUP_IOPAD(0x00C, PIN_OUTPUT, 0) /* (E21) MCU_RGMII1_TD2 */ - J721S2_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (E22) MCU_RGMII1_TD3 */ - J721S2_WKUP_IOPAD(0x018, PIN_OUTPUT, 0) /* (F21) MCU_RGMII1_TXC */ - J721S2_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (F22) MCU_RGMII1_TX_CTL */ - >; - }; - - mcu_mdio_pins_default: mcu-mdio-default-pins { - pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x034, PIN_OUTPUT, 0) /* (A21) MCU_MDIO0_MDC */ - J721S2_WKUP_IOPAD(0x030, PIN_INPUT, 0) /* (A22) MCU_MDIO0_MDIO */ - >; - }; - - mcu_mcan0_pins_default: mcu-mcan0-default-pins { - pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x054, PIN_INPUT, 0) /* (E28) MCU_MCAN0_RX */ - J721S2_WKUP_IOPAD(0x050, PIN_OUTPUT, 0) /* (E27) MCU_MCAN0_TX */ - >; - }; - - mcu_mcan1_pins_default: mcu-mcan1-default-pins { - pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x06C, PIN_INPUT, 0) /* (F26) WKUP_GPIO0_5.MCU_MCAN1_RX */ - J721S2_WKUP_IOPAD(0x068, PIN_OUTPUT, 0) /* (C23) WKUP_GPIO0_4.MCU_MCAN1_TX*/ - >; - }; - - mcu_i2c0_pins_default: mcu-i2c0-default-pins { - pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x0a0, PIN_INPUT, 0) /* (G24) MCU_I2C0_SCL */ - J721S2_WKUP_IOPAD(0x0a4, PIN_INPUT, 0) /* (J25) MCU_I2C0_SDA */ - >; - }; - - mcu_i2c1_pins_default: mcu-i2c1-default-pins { - pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x078, PIN_INPUT, 0) /* (F24) WKUP_GPIO0_8.MCU_I2C1_SCL */ - J721S2_WKUP_IOPAD(0x07c, PIN_INPUT, 0) /* (H26) WKUP_GPIO0_9.MCU_I2C1_SDA */ - >; - }; - - mcu_uart0_pins_default: mcu-uart0-default-pins { - pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (C24) WKUP_GPIO0_13.MCU_UART0_RXD */ - J721S2_WKUP_IOPAD(0x088, PIN_OUTPUT, 0) /* (C25) WKUP_GPIO0_12.MCU_UART0_TXD */ - >; - }; - - mcu_rpi_header_gpio0_pins0_default: mcu-rpi-header-gpio0-default-pins-0 { - pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x118, PIN_INPUT, 7) /* (G25) WKUP_GPIO0_66 */ - J721S2_WKUP_IOPAD(0x05C, PIN_INPUT, 7) /* (E24) MCU_SPI1_D0.WKUP_GPIO0_1 */ - J721S2_WKUP_IOPAD(0x060, PIN_INPUT, 7) /* (C28) MCU_SPI1_D1.WKUP_GPIO0_2 */ - J721S2_WKUP_IOPAD(0x058, PIN_INPUT, 7) /* (D26) MCU_SPI1_CLK.WKUP_GPIO0_0 */ - J721S2_WKUP_IOPAD(0x094, PIN_INPUT, 7) /* (D25) MCU_SPI1_CS2.WKUP_GPIO0_15*/ - J721S2_WKUP_IOPAD(0x0B8, PIN_INPUT, 7) /* (G27) WKUP_GPIO0_56 */ - J721S2_WKUP_IOPAD(0x114, PIN_INPUT, 7) /* (J26) WKUP_GPIO0_57 */ - J721S2_WKUP_IOPAD(0x11C, PIN_INPUT, 7) /* (J27) WKUP_GPIO0_67 */ - J721S2_WKUP_IOPAD(0x064, PIN_INPUT, 7) /* (C27) MCU_SPI1_CS0.WKUP_GPIO0_3 */ - >; - }; -}; - -&wkup_pmx3 { - mcu_rpi_header_gpio0_pins1_default: mcu-rpi-header-gpio0-default-pins-1 { - pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x000, PIN_INPUT, 7) /* (K26) WKUP_GPIO0_49 */ - >; - }; -}; - -&main_gpio0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&rpi_header_gpio0_pins_default>; -}; - -&wkup_gpio0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mcu_rpi_header_gpio0_pins0_default>, <&mcu_rpi_header_gpio0_pins1_default>; -}; - -&wkup_uart0 { - status = "reserved"; - pinctrl-names = "default"; - pinctrl-0 = <&wkup_uart0_pins_default>; -}; - -&mcu_uart0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mcu_uart0_pins_default>; -}; - -&main_uart8 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_uart8_pins_default>; - /* Shared with TFA on this platform */ - power-domains = <&k3_pds 357 TI_SCI_PD_SHARED>; -}; - -&main_i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&main_i2c0_pins_default>; - clock-frequency = <400000>; - - exp1: gpio@21 { - compatible = "ti,tca6416"; - reg = <0x21>; - gpio-controller; - #gpio-cells = <2>; - gpio-line-names = " ", " ", " ", " ", " ", - "BOARDID_EEPROM_WP", "CAN_STB", " ", - "GPIO_uSD_PWR_EN", " ", "IO_EXP_PCIe1_M.2_RTSz", - "IO_EXP_MCU_RGMII_RST#", " ", " ", " ", " "; - }; -}; - -&main_i2c4 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_i2c4_pins_default>; - clock-frequency = <400000>; -}; - -&mcu_i2c0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mcu_i2c0_pins_default>; - clock-frequency = <400000>; -}; - -&mcu_i2c1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mcu_i2c1_pins_default>; - /* i2c1 is used for DVI DDC, so we need to use 100kHz */ - clock-frequency = <100000>; - - exp2: gpio@20 { - compatible = "ti,tca6408"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - gpio-line-names = "HDMI_PDn","HDMI_LS_OE", - "DP0_3V3_EN","eDP_ENABLE"; - }; -}; - -&main_sdhci1 { - /* SD card */ - status = "okay"; - pinctrl-0 = <&main_mmc1_pins_default>; - pinctrl-names = "default"; - disable-wp; - vmmc-supply = <&vdd_mmc1>; - vqmmc-supply = <&vdd_sd_dv>; -}; - -&mcu_cpsw { - pinctrl-names = "default"; - pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>; -}; - -&davinci_mdio { - phy0: ethernet-phy@0 { - reg = <0>; - ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; - ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; - ti,min-output-impedance; - }; -}; - -&cpsw_port1 { - phy-mode = "rgmii-rxid"; - phy-handle = <&phy0>; -}; - -&mcu_mcan0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mcu_mcan0_pins_default>; - phys = <&transceiver1>; -}; - -&mcu_mcan1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mcu_mcan1_pins_default>; - phys = <&transceiver2>; -}; - -&main_mcan6 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_mcan6_pins_default>; - phys = <&transceiver3>; -}; - -&main_mcan7 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_mcan7_pins_default>; - phys = <&transceiver4>; -}; - -&dss { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&dss_vout0_pins_default>; - /* - * These clock assignments are chosen to enable the following outputs: - * - * VP0 - DisplayPort SST - * VP1 - DPI0 - * VP2 - DSI - * VP3 - DPI1 - */ - assigned-clocks = <&k3_clks 158 2>, - <&k3_clks 158 5>, - <&k3_clks 158 14>, - <&k3_clks 158 18>; - assigned-clock-parents = <&k3_clks 158 3>, - <&k3_clks 158 7>, - <&k3_clks 158 16>, - <&k3_clks 158 22>; -}; - -&dss_ports { - #address-cells = <1>; - #size-cells = <0>; - - /* HDMI */ - port@1 { - reg = <1>; - - dpi_out0: endpoint { - remote-endpoint = <&tfp410_in>; - }; - }; -}; - -&serdes_ln_ctrl { - idle-states = <J721S2_SERDES0_LANE0_PCIE1_LANE0>, <J721S2_SERDES0_LANE1_PCIE1_LANE1>, - <J721S2_SERDES0_LANE2_USB_SWAP>, <J721S2_SERDES0_LANE3_USB>; -}; - -&serdes_refclk { - clock-frequency = <100000000>; -}; - -&serdes0 { - status = "okay"; - - serdes0_pcie_link: phy@0 { - reg = <0>; - cdns,num-lanes = <2>; - #phy-cells = <0>; - cdns,phy-type = <PHY_TYPE_PCIE>; - resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>; - }; - - serdes0_usb_link: phy@2 { - status = "okay"; - reg = <2>; - cdns,num-lanes = <1>; - #phy-cells = <0>; - cdns,phy-type = <PHY_TYPE_USB3>; - resets = <&serdes_wiz0 3>; - }; -}; - -&pcie1_rc { - status = "okay"; - reset-gpios = <&exp1 10 GPIO_ACTIVE_HIGH>; - phys = <&serdes0_pcie_link>; - phy-names = "pcie-phy"; - num-lanes = <2>; -}; - -&usb_serdes_mux { - idle-states = <0>; /* USB0 to SERDES lane 2 */ -}; - -&usbss0 { - status = "okay"; - pinctrl-0 = <&main_usbss0_pins_default>; - pinctrl-names = "default"; - ti,vbus-divider; -}; - -&usb0 { - dr_mode = "host"; - maximum-speed = "super-speed"; - phys = <&serdes0_usb_link>; - phy-names = "cdns3,usb3-phy"; -}; diff --git a/arch/arm/dts/k3-am68-sk-r5-base-board.dts b/arch/arm/dts/k3-am68-sk-r5-base-board.dts index 695aadc..3b2d7af 100644 --- a/arch/arm/dts/k3-am68-sk-r5-base-board.dts +++ b/arch/arm/dts/k3-am68-sk-r5-base-board.dts @@ -9,77 +9,4 @@ #include "k3-j721s2-ddr-evm-lp4-4266.dtsi" #include "k3-j721s2-ddr.dtsi" #include "k3-am68-sk-base-board-u-boot.dtsi" - -/ { - chosen { - tick-timer = &mcu_timer0; - }; - - aliases { - remoteproc0 = &sysctrler; - remoteproc1 = &a72_0; - }; - - a72_0: a72@0 { - compatible = "ti,am654-rproc"; - reg = <0x0 0x00a90000 0x0 0x10>; - power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>, - <&k3_pds 202 TI_SCI_PD_EXCLUSIVE>; - resets = <&k3_reset 202 0>; - clocks = <&k3_clks 61 1>; - assigned-clocks = <&k3_clks 61 1>, <&k3_clks 202 0>; - assigned-clock-parents = <&k3_clks 61 2>; - assigned-clock-rates = <200000000>, <2000000000>; - ti,sci = <&sms>; - ti,sci-proc-id = <32>; - ti,sci-host-id = <10>; - bootph-pre-ram; - }; - - dm_tifs: dm-tifs { - compatible = "ti,j721e-dm-sci"; - ti,host-id = <3>; - ti,secure-host; - mbox-names = "rx", "tx"; - mboxes= <&secure_proxy_mcu 21>, - <&secure_proxy_mcu 23>; - bootph-pre-ram; - }; -}; - -&mcu_timer0 { - clock-frequency = <250000000>; - bootph-pre-ram; -}; - -&secure_proxy_mcu { - bootph-pre-ram; -}; - -&secure_proxy_sa3 { - bootph-pre-ram; -}; - -&cbass_mcu_wakeup { - sysctrler: sysctrler { - compatible = "ti,am654-system-controller"; - mboxes= <&secure_proxy_mcu 4>, <&secure_proxy_mcu 5>, <&secure_proxy_sa3 5>; - mbox-names = "tx", "rx", "boot_notify"; - bootph-pre-ram; - }; -}; - -&sms { - mboxes= <&secure_proxy_mcu 8>, <&secure_proxy_mcu 6>, <&secure_proxy_mcu 5>; - mbox-names = "tx", "rx", "notify"; - ti,host-id = <4>; - ti,secure-host; -}; - -&mcu_ringacc { - ti,sci = <&dm_tifs>; -}; - -&mcu_udmap { - ti,sci = <&dm_tifs>; -}; +#include "k3-j721s2-r5.dtsi" diff --git a/arch/arm/dts/k3-am68-sk-som.dtsi b/arch/arm/dts/k3-am68-sk-som.dtsi deleted file mode 100644 index 20861a0..0000000 --- a/arch/arm/dts/k3-am68-sk-som.dtsi +++ /dev/null @@ -1,259 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ - */ - -/dts-v1/; - -#include "k3-j721s2.dtsi" -#include <dt-bindings/gpio/gpio.h> - -/ { - memory@80000000 { - device_type = "memory"; - /* 16 GB RAM */ - reg = <0x00 0x80000000 0x00 0x80000000>, - <0x08 0x80000000 0x03 0x80000000>; - }; - - reserved_memory: reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - secure_ddr: optee@9e800000 { - reg = <0x00 0x9e800000 0x00 0x01800000>; - no-map; - }; - - mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa0000000 0x00 0x100000>; - no-map; - }; - - mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa0100000 0x00 0xf00000>; - no-map; - }; - - mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa1000000 0x00 0x100000>; - no-map; - }; - - mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa1100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa2000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core0_memory_region: r5f-memory@a2100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa2100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa3000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core1_memory_region: r5f-memory@a3100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa3100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa4000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core0_memory_region: r5f-memory@a4100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa4100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa5000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core1_memory_region: r5f-memory@a5100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa5100000 0x00 0xf00000>; - no-map; - }; - - c71_0_dma_memory_region: c71-dma-memory@a6000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa6000000 0x00 0x100000>; - no-map; - }; - - c71_0_memory_region: c71-memory@a6100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa6100000 0x00 0xf00000>; - no-map; - }; - - c71_1_dma_memory_region: c71-dma-memory@a7000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa7000000 0x00 0x100000>; - no-map; - }; - - c71_1_memory_region: c71-memory@a7100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa7100000 0x00 0xf00000>; - no-map; - }; - - rtos_ipc_memory_region: ipc-memories@a8000000 { - reg = <0x00 0xa8000000 0x00 0x01c00000>; - alignment = <0x1000>; - no-map; - }; - }; -}; - -&wkup_pmx2 { - wkup_i2c0_pins_default: wkup-i2c0-default-pins { - pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x098, PIN_INPUT, 0) /* (H24) WKUP_I2C0_SCL */ - J721S2_WKUP_IOPAD(0x09c, PIN_INPUT, 0) /* (H27) WKUP_I2C0_SDA */ - >; - }; -}; - -&wkup_i2c0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&wkup_i2c0_pins_default>; - clock-frequency = <400000>; - - eeprom@51 { - /* AT24C512C-MAHM-T */ - compatible = "atmel,24c512"; - reg = <0x51>; - }; -}; - -&mailbox0_cluster0 { - status = "okay"; - interrupts = <436>; - mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster1 { - status = "okay"; - interrupts = <432>; - mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster2 { - status = "okay"; - interrupts = <428>; - mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster4 { - status = "okay"; - interrupts = <420>; - mbox_c71_0: mbox-c71-0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_c71_1: mbox-c71-1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mcu_r5fss0_core0 { - mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>; - memory-region = <&mcu_r5fss0_core0_dma_memory_region>, - <&mcu_r5fss0_core0_memory_region>; -}; - -&mcu_r5fss0_core1 { - mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>; - memory-region = <&mcu_r5fss0_core1_dma_memory_region>, - <&mcu_r5fss0_core1_memory_region>; -}; - -&main_r5fss0_core0 { - mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>; - memory-region = <&main_r5fss0_core0_dma_memory_region>, - <&main_r5fss0_core0_memory_region>; -}; - -&main_r5fss0_core1 { - mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>; - memory-region = <&main_r5fss0_core1_dma_memory_region>, - <&main_r5fss0_core1_memory_region>; -}; - -&main_r5fss1_core0 { - mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core0>; - memory-region = <&main_r5fss1_core0_dma_memory_region>, - <&main_r5fss1_core0_memory_region>; -}; - -&main_r5fss1_core1 { - mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core1>; - memory-region = <&main_r5fss1_core1_dma_memory_region>, - <&main_r5fss1_core1_memory_region>; -}; - -&c71_0 { - status = "okay"; - mboxes = <&mailbox0_cluster4>, <&mbox_c71_0>; - memory-region = <&c71_0_dma_memory_region>, - <&c71_0_memory_region>; -}; - -&c71_1 { - status = "okay"; - mboxes = <&mailbox0_cluster4>, <&mbox_c71_1>; - memory-region = <&c71_1_dma_memory_region>, - <&c71_1_memory_region>; -}; diff --git a/arch/arm/dts/k3-j721s2-binman.dtsi b/arch/arm/dts/k3-j721s2-binman.dtsi index 7efb135..46297eb 100644 --- a/arch/arm/dts/k3-j721s2-binman.dtsi +++ b/arch/arm/dts/k3-j721s2-binman.dtsi @@ -141,11 +141,8 @@ #ifdef CONFIG_TARGET_J721S2_A72_EVM -#define SPL_J721S2_EVM_DTB "spl/dts/k3-j721s2-common-proc-board.dtb" -#define SPL_AM68_SK_DTB "spl/dts/k3-am68-sk-base-board.dtb" - +#define SPL_J721S2_EVM_DTB "spl/dts/ti/k3-j721s2-common-proc-board.dtb" #define J721S2_EVM_DTB "u-boot.dtb" -#define AM68_SK_DTB "arch/arm/dts/k3-am68-sk-base-board.dtb" &binman { ti-dm { @@ -306,20 +303,6 @@ }; }; - - fdt-1 { - description = "k3-am68-sk-base-board"; - type = "flat_dt"; - arch = "arm"; - compression = "none"; - ti-secure { - content = <&spl_am68_sk_dtb>; - keyfile = "custMpk.pem"; - }; - spl_am68_sk_dtb: blob-ext { - filename = SPL_AM68_SK_DTB; - }; - }; }; configurations { @@ -331,13 +314,6 @@ loadables = "tee", "dm", "spl"; fdt = "fdt-0"; }; - - conf-1 { - description = "k3-am68-sk-base-board"; - firmware = "atf"; - loadables = "tee", "dm", "spl"; - fdt = "fdt-1"; - }; }; }; }; @@ -370,25 +346,6 @@ algo = "crc32"; }; }; - - fdt-1 { - description = "k3-am68-sk-base-board"; - type = "flat_dt"; - arch = "arm"; - compression = "none"; - ti-secure { - content = <&am68_sk_dtb>; - keyfile = "custMpk.pem"; - }; - am68_sk_dtb: blob-ext { - filename = AM68_SK_DTB; - }; - - hash { - algo = "crc32"; - }; - }; - }; configurations { @@ -400,13 +357,6 @@ loadables = "uboot"; fdt = "fdt-0"; }; - conf-1 { - description = "k3-am68-sk-base-board"; - firmware = "uboot"; - loadables = "uboot"; - fdt = "fdt-1"; - }; - }; }; }; @@ -429,20 +379,10 @@ type = "flat_dt"; arch = "arm"; compression = "none"; - blob { + spl_j721s2_evm_dtb_unsigned: blob { filename = SPL_J721S2_EVM_DTB; }; }; - fdt-1 { - description = "k3-am68-sk-base-board"; - type = "flat_dt"; - arch = "arm"; - compression = "none"; - blob { - filename = SPL_AM68_SK_DTB; - }; - }; - }; configurations { @@ -454,12 +394,6 @@ loadables = "tee", "dm", "spl"; fdt = "fdt-0"; }; - conf-1 { - description = "k3-am68-sk-base-board"; - firmware = "atf"; - loadables = "tee", "dm", "spl"; - fdt = "fdt-1"; - }; }; }; }; @@ -480,26 +414,13 @@ type = "flat_dt"; arch = "arm"; compression = "none"; - blob { + j721s2_evm_dtb_unsigned: blob { filename = J721S2_EVM_DTB; }; hash { algo = "crc32"; }; }; - fdt-1 { - description = "k3-am68-sk-base-board"; - type = "flat_dt"; - arch = "arm"; - compression = "none"; - blob { - filename = AM68_SK_DTB; - }; - hash { - algo = "crc32"; - }; - }; - }; configurations { @@ -511,12 +432,6 @@ loadables = "uboot"; fdt = "fdt-0"; }; - conf-1 { - description = "k3-am68-sk-base-board"; - firmware = "uboot"; - loadables = "uboot"; - fdt = "fdt-1"; - }; }; }; }; diff --git a/arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi index 19b2d48..91a82b3 100644 --- a/arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi +++ b/arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi @@ -19,10 +19,14 @@ &cbass_mcu_wakeup { bootph-all; +}; - chipid@43000014 { - bootph-all; - }; +&wkup_conf { + bootph-all; +}; + +&chipid { + bootph-all; }; &mcu_navss { @@ -34,14 +38,6 @@ }; &mcu_udmap { - reg = <0x0 0x285c0000 0x0 0x100>, - <0x0 0x284c0000 0x0 0x4000>, - <0x0 0x2a800000 0x0 0x40000>, - <0x0 0x284a0000 0x0 0x4000>, - <0x0 0x2aa00000 0x0 0x40000>, - <0x0 0x28400000 0x0 0x2000>; - reg-names = "gcfg", "rchan", "rchanrt", "tchan", - "tchanrt", "rflow"; bootph-all; }; diff --git a/arch/arm/dts/k3-j721s2-common-proc-board.dts b/arch/arm/dts/k3-j721s2-common-proc-board.dts deleted file mode 100644 index c6b85bb..0000000 --- a/arch/arm/dts/k3-j721s2-common-proc-board.dts +++ /dev/null @@ -1,504 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ - * - * Common Processor Board: https://www.ti.com/tool/J721EXCPXEVM - */ - -/dts-v1/; - -#include "k3-j721s2-som-p0.dtsi" -#include <dt-bindings/net/ti-dp83867.h> -#include <dt-bindings/phy/phy-cadence.h> -#include <dt-bindings/phy/phy.h> - -#include "k3-serdes.h" - -/ { - compatible = "ti,j721s2-evm", "ti,j721s2"; - model = "Texas Instruments J721S2 EVM"; - - chosen { - stdout-path = "serial2:115200n8"; - }; - - aliases { - serial1 = &mcu_uart0; - serial2 = &main_uart8; - mmc0 = &main_sdhci0; - mmc1 = &main_sdhci1; - can0 = &main_mcan16; - can1 = &mcu_mcan0; - can2 = &mcu_mcan1; - can3 = &main_mcan3; - can4 = &main_mcan5; - }; - - evm_12v0: fixedregulator-evm12v0 { - /* main supply */ - compatible = "regulator-fixed"; - regulator-name = "evm_12v0"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - regulator-always-on; - regulator-boot-on; - }; - - vsys_3v3: fixedregulator-vsys3v3 { - /* Output of LM5140 */ - compatible = "regulator-fixed"; - regulator-name = "vsys_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&evm_12v0>; - regulator-always-on; - regulator-boot-on; - }; - - vsys_5v0: fixedregulator-vsys5v0 { - /* Output of LM5140 */ - compatible = "regulator-fixed"; - regulator-name = "vsys_5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&evm_12v0>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_mmc1: fixedregulator-sd { - /* Output of TPS22918 */ - compatible = "regulator-fixed"; - regulator-name = "vdd_mmc1"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - enable-active-high; - vin-supply = <&vsys_3v3>; - gpio = <&exp2 2 GPIO_ACTIVE_HIGH>; - }; - - vdd_sd_dv: gpio-regulator-TLV71033 { - /* Output of TLV71033 */ - compatible = "regulator-gpio"; - regulator-name = "tlv71033"; - pinctrl-names = "default"; - pinctrl-0 = <&vdd_sd_dv_pins_default>; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - vin-supply = <&vsys_5v0>; - gpios = <&main_gpio0 8 GPIO_ACTIVE_HIGH>; - states = <1800000 0x0>, - <3300000 0x1>; - }; - - transceiver1: can-phy1 { - compatible = "ti,tcan1043"; - #phy-cells = <0>; - max-bitrate = <5000000>; - pinctrl-names = "default"; - pinctrl-0 = <&mcu_mcan0_gpio_pins_default>; - standby-gpios = <&wkup_gpio0 69 GPIO_ACTIVE_LOW>; - enable-gpios = <&wkup_gpio0 0 GPIO_ACTIVE_HIGH>; - }; - - transceiver2: can-phy2 { - compatible = "ti,tcan1042"; - #phy-cells = <0>; - max-bitrate = <5000000>; - pinctrl-names = "default"; - pinctrl-0 = <&mcu_mcan1_gpio_pins_default>; - standby-gpios = <&wkup_gpio0 2 GPIO_ACTIVE_HIGH>; - }; - - transceiver3: can-phy3 { - compatible = "ti,tcan1043"; - #phy-cells = <0>; - max-bitrate = <5000000>; - standby-gpios = <&exp2 7 GPIO_ACTIVE_LOW>; - enable-gpios = <&exp2 6 GPIO_ACTIVE_HIGH>; - mux-states = <&mux0 1>; - }; - - transceiver4: can-phy4 { - compatible = "ti,tcan1042"; - #phy-cells = <0>; - max-bitrate = <5000000>; - standby-gpios = <&exp_som 7 GPIO_ACTIVE_HIGH>; - mux-states = <&mux1 1>; - }; -}; - -&main_pmx0 { - main_uart8_pins_default: main-uart8-default-pins { - pinctrl-single,pins = < - J721S2_IOPAD(0x040, PIN_INPUT, 14) /* (AC28) MCASP0_AXR0.UART8_CTSn */ - J721S2_IOPAD(0x044, PIN_OUTPUT, 14) /* (Y26) MCASP0_AXR1.UART8_RTSn */ - J721S2_IOPAD(0x0d0, PIN_INPUT, 11) /* (AF26) SPI0_CS1.UART8_RXD */ - J721S2_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AH27) SPI0_CLK.UART8_TXD */ - >; - }; - - main_i2c3_pins_default: main-i2c3-default-pins { - pinctrl-single,pins = < - J721S2_IOPAD(0x064, PIN_INPUT_PULLUP, 13) /* (W28) MCAN0_TX.I2C3_SCL */ - J721S2_IOPAD(0x060, PIN_INPUT_PULLUP, 13) /* (AC27) MCASP2_AXR1.I2C3_SDA */ - >; - }; - - main_mmc1_pins_default: main-mmc1-default-pins { - pinctrl-single,pins = < - J721S2_IOPAD(0x104, PIN_INPUT, 0) /* (P23) MMC1_CLK */ - J721S2_IOPAD(0x108, PIN_INPUT, 0) /* (N24) MMC1_CMD */ - J721S2_IOPAD(0x100, PIN_INPUT, 0) /* (###) MMC1_CLKLB */ - J721S2_IOPAD(0x0fc, PIN_INPUT, 0) /* (M23) MMC1_DAT0 */ - J721S2_IOPAD(0x0f8, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */ - J721S2_IOPAD(0x0f4, PIN_INPUT, 0) /* (R24) MMC1_DAT2 */ - J721S2_IOPAD(0x0f0, PIN_INPUT, 0) /* (R22) MMC1_DAT3 */ - J721S2_IOPAD(0x0e8, PIN_INPUT, 8) /* (AE25) TIMER_IO0.MMC1_SDCD */ - >; - }; - - vdd_sd_dv_pins_default: vdd-sd-dv-default-pins { - pinctrl-single,pins = < - J721S2_IOPAD(0x020, PIN_INPUT, 7) /* (AA23) MCAN15_RX.GPIO0_8 */ - >; - }; - - main_usbss0_pins_default: main-usbss0-default-pins { - pinctrl-single,pins = < - J721S2_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AG25) TIMER_IO1.USB0_DRVVBUS */ - >; - }; - - main_mcan3_pins_default: main-mcan3-default-pins { - pinctrl-single,pins = < - J721S2_IOPAD(0x080, PIN_INPUT, 0) /* (U26) MCASP0_AXR4.MCAN3_RX */ - J721S2_IOPAD(0x07c, PIN_OUTPUT, 0) /* (T27) MCASP0_AXR3.MCAN3_TX */ - >; - }; - - main_mcan5_pins_default: main-mcan5-default-pins { - pinctrl-single,pins = < - J721S2_IOPAD(0x03c, PIN_INPUT, 0) /* (U27) MCASP0_AFSX.MCAN5_RX */ - J721S2_IOPAD(0x038, PIN_OUTPUT, 0) /* (AB28) MCASP0_ACLKX.MCAN5_TX */ - >; - }; -}; - -&wkup_pmx2 { - wkup_uart0_pins_default: wkup-uart0-default-pins { - pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x070, PIN_INPUT, 0) /* (E25) WKUP_GPIO0_6.WKUP_UART0_CTSn */ - J721S2_WKUP_IOPAD(0x074, PIN_OUTPUT, 0) /* (F28) WKUP_GPIO0_7.WKUP_UART0_RTSn */ - J721S2_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (D28) WKUP_UART0_RXD */ - J721S2_WKUP_IOPAD(0x04c, PIN_OUTPUT, 0) /* (D27) WKUP_UART0_TXD */ - >; - }; - - mcu_uart0_pins_default: mcu-uart0-default-pins { - pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x090, PIN_INPUT, 0) /* (B24) WKUP_GPIO0_14.MCU_UART0_CTSn */ - J721S2_WKUP_IOPAD(0x094, PIN_OUTPUT, 0) /* (D25) WKUP_GPIO0_15.MCU_UART0_RTSn */ - J721S2_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (C24) WKUP_GPIO0_13.MCU_UART0_RXD */ - J721S2_WKUP_IOPAD(0x088, PIN_OUTPUT, 0) /* (C25) WKUP_GPIO0_12.MCU_UART0_TXD */ - >; - }; - - mcu_cpsw_pins_default: mcu-cpsw-default-pins { - pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x02c, PIN_INPUT, 0) /* (B22) MCU_RGMII1_RD0 */ - J721S2_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (B21) MCU_RGMII1_RD1 */ - J721S2_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (C22) MCU_RGMII1_RD2 */ - J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D23) MCU_RGMII1_RD3 */ - J721S2_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (D22) MCU_RGMII1_RXC */ - J721S2_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (E23) MCU_RGMII1_RX_CTL */ - J721S2_WKUP_IOPAD(0x014, PIN_OUTPUT, 0) /* (F23) MCU_RGMII1_TD0 */ - J721S2_WKUP_IOPAD(0x010, PIN_OUTPUT, 0) /* (G22) MCU_RGMII1_TD1 */ - J721S2_WKUP_IOPAD(0x00c, PIN_OUTPUT, 0) /* (E21) MCU_RGMII1_TD2 */ - J721S2_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (E22) MCU_RGMII1_TD3 */ - J721S2_WKUP_IOPAD(0x018, PIN_OUTPUT, 0) /* (F21) MCU_RGMII1_TXC */ - J721S2_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (F22) MCU_RGMII1_TX_CTL */ - >; - }; - - mcu_mdio_pins_default: mcu-mdio-default-pins { - pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x034, PIN_OUTPUT, 0) /* (A21) MCU_MDIO0_MDC */ - J721S2_WKUP_IOPAD(0x030, PIN_INPUT, 0) /* (A22) MCU_MDIO0_MDIO */ - >; - }; - - mcu_mcan0_pins_default: mcu-mcan0-default-pins { - pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x054, PIN_INPUT, 0) /* (E28) MCU_MCAN0_RX */ - J721S2_WKUP_IOPAD(0x050, PIN_OUTPUT, 0) /* (E27) MCU_MCAN0_TX */ - >; - }; - - mcu_mcan1_pins_default: mcu-mcan1-default-pins { - pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x06c, PIN_INPUT, 0) /* (F26) WKUP_GPIO0_5.MCU_MCAN1_RX */ - J721S2_WKUP_IOPAD(0x068, PIN_OUTPUT, 0) /*(C23) WKUP_GPIO0_4.MCU_MCAN1_TX */ - >; - }; - - mcu_mcan0_gpio_pins_default: mcu-mcan0-gpio-default-pins { - pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x058, PIN_INPUT, 7) /* (D26) WKUP_GPIO0_0 */ - J721S2_WKUP_IOPAD(0x040, PIN_INPUT, 7) /* (B25) MCU_SPI0_D1.WKUP_GPIO0_69 */ - >; - }; - - mcu_mcan1_gpio_pins_default: mcu-mcan1-gpio-default-pins { - pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x060, PIN_INPUT, 7) /* (C28) WKUP_GPIO0_2 */ - >; - }; - - mcu_adc0_pins_default: mcu-adc0-default-pins { - pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x0cc, PIN_INPUT, 0) /* (L25) MCU_ADC0_AIN0 */ - J721S2_WKUP_IOPAD(0x0d0, PIN_INPUT, 0) /* (K25) MCU_ADC0_AIN1 */ - J721S2_WKUP_IOPAD(0x0d4, PIN_INPUT, 0) /* (M24) MCU_ADC0_AIN2 */ - J721S2_WKUP_IOPAD(0x0d8, PIN_INPUT, 0) /* (L24) MCU_ADC0_AIN3 */ - J721S2_WKUP_IOPAD(0x0dc, PIN_INPUT, 0) /* (L27) MCU_ADC0_AIN4 */ - J721S2_WKUP_IOPAD(0x0e0, PIN_INPUT, 0) /* (K24) MCU_ADC0_AIN5 */ - J721S2_WKUP_IOPAD(0x0e4, PIN_INPUT, 0) /* (M27) MCU_ADC0_AIN6 */ - J721S2_WKUP_IOPAD(0x0e8, PIN_INPUT, 0) /* (M26) MCU_ADC0_AIN7 */ - >; - }; - - mcu_adc1_pins_default: mcu-adc1-default-pins { - pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x0ec, PIN_INPUT, 0) /* (P25) MCU_ADC1_AIN0 */ - J721S2_WKUP_IOPAD(0x0f0, PIN_INPUT, 0) /* (R25) MCU_ADC1_AIN1 */ - J721S2_WKUP_IOPAD(0x0f4, PIN_INPUT, 0) /* (P28) MCU_ADC1_AIN2 */ - J721S2_WKUP_IOPAD(0x0f8, PIN_INPUT, 0) /* (P27) MCU_ADC1_AIN3 */ - J721S2_WKUP_IOPAD(0x0fc, PIN_INPUT, 0) /* (N25) MCU_ADC1_AIN4 */ - J721S2_WKUP_IOPAD(0x100, PIN_INPUT, 0) /* (P26) MCU_ADC1_AIN5 */ - J721S2_WKUP_IOPAD(0x104, PIN_INPUT, 0) /* (N26) MCU_ADC1_AIN6 */ - J721S2_WKUP_IOPAD(0x108, PIN_INPUT, 0) /* (N27) MCU_ADC1_AIN7 */ - >; - }; -}; - -&wkup_pmx1 { - mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-default-pins { - pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (A19) MCU_OSPI1_CLK */ - J721S2_WKUP_IOPAD(0x024, PIN_OUTPUT, 0) /* (D20) MCU_OSPI1_CSn0 */ - J721S2_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (D21) MCU_OSPI1_D0 */ - J721S2_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (G20) MCU_OSPI1_D1 */ - J721S2_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (C20) MCU_OSPI1_D2 */ - J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (A20) MCU_OSPI1_D3 */ - J721S2_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (B19) MCU_OSPI1_DQS */ - J721S2_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (B20) MCU_OSPI1_LBCLKO */ - >; - }; -}; - -&main_gpio0 { - status = "okay"; -}; - -&wkup_gpio0 { - status = "okay"; -}; - -&wkup_uart0 { - status = "reserved"; - pinctrl-names = "default"; - pinctrl-0 = <&wkup_uart0_pins_default>; -}; - -&mcu_uart0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mcu_uart0_pins_default>; -}; - -&main_uart8 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_uart8_pins_default>; - /* Shared with TFA on this platform */ - power-domains = <&k3_pds 357 TI_SCI_PD_SHARED>; -}; - -&main_i2c0 { - clock-frequency = <400000>; - - exp1: gpio@20 { - compatible = "ti,tca6416"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - gpio-line-names = "PCIE_2L_MODE_SEL", "PCIE_2L_PERSTZ", "PCIE_2L_RC_RSTZ", - "PCIE_2L_EP_RST_EN", "PCIE_1L_MODE_SEL", "PCIE_1L_PERSTZ", - "PCIE_1L_RC_RSTZ", "PCIE_1L_EP_RST_EN", "PCIE_2L_PRSNT#", - "PCIE_1L_PRSNT#", "CDCI1_OE1/OE4", "CDCI1_OE2/OE3", "EXP_MUX1", - "EXP_MUX2", "EXP_MUX3", "GESI_EXP_PHY_RSTz"; - }; - - exp2: gpio@22 { - compatible = "ti,tca6424"; - reg = <0x22>; - gpio-controller; - #gpio-cells = <2>; - gpio-line-names = "APPLE_AUTH_RSTZ", "MLB_RSTZ", "GPIO_USD_PWR_EN", "USBC_PWR_EN", - "USBC_MODE_SEL1", "USBC_MODE_SEL0", "MCAN0_EN", "MCAN0_STB#", - "MUX_SPAREMUX_SPARE", "MCASP/TRACE_MUX_S0", "MCASP/TRACE_MUX_S1", - "MLB_MUX_SEL", "MCAN_MUX_SEL", "MCASP2/SPI3_MUX_SEL", "PCIe_CLKREQn_MUX_SEL", - "CDCI2_RSTZ", "ENET_EXP_PWRDN", "ENET_EXP_RESETZ", "ENET_I2CMUX_SEL", - "ENET_EXP_SPARE2", "M2PCIE_RTSZ", "USER_INPUT1", "USER_LED1", "USER_LED2"; - }; -}; - -&main_sdhci0 { - /* eMMC */ - status = "okay"; - non-removable; - ti,driver-strength-ohm = <50>; - disable-wp; -}; - -&main_sdhci1 { - /* SD card */ - status = "okay"; - pinctrl-0 = <&main_mmc1_pins_default>; - pinctrl-names = "default"; - disable-wp; - vmmc-supply = <&vdd_mmc1>; - vqmmc-supply = <&vdd_sd_dv>; -}; - -&mcu_cpsw { - pinctrl-names = "default"; - pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>; -}; - -&davinci_mdio { - phy0: ethernet-phy@0 { - reg = <0>; - ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; - ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; - ti,min-output-impedance; - }; -}; - -&cpsw_port1 { - phy-mode = "rgmii-rxid"; - phy-handle = <&phy0>; -}; - -&serdes_ln_ctrl { - idle-states = <J721S2_SERDES0_LANE0_PCIE1_LANE0>, <J721S2_SERDES0_LANE1_USB>, - <J721S2_SERDES0_LANE2_EDP_LANE2>, <J721S2_SERDES0_LANE3_EDP_LANE3>; -}; - -&serdes_refclk { - clock-frequency = <100000000>; -}; - -&serdes0 { - status = "okay"; - serdes0_pcie_link: phy@0 { - reg = <0>; - cdns,num-lanes = <1>; - #phy-cells = <0>; - cdns,phy-type = <PHY_TYPE_PCIE>; - resets = <&serdes_wiz0 1>; - }; -}; - -&usb_serdes_mux { - idle-states = <1>; /* USB0 to SERDES lane 1 */ -}; - -&usbss0 { - status = "okay"; - pinctrl-0 = <&main_usbss0_pins_default>; - pinctrl-names = "default"; - ti,vbus-divider; - ti,usb2-only; -}; - -&usb0 { - dr_mode = "otg"; - maximum-speed = "high-speed"; -}; - -&ospi1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mcu_fss0_ospi1_pins_default>; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0x0>; - spi-tx-bus-width = <1>; - spi-rx-bus-width = <4>; - spi-max-frequency = <40000000>; - cdns,tshsl-ns = <60>; - cdns,tsd2d-ns = <60>; - cdns,tchsh-ns = <60>; - cdns,tslch-ns = <60>; - cdns,read-delay = <2>; - }; -}; - -&pcie1_rc { - status = "okay"; - reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>; - phys = <&serdes0_pcie_link>; - phy-names = "pcie-phy"; - num-lanes = <1>; -}; - -&mcu_mcan0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mcu_mcan0_pins_default>; - phys = <&transceiver1>; -}; - -&mcu_mcan1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mcu_mcan1_pins_default>; - phys = <&transceiver2>; -}; - -&tscadc0 { - pinctrl-0 = <&mcu_adc0_pins_default>; - pinctrl-names = "default"; - status = "okay"; - adc { - ti,adc-channels = <0 1 2 3 4 5 6 7>; - }; -}; - -&tscadc1 { - pinctrl-0 = <&mcu_adc1_pins_default>; - pinctrl-names = "default"; - status = "okay"; - adc { - ti,adc-channels = <0 1 2 3 4 5 6 7>; - }; -}; - -&main_mcan3 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_mcan3_pins_default>; - phys = <&transceiver3>; -}; - -&main_mcan5 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_mcan5_pins_default>; - phys = <&transceiver4>; -}; diff --git a/arch/arm/dts/k3-j721s2-main.dtsi b/arch/arm/dts/k3-j721s2-main.dtsi deleted file mode 100644 index b03731b..0000000 --- a/arch/arm/dts/k3-j721s2-main.dtsi +++ /dev/null @@ -1,1928 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for J721S2 SoC Family Main Domain peripherals - * - * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ - */ - -#include <dt-bindings/phy/phy-cadence.h> -#include <dt-bindings/phy/phy-ti.h> - -/ { - serdes_refclk: clock-cmnrefclk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; -}; - -&cbass_main { - msmc_ram: sram@70000000 { - compatible = "mmio-sram"; - reg = <0x0 0x70000000 0x0 0x400000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x70000000 0x400000>; - - atf-sram@0 { - reg = <0x0 0x20000>; - }; - - tifs-sram@1f0000 { - reg = <0x1f0000 0x10000>; - }; - - l3cache-sram@200000 { - reg = <0x200000 0x200000>; - }; - }; - - scm_conf: syscon@104000 { - compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; - reg = <0x00 0x00104000 0x00 0x18000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00 0x00 0x00104000 0x18000>; - - usb_serdes_mux: mux-controller@0 { - compatible = "mmio-mux"; - reg = <0x0 0x4>; - #mux-control-cells = <1>; - mux-reg-masks = <0x0 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */ - }; - - phy_gmii_sel_cpsw: phy@34 { - compatible = "ti,am654-phy-gmii-sel"; - reg = <0x34 0x4>; - #phy-cells = <1>; - }; - - serdes_ln_ctrl: mux-controller@80 { - compatible = "mmio-mux"; - reg = <0x80 0x10>; - #mux-control-cells = <1>; - mux-reg-masks = <0x80 0x3>, <0x84 0x3>, /* SERDES0 lane0/1 select */ - <0x88 0x3>, <0x8c 0x3>; /* SERDES0 lane2/3 select */ - }; - - ehrpwm_tbclk: clock-controller@140 { - compatible = "ti,am654-ehrpwm-tbclk"; - reg = <0x140 0x18>; - #clock-cells = <1>; - }; - }; - - main_ehrpwm0: pwm@3000000 { - compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; - #pwm-cells = <3>; - reg = <0x00 0x3000000 0x00 0x100>; - power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>; - clocks = <&ehrpwm_tbclk 0>, <&k3_clks 160 0>; - clock-names = "tbclk", "fck"; - status = "disabled"; - }; - - main_ehrpwm1: pwm@3010000 { - compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; - #pwm-cells = <3>; - reg = <0x00 0x3010000 0x00 0x100>; - power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>; - clocks = <&ehrpwm_tbclk 1>, <&k3_clks 161 0>; - clock-names = "tbclk", "fck"; - status = "disabled"; - }; - - main_ehrpwm2: pwm@3020000 { - compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; - #pwm-cells = <3>; - reg = <0x00 0x3020000 0x00 0x100>; - power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>; - clocks = <&ehrpwm_tbclk 2>, <&k3_clks 162 0>; - clock-names = "tbclk", "fck"; - status = "disabled"; - }; - - main_ehrpwm3: pwm@3030000 { - compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; - #pwm-cells = <3>; - reg = <0x00 0x3030000 0x00 0x100>; - power-domains = <&k3_pds 163 TI_SCI_PD_EXCLUSIVE>; - clocks = <&ehrpwm_tbclk 3>, <&k3_clks 163 0>; - clock-names = "tbclk", "fck"; - status = "disabled"; - }; - - main_ehrpwm4: pwm@3040000 { - compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; - #pwm-cells = <3>; - reg = <0x00 0x3040000 0x00 0x100>; - power-domains = <&k3_pds 164 TI_SCI_PD_EXCLUSIVE>; - clocks = <&ehrpwm_tbclk 4>, <&k3_clks 164 0>; - clock-names = "tbclk", "fck"; - status = "disabled"; - }; - - main_ehrpwm5: pwm@3050000 { - compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; - #pwm-cells = <3>; - reg = <0x00 0x3050000 0x00 0x100>; - power-domains = <&k3_pds 165 TI_SCI_PD_EXCLUSIVE>; - clocks = <&ehrpwm_tbclk 5>, <&k3_clks 165 0>; - clock-names = "tbclk", "fck"; - status = "disabled"; - }; - - gic500: interrupt-controller@1800000 { - compatible = "arm,gic-v3"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x00 0x01800000 0x00 0x100000>, /* GICD */ - <0x00 0x01900000 0x00 0x100000>, /* GICR */ - <0x00 0x6f000000 0x00 0x2000>, /* GICC */ - <0x00 0x6f010000 0x00 0x1000>, /* GICH */ - <0x00 0x6f020000 0x00 0x2000>; /* GICV */ - - /* vcpumntirq: virtual CPU interface maintenance interrupt */ - interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; - - gic_its: msi-controller@1820000 { - compatible = "arm,gic-v3-its"; - reg = <0x00 0x01820000 0x00 0x10000>; - socionext,synquacer-pre-its = <0x1000000 0x400000>; - msi-controller; - #msi-cells = <1>; - }; - }; - - main_gpio_intr: interrupt-controller@a00000 { - compatible = "ti,sci-intr"; - reg = <0x00 0x00a00000 0x00 0x800>; - ti,intr-trigger-type = <1>; - interrupt-controller; - interrupt-parent = <&gic500>; - #interrupt-cells = <1>; - ti,sci = <&sms>; - ti,sci-dev-id = <148>; - ti,interrupt-ranges = <8 392 56>; - }; - - main_pmx0: pinctrl@11c000 { - compatible = "pinctrl-single"; - /* Proxy 0 addressing */ - reg = <0x0 0x11c000 0x0 0x120>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0xffffffff>; - }; - - /* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */ - main_timerio_input: pinctrl@104200 { - compatible = "pinctrl-single"; - reg = <0x00 0x104200 0x00 0x50>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0x00000007>; - }; - - /* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */ - main_timerio_output: pinctrl@104280 { - compatible = "pinctrl-single"; - reg = <0x00 0x104280 0x00 0x20>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0x0000001f>; - }; - - main_crypto: crypto@4e00000 { - compatible = "ti,j721e-sa2ul"; - reg = <0x00 0x04e00000 0x00 0x1200>; - power-domains = <&k3_pds 297 TI_SCI_PD_EXCLUSIVE>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x00 0x04e00000 0x00 0x04e00000 0x00 0x30000>; - - dmas = <&main_udmap 0xca40>, <&main_udmap 0x4a40>, - <&main_udmap 0x4a41>; - dma-names = "tx", "rx1", "rx2"; - - rng: rng@4e10000 { - compatible = "inside-secure,safexcel-eip76"; - reg = <0x00 0x04e10000 0x00 0x7d>; - interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; - }; - }; - - main_timer0: timer@2400000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2400000 0x00 0x400>; - interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 63 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 63 1>; - assigned-clock-parents = <&k3_clks 63 2>; - power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer1: timer@2410000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2410000 0x00 0x400>; - interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 64 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 64 1>; - assigned-clock-parents = <&k3_clks 64 2>; - power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer2: timer@2420000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2420000 0x00 0x400>; - interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 65 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 65 1>; - assigned-clock-parents = <&k3_clks 65 2>; - power-domains = <&k3_pds 65 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer3: timer@2430000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2430000 0x00 0x400>; - interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 66 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 66 1>; - assigned-clock-parents = <&k3_clks 66 2>; - power-domains = <&k3_pds 66 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer4: timer@2440000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2440000 0x00 0x400>; - interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 67 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 67 1>; - assigned-clock-parents = <&k3_clks 67 2>; - power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer5: timer@2450000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2450000 0x00 0x400>; - interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 68 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 68 1>; - assigned-clock-parents = <&k3_clks 68 2>; - power-domains = <&k3_pds 68 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer6: timer@2460000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2460000 0x00 0x400>; - interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 69 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 69 1>; - assigned-clock-parents = <&k3_clks 69 2>; - power-domains = <&k3_pds 69 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer7: timer@2470000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2470000 0x00 0x400>; - interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 70 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 70 1>; - assigned-clock-parents = <&k3_clks 70 2>; - power-domains = <&k3_pds 70 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer8: timer@2480000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2480000 0x00 0x400>; - interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 71 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 71 1>; - assigned-clock-parents = <&k3_clks 71 2>; - power-domains = <&k3_pds 71 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer9: timer@2490000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2490000 0x00 0x400>; - interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 72 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 72 1>; - assigned-clock-parents = <&k3_clks 72 2>; - power-domains = <&k3_pds 72 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer10: timer@24a0000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x24a0000 0x00 0x400>; - interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 73 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 73 1>; - assigned-clock-parents = <&k3_clks 73 2>; - power-domains = <&k3_pds 73 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer11: timer@24b0000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x24b0000 0x00 0x400>; - interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 74 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 74 1>; - assigned-clock-parents = <&k3_clks 74 2>; - power-domains = <&k3_pds 74 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer12: timer@24c0000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x24c0000 0x00 0x400>; - interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 75 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 75 1>; - assigned-clock-parents = <&k3_clks 75 2>; - power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer13: timer@24d0000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x24d0000 0x00 0x400>; - interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 76 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 76 1>; - assigned-clock-parents = <&k3_clks 76 2>; - power-domains = <&k3_pds 76 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer14: timer@24e0000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x24e0000 0x00 0x400>; - interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 77 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 77 1>; - assigned-clock-parents = <&k3_clks 77 2>; - power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer15: timer@24f0000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x24f0000 0x00 0x400>; - interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 78 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 78 1>; - assigned-clock-parents = <&k3_clks 78 2>; - power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer16: timer@2500000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2500000 0x00 0x400>; - interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 79 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 79 1>; - assigned-clock-parents = <&k3_clks 79 2>; - power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer17: timer@2510000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2510000 0x00 0x400>; - interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 80 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 80 1>; - assigned-clock-parents = <&k3_clks 80 2>; - power-domains = <&k3_pds 80 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer18: timer@2520000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2520000 0x00 0x400>; - interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 81 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 81 1>; - assigned-clock-parents = <&k3_clks 81 2>; - power-domains = <&k3_pds 81 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer19: timer@2530000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2530000 0x00 0x400>; - interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 82 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 82 1>; - assigned-clock-parents = <&k3_clks 82 2>; - power-domains = <&k3_pds 82 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_uart0: serial@2800000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02800000 0x00 0x200>; - interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; - current-speed = <115200>; - clocks = <&k3_clks 146 3>; - clock-names = "fclk"; - power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - main_uart1: serial@2810000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02810000 0x00 0x200>; - interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; - current-speed = <115200>; - clocks = <&k3_clks 350 3>; - clock-names = "fclk"; - power-domains = <&k3_pds 350 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - main_uart2: serial@2820000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02820000 0x00 0x200>; - interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; - current-speed = <115200>; - clocks = <&k3_clks 351 3>; - clock-names = "fclk"; - power-domains = <&k3_pds 351 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - main_uart3: serial@2830000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02830000 0x00 0x200>; - interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; - current-speed = <115200>; - clocks = <&k3_clks 352 3>; - clock-names = "fclk"; - power-domains = <&k3_pds 352 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - main_uart4: serial@2840000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02840000 0x00 0x200>; - interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; - current-speed = <115200>; - clocks = <&k3_clks 353 3>; - clock-names = "fclk"; - power-domains = <&k3_pds 353 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - main_uart5: serial@2850000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02850000 0x00 0x200>; - interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; - current-speed = <115200>; - clocks = <&k3_clks 354 3>; - clock-names = "fclk"; - power-domains = <&k3_pds 354 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - main_uart6: serial@2860000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02860000 0x00 0x200>; - interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; - current-speed = <115200>; - clocks = <&k3_clks 355 3>; - clock-names = "fclk"; - power-domains = <&k3_pds 355 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - main_uart7: serial@2870000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02870000 0x00 0x200>; - interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; - current-speed = <115200>; - clocks = <&k3_clks 356 3>; - clock-names = "fclk"; - power-domains = <&k3_pds 356 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - main_uart8: serial@2880000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02880000 0x00 0x200>; - interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; - current-speed = <115200>; - clocks = <&k3_clks 357 3>; - clock-names = "fclk"; - power-domains = <&k3_pds 357 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - main_uart9: serial@2890000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02890000 0x00 0x200>; - interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; - current-speed = <115200>; - clocks = <&k3_clks 358 3>; - clock-names = "fclk"; - power-domains = <&k3_pds 358 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - main_gpio0: gpio@600000 { - compatible = "ti,j721e-gpio", "ti,keystone-gpio"; - reg = <0x00 0x00600000 0x00 0x100>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&main_gpio_intr>; - interrupts = <145>, <146>, <147>, <148>, <149>; - interrupt-controller; - #interrupt-cells = <2>; - ti,ngpio = <66>; - ti,davinci-gpio-unbanked = <0>; - power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 111 0>; - clock-names = "gpio"; - status = "disabled"; - }; - - main_gpio2: gpio@610000 { - compatible = "ti,j721e-gpio", "ti,keystone-gpio"; - reg = <0x00 0x00610000 0x00 0x100>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&main_gpio_intr>; - interrupts = <154>, <155>, <156>, <157>, <158>; - interrupt-controller; - #interrupt-cells = <2>; - ti,ngpio = <66>; - ti,davinci-gpio-unbanked = <0>; - power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 112 0>; - clock-names = "gpio"; - status = "disabled"; - }; - - main_gpio4: gpio@620000 { - compatible = "ti,j721e-gpio", "ti,keystone-gpio"; - reg = <0x00 0x00620000 0x00 0x100>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&main_gpio_intr>; - interrupts = <163>, <164>, <165>, <166>, <167>; - interrupt-controller; - #interrupt-cells = <2>; - ti,ngpio = <66>; - ti,davinci-gpio-unbanked = <0>; - power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 113 0>; - clock-names = "gpio"; - status = "disabled"; - }; - - main_gpio6: gpio@630000 { - compatible = "ti,j721e-gpio", "ti,keystone-gpio"; - reg = <0x00 0x00630000 0x00 0x100>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&main_gpio_intr>; - interrupts = <172>, <173>, <174>, <175>, <176>; - interrupt-controller; - #interrupt-cells = <2>; - ti,ngpio = <66>; - ti,davinci-gpio-unbanked = <0>; - power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 114 0>; - clock-names = "gpio"; - status = "disabled"; - }; - - main_i2c0: i2c@2000000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x00 0x02000000 0x00 0x100>; - interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&k3_clks 214 1>; - clock-names = "fck"; - power-domains = <&k3_pds 214 TI_SCI_PD_EXCLUSIVE>; - }; - - main_i2c1: i2c@2010000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x00 0x02010000 0x00 0x100>; - interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&k3_clks 215 1>; - clock-names = "fck"; - power-domains = <&k3_pds 215 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - main_i2c2: i2c@2020000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x00 0x02020000 0x00 0x100>; - interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&k3_clks 216 1>; - clock-names = "fck"; - power-domains = <&k3_pds 216 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - main_i2c3: i2c@2030000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x00 0x02030000 0x00 0x100>; - interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&k3_clks 217 1>; - clock-names = "fck"; - power-domains = <&k3_pds 217 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - main_i2c4: i2c@2040000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x00 0x02040000 0x00 0x100>; - interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&k3_clks 218 1>; - clock-names = "fck"; - power-domains = <&k3_pds 218 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - main_i2c5: i2c@2050000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x00 0x02050000 0x00 0x100>; - interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&k3_clks 219 1>; - clock-names = "fck"; - power-domains = <&k3_pds 219 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - main_i2c6: i2c@2060000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x00 0x02060000 0x00 0x100>; - interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&k3_clks 220 1>; - clock-names = "fck"; - power-domains = <&k3_pds 220 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - main_sdhci0: mmc@4f80000 { - compatible = "ti,j721e-sdhci-8bit"; - reg = <0x00 0x04f80000 0x00 0x1000>, - <0x00 0x04f88000 0x00 0x400>; - interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; - power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 98 7>, <&k3_clks 98 1>; - clock-names = "clk_ahb", "clk_xin"; - assigned-clocks = <&k3_clks 98 1>; - assigned-clock-parents = <&k3_clks 98 2>; - bus-width = <8>; - ti,otap-del-sel-legacy = <0x0>; - ti,otap-del-sel-mmc-hs = <0x0>; - ti,otap-del-sel-ddr52 = <0x6>; - ti,otap-del-sel-hs200 = <0x8>; - ti,otap-del-sel-hs400 = <0x5>; - ti,itap-del-sel-legacy = <0x10>; - ti,itap-del-sel-mmc-hs = <0xa>; - ti,strobe-sel = <0x77>; - ti,clkbuf-sel = <0x7>; - ti,trm-icp = <0x8>; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - mmc-hs400-1_8v; - dma-coherent; - status = "disabled"; - }; - - main_sdhci1: mmc@4fb0000 { - compatible = "ti,j721e-sdhci-4bit"; - reg = <0x00 0x04fb0000 0x00 0x1000>, - <0x00 0x04fb8000 0x00 0x400>; - interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; - power-domains = <&k3_pds 99 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 99 8>, <&k3_clks 99 1>; - clock-names = "clk_ahb", "clk_xin"; - assigned-clocks = <&k3_clks 99 1>; - assigned-clock-parents = <&k3_clks 99 2>; - bus-width = <4>; - ti,otap-del-sel-legacy = <0x0>; - ti,otap-del-sel-sd-hs = <0x0>; - ti,otap-del-sel-sdr12 = <0xf>; - ti,otap-del-sel-sdr25 = <0xf>; - ti,otap-del-sel-sdr50 = <0xc>; - ti,otap-del-sel-sdr104 = <0x5>; - ti,otap-del-sel-ddr50 = <0xc>; - ti,itap-del-sel-legacy = <0x0>; - ti,itap-del-sel-sd-hs = <0x0>; - ti,itap-del-sel-sdr12 = <0x0>; - ti,itap-del-sel-sdr25 = <0x0>; - ti,clkbuf-sel = <0x7>; - ti,trm-icp = <0x8>; - dma-coherent; - /* Masking support for SDR104 capability */ - sdhci-caps-mask = <0x00000003 0x00000000>; - status = "disabled"; - }; - - main_navss: bus@30000000 { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>; - ti,sci-dev-id = <224>; - dma-coherent; - dma-ranges; - - main_navss_intr: interrupt-controller@310e0000 { - compatible = "ti,sci-intr"; - reg = <0x00 0x310e0000 0x00 0x4000>; - ti,intr-trigger-type = <4>; - interrupt-controller; - interrupt-parent = <&gic500>; - #interrupt-cells = <1>; - ti,sci = <&sms>; - ti,sci-dev-id = <227>; - ti,interrupt-ranges = <0 64 64>, - <64 448 64>, - <128 672 64>; - }; - - main_udmass_inta: msi-controller@33d00000 { - compatible = "ti,sci-inta"; - reg = <0x00 0x33d00000 0x00 0x100000>; - interrupt-controller; - #interrupt-cells = <0>; - interrupt-parent = <&main_navss_intr>; - msi-controller; - ti,sci = <&sms>; - ti,sci-dev-id = <265>; - ti,interrupt-ranges = <0 0 256>; - ti,unmapped-event-sources = <&main_bcdma_csi>; - }; - - secure_proxy_main: mailbox@32c00000 { - compatible = "ti,am654-secure-proxy"; - #mbox-cells = <1>; - reg-names = "target_data", "rt", "scfg"; - reg = <0x00 0x32c00000 0x00 0x100000>, - <0x00 0x32400000 0x00 0x100000>, - <0x00 0x32800000 0x00 0x100000>; - interrupt-names = "rx_011"; - interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; - }; - - hwspinlock: spinlock@30e00000 { - compatible = "ti,am654-hwspinlock"; - reg = <0x00 0x30e00000 0x00 0x1000>; - #hwlock-cells = <1>; - }; - - mailbox0_cluster0: mailbox@31f80000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f80000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox0_cluster1: mailbox@31f81000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f81000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox0_cluster2: mailbox@31f82000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f82000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox0_cluster3: mailbox@31f83000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f83000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox0_cluster4: mailbox@31f84000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f84000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox0_cluster5: mailbox@31f85000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f85000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox0_cluster6: mailbox@31f86000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f86000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox0_cluster7: mailbox@31f87000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f87000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox0_cluster8: mailbox@31f88000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f88000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox0_cluster9: mailbox@31f89000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f89000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox0_cluster10: mailbox@31f8a000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f8a000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox0_cluster11: mailbox@31f8b000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f8b000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox1_cluster0: mailbox@31f90000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f90000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox1_cluster1: mailbox@31f91000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f91000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox1_cluster2: mailbox@31f92000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f92000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox1_cluster3: mailbox@31f93000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f93000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox1_cluster4: mailbox@31f94000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f94000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox1_cluster5: mailbox@31f95000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f95000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox1_cluster6: mailbox@31f96000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f96000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox1_cluster7: mailbox@31f97000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f97000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox1_cluster8: mailbox@31f98000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f98000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox1_cluster9: mailbox@31f99000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f99000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox1_cluster10: mailbox@31f9a000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f9a000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox1_cluster11: mailbox@31f9b000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f9b000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - main_ringacc: ringacc@3c000000 { - compatible = "ti,am654-navss-ringacc"; - reg = <0x0 0x3c000000 0x0 0x400000>, - <0x0 0x38000000 0x0 0x400000>, - <0x0 0x31120000 0x0 0x100>, - <0x0 0x33000000 0x0 0x40000>, - <0x0 0x31080000 0x0 0x40000>; - reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; - ti,num-rings = <1024>; - ti,sci-rm-range-gp-rings = <0x1>; - ti,sci = <&sms>; - ti,sci-dev-id = <259>; - msi-parent = <&main_udmass_inta>; - }; - - main_udmap: dma-controller@31150000 { - compatible = "ti,j721e-navss-main-udmap"; - reg = <0x0 0x31150000 0x0 0x100>, - <0x0 0x34000000 0x0 0x80000>, - <0x0 0x35000000 0x0 0x200000>; - reg-names = "gcfg", "rchanrt", "tchanrt"; - msi-parent = <&main_udmass_inta>; - #dma-cells = <1>; - - ti,sci = <&sms>; - ti,sci-dev-id = <263>; - ti,ringacc = <&main_ringacc>; - - ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ - <0x0f>, /* TX_HCHAN */ - <0x10>; /* TX_UHCHAN */ - ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ - <0x0b>, /* RX_HCHAN */ - <0x0c>; /* RX_UHCHAN */ - ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ - }; - - main_bcdma_csi: dma-controller@311a0000 { - compatible = "ti,j721s2-dmss-bcdma-csi"; - reg = <0x00 0x311a0000 0x00 0x100>, - <0x00 0x35d00000 0x00 0x20000>, - <0x00 0x35c00000 0x00 0x10000>, - <0x00 0x35e00000 0x00 0x80000>; - reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt"; - msi-parent = <&main_udmass_inta>; - #dma-cells = <3>; - ti,sci = <&sms>; - ti,sci-dev-id = <225>; - ti,sci-rm-range-rchan = <0x21>; - ti,sci-rm-range-tchan = <0x22>; - status = "disabled"; - }; - - cpts@310d0000 { - compatible = "ti,j721e-cpts"; - reg = <0x0 0x310d0000 0x0 0x400>; - reg-names = "cpts"; - clocks = <&k3_clks 226 5>; - clock-names = "cpts"; - assigned-clocks = <&k3_clks 226 5>; /* NAVSS0_CPTS_0_RCLK */ - assigned-clock-parents = <&k3_clks 226 7>; /* MAIN_0_HSDIVOUT6_CLK */ - interrupts-extended = <&main_navss_intr 391>; - interrupt-names = "cpts"; - ti,cpts-periodic-outputs = <6>; - ti,cpts-ext-ts-inputs = <8>; - }; - }; - - main_cpsw: ethernet@c200000 { - compatible = "ti,j721e-cpsw-nuss"; - reg = <0x00 0xc200000 0x00 0x200000>; - reg-names = "cpsw_nuss"; - ranges = <0x0 0x0 0x0 0xc200000 0x0 0x200000>; - #address-cells = <2>; - #size-cells = <2>; - dma-coherent; - clocks = <&k3_clks 28 28>; - clock-names = "fck"; - power-domains = <&k3_pds 28 TI_SCI_PD_EXCLUSIVE>; - - dmas = <&main_udmap 0xc640>, - <&main_udmap 0xc641>, - <&main_udmap 0xc642>, - <&main_udmap 0xc643>, - <&main_udmap 0xc644>, - <&main_udmap 0xc645>, - <&main_udmap 0xc646>, - <&main_udmap 0xc647>, - <&main_udmap 0x4640>; - dma-names = "tx0", "tx1", "tx2", "tx3", - "tx4", "tx5", "tx6", "tx7", - "rx"; - - status = "disabled"; - - ethernet-ports { - #address-cells = <1>; - #size-cells = <0>; - - main_cpsw_port1: port@1 { - reg = <1>; - ti,mac-only; - label = "port1"; - phys = <&phy_gmii_sel_cpsw 1>; - status = "disabled"; - }; - }; - - main_cpsw_mdio: mdio@f00 { - compatible = "ti,cpsw-mdio","ti,davinci_mdio"; - reg = <0x00 0xf00 0x00 0x100>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&k3_clks 28 28>; - clock-names = "fck"; - bus_freq = <1000000>; - status = "disabled"; - }; - - cpts@3d000 { - compatible = "ti,am65-cpts"; - reg = <0x00 0x3d000 0x00 0x400>; - clocks = <&k3_clks 28 3>; - clock-names = "cpts"; - interrupts-extended = <&gic500 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "cpts"; - ti,cpts-ext-ts-inputs = <4>; - ti,cpts-periodic-outputs = <2>; - }; - }; - - usbss0: cdns-usb@4104000 { - compatible = "ti,j721e-usb"; - reg = <0x00 0x04104000 0x00 0x100>; - clocks = <&k3_clks 360 16>, <&k3_clks 360 15>; - clock-names = "ref", "lpm"; - assigned-clocks = <&k3_clks 360 16>; /* USB2_REFCLK */ - assigned-clock-parents = <&k3_clks 360 17>; - power-domains = <&k3_pds 360 TI_SCI_PD_EXCLUSIVE>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - dma-coherent; - - status = "disabled"; /* Needs pinmux */ - - usb0: usb@6000000 { - compatible = "cdns,usb3"; - reg = <0x00 0x06000000 0x00 0x10000>, - <0x00 0x06010000 0x00 0x10000>, - <0x00 0x06020000 0x00 0x10000>; - reg-names = "otg", "xhci", "dev"; - interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "host", "peripheral", "otg"; - maximum-speed = "super-speed"; - dr_mode = "otg"; - }; - }; - - serdes_wiz0: wiz@5060000 { - compatible = "ti,j721s2-wiz-10g"; - #address-cells = <1>; - #size-cells = <1>; - power-domains = <&k3_pds 365 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 365 0>, <&k3_clks 365 3>, <&serdes_refclk>; - clock-names = "fck", "core_ref_clk", "ext_ref_clk"; - num-lanes = <4>; - #reset-cells = <1>; - #clock-cells = <1>; - ranges = <0x5060000 0x0 0x5060000 0x10000>; - - assigned-clocks = <&k3_clks 365 3>; - assigned-clock-parents = <&k3_clks 365 7>; - - serdes0: serdes@5060000 { - compatible = "ti,j721e-serdes-10g"; - reg = <0x05060000 0x00010000>; - reg-names = "torrent_phy"; - resets = <&serdes_wiz0 0>; - reset-names = "torrent_reset"; - clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, - <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>; - clock-names = "refclk", "phy_en_refclk"; - assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, - <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>, - <&serdes_wiz0 TI_WIZ_REFCLK_DIG>; - assigned-clock-parents = <&k3_clks 365 3>, - <&k3_clks 365 3>, - <&k3_clks 365 3>; - #address-cells = <1>; - #size-cells = <0>; - #clock-cells = <1>; - - status = "disabled"; /* Needs lane config */ - }; - }; - - pcie1_rc: pcie@2910000 { - compatible = "ti,j7200-pcie-host", "ti,j721e-pcie-host"; - reg = <0x00 0x02910000 0x00 0x1000>, - <0x00 0x02917000 0x00 0x400>, - <0x00 0x0d800000 0x00 0x800000>, - <0x00 0x18000000 0x00 0x1000>; - reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; - interrupt-names = "link_state"; - interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>; - device_type = "pci"; - ti,syscon-pcie-ctrl = <&scm_conf 0x074>; - max-link-speed = <3>; - num-lanes = <4>; - power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 276 41>; - clock-names = "fck"; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x0 0xff>; - vendor-id = <0x104c>; - device-id = <0xb013>; - msi-map = <0x0 &gic_its 0x0 0x10000>; - dma-coherent; - ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>, - <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>; - dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie1_intc 0>, /* INT A */ - <0 0 0 2 &pcie1_intc 0>, /* INT B */ - <0 0 0 3 &pcie1_intc 0>, /* INT C */ - <0 0 0 4 &pcie1_intc 0>; /* INT D */ - - status = "disabled"; /* Needs gpio and serdes info */ - - pcie1_intc: interrupt-controller { - interrupt-controller; - #interrupt-cells = <1>; - interrupt-parent = <&gic500>; - interrupts = <GIC_SPI 324 IRQ_TYPE_EDGE_RISING>; - }; - }; - - main_mcan0: can@2701000 { - compatible = "bosch,m_can"; - reg = <0x00 0x02701000 0x00 0x200>, - <0x00 0x02708000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 182 0>, <&k3_clks 182 1>; - clock-names = "hclk", "cclk"; - interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "int0", "int1"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - main_mcan1: can@2711000 { - compatible = "bosch,m_can"; - reg = <0x00 0x02711000 0x00 0x200>, - <0x00 0x02718000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 183 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 183 0>, <&k3_clks 183 1>; - clock-names = "hclk", "cclk"; - interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "int0", "int1"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - main_mcan2: can@2721000 { - compatible = "bosch,m_can"; - reg = <0x00 0x02721000 0x00 0x200>, - <0x00 0x02728000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 184 0>, <&k3_clks 184 1>; - clock-names = "hclk", "cclk"; - interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "int0", "int1"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - main_mcan3: can@2731000 { - compatible = "bosch,m_can"; - reg = <0x00 0x02731000 0x00 0x200>, - <0x00 0x02738000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 185 0>, <&k3_clks 185 1>; - clock-names = "hclk", "cclk"; - interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "int0", "int1"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - main_mcan4: can@2741000 { - compatible = "bosch,m_can"; - reg = <0x00 0x02741000 0x00 0x200>, - <0x00 0x02748000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 186 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 186 0>, <&k3_clks 186 1>; - clock-names = "hclk", "cclk"; - interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "int0", "int1"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - main_mcan5: can@2751000 { - compatible = "bosch,m_can"; - reg = <0x00 0x02751000 0x00 0x200>, - <0x00 0x02758000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 187 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 187 0>, <&k3_clks 187 1>; - clock-names = "hclk", "cclk"; - interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "int0", "int1"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - main_mcan6: can@2761000 { - compatible = "bosch,m_can"; - reg = <0x00 0x02761000 0x00 0x200>, - <0x00 0x02768000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 188 0>, <&k3_clks 188 1>; - clock-names = "hclk", "cclk"; - interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "int0", "int1"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - main_mcan7: can@2771000 { - compatible = "bosch,m_can"; - reg = <0x00 0x02771000 0x00 0x200>, - <0x00 0x02778000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 189 0>, <&k3_clks 189 1>; - clock-names = "hclk", "cclk"; - interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "int0", "int1"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - main_mcan8: can@2781000 { - compatible = "bosch,m_can"; - reg = <0x00 0x02781000 0x00 0x200>, - <0x00 0x02788000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 190 0>, <&k3_clks 190 1>; - clock-names = "hclk", "cclk"; - interrupts = <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "int0", "int1"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - main_mcan9: can@2791000 { - compatible = "bosch,m_can"; - reg = <0x00 0x02791000 0x00 0x200>, - <0x00 0x02798000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 191 0>, <&k3_clks 191 1>; - clock-names = "hclk", "cclk"; - interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "int0", "int1"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - main_mcan10: can@27a1000 { - compatible = "bosch,m_can"; - reg = <0x00 0x027a1000 0x00 0x200>, - <0x00 0x027a8000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 192 0>, <&k3_clks 192 1>; - clock-names = "hclk", "cclk"; - interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "int0", "int1"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - main_mcan11: can@27b1000 { - compatible = "bosch,m_can"; - reg = <0x00 0x027b1000 0x00 0x200>, - <0x00 0x027b8000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 193 0>, <&k3_clks 193 1>; - clock-names = "hclk", "cclk"; - interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "int0", "int1"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - main_mcan12: can@27c1000 { - compatible = "bosch,m_can"; - reg = <0x00 0x027c1000 0x00 0x200>, - <0x00 0x027c8000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 194 0>, <&k3_clks 194 1>; - clock-names = "hclk", "cclk"; - interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "int0", "int1"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - main_mcan13: can@27d1000 { - compatible = "bosch,m_can"; - reg = <0x00 0x027d1000 0x00 0x200>, - <0x00 0x027d8000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 195 0>, <&k3_clks 195 1>; - clock-names = "hclk", "cclk"; - interrupts = <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "int0", "int1"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - main_mcan14: can@2681000 { - compatible = "bosch,m_can"; - reg = <0x00 0x02681000 0x00 0x200>, - <0x00 0x02688000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 197 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 197 0>, <&k3_clks 197 1>; - clock-names = "hclk", "cclk"; - interrupts = <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "int0", "int1"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - main_mcan15: can@2691000 { - compatible = "bosch,m_can"; - reg = <0x00 0x02691000 0x00 0x200>, - <0x00 0x02698000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 199 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 199 0>, <&k3_clks 199 1>; - clock-names = "hclk", "cclk"; - interrupts = <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "int0", "int1"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - main_mcan16: can@26a1000 { - compatible = "bosch,m_can"; - reg = <0x00 0x026a1000 0x00 0x200>, - <0x00 0x026a8000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 201 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 201 0>, <&k3_clks 201 1>; - clock-names = "hclk", "cclk"; - interrupts = <GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "int0", "int1"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - main_mcan17: can@26b1000 { - compatible = "bosch,m_can"; - reg = <0x00 0x026b1000 0x00 0x200>, - <0x00 0x026b8000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 206 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 206 0>, <&k3_clks 206 1>; - clock-names = "hclk", "cclk"; - interrupts = <GIC_SPI 787 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 788 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "int0", "int1"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - main_spi0: spi@2100000 { - compatible = "ti,am654-mcspi","ti,omap4-mcspi"; - reg = <0x00 0x02100000 0x00 0x400>; - interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 339 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 339 1>; - status = "disabled"; - }; - - main_spi1: spi@2110000 { - compatible = "ti,am654-mcspi","ti,omap4-mcspi"; - reg = <0x00 0x02110000 0x00 0x400>; - interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 340 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 340 1>; - status = "disabled"; - }; - - main_spi2: spi@2120000 { - compatible = "ti,am654-mcspi","ti,omap4-mcspi"; - reg = <0x00 0x02120000 0x00 0x400>; - interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 341 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 341 1>; - status = "disabled"; - }; - - main_spi3: spi@2130000 { - compatible = "ti,am654-mcspi","ti,omap4-mcspi"; - reg = <0x00 0x02130000 0x00 0x400>; - interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 342 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 342 1>; - status = "disabled"; - }; - - main_spi4: spi@2140000 { - compatible = "ti,am654-mcspi","ti,omap4-mcspi"; - reg = <0x00 0x02140000 0x00 0x400>; - interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 343 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 343 1>; - status = "disabled"; - }; - - main_spi5: spi@2150000 { - compatible = "ti,am654-mcspi","ti,omap4-mcspi"; - reg = <0x00 0x02150000 0x00 0x400>; - interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 344 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 344 1>; - status = "disabled"; - }; - - main_spi6: spi@2160000 { - compatible = "ti,am654-mcspi","ti,omap4-mcspi"; - reg = <0x00 0x02160000 0x00 0x400>; - interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 345 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 345 1>; - status = "disabled"; - }; - - main_spi7: spi@2170000 { - compatible = "ti,am654-mcspi","ti,omap4-mcspi"; - reg = <0x00 0x02170000 0x00 0x400>; - interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 346 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 346 1>; - status = "disabled"; - }; - - dss: dss@4a00000 { - compatible = "ti,j721e-dss"; - reg = <0x00 0x04a00000 0x00 0x10000>, /* common_m */ - <0x00 0x04a10000 0x00 0x10000>, /* common_s0*/ - <0x00 0x04b00000 0x00 0x10000>, /* common_s1*/ - <0x00 0x04b10000 0x00 0x10000>, /* common_s2*/ - <0x00 0x04a20000 0x00 0x10000>, /* vidl1 */ - <0x00 0x04a30000 0x00 0x10000>, /* vidl2 */ - <0x00 0x04a50000 0x00 0x10000>, /* vid1 */ - <0x00 0x04a60000 0x00 0x10000>, /* vid2 */ - <0x00 0x04a70000 0x00 0x10000>, /* ovr1 */ - <0x00 0x04a90000 0x00 0x10000>, /* ovr2 */ - <0x00 0x04ab0000 0x00 0x10000>, /* ovr3 */ - <0x00 0x04ad0000 0x00 0x10000>, /* ovr4 */ - <0x00 0x04a80000 0x00 0x10000>, /* vp1 */ - <0x00 0x04aa0000 0x00 0x10000>, /* vp2 */ - <0x00 0x04ac0000 0x00 0x10000>, /* vp3 */ - <0x00 0x04ae0000 0x00 0x10000>, /* vp4 */ - <0x00 0x04af0000 0x00 0x10000>; /* wb */ - reg-names = "common_m", "common_s0", - "common_s1", "common_s2", - "vidl1", "vidl2","vid1","vid2", - "ovr1", "ovr2", "ovr3", "ovr4", - "vp1", "vp2", "vp3", "vp4", - "wb"; - clocks = <&k3_clks 158 0>, - <&k3_clks 158 2>, - <&k3_clks 158 5>, - <&k3_clks 158 14>, - <&k3_clks 158 18>; - clock-names = "fck", "vp1", "vp2", "vp3", "vp4"; - power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>; - interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "common_m", - "common_s0", - "common_s1", - "common_s2"; - status = "disabled"; - - dss_ports: ports { - }; - }; - - main_r5fss0: r5fss@5c00000 { - compatible = "ti,j721s2-r5fss"; - ti,cluster-mode = <1>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x5c00000 0x00 0x5c00000 0x20000>, - <0x5d00000 0x00 0x5d00000 0x20000>; - power-domains = <&k3_pds 277 TI_SCI_PD_EXCLUSIVE>; - - main_r5fss0_core0: r5f@5c00000 { - compatible = "ti,j721s2-r5f"; - reg = <0x5c00000 0x00010000>, - <0x5c10000 0x00010000>; - reg-names = "atcm", "btcm"; - ti,sci = <&sms>; - ti,sci-dev-id = <279>; - ti,sci-proc-ids = <0x06 0xff>; - resets = <&k3_reset 279 1>; - firmware-name = "j721s2-main-r5f0_0-fw"; - ti,atcm-enable = <1>; - ti,btcm-enable = <1>; - ti,loczrama = <1>; - }; - - main_r5fss0_core1: r5f@5d00000 { - compatible = "ti,j721s2-r5f"; - reg = <0x5d00000 0x00010000>, - <0x5d10000 0x00010000>; - reg-names = "atcm", "btcm"; - ti,sci = <&sms>; - ti,sci-dev-id = <280>; - ti,sci-proc-ids = <0x07 0xff>; - resets = <&k3_reset 280 1>; - firmware-name = "j721s2-main-r5f0_1-fw"; - ti,atcm-enable = <1>; - ti,btcm-enable = <1>; - ti,loczrama = <1>; - }; - }; - - main_r5fss1: r5fss@5e00000 { - compatible = "ti,j721s2-r5fss"; - ti,cluster-mode = <1>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x5e00000 0x00 0x5e00000 0x20000>, - <0x5f00000 0x00 0x5f00000 0x20000>; - power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>; - - main_r5fss1_core0: r5f@5e00000 { - compatible = "ti,j721s2-r5f"; - reg = <0x5e00000 0x00010000>, - <0x5e10000 0x00010000>; - reg-names = "atcm", "btcm"; - ti,sci = <&sms>; - ti,sci-dev-id = <281>; - ti,sci-proc-ids = <0x08 0xff>; - resets = <&k3_reset 281 1>; - firmware-name = "j721s2-main-r5f1_0-fw"; - ti,atcm-enable = <1>; - ti,btcm-enable = <1>; - ti,loczrama = <1>; - }; - - main_r5fss1_core1: r5f@5f00000 { - compatible = "ti,j721s2-r5f"; - reg = <0x5f00000 0x00010000>, - <0x5f10000 0x00010000>; - reg-names = "atcm", "btcm"; - ti,sci = <&sms>; - ti,sci-dev-id = <282>; - ti,sci-proc-ids = <0x09 0xff>; - resets = <&k3_reset 282 1>; - firmware-name = "j721s2-main-r5f1_1-fw"; - ti,atcm-enable = <1>; - ti,btcm-enable = <1>; - ti,loczrama = <1>; - }; - }; - - c71_0: dsp@64800000 { - compatible = "ti,j721s2-c71-dsp"; - reg = <0x00 0x64800000 0x00 0x00080000>, - <0x00 0x64e00000 0x00 0x0000c000>; - reg-names = "l2sram", "l1dram"; - ti,sci = <&sms>; - ti,sci-dev-id = <8>; - ti,sci-proc-ids = <0x30 0xff>; - resets = <&k3_reset 8 1>; - firmware-name = "j721s2-c71_0-fw"; - status = "disabled"; - }; - - c71_1: dsp@65800000 { - compatible = "ti,j721s2-c71-dsp"; - reg = <0x00 0x65800000 0x00 0x00080000>, - <0x00 0x65e00000 0x00 0x0000c000>; - reg-names = "l2sram", "l1dram"; - ti,sci = <&sms>; - ti,sci-dev-id = <11>; - ti,sci-proc-ids = <0x31 0xff>; - resets = <&k3_reset 11 1>; - firmware-name = "j721s2-c71_1-fw"; - status = "disabled"; - }; - - main_esm: esm@700000 { - compatible = "ti,j721e-esm"; - reg = <0x00 0x700000 0x00 0x1000>; - ti,esm-pins = <688>, <689>; - bootph-pre-ram; - }; - - watchdog0: watchdog@2200000 { - compatible = "ti,j7-rti-wdt"; - reg = <0x00 0x2200000 0x00 0x100>; - clocks = <&k3_clks 286 1>; - power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>; - assigned-clocks = <&k3_clks 286 1>; - assigned-clock-parents = <&k3_clks 286 5>; - }; - - watchdog1: watchdog@2210000 { - compatible = "ti,j7-rti-wdt"; - reg = <0x00 0x2210000 0x00 0x100>; - clocks = <&k3_clks 287 1>; - power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>; - assigned-clocks = <&k3_clks 287 1>; - assigned-clock-parents = <&k3_clks 287 5>; - }; - - /* - * The following RTI instances are coupled with MCU R5Fs, c7x and - * GPU so keeping them reserved as these will be used by their - * respective firmware - */ - watchdog2: watchdog@22f0000 { - compatible = "ti,j7-rti-wdt"; - reg = <0x00 0x22f0000 0x00 0x100>; - clocks = <&k3_clks 290 1>; - power-domains = <&k3_pds 290 TI_SCI_PD_EXCLUSIVE>; - assigned-clocks = <&k3_clks 290 1>; - assigned-clock-parents = <&k3_clks 290 5>; - /* reserved for GPU */ - status = "reserved"; - }; - - watchdog3: watchdog@2300000 { - compatible = "ti,j7-rti-wdt"; - reg = <0x00 0x2300000 0x00 0x100>; - clocks = <&k3_clks 288 1>; - power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>; - assigned-clocks = <&k3_clks 288 1>; - assigned-clock-parents = <&k3_clks 288 5>; - /* reserved for C7X_0 */ - status = "reserved"; - }; - - watchdog4: watchdog@2310000 { - compatible = "ti,j7-rti-wdt"; - reg = <0x00 0x2310000 0x00 0x100>; - clocks = <&k3_clks 289 1>; - power-domains = <&k3_pds 289 TI_SCI_PD_EXCLUSIVE>; - assigned-clocks = <&k3_clks 289 1>; - assigned-clock-parents = <&k3_clks 289 5>; - /* reserved for C7X_1 */ - status = "reserved"; - }; - - watchdog5: watchdog@23c0000 { - compatible = "ti,j7-rti-wdt"; - reg = <0x00 0x23c0000 0x00 0x100>; - clocks = <&k3_clks 291 1>; - power-domains = <&k3_pds 291 TI_SCI_PD_EXCLUSIVE>; - assigned-clocks = <&k3_clks 291 1>; - assigned-clock-parents = <&k3_clks 291 5>; - /* reserved for MAIN_R5F0_0 */ - status = "reserved"; - }; - - watchdog6: watchdog@23d0000 { - compatible = "ti,j7-rti-wdt"; - reg = <0x00 0x23d0000 0x00 0x100>; - clocks = <&k3_clks 292 1>; - power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>; - assigned-clocks = <&k3_clks 292 1>; - assigned-clock-parents = <&k3_clks 292 5>; - /* reserved for MAIN_R5F0_1 */ - status = "reserved"; - }; - - watchdog7: watchdog@23e0000 { - compatible = "ti,j7-rti-wdt"; - reg = <0x00 0x23e0000 0x00 0x100>; - clocks = <&k3_clks 293 1>; - power-domains = <&k3_pds 293 TI_SCI_PD_EXCLUSIVE>; - assigned-clocks = <&k3_clks 293 1>; - assigned-clock-parents = <&k3_clks 293 5>; - /* reserved for MAIN_R5F1_0 */ - status = "reserved"; - }; - - watchdog8: watchdog@23f0000 { - compatible = "ti,j7-rti-wdt"; - reg = <0x00 0x23f0000 0x00 0x100>; - clocks = <&k3_clks 294 1>; - power-domains = <&k3_pds 294 TI_SCI_PD_EXCLUSIVE>; - assigned-clocks = <&k3_clks 294 1>; - assigned-clock-parents = <&k3_clks 294 5>; - /* reserved for MAIN_R5F1_1 */ - status = "reserved"; - }; -}; diff --git a/arch/arm/dts/k3-j721s2-mcu-wakeup.dtsi b/arch/arm/dts/k3-j721s2-mcu-wakeup.dtsi deleted file mode 100644 index 7254f3b..0000000 --- a/arch/arm/dts/k3-j721s2-mcu-wakeup.dtsi +++ /dev/null @@ -1,738 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for J721S2 SoC Family MCU/WAKEUP Domain peripherals - * - * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ - */ - -&cbass_mcu_wakeup { - sms: system-controller@44083000 { - compatible = "ti,k2g-sci"; - ti,host-id = <12>; - - mbox-names = "rx", "tx"; - - mboxes = <&secure_proxy_main 11>, - <&secure_proxy_main 13>; - - reg-names = "debug_messages"; - reg = <0x00 0x44083000 0x00 0x1000>; - - k3_pds: power-controller { - compatible = "ti,sci-pm-domain"; - #power-domain-cells = <2>; - }; - - k3_clks: clock-controller { - compatible = "ti,k2g-sci-clk"; - #clock-cells = <2>; - }; - - k3_reset: reset-controller { - compatible = "ti,sci-reset"; - #reset-cells = <2>; - }; - }; - - chipid@43000014 { - compatible = "ti,am654-chipid"; - reg = <0x00 0x43000014 0x00 0x4>; - }; - - secure_proxy_sa3: mailbox@43600000 { - compatible = "ti,am654-secure-proxy"; - #mbox-cells = <1>; - reg-names = "target_data", "rt", "scfg"; - reg = <0x00 0x43600000 0x00 0x10000>, - <0x00 0x44880000 0x00 0x20000>, - <0x00 0x44860000 0x00 0x20000>; - /* - * Marked Disabled: - * Node is incomplete as it is meant for bootloaders and - * firmware on non-MPU processors - */ - status = "disabled"; - }; - - mcu_ram: sram@41c00000 { - compatible = "mmio-sram"; - reg = <0x00 0x41c00000 0x00 0x100000>; - ranges = <0x00 0x00 0x41c00000 0x100000>; - #address-cells = <1>; - #size-cells = <1>; - }; - - wkup_pmx0: pinctrl@4301c000 { - compatible = "pinctrl-single"; - /* Proxy 0 addressing */ - reg = <0x00 0x4301c000 0x00 0x034>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0xffffffff>; - }; - - wkup_pmx1: pinctrl@4301c038 { - compatible = "pinctrl-single"; - /* Proxy 0 addressing */ - reg = <0x00 0x4301c038 0x00 0x02C>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0xffffffff>; - }; - - wkup_pmx2: pinctrl@4301c068 { - compatible = "pinctrl-single"; - /* Proxy 0 addressing */ - reg = <0x00 0x4301c068 0x00 0x120>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0xffffffff>; - }; - - wkup_pmx3: pinctrl@4301c190 { - compatible = "pinctrl-single"; - /* Proxy 0 addressing */ - reg = <0x00 0x4301c190 0x00 0x004>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0xffffffff>; - }; - - /* MCU_TIMERIO pad input CTRLMMR_MCU_TIMER*_CTRL registers */ - mcu_timerio_input: pinctrl@40f04200 { - compatible = "pinctrl-single"; - reg = <0x00 0x40f04200 0x00 0x28>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0x0000000f>; - /* Non-MPU Firmware usage */ - status = "reserved"; - }; - - /* MCU_TIMERIO pad output CTRLMMR_MCU_TIMERIO*_CTRL registers */ - mcu_timerio_output: pinctrl@40f04280 { - compatible = "pinctrl-single"; - reg = <0x00 0x40f04280 0x00 0x28>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0x0000000f>; - /* Non-MPU Firmware usage */ - status = "reserved"; - }; - - wkup_gpio_intr: interrupt-controller@42200000 { - compatible = "ti,sci-intr"; - reg = <0x00 0x42200000 0x00 0x400>; - ti,intr-trigger-type = <1>; - interrupt-controller; - interrupt-parent = <&gic500>; - #interrupt-cells = <1>; - ti,sci = <&sms>; - ti,sci-dev-id = <125>; - ti,interrupt-ranges = <16 960 16>; - }; - - mcu_conf: syscon@40f00000 { - compatible = "syscon", "simple-mfd"; - reg = <0x0 0x40f00000 0x0 0x20000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x40f00000 0x20000>; - - phy_gmii_sel: phy@4040 { - compatible = "ti,am654-phy-gmii-sel"; - reg = <0x4040 0x4>; - #phy-cells = <1>; - }; - - }; - - mcu_timer0: timer@40400000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x40400000 0x00 0x400>; - interrupts = <GIC_SPI 816 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 35 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 35 1>; - assigned-clock-parents = <&k3_clks 35 2>; - power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - /* Non-MPU Firmware usage */ - status = "reserved"; - }; - - mcu_timer1: timer@40410000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x40410000 0x00 0x400>; - interrupts = <GIC_SPI 817 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 83 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 83 1>; - assigned-clock-parents = <&k3_clks 83 2>; - power-domains = <&k3_pds 83 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - /* Non-MPU Firmware usage */ - status = "reserved"; - }; - - mcu_timer2: timer@40420000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x40420000 0x00 0x400>; - interrupts = <GIC_SPI 818 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 84 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 84 1>; - assigned-clock-parents = <&k3_clks 84 2>; - power-domains = <&k3_pds 84 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - /* Non-MPU Firmware usage */ - status = "reserved"; - }; - - mcu_timer3: timer@40430000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x40430000 0x00 0x400>; - interrupts = <GIC_SPI 819 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 85 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 85 1>; - assigned-clock-parents = <&k3_clks 85 2>; - power-domains = <&k3_pds 85 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - /* Non-MPU Firmware usage */ - status = "reserved"; - }; - - mcu_timer4: timer@40440000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x40440000 0x00 0x400>; - interrupts = <GIC_SPI 820 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 86 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 86 1>; - assigned-clock-parents = <&k3_clks 86 2>; - power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - /* Non-MPU Firmware usage */ - status = "reserved"; - }; - - mcu_timer5: timer@40450000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x40450000 0x00 0x400>; - interrupts = <GIC_SPI 821 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 87 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 87 1>; - assigned-clock-parents = <&k3_clks 87 2>; - power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - /* Non-MPU Firmware usage */ - status = "reserved"; - }; - - mcu_timer6: timer@40460000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x40460000 0x00 0x400>; - interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 88 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 88 1>; - assigned-clock-parents = <&k3_clks 88 2>; - power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - /* Non-MPU Firmware usage */ - status = "reserved"; - }; - - mcu_timer7: timer@40470000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x40470000 0x00 0x400>; - interrupts = <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 89 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 89 1>; - assigned-clock-parents = <&k3_clks 89 2>; - power-domains = <&k3_pds 89 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - /* Non-MPU Firmware usage */ - status = "reserved"; - }; - - mcu_timer8: timer@40480000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x40480000 0x00 0x400>; - interrupts = <GIC_SPI 824 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 90 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 90 1>; - assigned-clock-parents = <&k3_clks 90 2>; - power-domains = <&k3_pds 90 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - /* Non-MPU Firmware usage */ - status = "reserved"; - }; - - mcu_timer9: timer@40490000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x40490000 0x00 0x400>; - interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 91 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 91 1>; - assigned-clock-parents = <&k3_clks 91 2>; - power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - /* Non-MPU Firmware usage */ - status = "reserved"; - }; - - wkup_uart0: serial@42300000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x42300000 0x00 0x200>; - interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>; - current-speed = <115200>; - clocks = <&k3_clks 359 3>; - clock-names = "fclk"; - power-domains = <&k3_pds 359 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - mcu_uart0: serial@40a00000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x40a00000 0x00 0x200>; - interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>; - current-speed = <115200>; - clocks = <&k3_clks 149 3>; - clock-names = "fclk"; - power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - wkup_gpio0: gpio@42110000 { - compatible = "ti,j721e-gpio", "ti,keystone-gpio"; - reg = <0x00 0x42110000 0x00 0x100>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&wkup_gpio_intr>; - interrupts = <103>, <104>, <105>, <106>, <107>, <108>; - interrupt-controller; - #interrupt-cells = <2>; - ti,ngpio = <89>; - ti,davinci-gpio-unbanked = <0>; - power-domains = <&k3_pds 115 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 115 0>; - clock-names = "gpio"; - status = "disabled"; - }; - - wkup_gpio1: gpio@42100000 { - compatible = "ti,j721e-gpio", "ti,keystone-gpio"; - reg = <0x00 0x42100000 0x00 0x100>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&wkup_gpio_intr>; - interrupts = <112>, <113>, <114>, <115>, <116>, <117>; - interrupt-controller; - #interrupt-cells = <2>; - ti,ngpio = <89>; - ti,davinci-gpio-unbanked = <0>; - power-domains = <&k3_pds 116 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 116 0>; - clock-names = "gpio"; - status = "disabled"; - }; - - wkup_i2c0: i2c@42120000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x00 0x42120000 0x00 0x100>; - interrupts = <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&k3_clks 223 1>; - clock-names = "fck"; - power-domains = <&k3_pds 223 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - mcu_i2c0: i2c@40b00000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x00 0x40b00000 0x00 0x100>; - interrupts = <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&k3_clks 221 1>; - clock-names = "fck"; - power-domains = <&k3_pds 221 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - mcu_i2c1: i2c@40b10000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x00 0x40b10000 0x00 0x100>; - interrupts = <GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&k3_clks 222 1>; - clock-names = "fck"; - power-domains = <&k3_pds 222 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - mcu_mcan0: can@40528000 { - compatible = "bosch,m_can"; - reg = <0x00 0x40528000 0x00 0x200>, - <0x00 0x40500000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 207 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 207 0>, <&k3_clks 207 1>; - clock-names = "hclk", "cclk"; - interrupts = <GIC_SPI 832 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "int0", "int1"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - mcu_mcan1: can@40568000 { - compatible = "bosch,m_can"; - reg = <0x00 0x40568000 0x00 0x200>, - <0x00 0x40540000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 208 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 208 0>, <&k3_clks 208 1>; - clock-names = "hclk", "cclk"; - interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "int0", "int1"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - mcu_spi0: spi@40300000 { - compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; - reg = <0x00 0x040300000 0x00 0x400>; - interrupts = <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 347 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 347 0>; - status = "disabled"; - }; - - mcu_spi1: spi@40310000 { - compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; - reg = <0x00 0x040310000 0x00 0x400>; - interrupts = <GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 348 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 348 0>; - status = "disabled"; - }; - - mcu_spi2: spi@40320000 { - compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; - reg = <0x00 0x040320000 0x00 0x400>; - interrupts = <GIC_SPI 850 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 349 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 349 0>; - status = "disabled"; - }; - - mcu_navss: bus@28380000 { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>; - dma-coherent; - dma-ranges; - - ti,sci-dev-id = <267>; - - mcu_ringacc: ringacc@2b800000 { - compatible = "ti,am654-navss-ringacc"; - reg = <0x0 0x2b800000 0x0 0x400000>, - <0x0 0x2b000000 0x0 0x400000>, - <0x0 0x28590000 0x0 0x100>, - <0x0 0x2a500000 0x0 0x40000>, - <0x0 0x28440000 0x0 0x40000>; - reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; - ti,num-rings = <286>; - ti,sci-rm-range-gp-rings = <0x1>; - ti,sci = <&sms>; - ti,sci-dev-id = <272>; - msi-parent = <&main_udmass_inta>; - }; - - mcu_udmap: dma-controller@285c0000 { - compatible = "ti,j721e-navss-mcu-udmap"; - reg = <0x0 0x285c0000 0x0 0x100>, - <0x0 0x2a800000 0x0 0x40000>, - <0x0 0x2aa00000 0x0 0x40000>; - reg-names = "gcfg", "rchanrt", "tchanrt"; - msi-parent = <&main_udmass_inta>; - #dma-cells = <1>; - - ti,sci = <&sms>; - ti,sci-dev-id = <273>; - ti,ringacc = <&mcu_ringacc>; - ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ - <0x0f>; /* TX_HCHAN */ - ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ - <0x0b>; /* RX_HCHAN */ - ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ - }; - }; - - secure_proxy_mcu: mailbox@2a480000 { - compatible = "ti,am654-secure-proxy"; - #mbox-cells = <1>; - reg-names = "target_data", "rt", "scfg"; - reg = <0x00 0x2a480000 0x00 0x80000>, - <0x00 0x2a380000 0x00 0x80000>, - <0x00 0x2a400000 0x00 0x80000>; - /* - * Marked Disabled: - * Node is incomplete as it is meant for bootloaders and - * firmware on non-MPU processors - */ - status = "disabled"; - }; - - mcu_cpsw: ethernet@46000000 { - compatible = "ti,j721e-cpsw-nuss"; - #address-cells = <2>; - #size-cells = <2>; - reg = <0x0 0x46000000 0x0 0x200000>; - reg-names = "cpsw_nuss"; - ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>; - dma-coherent; - clocks = <&k3_clks 29 28>; - clock-names = "fck"; - power-domains = <&k3_pds 29 TI_SCI_PD_EXCLUSIVE>; - - dmas = <&mcu_udmap 0xf000>, - <&mcu_udmap 0xf001>, - <&mcu_udmap 0xf002>, - <&mcu_udmap 0xf003>, - <&mcu_udmap 0xf004>, - <&mcu_udmap 0xf005>, - <&mcu_udmap 0xf006>, - <&mcu_udmap 0xf007>, - <&mcu_udmap 0x7000>; - dma-names = "tx0", "tx1", "tx2", "tx3", - "tx4", "tx5", "tx6", "tx7", - "rx"; - - ethernet-ports { - #address-cells = <1>; - #size-cells = <0>; - - cpsw_port1: port@1 { - reg = <1>; - ti,mac-only; - label = "port1"; - ti,syscon-efuse = <&mcu_conf 0x200>; - phys = <&phy_gmii_sel 1>; - }; - }; - - davinci_mdio: mdio@f00 { - compatible = "ti,cpsw-mdio","ti,davinci_mdio"; - reg = <0x0 0xf00 0x0 0x100>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&k3_clks 29 28>; - clock-names = "fck"; - bus_freq = <1000000>; - }; - - cpts@3d000 { - compatible = "ti,am65-cpts"; - reg = <0x0 0x3d000 0x0 0x400>; - clocks = <&k3_clks 29 3>; - clock-names = "cpts"; - assigned-clocks = <&k3_clks 29 3>; /* CPTS_RFT_CLK */ - assigned-clock-parents = <&k3_clks 29 5>; /* MAIN_0_HSDIVOUT6_CLK */ - interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "cpts"; - ti,cpts-ext-ts-inputs = <4>; - ti,cpts-periodic-outputs = <2>; - }; - }; - - tscadc0: tscadc@40200000 { - compatible = "ti,am3359-tscadc"; - reg = <0x00 0x40200000 0x00 0x1000>; - interrupts = <GIC_SPI 860 IRQ_TYPE_LEVEL_HIGH>; - power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 0 0>; - assigned-clocks = <&k3_clks 0 2>; - assigned-clock-rates = <60000000>; - clock-names = "fck"; - dmas = <&main_udmap 0x7400>, - <&main_udmap 0x7401>; - dma-names = "fifo0", "fifo1"; - status = "disabled"; - - adc { - #io-channel-cells = <1>; - compatible = "ti,am3359-adc"; - }; - }; - - tscadc1: tscadc@40210000 { - compatible = "ti,am3359-tscadc"; - reg = <0x00 0x40210000 0x00 0x1000>; - interrupts = <GIC_SPI 861 IRQ_TYPE_LEVEL_HIGH>; - power-domains = <&k3_pds 1 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 1 0>; - assigned-clocks = <&k3_clks 1 2>; - assigned-clock-rates = <60000000>; - clock-names = "fck"; - dmas = <&main_udmap 0x7402>, - <&main_udmap 0x7403>; - dma-names = "fifo0", "fifo1"; - status = "disabled"; - - adc { - #io-channel-cells = <1>; - compatible = "ti,am3359-adc"; - }; - }; - - fss: bus@47000000 { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, - <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, - <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; - - ospi0: spi@47040000 { - compatible = "ti,am654-ospi", "cdns,qspi-nor"; - reg = <0x00 0x47040000 0x00 0x100>, - <0x05 0x00000000 0x01 0x00000000>; - interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>; - cdns,fifo-depth = <256>; - cdns,fifo-width = <4>; - cdns,trigger-address = <0x0>; - clocks = <&k3_clks 109 5>; - assigned-clocks = <&k3_clks 109 5>; - assigned-clock-parents = <&k3_clks 109 7>; - assigned-clock-rates = <166666666>; - power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>; - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; /* Needs pinmux */ - }; - - ospi1: spi@47050000 { - compatible = "ti,am654-ospi", "cdns,qspi-nor"; - reg = <0x00 0x47050000 0x00 0x100>, - <0x07 0x00000000 0x01 0x00000000>; - interrupts = <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>; - cdns,fifo-depth = <256>; - cdns,fifo-width = <4>; - cdns,trigger-address = <0x0>; - clocks = <&k3_clks 110 5>; - power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>; - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; /* Needs pinmux */ - }; - }; - - wkup_vtm0: temperature-sensor@42040000 { - compatible = "ti,j7200-vtm"; - reg = <0x00 0x42040000 0x0 0x350>, - <0x00 0x42050000 0x0 0x350>; - power-domains = <&k3_pds 154 TI_SCI_PD_SHARED>; - #thermal-sensor-cells = <1>; - }; - - mcu_r5fss0: r5fss@41000000 { - compatible = "ti,j721s2-r5fss"; - ti,cluster-mode = <1>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x41000000 0x00 0x41000000 0x20000>, - <0x41400000 0x00 0x41400000 0x20000>; - power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>; - - mcu_r5fss0_core0: r5f@41000000 { - compatible = "ti,j721s2-r5f"; - reg = <0x41000000 0x00010000>, - <0x41010000 0x00010000>; - reg-names = "atcm", "btcm"; - ti,sci = <&sms>; - ti,sci-dev-id = <284>; - ti,sci-proc-ids = <0x01 0xff>; - resets = <&k3_reset 284 1>; - firmware-name = "j721s2-mcu-r5f0_0-fw"; - ti,atcm-enable = <1>; - ti,btcm-enable = <1>; - ti,loczrama = <1>; - }; - - mcu_r5fss0_core1: r5f@41400000 { - compatible = "ti,j721s2-r5f"; - reg = <0x41400000 0x00010000>, - <0x41410000 0x00010000>; - reg-names = "atcm", "btcm"; - ti,sci = <&sms>; - ti,sci-dev-id = <285>; - ti,sci-proc-ids = <0x02 0xff>; - resets = <&k3_reset 285 1>; - firmware-name = "j721s2-mcu-r5f0_1-fw"; - ti,atcm-enable = <1>; - ti,btcm-enable = <1>; - ti,loczrama = <1>; - }; - }; - - mcu_esm: esm@40800000 { - compatible = "ti,j721e-esm"; - reg = <0x00 0x40800000 0x00 0x1000>; - ti,esm-pins = <95>; - bootph-pre-ram; - }; - - wkup_esm: esm@42080000 { - compatible = "ti,j721e-esm"; - reg = <0x00 0x42080000 0x00 0x1000>; - ti,esm-pins = <63>; - bootph-pre-ram; - }; - - /* - * The 2 RTI instances are couple with MCU R5Fs so keeping them - * reserved as these will be used by their respective firmware - */ - mcu_watchdog0: watchdog@40600000 { - compatible = "ti,j7-rti-wdt"; - reg = <0x00 0x40600000 0x00 0x100>; - clocks = <&k3_clks 295 1>; - power-domains = <&k3_pds 295 TI_SCI_PD_EXCLUSIVE>; - assigned-clocks = <&k3_clks 295 1>; - assigned-clock-parents = <&k3_clks 295 5>; - /* reserved for MCU_R5F0_0 */ - status = "reserved"; - }; - - mcu_watchdog1: watchdog@40610000 { - compatible = "ti,j7-rti-wdt"; - reg = <0x00 0x40610000 0x00 0x100>; - clocks = <&k3_clks 296 1>; - power-domains = <&k3_pds 296 TI_SCI_PD_EXCLUSIVE>; - assigned-clocks = <&k3_clks 296 1>; - assigned-clock-parents = <&k3_clks 296 5>; - /* reserved for MCU_R5F0_1 */ - status = "reserved"; - }; -}; diff --git a/arch/arm/dts/k3-j721s2-r5-common-proc-board.dts b/arch/arm/dts/k3-j721s2-r5-common-proc-board.dts index 03bd680..e92b191 100644 --- a/arch/arm/dts/k3-j721s2-r5-common-proc-board.dts +++ b/arch/arm/dts/k3-j721s2-r5-common-proc-board.dts @@ -9,80 +9,4 @@ #include "k3-j721s2-ddr-evm-lp4-4266.dtsi" #include "k3-j721s2-ddr.dtsi" #include "k3-j721s2-common-proc-board-u-boot.dtsi" - -/ { - chosen { - tick-timer = &mcu_timer0; - }; - - aliases { - remoteproc0 = &sysctrler; - remoteproc1 = &a72_0; - }; - - a72_0: a72@0 { - compatible = "ti,am654-rproc"; - reg = <0x0 0x00a90000 0x0 0x10>; - power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>, - <&k3_pds 202 TI_SCI_PD_EXCLUSIVE>, - <&k3_pds 4 TI_SCI_PD_EXCLUSIVE>; - resets = <&k3_reset 202 0>; - clocks = <&k3_clks 61 1>; - assigned-clocks = <&k3_clks 61 1>, <&k3_clks 202 0>; - assigned-clock-parents = <&k3_clks 61 2>; - assigned-clock-rates = <200000000>, <2000000000>; - ti,sci = <&sms>; - ti,sci-proc-id = <32>; - ti,sci-host-id = <10>; - bootph-pre-ram; - }; - - dm_tifs: dm-tifs { - compatible = "ti,j721e-dm-sci"; - ti,host-id = <3>; - ti,secure-host; - mbox-names = "rx", "tx"; - mboxes= <&secure_proxy_mcu 21>, - <&secure_proxy_mcu 23>; - bootph-pre-ram; - }; -}; - -&mcu_timer0 { - clock-frequency = <250000000>; - bootph-pre-ram; -}; - -&secure_proxy_sa3 { - bootph-pre-ram; - status = "okay"; -}; - -&secure_proxy_mcu { - bootph-pre-ram; - status = "okay"; -}; - -&cbass_mcu_wakeup { - sysctrler: sysctrler { - compatible = "ti,am654-system-controller"; - mboxes= <&secure_proxy_mcu 4>, <&secure_proxy_mcu 5>, <&secure_proxy_sa3 5>; - mbox-names = "tx", "rx", "boot_notify"; - bootph-pre-ram; - }; -}; - -&sms { - mboxes= <&secure_proxy_mcu 8>, <&secure_proxy_mcu 6>, <&secure_proxy_mcu 5>; - mbox-names = "tx", "rx", "notify"; - ti,host-id = <4>; - ti,secure-host; -}; - -&mcu_ringacc { - ti,sci = <&dm_tifs>; -}; - -&mcu_udmap { - ti,sci = <&dm_tifs>; -}; +#include "k3-j721s2-r5.dtsi" diff --git a/arch/arm/dts/k3-j721s2-r5.dtsi b/arch/arm/dts/k3-j721s2-r5.dtsi new file mode 100644 index 0000000..eb0df42 --- /dev/null +++ b/arch/arm/dts/k3-j721s2-r5.dtsi @@ -0,0 +1,81 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/ { + chosen { + tick-timer = &mcu_timer0; + }; + + aliases { + remoteproc0 = &sysctrler; + remoteproc1 = &a72_0; + }; + + a72_0: a72@0 { + compatible = "ti,am654-rproc"; + reg = <0x0 0x00a90000 0x0 0x10>; + power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>, + <&k3_pds 202 TI_SCI_PD_EXCLUSIVE>, + <&k3_pds 4 TI_SCI_PD_EXCLUSIVE>; + resets = <&k3_reset 202 0>; + clocks = <&k3_clks 61 1>; + assigned-clocks = <&k3_clks 61 1>, <&k3_clks 202 0>; + assigned-clock-parents = <&k3_clks 61 2>; + assigned-clock-rates = <200000000>, <2000000000>; + ti,sci = <&sms>; + ti,sci-proc-id = <32>; + ti,sci-host-id = <10>; + bootph-pre-ram; + }; + + dm_tifs: dm-tifs { + compatible = "ti,j721e-dm-sci"; + ti,host-id = <3>; + ti,secure-host; + mbox-names = "rx", "tx"; + mboxes= <&secure_proxy_mcu 21>, + <&secure_proxy_mcu 23>; + bootph-pre-ram; + }; +}; + +&mcu_timer0 { + clock-frequency = <250000000>; + bootph-pre-ram; +}; + +&secure_proxy_sa3 { + bootph-pre-ram; + status = "okay"; +}; + +&secure_proxy_mcu { + bootph-pre-ram; + status = "okay"; +}; + +&cbass_mcu_wakeup { + sysctrler: sysctrler { + compatible = "ti,am654-system-controller"; + mboxes= <&secure_proxy_mcu 4>, <&secure_proxy_mcu 5>, <&secure_proxy_sa3 5>; + mbox-names = "tx", "rx", "boot_notify"; + bootph-pre-ram; + }; +}; + +&sms { + mboxes= <&secure_proxy_mcu 8>, <&secure_proxy_mcu 6>, <&secure_proxy_mcu 5>; + mbox-names = "tx", "rx", "notify"; + ti,host-id = <4>; + ti,secure-host; +}; + +&mcu_ringacc { + ti,sci = <&dm_tifs>; +}; + +&mcu_udmap { + ti,sci = <&dm_tifs>; +}; diff --git a/arch/arm/dts/k3-j721s2-som-p0.dtsi b/arch/arm/dts/k3-j721s2-som-p0.dtsi deleted file mode 100644 index dcad372..0000000 --- a/arch/arm/dts/k3-j721s2-som-p0.dtsi +++ /dev/null @@ -1,361 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * SoM: https://www.ti.com/lit/zip/sprr439 - * - * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ - */ - -/dts-v1/; - -#include "k3-j721s2.dtsi" -#include <dt-bindings/gpio/gpio.h> - -/ { - memory@80000000 { - device_type = "memory"; - /* 16 GB RAM */ - reg = <0x00 0x80000000 0x00 0x80000000>, - <0x08 0x80000000 0x03 0x80000000>; - }; - - /* Reserving memory regions still pending */ - reserved_memory: reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - secure_ddr: optee@9e800000 { - reg = <0x00 0x9e800000 0x00 0x01800000>; - alignment = <0x1000>; - no-map; - }; - - mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa0000000 0x00 0x100000>; - no-map; - }; - - mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa0100000 0x00 0xf00000>; - no-map; - }; - - mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa1000000 0x00 0x100000>; - no-map; - }; - - mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa1100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa2000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core0_memory_region: r5f-memory@a2100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa2100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa3000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core1_memory_region: r5f-memory@a3100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa3100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa4000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core0_memory_region: r5f-memory@a4100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa4100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa5000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core1_memory_region: r5f-memory@a5100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa5100000 0x00 0xf00000>; - no-map; - }; - - c71_0_dma_memory_region: c71-dma-memory@a6000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa6000000 0x00 0x100000>; - no-map; - }; - - c71_0_memory_region: c71-memory@a6100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa6100000 0x00 0xf00000>; - no-map; - }; - - c71_1_dma_memory_region: c71-dma-memory@a7000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa7000000 0x00 0x100000>; - no-map; - }; - - c71_1_memory_region: c71-memory@a7100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa7100000 0x00 0xf00000>; - no-map; - }; - - rtos_ipc_memory_region: ipc-memories@a8000000 { - reg = <0x00 0xa8000000 0x00 0x01c00000>; - alignment = <0x1000>; - no-map; - }; - }; - - mux0: mux-controller { - compatible = "gpio-mux"; - #mux-state-cells = <1>; - mux-gpios = <&exp_som 1 GPIO_ACTIVE_HIGH>; - }; - - mux1: mux-controller { - compatible = "gpio-mux"; - #mux-state-cells = <1>; - mux-gpios = <&exp_som 2 GPIO_ACTIVE_HIGH>; - }; - - transceiver0: can-phy0 { - /* standby pin has been grounded by default */ - compatible = "ti,tcan1042"; - #phy-cells = <0>; - max-bitrate = <5000000>; - }; -}; - -&wkup_pmx0 { - mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins { - pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (D19) MCU_OSPI0_CLK */ - J721S2_WKUP_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F15) MCU_OSPI0_CSn0 */ - J721S2_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (C19) MCU_OSPI0_D0 */ - J721S2_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (F16) MCU_OSPI0_D1 */ - J721S2_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (G15) MCU_OSPI0_D2 */ - J721S2_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (F18) MCU_OSPI0_D3 */ - J721S2_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (E19) MCU_OSPI0_D4 */ - J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (G19) MCU_OSPI0_D5 */ - J721S2_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (F19) MCU_OSPI0_D6 */ - J721S2_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (F20) MCU_OSPI0_D7 */ - J721S2_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (E18) MCU_OSPI0_DQS */ - J721S2_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (E20) MCU_OSPI0_LBCLKO */ - >; - }; -}; - -&wkup_pmx2 { - wkup_i2c0_pins_default: wkup-i2c0-default-pins { - pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x98, PIN_INPUT, 0) /* (H24) WKUP_I2C0_SCL */ - J721S2_WKUP_IOPAD(0x9c, PIN_INPUT, 0) /* (H27) WKUP_I2C0_SDA */ - >; - }; -}; - -&main_pmx0 { - main_i2c0_pins_default: main-i2c0-default-pins { - pinctrl-single,pins = < - J721S2_IOPAD(0x0e0, PIN_INPUT_PULLUP, 0) /* (AH25) I2C0_SCL */ - J721S2_IOPAD(0x0e4, PIN_INPUT_PULLUP, 0) /* (AE24) I2C0_SDA */ - >; - }; - - main_mcan16_pins_default: main-mcan16-default-pins { - pinctrl-single,pins = < - J721S2_IOPAD(0x028, PIN_INPUT, 0) /* (AB24) MCAN16_RX */ - J721S2_IOPAD(0x024, PIN_OUTPUT, 0) /* (Y28) MCAN16_TX */ - >; - }; -}; - -&wkup_i2c0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&wkup_i2c0_pins_default>; - clock-frequency = <400000>; - - eeprom@50 { - /* CAV24C256WE-GT3 */ - compatible = "atmel,24c256"; - reg = <0x50>; - }; -}; - -&main_i2c0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_i2c0_pins_default>; - clock-frequency = <400000>; - - exp_som: gpio@21 { - compatible = "ti,tca6408"; - reg = <0x21>; - gpio-controller; - #gpio-cells = <2>; - gpio-line-names = "USB2.0_MUX_SEL", "CANUART_MUX1_SEL0", - "CANUART_MUX2_SEL0", "CANUART_MUX_SEL1", - "GPIO_RGMII1_RST", "GPIO_eDP_ENABLE", - "GPIO_LIN_EN", "CAN_STB"; - }; -}; - -&main_mcan16 { - status = "okay"; - pinctrl-0 = <&main_mcan16_pins_default>; - pinctrl-names = "default"; - phys = <&transceiver0>; -}; - -&ospi0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0x0>; - spi-tx-bus-width = <8>; - spi-rx-bus-width = <8>; - spi-max-frequency = <25000000>; - cdns,tshsl-ns = <60>; - cdns,tsd2d-ns = <60>; - cdns,tchsh-ns = <60>; - cdns,tslch-ns = <60>; - cdns,read-delay = <4>; - }; -}; - -&mailbox0_cluster0 { - status = "okay"; - interrupts = <436>; - mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster1 { - status = "okay"; - interrupts = <432>; - mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster2 { - status = "okay"; - interrupts = <428>; - mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster4 { - status = "okay"; - interrupts = <420>; - mbox_c71_0: mbox-c71-0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_c71_1: mbox-c71-1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mcu_r5fss0_core0 { - mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>; - memory-region = <&mcu_r5fss0_core0_dma_memory_region>, - <&mcu_r5fss0_core0_memory_region>; -}; - -&mcu_r5fss0_core1 { - mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>; - memory-region = <&mcu_r5fss0_core1_dma_memory_region>, - <&mcu_r5fss0_core1_memory_region>; -}; - -&main_r5fss0_core0 { - mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>; - memory-region = <&main_r5fss0_core0_dma_memory_region>, - <&main_r5fss0_core0_memory_region>; -}; - -&main_r5fss0_core1 { - mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>; - memory-region = <&main_r5fss0_core1_dma_memory_region>, - <&main_r5fss0_core1_memory_region>; -}; - -&main_r5fss1_core0 { - mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core0>; - memory-region = <&main_r5fss1_core0_dma_memory_region>, - <&main_r5fss1_core0_memory_region>; -}; - -&main_r5fss1_core1 { - mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core1>; - memory-region = <&main_r5fss1_core1_dma_memory_region>, - <&main_r5fss1_core1_memory_region>; -}; - -&c71_0 { - status = "okay"; - mboxes = <&mailbox0_cluster4>, <&mbox_c71_0>; - memory-region = <&c71_0_dma_memory_region>, - <&c71_0_memory_region>; -}; - -&c71_1 { - status = "okay"; - mboxes = <&mailbox0_cluster4>, <&mbox_c71_1>; - memory-region = <&c71_1_dma_memory_region>, - <&c71_1_memory_region>; -}; diff --git a/arch/arm/dts/k3-j721s2-thermal.dtsi b/arch/arm/dts/k3-j721s2-thermal.dtsi deleted file mode 100644 index f7b1a15..0000000 --- a/arch/arm/dts/k3-j721s2-thermal.dtsi +++ /dev/null @@ -1,101 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -#include <dt-bindings/thermal/thermal.h> - -wkup0_thermal: wkup0-thermal { - polling-delay-passive = <250>; /* milliseconds */ - polling-delay = <500>; /* milliseconds */ - thermal-sensors = <&wkup_vtm0 0>; - - trips { - wkup0_crit: wkup0-crit { - temperature = <125000>; /* milliCelsius */ - hysteresis = <2000>; /* milliCelsius */ - type = "critical"; - }; - }; -}; - -wkup1_thermal: wkup1-thermal { - polling-delay-passive = <250>; /* milliseconds */ - polling-delay = <500>; /* milliseconds */ - thermal-sensors = <&wkup_vtm0 1>; - - trips { - wkup1_crit: wkup1-crit { - temperature = <125000>; /* milliCelsius */ - hysteresis = <2000>; /* milliCelsius */ - type = "critical"; - }; - }; -}; - -main0_thermal: main0-thermal { - polling-delay-passive = <250>; /* milliseconds */ - polling-delay = <500>; /* milliseconds */ - thermal-sensors = <&wkup_vtm0 2>; - - trips { - main0_crit: main0-crit { - temperature = <125000>; /* milliCelsius */ - hysteresis = <2000>; /* milliCelsius */ - type = "critical"; - }; - }; -}; - -main1_thermal: main1-thermal { - polling-delay-passive = <250>; /* milliseconds */ - polling-delay = <500>; /* milliseconds */ - thermal-sensors = <&wkup_vtm0 3>; - - trips { - main1_crit: main1-crit { - temperature = <125000>; /* milliCelsius */ - hysteresis = <2000>; /* milliCelsius */ - type = "critical"; - }; - }; -}; - -main2_thermal: main2-thermal { - polling-delay-passive = <250>; /* milliseconds */ - polling-delay = <500>; /* milliseconds */ - thermal-sensors = <&wkup_vtm0 4>; - - trips { - main2_crit: main2-crit { - temperature = <125000>; /* milliCelsius */ - hysteresis = <2000>; /* milliCelsius */ - type = "critical"; - }; - }; -}; - -main3_thermal: main3-thermal { - polling-delay-passive = <250>; /* milliseconds */ - polling-delay = <500>; /* milliseconds */ - thermal-sensors = <&wkup_vtm0 5>; - - trips { - main3_crit: main3-crit { - temperature = <125000>; /* milliCelsius */ - hysteresis = <2000>; /* milliCelsius */ - type = "critical"; - }; - }; -}; - -main4_thermal: main4-thermal { - polling-delay-passive = <250>; /* milliseconds */ - polling-delay = <500>; /* milliseconds */ - thermal-sensors = <&wkup_vtm0 6>; - - trips { - main4_crit: main4-crit { - temperature = <125000>; /* milliCelsius */ - hysteresis = <2000>; /* milliCelsius */ - type = "critical"; - }; - }; -}; diff --git a/arch/arm/dts/k3-j721s2.dtsi b/arch/arm/dts/k3-j721s2.dtsi deleted file mode 100644 index 1f636ac..0000000 --- a/arch/arm/dts/k3-j721s2.dtsi +++ /dev/null @@ -1,175 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for J721S2 SoC Family - * - * TRM (SPRUJ28 NOVEMBER 2021): https://www.ti.com/lit/pdf/spruj28 - * - * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ - * - */ - -#include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/soc/ti,sci_pm_domain.h> - -#include "k3-pinctrl.h" - -/ { - - model = "Texas Instruments K3 J721S2 SoC"; - compatible = "ti,j721s2"; - interrupt-parent = <&gic500>; - #address-cells = <2>; - #size-cells = <2>; - - chosen { }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - cpu-map { - cluster0: cluster0 { - core0 { - cpu = <&cpu0>; - }; - - core1 { - cpu = <&cpu1>; - }; - }; - }; - - cpu0: cpu@0 { - compatible = "arm,cortex-a72"; - reg = <0x000>; - device_type = "cpu"; - enable-method = "psci"; - i-cache-size = <0xc000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&L2_0>; - }; - - cpu1: cpu@1 { - compatible = "arm,cortex-a72"; - reg = <0x001>; - device_type = "cpu"; - enable-method = "psci"; - i-cache-size = <0xc000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&L2_0>; - }; - }; - - L2_0: l2-cache0 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - cache-size = <0x100000>; - cache-line-size = <64>; - cache-sets = <1024>; - next-level-cache = <&msmc_l3>; - }; - - msmc_l3: l3-cache0 { - compatible = "cache"; - cache-level = <3>; - cache-unified; - }; - - firmware { - optee { - compatible = "linaro,optee-tz"; - method = "smc"; - }; - - psci: psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - }; - - a72_timer0: timer-cl0-cpu0 { - compatible = "arm,armv8-timer"; - interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */ - <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */ - <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */ - <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */ - - }; - - pmu: pmu { - compatible = "arm,cortex-a72-pmu"; - /* Recommendation from GIC500 TRM Table A.3 */ - interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; - }; - - cbass_main: bus@100000 { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */ - <0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */ - <0x00 0x01000000 0x00 0x01000000 0x00 0x0d000000>, /* Most peripherals */ - <0x00 0x0d800000 0x00 0x0d800000 0x00 0x00800000>, /* PCIe Core*/ - <0x00 0x18000000 0x00 0x18000000 0x00 0x08000000>, /* PCIe1 DAT0 */ - <0x00 0x64800000 0x00 0x64800000 0x00 0x0070c000>, /* C71_1 */ - <0x00 0x65800000 0x00 0x65800000 0x00 0x0070c000>, /* C71_2 */ - <0x00 0x6f000000 0x00 0x6f000000 0x00 0x00310000>, /* A72 PERIPHBASE */ - <0x00 0x70000000 0x00 0x70000000 0x00 0x00400000>, /* MSMC RAM */ - <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */ - <0x41 0x00000000 0x41 0x00000000 0x01 0x00000000>, /* PCIe1 DAT1 */ - <0x4e 0x20000000 0x4e 0x20000000 0x00 0x00080000>, /* GPU */ - - /* MCUSS_WKUP Range */ - <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, - <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, - <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, - <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, - <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, - <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, - <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, - <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, - <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, - <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, - <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, - <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, - <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; - - cbass_mcu_wakeup: bus@28380000 { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/ - <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, /* First peripheral window */ - <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */ - <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */ - <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */ - <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, /* MCU SRAM */ - <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP peripheral window */ - <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */ - <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */ - <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI register space */ - <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, /* FSS OSPI0/1 data region 0 */ - <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS OSPI0 data region 3 */ - <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; /* FSS OSPI1 data region 3*/ - - }; - - }; - - thermal_zones: thermal-zones { - #include "k3-j721s2-thermal.dtsi" - }; -}; - -/* Now include peripherals from each bus segment */ -#include "k3-j721s2-main.dtsi" -#include "k3-j721s2-mcu-wakeup.dtsi" diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 43f7503..7e30cac 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -69,8 +69,10 @@ /* * CNTHCTL_EL2 bits definitions */ -#define CNTHCTL_EL2_EL1PCEN_EN (1 << 1) /* Physical timer regs accessible */ -#define CNTHCTL_EL2_EL1PCTEN_EN (1 << 0) /* Physical counter accessible */ +#define CNTHCTL_EL2_EVNT_EN BIT(2) /* Enable the event stream */ +#define CNTHCTL_EL2_EVNT_I(val) ((val) << 4) /* Event stream trigger bits */ +#define CNTHCTL_EL2_EL1PCEN_EN (1 << 1) /* Physical timer regs accessible */ +#define CNTHCTL_EL2_EL1PCTEN_EN (1 << 0) /* Physical counter accessible */ /* * HCR_EL2 bits definitions @@ -154,6 +156,13 @@ enum dcache_option { "wfi" : : : "memory"); \ }) +#define wfe() \ + ({asm volatile( \ + "wfe" : : : "memory"); \ + }) + +#define sev() asm volatile("sev") + static inline unsigned int current_el(void) { unsigned long el; @@ -369,6 +378,8 @@ void switch_to_hypervisor_ret(void); #ifdef __ARM_ARCH_7A__ #define wfi() __asm__ __volatile__ ("wfi" : : : "memory") +#define wfe() __asm__ __volatile__ ("wfe" : : : "memory") +#define sev() __asm__ __volatile__ ("sev") #else #define wfi() #endif diff --git a/arch/arm/mach-exynos/include/mach/system.h b/arch/arm/mach-exynos/include/mach/system.h index 5d0beba..0aed4c3 100644 --- a/arch/arm/mach-exynos/include/mach/system.h +++ b/arch/arm/mach-exynos/include/mach/system.h @@ -36,25 +36,6 @@ struct exynos5_sysreg { #define USB20_PHY_CFG_HOST_LINK_EN (1 << 0) -/* - * This instruction causes an event to be signaled to all cores - * within a multiprocessor system. If SEV is implemented, - * WFE must also be implemented. - */ -#define sev() __asm__ __volatile__ ("sev\n\t" : : ); -/* - * If the Event Register is not set, WFE suspends execution until - * one of the following events occurs: - * - an IRQ interrupt, unless masked by the CPSR I-bit - * - an FIQ interrupt, unless masked by the CPSR F-bit - * - an Imprecise Data abort, unless masked by the CPSR A-bit - * - a Debug Entry request, if Debug is enabled - * - an Event signaled by another processor using the SEV instruction. - * If the Event Register is set, WFE clears it and returns immediately. - * If WFE is implemented, SEV must also be implemented. - */ -#define wfe() __asm__ __volatile__ ("wfe\n\t" : : ); - /* Move 0xd3 value to CPSR register to enable SVC mode */ #define svc32_mode_en() __asm__ __volatile__ \ ("@ I&F disable, Mode: 0x13 - SVC\n\t" \ diff --git a/arch/arm/mach-k3/Makefile b/arch/arm/mach-k3/Makefile index 3101f57..2b3ebd5 100644 --- a/arch/arm/mach-k3/Makefile +++ b/arch/arm/mach-k3/Makefile @@ -6,24 +6,12 @@ obj-$(CONFIG_ARM64) += arm64/ obj-$(CONFIG_CPU_V7R) += r5/ obj-$(CONFIG_OF_LIBFDT) += common_fdt.o -ifeq ($(CONFIG_OF_LIBFDT)$(CONFIG_OF_SYSTEM_SETUP),yy) -obj-$(CONFIG_SOC_K3_AM654) += am654_fdt.o -obj-$(CONFIG_SOC_K3_J721E) += j721e_fdt.o -obj-$(CONFIG_SOC_K3_J721S2) += j721s2_fdt.o -obj-$(CONFIG_SOC_K3_AM625) += am625_fdt.o -obj-$(CONFIG_SOC_K3_AM62A7) += am62a7_fdt.o -obj-$(CONFIG_SOC_K3_J784S4) += j784s4_fdt.o -endif -ifeq ($(CONFIG_SPL_BUILD),y) -obj-$(CONFIG_SOC_K3_AM654) += am654_init.o -obj-$(CONFIG_SOC_K3_J721E) += j721e_init.o -obj-$(CONFIG_SOC_K3_J721S2) += j721s2_init.o -obj-$(CONFIG_SOC_K3_AM642) += am642_init.o -obj-$(CONFIG_SOC_K3_AM625) += am625_init.o -obj-$(CONFIG_SOC_K3_AM62A7) += am62a7_init.o -obj-$(CONFIG_SOC_K3_J784S4) += j784s4_init.o -obj-$(CONFIG_SOC_K3_AM62P5) += am62p5_init.o -endif obj-y += common.o security.o +obj-$(CONFIG_SOC_K3_AM62A7) += am62ax/ +obj-$(CONFIG_SOC_K3_AM62P5) += am62px/ obj-$(CONFIG_SOC_K3_AM625) += am62x/ obj-$(CONFIG_SOC_K3_AM642) += am64x/ +obj-$(CONFIG_SOC_K3_AM654) += am65x/ +obj-$(CONFIG_SOC_K3_J721E) += j721e/ +obj-$(CONFIG_SOC_K3_J721S2) += j721s2/ +obj-$(CONFIG_SOC_K3_J784S4) += j784s4/ diff --git a/arch/arm/mach-k3/am62ax/Makefile b/arch/arm/mach-k3/am62ax/Makefile new file mode 100644 index 0000000..1717ca3 --- /dev/null +++ b/arch/arm/mach-k3/am62ax/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ +# Andrew Davis <afd@ti.com> + +obj-$(CONFIG_OF_SYSTEM_SETUP) += am62a7_fdt.o +obj-$(CONFIG_SPL_BUILD) += am62a7_init.o diff --git a/arch/arm/mach-k3/am62a7_fdt.c b/arch/arm/mach-k3/am62ax/am62a7_fdt.c index d67f012..7f764ab 100644 --- a/arch/arm/mach-k3/am62a7_fdt.c +++ b/arch/arm/mach-k3/am62ax/am62a7_fdt.c @@ -4,9 +4,10 @@ */ #include <asm/hardware.h> -#include "common_fdt.h" #include <fdt_support.h> +#include "../common_fdt.h" + int ft_system_setup(void *blob, struct bd_info *bd) { fdt_fixup_reserved(blob, "tfa", CONFIG_K3_ATF_LOAD_ADDR, 0x80000); diff --git a/arch/arm/mach-k3/am62a7_init.c b/arch/arm/mach-k3/am62ax/am62a7_init.c index 658828c..0f62f39 100644 --- a/arch/arm/mach-k3/am62a7_init.c +++ b/arch/arm/mach-k3/am62ax/am62a7_init.c @@ -8,12 +8,13 @@ #include <spl.h> #include <asm/io.h> #include <asm/arch/hardware.h> -#include "sysfw-loader.h" -#include "common.h" #include <dm.h> #include <dm/uclass-internal.h> #include <dm/pinctrl.h> +#include "../sysfw-loader.h" +#include "../common.h" + struct fwl_data cbass_main_fwls[] = { { "FSS_DAT_REG3", 7, 8 }, }; diff --git a/arch/arm/mach-k3/am62px/Makefile b/arch/arm/mach-k3/am62px/Makefile new file mode 100644 index 0000000..5902862 --- /dev/null +++ b/arch/arm/mach-k3/am62px/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ +# Andrew Davis <afd@ti.com> + +obj-$(CONFIG_SPL_BUILD) += am62p5_init.o diff --git a/arch/arm/mach-k3/am62p5_init.c b/arch/arm/mach-k3/am62px/am62p5_init.c index aab99aa..34ed01c 100644 --- a/arch/arm/mach-k3/am62p5_init.c +++ b/arch/arm/mach-k3/am62px/am62p5_init.c @@ -8,12 +8,13 @@ #include <spl.h> #include <asm/io.h> #include <asm/arch/hardware.h> -#include "sysfw-loader.h" -#include "common.h" #include <dm.h> #include <dm/uclass-internal.h> #include <dm/pinctrl.h> +#include "../sysfw-loader.h" +#include "../common.h" + struct fwl_data cbass_main_fwls[] = { { "FSS_DAT_REG3", 7, 8 }, }; diff --git a/arch/arm/mach-k3/am62x/Makefile b/arch/arm/mach-k3/am62x/Makefile index acf09c3..8494cdd 100644 --- a/arch/arm/mach-k3/am62x/Makefile +++ b/arch/arm/mach-k3/am62x/Makefile @@ -1,2 +1,5 @@ # SPDX-License-Identifier: GPL-2.0+ + +obj-$(CONFIG_OF_SYSTEM_SETUP) += am625_fdt.o +obj-$(CONFIG_SPL_BUILD) += am625_init.o obj-y += boot.o diff --git a/arch/arm/mach-k3/am625_fdt.c b/arch/arm/mach-k3/am62x/am625_fdt.c index c56adef..8fe200a 100644 --- a/arch/arm/mach-k3/am625_fdt.c +++ b/arch/arm/mach-k3/am62x/am625_fdt.c @@ -4,9 +4,10 @@ */ #include <asm/hardware.h> -#include "common_fdt.h" #include <fdt_support.h> +#include "../common_fdt.h" + static void fdt_fixup_cores_nodes_am625(void *blob, int core_nr) { char node_path[32]; diff --git a/arch/arm/mach-k3/am625_init.c b/arch/arm/mach-k3/am62x/am625_init.c index 668f9a5..ed8d24e 100644 --- a/arch/arm/mach-k3/am625_init.c +++ b/arch/arm/mach-k3/am62x/am625_init.c @@ -9,13 +9,14 @@ #include <spl.h> #include <asm/io.h> #include <asm/arch/hardware.h> -#include "sysfw-loader.h" -#include "common.h" #include <dm.h> #include <dm/uclass-internal.h> #include <dm/pinctrl.h> #include <dm/ofnode.h> +#include "../sysfw-loader.h" +#include "../common.h" + #define RTC_BASE_ADDRESS 0x2b1f0000 #define REG_K3RTC_S_CNT_LSW (RTC_BASE_ADDRESS + 0x18) #define REG_K3RTC_KICK0 (RTC_BASE_ADDRESS + 0x70) diff --git a/arch/arm/mach-k3/am64x/Makefile b/arch/arm/mach-k3/am64x/Makefile index acf09c3..d0b2862 100644 --- a/arch/arm/mach-k3/am64x/Makefile +++ b/arch/arm/mach-k3/am64x/Makefile @@ -1,2 +1,4 @@ # SPDX-License-Identifier: GPL-2.0+ + +obj-$(CONFIG_SPL_BUILD) += am642_init.o obj-y += boot.o diff --git a/arch/arm/mach-k3/am642_init.c b/arch/arm/mach-k3/am64x/am642_init.c index f341b4f..41812b7 100644 --- a/arch/arm/mach-k3/am642_init.c +++ b/arch/arm/mach-k3/am64x/am642_init.c @@ -11,8 +11,6 @@ #include <spl.h> #include <asm/io.h> #include <asm/arch/hardware.h> -#include "sysfw-loader.h" -#include "common.h" #include <linux/soc/ti/ti_sci_protocol.h> #include <dm.h> #include <dm/uclass-internal.h> @@ -21,6 +19,9 @@ #include <dm/root.h> #include <command.h> +#include "../sysfw-loader.h" +#include "../common.h" + #define CTRLMMR_MCU_RST_CTRL 0x04518170 #define CTRLMMR_MCU_RST_SRC (MCU_CTRL_MMR0_BASE + 0x18178) diff --git a/arch/arm/mach-k3/am65x/Makefile b/arch/arm/mach-k3/am65x/Makefile new file mode 100644 index 0000000..20d5f1d --- /dev/null +++ b/arch/arm/mach-k3/am65x/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ +# Andrew Davis <afd@ti.com> + +obj-$(CONFIG_OF_SYSTEM_SETUP) += am654_fdt.o +obj-$(CONFIG_SPL_BUILD) += am654_init.o diff --git a/arch/arm/mach-k3/am654_fdt.c b/arch/arm/mach-k3/am65x/am654_fdt.c index 652fe8d..bcb1520 100644 --- a/arch/arm/mach-k3/am654_fdt.c +++ b/arch/arm/mach-k3/am65x/am654_fdt.c @@ -3,9 +3,10 @@ * Copyright 2023 Toradex - https://www.toradex.com/ */ -#include "common_fdt.h" #include <fdt_support.h> +#include "../common_fdt.h" + int ft_system_setup(void *blob, struct bd_info *bd) { return fdt_fixup_msmc_ram_k3(blob); diff --git a/arch/arm/mach-k3/am654_init.c b/arch/arm/mach-k3/am65x/am654_init.c index 7c2a143..a4f0380 100644 --- a/arch/arm/mach-k3/am654_init.c +++ b/arch/arm/mach-k3/am65x/am654_init.c @@ -12,8 +12,6 @@ #include <asm/io.h> #include <spl.h> #include <asm/arch/hardware.h> -#include "sysfw-loader.h" -#include "common.h" #include <dm.h> #include <dm/uclass-internal.h> #include <dm/pinctrl.h> @@ -22,6 +20,9 @@ #include <mmc.h> #include <stdlib.h> +#include "../sysfw-loader.h" +#include "../common.h" + DECLARE_GLOBAL_DATA_PTR; #ifdef CONFIG_K3_LOAD_SYSFW diff --git a/arch/arm/mach-k3/j721e/Makefile b/arch/arm/mach-k3/j721e/Makefile new file mode 100644 index 0000000..982b88d --- /dev/null +++ b/arch/arm/mach-k3/j721e/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ +# Andrew Davis <afd@ti.com> + +obj-$(CONFIG_OF_SYSTEM_SETUP) += j721e_fdt.o +obj-$(CONFIG_SPL_BUILD) += j721e_init.o diff --git a/arch/arm/mach-k3/j721e_fdt.c b/arch/arm/mach-k3/j721e/j721e_fdt.c index 652fe8d..bcb1520 100644 --- a/arch/arm/mach-k3/j721e_fdt.c +++ b/arch/arm/mach-k3/j721e/j721e_fdt.c @@ -3,9 +3,10 @@ * Copyright 2023 Toradex - https://www.toradex.com/ */ -#include "common_fdt.h" #include <fdt_support.h> +#include "../common_fdt.h" + int ft_system_setup(void *blob, struct bd_info *bd) { return fdt_fixup_msmc_ram_k3(blob); diff --git a/arch/arm/mach-k3/j721e_init.c b/arch/arm/mach-k3/j721e/j721e_init.c index 7ee9b75..c2024f2 100644 --- a/arch/arm/mach-k3/j721e_init.c +++ b/arch/arm/mach-k3/j721e/j721e_init.c @@ -11,8 +11,6 @@ #include <asm/io.h> #include <asm/armv7_mpu.h> #include <asm/arch/hardware.h> -#include "sysfw-loader.h" -#include "common.h" #include <linux/soc/ti/ti_sci_protocol.h> #include <dm.h> #include <dm/uclass-internal.h> @@ -22,6 +20,9 @@ #include <mmc.h> #include <remoteproc.h> +#include "../sysfw-loader.h" +#include "../common.h" + #ifdef CONFIG_K3_LOAD_SYSFW struct fwl_data cbass_hc_cfg0_fwls[] = { #if defined(CONFIG_TARGET_J721E_R5_EVM) diff --git a/arch/arm/mach-k3/j721s2/Makefile b/arch/arm/mach-k3/j721s2/Makefile new file mode 100644 index 0000000..ceef682 --- /dev/null +++ b/arch/arm/mach-k3/j721s2/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ +# Andrew Davis <afd@ti.com> + +obj-$(CONFIG_OF_SYSTEM_SETUP) += j721s2_fdt.o +obj-$(CONFIG_SPL_BUILD) += j721s2_init.o diff --git a/arch/arm/mach-k3/j721s2_fdt.c b/arch/arm/mach-k3/j721s2/j721s2_fdt.c index 652fe8d..bcb1520 100644 --- a/arch/arm/mach-k3/j721s2_fdt.c +++ b/arch/arm/mach-k3/j721s2/j721s2_fdt.c @@ -3,9 +3,10 @@ * Copyright 2023 Toradex - https://www.toradex.com/ */ -#include "common_fdt.h" #include <fdt_support.h> +#include "../common_fdt.h" + int ft_system_setup(void *blob, struct bd_info *bd) { return fdt_fixup_msmc_ram_k3(blob); diff --git a/arch/arm/mach-k3/j721s2_init.c b/arch/arm/mach-k3/j721s2/j721s2_init.c index 3374889..fe9766e 100644 --- a/arch/arm/mach-k3/j721s2_init.c +++ b/arch/arm/mach-k3/j721s2/j721s2_init.c @@ -11,8 +11,6 @@ #include <asm/io.h> #include <asm/armv7_mpu.h> #include <asm/arch/hardware.h> -#include "sysfw-loader.h" -#include "common.h" #include <linux/soc/ti/ti_sci_protocol.h> #include <dm.h> #include <dm/uclass-internal.h> @@ -21,6 +19,9 @@ #include <mmc.h> #include <remoteproc.h> +#include "../sysfw-loader.h" +#include "../common.h" + struct fwl_data cbass_hc_cfg0_fwls[] = { { "PCIE0_CFG", 2577, 7 }, { "EMMC8SS0_CFG", 2579, 4 }, diff --git a/arch/arm/mach-k3/j784s4/Makefile b/arch/arm/mach-k3/j784s4/Makefile new file mode 100644 index 0000000..6d1841e --- /dev/null +++ b/arch/arm/mach-k3/j784s4/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ +# Andrew Davis <afd@ti.com> + +obj-$(CONFIG_OF_SYSTEM_SETUP) += j784s4_fdt.o +obj-$(CONFIG_SPL_BUILD) += j784s4_init.o diff --git a/arch/arm/mach-k3/j784s4_fdt.c b/arch/arm/mach-k3/j784s4/j784s4_fdt.c index d05ed8b..e127509 100644 --- a/arch/arm/mach-k3/j784s4_fdt.c +++ b/arch/arm/mach-k3/j784s4/j784s4_fdt.c @@ -6,9 +6,10 @@ * Apurva Nandan <a-nandan@ti.com> */ -#include "common_fdt.h" #include <fdt_support.h> +#include "../common_fdt.h" + int ft_system_setup(void *blob, struct bd_info *bd) { return fdt_fixup_msmc_ram_k3(blob); diff --git a/arch/arm/mach-k3/j784s4_init.c b/arch/arm/mach-k3/j784s4/j784s4_init.c index ae44203..1ce13e0 100644 --- a/arch/arm/mach-k3/j784s4_init.c +++ b/arch/arm/mach-k3/j784s4/j784s4_init.c @@ -11,8 +11,6 @@ #include <asm/io.h> #include <asm/armv7_mpu.h> #include <asm/arch/hardware.h> -#include "sysfw-loader.h" -#include "common.h" #include <linux/soc/ti/ti_sci_protocol.h> #include <dm.h> #include <dm/uclass-internal.h> @@ -20,6 +18,9 @@ #include <mmc.h> #include <remoteproc.h> +#include "../sysfw-loader.h" +#include "../common.h" + #define J784S4_MAX_DDR_CONTROLLERS 4 struct fwl_data infra_cbass0_fwls[] = { diff --git a/board/beagle/beagleplay/beagleplay.env b/board/beagle/beagleplay/beagleplay.env index bbf6b92..8dbfc2f 100644 --- a/board/beagle/beagleplay/beagleplay.env +++ b/board/beagle/beagleplay/beagleplay.env @@ -1,5 +1,6 @@ #include <env/ti/ti_common.env> #include <env/ti/mmc.env> +#include <env/ti/k3_dfu.env> name_kern=Image console=ttyS2,115200n8 diff --git a/board/ti/am62ax/am62ax.env b/board/ti/am62ax/am62ax.env index 334374a..97122fb 100644 --- a/board/ti/am62ax/am62ax.env +++ b/board/ti/am62ax/am62ax.env @@ -1,5 +1,8 @@ #include <env/ti/ti_common.env> #include <env/ti/mmc.env> +#if CONFIG_CMD_REMOTEPROC +#include <env/ti/k3_rproc.env> +#endif name_kern=Image console=ttyS2,115200n8 @@ -27,3 +30,4 @@ get_kern_mmc=load mmc ${bootpart} ${loadaddr} get_fit_mmc=load mmc ${bootpart} ${addr_fit} ${bootdir}/${name_fit} partitions=name=rootfs,start=0,size=-,uuid=${uuid_gpt_rootfs} +rproc_fw_binaries= 0 /lib/firmware/am62a-mcu-r5f0_0-fw 1 /lib/firmware/am62a-c71_0-fw diff --git a/board/ti/am62x/am62x.env b/board/ti/am62x/am62x.env index 9cb186c..09b9b16 100644 --- a/board/ti/am62x/am62x.env +++ b/board/ti/am62x/am62x.env @@ -1,5 +1,6 @@ #include <env/ti/ti_common.env> #include <env/ti/mmc.env> +#include <env/ti/k3_dfu.env> name_kern=Image console=ttyS2,115200n8 diff --git a/board/ti/j721s2/MAINTAINERS b/board/ti/j721s2/MAINTAINERS index 08c8d11..e31f2ac 100644 --- a/board/ti/j721s2/MAINTAINERS +++ b/board/ti/j721s2/MAINTAINERS @@ -7,17 +7,12 @@ F: doc/board/ti/j721s2_evm.rst F: include/configs/j721s2_evm.h F: configs/j721s2_evm_r5_defconfig F: configs/j721s2_evm_a72_defconfig -F: arch/arm/dts/k3-j721s2.dtsi -F: arch/arm/dts/k3-j721s2-main.dtsi -F: arch/arm/dts/k3-j721s2-mcu-wakeup.dtsi -F: arch/arm/dts/k3-j721s2-thermal.dtsi -F: arch/arm/dts/k3-j721s2-som-p0.dtsi -F: arch/arm/dts/k3-j721s2-common-proc-board.dts +F: configs/am68_sk_r5_defconfig +F: configs/am68_sk_a72_defconfig F: arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi +F: arch/arm/dts/k3-j721s2-r5.dtsi F: arch/arm/dts/k3-j721s2-r5-common-proc-board.dts F: arch/arm/dts/k3-j721s2-ddr.dtsi F: arch/arm/dts/k3-j721s2-ddr-evm-lp4-4266.dtsi -F: arch/arm/dts/k3-am68-sk-som.dtsi -F: arch/arm/dts/k3-am68-sk-base-board.dts F: arch/arm/dts/k3-am68-sk-base-board-u-boot.dtsi F: arch/arm/dts/k3-am68-sk-r5-base-board.dts diff --git a/board/ti/j721s2/j721s2.env b/board/ti/j721s2/j721s2.env index 9a03b9f..a6b2255 100644 --- a/board/ti/j721s2/j721s2.env +++ b/board/ti/j721s2/j721s2.env @@ -13,6 +13,7 @@ args_all=setenv optargs earlycon=ns16550a,mmio32,0x02880000 ${mtdparts} run_kern=booti ${loadaddr} ${rd_spec} ${fdtaddr} +boot_targets=mmc1 mmc0 usb pxe dhcp boot=mmc mmcdev=1 bootpart=1:2 diff --git a/cmd/sandbox/exception.c b/cmd/sandbox/exception.c index cfa153d..f9c847d 100644 --- a/cmd/sandbox/exception.c +++ b/cmd/sandbox/exception.c @@ -19,7 +19,11 @@ static int do_sigsegv(struct cmd_tbl *cmdtp, int flag, int argc, static int do_undefined(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { +#ifdef __powerpc__ + asm volatile (".long 0xffffffff\n"); +#else asm volatile (".word 0xffff\n"); +#endif return CMD_RET_FAILURE; } diff --git a/configs/am62ax_evm_a53_defconfig b/configs/am62ax_evm_a53_defconfig index c4556f5..6b29a4b 100644 --- a/configs/am62ax_evm_a53_defconfig +++ b/configs/am62ax_evm_a53_defconfig @@ -72,6 +72,8 @@ CONFIG_POWER_DOMAIN=y CONFIG_TI_SCI_POWER_DOMAIN=y CONFIG_K3_SYSTEM_CONTROLLER=y CONFIG_REMOTEPROC_TI_K3_ARM64=y +CONFIG_REMOTEPROC_TI_K3_R5F=y +CONFIG_REMOTEPROC_TI_K3_DSP=y CONFIG_RESET_TI_SCI=y CONFIG_DM_SERIAL=y CONFIG_SOC_DEVICE=y @@ -81,3 +83,4 @@ CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y CONFIG_SYSRESET_TI_SCI=y CONFIG_FS_FAT_MAX_CLUSTSIZE=16384 +CONFIG_CMD_REMOTEPROC=y diff --git a/configs/am62x_a53_usbdfu.config b/configs/am62x_a53_usbdfu.config new file mode 100644 index 0000000..3a19cf2 --- /dev/null +++ b/configs/am62x_a53_usbdfu.config @@ -0,0 +1,29 @@ +CONFIG_SYS_MALLOC_LEN=0x2000000 +CONFIG_SPL_ENV_SUPPORT=y +CONFIG_SPL_RAM_SUPPORT=y +CONFIG_SPL_RAM_DEVICE=y +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_DFU=y +CONFIG_CMD_DFU=y +CONFIG_CMD_USB=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +CONFIG_DFU_MMC=y +CONFIG_DFU_RAM=y +CONFIG_SYS_DFU_DATA_BUF_SIZE=0x5000 +CONFIG_SYS_DFU_MAX_FILE_SIZE=0x800000 +CONFIG_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_SPL_DM_USB_GADGET=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_SPL_USB_DWC3_GENERIC=y +CONFIG_SPL_USB_DWC3_AM62=y +CONFIG_USB_DWC3_AM62=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" +CONFIG_USB_GADGET_VENDOR_NUM=0x0451 +CONFIG_USB_GADGET_PRODUCT_NUM=0x6165 +CONFIG_USB_GADGET_DOWNLOAD=y diff --git a/configs/am62x_beagleplay_a53_defconfig b/configs/am62x_beagleplay_a53_defconfig index 4f1be1d..ec62670 100644 --- a/configs/am62x_beagleplay_a53_defconfig +++ b/configs/am62x_beagleplay_a53_defconfig @@ -121,3 +121,5 @@ CONFIG_EXT4_WRITE=y CONFIG_FS_FAT_MAX_CLUSTSIZE=16384 CONFIG_LZO=y CONFIG_EFI_SET_TIME=y + +#include <configs/am62x_a53_usbdfu.config> diff --git a/configs/am62x_evm_a53_defconfig b/configs/am62x_evm_a53_defconfig index 6c708dc..16294a6 100644 --- a/configs/am62x_evm_a53_defconfig +++ b/configs/am62x_evm_a53_defconfig @@ -68,6 +68,7 @@ CONFIG_SPL_OF_TRANSLATE=y CONFIG_CLK=y CONFIG_SPL_CLK=y CONFIG_CLK_TI_SCI=y +CONFIG_DFU_SF=y CONFIG_DMA_CHANNELS=y CONFIG_TI_K3_NAVSS_UDMA=y CONFIG_TI_SCI_PROTOCOL=y @@ -111,3 +112,5 @@ CONFIG_SPL_SYSRESET=y CONFIG_SYSRESET_TI_SCI=y CONFIG_FS_FAT_MAX_CLUSTSIZE=16384 CONFIG_EFI_SET_TIME=y + +#include <configs/am62x_a53_usbdfu.config> diff --git a/configs/am62x_r5_usbdfu.config b/configs/am62x_r5_usbdfu.config new file mode 100644 index 0000000..772bb2a --- /dev/null +++ b/configs/am62x_r5_usbdfu.config @@ -0,0 +1,28 @@ +CONFIG_SPL_ENV_SUPPORT=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +CONFIG_SYS_DFU_DATA_BUF_SIZE=0x5000 +CONFIG_MISC=y +CONFIG_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_SPL_DM_USB_GADGET=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_SPL_USB_DWC3_GENERIC=y +CONFIG_SPL_USB_DWC3_AM62=y +CONFIG_USB_GADGET=y +CONFIG_SPL_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" +CONFIG_USB_GADGET_VENDOR_NUM=0x0451 +CONFIG_USB_GADGET_PRODUCT_NUM=0x6165 +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_SPL_DFU=y +# CONFIG_SPL_MMC is not set +# CONFIG_SPL_FS_FAT is not set +# CONFIG_SPL_LIBDISK_SUPPORT is not set +# CONFIG_SPL_SPI is not set +# CONFIG_SPL_SYS_MALLOC is not set +# CONFIG_CMD_GPT is not set +# CONFIG_CMD_MMC is not set +# CONFIG_CMD_FAT is not set +# CONFIG_MMC_SDHCI is not set diff --git a/configs/am68_sk_a72_defconfig b/configs/am68_sk_a72_defconfig new file mode 100644 index 0000000..e750614 --- /dev/null +++ b/configs/am68_sk_a72_defconfig @@ -0,0 +1,10 @@ +#include <configs/j721s2_evm_a72_defconfig> + +CONFIG_ARM=y +CONFIG_ARCH_K3=y +CONFIG_SOC_K3_J721S2=y +CONFIG_TARGET_J721S2_A72_EVM=y + +CONFIG_SPL_OF_LIST="ti/k3-am68-sk-base-board" +CONFIG_DEFAULT_DEVICE_TREE="ti/k3-am68-sk-base-board" +CONFIG_OF_LIST="ti/k3-am68-sk-base-board" diff --git a/configs/am68_sk_r5_defconfig b/configs/am68_sk_r5_defconfig new file mode 100644 index 0000000..e9b6882 --- /dev/null +++ b/configs/am68_sk_r5_defconfig @@ -0,0 +1,10 @@ +#include <configs/j721s2_evm_r5_defconfig> + +CONFIG_ARM=y +CONFIG_ARCH_K3=y +CONFIG_SOC_K3_J721S2=y +CONFIG_TARGET_J721S2_R5_EVM=y + +CONFIG_DEFAULT_DEVICE_TREE="k3-am68-sk-r5-base-board" +CONFIG_SPL_OF_LIST="k3-am68-sk-r5-base-board" +CONFIG_OF_LIST="k3-am68-sk-r5-base-board" diff --git a/configs/j721s2_evm_a72_defconfig b/configs/j721s2_evm_a72_defconfig index 19cd44b..5ed8d00 100644 --- a/configs/j721s2_evm_a72_defconfig +++ b/configs/j721s2_evm_a72_defconfig @@ -13,7 +13,7 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80480000 CONFIG_ENV_SIZE=0x20000 CONFIG_DM_GPIO=y CONFIG_SPL_DM_SPI=y -CONFIG_DEFAULT_DEVICE_TREE="k3-j721s2-common-proc-board" +CONFIG_DEFAULT_DEVICE_TREE="ti/k3-j721s2-common-proc-board" CONFIG_SPL_TEXT_BASE=0x80080000 CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y @@ -33,9 +33,10 @@ CONFIG_SPL_SPI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000 -CONFIG_DISTRO_DEFAULTS=y CONFIG_OF_SYSTEM_SETUP=y -CONFIG_BOOTCOMMAND="run envboot; run distro_bootcmd;" +CONFIG_BOOTSTD_FULL=y +CONFIG_BOOTSTD_DEFAULTS=y +CONFIG_BOOTCOMMAND="run envboot; bootflow scan -lb" CONFIG_LOGLEVEL=7 CONFIG_SPL_MAX_SIZE=0xc0000 CONFIG_SPL_BOARD_INIT=y @@ -83,8 +84,9 @@ CONFIG_CMD_UBI=y # CONFIG_SPL_EFI_PARTITION is not set CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_LIST="k3-j721s2-common-proc-board k3-am68-sk-base-board" +CONFIG_OF_LIST="ti/k3-j721s2-common-proc-board" CONFIG_SPL_MULTI_DTB_FIT=y +CONFIG_OF_UPSTREAM=y CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y diff --git a/configs/j721s2_evm_r5_defconfig b/configs/j721s2_evm_r5_defconfig index 5ef5247..3c958ca 100644 --- a/configs/j721s2_evm_r5_defconfig +++ b/configs/j721s2_evm_r5_defconfig @@ -82,7 +82,7 @@ CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_SPL_MULTI_DTB_FIT=y -CONFIG_SPL_OF_LIST="k3-j721s2-r5-common-proc-board k3-am68-sk-r5-base-board" +CONFIG_SPL_OF_LIST="k3-j721s2-r5-common-proc-board" CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y CONFIG_ENV_OVERWRITE=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y diff --git a/doc/board/beagle/am62x_beagleplay.rst b/doc/board/beagle/am62x_beagleplay.rst index 7784e62..cdc6102 100644 --- a/doc/board/beagle/am62x_beagleplay.rst +++ b/doc/board/beagle/am62x_beagleplay.rst @@ -268,7 +268,19 @@ for details. - USB Device Firmware Upgrade (DFU) mode To switch to SD card boot mode, hold the USR button while powering on -with Type-C power supply, then release when power LED lights up. +with a USB type C power supply, then release when power LED lights up. + +DFU based boot +-------------- + +To boot the board over DFU, ensure there is no SD card inserted with a +bootloader. Hold the USR switch while plugging into the type C to boot into DFU +mode. After power-on the build artifacts needs to be uploaded one by one with a +tool like dfu-util. + +.. include:: ../ti/am62x_sk.rst + :start-after: .. am62x_evm_rst_include_start_dfu_boot + :end-before: .. am62x_evm_rst_include_end_dfu_boot Debugging U-Boot ---------------- diff --git a/doc/board/ti/am62x_sk.rst b/doc/board/ti/am62x_sk.rst index b12dc85..d5f7fe3 100644 --- a/doc/board/ti/am62x_sk.rst +++ b/doc/board/ti/am62x_sk.rst @@ -109,6 +109,20 @@ Set the variables corresponding to this platform: :start-after: .. k3_rst_include_start_build_steps_spl_r5 :end-before: .. k3_rst_include_end_build_steps_spl_r5 +* 3.1.1 Alternative build of R5 for DFU boot: + +As the SPL size can get too big when building with support for booting both +from local storage *and* DFU an extra config fragment should be used to enable +DFU support (and disable storage support) + +.. prompt:: bash $ + + export UBOOT_CFG_CORTEXR="${UBOOT_CFG_CORTEXR} am62x_r5_usbdfu.config" + +.. include:: ../ti/k3.rst + :start-after: .. k3_rst_include_start_build_steps_spl_r5 + :end-before: .. k3_rst_include_end_build_steps_spl_r5 + * 3.2 A53: .. include:: ../ti/k3.rst @@ -251,6 +265,29 @@ https://www.ti.com/lit/pdf/spruiv7 under the `Boot Mode Pins` section. For SW2 and SW1, the switch state in the "ON" position = 1. +DFU based boot +-------------- + +To boot the board over DFU, set the switches to DFU mode and connect to the +USB type C DRD port on the board. After power-on the build artifacts needs to be +uploaded one by one with a tool like dfu-util. + +.. am62x_evm_rst_include_start_dfu_boot + +The initial ROM will have a DFU alt named `bootloader` for the initial R5 spl +upload. The next stages as exposed by U-Boot have target alts matching the name +of the artifacts, for these a USB reset has to be done after each upload. + +When using dfu-util the following commands can be used to boot to a U-Boot shell: + +.. prompt:: bash $ + + dfu-util -a bootloader -D tiboot3.bin + dfu-util -R -a tispl -D tispl.bin + dfu-util -R -a u-boot.img -D u-boot.img + +.. am62x_evm_rst_include_end_dfu_boot + Debugging U-Boot ---------------- diff --git a/drivers/crypto/nuvoton/npcm_sha.c b/drivers/crypto/nuvoton/npcm_sha.c index f06be86..6da1620 100644 --- a/drivers/crypto/nuvoton/npcm_sha.c +++ b/drivers/crypto/nuvoton/npcm_sha.c @@ -1,867 +1,344 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (c) 2022 Nuvoton Technology Corp. + * Copyright (c) 2024 Nuvoton Technology Corp. */ #include <dm.h> #include <hash.h> #include <malloc.h> -#include <uboot_aes.h> #include <asm/io.h> +#include <linux/iopoll.h> -#define HASH_DIG_H_NUM 8 +#define SHA512_BLOCK_LENGTH (1024 / 8) +/* Register fields */ #define HASH_CTR_STS_SHA_EN BIT(0) #define HASH_CTR_STS_SHA_BUSY BIT(1) #define HASH_CTR_STS_SHA_RST BIT(2) #define HASH_CFG_SHA1_SHA2 BIT(0) - -/* SHA type */ -enum npcm_sha_type { - npcm_sha_type_sha2 = 0, - npcm_sha_type_sha1, - npcm_sha_type_num +#define SHA512_CMD_SHA_512 BIT(3) +#define SHA512_CMD_INTERNAL_ROUND BIT(2) +#define SHA512_CMD_WRITE BIT(1) +#define SHA512_CMD_READ BIT(0) + +enum { + type_sha1 = 0, + type_sha256, + type_sha384, + type_sha512, }; struct npcm_sha_regs { - unsigned int hash_data_in; - unsigned char hash_ctr_sts; - unsigned char reserved_0[0x03]; - unsigned char hash_cfg; - unsigned char reserved_1[0x03]; - unsigned char hash_ver; - unsigned char reserved_2[0x13]; - unsigned int hash_dig[HASH_DIG_H_NUM]; + u8 data_in; + u8 data_out; + u8 ctr_sts; + u8 hash_cfg; + u8 sha512_cmd; }; -struct npcm_sha_priv { - struct npcm_sha_regs *regs; +struct hash_info { + u32 block_sz; + u32 digest_len; + u8 length_bytes; + u8 type; }; -static struct npcm_sha_priv *sha_priv; +struct message_block { + u64 length[2]; + u64 nonhash_sz; + u8 buffer[SHA512_BLOCK_LENGTH * 2]; +}; -#ifdef SHA_DEBUG_MODULE -#define sha_print(fmt, args...) printf(fmt, ##args) -#else -#define sha_print(fmt, args...) (void)0 -#endif - -#define SHA_BLOCK_LENGTH (512 / 8) -#define SHA_2_HASH_LENGTH (256 / 8) -#define SHA_1_HASH_LENGTH (160 / 8) -#define SHA_HASH_LENGTH(type) ((type == npcm_sha_type_sha2) ? \ - (SHA_2_HASH_LENGTH) : (SHA_1_HASH_LENGTH)) - -#define SHA_SECRUN_BUFF_SIZE 64 -#define SHA_TIMEOUT 100 -#define SHA_DATA_LAST_BYTE 0x80 - -#define SHA2_NUM_OF_SELF_TESTS 3 -#define SHA1_NUM_OF_SELF_TESTS 4 - -#define NUVOTON_ALIGNMENT 4 - -/*-----------------------------------------------------------------------------*/ -/* SHA instance struct handler */ -/*-----------------------------------------------------------------------------*/ -struct SHA_HANDLE_T { - u32 hv[SHA_2_HASH_LENGTH / sizeof(u32)]; - u32 length0; - u32 length1; - u32 block[SHA_BLOCK_LENGTH / sizeof(u32)]; - u8 type; - bool active; +struct npcm_sha_priv { + void *base; + struct npcm_sha_regs *regs; + struct hash_info *hash; + struct message_block block; + bool internal_round; + bool support_sha512; }; -// The # of bytes currently in the sha block buffer -#define SHA_BUFF_POS(length) ((length) & (SHA_BLOCK_LENGTH - 1)) - -// The # of free bytes in the sha block buffer -#define SHA_BUFF_FREE(length) (SHA_BLOCK_LENGTH - SHA_BUFF_POS(length)) - -static void SHA_FlushLocalBuffer_l(const u32 *buff); -static int SHA_BusyWait_l(void); -static void SHA_GetShaDigest_l(u8 *hashdigest, u8 type); -static void SHA_SetShaDigest_l(const u32 *hashdigest, u8 type); -static void SHA_SetBlock_l(const u8 *data, u32 len, u16 position, u32 *block); -static void SHA_ClearBlock_l(u16 len, u16 position, u32 *block); -static void SHA_SetLength32_l(struct SHA_HANDLE_T *handleptr, u32 *block); - -static int SHA_Init(struct SHA_HANDLE_T *handleptr); -static int SHA_Start(struct SHA_HANDLE_T *handleptr, u8 type); -static int SHA_Update(struct SHA_HANDLE_T *handleptr, const u8 *buffer, u32 len); -static int SHA_Finish(struct SHA_HANDLE_T *handleptr, u8 *hashdigest); -static int SHA_Reset(void); -static int SHA_Power(bool on); -#ifdef SHA_PRINT -static void SHA_PrintRegs(void); -static void SHA_PrintVersion(void); -#endif - -static struct SHA_HANDLE_T sha_handle; - -/*----------------------------------------------------------------------------*/ -/* Checks if give function returns int error, and returns the error */ -/* immediately after SHA disabling */ -/*----------------------------------------------------------------------------*/ -int npcm_sha_check(int status) -{ - if (status != 0) { - SHA_Power(false); - return status; - } - return 0; -} +static struct npcm_sha_regs npcm_sha_reg_tbl[] = { + { .data_in = 0x0, .data_out = 0x20, .ctr_sts = 0x4, .hash_cfg = 0x8 }, + { .data_in = 0x10, .data_out = 0x1c, .ctr_sts = 0x14, .sha512_cmd = 0x18 }, +}; -/*----------------------------------------------------------------------------*/ -/* Function: npcm_sha_calc */ -/* */ -/* Parameters: type - SHA module type */ -/* inBuff - Pointer to a buffer containing the data to */ -/* be hashed */ -/* len - Length of the data to hash */ -/* hashDigest - Pointer to a buffer where the reseulting */ -/* digest will be copied to */ -/* */ -/* Returns: 0 on success or other int error code on error */ -/* Side effects: */ -/* Description: */ -/* This routine performs complete SHA calculation in one */ -/* step */ -/*----------------------------------------------------------------------------*/ -int npcm_sha_calc(u8 type, const u8 *inbuff, u32 len, u8 *hashdigest) -{ - int status; - struct SHA_HANDLE_T handle; - - SHA_Init(&handle); - SHA_Power(true); - SHA_Reset(); - SHA_Start(&handle, type); - status = SHA_Update(&handle, inbuff, len); - npcm_sha_check(status); - status = SHA_Finish(&handle, hashdigest); - npcm_sha_check(status); - SHA_Power(false); +static struct hash_info npcm_hash_tbl[] = { + { .type = type_sha1, .block_sz = 64, .digest_len = 160, .length_bytes = 8 }, + { .type = type_sha256, .block_sz = 64, .digest_len = 256, .length_bytes = 8 }, + { .type = type_sha384, .block_sz = 128, .digest_len = 384, .length_bytes = 16 }, + { .type = type_sha512, .block_sz = 128, .digest_len = 512, .length_bytes = 16 }, +}; - return 0; -} +static struct npcm_sha_priv *sha_priv; -/* - * Computes hash value of input pbuf using h/w acceleration - * - * @param in_addr A pointer to the input buffer - * @param bufleni Byte length of input buffer - * @param out_addr A pointer to the output buffer. When complete - * 32 bytes are copied to pout[0]...pout[31]. Thus, a user - * should allocate at least 32 bytes at pOut in advance. - * @param chunk_size chunk size for sha256 - */ -void hw_sha256(const uchar *in_addr, uint buflen, uchar *out_addr, uint chunk_size) +static int npcm_sha_init(u8 type) { - puts("\nhw_sha256 using BMC HW accelerator\t"); - npcm_sha_calc(npcm_sha_type_sha2, (u8 *)in_addr, buflen, (u8 *)out_addr); -} + struct message_block *block = &sha_priv->block; -/* - * Computes hash value of input pbuf using h/w acceleration - * - * @param in_addr A pointer to the input buffer - * @param bufleni Byte length of input buffer - * @param out_addr A pointer to the output buffer. When complete - * 32 bytes are copied to pout[0]...pout[31]. Thus, a user - * should allocate at least 32 bytes at pOut in advance. - * @param chunk_size chunk_size for sha1 - */ -void hw_sha1(const uchar *in_addr, uint buflen, uchar *out_addr, uint chunk_size) -{ - puts("\nhw_sha1 using BMC HW accelerator\t"); - npcm_sha_calc(npcm_sha_type_sha1, (u8 *)in_addr, buflen, (u8 *)out_addr); -} + if (type > type_sha512 || + (!sha_priv->support_sha512 && + (type == type_sha384 || type == type_sha512))) + return -ENOTSUPP; -/* - * Create the context for sha progressive hashing using h/w acceleration - * - * @algo: Pointer to the hash_algo struct - * @ctxp: Pointer to the pointer of the context for hashing - * @return 0 if ok, -ve on error - */ -int hw_sha_init(struct hash_algo *algo, void **ctxp) -{ - const char *algo_name1 = "sha1"; - const char *algo_name2 = "sha256"; - - SHA_Init(&sha_handle); - SHA_Power(true); - SHA_Reset(); - if (!strcmp(algo_name1, algo->name)) - return SHA_Start(&sha_handle, npcm_sha_type_sha1); - else if (!strcmp(algo_name2, algo->name)) - return SHA_Start(&sha_handle, npcm_sha_type_sha2); - else - return -EPROTO; -} + sha_priv->regs = &npcm_sha_reg_tbl[type / 2]; + sha_priv->hash = &npcm_hash_tbl[type]; + block->length[0] = 0; + block->length[1] = 0; + block->nonhash_sz = 0; + sha_priv->internal_round = false; -/* - * Update buffer for sha progressive hashing using h/w acceleration - * - * The context is freed by this function if an error occurs. - * - * @algo: Pointer to the hash_algo struct - * @ctx: Pointer to the context for hashing - * @buf: Pointer to the buffer being hashed - * @size: Size of the buffer being hashed - * @is_last: 1 if this is the last update; 0 otherwise - * @return 0 if ok, -ve on error - */ -int hw_sha_update(struct hash_algo *algo, void *ctx, const void *buf, - unsigned int size, int is_last) -{ - return SHA_Update(&sha_handle, buf, size); + return 0; } -/* - * Copy sha hash result at destination location - * - * The context is freed after completion of hash operation or after an error. - * - * @algo: Pointer to the hash_algo struct - * @ctx: Pointer to the context for hashing - * @dest_buf: Pointer to the destination buffer where hash is to be copied - * @size: Size of the buffer being hashed - * @return 0 if ok, -ve on error - */ -int hw_sha_finish(struct hash_algo *algo, void *ctx, void *dest_buf, int size) +static void npcm_sha_reset(void) { - int status; - - status = SHA_Finish(&sha_handle, dest_buf); - npcm_sha_check(status); - return SHA_Power(false); + struct npcm_sha_regs *regs = sha_priv->regs; + struct hash_info *hash = sha_priv->hash; + u8 val; + + if (hash->type == type_sha1) + writeb(HASH_CFG_SHA1_SHA2, sha_priv->base + regs->hash_cfg); + else if (hash->type == type_sha256) + writeb(0, sha_priv->base + regs->hash_cfg); + else if (hash->type == type_sha384) + writeb(0, sha_priv->base + regs->sha512_cmd); + else if (hash->type == type_sha512) + writeb(SHA512_CMD_SHA_512, sha_priv->base + regs->sha512_cmd); + + val = readb(sha_priv->base + regs->ctr_sts) & ~HASH_CTR_STS_SHA_EN; + writeb(val | HASH_CTR_STS_SHA_RST, sha_priv->base + regs->ctr_sts); } -/*----------------------------------------------------------------------------*/ -/* Function: SHA_Init */ -/* */ -/* Parameters: handlePtr - SHA processing handle pointer */ -/* Returns: 0 on success or other int error code on error. */ -/* Side effects: */ -/* Description: */ -/* This routine initialize the SHA module */ -/*----------------------------------------------------------------------------*/ -static int SHA_Init(struct SHA_HANDLE_T *handleptr) +static void npcm_sha_enable(bool on) { - handleptr->active = false; + struct npcm_sha_regs *regs = sha_priv->regs; + u8 val; - return 0; + val = readb(sha_priv->base + regs->ctr_sts) & ~HASH_CTR_STS_SHA_EN; + val |= on; + writeb(val | on, sha_priv->base + regs->ctr_sts); } -/*----------------------------------------------------------------------------*/ -/* Function: SHA_Start */ -/* */ -/* Parameters: handlePtr - SHA processing handle pointer */ -/* type - SHA module type */ -/* */ -/* Returns: 0 on success or other int error code on error. */ -/* Side effects: */ -/* Description: */ -/* This routine start a single SHA process */ -/*----------------------------------------------------------------------------*/ -static int SHA_Start(struct SHA_HANDLE_T *handleptr, u8 type) +static int npcm_sha_flush_block(u8 *block) { struct npcm_sha_regs *regs = sha_priv->regs; + struct hash_info *hash = sha_priv->hash; + u32 *blk_dw = (u32 *)block; + u8 val; + int i; + + if (readb_poll_timeout(sha_priv->base + regs->ctr_sts, val, + !(val & HASH_CTR_STS_SHA_BUSY), 100)) + return -ETIMEDOUT; + + if (hash->type == type_sha384 || hash->type == type_sha512) { + val = SHA512_CMD_WRITE; + if (hash->type == type_sha512) + val |= SHA512_CMD_SHA_512; + if (sha_priv->internal_round) + val |= SHA512_CMD_INTERNAL_ROUND; + writeb(val, sha_priv->base + regs->sha512_cmd); + } + for (i = 0; i < (hash->block_sz / sizeof(u32)); i++) + writel(blk_dw[i], sha_priv->base + regs->data_in); - // Initialize handle - handleptr->length0 = 0; - handleptr->length1 = 0; - handleptr->type = type; - handleptr->active = true; - - // Set SHA type - writeb(handleptr->type & HASH_CFG_SHA1_SHA2, ®s->hash_cfg); - - // Reset SHA hardware - SHA_Reset(); - - /* The handlePtr->hv is initialized with the correct IV as the SHA engine - * automatically fill the HASH_DIG_Hn registers according to SHA spec - * (following SHA_RST assertion) - */ - SHA_GetShaDigest_l((u8 *)handleptr->hv, type); - - // Init block with zeros - memset(handleptr->block, 0, sizeof(handleptr->block)); + sha_priv->internal_round = true; return 0; } -/*----------------------------------------------------------------------------*/ -/* Function: SHA_Update */ -/* */ -/* Parameters: handlePtr - SHA processing handle pointer */ -/* buffer - Pointer to the data that will be added to */ -/* the hash calculation */ -/* len - Length of data to add to SHA calculation */ -/* */ -/* */ -/* Returns: 0 on success or other int error code on error */ -/* Side effects: */ -/* Description: */ -/* This routine adds data to previously started SHA */ -/* calculation */ -/*----------------------------------------------------------------------------*/ -static int SHA_Update(struct SHA_HANDLE_T *handleptr, const u8 *buffer, u32 len) +static int npcm_sha_update_block(const u8 *in, u32 len) { - struct npcm_sha_regs *regs = sha_priv->regs; - u32 localbuffer[SHA_SECRUN_BUFF_SIZE / sizeof(u32)]; - u32 bufferlen = len; - u16 pos = 0; - u8 *blockptr; - int status; - - // Error check - if (!handleptr->active) - return -EPROTO; - - // Wait till SHA is not busy - status = SHA_BusyWait_l(); - npcm_sha_check(status); - - // Set SHA type - writeb(handleptr->type & HASH_CFG_SHA1_SHA2, ®s->hash_cfg); - - // Write SHA latest digest into SHA module - SHA_SetShaDigest_l(handleptr->hv, handleptr->type); - - // Set number of unhashed bytes which remained from last update - pos = SHA_BUFF_POS(handleptr->length0); - - // Copy unhashed bytes which remained from last update to secrun buffer - SHA_SetBlock_l((u8 *)handleptr->block, pos, 0, localbuffer); - - while (len) { - // Wait for the hardware to be available (in case we are hashing) - status = SHA_BusyWait_l(); - npcm_sha_check(status); - - // Move as much bytes as we can into the secrun buffer - bufferlen = min(len, SHA_BUFF_FREE(handleptr->length0)); - - // Copy current given buffer to the secrun buffer - SHA_SetBlock_l((u8 *)buffer, bufferlen, pos, localbuffer); - - // Update size of hashed bytes - handleptr->length0 += bufferlen; - - if (handleptr->length0 < bufferlen) - handleptr->length1++; - - // Update length of data left to digest - len -= bufferlen; - - // Update given buffer pointer - buffer += bufferlen; - - // If secrun buffer is full - if (SHA_BUFF_POS(handleptr->length0) == 0) { - /* We just filled up the buffer perfectly, so let it hash (we'll - * unload the hash only when we are done with all hashing) - */ - SHA_FlushLocalBuffer_l(localbuffer); - - pos = 0; - bufferlen = 0; - } + struct message_block *block = &sha_priv->block; + struct hash_info *hash = sha_priv->hash; + u8 *buffer = &block->buffer[0]; + u32 block_sz = hash->block_sz; + u32 hash_sz; + + hash_sz = (block->nonhash_sz + len) > block_sz ? + (block_sz - block->nonhash_sz) : len; + memcpy(buffer + block->nonhash_sz, in, hash_sz); + block->nonhash_sz += hash_sz; + block->length[0] += hash_sz; + if (block->length[0] < hash_sz) + block->length[1]++; + + if (block->nonhash_sz == block_sz) { + block->nonhash_sz = 0; + if (npcm_sha_flush_block(buffer)) + return -EBUSY; } - // Wait till SHA is not busy - status = SHA_BusyWait_l(); - npcm_sha_check(status); - - /* Copy unhashed bytes from given buffer to handle block for next update/finish */ - blockptr = (u8 *)handleptr->block; - while (bufferlen) - blockptr[--bufferlen + pos] = *(--buffer); - - // Save SHA current digest - SHA_GetShaDigest_l((u8 *)handleptr->hv, handleptr->type); - - return 0; + return hash_sz; } -/*----------------------------------------------------------------------------*/ -/* Function: SHA_Finish */ -/* */ -/* Parameters: handlePtr - SHA processing handle pointer */ -/* hashDigest - Pointer to a buffer where the final digest */ -/* will be copied to */ -/* */ -/* Returns: 0 on success or other int error code on error */ -/* Side effects: */ -/* Description: */ -/* This routine finish SHA calculation and get */ -/* the resulting SHA digest */ -/*----------------------------------------------------------------------------*/ -static int SHA_Finish(struct SHA_HANDLE_T *handleptr, u8 *hashdigest) +static int npcm_sha_update(const u8 *input, u32 len) { - struct npcm_sha_regs *regs = sha_priv->regs; - u32 localbuffer[SHA_SECRUN_BUFF_SIZE / sizeof(u32)]; - const u8 lastbyte = SHA_DATA_LAST_BYTE; - u16 pos; - int status; - - // Error check - if (!handleptr->active) - return -EPROTO; - - // Set SHA type - writeb(handleptr->type & HASH_CFG_SHA1_SHA2, ®s->hash_cfg); - - // Wait till SHA is not busy - status = SHA_BusyWait_l(); - npcm_sha_check(status); - - // Finish off the current buffer with the SHA spec'ed padding - pos = SHA_BUFF_POS(handleptr->length0); - - // Init SHA digest - SHA_SetShaDigest_l(handleptr->hv, handleptr->type); - - // Load data into secrun buffer - SHA_SetBlock_l((u8 *)handleptr->block, pos, 0, localbuffer); - - // Set data last byte as in SHA algorithm spec - SHA_SetBlock_l(&lastbyte, 1, pos++, localbuffer); + int hash_sz; - // If the remainder of data is longer then one block - if (pos > (SHA_BLOCK_LENGTH - 8)) { - /* The length will be in the next block Pad the rest of the last block with 0's */ - SHA_ClearBlock_l((SHA_BLOCK_LENGTH - pos), pos, localbuffer); - - // Hash the current block - SHA_FlushLocalBuffer_l(localbuffer); - - pos = 0; - - // Wait till SHA is not busy - status = SHA_BusyWait_l(); - npcm_sha_check(status); + while (len) { + hash_sz = npcm_sha_update_block(input, len); + if (hash_sz < 0) { + printf("SHA512 module busy\n"); + return -EBUSY; + } + len -= hash_sz; + input += hash_sz; } - // Pad the rest of the last block with 0's except for the last 8-3 bytes - SHA_ClearBlock_l((SHA_BLOCK_LENGTH - (8 - 3)) - pos, pos, localbuffer); - - /* The last 8-3 bytes are set to the bit-length of the message in big-endian form */ - SHA_SetLength32_l(handleptr, localbuffer); - - // Hash all that, and save the hash for the caller - SHA_FlushLocalBuffer_l(localbuffer); - - // Wait till SHA is not busy - status = SHA_BusyWait_l(); - npcm_sha_check(status); - - // Save SHA final digest into given buffer - SHA_GetShaDigest_l(hashdigest, handleptr->type); - - // Free handle - handleptr->active = false; - return 0; } -/*----------------------------------------------------------------------------*/ -/* Function: SHA_Reset */ -/* */ -/* Parameters: none */ -/* Returns: none */ -/* Side effects: */ -/* Description: */ -/* This routine reset SHA module */ -/*----------------------------------------------------------------------------*/ -static int SHA_Reset(void) +static int npcm_sha_finish(u8 *out) { struct npcm_sha_regs *regs = sha_priv->regs; - - writel(readl(®s->hash_ctr_sts) | HASH_CTR_STS_SHA_RST, ®s->hash_ctr_sts); + struct message_block *block = &sha_priv->block; + struct hash_info *hash = sha_priv->hash; + u8 *buffer = &block->buffer[0]; + u32 block_sz = hash->block_sz; + u32 *out32 = (u32 *)out; + u32 zero_len, val; + u64 *length; + u8 reg_data_out; + int i; + + /* Padding, minimal padding size is last_byte+length_bytes */ + if ((block_sz - block->nonhash_sz) >= (hash->length_bytes + 1)) + zero_len = block_sz - block->nonhash_sz - (hash->length_bytes + 1); + else + zero_len = block_sz * 2 - block->nonhash_sz - (hash->length_bytes + 1); + /* Last byte */ + buffer[block->nonhash_sz++] = 0x80; + /* Zero bits padding */ + memset(&buffer[block->nonhash_sz], 0, zero_len); + block->nonhash_sz += zero_len; + /* Message length */ + length = (u64 *)&buffer[block->nonhash_sz]; + if (hash->length_bytes == 16) { + *length++ = cpu_to_be64(block->length[1] << 3 | block->length[0] >> 61); + block->nonhash_sz += 8; + } + *length = cpu_to_be64(block->length[0] << 3); + block->nonhash_sz += 8; + if (npcm_sha_flush_block(&block->buffer[0])) + return -ETIMEDOUT; + + /* After padding, the last message may produce 2 blocks */ + if (block->nonhash_sz > block_sz) { + if (npcm_sha_flush_block(&block->buffer[block_sz])) + return -ETIMEDOUT; + } + /* Read digest */ + if (readb_poll_timeout(sha_priv->base + regs->ctr_sts, val, + !(val & HASH_CTR_STS_SHA_BUSY), 100)) + return -ETIMEDOUT; + if (hash->type == type_sha384) + writeb(SHA512_CMD_READ, sha_priv->base + regs->sha512_cmd); + else if (hash->type == type_sha512) + writeb(SHA512_CMD_SHA_512 | SHA512_CMD_READ, + sha_priv->base + regs->sha512_cmd); + + reg_data_out = regs->data_out; + for (i = 0; i < (hash->digest_len / 32); i++) { + *out32 = readl(sha_priv->base + reg_data_out); + out32++; + if (hash->type == type_sha1 || hash->type == type_sha256) + reg_data_out += 4; + } return 0; } -/*----------------------------------------------------------------------------*/ -/* Function: SHA_Power */ -/* */ -/* Parameters: on - true enable the module, false disable the module */ -/* Returns: none */ -/* Side effects: */ -/* Description: */ -/* This routine set SHA module power on/off */ -/*----------------------------------------------------------------------------*/ -static int SHA_Power(bool on) +int npcm_sha_calc(const u8 *input, u32 len, u8 *output, u8 type) { - struct npcm_sha_regs *regs = sha_priv->regs; - u8 hash_sts; - - hash_sts = readb(®s->hash_ctr_sts) & ~HASH_CTR_STS_SHA_EN; - writeb(hash_sts | (on & HASH_CTR_STS_SHA_EN), ®s->hash_ctr_sts); + if (npcm_sha_init(type)) + return -ENOTSUPP; + npcm_sha_reset(); + npcm_sha_enable(true); + npcm_sha_update(input, len); + npcm_sha_finish(output); + npcm_sha_enable(false); return 0; } -#ifdef SHA_PRINT -/*----------------------------------------------------------------------------*/ -/* Function: SHA_PrintRegs */ -/* */ -/* Parameters: none */ -/* Returns: none */ -/* Side effects: */ -/* Description: */ -/* This routine prints the module registers */ -/*----------------------------------------------------------------------------*/ -static void SHA_PrintRegs(void) +void hw_sha512(const unsigned char *input, unsigned int len, + unsigned char *output, unsigned int chunk_sz) { -#ifdef SHA_DEBUG_MODULE - struct npcm_sha_regs *regs = sha_priv->regs; -#endif - unsigned int i; - - sha_print("/*--------------*/\n"); - sha_print("/* SHA */\n"); - sha_print("/*--------------*/\n\n"); - - sha_print("HASH_CTR_STS = 0x%02X\n", readb(®s->hash_ctr_sts)); - sha_print("HASH_CFG = 0x%02X\n", readb(®s->hash_cfg)); - - for (i = 0; i < HASH_DIG_H_NUM; i++) - sha_print("HASH_DIG_H%d = 0x%08X\n", i, readl(®s->hash_dig[i])); - - sha_print("HASH_VER = 0x%08X\n", readb(®s->hash_ver)); - - sha_print("\n"); + if (!sha_priv->support_sha512) { + puts(" HW accelerator not support\n"); + return; + } + puts(" using BMC HW accelerator\n"); + npcm_sha_calc(input, len, output, type_sha512); } -/*----------------------------------------------------------------------------*/ -/* Function: SHA_PrintVersion */ -/* */ -/* Parameters: none */ -/* Returns: none */ -/* Side effects: */ -/* Description: */ -/* This routine prints the module version */ -/*----------------------------------------------------------------------------*/ -static void SHA_PrintVersion(void) -{ - struct npcm_sha_regs *regs = sha_priv->regs; - - printf("SHA MODULE VER = %d\n", readb(®s->hash_ver)); -} -#endif - -/*----------------------------------------------------------------------------*/ -/* Function: npcm_sha_selftest */ -/* */ -/* Parameters: type - SHA module type */ -/* Returns: 0 on success or other int error code on error */ -/* Side effects: */ -/* Description: */ -/* This routine performs various tests on the SHA HW and SW */ -/*----------------------------------------------------------------------------*/ -int npcm_sha_selftest(u8 type) +void hw_sha384(const unsigned char *input, unsigned int len, + unsigned char *output, unsigned int chunk_sz) { - int status; - struct SHA_HANDLE_T handle; - u8 hashdigest[max(SHA_1_HASH_LENGTH, SHA_2_HASH_LENGTH)]; - u16 i, j; - - /*------------------------------------------------------------------------*/ - /* SHA1 tests info */ - /*------------------------------------------------------------------------*/ - - static const u8 sha1selftestbuff[SHA1_NUM_OF_SELF_TESTS][94] = { - {"abc"}, - {"abcdbcdecdefdefgefghfghighijhijkijkljklmklmnlmnomnopnopq"}, - {"0123456789012345678901234567890123456789012345678901234567890123"}, - {0x30, 0x5c, 0x30, 0x2c, 0x02, 0x01, 0x00, 0x30, 0x09, 0x06, 0x05, 0x2b, - 0x0e, 0x03, 0x02, 0x1a, 0x05, 0x00, 0x30, 0x06, 0x06, 0x04, 0x67, 0x2a, - 0x01, 0x0c, 0x04, 0x14, 0xe1, 0xb6, 0x93, 0xfe, 0x33, 0x43, 0xc1, 0x20, - 0x5d, 0x4b, 0xaa, 0xb8, 0x63, 0xfb, 0xcf, 0x6c, 0x46, 0x1e, 0x88, 0x04, - 0x30, 0x2c, 0x02, 0x01, 0x00, 0x30, 0x09, 0x06, 0x05, 0x2b, 0x0e, 0x03, - 0x02, 0x1a, 0x05, 0x00, 0x30, 0x06, 0x06, 0x04, 0x67, 0x2a, 0x01, 0x0c, - 0x04, 0x14, 0x13, 0xc1, 0x0c, 0xfc, 0xc8, 0x92, 0xd7, 0xde, 0x07, 0x1c, - 0x40, 0xde, 0x4f, 0xcd, 0x07, 0x5b, 0x68, 0x20, 0x5a, 0x6c} - }; - - static const u8 sha1selftestbufflen[SHA1_NUM_OF_SELF_TESTS] = { - 3, 56, 64, 94 - }; - - static const u8 sha1selftestexpres[SHA1_NUM_OF_SELF_TESTS][SHA_1_HASH_LENGTH] = { - {0xA9, 0x99, 0x3E, 0x36, - 0x47, 0x06, 0x81, 0x6A, - 0xBA, 0x3E, 0x25, 0x71, - 0x78, 0x50, 0xC2, 0x6C, - 0x9C, 0xD0, 0xD8, 0x9D}, - {0x84, 0x98, 0x3E, 0x44, - 0x1C, 0x3B, 0xD2, 0x6E, - 0xBA, 0xAE, 0x4A, 0xA1, - 0xF9, 0x51, 0x29, 0xE5, - 0xE5, 0x46, 0x70, 0xF1}, - {0xCF, 0x08, 0x00, 0xF7, - 0x64, 0x4A, 0xCE, 0x3C, - 0xB4, 0xC3, 0xFA, 0x33, - 0x38, 0x8D, 0x3B, 0xA0, - 0xEA, 0x3C, 0x8B, 0x6E}, - {0xc9, 0x84, 0x45, 0xc8, - 0x64, 0x04, 0xb1, 0xe3, - 0x3c, 0x6b, 0x0a, 0x8c, - 0x8b, 0x80, 0x94, 0xfc, - 0xf3, 0xc9, 0x98, 0xab} - }; - - /*------------------------------------------------------------------------*/ - /* SHA2 tests info */ - /*------------------------------------------------------------------------*/ - - static const u8 sha2selftestbuff[SHA2_NUM_OF_SELF_TESTS][100] = { - { "abc" }, - { "abcdbcdecdefdefgefghfghighijhijkijkljklmklmnlmnomnopnopq" }, - {'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', - 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', - 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', - 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', - 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', - 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', - 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', - 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', - 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', - 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a'} - }; - - static const u8 sha2selftestbufflen[SHA2_NUM_OF_SELF_TESTS] = { - 3, 56, 100 - }; - - static const u8 sha2selftestexpres[SHA2_NUM_OF_SELF_TESTS][SHA_2_HASH_LENGTH] = { - /* - * SHA-256 test vectors - */ - { 0xBA, 0x78, 0x16, 0xBF, 0x8F, 0x01, 0xCF, 0xEA, - 0x41, 0x41, 0x40, 0xDE, 0x5D, 0xAE, 0x22, 0x23, - 0xB0, 0x03, 0x61, 0xA3, 0x96, 0x17, 0x7A, 0x9C, - 0xB4, 0x10, 0xFF, 0x61, 0xF2, 0x00, 0x15, 0xAD }, - { 0x24, 0x8D, 0x6A, 0x61, 0xD2, 0x06, 0x38, 0xB8, - 0xE5, 0xC0, 0x26, 0x93, 0x0C, 0x3E, 0x60, 0x39, - 0xA3, 0x3C, 0xE4, 0x59, 0x64, 0xFF, 0x21, 0x67, - 0xF6, 0xEC, 0xED, 0xD4, 0x19, 0xDB, 0x06, 0xC1 }, - { 0xCD, 0xC7, 0x6E, 0x5C, 0x99, 0x14, 0xFB, 0x92, - 0x81, 0xA1, 0xC7, 0xE2, 0x84, 0xD7, 0x3E, 0x67, - 0xF1, 0x80, 0x9A, 0x48, 0xA4, 0x97, 0x20, 0x0E, - 0x04, 0x6D, 0x39, 0xCC, 0xC7, 0x11, 0x2C, 0xD0 }, - }; - - if (type == npcm_sha_type_sha1) { - /*--------------------------------------------------------------------*/ - /* SHA 1 TESTS */ - /*--------------------------------------------------------------------*/ - for (i = 0; i < SHA1_NUM_OF_SELF_TESTS; i++) { - if (i != 3) { - status = npcm_sha_calc(npcm_sha_type_sha1, sha1selftestbuff[i], sha1selftestbufflen[i], hashdigest); - npcm_sha_check(status); - } else { - SHA_Power(true); - SHA_Reset(); - status = SHA_Start(&handle, npcm_sha_type_sha1); - npcm_sha_check(status); - status = SHA_Update(&handle, sha1selftestbuff[i], 73); - npcm_sha_check(status); - status = SHA_Update(&handle, &sha1selftestbuff[i][73], sha1selftestbufflen[i] - 73); - npcm_sha_check(status); - status = SHA_Finish(&handle, hashdigest); - npcm_sha_check(status); - SHA_Power(false); - } - - if (memcmp(hashdigest, sha1selftestexpres[i], SHA_1_HASH_LENGTH)) - return -1; - } - - } else { - /*--------------------------------------------------------------------*/ - /* SHA 2 TESTS */ - /*--------------------------------------------------------------------*/ - for (i = 0; i < SHA2_NUM_OF_SELF_TESTS; i++) { - SHA_Power(true); - SHA_Reset(); - status = SHA_Start(&handle, npcm_sha_type_sha2); - npcm_sha_check(status); - if (i == 2) { - for (j = 0; j < 10000; j++) { //not working - status = SHA_Update(&handle, sha2selftestbuff[i], sha2selftestbufflen[i]); - npcm_sha_check(status); - } - } else { - status = SHA_Update(&handle, sha2selftestbuff[i], sha2selftestbufflen[i]); - npcm_sha_check(status); - } - - status = SHA_Finish(&handle, hashdigest); - npcm_sha_check(status); - SHA_Power(false); - if (memcmp(hashdigest, sha2selftestexpres[i], SHA_2_HASH_LENGTH)) - return -1; - - npcm_sha_calc(npcm_sha_type_sha2, sha2selftestbuff[i], sha2selftestbufflen[i], hashdigest); - if (memcmp(hashdigest, sha2selftestexpres[i], SHA_2_HASH_LENGTH)) - return -1; - } + if (!sha_priv->support_sha512) { + puts(" HW accelerator not support\n"); + return; } - - return 0; + puts(" using BMC HW accelerator\n"); + npcm_sha_calc(input, len, output, type_sha384); } -/*----------------------------------------------------------------------------*/ -/* Function: SHA_FlushLocalBuffer_l */ -/* */ -/* Parameters: */ -/* Returns: none */ -/* Side effects: */ -/* Description: This routine flush secrun buffer to SHA module */ -/*----------------------------------------------------------------------------*/ -static void SHA_FlushLocalBuffer_l(const u32 *buff) +void hw_sha256(const unsigned char *input, unsigned int len, + unsigned char *output, unsigned int chunk_sz) { - struct npcm_sha_regs *regs = sha_priv->regs; - u32 i; - - for (i = 0; i < (SHA_BLOCK_LENGTH / sizeof(u32)); i++) - writel(buff[i], ®s->hash_data_in); + puts(" using BMC HW accelerator\n"); + npcm_sha_calc(input, len, output, type_sha256); } -/*----------------------------------------------------------------------------*/ -/* Function: SHA_BusyWait_l */ -/* */ -/* Parameters: */ -/* Returns: 0 if no error was found or DEFS_STATUS_ERROR otherwise */ -/* Side effects: */ -/* Description: This routine wait for SHA unit to no longer be busy */ -/*----------------------------------------------------------------------------*/ -static int SHA_BusyWait_l(void) +void hw_sha1(const unsigned char *input, unsigned int len, + unsigned char *output, unsigned int chunk_sz) { - struct npcm_sha_regs *regs = sha_priv->regs; - u32 timeout = SHA_TIMEOUT; - - do { - if (timeout-- == 0) - return -ETIMEDOUT; - } while ((readb(®s->hash_ctr_sts) & HASH_CTR_STS_SHA_BUSY) - == HASH_CTR_STS_SHA_BUSY); - - return 0; + puts(" using BMC HW accelerator\n"); + npcm_sha_calc(input, len, output, type_sha1); } -/*----------------------------------------------------------------------------*/ -/* Function: SHA_GetShaDigest_l */ -/* */ -/* Parameters: hashDigest - buffer for the hash output. */ -/* type - SHA module type */ -/* Returns: none */ -/* Side effects: */ -/* Description: This routine copy the hash digest from the hardware */ -/* and into given buffer (in ram) */ -/*----------------------------------------------------------------------------*/ -static void SHA_GetShaDigest_l(u8 *hashdigest, u8 type) +int hw_sha_init(struct hash_algo *algo, void **ctxp) { - struct npcm_sha_regs *regs = sha_priv->regs; - u16 j; - u8 len = SHA_HASH_LENGTH(type) / sizeof(u32); - - // Copy Bytes from SHA module to given buffer - for (j = 0; j < len; j++) - ((u32 *)hashdigest)[j] = readl(®s->hash_dig[j]); -} + if (!strcmp("sha1", algo->name)) { + npcm_sha_init(type_sha1); + } else if (!strcmp("sha256", algo->name)) { + npcm_sha_init(type_sha256); + } else if (!strcmp("sha384", algo->name)) { + if (!sha_priv->support_sha512) + return -ENOTSUPP; + npcm_sha_init(type_sha384); + } else if (!strcmp("sha512", algo->name)) { + if (!sha_priv->support_sha512) + return -ENOTSUPP; + npcm_sha_init(type_sha512); + } else { + return -ENOTSUPP; + } -/*----------------------------------------------------------------------------*/ -/* Function: SHA_SetShaDigest_l */ -/* */ -/* Parameters: hashDigest - input buffer to set as hash digest */ -/* type - SHA module type */ -/* Returns: none */ -/* Side effects: */ -/* Description: This routine set the hash digest in the hardware from */ -/* a given buffer (in ram) */ -/*----------------------------------------------------------------------------*/ -static void SHA_SetShaDigest_l(const u32 *hashdigest, u8 type) -{ - struct npcm_sha_regs *regs = sha_priv->regs; - u16 j; - u8 len = SHA_HASH_LENGTH(type) / sizeof(u32); + printf("Using npcm SHA engine\n"); + npcm_sha_reset(); + npcm_sha_enable(true); - // Copy Bytes from given buffer to SHA module - for (j = 0; j < len; j++) - writel(hashdigest[j], ®s->hash_dig[j]); + return 0; } -/*----------------------------------------------------------------------------*/ -/* Function: SHA_SetBlock_l */ -/* */ -/* Parameters: data - data to copy */ -/* len - size of data */ -/* position - byte offset into the block at which data */ -/* should be placed */ -/* block - block buffer */ -/* Returns: none */ -/* Side effects: */ -/* Description: This routine load bytes into block buffer */ -/*----------------------------------------------------------------------------*/ -static void SHA_SetBlock_l(const u8 *data, u32 len, u16 position, u32 *block) +int hw_sha_update(struct hash_algo *algo, void *ctx, const void *buf, + unsigned int size, int is_last) { - u8 *dest = (u8 *)block; - - memcpy(dest + position, data, len); + return npcm_sha_update(buf, size); } -/*----------------------------------------------------------------------------*/ -/* Function: SHA_SetBlock_l */ -/* */ -/* Parameters: */ -/* len - size of data */ -/* position - byte offset into the block at which data */ -/* should be placed */ -/* block - block buffer */ -/* Returns: none */ -/* Side effects: */ -/* Description: This routine load zero's into the block buffer */ -/*----------------------------------------------------------------------------*/ -static void SHA_ClearBlock_l(u16 len, u16 position, u32 *block) +int hw_sha_finish(struct hash_algo *algo, void *ctx, void *dest_buf, + int size) { - u8 *dest = (u8 *)block; + int ret; - memset(dest + position, 0, len); -} + ret = npcm_sha_finish(dest_buf); + npcm_sha_enable(false); -/*----------------------------------------------------------------------------*/ -/* Function: SHA_SetLength32_l */ -/* */ -/* Parameters: */ -/* handlePtr - SHA processing handle pointer */ -/* block - block buffer */ -/* Returns: none */ -/* Side effects: */ -/* Description: This routine set the length of the hash's data */ -/* len is the 32-bit byte length of the message */ -/*lint -efunc(734,SHA_SetLength32_l) Supperess loss of percision lint warning */ -/*----------------------------------------------------------------------------*/ -static void SHA_SetLength32_l(struct SHA_HANDLE_T *handleptr, u32 *block) -{ - u16 *secrunbufferswappedptr = (u16 *)(void *)(block); - - secrunbufferswappedptr[(SHA_BLOCK_LENGTH / sizeof(u16)) - 1] = (u16) - ((handleptr->length0 << 3) << 8) | ((u16)(handleptr->length0 << 3) >> 8); - secrunbufferswappedptr[(SHA_BLOCK_LENGTH / sizeof(u16)) - 2] = (u16) - ((handleptr->length0 >> (16 - 3)) >> 8) | ((u16)(handleptr->length0 >> (16 - 3)) << 8); - secrunbufferswappedptr[(SHA_BLOCK_LENGTH / sizeof(u16)) - 3] = (u16) - ((handleptr->length1 << 3) << 8) | ((u16)(handleptr->length1 << 3) >> 8); - secrunbufferswappedptr[(SHA_BLOCK_LENGTH / sizeof(u16)) - 4] = (u16) - ((handleptr->length1 >> (16 - 3)) >> 8) | ((u16)(handleptr->length1 >> (16 - 3)) << 8); + return ret; } static int npcm_sha_bind(struct udevice *dev) @@ -870,12 +347,15 @@ static int npcm_sha_bind(struct udevice *dev) if (!sha_priv) return -ENOMEM; - sha_priv->regs = dev_remap_addr_index(dev, 0); - if (!sha_priv->regs) { + sha_priv->base = dev_read_addr_ptr(dev); + if (!sha_priv->base) { printf("Cannot find sha reg address, binding failed\n"); return -EINVAL; } + if (IS_ENABLED(CONFIG_ARCH_NPCM8XX)) + sha_priv->support_sha512 = true; + printf("SHA: NPCM SHA module bind OK\n"); return 0; diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c index 8e11d81..da341a2 100644 --- a/drivers/dma/ti/k3-udma.c +++ b/drivers/dma/ti/k3-udma.c @@ -11,6 +11,7 @@ #include <asm/io.h> #include <asm/bitops.h> #include <malloc.h> +#include <net.h> #include <linux/bitops.h> #include <linux/dma-mapping.h> #include <linux/sizes.h> @@ -2676,6 +2677,9 @@ int udma_prepare_rcv_buf(struct dma *dma, void *dst, size_t size) cppi5_hdesc_set_pktlen(desc_rx, size); cppi5_hdesc_attach_buf(desc_rx, dma_dst, size, dma_dst, size); + invalidate_dcache_range((unsigned long)dma_dst, + (unsigned long)(dma_dst + size)); + flush_dcache_range((unsigned long)desc_rx, ALIGN((unsigned long)desc_rx + uc->config.hdesc_size, ARCH_DMA_MINALIGN)); diff --git a/drivers/net/ti/am65-cpsw-nuss.c b/drivers/net/ti/am65-cpsw-nuss.c index 335c8be..c70b42f 100644 --- a/drivers/net/ti/am65-cpsw-nuss.c +++ b/drivers/net/ti/am65-cpsw-nuss.c @@ -327,6 +327,9 @@ static int am65_cpsw_start(struct udevice *dev) struct ti_udma_drv_chan_cfg_data *dma_rx_cfg_data; int ret, i; + if (common->started) + return 0; + ret = power_domain_on(&common->pwrdmn); if (ret) { dev_err(dev, "power_domain_on() failed %d\n", ret); @@ -358,7 +361,7 @@ static int am65_cpsw_start(struct udevice *dev) UDMA_RX_BUF_SIZE); if (ret) { dev_err(dev, "RX dma add buf failed %d\n", ret); - goto err_free_tx; + goto err_free_rx; } } @@ -487,6 +490,9 @@ static int am65_cpsw_send(struct udevice *dev, void *packet, int length) struct ti_udma_drv_packet_data packet_data; int ret; + if (!common->started) + return -ENETDOWN; + packet_data.pkt_type = AM65_CPSW_CPPI_PKT_TYPE; packet_data.dest_tag = priv->port_id; ret = dma_send(&common->dma_tx, packet, length, &packet_data); @@ -503,6 +509,9 @@ static int am65_cpsw_recv(struct udevice *dev, int flags, uchar **packetp) struct am65_cpsw_priv *priv = dev_get_priv(dev); struct am65_cpsw_common *common = priv->cpsw_common; + if (!common->started) + return -ENETDOWN; + /* try to receive a new packet */ return dma_receive(&common->dma_rx, (void **)packetp, NULL); } diff --git a/drivers/phy/phy-npcm-usb.c b/drivers/phy/phy-npcm-usb.c index 028fedf..2cca0f4 100644 --- a/drivers/phy/phy-npcm-usb.c +++ b/drivers/phy/phy-npcm-usb.c @@ -11,6 +11,7 @@ #include <dm/device_compat.h> #include <linux/bitfield.h> #include <linux/delay.h> +#include <dt-bindings/phy/nuvoton,npcm-usbphy.h> /* GCR Register Offsets */ #define GCR_INTCR3 0x9C @@ -31,14 +32,6 @@ #define USBPHY3SW_HOST2 FIELD_PREP(USBPHY3SW, 1) #define USBPHY3SW_DEV8_PHY3 FIELD_PREP(USBPHY3SW, 3) -enum controller_id { - UDC0_7, - UDC8, - UDC9, - USBH1, - USBH2, -}; - enum phy_id { PHY1 = 1, PHY2, @@ -46,13 +39,13 @@ enum phy_id { }; /* Phy Switch Settings */ -#define USBDPHY1 ((PHY1 << 8) | UDC0_7) /* Connect UDC0~7 to PHY1 */ -#define USBD8PHY1 ((PHY1 << 8) | UDC8) /* Connect UDC8 to PHY1 */ -#define USBD9PHY1 ((PHY1 << 8) | UDC9) /* Connect UDC9 to PHY1 */ -#define USBD9PHY2 ((PHY2 << 8) | UDC9) /* Connect UDC9 to PHY2 */ -#define USBH1PHY2 ((PHY2 << 8) | USBH1) /* Connect USBH1 to PHY2 */ -#define USBD8PHY3 ((PHY3 << 8) | UDC8) /* Connect UDC8 to PHY3 */ -#define USBH2PHY3 ((PHY3 << 8) | USBH2) /* Connect USBH2 to PHY3 */ +#define USBDPHY1 ((PHY1 << 8) | NPCM_UDC0_7) /* Connect UDC0~7 to PHY1 */ +#define USBD8PHY1 ((PHY1 << 8) | NPCM_UDC8) /* Connect UDC8 to PHY1 */ +#define USBD9PHY1 ((PHY1 << 8) | NPCM_UDC9) /* Connect UDC9 to PHY1 */ +#define USBD9PHY2 ((PHY2 << 8) | NPCM_UDC9) /* Connect UDC9 to PHY2 */ +#define USBH1PHY2 ((PHY2 << 8) | NPCM_USBH1) /* Connect USBH1 to PHY2 */ +#define USBD8PHY3 ((PHY3 << 8) | NPCM_UDC8) /* Connect UDC8 to PHY3 */ +#define USBH2PHY3 ((PHY3 << 8) | NPCM_USBH2) /* Connect USBH2 to PHY3 */ struct npcm_usbphy { struct regmap *syscon; @@ -152,12 +145,12 @@ static int npcm_usb_phy_exit(struct phy *phy) return 0; } -static int npcm_usb_phy_xlate(struct phy *phy, struct ofnode_phandle_args *args) +static int npcm_usb_phy_xlate(struct phy *phy, struct ofnode_phandle_args *args) { struct npcm_usbphy *priv = dev_get_priv(phy->dev); u16 phy_switch; - if (args->args_count < 1 || args->args[0] > USBH2) + if (args->args_count < 1 || args->args[0] > NPCM_MAX_USB_CTRL_ID) return -EINVAL; phy_switch = (priv->id << 8) | args->args[0]; diff --git a/drivers/pinctrl/pinctrl-uclass.c b/drivers/pinctrl/pinctrl-uclass.c index d9bda74..d9c7689 100644 --- a/drivers/pinctrl/pinctrl-uclass.c +++ b/drivers/pinctrl/pinctrl-uclass.c @@ -209,7 +209,7 @@ pinctrl_gpio_get_pinctrl_and_offset(struct udevice *dev, unsigned offset, pfc_base = args.args[1]; pfc_pins = args.args[2]; - if (offset >= gpio_offset && offset <= gpio_offset + pfc_pins) + if (offset >= gpio_offset && offset < gpio_offset + pfc_pins) break; } diff --git a/drivers/remoteproc/ti_k3_dsp_rproc.c b/drivers/remoteproc/ti_k3_dsp_rproc.c index 57fe103..076b6f2 100644 --- a/drivers/remoteproc/ti_k3_dsp_rproc.c +++ b/drivers/remoteproc/ti_k3_dsp_rproc.c @@ -338,7 +338,8 @@ static int k3_dsp_of_get_memories(struct udevice *dev) for (i = 0; i < dsp->num_mems; i++) { /* C71 cores only have a L1P Cache, there are no L1P SRAMs */ if (((device_is_compatible(dev, "ti,j721e-c71-dsp")) || - (device_is_compatible(dev, "ti,j721s2-c71-dsp"))) && + (device_is_compatible(dev, "ti,j721s2-c71-dsp")) || + (device_is_compatible(dev, "ti,am62a-c7xv-dsp"))) && !strcmp(mem_names[i], "l1pram")) { dsp->mem[i].bus_addr = FDT_ADDR_T_NONE; dsp->mem[i].dev_addr = FDT_ADDR_T_NONE; @@ -346,7 +347,14 @@ static int k3_dsp_of_get_memories(struct udevice *dev) dsp->mem[i].size = 0; continue; } - + if (device_is_compatible(dev, "ti,am62a-c7xv-dsp") && + !strcmp(mem_names[i], "l1dram")) { + dsp->mem[i].bus_addr = FDT_ADDR_T_NONE; + dsp->mem[i].dev_addr = FDT_ADDR_T_NONE; + dsp->mem[i].cpu_addr = NULL; + dsp->mem[i].size = 0; + continue; + } dsp->mem[i].bus_addr = dev_read_addr_size_name(dev, mem_names[i], (fdt_addr_t *)&dsp->mem[i].size); if (dsp->mem[i].bus_addr == FDT_ADDR_T_NONE) { @@ -458,6 +466,7 @@ static const struct udevice_id k3_dsp_ids[] = { { .compatible = "ti,j721e-c66-dsp", .data = (ulong)&c66_data, }, { .compatible = "ti,j721e-c71-dsp", .data = (ulong)&c71_data, }, { .compatible = "ti,j721s2-c71-dsp", .data = (ulong)&c71_data, }, + { .compatible = "ti,am62a-c7xv-dsp", .data = (ulong)&c71_data, }, {} }; diff --git a/drivers/remoteproc/ti_k3_r5f_rproc.c b/drivers/remoteproc/ti_k3_r5f_rproc.c index b55b1dc..74bf043 100644 --- a/drivers/remoteproc/ti_k3_r5f_rproc.c +++ b/drivers/remoteproc/ti_k3_r5f_rproc.c @@ -39,6 +39,8 @@ #define PROC_BOOT_CFG_FLAG_GEN_IGN_BOOTVECTOR 0x10000000 /* Available from J7200 SoCs onwards */ #define PROC_BOOT_CFG_FLAG_R5_MEM_INIT_DIS 0x00004000 +#define PROC_BOOT_CFG_FLAG_R5_SINGLE_CORE 0x00008000 + /* R5 TI-SCI Processor Control Flags */ #define PROC_BOOT_CTRL_FLAG_R5_CORE_HALT 0x00000001 @@ -54,6 +56,8 @@ enum cluster_mode { CLUSTER_MODE_SPLIT = 0, CLUSTER_MODE_LOCKSTEP, + CLUSTER_MODE_SINGLECPU, + CLUSTER_MODE_SINGLECORE, }; /** @@ -64,6 +68,7 @@ enum cluster_mode { struct k3_r5f_ip_data { bool tcm_is_double; bool tcm_ecc_autoinit; + bool is_single_core; }; /** @@ -598,8 +603,10 @@ static int k3_r5f_rproc_configure(struct k3_r5f_core *core) /* Sanity check for Lockstep mode */ lockstep_permitted = !!(sts & PROC_BOOT_STATUS_FLAG_R5_LOCKSTEP_PERMITTED); - if (cluster->mode && is_primary_core(core) && !lockstep_permitted) { - dev_err(core->dev, "LockStep mode not permitted on this device\n"); + if (cluster->mode == CLUSTER_MODE_LOCKSTEP && is_primary_core(core) && + !lockstep_permitted) { + dev_err(core->dev, "LockStep mode not permitted on this \ + device\n"); ret = -EINVAL; goto out; } @@ -614,6 +621,9 @@ static int k3_r5f_rproc_configure(struct k3_r5f_core *core) clr_cfg |= PROC_BOOT_CFG_FLAG_R5_LOCKSTEP; } + if (core->ipdata->is_single_core) + set_cfg = PROC_BOOT_CFG_FLAG_R5_SINGLE_CORE; + if (core->atcm_enable) set_cfg |= PROC_BOOT_CFG_FLAG_R5_ATCM_EN; else @@ -852,11 +862,19 @@ static int k3_r5f_remove(struct udevice *dev) static const struct k3_r5f_ip_data k3_data = { .tcm_is_double = false, .tcm_ecc_autoinit = false, + .is_single_core = false, }; static const struct k3_r5f_ip_data j7200_j721s2_data = { .tcm_is_double = true, .tcm_ecc_autoinit = true, + .is_single_core = false, +}; + +static const struct k3_r5f_ip_data am62_data = { + .tcm_is_double = false, + .tcm_ecc_autoinit = false, + .is_single_core = true, }; static const struct udevice_id k3_r5f_rproc_ids[] = { @@ -864,6 +882,7 @@ static const struct udevice_id k3_r5f_rproc_ids[] = { { .compatible = "ti,j721e-r5f", .data = (ulong)&k3_data, }, { .compatible = "ti,j7200-r5f", .data = (ulong)&j7200_j721s2_data, }, { .compatible = "ti,j721s2-r5f", .data = (ulong)&j7200_j721s2_data, }, + { .compatible = "ti,am62-r5f", .data = (ulong)&am62_data, }, {} }; @@ -886,6 +905,11 @@ static int k3_r5f_cluster_probe(struct udevice *dev) cluster->mode = dev_read_u32_default(dev, "ti,cluster-mode", CLUSTER_MODE_LOCKSTEP); + if (device_is_compatible(dev, "ti,am62-r5fss")) { + cluster->mode = CLUSTER_MODE_SINGLECORE; + return 0; + } + if (device_get_child_count(dev) != 2) { dev_err(dev, "Invalid number of R5 cores"); return -EINVAL; @@ -902,6 +926,7 @@ static const struct udevice_id k3_r5fss_ids[] = { { .compatible = "ti,j721e-r5fss"}, { .compatible = "ti,j7200-r5fss"}, { .compatible = "ti,j721s2-r5fss"}, + { .compatible = "ti,am62-r5fss"}, {} }; diff --git a/drivers/usb/dwc3/Kconfig b/drivers/usb/dwc3/Kconfig index c0c8c16..0100723 100644 --- a/drivers/usb/dwc3/Kconfig +++ b/drivers/usb/dwc3/Kconfig @@ -37,6 +37,20 @@ config SPL_USB_DWC3_GENERIC Select this for Xilinx ZynqMP and similar Platforms. This wrapper supports Host and Peripheral operation modes. +config SPL_USB_DWC3_AM62 + bool "TI AM62 USB wrapper" + depends on SPL_DM_USB && SPL_USB_DWC3_GENERIC && SPL_SYSCON + help + Select this for TI AM62 Platforms. + This wrapper supports Host and Peripheral operation modes. + +config USB_DWC3_AM62 + bool "TI AM62 USB wrapper" + depends on DM_USB && USB_DWC3_GENERIC && SYSCON + help + Select this for TI AM62 Platforms. + This wrapper supports Host and Peripheral operation modes. + config USB_DWC3_MESON_G12A bool "Amlogic Meson G12A USB wrapper" depends on DM_USB && USB_DWC3 && ARCH_MESON diff --git a/drivers/usb/dwc3/Makefile b/drivers/usb/dwc3/Makefile index 97b4f71..a46b682 100644 --- a/drivers/usb/dwc3/Makefile +++ b/drivers/usb/dwc3/Makefile @@ -6,6 +6,7 @@ dwc3-y := core.o obj-$(CONFIG_USB_DWC3_GADGET) += gadget.o ep0.o +obj-$(CONFIG_$(SPL_)USB_DWC3_AM62) += dwc3-am62.o obj-$(CONFIG_USB_DWC3_OMAP) += dwc3-omap.o obj-$(CONFIG_USB_DWC3_MESON_G12A) += dwc3-meson-g12a.o obj-$(CONFIG_USB_DWC3_MESON_GXL) += dwc3-meson-gxl.o diff --git a/drivers/usb/dwc3/dwc3-am62.c b/drivers/usb/dwc3/dwc3-am62.c new file mode 100644 index 0000000..9951960 --- /dev/null +++ b/drivers/usb/dwc3/dwc3-am62.c @@ -0,0 +1,125 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * TI AM62 specific glue layer for DWC3 + */ + +#include <dm.h> +#include <dm/device_compat.h> +#include <regmap.h> +#include <syscon.h> +#include <asm/io.h> + +#include "dwc3-generic.h" + +#define USBSS_MODE_CONTROL 0x1c +#define USBSS_PHY_CONFIG 0x8 +#define USBSS_PHY_VBUS_SEL_MASK GENMASK(2, 1) +#define USBSS_PHY_VBUS_SEL_SHIFT 1 +#define USBSS_MODE_VALID BIT(0) +#define PHY_PLL_REFCLK_MASK GENMASK(3, 0) +static const int dwc3_ti_am62_rate_table[] = { /* in KHZ */ + 9600, + 10000, + 12000, + 19200, + 20000, + 24000, + 25000, + 26000, + 38400, + 40000, + 58000, + 50000, + 52000, +}; + +static void dwc3_ti_am62_glue_configure(struct udevice *dev, int index, + enum usb_dr_mode mode) +{ + struct clk usb2_refclk; + int rate_code, i, ret; + unsigned long rate; + u32 reg; + void *usbss; + bool vbus_divider; + struct regmap *syscon; + struct ofnode_phandle_args args; + + usbss = dev_remap_addr_index(dev, 0); + if (IS_ERR(usbss)) { + dev_err(dev, "can't map IOMEM resource\n"); + return; + } + + ret = clk_get_by_name(dev, "ref", &usb2_refclk); + if (ret) { + dev_err(dev, "can't get usb2_refclk\n"); + return; + } + + /* Calculate the rate code */ + rate = clk_get_rate(&usb2_refclk); + rate /= 1000; /* To KHz */ + for (i = 0; i < ARRAY_SIZE(dwc3_ti_am62_rate_table); i++) { + if (dwc3_ti_am62_rate_table[i] == rate) + break; + } + + if (i == ARRAY_SIZE(dwc3_ti_am62_rate_table)) { + dev_err(dev, "unsupported usb2_refclk rate: %lu KHz\n", rate); + return; + } + + rate_code = i; + + /* Read the syscon property */ + syscon = syscon_regmap_lookup_by_phandle(dev, "ti,syscon-phy-pll-refclk"); + if (IS_ERR(syscon)) { + dev_err(dev, "unable to get ti,syscon-phy-pll-refclk regmap\n"); + return; + } + + ret = ofnode_parse_phandle_with_args(dev_ofnode(dev), "ti,syscon-phy-pll-refclk", NULL, 1, + 0, &args); + if (ret) + return; + + /* Program PHY PLL refclk by reading syscon property */ + ret = regmap_update_bits(syscon, args.args[0], PHY_PLL_REFCLK_MASK, rate_code); + if (ret) { + dev_err(dev, "failed to set phy pll reference clock rate\n"); + return; + } + + /* VBUS divider select */ + reg = readl(usbss + USBSS_PHY_CONFIG); + vbus_divider = dev_read_bool(dev, "ti,vbus-divider"); + if (vbus_divider) + reg |= 1 << USBSS_PHY_VBUS_SEL_SHIFT; + + writel(reg, usbss + USBSS_PHY_CONFIG); + + /* Set mode valid */ + reg = readl(usbss + USBSS_MODE_CONTROL); + reg |= USBSS_MODE_VALID; + writel(reg, usbss + USBSS_MODE_CONTROL); +} + +struct dwc3_glue_ops ti_am62_ops = { + .glue_configure = dwc3_ti_am62_glue_configure, +}; + +static const struct udevice_id dwc3_am62_match[] = { + { .compatible = "ti,am62-usb", .data = (ulong)&ti_am62_ops }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(dwc3_am62_wrapper) = { + .name = "dwc3-am62", + .id = UCLASS_SIMPLE_BUS, + .of_match = dwc3_am62_match, + .bind = dwc3_glue_bind, + .probe = dwc3_glue_probe, + .remove = dwc3_glue_remove, + .plat_auto = sizeof(struct dwc3_glue_data), +}; @@ -31,6 +31,7 @@ #include <ext4fs.h> #include <mmc.h> #include <scsi.h> +#include <virtio.h> #include <asm/global_data.h> DECLARE_GLOBAL_DATA_PTR; @@ -150,6 +151,10 @@ static int env_ext4_load(void) if (!strcmp(ifname, "scsi")) scsi_scan(true); #endif +#if defined(CONFIG_VIRTIO) + if (!strcmp(ifname, "virtio")) + virtio_init(); +#endif part = blk_get_device_part_str(ifname, dev_and_part, &dev_desc, &info, 1); @@ -17,6 +17,7 @@ #include <fat.h> #include <mmc.h> #include <scsi.h> +#include <virtio.h> #include <asm/cache.h> #include <asm/global_data.h> #include <linux/stddef.h> @@ -133,6 +134,10 @@ static int env_fat_load(void) if (!strcmp(CONFIG_ENV_FAT_INTERFACE, "scsi")) scsi_scan(true); #endif +#if defined(CONFIG_VIRTIO) + if (!strcmp(ifname, "virtio")) + virtio_init(); +#endif #endif part = blk_get_device_part_str(ifname, dev_and_part, &dev_desc, &info, 1); diff --git a/fs/zfs/zfs.c b/fs/zfs/zfs.c index c44e7ec..9906d55 100644 --- a/fs/zfs/zfs.c +++ b/fs/zfs/zfs.c @@ -16,6 +16,7 @@ #include <linux/time.h> #include <linux/ctype.h> #include <asm/byteorder.h> +#include <u-boot/zlib.h> #include "zfs_common.h" #include "div64.h" @@ -182,7 +183,8 @@ static int zlib_decompress(void *s, void *d, uint32_t slen, uint32_t dlen) { - if (zlib_decompress(s, d, slen, dlen) < 0) + uLongf z_dest_len = dlen; + if (uncompress(d, &z_dest_len, s, slen) != Z_OK) return ZFS_ERR_BAD_FS; return ZFS_ERR_NONE; } @@ -333,6 +335,12 @@ vdev_uberblock_compare(uberblock_t *ub1, uberblock_t *ub2) return 0; } +static inline int +is_supported_spa_version(uint64_t version) { + return version == FEATURES_SUPPORTED_SPA_VERSION || + (version > 0 && version <= SPA_VERSION); +} + /* * Three pieces of information are needed to verify an uberblock: the magic * number, the version number, and the checksum. @@ -354,14 +362,12 @@ uberblock_verify(uberblock_t *uber, int offset, struct zfs_data *data) return ZFS_ERR_BAD_FS; } - if (zfs_to_cpu64(uber->ub_magic, LITTLE_ENDIAN) == UBERBLOCK_MAGIC - && zfs_to_cpu64(uber->ub_version, LITTLE_ENDIAN) > 0 - && zfs_to_cpu64(uber->ub_version, LITTLE_ENDIAN) <= SPA_VERSION) + if (zfs_to_cpu64(uber->ub_magic, LITTLE_ENDIAN) == UBERBLOCK_MAGIC && + is_supported_spa_version(zfs_to_cpu64(uber->ub_version, LITTLE_ENDIAN))) endian = LITTLE_ENDIAN; - if (zfs_to_cpu64(uber->ub_magic, BIG_ENDIAN) == UBERBLOCK_MAGIC - && zfs_to_cpu64(uber->ub_version, BIG_ENDIAN) > 0 - && zfs_to_cpu64(uber->ub_version, BIG_ENDIAN) <= SPA_VERSION) + if (zfs_to_cpu64(uber->ub_magic, BIG_ENDIAN) == UBERBLOCK_MAGIC && + is_supported_spa_version(zfs_to_cpu64(uber->ub_version, BIG_ENDIAN))) endian = BIG_ENDIAN; if (endian == UNKNOWN_ENDIAN) { @@ -1787,7 +1793,7 @@ check_pool_label(struct zfs_data *data) return ZFS_ERR_BAD_FS; } - if (version > SPA_VERSION) { + if (!is_supported_spa_version(version)) { free(nvlist); printf("SPA version too new %llu > %llu\n", (unsigned long long) version, diff --git a/include/configs/j721s2_evm.h b/include/configs/j721s2_evm.h index 846cfa7..6186ec3 100644 --- a/include/configs/j721s2_evm.h +++ b/include/configs/j721s2_evm.h @@ -10,7 +10,6 @@ #define __CONFIG_J721S2_EVM_H #include <linux/sizes.h> -#include <config_distro_bootcmd.h> /* SPL Loader Configuration */ #if defined(CONFIG_TARGET_J721S2_A72_EVM) diff --git a/include/virtio.h b/include/virtio.h index 1ab0ec5..17f894a 100644 --- a/include/virtio.h +++ b/include/virtio.h @@ -21,6 +21,7 @@ #define __VIRTIO_H__ #include <virtio_types.h> +#include <dm/device.h> #include <linux/bitops.h> #include <linux/bug.h> #include <linux/typecheck.h> diff --git a/include/zfs/zfs.h b/include/zfs/zfs.h index 17b93c1..72d8745 100644 --- a/include/zfs/zfs.h +++ b/include/zfs/zfs.h @@ -15,6 +15,7 @@ * On-disk version number. */ #define SPA_VERSION 28ULL +#define FEATURES_SUPPORTED_SPA_VERSION 5000ULL /* * The following are configuration names used in the nvlist describing a pool's diff --git a/net/eth-uclass.c b/net/eth-uclass.c index 4e3933f..e34d7af 100644 --- a/net/eth-uclass.c +++ b/net/eth-uclass.c @@ -47,6 +47,8 @@ struct eth_uclass_priv { /* eth_errno - This stores the most recent failure code from DM functions */ static int eth_errno; +/* Are we currently in eth_init() or eth_halt()? */ +static bool in_init_halt; /* board-specific Ethernet Interface initializations. */ __weak int board_interface_eth_init(struct udevice *dev, @@ -284,11 +286,19 @@ U_BOOT_ENV_CALLBACK(ethaddr, on_ethaddr); int eth_init(void) { - char *ethact = env_get("ethact"); - char *ethrotate = env_get("ethrotate"); struct udevice *current = NULL; struct udevice *old_current; int ret = -ENODEV; + char *ethrotate; + char *ethact; + + if (in_init_halt) + return -EBUSY; + + in_init_halt = true; + + ethact = env_get("ethact"); + ethrotate = env_get("ethrotate"); /* * When 'ethrotate' variable is set to 'no' and 'ethact' variable @@ -297,8 +307,10 @@ int eth_init(void) if ((ethrotate != NULL) && (strcmp(ethrotate, "no") == 0)) { if (ethact) { current = eth_get_dev_by_name(ethact); - if (!current) - return -EINVAL; + if (!current) { + ret = -EINVAL; + goto end; + } } } @@ -306,7 +318,8 @@ int eth_init(void) current = eth_get_dev(); if (!current) { log_err("No ethernet found.\n"); - return -ENODEV; + ret = -ENODEV; + goto end; } } @@ -323,7 +336,8 @@ int eth_init(void) priv->state = ETH_STATE_ACTIVE; priv->running = true; - return 0; + ret = 0; + goto end; } } else { ret = eth_errno; @@ -343,6 +357,8 @@ int eth_init(void) current = eth_get_dev(); } while (old_current != current); +end: + in_init_halt = false; return ret; } @@ -351,17 +367,25 @@ void eth_halt(void) struct udevice *current; struct eth_device_priv *priv; + if (in_init_halt) + return; + + in_init_halt = true; + current = eth_get_dev(); if (!current) - return; + goto end; priv = dev_get_uclass_priv(current); if (!priv || !priv->running) - return; + goto end; eth_get_ops(current)->stop(current); priv->state = ETH_STATE_PASSIVE; priv->running = false; + +end: + in_init_halt = false; } int eth_is_active(struct udevice *dev) diff --git a/scripts/gen_compile_commands.py b/scripts/gen_compile_commands.py index fec513e..e746add 100755 --- a/scripts/gen_compile_commands.py +++ b/scripts/gen_compile_commands.py @@ -172,7 +172,7 @@ def process_line(root_directory, command_prefix, file_path): # escape the pound sign '#', either as '\#' or '$(pound)' (depending on the # kernel version). The compile_commands.json file is not interepreted # by Make, so this code replaces the escaped version with '#'. - prefix = command_prefix.replace('\#', '#').replace('$(pound)', '#') + prefix = command_prefix.replace(r'\#', '#').replace('$(pound)', '#') # Return the canonical path, eliminating any symbolic links encountered in the path. abs_path = os.path.realpath(os.path.join(root_directory, file_path)) |