diff options
28 files changed, 26 insertions, 68 deletions
diff --git a/arch/Kconfig b/arch/Kconfig index b6f9e17..d43d348 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -7,6 +7,25 @@ config HAVE_ARCH_IOREMAP config NEEDS_MANUAL_RELOC bool +config SYS_CACHE_SHIFT_4 + bool + +config SYS_CACHE_SHIFT_5 + bool + +config SYS_CACHE_SHIFT_6 + bool + +config SYS_CACHE_SHIFT_7 + bool + +config SYS_CACHELINE_SIZE + int + default 128 if SYS_CACHE_SHIFT_7 + default 64 if SYS_CACHE_SHIFT_6 + default 32 if SYS_CACHE_SHIFT_5 + default 16 if SYS_CACHE_SHIFT_4 + config LINKER_LIST_ALIGN int default 32 if SANDBOX @@ -29,6 +48,7 @@ config ARC select DM select HAVE_PRIVATE_LIBGCC select SUPPORT_OF_CONTROL + select SYS_CACHE_SHIFT_7 select TIMER config ARM @@ -44,6 +64,7 @@ config M68K select NEEDS_MANUAL_RELOC select SYS_BOOT_GET_CMDLINE select SYS_BOOT_GET_KBD + select SYS_CACHE_SHIFT_4 select SUPPORT_OF_CONTROL config MICROBLAZE @@ -122,6 +143,7 @@ config SANDBOX select SPI select SUPPORT_OF_CONTROL select SYSRESET_CMD_POWEROFF + select SYS_CACHE_SHIFT_4 select IRQ select SUPPORT_EXTENSION_SCAN imply BITREVERSE @@ -188,6 +210,7 @@ config X86 select OF_CONTROL select PCI select SUPPORT_OF_CONTROL + select SYS_CACHE_SHIFT_6 select TIMER select USE_PRIVATE_LIBGCC select X86_TSC_TIMER diff --git a/arch/arc/include/asm/cache.h b/arch/arc/include/asm/cache.h index ab61846..a48e1ae 100644 --- a/arch/arc/include/asm/cache.h +++ b/arch/arc/include/asm/cache.h @@ -16,9 +16,6 @@ */ #define ARCH_DMA_MINALIGN 128 -/* CONFIG_SYS_CACHELINE_SIZE is used a lot in drivers */ -#define CONFIG_SYS_CACHELINE_SIZE ARCH_DMA_MINALIGN - #if defined(ARC_MMU_ABSENT) #define CONFIG_ARC_MMU_VER 0 #elif defined(CONFIG_ARC_MMU_V2) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index d692139..e478b90 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -332,21 +332,6 @@ config SYS_ARM_ARCH default 4 if CPU_SA1100 default 8 if ARM64 -config SYS_CACHE_SHIFT_5 - bool - -config SYS_CACHE_SHIFT_6 - bool - -config SYS_CACHE_SHIFT_7 - bool - -config SYS_CACHELINE_SIZE - int - default 128 if SYS_CACHE_SHIFT_7 - default 64 if SYS_CACHE_SHIFT_6 - default 32 if SYS_CACHE_SHIFT_5 - choice prompt "Select the ARM data write cache policy" default SYS_ARM_CACHE_WRITETHROUGH if TARGET_BCMCYGNUS || \ diff --git a/arch/mips/include/asm/cache.h b/arch/mips/include/asm/cache.h index 00696e6..e048533 100644 --- a/arch/mips/include/asm/cache.h +++ b/arch/mips/include/asm/cache.h @@ -6,18 +6,6 @@ #ifndef __MIPS_CACHE_H__ #define __MIPS_CACHE_H__ -#define L1_CACHE_SHIFT CONFIG_MIPS_L1_CACHE_SHIFT -#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) - -#define ARCH_DMA_MINALIGN (L1_CACHE_BYTES) - -/* - * CONFIG_SYS_CACHELINE_SIZE is still used in various drivers primarily for - * DMA buffer alignment. Satisfy those drivers by providing it as a synonym - * of ARCH_DMA_MINALIGN for now. - */ -#define CONFIG_SYS_CACHELINE_SIZE ARCH_DMA_MINALIGN - #ifndef __ASSEMBLY__ /** * mips_cache_probe() - Probe the properties of the caches diff --git a/arch/powerpc/include/asm/cache.h b/arch/powerpc/include/asm/cache.h index ac8eeb4..f753ddf 100644 --- a/arch/powerpc/include/asm/cache.h +++ b/arch/powerpc/include/asm/cache.h @@ -25,13 +25,6 @@ */ #define ARCH_DMA_MINALIGN L1_CACHE_BYTES -/* - * For compatibility reasons support the CONFIG_SYS_CACHELINE_SIZE too - */ -#ifndef CONFIG_SYS_CACHELINE_SIZE -#define CONFIG_SYS_CACHELINE_SIZE L1_CACHE_BYTES -#endif - #define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1)) #define L1_CACHE_PAGES 8 diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 4b0c3df..691ed11 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -22,9 +22,11 @@ config TARGET_SIFIVE_UNLEASHED config TARGET_SIFIVE_UNMATCHED bool "Support SiFive Unmatched Board" + select SYS_CACHE_SHIFT_6 config TARGET_SIPEED_MAIX bool "Support Sipeed Maix Board" + select SYS_CACHE_SHIFT_6 config TARGET_OPENPITON_RISCV64 bool "Support RISC-V cores on OpenPiton SoC" diff --git a/arch/sandbox/include/asm/cache.h b/arch/sandbox/include/asm/cache.h index 9348a13..609a835 100644 --- a/arch/sandbox/include/asm/cache.h +++ b/arch/sandbox/include/asm/cache.h @@ -19,6 +19,5 @@ #else #define ARCH_DMA_MINALIGN 16 #endif -#define CONFIG_SYS_CACHELINE_SIZE ARCH_DMA_MINALIGN #endif /* __SANDBOX_CACHE_H__ */ diff --git a/arch/x86/include/asm/cache.h b/arch/x86/include/asm/cache.h index 145b878..256a3c0 100644 --- a/arch/x86/include/asm/cache.h +++ b/arch/x86/include/asm/cache.h @@ -7,13 +7,8 @@ #define __X86_CACHE_H__ /* - * If CONFIG_SYS_CACHELINE_SIZE is defined use it for DMA alignment. Otherwise - * use 64-bytes, a safe default for x86. + * Use CONFIG_SYS_CACHELINE_SIZE (which is set to 64-bytes) for DMA alignment. */ -#ifndef CONFIG_SYS_CACHELINE_SIZE -#define CONFIG_SYS_CACHELINE_SIZE 64 -#endif - #define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE static inline void wbinvd(void) diff --git a/include/configs/M5208EVBE.h b/include/configs/M5208EVBE.h index 1b8312b..efd4d76 100644 --- a/include/configs/M5208EVBE.h +++ b/include/configs/M5208EVBE.h @@ -138,7 +138,6 @@ env/embedded.o(.text*); /* Cache Configuration */ -#define CONFIG_SYS_CACHELINE_SIZE 16 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ CONFIG_SYS_INIT_RAM_SIZE - 8) diff --git a/include/configs/M5235EVB.h b/include/configs/M5235EVB.h index d061f45..9a98854 100644 --- a/include/configs/M5235EVB.h +++ b/include/configs/M5235EVB.h @@ -154,7 +154,6 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CONFIG_SYS_CACHELINE_SIZE 16 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ CONFIG_SYS_INIT_RAM_SIZE - 8) diff --git a/include/configs/M5249EVB.h b/include/configs/M5249EVB.h index 1a1a110..eea718c 100644 --- a/include/configs/M5249EVB.h +++ b/include/configs/M5249EVB.h @@ -104,7 +104,6 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CONFIG_SYS_CACHELINE_SIZE 16 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ CONFIG_SYS_INIT_RAM_SIZE - 8) diff --git a/include/configs/M5253DEMO.h b/include/configs/M5253DEMO.h index 8ac0086..ad310e8 100644 --- a/include/configs/M5253DEMO.h +++ b/include/configs/M5253DEMO.h @@ -160,7 +160,6 @@ #endif /* Cache Configuration */ -#define CONFIG_SYS_CACHELINE_SIZE 16 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ CONFIG_SYS_INIT_RAM_SIZE - 8) diff --git a/include/configs/M5272C3.h b/include/configs/M5272C3.h index 2cdd436..e0dd5b4 100644 --- a/include/configs/M5272C3.h +++ b/include/configs/M5272C3.h @@ -134,7 +134,6 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CONFIG_SYS_CACHELINE_SIZE 16 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ CONFIG_SYS_INIT_RAM_SIZE - 8) diff --git a/include/configs/M5275EVB.h b/include/configs/M5275EVB.h index eb7823a..072d44a 100644 --- a/include/configs/M5275EVB.h +++ b/include/configs/M5275EVB.h @@ -147,7 +147,6 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CONFIG_SYS_CACHELINE_SIZE 16 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ CONFIG_SYS_INIT_RAM_SIZE - 8) diff --git a/include/configs/M5282EVB.h b/include/configs/M5282EVB.h index 6a50a25..7c0450d 100644 --- a/include/configs/M5282EVB.h +++ b/include/configs/M5282EVB.h @@ -142,7 +142,6 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CONFIG_SYS_CACHELINE_SIZE 16 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ CONFIG_SYS_INIT_RAM_SIZE - 8) diff --git a/include/configs/M53017EVB.h b/include/configs/M53017EVB.h index a063b92..349996e 100644 --- a/include/configs/M53017EVB.h +++ b/include/configs/M53017EVB.h @@ -158,7 +158,6 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CONFIG_SYS_CACHELINE_SIZE 16 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ CONFIG_SYS_INIT_RAM_SIZE - 8) diff --git a/include/configs/M5329EVB.h b/include/configs/M5329EVB.h index 4fc6d38..169f053 100644 --- a/include/configs/M5329EVB.h +++ b/include/configs/M5329EVB.h @@ -165,7 +165,6 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CONFIG_SYS_CACHELINE_SIZE 16 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ CONFIG_SYS_INIT_RAM_SIZE - 8) diff --git a/include/configs/M5373EVB.h b/include/configs/M5373EVB.h index 7a9240a..7f3a39a 100644 --- a/include/configs/M5373EVB.h +++ b/include/configs/M5373EVB.h @@ -167,7 +167,6 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CONFIG_SYS_CACHELINE_SIZE 16 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ CONFIG_SYS_INIT_RAM_SIZE - 8) diff --git a/include/configs/amcore.h b/include/configs/amcore.h index 641d8fd..1eb9e5f 100644 --- a/include/configs/amcore.h +++ b/include/configs/amcore.h @@ -75,7 +75,6 @@ * This is a single unified instruction/data cache. * sdram - single region - no masks */ -#define CONFIG_SYS_CACHELINE_SIZE 16 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ CONFIG_SYS_INIT_RAM_SIZE - 8) diff --git a/include/configs/astro_mcf5373l.h b/include/configs/astro_mcf5373l.h index 2ea33e5..845dd5e 100644 --- a/include/configs/astro_mcf5373l.h +++ b/include/configs/astro_mcf5373l.h @@ -272,7 +272,6 @@ #endif /* Cache Configuration */ -#define CONFIG_SYS_CACHELINE_SIZE 16 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ CONFIG_SYS_INIT_RAM_SIZE - 8) diff --git a/include/configs/cobra5272.h b/include/configs/cobra5272.h index c859616..c4c7dcc 100644 --- a/include/configs/cobra5272.h +++ b/include/configs/cobra5272.h @@ -237,7 +237,6 @@ from which user programs will be started */ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CONFIG_SYS_CACHELINE_SIZE 16 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ CONFIG_SYS_INIT_RAM_SIZE - 8) diff --git a/include/configs/eb_cpu5282.h b/include/configs/eb_cpu5282.h index 77584fa..2fa057c 100644 --- a/include/configs/eb_cpu5282.h +++ b/include/configs/eb_cpu5282.h @@ -135,7 +135,6 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CONFIG_SYS_CACHELINE_SIZE 16 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ CONFIG_SYS_INIT_RAM_SIZE - 8) diff --git a/include/configs/mx7ulp_evk.h b/include/configs/mx7ulp_evk.h index 0c31030..f653742 100644 --- a/include/configs/mx7ulp_evk.h +++ b/include/configs/mx7ulp_evk.h @@ -33,8 +33,6 @@ /* UART */ #define LPUART_BASE LPUART4_RBASE -#define CONFIG_SYS_CACHELINE_SIZE 64 - /* Miscellaneous configurable options */ #define CONFIG_SYS_PROMPT "=> " #define CONFIG_SYS_CBSIZE 512 diff --git a/include/configs/rk3188_common.h b/include/configs/rk3188_common.h index 3bcc048..b7c001a 100644 --- a/include/configs/rk3188_common.h +++ b/include/configs/rk3188_common.h @@ -6,8 +6,6 @@ #ifndef __CONFIG_RK3188_COMMON_H #define __CONFIG_RK3188_COMMON_H -#define CONFIG_SYS_CACHELINE_SIZE 64 - #include <asm/arch-rockchip/hardware.h> #include "rockchip-common.h" diff --git a/include/configs/rk3368_common.h b/include/configs/rk3368_common.h index fbbb8cf..f83761a 100644 --- a/include/configs/rk3368_common.h +++ b/include/configs/rk3368_common.h @@ -8,8 +8,6 @@ #include "rockchip-common.h" -#define CONFIG_SYS_CACHELINE_SIZE 64 - #include <asm/arch-rockchip/hardware.h> #include <linux/sizes.h> diff --git a/include/configs/sifive-unmatched.h b/include/configs/sifive-unmatched.h index d63a5f6..f13e95f 100644 --- a/include/configs/sifive-unmatched.h +++ b/include/configs/sifive-unmatched.h @@ -38,8 +38,6 @@ #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit resources */ -#define CONFIG_SYS_CACHELINE_SIZE 64 - /* Environment options */ #ifndef CONFIG_SPL_BUILD diff --git a/include/configs/sipeed-maix.h b/include/configs/sipeed-maix.h index 0fbe8a5..00cc4b8 100644 --- a/include/configs/sipeed-maix.h +++ b/include/configs/sipeed-maix.h @@ -12,7 +12,6 @@ /* Start just below the second bank so we don't clobber it during reloc */ #define CONFIG_SYS_INIT_SP_ADDR 0x803FFFFF #define CONFIG_SYS_MALLOC_LEN SZ_128K -#define CONFIG_SYS_CACHELINE_SIZE 64 #define CONFIG_SYS_SDRAM_BASE 0x80000000 #define CONFIG_SYS_SDRAM_SIZE SZ_8M diff --git a/include/configs/stmark2.h b/include/configs/stmark2.h index da162cb..a2c466e 100644 --- a/include/configs/stmark2.h +++ b/include/configs/stmark2.h @@ -132,7 +132,6 @@ #endif /* Cache Configuration */ -#define CONFIG_SYS_CACHELINE_SIZE 16 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ CONFIG_SYS_INIT_RAM_SIZE - 8) #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ |