diff options
384 files changed, 50983 insertions, 1622 deletions
diff --git a/.azure-pipelines.yml b/.azure-pipelines.yml new file mode 100644 index 0000000..d476d8d --- /dev/null +++ b/.azure-pipelines.yml @@ -0,0 +1,420 @@ +variables: + windows_vm: vs2015-win2012r2 + ubuntu_vm: ubuntu-18.04 + ci_runner_image: trini/u-boot-gitlab-ci-runner:bionic-20190912.1-03Oct2019 + # Add '-u 0' options for Azure pipelines, otherwise we get "permission + # denied" error when it tries to "useradd -m -u 1001 vsts_azpcontainer", + # since our $(ci_runner_image) user is not root. + container_option: -u 0 + work_dir: /u + +jobs: + - job: tools_only_windows + displayName: 'Ensure host tools build for Windows' + pool: + vmImage: $(windows_vm) + strategy: + matrix: + i686: + MSYS_DIR: msys32 + BASE_REPO: msys2-ci-base-i686 + x86_64: + MSYS_DIR: msys64 + BASE_REPO: msys2-ci-base + steps: + - script: | + git clone https://github.com/msys2/$(BASE_REPO).git %CD:~0,2%\$(MSYS_DIR) + displayName: 'Install MSYS2' + - script: | + set PATH=%CD:~0,2%\$(MSYS_DIR)\usr\bin;C:\Windows\system32;C:\Windows;C:\Windows\System32\Wbem + %CD:~0,2%\$(MSYS_DIR)\usr\bin\pacman --noconfirm -Syyuu + displayName: 'Update MSYS2' + - script: | + set PATH=%CD:~0,2%\$(MSYS_DIR)\usr\bin;C:\Windows\system32;C:\Windows;C:\Windows\System32\Wbem + %CD:~0,2%\$(MSYS_DIR)\usr\bin\pacman --noconfirm --needed -S make gcc bison diffutils openssl-devel + displayName: 'Install Toolchain' + - script: | + set PATH=C:\Windows\system32;C:\Windows;C:\Windows\System32\Wbem + echo make tools-only_defconfig tools-only NO_SDL=1 > build-tools.sh + %CD:~0,2%\$(MSYS_DIR)\usr\bin\bash -lc "bash build-tools.sh" + displayName: 'Build Host Tools' + env: + # Tell MSYS2 we need a POSIX emulation layer + MSYSTEM: MSYS + # Tell MSYS2 not to ‘cd’ our startup directory to HOME + CHERE_INVOKING: yes + + - job: cppcheck + displayName: 'Static code analysis with cppcheck' + pool: + vmImage: $(ubuntu_vm) + container: + image: $(ci_runner_image) + options: $(container_option) + steps: + - script: cppcheck --force --quiet --inline-suppr . + + - job: todo + displayName: 'Search for TODO within source tree' + pool: + vmImage: $(ubuntu_vm) + container: + image: $(ci_runner_image) + options: $(container_option) + steps: + - script: grep -r TODO . + - script: grep -r FIXME . + - script: grep -r HACK . | grep -v HACKKIT + + - job: sloccount + displayName: 'Some statistics about the code base' + pool: + vmImage: $(ubuntu_vm) + container: + image: $(ci_runner_image) + options: $(container_option) + steps: + - script: sloccount . + + - job: maintainers + displayName: 'Ensure all configs have MAINTAINERS entries' + pool: + vmImage: $(ubuntu_vm) + container: + image: $(ci_runner_image) + options: $(container_option) + steps: + - script: | + if [ `./tools/genboardscfg.py -f 2>&1 | wc -l` -ne 0 ]; then exit 1; fi + + - job: tools_only + displayName: 'Ensure host tools build' + pool: + vmImage: $(ubuntu_vm) + container: + image: $(ci_runner_image) + options: $(container_option) + steps: + - script: | + make tools-only_config tools-only -j$(nproc) + + - job: envtools + displayName: 'Ensure env tools build' + pool: + vmImage: $(ubuntu_vm) + container: + image: $(ci_runner_image) + options: $(container_option) + steps: + - script: | + make tools-only_config envtools -j$(nproc) + + - job: utils + displayName: 'Run binman, buildman, dtoc and patman testsuites' + pool: + vmImage: $(ubuntu_vm) + steps: + - script: | + cat << EOF > build.sh + set -ex + cd ${WORK_DIR} + EOF + cat << "EOF" >> build.sh + git config --global user.name "Azure Pipelines" + git config --global user.email bmeng.cn@gmail.com + export USER=azure + virtualenv /tmp/venv + . /tmp/venv/bin/activate + pip install pyelftools + export UBOOT_TRAVIS_BUILD_DIR=/tmp/.bm-work/sandbox_spl + export PYTHONPATH=${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc/pylibfdt + export PATH=${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc:${PATH} + ./tools/buildman/buildman -o /tmp -P sandbox_spl + ./tools/binman/binman --toolpath ${UBOOT_TRAVIS_BUILD_DIR}/tools test + ./tools/buildman/buildman -t + ./tools/dtoc/dtoc -t + ./tools/patman/patman --test + EOF + cat build.sh + # We cannot use "container" like other jobs above, as buildman + # seems to hang forever with pre-configured "container" environment + docker run -v $PWD:$(work_dir) $(ci_runner_image) /bin/bash $(work_dir)/build.sh + + - job: test_py + displayName: 'test.py' + pool: + vmImage: $(ubuntu_vm) + strategy: + matrix: + sandbox: + TEST_PY_BD: "sandbox" + BUILDMAN: "^sandbox$" + sandbox_spl: + TEST_PY_BD: "sandbox_spl" + TEST_PY_TEST_SPEC: "test_ofplatdata" + BUILDMAN: "^sandbox_spl$" + sandbox_flattree: + TEST_PY_BD: "sandbox_flattree" + BUILDMAN: "^sandbox_flattree$" + evb_ast2500: + TEST_PY_BD: "evb-ast2500" + TEST_PY_ID: "--id qemu" + BUILDMAN: "^evb-ast2500$" + vexpress_ca15_tc2: + TEST_PY_BD: "vexpress_ca15_tc2" + TEST_PY_ID: "--id qemu" + BUILDMAN: "^vexpress_ca15_tc2$" + vexpress_ca9x4: + TEST_PY_BD: "vexpress_ca9x4" + TEST_PY_ID: "--id qemu" + BUILDMAN: "^vexpress_ca9x4$" + integratorcp_cm926ejs: + TEST_PY_BD: "integratorcp_cm926ejs" + TEST_PY_ID: "--id qemu" + TEST_PY_TEST_SPEC: "not sleep" + BUILDMAN: "^integratorcp_cm926ejs$" + qemu_arm: + TEST_PY_BD: "qemu_arm" + TEST_PY_TEST_SPEC: "not sleep" + BUILDMAN: "^qemu_arm$" + qemu_arm64: + TEST_PY_BD: "qemu_arm64" + TEST_PY_TEST_SPEC: "not sleep" + BUILDMAN: "^qemu_arm64$" + qemu_mips: + TEST_PY_BD: "qemu_mips" + TEST_PY_TEST_SPEC: "not sleep" + BUILDMAN: "^qemu_mips$" + qemu_mipsel: + TEST_PY_BD: "qemu_mipsel" + TEST_PY_TEST_SPEC: "not sleep" + BUILDMAN: "^qemu_mipsel$" + qemu_mips64: + TEST_PY_BD: "qemu_mips64" + TEST_PY_TEST_SPEC: "not sleep" + BUILDMAN: "^qemu_mips64$" + qemu_mips64el: + TEST_PY_BD: "qemu_mips64el" + TEST_PY_TEST_SPEC: "not sleep" + BUILDMAN: "^qemu_mips64el$" + qemu_ppce500: + TEST_PY_BD: "qemu-ppce500" + TEST_PY_TEST_SPEC: "not sleep" + BUILDMAN: "^qemu-ppce500$" + qemu_riscv64: + TEST_PY_BD: "qemu-riscv64" + TEST_PY_TEST_SPEC: "not sleep" + BUILDMAN: "^qemu-riscv64$" + qemu_x86: + TEST_PY_BD: "qemu-x86" + TEST_PY_TEST_SPEC: "not sleep" + BUILDMAN: "^qemu-x86$" + qemu_x86_64: + TEST_PY_BD: "qemu-x86_64" + TEST_PY_TEST_SPEC: "not sleep" + BUILDMAN: "^qemu-x86_64$" + zynq_zc702: + TEST_PY_BD: "zynq_zc702" + TEST_PY_ID: "--id qemu" + TEST_PY_TEST_SPEC: "not sleep" + BUILDMAN: "^zynq_zc702$" + xilinx_versal_virt: + TEST_PY_BD: "xilinx_versal_virt" + TEST_PY_ID: "--id qemu" + TEST_PY_TEST_SPEC: "not sleep" + BUILDMAN: "^xilinx_versal_virt$" + xtfpga: + TEST_PY_BD: "xtfpga" + TEST_PY_ID: "--id qemu" + TEST_PY_TEST_SPEC: "not sleep" + BUILDMAN: "^xtfpga$" + steps: + - script: | + cat << EOF > test.sh + set -ex + # make environment variables available as tests are running inside a container + export WORK_DIR="${WORK_DIR}" + export TEST_PY_BD="${TEST_PY_BD}" + export TEST_PY_ID="${TEST_PY_ID}" + export TEST_PY_TEST_SPEC="${TEST_PY_TEST_SPEC}" + export BUILDMAN="${BUILDMAN}" + EOF + cat << "EOF" >> test.sh + # the below corresponds to .gitlab-ci.yml "before_script" + cd ${WORK_DIR} + git clone --depth=1 git://github.com/swarren/uboot-test-hooks.git /tmp/uboot-test-hooks + ln -s travis-ci /tmp/uboot-test-hooks/bin/`hostname` + ln -s travis-ci /tmp/uboot-test-hooks/py/`hostname` + virtualenv /tmp/venv + . /tmp/venv/bin/activate + pip install pytest==2.8.7 + pip install python-subunit + pip install coverage + grub-mkimage --prefix=\"\" -o ~/grub_x86.efi -O i386-efi normal echo lsefimmap lsefi lsefisystab efinet tftp minicmd + grub-mkimage --prefix=\"\" -o ~/grub_x64.efi -O x86_64-efi normal echo lsefimmap lsefi lsefisystab efinet tftp minicmd + mkdir ~/grub2-arm + cd ~/grub2-arm; wget -O - http://download.opensuse.org/ports/armv7hl/distribution/leap/42.2/repo/oss/suse/armv7hl/grub2-arm-efi-2.02~beta2-87.1.armv7hl.rpm | rpm2cpio | cpio -di + mkdir ~/grub2-arm64 + cd ~/grub2-arm64; wget -O - http://download.opensuse.org/ports/aarch64/distribution/leap/42.2/repo/oss/suse/aarch64/grub2-arm64-efi-2.02~beta2-87.1.aarch64.rpm | rpm2cpio | cpio -di + # the below corresponds to .gitlab-ci.yml "script" + cd ${WORK_DIR} + if [[ "${BUILDMAN}" != "" ]]; then + ret=0; + tools/buildman/buildman -o /tmp -P -E ${BUILDMAN} ${OVERRIDE} || ret=$?; + if [[ $ret -ne 0 && $ret -ne 129 ]]; then + tools/buildman/buildman -o /tmp -sdeP ${BUILDMAN}; + exit $ret; + fi; + fi + export UBOOT_TRAVIS_BUILD_DIR=/tmp/.bm-work/${TEST_PY_BD}; + export PATH=/opt/qemu/bin:/tmp/uboot-test-hooks/bin:/usr/bin:/bin; + export PYTHONPATH=/tmp/uboot-test-hooks/py/travis-ci; + if [[ "${TEST_PY_BD}" != "" ]]; then + ./test/py/test.py --bd ${TEST_PY_BD} ${TEST_PY_ID} -k "${TEST_PY_TEST_SPEC:-not a_test_which_does_not_exist}" --build-dir "$UBOOT_TRAVIS_BUILD_DIR"; + ret=$?; + if [[ $ret -ne 0 ]]; then + exit $ret; + fi; + fi + # the below corresponds to .gitlab-ci.yml "after_script" + rm -rf ~/grub2* /tmp/uboot-test-hooks /tmp/venv + EOF + cat test.sh + # make current directory writeable to uboot user inside the container + # as sandbox testing need create files like spi flash images, etc. + # (TODO: clean up this in the future) + chmod 777 . + docker run -v $PWD:$(work_dir) $(ci_runner_image) /bin/bash $(work_dir)/test.sh + + - job: build_the_world + displayName: 'Build the World' + pool: + vmImage: $(ubuntu_vm) + strategy: + # Use almost the same target division in .travis.yml, only merged + # 4 small build jobs (arc/microblaze/nds32/xtensa) into one. + matrix: + arc_microblaze_nds32_xtensa: + BUILDMAN: "arc microblaze nds32 xtensa" + arm11_arm7_arm920t_arm946es: + BUILDMAN: "arm11 arm7 arm920t arm946es" + arm926ejs: + BUILDMAN: "arm926ejs -x freescale,siemens,at91,kirkwood,spear,omap" + at91_non_armv7: + BUILDMAN: "at91 -x armv7" + at91_non_arm926ejs: + BUILDMAN: "at91 -x arm926ejs" + boundary_engicam_toradex: + BUILDMAN: "boundary engicam toradex" + arm_bcm: + BUILDMAN: "bcm -x mips" + nxp_arm32: + BUILDMAN: "freescale -x powerpc,m68k,aarch64" + nxp_aarch64_ls101x: + BUILDMAN: "freescale&aarch64&ls101" + nxp_aarch64_ls102x: + BUILDMAN: "freescale&aarch64&ls102" + nxp_aarch64_ls104x: + BUILDMAN: "freescale&aarch64&ls104" + nxp_aarch64_ls108x: + BUILDMAN: "freescale&aarch64&ls108" + nxp_aarch64_ls20xx: + BUILDMAN: "freescale&aarch64&ls20" + nxp_aarch64_lx216x: + BUILDMAN: "freescale&aarch64&lx216" + imx6: + BUILDMAN: "mx6 -x boundary,engicam,freescale,technexion,toradex" + imx: + BUILDMAN: "mx -x mx6,freescale,technexion,toradex" + keystone2_keystone3: + BUILDMAN: "k2 k3" + samsung_socfpga: + BUILDMAN: "samsung socfpga" + spear: + BUILDMAN: "spear" + sun4i: + BUILDMAN: "sun4i" + sun5i: + BUILDMAN: "sun5i" + sun6i: + BUILDMAN: "sun6i" + sun7i: + BUILDMAN: "sun7i" + sun8i_32bit: + BUILDMAN: "sun8i&armv7" + sun8i_64bit: + BUILDMAN: "sun8i&aarch64" + sun9i: + BUILDMAN: "sun9i" + sun50i: + BUILDMAN: "sun50i" + arm_catch_all: + BUILDMAN: "arm -x arm11,arm7,arm9,aarch64,at91,bcm,freescale,kirkwood,mvebu,siemens,tegra,uniphier,mx,samsung,sunxi,am33xx,omap,rockchip,toradex,socfpga,k2,k3,zynq" + sandbox_x86: + BUILDMAN: "sandbox x86" + technexion: + BUILDMAN: "technexion" + kirkwood: + BUILDMAN: "kirkwood" + mvebu: + BUILDMAN: "mvebu" + m68k: + BUILDMAN: "m68k" + mips: + BUILDMAN: "mips" + non_fsl_ppc: + BUILDMAN: "powerpc -x freescale" + mpc85xx_freescale: + BUILDMAN: "mpc85xx&freescale -x t208xrdb -x t4qds -x t102* -x p1_p2_rdb_pc -x p1010rdb -x corenet_ds -x b4860qds -x bsc91*" + t208xrdb_corenet_ds: + BUILDMAN: "t208xrdb corenet_ds" + fsl_ppc: + BUILDMAN: "t4qds b4860qds mpc83xx&freescale mpc86xx&freescale" + t102x: + BUILDMAN: "t102*" + p1_p2_rdb_pc: + BUILDMAN: "p1_p2_rdb_pc" + p1010rdb_bsc91: + BUILDMAN: "p1010rdb bsc91" + siemens: + BUILDMAN: "siemens" + tegra: + BUILDMAN: "tegra -x toradex" + am33xx_no_siemens: + BUILDMAN: "am33xx -x siemens" + omap: + BUILDMAN: "omap" + uniphier: + BUILDMAN: "uniphier" + aarch64_catch_all: + BUILDMAN: "aarch64 -x bcm,k3,tegra,ls1,ls2,mvebu,uniphier,sunxi,samsung,rockchip,versal,zynq" + rockchip: + BUILDMAN: "rockchip" + sh: + BUILDMAN: "sh -x arm" + zynq: + BUILDMAN: "zynq&armv7" + zynqmp_versal: + BUILDMAN: "versal|zynqmp&aarch64" + riscv: + BUILDMAN: "riscv" + steps: + - script: | + cat << EOF > build.sh + set -ex + cd ${WORK_DIR} + # make environment variables available as tests are running inside a container + export BUILDMAN="${BUILDMAN}" + EOF + cat << "EOF" >> build.sh + if [[ "${BUILDMAN}" != "" ]]; then + ret=0; + tools/buildman/buildman -o /tmp -P -E ${BUILDMAN} ${OVERRIDE} || ret=$?; + if [[ $ret -ne 0 && $ret -ne 129 ]]; then + tools/buildman/buildman -o /tmp -sdeP ${BUILDMAN}; + exit $ret; + fi; + fi + EOF + cat build.sh + docker run -v $PWD:$(work_dir) $(ci_runner_image) /bin/bash $(work_dir)/build.sh diff --git a/.gitattributes b/.gitattributes new file mode 100644 index 0000000..8560b79 --- /dev/null +++ b/.gitattributes @@ -0,0 +1,2 @@ +# Declare files that always have LF line endings on checkout +* text eol=lf diff --git a/.travis.yml b/.travis.yml index a3e7451..3aaed93 100644 --- a/.travis.yml +++ b/.travis.yml @@ -200,7 +200,7 @@ matrix: - BUILDMAN="freescale&aarch64&ls108" - name: "buildman NXP AArch64 LS20xx" env: - - BUILDMAN="freescale&aarch64&&ls20" + - BUILDMAN="freescale&aarch64&ls20" - name: "buildman NXP AArch64 LX216x" env: - BUILDMAN="freescale&aarch64&lx216" diff --git a/MAINTAINERS b/MAINTAINERS index a7c355c..42b5959 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -246,6 +246,7 @@ S: Maintained T: git https://gitlab.denx.de/u-boot/custodians/u-boot-atmel.git F: arch/arm/mach-at91/ F: board/atmel/ +F: drivers/misc/microchip_flexcom.c ARM OWL M: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> @@ -840,6 +841,11 @@ S: Maintained T: git https://gitlab.denx.de/u-boot/custodians/u-boot-ubi.git F: drivers/mtd/ubi/ +UFS +M: Faiz Abbas <faiz_abbas@ti.com> +S: Maintained +F: drivers/ufs/ + USB M: Marek Vasut <marex@denx.de> S: Maintained @@ -851,6 +857,7 @@ M: Bin Meng <bmeng.cn@gmail.com> S: Maintained T: git https://gitlab.denx.de/u-boot/custodians/u-boot-usb.git topic-xhci F: drivers/usb/host/xhci* +F: include/usb/xhci.h VIDEO M: Anatolij Gustschin <agust@denx.de> @@ -1,9 +1,9 @@ # SPDX-License-Identifier: GPL-2.0+ -VERSION = 2019 -PATCHLEVEL = 10 +VERSION = 2020 +PATCHLEVEL = 01 SUBLEVEL = -EXTRAVERSION = +EXTRAVERSION = -rc1 NAME = # *DOCUMENTATION* @@ -1276,10 +1276,21 @@ endif MKIMAGEFLAGS_u-boot-dtb.img = $(MKIMAGEFLAGS_u-boot.img) -MKIMAGEFLAGS_u-boot.kwb = -n $(srctree)/$(CONFIG_SYS_KWD_CONFIG:"%"=%) \ +# Some boards have the kwbimage.cfg file written in advance, while some +# other boards generate it on the fly during the build in the build tree. +# Let's check if the file exists in the build tree first, otherwise we +# fall back to use the one in the source tree. +KWD_CONFIG_FILE = $(shell \ + if [ -f $(objtree)/$(CONFIG_SYS_KWD_CONFIG:"%"=%) ]; then \ + echo -n $(objtree)/$(CONFIG_SYS_KWD_CONFIG:"%"=%); \ + else \ + echo -n $(srctree)/$(CONFIG_SYS_KWD_CONFIG:"%"=%); \ + fi) + +MKIMAGEFLAGS_u-boot.kwb = -n $(KWD_CONFIG_FILE) \ -T kwbimage -a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_TEXT_BASE) -MKIMAGEFLAGS_u-boot-spl.kwb = -n $(srctree)/$(CONFIG_SYS_KWD_CONFIG:"%"=%) \ +MKIMAGEFLAGS_u-boot-spl.kwb = -n $(KWD_CONFIG_FILE) \ -T kwbimage -a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_TEXT_BASE) \ $(if $(KEYDIR),-k $(KEYDIR)) @@ -1837,11 +1848,14 @@ checkarmreloc: u-boot false; \ fi -envtools: scripts_basic $(version_h) $(timestamp_h) +tools/version.h: include/version.h + $(call if_changed,copy) + +envtools: scripts_basic $(version_h) $(timestamp_h) tools/version.h $(Q)$(MAKE) $(build)=tools/env tools-only: export TOOLS_ONLY=y -tools-only: scripts_basic $(version_h) $(timestamp_h) +tools-only: scripts_basic $(version_h) $(timestamp_h) tools/version.h $(Q)$(MAKE) $(build)=tools tools-all: export HOST_TOOLS_ALL=y @@ -1869,7 +1883,7 @@ CLEAN_DIRS += $(MODVERDIR) \ $(foreach d, spl tpl, $(patsubst %,$d/%, \ $(filter-out include, $(shell ls -1 $d 2>/dev/null)))) -CLEAN_FILES += include/bmp_logo.h include/bmp_logo_data.h \ +CLEAN_FILES += include/bmp_logo.h include/bmp_logo_data.h tools/version.h \ boot* u-boot* MLO* SPL System.map fit-dtb.blob* # Directories & files removed with 'make mrproper' diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 75041ce..629c5e8 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1008,7 +1008,6 @@ config ARCH_VF610 config ARCH_ZYNQ bool "Xilinx Zynq based platform" - select BOARD_EARLY_INIT_F if WDT select CLK select CLK_ZYNQ select CPU_V7A diff --git a/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c b/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c index bb169aa..df64f54 100644 --- a/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c +++ b/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c @@ -68,12 +68,18 @@ static void __secure ls1_deepsleep_irq_cfg(void) ippdexpcr0 = in_be32(&rcpm->ippdexpcr0); /* - * Workaround: There is bug of register ippdexpcr1, when read it always - * returns zero, so its value is saved to a scrachpad register to be - * read, that is why we don't read it from register ippdexpcr1 itself. + * Workaround of errata A-008646 + * Errata states that read to register ippdexpcr1 always returns + * zero irrespective of what value is written into it. So its value + * is first saved to a spare register and then read from it */ - ippdexpcr1 = in_le32(&scfg->sparecr[7]); - out_be32(&rcpm->ippdexpcr1, ippdexpcr1); + ippdexpcr1 = in_be32(&scfg->sparecr[7]); + + /* + * To allow OCRAM to be used as wakeup source in deep sleep, + * do not power it down. + */ + out_be32(&rcpm->ippdexpcr1, ippdexpcr1 | RCPM_IPPDEXPCR1_OCRAM1); if (ippdexpcr0 & RCPM_IPPDEXPCR0_ETSEC) pmcintecr |= SCFG_PMCINTECR_ETSECRXG0 | diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index a5d0b53..8fd6c75 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -59,6 +59,9 @@ static struct cpu_type cpu_type_list[] = { CPU_TYPE_ENTRY(LS1026A, LS1026A, 2), CPU_TYPE_ENTRY(LS2040A, LS2040A, 4), CPU_TYPE_ENTRY(LS1012A, LS1012A, 1), + CPU_TYPE_ENTRY(LS1017A, LS1017A, 1), + CPU_TYPE_ENTRY(LS1018A, LS1018A, 1), + CPU_TYPE_ENTRY(LS1027A, LS1027A, 2), CPU_TYPE_ENTRY(LS1028A, LS1028A, 2), CPU_TYPE_ENTRY(LS1088A, LS1088A, 8), CPU_TYPE_ENTRY(LS1084A, LS1084A, 8), diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c index 19917b2..e993209 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c @@ -401,6 +401,26 @@ void fdt_fixup_remove_jr(void *blob) } #endif +#ifdef CONFIG_ARCH_LS1028A +static void fdt_disable_multimedia(void *blob, unsigned int svr) +{ + int off; + + if (IS_MULTIMEDIA_EN(svr)) + return; + + /* Disable eDP/LCD node */ + off = fdt_node_offset_by_compatible(blob, -1, "arm,mali-dp500"); + if (off != -FDT_ERR_NOTFOUND) + fdt_status_disabled(blob, off); + + /* Disable GPU node */ + off = fdt_node_offset_by_compatible(blob, -1, "fsl,ls1028a-gpu"); + if (off != -FDT_ERR_NOTFOUND) + fdt_status_disabled(blob, off); +} +#endif + void ft_cpu_setup(void *blob, bd_t *bd) { struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); @@ -462,4 +482,7 @@ void ft_cpu_setup(void *blob, bd_t *bd) #ifdef CONFIG_HAS_FEATURE_ENHANCED_MSI fdt_fixup_msi(blob); #endif +#ifdef CONFIG_ARCH_LS1028A + fdt_disable_multimedia(blob, svr); +#endif } diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 3fd34e3..1f1869e 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -627,10 +627,19 @@ void fsl_lsch2_early_init_f(void) #endif #endif /* Make SEC reads and writes snoopable */ +#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) + setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP | + SCFG_SNPCNFGCR_SECWRSNP | SCFG_SNPCNFGCR_USB1RDSNP | + SCFG_SNPCNFGCR_USB1WRSNP | SCFG_SNPCNFGCR_USB2RDSNP | + SCFG_SNPCNFGCR_USB2WRSNP | SCFG_SNPCNFGCR_USB3RDSNP | + SCFG_SNPCNFGCR_USB3WRSNP | SCFG_SNPCNFGCR_SATARDSNP | + SCFG_SNPCNFGCR_SATAWRSNP); +#else setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP | SCFG_SNPCNFGCR_SECWRSNP | SCFG_SNPCNFGCR_SATARDSNP | SCFG_SNPCNFGCR_SATAWRSNP); +#endif /* * Enable snoop requests and DVM message requests for diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 3b8dc2f..47978e7 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -250,9 +250,12 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \ avnet-ultra96-rev1.dtb \ avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0.dtb \ zynqmp-a2197-revA.dtb \ - zynqmp-a2197-g-revA.dtb \ - zynqmp-a2197-m-revA.dtb \ - zynqmp-a2197-p-revA.dtb \ + zynqmp-e-a2197-00-revA.dtb \ + zynqmp-g-a2197-00-revA.dtb \ + zynqmp-m-a2197-01-revA.dtb \ + zynqmp-m-a2197-02-revA.dtb \ + zynqmp-m-a2197-03-revA.dtb \ + zynqmp-p-a2197-00-revA.dtb \ zynqmp-mini.dtb \ zynqmp-mini-emmc0.dtb \ zynqmp-mini-emmc1.dtb \ @@ -268,6 +271,7 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \ zynqmp-zcu111-revA.dtb \ zynqmp-zcu1275-revA.dtb \ zynqmp-zcu1275-revB.dtb \ + zynqmp-zcu216-revA.dtb \ zynqmp-zc1232-revA.dtb \ zynqmp-zc1254-revA.dtb \ zynqmp-zc1751-xm015-dc1.dtb \ @@ -536,6 +540,7 @@ dtb-$(CONFIG_MACH_SUN50I) += \ sun50i-a64-nanopi-a64.dtb \ sun50i-a64-oceanic-5205-5inmfd.dtb \ sun50i-a64-olinuxino.dtb \ + sun50i-a64-olinuxino-emmc.dtb \ sun50i-a64-orangepi-win.dtb \ sun50i-a64-pine64-lts.dtb \ sun50i-a64-pine64-plus.dtb \ @@ -833,4 +838,4 @@ PHONY += dtbs dtbs: $(addprefix $(obj)/, $(dtb-y)) @: -clean-files := *.dtb *_HS +clean-files := *.dtb *.dtbo *_HS diff --git a/arch/arm/dts/dra7-evm-u-boot.dtsi b/arch/arm/dts/dra7-evm-u-boot.dtsi index badaebc..f06c701 100644 --- a/arch/arm/dts/dra7-evm-u-boot.dtsi +++ b/arch/arm/dts/dra7-evm-u-boot.dtsi @@ -32,3 +32,20 @@ &mmc2_iodelay_hs200_rev20_conf { u-boot,dm-spl; }; + +&omap_dwc3_1 { + u-boot,dm-spl; +}; + +&usb1 { + u-boot,dm-spl; + dr_mode = "peripheral"; +}; + +&usb2_phy1 { + u-boot,dm-spl; +}; + +&usb3_phy1 { + u-boot,dm-spl; +}; diff --git a/arch/arm/dts/dra71-evm-u-boot.dtsi b/arch/arm/dts/dra71-evm-u-boot.dtsi index f9da15f..b56d4fc 100644 --- a/arch/arm/dts/dra71-evm-u-boot.dtsi +++ b/arch/arm/dts/dra71-evm-u-boot.dtsi @@ -44,3 +44,20 @@ &mmc2_iodelay_hs200_rev20_conf { u-boot,dm-spl; }; + +&omap_dwc3_1 { + u-boot,dm-spl; +}; + +&usb1 { + u-boot,dm-spl; + dr_mode = "peripheral"; +}; + +&usb2_phy1 { + u-boot,dm-spl; +}; + +&usb3_phy1 { + u-boot,dm-spl; +}; diff --git a/arch/arm/dts/dra72-evm-revc-u-boot.dtsi b/arch/arm/dts/dra72-evm-revc-u-boot.dtsi index f9da15f..b56d4fc 100644 --- a/arch/arm/dts/dra72-evm-revc-u-boot.dtsi +++ b/arch/arm/dts/dra72-evm-revc-u-boot.dtsi @@ -44,3 +44,20 @@ &mmc2_iodelay_hs200_rev20_conf { u-boot,dm-spl; }; + +&omap_dwc3_1 { + u-boot,dm-spl; +}; + +&usb1 { + u-boot,dm-spl; + dr_mode = "peripheral"; +}; + +&usb2_phy1 { + u-boot,dm-spl; +}; + +&usb3_phy1 { + u-boot,dm-spl; +}; diff --git a/arch/arm/dts/dra72-evm-u-boot.dtsi b/arch/arm/dts/dra72-evm-u-boot.dtsi new file mode 100644 index 0000000..6c868f7 --- /dev/null +++ b/arch/arm/dts/dra72-evm-u-boot.dtsi @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ + */ + +#include "omap5-u-boot.dtsi" + +&omap_dwc3_1 { + u-boot,dm-spl; +}; + +&usb1 { + u-boot,dm-spl; + dr_mode = "peripheral"; +}; + +&usb2_phy1 { + u-boot,dm-spl; +}; + +&usb3_phy1 { + u-boot,dm-spl; +}; diff --git a/arch/arm/dts/dra76-evm-u-boot.dtsi b/arch/arm/dts/dra76-evm-u-boot.dtsi index f651f40..a4dfbe7 100644 --- a/arch/arm/dts/dra76-evm-u-boot.dtsi +++ b/arch/arm/dts/dra76-evm-u-boot.dtsi @@ -24,3 +24,20 @@ &mmc2_iodelay_hs200_conf { u-boot,dm-spl; }; + +&omap_dwc3_1 { + u-boot,dm-spl; +}; + +&usb1 { + u-boot,dm-spl; + dr_mode = "peripheral"; +}; + +&usb2_phy1 { + u-boot,dm-spl; +}; + +&usb3_phy1 { + u-boot,dm-spl; +}; diff --git a/arch/arm/dts/k3-am65.dtsi b/arch/arm/dts/k3-am65.dtsi index a1467a4..3ead944 100644 --- a/arch/arm/dts/k3-am65.dtsi +++ b/arch/arm/dts/k3-am65.dtsi @@ -74,6 +74,8 @@ <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, <0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>, <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, + <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, + <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, @@ -86,6 +88,8 @@ ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/ <0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>, /* First peripheral window */ <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */ + <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */ + <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */ <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP */ <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */ <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */ diff --git a/arch/arm/dts/k3-am654-base-board-ddr4-1600MHz.dtsi b/arch/arm/dts/k3-am654-base-board-ddr4-1600MTs.dtsi index e861cb7..d07aaea 100644 --- a/arch/arm/dts/k3-am654-base-board-ddr4-1600MHz.dtsi +++ b/arch/arm/dts/k3-am654-base-board-ddr4-1600MTs.dtsi @@ -1,15 +1,16 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ - * This file was generated by the AM65x_DRA80xM EMIF Tool: + * This file was generated by AM65x_DRA80xM_EMIF_Tool_1.98.xlsm * http://www.ti.com/lit/pdf/spracj0 * Configuration Parameters * Memory Type: DDR4 - * Data Rate: 1600 + * Data Rate: 1600 MT/s * ECC Enabled: No - * Data Width: 32 + * Data Width: 32 bits */ #define DDR_PLL_FREQUENCY 400000000 +#define DDRSS_V2H_CTL_REG 0x000073FF #define DDRCTL_MSTR 0x41040010 #define DDRCTL_RFSHCTL0 0x00210070 #define DDRCTL_ECCCFG0 0x00000000 @@ -32,10 +33,10 @@ #define DDRCTL_DRAMTMG5 0x04040302 #define DDRCTL_DRAMTMG6 0x00000004 #define DDRCTL_DRAMTMG7 0x00000404 -#define DDRCTL_DRAMTMG8 0x03030C05 +#define DDRCTL_DRAMTMG8 0x03030A05 #define DDRCTL_DRAMTMG9 0x00020208 #define DDRCTL_DRAMTMG10 0x001C180A -#define DDRCTL_DRAMTMG11 0x1106010E +#define DDRCTL_DRAMTMG11 0x0E06010E #define DDRCTL_DRAMTMG12 0x00020008 #define DDRCTL_DRAMTMG13 0x0B100002 #define DDRCTL_DRAMTMG14 0x00000000 @@ -47,7 +48,7 @@ #define DDRCTL_DFITMG1 0x000A0606 #define DDRCTL_DFITMG2 0x00000604 #define DDRCTL_DFIMISC 0x00000001 -#define DDRCTL_ADDRMAP0 0x001F1F1F +#define DDRCTL_ADDRMAP0 0x0000001F #define DDRCTL_ADDRMAP1 0x003F0808 #define DDRCTL_ADDRMAP2 0x00000000 #define DDRCTL_ADDRMAP3 0x00000000 @@ -83,13 +84,13 @@ #define DDRPHY_DCR 0x0000040C #define DDRPHY_DTPR0 0x041A0B06 #define DDRPHY_DTPR1 0x28140000 -#define DDRPHY_DTPR2 0x0034E300 -#define DDRPHY_DTPR3 0x02800800 +#define DDRPHY_DTPR2 0x0034E255 +#define DDRPHY_DTPR3 0x01D50800 #define DDRPHY_DTPR4 0x31180805 #define DDRPHY_DTPR5 0x00250B06 #define DDRPHY_DTPR6 0x00000505 #define DDRPHY_ZQCR 0x008A2A58 -#define DDRPHY_ZQ0PR0 0x000077DD +#define DDRPHY_ZQ0PR0 0x000077DD #define DDRPHY_ZQ1PR0 0x000077DD #define DDRPHY_MR0 0x00000214 #define DDRPHY_MR1 0x00000501 @@ -109,6 +110,8 @@ #define DDRPHY_DX8SL2PLLCR0 0x021c4000 #define DDRPHY_DTCR0 0x8000B1C7 #define DDRPHY_DTCR1 0x00010236 +#define DDRPHY_ACIOCR0 0x30070000 +#define DDRPHY_ACIOCR3 0x00000001 #define DDRPHY_ACIOCR5 0x04800000 #define DDRPHY_IOVCR0 0x0F0C0C0C #define DDRPHY_DX0GCR0 0x00000000 @@ -148,9 +151,12 @@ #define DDRPHY_DX3GTR0 0x00020002 #define DDRPHY_DX4GTR0 0x00020002 #define DDRPHY_ODTCR 0x00010000 -#define DDRPHY_DX8SL0IOCR 0x04800000 -#define DDRPHY_DX8SL1IOCR 0x04800000 -#define DDRPHY_DX8SL2IOCR 0x04800000 +#define DDRPHY_DX8SL0IOCR 0x74800000 +#define DDRPHY_DX8SL1IOCR 0x74800000 +#define DDRPHY_DX8SL2IOCR 0x74800000 #define DDRPHY_DX8SL0DXCTL2 0x00141830 #define DDRPHY_DX8SL1DXCTL2 0x00141830 #define DDRPHY_DX8SL2DXCTL2 0x00141830 +#define DDRPHY_DX8SL0DQSCTL 0x01264000 +#define DDRPHY_DX8SL1DQSCTL 0x01264000 +#define DDRPHY_DX8SL2DQSCTL 0x01264000 diff --git a/arch/arm/dts/k3-am654-ddr.dtsi b/arch/arm/dts/k3-am654-ddr.dtsi index 622a3ed..b228796 100644 --- a/arch/arm/dts/k3-am654-ddr.dtsi +++ b/arch/arm/dts/k3-am654-ddr.dtsi @@ -17,6 +17,10 @@ assigned-clock-rates = <DDR_PLL_FREQUENCY>; u-boot,dm-spl; + ti,ss-reg = < + DDRSS_V2H_CTL_REG + >; + ti,ctl-reg = < DDRCTL_DFIMISC DDRCTL_DFITMG0 @@ -132,12 +136,15 @@ DDRPHY_DX8SL0DXCTL2 DDRPHY_DX8SL0IOCR DDRPHY_DX8SL0PLLCR0 + DDRPHY_DX8SL0DQSCTL DDRPHY_DX8SL1DXCTL2 DDRPHY_DX8SL1IOCR DDRPHY_DX8SL1PLLCR0 + DDRPHY_DX8SL1DQSCTL DDRPHY_DX8SL2DXCTL2 DDRPHY_DX8SL2IOCR DDRPHY_DX8SL2PLLCR0 + DDRPHY_DX8SL2DQSCTL DDRPHY_DXCCR DDRPHY_ODTCR DDRPHY_PGCR0 @@ -168,6 +175,8 @@ >; ti,phy-ioctl = < + DDRPHY_ACIOCR0 + DDRPHY_ACIOCR3 DDRPHY_ACIOCR5 DDRPHY_IOVCR0 >; diff --git a/arch/arm/dts/k3-am654-r5-base-board.dts b/arch/arm/dts/k3-am654-r5-base-board.dts index e31ed4f..174d202 100644 --- a/arch/arm/dts/k3-am654-r5-base-board.dts +++ b/arch/arm/dts/k3-am654-r5-base-board.dts @@ -7,7 +7,7 @@ #include "k3-am654.dtsi" #include "k3-am654-base-board-u-boot.dtsi" -#include "k3-am654-base-board-ddr4-1600MHz.dtsi" +#include "k3-am654-base-board-ddr4-1600MTs.dtsi" #include "k3-am654-ddr.dtsi" / { diff --git a/arch/arm/dts/k3-j721e-ddr-evm-lp4-3733.dtsi b/arch/arm/dts/k3-j721e-ddr-evm-lp4-3733.dtsi new file mode 100644 index 0000000..135b619 --- /dev/null +++ b/arch/arm/dts/k3-j721e-ddr-evm-lp4-3733.dtsi @@ -0,0 +1,2195 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ + * This file was generated by the AM752x_DRA82x_TDA4x_DDRSS_RegConfigTool, Revision: 0.1.0 + * This file was generated on 09/06/2019 +*/ + +#define DDRSS_PLL_FHS_CNT 10 +#define DDRSS_PLL_FREQUENCY_1 933000000 +#define DDRSS_PLL_FREQUENCY_2 933000000 + +#define DDRSS_CTL_00_DATA 0x00000B00 +#define DDRSS_CTL_01_DATA 0x00000000 +#define DDRSS_CTL_02_DATA 0x00000000 +#define DDRSS_CTL_03_DATA 0x00000000 +#define DDRSS_CTL_04_DATA 0x00000000 +#define DDRSS_CTL_05_DATA 0x00000000 +#define DDRSS_CTL_06_DATA 0x00000000 +#define DDRSS_CTL_07_DATA 0x00002710 +#define DDRSS_CTL_08_DATA 0x000186A0 +#define DDRSS_CTL_09_DATA 0x00000005 +#define DDRSS_CTL_10_DATA 0x00000064 +#define DDRSS_CTL_11_DATA 0x0005B18F +#define DDRSS_CTL_12_DATA 0x0038EF90 +#define DDRSS_CTL_13_DATA 0x00000005 +#define DDRSS_CTL_14_DATA 0x00000E94 +#define DDRSS_CTL_15_DATA 0x0005B18F +#define DDRSS_CTL_16_DATA 0x0038EF90 +#define DDRSS_CTL_17_DATA 0x00000005 +#define DDRSS_CTL_18_DATA 0x00000E94 +#define DDRSS_CTL_19_DATA 0x01010000 +#define DDRSS_CTL_20_DATA 0x02011001 +#define DDRSS_CTL_21_DATA 0x02010000 +#define DDRSS_CTL_22_DATA 0x00020100 +#define DDRSS_CTL_23_DATA 0x0000000A +#define DDRSS_CTL_24_DATA 0x00000019 +#define DDRSS_CTL_25_DATA 0x00000000 +#define DDRSS_CTL_26_DATA 0x00000000 +#define DDRSS_CTL_27_DATA 0x02020200 +#define DDRSS_CTL_28_DATA 0x00004B4B +#define DDRSS_CTL_29_DATA 0x00100000 +#define DDRSS_CTL_30_DATA 0x00000000 +#define DDRSS_CTL_31_DATA 0x00000000 +#define DDRSS_CTL_32_DATA 0x00000000 +#define DDRSS_CTL_33_DATA 0x00000000 +#define DDRSS_CTL_34_DATA 0x040C0000 +#define DDRSS_CTL_35_DATA 0x10401040 +#define DDRSS_CTL_36_DATA 0x00050804 +#define DDRSS_CTL_37_DATA 0x09040008 +#define DDRSS_CTL_38_DATA 0x12000204 +#define DDRSS_CTL_39_DATA 0x1854007A +#define DDRSS_CTL_40_DATA 0x12003A26 +#define DDRSS_CTL_41_DATA 0x1854007A +#define DDRSS_CTL_42_DATA 0x20003A26 +#define DDRSS_CTL_43_DATA 0x000A0A09 +#define DDRSS_CTL_44_DATA 0x040006DB +#define DDRSS_CTL_45_DATA 0x1B130F04 +#define DDRSS_CTL_46_DATA 0x0E00FFCD +#define DDRSS_CTL_47_DATA 0x1B130F0E +#define DDRSS_CTL_48_DATA 0x0E00FFCD +#define DDRSS_CTL_49_DATA 0x0203040E +#define DDRSS_CTL_50_DATA 0x26040500 +#define DDRSS_CTL_51_DATA 0x08282628 +#define DDRSS_CTL_52_DATA 0x14000D0A +#define DDRSS_CTL_53_DATA 0x03010A0A +#define DDRSS_CTL_54_DATA 0x01010003 +#define DDRSS_CTL_55_DATA 0x044E4E08 +#define DDRSS_CTL_56_DATA 0x042B2B04 +#define DDRSS_CTL_57_DATA 0x00002B2B +#define DDRSS_CTL_58_DATA 0x00010100 +#define DDRSS_CTL_59_DATA 0x03010000 +#define DDRSS_CTL_60_DATA 0x00000E08 +#define DDRSS_CTL_61_DATA 0x000000BB +#define DDRSS_CTL_62_DATA 0x0000020B +#define DDRSS_CTL_63_DATA 0x00001C64 +#define DDRSS_CTL_64_DATA 0x0000020B +#define DDRSS_CTL_65_DATA 0x00001C64 +#define DDRSS_CTL_66_DATA 0x00000005 +#define DDRSS_CTL_67_DATA 0x00030000 +#define DDRSS_CTL_68_DATA 0x00830010 +#define DDRSS_CTL_69_DATA 0x00830386 +#define DDRSS_CTL_70_DATA 0x00400386 +#define DDRSS_CTL_71_DATA 0x00120103 +#define DDRSS_CTL_72_DATA 0x000E0005 +#define DDRSS_CTL_73_DATA 0x2908000E +#define DDRSS_CTL_74_DATA 0x05050129 +#define DDRSS_CTL_75_DATA 0x0401030A +#define DDRSS_CTL_76_DATA 0x041B0E0A +#define DDRSS_CTL_77_DATA 0x0E0A0401 +#define DDRSS_CTL_78_DATA 0x0001041B +#define DDRSS_CTL_79_DATA 0x000F000F +#define DDRSS_CTL_80_DATA 0x02190219 +#define DDRSS_CTL_81_DATA 0x02190219 +#define DDRSS_CTL_82_DATA 0x03050505 +#define DDRSS_CTL_83_DATA 0x03010303 +#define DDRSS_CTL_84_DATA 0x1C0A0E0A +#define DDRSS_CTL_85_DATA 0x04040E04 +#define DDRSS_CTL_86_DATA 0x1C0A0E0A +#define DDRSS_CTL_87_DATA 0x04040E04 +#define DDRSS_CTL_88_DATA 0x03010000 +#define DDRSS_CTL_89_DATA 0x00010000 +#define DDRSS_CTL_90_DATA 0x00000000 +#define DDRSS_CTL_91_DATA 0x00000000 +#define DDRSS_CTL_92_DATA 0x01000000 +#define DDRSS_CTL_93_DATA 0x80104002 +#define DDRSS_CTL_94_DATA 0x00000000 +#define DDRSS_CTL_95_DATA 0x00040005 +#define DDRSS_CTL_96_DATA 0x00000000 +#define DDRSS_CTL_97_DATA 0x00050000 +#define DDRSS_CTL_98_DATA 0x00000004 +#define DDRSS_CTL_99_DATA 0x00000000 +#define DDRSS_CTL_100_DATA 0x00040005 +#define DDRSS_CTL_101_DATA 0x00000000 +#define DDRSS_CTL_102_DATA 0x00002EC0 +#define DDRSS_CTL_103_DATA 0x00002EC0 +#define DDRSS_CTL_104_DATA 0x00002EC0 +#define DDRSS_CTL_105_DATA 0x00002EC0 +#define DDRSS_CTL_106_DATA 0x00002EC0 +#define DDRSS_CTL_107_DATA 0x00000000 +#define DDRSS_CTL_108_DATA 0x0000051D +#define DDRSS_CTL_109_DATA 0x00071900 +#define DDRSS_CTL_110_DATA 0x00071900 +#define DDRSS_CTL_111_DATA 0x00071900 +#define DDRSS_CTL_112_DATA 0x00071900 +#define DDRSS_CTL_113_DATA 0x00071900 +#define DDRSS_CTL_114_DATA 0x00000000 +#define DDRSS_CTL_115_DATA 0x0000C6BC +#define DDRSS_CTL_116_DATA 0x00071900 +#define DDRSS_CTL_117_DATA 0x00071900 +#define DDRSS_CTL_118_DATA 0x00071900 +#define DDRSS_CTL_119_DATA 0x00071900 +#define DDRSS_CTL_120_DATA 0x00071900 +#define DDRSS_CTL_121_DATA 0x00000000 +#define DDRSS_CTL_122_DATA 0x0000C6BC +#define DDRSS_CTL_123_DATA 0x00000000 +#define DDRSS_CTL_124_DATA 0x00000000 +#define DDRSS_CTL_125_DATA 0x00000000 +#define DDRSS_CTL_126_DATA 0x00000000 +#define DDRSS_CTL_127_DATA 0x00000000 +#define DDRSS_CTL_128_DATA 0x00000000 +#define DDRSS_CTL_129_DATA 0x00000000 +#define DDRSS_CTL_130_DATA 0x00000000 +#define DDRSS_CTL_131_DATA 0x0A030500 +#define DDRSS_CTL_132_DATA 0x00040A04 +#define DDRSS_CTL_133_DATA 0x0A090000 +#define DDRSS_CTL_134_DATA 0x0A090701 +#define DDRSS_CTL_135_DATA 0x0900000E +#define DDRSS_CTL_136_DATA 0x0907010A +#define DDRSS_CTL_137_DATA 0x00000E0A +#define DDRSS_CTL_138_DATA 0x07010A09 +#define DDRSS_CTL_139_DATA 0x000E0A09 +#define DDRSS_CTL_140_DATA 0x07000401 +#define DDRSS_CTL_141_DATA 0x00000000 +#define DDRSS_CTL_142_DATA 0x00000000 +#define DDRSS_CTL_143_DATA 0x00000000 +#define DDRSS_CTL_144_DATA 0x00000000 +#define DDRSS_CTL_145_DATA 0x00000000 +#define DDRSS_CTL_146_DATA 0x00000000 +#define DDRSS_CTL_147_DATA 0x00000000 +#define DDRSS_CTL_148_DATA 0x08080000 +#define DDRSS_CTL_149_DATA 0x01000000 +#define DDRSS_CTL_150_DATA 0x800000C0 +#define DDRSS_CTL_151_DATA 0x800000C0 +#define DDRSS_CTL_152_DATA 0x800000C0 +#define DDRSS_CTL_153_DATA 0x00000000 +#define DDRSS_CTL_154_DATA 0x00001500 +#define DDRSS_CTL_155_DATA 0x00000000 +#define DDRSS_CTL_156_DATA 0x00000001 +#define DDRSS_CTL_157_DATA 0x00000002 +#define DDRSS_CTL_158_DATA 0x0000100E +#define DDRSS_CTL_159_DATA 0x00000000 +#define DDRSS_CTL_160_DATA 0x00000000 +#define DDRSS_CTL_161_DATA 0x00000000 +#define DDRSS_CTL_162_DATA 0x00000000 +#define DDRSS_CTL_163_DATA 0x00000000 +#define DDRSS_CTL_164_DATA 0x000A0000 +#define DDRSS_CTL_165_DATA 0x000D0005 +#define DDRSS_CTL_166_DATA 0x000D0404 +#define DDRSS_CTL_167_DATA 0x00BB0176 +#define DDRSS_CTL_168_DATA 0x0E0E01D3 +#define DDRSS_CTL_169_DATA 0x017601D3 +#define DDRSS_CTL_170_DATA 0x01D300BB +#define DDRSS_CTL_171_DATA 0x01D30E0E +#define DDRSS_CTL_172_DATA 0x00000000 +#define DDRSS_CTL_173_DATA 0x00000000 +#define DDRSS_CTL_174_DATA 0x00000000 +#define DDRSS_CTL_175_DATA 0x36E40084 +#define DDRSS_CTL_176_DATA 0x330036E4 +#define DDRSS_CTL_177_DATA 0x00003333 +#define DDRSS_CTL_178_DATA 0x56000000 +#define DDRSS_CTL_179_DATA 0x27270056 +#define DDRSS_CTL_180_DATA 0x0F0F0000 +#define DDRSS_CTL_181_DATA 0x00000000 +#define DDRSS_CTL_182_DATA 0x00840606 +#define DDRSS_CTL_183_DATA 0x36E436E4 +#define DDRSS_CTL_184_DATA 0x33333300 +#define DDRSS_CTL_185_DATA 0x00000000 +#define DDRSS_CTL_186_DATA 0x00565600 +#define DDRSS_CTL_187_DATA 0x00002727 +#define DDRSS_CTL_188_DATA 0x00000F0F +#define DDRSS_CTL_189_DATA 0x06060000 +#define DDRSS_CTL_190_DATA 0x00000020 +#define DDRSS_CTL_191_DATA 0x00000000 +#define DDRSS_CTL_192_DATA 0x00000001 +#define DDRSS_CTL_193_DATA 0x00000000 +#define DDRSS_CTL_194_DATA 0x01000000 +#define DDRSS_CTL_195_DATA 0x00000001 +#define DDRSS_CTL_196_DATA 0x00000000 +#define DDRSS_CTL_197_DATA 0x00000000 +#define DDRSS_CTL_198_DATA 0x00000000 +#define DDRSS_CTL_199_DATA 0x00000000 +#define DDRSS_CTL_200_DATA 0x00000000 +#define DDRSS_CTL_201_DATA 0x00000000 +#define DDRSS_CTL_202_DATA 0x00000000 +#define DDRSS_CTL_203_DATA 0x00000000 +#define DDRSS_CTL_204_DATA 0x00000000 +#define DDRSS_CTL_205_DATA 0x00000000 +#define DDRSS_CTL_206_DATA 0x02000000 +#define DDRSS_CTL_207_DATA 0x01080101 +#define DDRSS_CTL_208_DATA 0x00000000 +#define DDRSS_CTL_209_DATA 0x00000000 +#define DDRSS_CTL_210_DATA 0x00000000 +#define DDRSS_CTL_211_DATA 0x00000000 +#define DDRSS_CTL_212_DATA 0x00000000 +#define DDRSS_CTL_213_DATA 0x00000000 +#define DDRSS_CTL_214_DATA 0x00000000 +#define DDRSS_CTL_215_DATA 0x00000000 +#define DDRSS_CTL_216_DATA 0x00000000 +#define DDRSS_CTL_217_DATA 0x00000000 +#define DDRSS_CTL_218_DATA 0x00000000 +#define DDRSS_CTL_219_DATA 0x00000000 +#define DDRSS_CTL_220_DATA 0x00000000 +#define DDRSS_CTL_221_DATA 0x00000000 +#define DDRSS_CTL_222_DATA 0x00001000 +#define DDRSS_CTL_223_DATA 0x006403E8 +#define DDRSS_CTL_224_DATA 0x00000000 +#define DDRSS_CTL_225_DATA 0x00000000 +#define DDRSS_CTL_226_DATA 0x00000000 +#define DDRSS_CTL_227_DATA 0x15110000 +#define DDRSS_CTL_228_DATA 0x00040C18 +#define DDRSS_CTL_229_DATA 0x00000000 +#define DDRSS_CTL_230_DATA 0x00000000 +#define DDRSS_CTL_231_DATA 0x00000000 +#define DDRSS_CTL_232_DATA 0x00000000 +#define DDRSS_CTL_233_DATA 0x00000000 +#define DDRSS_CTL_234_DATA 0x00000000 +#define DDRSS_CTL_235_DATA 0x00000000 +#define DDRSS_CTL_236_DATA 0x00000000 +#define DDRSS_CTL_237_DATA 0x00000000 +#define DDRSS_CTL_238_DATA 0x00000000 +#define DDRSS_CTL_239_DATA 0x00000000 +#define DDRSS_CTL_240_DATA 0x00000000 +#define DDRSS_CTL_241_DATA 0x00000000 +#define DDRSS_CTL_242_DATA 0x00030000 +#define DDRSS_CTL_243_DATA 0x00000000 +#define DDRSS_CTL_244_DATA 0x00000000 +#define DDRSS_CTL_245_DATA 0x00000000 +#define DDRSS_CTL_246_DATA 0x00000000 +#define DDRSS_CTL_247_DATA 0x00000000 +#define DDRSS_CTL_248_DATA 0x00000000 +#define DDRSS_CTL_249_DATA 0x00000000 +#define DDRSS_CTL_250_DATA 0x00000000 +#define DDRSS_CTL_251_DATA 0x00000000 +#define DDRSS_CTL_252_DATA 0x00000000 +#define DDRSS_CTL_253_DATA 0x00000000 +#define DDRSS_CTL_254_DATA 0x00000000 +#define DDRSS_CTL_255_DATA 0x00000000 +#define DDRSS_CTL_256_DATA 0x00000000 +#define DDRSS_CTL_257_DATA 0x01000200 +#define DDRSS_CTL_258_DATA 0x00320040 +#define DDRSS_CTL_259_DATA 0x00020008 +#define DDRSS_CTL_260_DATA 0x00400100 +#define DDRSS_CTL_261_DATA 0x0038074A +#define DDRSS_CTL_262_DATA 0x01000200 +#define DDRSS_CTL_263_DATA 0x074A0040 +#define DDRSS_CTL_264_DATA 0x00000038 +#define DDRSS_CTL_265_DATA 0x005E0003 +#define DDRSS_CTL_266_DATA 0x0100005E +#define DDRSS_CTL_267_DATA 0x00000000 +#define DDRSS_CTL_268_DATA 0x01010000 +#define DDRSS_CTL_269_DATA 0x00000202 +#define DDRSS_CTL_270_DATA 0x00000FFF +#define DDRSS_CTL_271_DATA 0x1FFF1000 +#define DDRSS_CTL_272_DATA 0x01FF0000 +#define DDRSS_CTL_273_DATA 0x000101FF +#define DDRSS_CTL_274_DATA 0xFFFF0B00 +#define DDRSS_CTL_275_DATA 0x01010001 +#define DDRSS_CTL_276_DATA 0x01010101 +#define DDRSS_CTL_277_DATA 0x01180101 +#define DDRSS_CTL_278_DATA 0x00030000 +#define DDRSS_CTL_279_DATA 0x00000000 +#define DDRSS_CTL_280_DATA 0x00000000 +#define DDRSS_CTL_281_DATA 0x00000000 +#define DDRSS_CTL_282_DATA 0x00000000 +#define DDRSS_CTL_283_DATA 0x00000000 +#define DDRSS_CTL_284_DATA 0x00000000 +#define DDRSS_CTL_285_DATA 0x00000000 +#define DDRSS_CTL_286_DATA 0x00040101 +#define DDRSS_CTL_287_DATA 0x04010100 +#define DDRSS_CTL_288_DATA 0x00000000 +#define DDRSS_CTL_289_DATA 0x00000000 +#define DDRSS_CTL_290_DATA 0x03030300 +#define DDRSS_CTL_291_DATA 0x00000001 +#define DDRSS_CTL_292_DATA 0x00000000 +#define DDRSS_CTL_293_DATA 0x00000000 +#define DDRSS_CTL_294_DATA 0x00000000 +#define DDRSS_CTL_295_DATA 0x00000000 +#define DDRSS_CTL_296_DATA 0x00000000 +#define DDRSS_CTL_297_DATA 0x00000000 +#define DDRSS_CTL_298_DATA 0x00000000 +#define DDRSS_CTL_299_DATA 0x00000000 +#define DDRSS_CTL_300_DATA 0x00000000 +#define DDRSS_CTL_301_DATA 0x00000000 +#define DDRSS_CTL_302_DATA 0x00000000 +#define DDRSS_CTL_303_DATA 0x00000000 +#define DDRSS_CTL_304_DATA 0x00000000 +#define DDRSS_CTL_305_DATA 0x00000000 +#define DDRSS_CTL_306_DATA 0x00000000 +#define DDRSS_CTL_307_DATA 0x00000000 +#define DDRSS_CTL_308_DATA 0x00000000 +#define DDRSS_CTL_309_DATA 0x00000000 +#define DDRSS_CTL_310_DATA 0x00000000 +#define DDRSS_CTL_311_DATA 0x00000000 +#define DDRSS_CTL_312_DATA 0x00000000 +#define DDRSS_CTL_313_DATA 0x01000000 +#define DDRSS_CTL_314_DATA 0x00020201 +#define DDRSS_CTL_315_DATA 0x01000101 +#define DDRSS_CTL_316_DATA 0x01010001 +#define DDRSS_CTL_317_DATA 0x00010101 +#define DDRSS_CTL_318_DATA 0x05090903 +#define DDRSS_CTL_319_DATA 0x0E081B1B +#define DDRSS_CTL_320_DATA 0x0009030E +#define DDRSS_CTL_321_DATA 0x0A0D030F +#define DDRSS_CTL_322_DATA 0x0A0D0306 +#define DDRSS_CTL_323_DATA 0x0D090006 +#define DDRSS_CTL_324_DATA 0x0100000D +#define DDRSS_CTL_325_DATA 0x07030701 +#define DDRSS_CTL_326_DATA 0x00000003 +#define DDRSS_CTL_327_DATA 0x00000000 +#define DDRSS_CTL_328_DATA 0x00010000 +#define DDRSS_CTL_329_DATA 0x00280D00 +#define DDRSS_CTL_330_DATA 0x00000001 +#define DDRSS_CTL_331_DATA 0x00030001 +#define DDRSS_CTL_332_DATA 0x00000000 +#define DDRSS_CTL_333_DATA 0x00000000 +#define DDRSS_CTL_334_DATA 0x00000000 +#define DDRSS_CTL_335_DATA 0x00000000 +#define DDRSS_CTL_336_DATA 0x00000000 +#define DDRSS_CTL_337_DATA 0x00000000 +#define DDRSS_CTL_338_DATA 0x00000000 +#define DDRSS_CTL_339_DATA 0x00000000 +#define DDRSS_CTL_340_DATA 0x01000000 +#define DDRSS_CTL_341_DATA 0x00000001 +#define DDRSS_CTL_342_DATA 0x00010100 +#define DDRSS_CTL_343_DATA 0x03030000 +#define DDRSS_CTL_344_DATA 0x00000000 +#define DDRSS_CTL_345_DATA 0x00000000 +#define DDRSS_CTL_346_DATA 0x00000000 +#define DDRSS_CTL_347_DATA 0x00000000 +#define DDRSS_CTL_348_DATA 0x00000000 +#define DDRSS_CTL_349_DATA 0x00000000 +#define DDRSS_CTL_350_DATA 0x00000000 +#define DDRSS_CTL_351_DATA 0x00000000 +#define DDRSS_CTL_352_DATA 0x00000000 +#define DDRSS_CTL_353_DATA 0x00000000 +#define DDRSS_CTL_354_DATA 0x00000000 +#define DDRSS_CTL_355_DATA 0x00000000 +#define DDRSS_CTL_356_DATA 0x00000000 +#define DDRSS_CTL_357_DATA 0x00000000 +#define DDRSS_CTL_358_DATA 0x00000000 +#define DDRSS_CTL_359_DATA 0x00000000 +#define DDRSS_CTL_360_DATA 0x000556AA +#define DDRSS_CTL_361_DATA 0x000AAAAA +#define DDRSS_CTL_362_DATA 0x000AA955 +#define DDRSS_CTL_363_DATA 0x00055555 +#define DDRSS_CTL_364_DATA 0x000B3133 +#define DDRSS_CTL_365_DATA 0x0004CD33 +#define DDRSS_CTL_366_DATA 0x0004CECC +#define DDRSS_CTL_367_DATA 0x000B32CC +#define DDRSS_CTL_368_DATA 0x00010300 +#define DDRSS_CTL_369_DATA 0x03000100 +#define DDRSS_CTL_370_DATA 0x00000000 +#define DDRSS_CTL_371_DATA 0x00000000 +#define DDRSS_CTL_372_DATA 0x00000000 +#define DDRSS_CTL_373_DATA 0x00000000 +#define DDRSS_CTL_374_DATA 0x00000000 +#define DDRSS_CTL_375_DATA 0x00000000 +#define DDRSS_CTL_376_DATA 0x00000000 +#define DDRSS_CTL_377_DATA 0x00010000 +#define DDRSS_CTL_378_DATA 0x00000404 +#define DDRSS_CTL_379_DATA 0x00000000 +#define DDRSS_CTL_380_DATA 0x00000000 +#define DDRSS_CTL_381_DATA 0x00000000 +#define DDRSS_CTL_382_DATA 0x00000000 +#define DDRSS_CTL_383_DATA 0x00000000 +#define DDRSS_CTL_384_DATA 0x00000000 +#define DDRSS_CTL_385_DATA 0x00000000 +#define DDRSS_CTL_386_DATA 0x00000000 +#define DDRSS_CTL_387_DATA 0x37371B00 +#define DDRSS_CTL_388_DATA 0x000A0000 +#define DDRSS_CTL_389_DATA 0x00000176 +#define DDRSS_CTL_390_DATA 0x00000200 +#define DDRSS_CTL_391_DATA 0x00000200 +#define DDRSS_CTL_392_DATA 0x00000200 +#define DDRSS_CTL_393_DATA 0x00000200 +#define DDRSS_CTL_394_DATA 0x00000462 +#define DDRSS_CTL_395_DATA 0x00000E9C +#define DDRSS_CTL_396_DATA 0x00000204 +#define DDRSS_CTL_397_DATA 0x000038C8 +#define DDRSS_CTL_398_DATA 0x00000200 +#define DDRSS_CTL_399_DATA 0x00000200 +#define DDRSS_CTL_400_DATA 0x00000200 +#define DDRSS_CTL_401_DATA 0x00000200 +#define DDRSS_CTL_402_DATA 0x0000AA58 +#define DDRSS_CTL_403_DATA 0x000237D0 +#define DDRSS_CTL_404_DATA 0x00000C12 +#define DDRSS_CTL_405_DATA 0x000038C8 +#define DDRSS_CTL_406_DATA 0x00000200 +#define DDRSS_CTL_407_DATA 0x00000200 +#define DDRSS_CTL_408_DATA 0x00000200 +#define DDRSS_CTL_409_DATA 0x00000200 +#define DDRSS_CTL_410_DATA 0x0000AA58 +#define DDRSS_CTL_411_DATA 0x000237D0 +#define DDRSS_CTL_412_DATA 0x02020C12 +#define DDRSS_CTL_413_DATA 0x03030202 +#define DDRSS_CTL_414_DATA 0x00000022 +#define DDRSS_CTL_415_DATA 0x00000000 +#define DDRSS_CTL_416_DATA 0x00000000 +#define DDRSS_CTL_417_DATA 0x00001403 +#define DDRSS_CTL_418_DATA 0x000007D0 +#define DDRSS_CTL_419_DATA 0x00000000 +#define DDRSS_CTL_420_DATA 0x00000000 +#define DDRSS_CTL_421_DATA 0x00030000 +#define DDRSS_CTL_422_DATA 0x0006001E +#define DDRSS_CTL_423_DATA 0x00190031 +#define DDRSS_CTL_424_DATA 0x00190031 +#define DDRSS_CTL_425_DATA 0x00000000 +#define DDRSS_CTL_426_DATA 0x00000000 +#define DDRSS_CTL_427_DATA 0x02000000 +#define DDRSS_CTL_428_DATA 0x01000404 +#define DDRSS_CTL_429_DATA 0x091A091A +#define DDRSS_CTL_430_DATA 0x00000105 +#define DDRSS_CTL_431_DATA 0x00010101 +#define DDRSS_CTL_432_DATA 0x00010101 +#define DDRSS_CTL_433_DATA 0x00010001 +#define DDRSS_CTL_434_DATA 0x00000101 +#define DDRSS_CTL_435_DATA 0x02000201 +#define DDRSS_CTL_436_DATA 0x02010000 +#define DDRSS_CTL_437_DATA 0x00000200 +#define DDRSS_CTL_438_DATA 0x22060000 +#define DDRSS_CTL_439_DATA 0x00000122 +#define DDRSS_CTL_440_DATA 0xFFFFFFFF +#define DDRSS_CTL_441_DATA 0xFFFFFFFF +#define DDRSS_CTL_442_DATA 0x00000000 +#define DDRSS_CTL_443_DATA 0x00000000 +#define DDRSS_CTL_444_DATA 0x00000000 +#define DDRSS_CTL_445_DATA 0x00000000 +#define DDRSS_CTL_446_DATA 0x00000000 +#define DDRSS_CTL_447_DATA 0x00000000 +#define DDRSS_CTL_448_DATA 0x00000000 +#define DDRSS_CTL_449_DATA 0x00000000 +#define DDRSS_CTL_450_DATA 0x00000000 +#define DDRSS_CTL_451_DATA 0x00000000 +#define DDRSS_CTL_452_DATA 0x00000000 +#define DDRSS_CTL_453_DATA 0x00000000 +#define DDRSS_CTL_454_DATA 0x00000000 +#define DDRSS_CTL_455_DATA 0x00000000 +#define DDRSS_CTL_456_DATA 0x00000000 +#define DDRSS_CTL_457_DATA 0x00000000 +#define DDRSS_CTL_458_DATA 0x00000000 + +#define DDRSS_PI_00_DATA 0x00000B00 +#define DDRSS_PI_01_DATA 0x00000000 +#define DDRSS_PI_02_DATA 0x00000000 +#define DDRSS_PI_03_DATA 0x00000000 +#define DDRSS_PI_04_DATA 0x00000000 +#define DDRSS_PI_05_DATA 0x00000101 +#define DDRSS_PI_06_DATA 0x00640000 +#define DDRSS_PI_07_DATA 0x00000001 +#define DDRSS_PI_08_DATA 0x00000000 +#define DDRSS_PI_09_DATA 0x00000000 +#define DDRSS_PI_10_DATA 0x00000000 +#define DDRSS_PI_11_DATA 0x00000000 +#define DDRSS_PI_12_DATA 0x00000007 +#define DDRSS_PI_13_DATA 0x00010002 +#define DDRSS_PI_14_DATA 0x0800000F +#define DDRSS_PI_15_DATA 0x00000103 +#define DDRSS_PI_16_DATA 0x00000005 +#define DDRSS_PI_17_DATA 0x00000000 +#define DDRSS_PI_18_DATA 0x00000000 +#define DDRSS_PI_19_DATA 0x00000000 +#define DDRSS_PI_20_DATA 0x00000000 +#define DDRSS_PI_21_DATA 0x00000000 +#define DDRSS_PI_22_DATA 0x00000000 +#define DDRSS_PI_23_DATA 0x00000000 +#define DDRSS_PI_24_DATA 0x00000000 +#define DDRSS_PI_25_DATA 0x00000000 +#define DDRSS_PI_26_DATA 0x00010100 +#define DDRSS_PI_27_DATA 0x00280A00 +#define DDRSS_PI_28_DATA 0x00000000 +#define DDRSS_PI_29_DATA 0x0F000000 +#define DDRSS_PI_30_DATA 0x00003200 +#define DDRSS_PI_31_DATA 0x00000000 +#define DDRSS_PI_32_DATA 0x00000000 +#define DDRSS_PI_33_DATA 0x01010102 +#define DDRSS_PI_34_DATA 0x00000000 +#define DDRSS_PI_35_DATA 0x000000AA +#define DDRSS_PI_36_DATA 0x00000055 +#define DDRSS_PI_37_DATA 0x000000B5 +#define DDRSS_PI_38_DATA 0x0000004A +#define DDRSS_PI_39_DATA 0x00000056 +#define DDRSS_PI_40_DATA 0x000000A9 +#define DDRSS_PI_41_DATA 0x000000A9 +#define DDRSS_PI_42_DATA 0x000000B5 +#define DDRSS_PI_43_DATA 0x00000000 +#define DDRSS_PI_44_DATA 0x00000000 +#define DDRSS_PI_45_DATA 0x000F0F00 +#define DDRSS_PI_46_DATA 0x00000019 +#define DDRSS_PI_47_DATA 0x000007D0 +#define DDRSS_PI_48_DATA 0x00000300 +#define DDRSS_PI_49_DATA 0x00000000 +#define DDRSS_PI_50_DATA 0x00000000 +#define DDRSS_PI_51_DATA 0x01000000 +#define DDRSS_PI_52_DATA 0x00010101 +#define DDRSS_PI_53_DATA 0x00000000 +#define DDRSS_PI_54_DATA 0x00030000 +#define DDRSS_PI_55_DATA 0x0F000000 +#define DDRSS_PI_56_DATA 0x00000017 +#define DDRSS_PI_57_DATA 0x00000000 +#define DDRSS_PI_58_DATA 0x00000000 +#define DDRSS_PI_59_DATA 0x00000000 +#define DDRSS_PI_60_DATA 0x0A0A140A +#define DDRSS_PI_61_DATA 0x10020101 +#define DDRSS_PI_62_DATA 0x00020805 +#define DDRSS_PI_63_DATA 0x01000404 +#define DDRSS_PI_64_DATA 0x00000000 +#define DDRSS_PI_65_DATA 0x00000000 +#define DDRSS_PI_66_DATA 0x00000101 +#define DDRSS_PI_67_DATA 0x0001010F +#define DDRSS_PI_68_DATA 0x00340000 +#define DDRSS_PI_69_DATA 0x00000000 +#define DDRSS_PI_70_DATA 0x00000000 +#define DDRSS_PI_71_DATA 0x00000000 +#define DDRSS_PI_72_DATA 0x01000000 +#define DDRSS_PI_73_DATA 0x00080100 +#define DDRSS_PI_74_DATA 0x02000200 +#define DDRSS_PI_75_DATA 0x01000100 +#define DDRSS_PI_76_DATA 0x01000000 +#define DDRSS_PI_77_DATA 0x02000200 +#define DDRSS_PI_78_DATA 0x00000200 +#define DDRSS_PI_79_DATA 0x00000000 +#define DDRSS_PI_80_DATA 0x00000000 +#define DDRSS_PI_81_DATA 0x00000000 +#define DDRSS_PI_82_DATA 0x00000000 +#define DDRSS_PI_83_DATA 0x00000000 +#define DDRSS_PI_84_DATA 0x00000000 +#define DDRSS_PI_85_DATA 0x00000000 +#define DDRSS_PI_86_DATA 0x00000000 +#define DDRSS_PI_87_DATA 0x00000000 +#define DDRSS_PI_88_DATA 0x00000000 +#define DDRSS_PI_89_DATA 0x00000000 +#define DDRSS_PI_90_DATA 0x00000000 +#define DDRSS_PI_91_DATA 0x00000400 +#define DDRSS_PI_92_DATA 0x02010000 +#define DDRSS_PI_93_DATA 0x00080003 +#define DDRSS_PI_94_DATA 0x00080000 +#define DDRSS_PI_95_DATA 0x00000001 +#define DDRSS_PI_96_DATA 0x00000000 +#define DDRSS_PI_97_DATA 0x0000AA00 +#define DDRSS_PI_98_DATA 0x00000000 +#define DDRSS_PI_99_DATA 0x00000000 +#define DDRSS_PI_100_DATA 0x00010000 +#define DDRSS_PI_101_DATA 0x00000000 +#define DDRSS_PI_102_DATA 0x00000000 +#define DDRSS_PI_103_DATA 0x00000000 +#define DDRSS_PI_104_DATA 0x00000000 +#define DDRSS_PI_105_DATA 0x00000000 +#define DDRSS_PI_106_DATA 0x00000000 +#define DDRSS_PI_107_DATA 0x00000000 +#define DDRSS_PI_108_DATA 0x00000000 +#define DDRSS_PI_109_DATA 0x00000000 +#define DDRSS_PI_110_DATA 0x00000000 +#define DDRSS_PI_111_DATA 0x00000000 +#define DDRSS_PI_112_DATA 0x00000000 +#define DDRSS_PI_113_DATA 0x00000000 +#define DDRSS_PI_114_DATA 0x00000000 +#define DDRSS_PI_115_DATA 0x00000000 +#define DDRSS_PI_116_DATA 0x00000000 +#define DDRSS_PI_117_DATA 0x00000000 +#define DDRSS_PI_118_DATA 0x00000000 +#define DDRSS_PI_119_DATA 0x00000000 +#define DDRSS_PI_120_DATA 0x00000000 +#define DDRSS_PI_121_DATA 0x00000000 +#define DDRSS_PI_122_DATA 0x00000000 +#define DDRSS_PI_123_DATA 0x00000000 +#define DDRSS_PI_124_DATA 0x00000000 +#define DDRSS_PI_125_DATA 0x00000008 +#define DDRSS_PI_126_DATA 0x00000000 +#define DDRSS_PI_127_DATA 0x00000000 +#define DDRSS_PI_128_DATA 0x00000000 +#define DDRSS_PI_129_DATA 0x00000000 +#define DDRSS_PI_130_DATA 0x00000000 +#define DDRSS_PI_131_DATA 0x00000000 +#define DDRSS_PI_132_DATA 0x00000000 +#define DDRSS_PI_133_DATA 0x00000000 +#define DDRSS_PI_134_DATA 0x00000002 +#define DDRSS_PI_135_DATA 0x00000000 +#define DDRSS_PI_136_DATA 0x00000000 +#define DDRSS_PI_137_DATA 0x0000000A +#define DDRSS_PI_138_DATA 0x00000019 +#define DDRSS_PI_139_DATA 0x00000100 +#define DDRSS_PI_140_DATA 0x00000000 +#define DDRSS_PI_141_DATA 0x00000000 +#define DDRSS_PI_142_DATA 0x00000000 +#define DDRSS_PI_143_DATA 0x00000000 +#define DDRSS_PI_144_DATA 0x01000000 +#define DDRSS_PI_145_DATA 0x00010003 +#define DDRSS_PI_146_DATA 0x02000101 +#define DDRSS_PI_147_DATA 0x01030001 +#define DDRSS_PI_148_DATA 0x00010400 +#define DDRSS_PI_149_DATA 0x06000105 +#define DDRSS_PI_150_DATA 0x01070001 +#define DDRSS_PI_151_DATA 0x00000000 +#define DDRSS_PI_152_DATA 0x00000000 +#define DDRSS_PI_153_DATA 0x00000000 +#define DDRSS_PI_154_DATA 0x00010001 +#define DDRSS_PI_155_DATA 0x00000000 +#define DDRSS_PI_156_DATA 0x00000000 +#define DDRSS_PI_157_DATA 0x00000000 +#define DDRSS_PI_158_DATA 0x00000000 +#define DDRSS_PI_159_DATA 0x00000401 +#define DDRSS_PI_160_DATA 0x00000000 +#define DDRSS_PI_161_DATA 0x00010000 +#define DDRSS_PI_162_DATA 0x00000000 +#define DDRSS_PI_163_DATA 0x26260100 +#define DDRSS_PI_164_DATA 0x00000034 +#define DDRSS_PI_165_DATA 0x0000005E +#define DDRSS_PI_166_DATA 0x0002005E +#define DDRSS_PI_167_DATA 0x02000200 +#define DDRSS_PI_168_DATA 0x40100C04 +#define DDRSS_PI_169_DATA 0x000E4010 +#define DDRSS_PI_170_DATA 0x000000BB +#define DDRSS_PI_171_DATA 0x0000020B +#define DDRSS_PI_172_DATA 0x00001C64 +#define DDRSS_PI_173_DATA 0x0000020B +#define DDRSS_PI_174_DATA 0x04001C64 +#define DDRSS_PI_175_DATA 0x01010404 +#define DDRSS_PI_176_DATA 0x00001501 +#define DDRSS_PI_177_DATA 0x00150015 +#define DDRSS_PI_178_DATA 0x01000100 +#define DDRSS_PI_179_DATA 0x00000100 +#define DDRSS_PI_180_DATA 0x00000000 +#define DDRSS_PI_181_DATA 0x01010101 +#define DDRSS_PI_182_DATA 0x00000101 +#define DDRSS_PI_183_DATA 0x00000000 +#define DDRSS_PI_184_DATA 0x00000000 +#define DDRSS_PI_185_DATA 0x12040000 +#define DDRSS_PI_186_DATA 0x0C0C0212 +#define DDRSS_PI_187_DATA 0x00040402 +#define DDRSS_PI_188_DATA 0x000C8034 +#define DDRSS_PI_189_DATA 0x001F0047 +#define DDRSS_PI_190_DATA 0x001F0047 +#define DDRSS_PI_191_DATA 0x01010101 +#define DDRSS_PI_192_DATA 0x0003000D +#define DDRSS_PI_193_DATA 0x000301D3 +#define DDRSS_PI_194_DATA 0x010001D3 +#define DDRSS_PI_195_DATA 0x000E000E +#define DDRSS_PI_196_DATA 0x01D40100 +#define DDRSS_PI_197_DATA 0x010001D4 +#define DDRSS_PI_198_DATA 0x01D401D4 +#define DDRSS_PI_199_DATA 0x32103200 +#define DDRSS_PI_200_DATA 0x01013210 +#define DDRSS_PI_201_DATA 0x0A070601 +#define DDRSS_PI_202_DATA 0x1C11090D +#define DDRSS_PI_203_DATA 0x1C110913 +#define DDRSS_PI_204_DATA 0x0000C013 +#define DDRSS_PI_205_DATA 0x00C01000 +#define DDRSS_PI_206_DATA 0x00C01000 +#define DDRSS_PI_207_DATA 0x00021000 +#define DDRSS_PI_208_DATA 0x0021000D +#define DDRSS_PI_209_DATA 0x002101D3 +#define DDRSS_PI_210_DATA 0x001101D3 +#define DDRSS_PI_211_DATA 0x32000056 +#define DDRSS_PI_212_DATA 0x00000101 +#define DDRSS_PI_213_DATA 0x005A0035 +#define DDRSS_PI_214_DATA 0x01013212 +#define DDRSS_PI_215_DATA 0x00003500 +#define DDRSS_PI_216_DATA 0x3212005A +#define DDRSS_PI_217_DATA 0x09000101 +#define DDRSS_PI_218_DATA 0x04010504 +#define DDRSS_PI_219_DATA 0x0400062B +#define DDRSS_PI_220_DATA 0x0A032001 +#define DDRSS_PI_221_DATA 0x262B0F0A +#define DDRSS_PI_222_DATA 0x00002819 +#define DDRSS_PI_223_DATA 0x5400E638 +#define DDRSS_PI_224_DATA 0x1B1C2007 +#define DDRSS_PI_225_DATA 0x262B0F13 +#define DDRSS_PI_226_DATA 0x00002819 +#define DDRSS_PI_227_DATA 0x5400E638 +#define DDRSS_PI_228_DATA 0x1B1C2007 +#define DDRSS_PI_229_DATA 0x00017613 +#define DDRSS_PI_230_DATA 0x00000E9C +#define DDRSS_PI_231_DATA 0x000038C8 +#define DDRSS_PI_232_DATA 0x000237D0 +#define DDRSS_PI_233_DATA 0x000038C8 +#define DDRSS_PI_234_DATA 0x000237D0 +#define DDRSS_PI_235_DATA 0x0219000F +#define DDRSS_PI_236_DATA 0x03030219 +#define DDRSS_PI_237_DATA 0x00271003 +#define DDRSS_PI_238_DATA 0x000186A0 +#define DDRSS_PI_239_DATA 0x00000005 +#define DDRSS_PI_240_DATA 0x00000064 +#define DDRSS_PI_241_DATA 0x0000000F +#define DDRSS_PI_242_DATA 0x0005B18F +#define DDRSS_PI_243_DATA 0x000186A0 +#define DDRSS_PI_244_DATA 0x00000005 +#define DDRSS_PI_245_DATA 0x00000E94 +#define DDRSS_PI_246_DATA 0x00000219 +#define DDRSS_PI_247_DATA 0x0005B18F +#define DDRSS_PI_248_DATA 0x000186A0 +#define DDRSS_PI_249_DATA 0x00000005 +#define DDRSS_PI_250_DATA 0x00000E94 +#define DDRSS_PI_251_DATA 0x01000219 +#define DDRSS_PI_252_DATA 0x00320040 +#define DDRSS_PI_253_DATA 0x00010008 +#define DDRSS_PI_254_DATA 0x074A0040 +#define DDRSS_PI_255_DATA 0x00010038 +#define DDRSS_PI_256_DATA 0x074A0040 +#define DDRSS_PI_257_DATA 0x00000338 +#define DDRSS_PI_258_DATA 0x005E005E +#define DDRSS_PI_259_DATA 0x00040404 +#define DDRSS_PI_260_DATA 0x00000055 +#define DDRSS_PI_261_DATA 0x55003C5A +#define DDRSS_PI_262_DATA 0x5A000000 +#define DDRSS_PI_263_DATA 0x0055003C +#define DDRSS_PI_264_DATA 0x3C5A0000 +#define DDRSS_PI_265_DATA 0x00005500 +#define DDRSS_PI_266_DATA 0x0C3C5A00 +#define DDRSS_PI_267_DATA 0x080F0E0D +#define DDRSS_PI_268_DATA 0x000B0A09 +#define DDRSS_PI_269_DATA 0x00030201 +#define DDRSS_PI_270_DATA 0x01000000 +#define DDRSS_PI_271_DATA 0x04020201 +#define DDRSS_PI_272_DATA 0x00080804 +#define DDRSS_PI_273_DATA 0x00000000 +#define DDRSS_PI_274_DATA 0x00000000 +#define DDRSS_PI_275_DATA 0x00330084 +#define DDRSS_PI_276_DATA 0x00160000 +#define DDRSS_PI_277_DATA 0x563336E4 +#define DDRSS_PI_278_DATA 0x00160F27 +#define DDRSS_PI_279_DATA 0x563336E4 +#define DDRSS_PI_280_DATA 0x00160F27 +#define DDRSS_PI_281_DATA 0x00330084 +#define DDRSS_PI_282_DATA 0x00160000 +#define DDRSS_PI_283_DATA 0x563336E4 +#define DDRSS_PI_284_DATA 0x00160F27 +#define DDRSS_PI_285_DATA 0x563336E4 +#define DDRSS_PI_286_DATA 0x00160F27 +#define DDRSS_PI_287_DATA 0x00330084 +#define DDRSS_PI_288_DATA 0x00160000 +#define DDRSS_PI_289_DATA 0x563336E4 +#define DDRSS_PI_290_DATA 0x00160F27 +#define DDRSS_PI_291_DATA 0x563336E4 +#define DDRSS_PI_292_DATA 0x00160F27 +#define DDRSS_PI_293_DATA 0x00330084 +#define DDRSS_PI_294_DATA 0x00160000 +#define DDRSS_PI_295_DATA 0x563336E4 +#define DDRSS_PI_296_DATA 0x00160F27 +#define DDRSS_PI_297_DATA 0x563336E4 +#define DDRSS_PI_298_DATA 0x00160F27 +#define DDRSS_PI_299_DATA 0x00000000 + +#define DDRSS_PHY_00_DATA 0x000004F0 +#define DDRSS_PHY_01_DATA 0x00000000 +#define DDRSS_PHY_02_DATA 0x00030200 +#define DDRSS_PHY_03_DATA 0x00000000 +#define DDRSS_PHY_04_DATA 0x00000000 +#define DDRSS_PHY_05_DATA 0x01030000 +#define DDRSS_PHY_06_DATA 0x00010000 +#define DDRSS_PHY_07_DATA 0x01030004 +#define DDRSS_PHY_08_DATA 0x01000000 +#define DDRSS_PHY_09_DATA 0x00000000 +#define DDRSS_PHY_10_DATA 0x00000000 +#define DDRSS_PHY_11_DATA 0x01000001 +#define DDRSS_PHY_12_DATA 0x00000100 +#define DDRSS_PHY_13_DATA 0x000800C0 +#define DDRSS_PHY_14_DATA 0x060100CC +#define DDRSS_PHY_15_DATA 0x00030066 +#define DDRSS_PHY_16_DATA 0x00000000 +#define DDRSS_PHY_17_DATA 0x00000001 +#define DDRSS_PHY_18_DATA 0x0000AAAA +#define DDRSS_PHY_19_DATA 0x00005555 +#define DDRSS_PHY_20_DATA 0x0000B5B5 +#define DDRSS_PHY_21_DATA 0x00004A4A +#define DDRSS_PHY_22_DATA 0x00005656 +#define DDRSS_PHY_23_DATA 0x0000A9A9 +#define DDRSS_PHY_24_DATA 0x0000A9A9 +#define DDRSS_PHY_25_DATA 0x0000B5B5 +#define DDRSS_PHY_26_DATA 0x00000000 +#define DDRSS_PHY_27_DATA 0x00000000 +#define DDRSS_PHY_28_DATA 0x2A000000 +#define DDRSS_PHY_29_DATA 0x00000808 +#define DDRSS_PHY_30_DATA 0x0F000000 +#define DDRSS_PHY_31_DATA 0x00000F0F +#define DDRSS_PHY_32_DATA 0x10200000 +#define DDRSS_PHY_33_DATA 0x0C002004 +#define DDRSS_PHY_34_DATA 0x00000000 +#define DDRSS_PHY_35_DATA 0x00000000 +#define DDRSS_PHY_36_DATA 0x55555555 +#define DDRSS_PHY_37_DATA 0xAAAAAAAA +#define DDRSS_PHY_38_DATA 0x55555555 +#define DDRSS_PHY_39_DATA 0xAAAAAAAA +#define DDRSS_PHY_40_DATA 0x00005555 +#define DDRSS_PHY_41_DATA 0x01000100 +#define DDRSS_PHY_42_DATA 0x00800180 +#define DDRSS_PHY_43_DATA 0x00000001 +#define DDRSS_PHY_44_DATA 0x00000000 +#define DDRSS_PHY_45_DATA 0x00000000 +#define DDRSS_PHY_46_DATA 0x00000000 +#define DDRSS_PHY_47_DATA 0x00000000 +#define DDRSS_PHY_48_DATA 0x00000000 +#define DDRSS_PHY_49_DATA 0x00000000 +#define DDRSS_PHY_50_DATA 0x00000000 +#define DDRSS_PHY_51_DATA 0x00000000 +#define DDRSS_PHY_52_DATA 0x00000000 +#define DDRSS_PHY_53_DATA 0x00000000 +#define DDRSS_PHY_54_DATA 0x00000000 +#define DDRSS_PHY_55_DATA 0x00000000 +#define DDRSS_PHY_56_DATA 0x00000000 +#define DDRSS_PHY_57_DATA 0x00000000 +#define DDRSS_PHY_58_DATA 0x00000000 +#define DDRSS_PHY_59_DATA 0x00000000 +#define DDRSS_PHY_60_DATA 0x00000000 +#define DDRSS_PHY_61_DATA 0x00000000 +#define DDRSS_PHY_62_DATA 0x00000000 +#define DDRSS_PHY_63_DATA 0x00000000 +#define DDRSS_PHY_64_DATA 0x00000000 +#define DDRSS_PHY_65_DATA 0x00000000 +#define DDRSS_PHY_66_DATA 0x00000104 +#define DDRSS_PHY_67_DATA 0x00000120 +#define DDRSS_PHY_68_DATA 0x00000000 +#define DDRSS_PHY_69_DATA 0x00000000 +#define DDRSS_PHY_70_DATA 0x00000000 +#define DDRSS_PHY_71_DATA 0x00000000 +#define DDRSS_PHY_72_DATA 0x00000000 +#define DDRSS_PHY_73_DATA 0x00000000 +#define DDRSS_PHY_74_DATA 0x00000000 +#define DDRSS_PHY_75_DATA 0x00000001 +#define DDRSS_PHY_76_DATA 0x07FF0000 +#define DDRSS_PHY_77_DATA 0x0080081F +#define DDRSS_PHY_78_DATA 0x00081020 +#define DDRSS_PHY_79_DATA 0x04010000 +#define DDRSS_PHY_80_DATA 0x00000000 +#define DDRSS_PHY_81_DATA 0x00000000 +#define DDRSS_PHY_82_DATA 0x00000000 +#define DDRSS_PHY_83_DATA 0x00000100 +#define DDRSS_PHY_84_DATA 0x01CC0C01 +#define DDRSS_PHY_85_DATA 0x0003CC0C +#define DDRSS_PHY_86_DATA 0x20000140 +#define DDRSS_PHY_87_DATA 0x07FF0200 +#define DDRSS_PHY_88_DATA 0x0000DD01 +#define DDRSS_PHY_89_DATA 0x10100303 +#define DDRSS_PHY_90_DATA 0x10101010 +#define DDRSS_PHY_91_DATA 0x10101010 +#define DDRSS_PHY_92_DATA 0x00041010 +#define DDRSS_PHY_93_DATA 0x00100010 +#define DDRSS_PHY_94_DATA 0x00100010 +#define DDRSS_PHY_95_DATA 0x00100010 +#define DDRSS_PHY_96_DATA 0x00100010 +#define DDRSS_PHY_97_DATA 0x00050010 +#define DDRSS_PHY_98_DATA 0x51517041 +#define DDRSS_PHY_99_DATA 0x31C06000 +#define DDRSS_PHY_100_DATA 0x07AB0340 +#define DDRSS_PHY_101_DATA 0x00C0C001 +#define DDRSS_PHY_102_DATA 0x0D0C0001 +#define DDRSS_PHY_103_DATA 0x10001000 +#define DDRSS_PHY_104_DATA 0x0C063E42 +#define DDRSS_PHY_105_DATA 0x0F0C3201 +#define DDRSS_PHY_106_DATA 0x01000140 +#define DDRSS_PHY_107_DATA 0x0C000420 +#define DDRSS_PHY_108_DATA 0x000002DD +#define DDRSS_PHY_109_DATA 0x0A0000D0 +#define DDRSS_PHY_110_DATA 0x00030200 +#define DDRSS_PHY_111_DATA 0x02800000 +#define DDRSS_PHY_112_DATA 0x80800000 +#define DDRSS_PHY_113_DATA 0x000D2010 +#define DDRSS_PHY_114_DATA 0x76543210 +#define DDRSS_PHY_115_DATA 0x00000008 +#define DDRSS_PHY_116_DATA 0x02800280 +#define DDRSS_PHY_117_DATA 0x02800280 +#define DDRSS_PHY_118_DATA 0x02800280 +#define DDRSS_PHY_119_DATA 0x02800280 +#define DDRSS_PHY_120_DATA 0x00000280 +#define DDRSS_PHY_121_DATA 0x0000A000 +#define DDRSS_PHY_122_DATA 0x00A000A0 +#define DDRSS_PHY_123_DATA 0x00A000A0 +#define DDRSS_PHY_124_DATA 0x00A000A0 +#define DDRSS_PHY_125_DATA 0x00A000A0 +#define DDRSS_PHY_126_DATA 0x00A000A0 +#define DDRSS_PHY_127_DATA 0x00A000A0 +#define DDRSS_PHY_128_DATA 0x00A000A0 +#define DDRSS_PHY_129_DATA 0x00A000A0 +#define DDRSS_PHY_130_DATA 0x006D00A0 +#define DDRSS_PHY_131_DATA 0x01A00005 +#define DDRSS_PHY_132_DATA 0x00000000 +#define DDRSS_PHY_133_DATA 0x00000000 +#define DDRSS_PHY_134_DATA 0x00080200 +#define DDRSS_PHY_135_DATA 0x00000000 +#define DDRSS_PHY_136_DATA 0x20202020 +#define DDRSS_PHY_137_DATA 0x20202020 +#define DDRSS_PHY_138_DATA 0xF0F02020 +#define DDRSS_PHY_139_DATA 0x00000000 +#define DDRSS_PHY_140_DATA 0x00000000 +#define DDRSS_PHY_141_DATA 0x00000000 +#define DDRSS_PHY_142_DATA 0x00000000 +#define DDRSS_PHY_143_DATA 0x00000000 +#define DDRSS_PHY_144_DATA 0x00000000 +#define DDRSS_PHY_145_DATA 0x00000000 +#define DDRSS_PHY_146_DATA 0x00000000 +#define DDRSS_PHY_147_DATA 0x00000000 +#define DDRSS_PHY_148_DATA 0x00000000 +#define DDRSS_PHY_149_DATA 0x00000000 +#define DDRSS_PHY_150_DATA 0x00000000 +#define DDRSS_PHY_151_DATA 0x00000000 +#define DDRSS_PHY_152_DATA 0x00000000 +#define DDRSS_PHY_153_DATA 0x00000000 +#define DDRSS_PHY_154_DATA 0x00000000 +#define DDRSS_PHY_155_DATA 0x00000000 +#define DDRSS_PHY_156_DATA 0x00000000 +#define DDRSS_PHY_157_DATA 0x00000000 +#define DDRSS_PHY_158_DATA 0x00000000 +#define DDRSS_PHY_159_DATA 0x00000000 +#define DDRSS_PHY_160_DATA 0x00000000 +#define DDRSS_PHY_161_DATA 0x00000000 +#define DDRSS_PHY_162_DATA 0x00000000 +#define DDRSS_PHY_163_DATA 0x00000000 +#define DDRSS_PHY_164_DATA 0x00000000 +#define DDRSS_PHY_165_DATA 0x00000000 +#define DDRSS_PHY_166_DATA 0x00000000 +#define DDRSS_PHY_167_DATA 0x00000000 +#define DDRSS_PHY_168_DATA 0x00000000 +#define DDRSS_PHY_169_DATA 0x00000000 +#define DDRSS_PHY_170_DATA 0x00000000 +#define DDRSS_PHY_171_DATA 0x00000000 +#define DDRSS_PHY_172_DATA 0x00000000 +#define DDRSS_PHY_173_DATA 0x00000000 +#define DDRSS_PHY_174_DATA 0x00000000 +#define DDRSS_PHY_175_DATA 0x00000000 +#define DDRSS_PHY_176_DATA 0x00000000 +#define DDRSS_PHY_177_DATA 0x00000000 +#define DDRSS_PHY_178_DATA 0x00000000 +#define DDRSS_PHY_179_DATA 0x00000000 +#define DDRSS_PHY_180_DATA 0x00000000 +#define DDRSS_PHY_181_DATA 0x00000000 +#define DDRSS_PHY_182_DATA 0x00000000 +#define DDRSS_PHY_183_DATA 0x00000000 +#define DDRSS_PHY_184_DATA 0x00000000 +#define DDRSS_PHY_185_DATA 0x00000000 +#define DDRSS_PHY_186_DATA 0x00000000 +#define DDRSS_PHY_187_DATA 0x00000000 +#define DDRSS_PHY_188_DATA 0x00000000 +#define DDRSS_PHY_189_DATA 0x00000000 +#define DDRSS_PHY_190_DATA 0x00000000 +#define DDRSS_PHY_191_DATA 0x00000000 +#define DDRSS_PHY_192_DATA 0x00000000 +#define DDRSS_PHY_193_DATA 0x00000000 +#define DDRSS_PHY_194_DATA 0x00000000 +#define DDRSS_PHY_195_DATA 0x00000000 +#define DDRSS_PHY_196_DATA 0x00000000 +#define DDRSS_PHY_197_DATA 0x00000000 +#define DDRSS_PHY_198_DATA 0x00000000 +#define DDRSS_PHY_199_DATA 0x00000000 +#define DDRSS_PHY_200_DATA 0x00000000 +#define DDRSS_PHY_201_DATA 0x00000000 +#define DDRSS_PHY_202_DATA 0x00000000 +#define DDRSS_PHY_203_DATA 0x00000000 +#define DDRSS_PHY_204_DATA 0x00000000 +#define DDRSS_PHY_205_DATA 0x00000000 +#define DDRSS_PHY_206_DATA 0x00000000 +#define DDRSS_PHY_207_DATA 0x00000000 +#define DDRSS_PHY_208_DATA 0x00000000 +#define DDRSS_PHY_209_DATA 0x00000000 +#define DDRSS_PHY_210_DATA 0x00000000 +#define DDRSS_PHY_211_DATA 0x00000000 +#define DDRSS_PHY_212_DATA 0x00000000 +#define DDRSS_PHY_213_DATA 0x00000000 +#define DDRSS_PHY_214_DATA 0x00000000 +#define DDRSS_PHY_215_DATA 0x00000000 +#define DDRSS_PHY_216_DATA 0x00000000 +#define DDRSS_PHY_217_DATA 0x00000000 +#define DDRSS_PHY_218_DATA 0x00000000 +#define DDRSS_PHY_219_DATA 0x00000000 +#define DDRSS_PHY_220_DATA 0x00000000 +#define DDRSS_PHY_221_DATA 0x00000000 +#define DDRSS_PHY_222_DATA 0x00000000 +#define DDRSS_PHY_223_DATA 0x00000000 +#define DDRSS_PHY_224_DATA 0x00000000 +#define DDRSS_PHY_225_DATA 0x00000000 +#define DDRSS_PHY_226_DATA 0x00000000 +#define DDRSS_PHY_227_DATA 0x00000000 +#define DDRSS_PHY_228_DATA 0x00000000 +#define DDRSS_PHY_229_DATA 0x00000000 +#define DDRSS_PHY_230_DATA 0x00000000 +#define DDRSS_PHY_231_DATA 0x00000000 +#define DDRSS_PHY_232_DATA 0x00000000 +#define DDRSS_PHY_233_DATA 0x00000000 +#define DDRSS_PHY_234_DATA 0x00000000 +#define DDRSS_PHY_235_DATA 0x00000000 +#define DDRSS_PHY_236_DATA 0x00000000 +#define DDRSS_PHY_237_DATA 0x00000000 +#define DDRSS_PHY_238_DATA 0x00000000 +#define DDRSS_PHY_239_DATA 0x00000000 +#define DDRSS_PHY_240_DATA 0x00000000 +#define DDRSS_PHY_241_DATA 0x00000000 +#define DDRSS_PHY_242_DATA 0x00000000 +#define DDRSS_PHY_243_DATA 0x00000000 +#define DDRSS_PHY_244_DATA 0x00000000 +#define DDRSS_PHY_245_DATA 0x00000000 +#define DDRSS_PHY_246_DATA 0x00000000 +#define DDRSS_PHY_247_DATA 0x00000000 +#define DDRSS_PHY_248_DATA 0x00000000 +#define DDRSS_PHY_249_DATA 0x00000000 +#define DDRSS_PHY_250_DATA 0x00000000 +#define DDRSS_PHY_251_DATA 0x00000000 +#define DDRSS_PHY_252_DATA 0x00000000 +#define DDRSS_PHY_253_DATA 0x00000000 +#define DDRSS_PHY_254_DATA 0x00000000 +#define DDRSS_PHY_255_DATA 0x00000000 +#define DDRSS_PHY_256_DATA 0x000004F0 +#define DDRSS_PHY_257_DATA 0x00000000 +#define DDRSS_PHY_258_DATA 0x00030200 +#define DDRSS_PHY_259_DATA 0x00000000 +#define DDRSS_PHY_260_DATA 0x00000000 +#define DDRSS_PHY_261_DATA 0x01030000 +#define DDRSS_PHY_262_DATA 0x00010000 +#define DDRSS_PHY_263_DATA 0x01030004 +#define DDRSS_PHY_264_DATA 0x01000000 +#define DDRSS_PHY_265_DATA 0x00000000 +#define DDRSS_PHY_266_DATA 0x00000000 +#define DDRSS_PHY_267_DATA 0x01000001 +#define DDRSS_PHY_268_DATA 0x00000100 +#define DDRSS_PHY_269_DATA 0x000800C0 +#define DDRSS_PHY_270_DATA 0x060100CC +#define DDRSS_PHY_271_DATA 0x00030066 +#define DDRSS_PHY_272_DATA 0x00000000 +#define DDRSS_PHY_273_DATA 0x00000001 +#define DDRSS_PHY_274_DATA 0x0000AAAA +#define DDRSS_PHY_275_DATA 0x00005555 +#define DDRSS_PHY_276_DATA 0x0000B5B5 +#define DDRSS_PHY_277_DATA 0x00004A4A +#define DDRSS_PHY_278_DATA 0x00005656 +#define DDRSS_PHY_279_DATA 0x0000A9A9 +#define DDRSS_PHY_280_DATA 0x0000A9A9 +#define DDRSS_PHY_281_DATA 0x0000B5B5 +#define DDRSS_PHY_282_DATA 0x00000000 +#define DDRSS_PHY_283_DATA 0x00000000 +#define DDRSS_PHY_284_DATA 0x2A000000 +#define DDRSS_PHY_285_DATA 0x00000808 +#define DDRSS_PHY_286_DATA 0x0F000000 +#define DDRSS_PHY_287_DATA 0x00000F0F +#define DDRSS_PHY_288_DATA 0x10200000 +#define DDRSS_PHY_289_DATA 0x0C002004 +#define DDRSS_PHY_290_DATA 0x00000000 +#define DDRSS_PHY_291_DATA 0x00000000 +#define DDRSS_PHY_292_DATA 0x55555555 +#define DDRSS_PHY_293_DATA 0xAAAAAAAA +#define DDRSS_PHY_294_DATA 0x55555555 +#define DDRSS_PHY_295_DATA 0xAAAAAAAA +#define DDRSS_PHY_296_DATA 0x00005555 +#define DDRSS_PHY_297_DATA 0x01000100 +#define DDRSS_PHY_298_DATA 0x00800180 +#define DDRSS_PHY_299_DATA 0x00000000 +#define DDRSS_PHY_300_DATA 0x00000000 +#define DDRSS_PHY_301_DATA 0x00000000 +#define DDRSS_PHY_302_DATA 0x00000000 +#define DDRSS_PHY_303_DATA 0x00000000 +#define DDRSS_PHY_304_DATA 0x00000000 +#define DDRSS_PHY_305_DATA 0x00000000 +#define DDRSS_PHY_306_DATA 0x00000000 +#define DDRSS_PHY_307_DATA 0x00000000 +#define DDRSS_PHY_308_DATA 0x00000000 +#define DDRSS_PHY_309_DATA 0x00000000 +#define DDRSS_PHY_310_DATA 0x00000000 +#define DDRSS_PHY_311_DATA 0x00000000 +#define DDRSS_PHY_312_DATA 0x00000000 +#define DDRSS_PHY_313_DATA 0x00000000 +#define DDRSS_PHY_314_DATA 0x00000000 +#define DDRSS_PHY_315_DATA 0x00000000 +#define DDRSS_PHY_316_DATA 0x00000000 +#define DDRSS_PHY_317_DATA 0x00000000 +#define DDRSS_PHY_318_DATA 0x00000000 +#define DDRSS_PHY_319_DATA 0x00000000 +#define DDRSS_PHY_320_DATA 0x00000000 +#define DDRSS_PHY_321_DATA 0x00000000 +#define DDRSS_PHY_322_DATA 0x00000104 +#define DDRSS_PHY_323_DATA 0x00000120 +#define DDRSS_PHY_324_DATA 0x00000000 +#define DDRSS_PHY_325_DATA 0x00000000 +#define DDRSS_PHY_326_DATA 0x00000000 +#define DDRSS_PHY_327_DATA 0x00000000 +#define DDRSS_PHY_328_DATA 0x00000000 +#define DDRSS_PHY_329_DATA 0x00000000 +#define DDRSS_PHY_330_DATA 0x00000000 +#define DDRSS_PHY_331_DATA 0x00000001 +#define DDRSS_PHY_332_DATA 0x07FF0000 +#define DDRSS_PHY_333_DATA 0x0080081F +#define DDRSS_PHY_334_DATA 0x00081020 +#define DDRSS_PHY_335_DATA 0x04010000 +#define DDRSS_PHY_336_DATA 0x00000000 +#define DDRSS_PHY_337_DATA 0x00000000 +#define DDRSS_PHY_338_DATA 0x00000000 +#define DDRSS_PHY_339_DATA 0x00000100 +#define DDRSS_PHY_340_DATA 0x01CC0C01 +#define DDRSS_PHY_341_DATA 0x0003CC0C +#define DDRSS_PHY_342_DATA 0x20000140 +#define DDRSS_PHY_343_DATA 0x07FF0200 +#define DDRSS_PHY_344_DATA 0x0000DD01 +#define DDRSS_PHY_345_DATA 0x10100303 +#define DDRSS_PHY_346_DATA 0x10101010 +#define DDRSS_PHY_347_DATA 0x10101010 +#define DDRSS_PHY_348_DATA 0x00041010 +#define DDRSS_PHY_349_DATA 0x00100010 +#define DDRSS_PHY_350_DATA 0x00100010 +#define DDRSS_PHY_351_DATA 0x00100010 +#define DDRSS_PHY_352_DATA 0x00100010 +#define DDRSS_PHY_353_DATA 0x00050010 +#define DDRSS_PHY_354_DATA 0x51517041 +#define DDRSS_PHY_355_DATA 0x31C06000 +#define DDRSS_PHY_356_DATA 0x07AB0340 +#define DDRSS_PHY_357_DATA 0x00C0C001 +#define DDRSS_PHY_358_DATA 0x0D0C0001 +#define DDRSS_PHY_359_DATA 0x10001000 +#define DDRSS_PHY_360_DATA 0x0C063E42 +#define DDRSS_PHY_361_DATA 0x0F0C3201 +#define DDRSS_PHY_362_DATA 0x01000140 +#define DDRSS_PHY_363_DATA 0x0C000420 +#define DDRSS_PHY_364_DATA 0x000002DD +#define DDRSS_PHY_365_DATA 0x0A0000D0 +#define DDRSS_PHY_366_DATA 0x00030200 +#define DDRSS_PHY_367_DATA 0x02800000 +#define DDRSS_PHY_368_DATA 0x80800000 +#define DDRSS_PHY_369_DATA 0x000D2010 +#define DDRSS_PHY_370_DATA 0x76543210 +#define DDRSS_PHY_371_DATA 0x00000008 +#define DDRSS_PHY_372_DATA 0x02800280 +#define DDRSS_PHY_373_DATA 0x02800280 +#define DDRSS_PHY_374_DATA 0x02800280 +#define DDRSS_PHY_375_DATA 0x02800280 +#define DDRSS_PHY_376_DATA 0x00000280 +#define DDRSS_PHY_377_DATA 0x0000A000 +#define DDRSS_PHY_378_DATA 0x00A000A0 +#define DDRSS_PHY_379_DATA 0x00A000A0 +#define DDRSS_PHY_380_DATA 0x00A000A0 +#define DDRSS_PHY_381_DATA 0x00A000A0 +#define DDRSS_PHY_382_DATA 0x00A000A0 +#define DDRSS_PHY_383_DATA 0x00A000A0 +#define DDRSS_PHY_384_DATA 0x00A000A0 +#define DDRSS_PHY_385_DATA 0x00A000A0 +#define DDRSS_PHY_386_DATA 0x006D00A0 +#define DDRSS_PHY_387_DATA 0x01A00005 +#define DDRSS_PHY_388_DATA 0x00000000 +#define DDRSS_PHY_389_DATA 0x00000000 +#define DDRSS_PHY_390_DATA 0x00080200 +#define DDRSS_PHY_391_DATA 0x00000000 +#define DDRSS_PHY_392_DATA 0x20202020 +#define DDRSS_PHY_393_DATA 0x20202020 +#define DDRSS_PHY_394_DATA 0xF0F02020 +#define DDRSS_PHY_395_DATA 0x00000000 +#define DDRSS_PHY_396_DATA 0x00000000 +#define DDRSS_PHY_397_DATA 0x00000000 +#define DDRSS_PHY_398_DATA 0x00000000 +#define DDRSS_PHY_399_DATA 0x00000000 +#define DDRSS_PHY_400_DATA 0x00000000 +#define DDRSS_PHY_401_DATA 0x00000000 +#define DDRSS_PHY_402_DATA 0x00000000 +#define DDRSS_PHY_403_DATA 0x00000000 +#define DDRSS_PHY_404_DATA 0x00000000 +#define DDRSS_PHY_405_DATA 0x00000000 +#define DDRSS_PHY_406_DATA 0x00000000 +#define DDRSS_PHY_407_DATA 0x00000000 +#define DDRSS_PHY_408_DATA 0x00000000 +#define DDRSS_PHY_409_DATA 0x00000000 +#define DDRSS_PHY_410_DATA 0x00000000 +#define DDRSS_PHY_411_DATA 0x00000000 +#define DDRSS_PHY_412_DATA 0x00000000 +#define DDRSS_PHY_413_DATA 0x00000000 +#define DDRSS_PHY_414_DATA 0x00000000 +#define DDRSS_PHY_415_DATA 0x00000000 +#define DDRSS_PHY_416_DATA 0x00000000 +#define DDRSS_PHY_417_DATA 0x00000000 +#define DDRSS_PHY_418_DATA 0x00000000 +#define DDRSS_PHY_419_DATA 0x00000000 +#define DDRSS_PHY_420_DATA 0x00000000 +#define DDRSS_PHY_421_DATA 0x00000000 +#define DDRSS_PHY_422_DATA 0x00000000 +#define DDRSS_PHY_423_DATA 0x00000000 +#define DDRSS_PHY_424_DATA 0x00000000 +#define DDRSS_PHY_425_DATA 0x00000000 +#define DDRSS_PHY_426_DATA 0x00000000 +#define DDRSS_PHY_427_DATA 0x00000000 +#define DDRSS_PHY_428_DATA 0x00000000 +#define DDRSS_PHY_429_DATA 0x00000000 +#define DDRSS_PHY_430_DATA 0x00000000 +#define DDRSS_PHY_431_DATA 0x00000000 +#define DDRSS_PHY_432_DATA 0x00000000 +#define DDRSS_PHY_433_DATA 0x00000000 +#define DDRSS_PHY_434_DATA 0x00000000 +#define DDRSS_PHY_435_DATA 0x00000000 +#define DDRSS_PHY_436_DATA 0x00000000 +#define DDRSS_PHY_437_DATA 0x00000000 +#define DDRSS_PHY_438_DATA 0x00000000 +#define DDRSS_PHY_439_DATA 0x00000000 +#define DDRSS_PHY_440_DATA 0x00000000 +#define DDRSS_PHY_441_DATA 0x00000000 +#define DDRSS_PHY_442_DATA 0x00000000 +#define DDRSS_PHY_443_DATA 0x00000000 +#define DDRSS_PHY_444_DATA 0x00000000 +#define DDRSS_PHY_445_DATA 0x00000000 +#define DDRSS_PHY_446_DATA 0x00000000 +#define DDRSS_PHY_447_DATA 0x00000000 +#define DDRSS_PHY_448_DATA 0x00000000 +#define DDRSS_PHY_449_DATA 0x00000000 +#define DDRSS_PHY_450_DATA 0x00000000 +#define DDRSS_PHY_451_DATA 0x00000000 +#define DDRSS_PHY_452_DATA 0x00000000 +#define DDRSS_PHY_453_DATA 0x00000000 +#define DDRSS_PHY_454_DATA 0x00000000 +#define DDRSS_PHY_455_DATA 0x00000000 +#define DDRSS_PHY_456_DATA 0x00000000 +#define DDRSS_PHY_457_DATA 0x00000000 +#define DDRSS_PHY_458_DATA 0x00000000 +#define DDRSS_PHY_459_DATA 0x00000000 +#define DDRSS_PHY_460_DATA 0x00000000 +#define DDRSS_PHY_461_DATA 0x00000000 +#define DDRSS_PHY_462_DATA 0x00000000 +#define DDRSS_PHY_463_DATA 0x00000000 +#define DDRSS_PHY_464_DATA 0x00000000 +#define DDRSS_PHY_465_DATA 0x00000000 +#define DDRSS_PHY_466_DATA 0x00000000 +#define DDRSS_PHY_467_DATA 0x00000000 +#define DDRSS_PHY_468_DATA 0x00000000 +#define DDRSS_PHY_469_DATA 0x00000000 +#define DDRSS_PHY_470_DATA 0x00000000 +#define DDRSS_PHY_471_DATA 0x00000000 +#define DDRSS_PHY_472_DATA 0x00000000 +#define DDRSS_PHY_473_DATA 0x00000000 +#define DDRSS_PHY_474_DATA 0x00000000 +#define DDRSS_PHY_475_DATA 0x00000000 +#define DDRSS_PHY_476_DATA 0x00000000 +#define DDRSS_PHY_477_DATA 0x00000000 +#define DDRSS_PHY_478_DATA 0x00000000 +#define DDRSS_PHY_479_DATA 0x00000000 +#define DDRSS_PHY_480_DATA 0x00000000 +#define DDRSS_PHY_481_DATA 0x00000000 +#define DDRSS_PHY_482_DATA 0x00000000 +#define DDRSS_PHY_483_DATA 0x00000000 +#define DDRSS_PHY_484_DATA 0x00000000 +#define DDRSS_PHY_485_DATA 0x00000000 +#define DDRSS_PHY_486_DATA 0x00000000 +#define DDRSS_PHY_487_DATA 0x00000000 +#define DDRSS_PHY_488_DATA 0x00000000 +#define DDRSS_PHY_489_DATA 0x00000000 +#define DDRSS_PHY_490_DATA 0x00000000 +#define DDRSS_PHY_491_DATA 0x00000000 +#define DDRSS_PHY_492_DATA 0x00000000 +#define DDRSS_PHY_493_DATA 0x00000000 +#define DDRSS_PHY_494_DATA 0x00000000 +#define DDRSS_PHY_495_DATA 0x00000000 +#define DDRSS_PHY_496_DATA 0x00000000 +#define DDRSS_PHY_497_DATA 0x00000000 +#define DDRSS_PHY_498_DATA 0x00000000 +#define DDRSS_PHY_499_DATA 0x00000000 +#define DDRSS_PHY_500_DATA 0x00000000 +#define DDRSS_PHY_501_DATA 0x00000000 +#define DDRSS_PHY_502_DATA 0x00000000 +#define DDRSS_PHY_503_DATA 0x00000000 +#define DDRSS_PHY_504_DATA 0x00000000 +#define DDRSS_PHY_505_DATA 0x00000000 +#define DDRSS_PHY_506_DATA 0x00000000 +#define DDRSS_PHY_507_DATA 0x00000000 +#define DDRSS_PHY_508_DATA 0x00000000 +#define DDRSS_PHY_509_DATA 0x00000000 +#define DDRSS_PHY_510_DATA 0x00000000 +#define DDRSS_PHY_511_DATA 0x00000000 +#define DDRSS_PHY_512_DATA 0x000004F0 +#define DDRSS_PHY_513_DATA 0x00000000 +#define DDRSS_PHY_514_DATA 0x00030200 +#define DDRSS_PHY_515_DATA 0x00000000 +#define DDRSS_PHY_516_DATA 0x00000000 +#define DDRSS_PHY_517_DATA 0x01030000 +#define DDRSS_PHY_518_DATA 0x00010000 +#define DDRSS_PHY_519_DATA 0x01030004 +#define DDRSS_PHY_520_DATA 0x01000000 +#define DDRSS_PHY_521_DATA 0x00000000 +#define DDRSS_PHY_522_DATA 0x00000000 +#define DDRSS_PHY_523_DATA 0x01000001 +#define DDRSS_PHY_524_DATA 0x00000100 +#define DDRSS_PHY_525_DATA 0x000800C0 +#define DDRSS_PHY_526_DATA 0x060100CC +#define DDRSS_PHY_527_DATA 0x00030066 +#define DDRSS_PHY_528_DATA 0x00000000 +#define DDRSS_PHY_529_DATA 0x00000001 +#define DDRSS_PHY_530_DATA 0x0000AAAA +#define DDRSS_PHY_531_DATA 0x00005555 +#define DDRSS_PHY_532_DATA 0x0000B5B5 +#define DDRSS_PHY_533_DATA 0x00004A4A +#define DDRSS_PHY_534_DATA 0x00005656 +#define DDRSS_PHY_535_DATA 0x0000A9A9 +#define DDRSS_PHY_536_DATA 0x0000A9A9 +#define DDRSS_PHY_537_DATA 0x0000B5B5 +#define DDRSS_PHY_538_DATA 0x00000000 +#define DDRSS_PHY_539_DATA 0x00000000 +#define DDRSS_PHY_540_DATA 0x2A000000 +#define DDRSS_PHY_541_DATA 0x00000808 +#define DDRSS_PHY_542_DATA 0x0F000000 +#define DDRSS_PHY_543_DATA 0x00000F0F +#define DDRSS_PHY_544_DATA 0x10200000 +#define DDRSS_PHY_545_DATA 0x0C002004 +#define DDRSS_PHY_546_DATA 0x00000000 +#define DDRSS_PHY_547_DATA 0x00000000 +#define DDRSS_PHY_548_DATA 0x55555555 +#define DDRSS_PHY_549_DATA 0xAAAAAAAA +#define DDRSS_PHY_550_DATA 0x55555555 +#define DDRSS_PHY_551_DATA 0xAAAAAAAA +#define DDRSS_PHY_552_DATA 0x00005555 +#define DDRSS_PHY_553_DATA 0x01000100 +#define DDRSS_PHY_554_DATA 0x00800180 +#define DDRSS_PHY_555_DATA 0x00000001 +#define DDRSS_PHY_556_DATA 0x00000000 +#define DDRSS_PHY_557_DATA 0x00000000 +#define DDRSS_PHY_558_DATA 0x00000000 +#define DDRSS_PHY_559_DATA 0x00000000 +#define DDRSS_PHY_560_DATA 0x00000000 +#define DDRSS_PHY_561_DATA 0x00000000 +#define DDRSS_PHY_562_DATA 0x00000000 +#define DDRSS_PHY_563_DATA 0x00000000 +#define DDRSS_PHY_564_DATA 0x00000000 +#define DDRSS_PHY_565_DATA 0x00000000 +#define DDRSS_PHY_566_DATA 0x00000000 +#define DDRSS_PHY_567_DATA 0x00000000 +#define DDRSS_PHY_568_DATA 0x00000000 +#define DDRSS_PHY_569_DATA 0x00000000 +#define DDRSS_PHY_570_DATA 0x00000000 +#define DDRSS_PHY_571_DATA 0x00000000 +#define DDRSS_PHY_572_DATA 0x00000000 +#define DDRSS_PHY_573_DATA 0x00000000 +#define DDRSS_PHY_574_DATA 0x00000000 +#define DDRSS_PHY_575_DATA 0x00000000 +#define DDRSS_PHY_576_DATA 0x00000000 +#define DDRSS_PHY_577_DATA 0x00000000 +#define DDRSS_PHY_578_DATA 0x00000104 +#define DDRSS_PHY_579_DATA 0x00000120 +#define DDRSS_PHY_580_DATA 0x00000000 +#define DDRSS_PHY_581_DATA 0x00000000 +#define DDRSS_PHY_582_DATA 0x00000000 +#define DDRSS_PHY_583_DATA 0x00000000 +#define DDRSS_PHY_584_DATA 0x00000000 +#define DDRSS_PHY_585_DATA 0x00000000 +#define DDRSS_PHY_586_DATA 0x00000000 +#define DDRSS_PHY_587_DATA 0x00000001 +#define DDRSS_PHY_588_DATA 0x07FF0000 +#define DDRSS_PHY_589_DATA 0x0080081F +#define DDRSS_PHY_590_DATA 0x00081020 +#define DDRSS_PHY_591_DATA 0x04010000 +#define DDRSS_PHY_592_DATA 0x00000000 +#define DDRSS_PHY_593_DATA 0x00000000 +#define DDRSS_PHY_594_DATA 0x00000000 +#define DDRSS_PHY_595_DATA 0x00000100 +#define DDRSS_PHY_596_DATA 0x01CC0C01 +#define DDRSS_PHY_597_DATA 0x0003CC0C +#define DDRSS_PHY_598_DATA 0x20000140 +#define DDRSS_PHY_599_DATA 0x07FF0200 +#define DDRSS_PHY_600_DATA 0x0000DD01 +#define DDRSS_PHY_601_DATA 0x10100303 +#define DDRSS_PHY_602_DATA 0x10101010 +#define DDRSS_PHY_603_DATA 0x10101010 +#define DDRSS_PHY_604_DATA 0x00041010 +#define DDRSS_PHY_605_DATA 0x00100010 +#define DDRSS_PHY_606_DATA 0x00100010 +#define DDRSS_PHY_607_DATA 0x00100010 +#define DDRSS_PHY_608_DATA 0x00100010 +#define DDRSS_PHY_609_DATA 0x00050010 +#define DDRSS_PHY_610_DATA 0x51517041 +#define DDRSS_PHY_611_DATA 0x31C06000 +#define DDRSS_PHY_612_DATA 0x07AB0340 +#define DDRSS_PHY_613_DATA 0x00C0C001 +#define DDRSS_PHY_614_DATA 0x0D0C0001 +#define DDRSS_PHY_615_DATA 0x10001000 +#define DDRSS_PHY_616_DATA 0x0C063E42 +#define DDRSS_PHY_617_DATA 0x0F0C3201 +#define DDRSS_PHY_618_DATA 0x01000140 +#define DDRSS_PHY_619_DATA 0x0C000420 +#define DDRSS_PHY_620_DATA 0x000002DD +#define DDRSS_PHY_621_DATA 0x0A0000D0 +#define DDRSS_PHY_622_DATA 0x00030200 +#define DDRSS_PHY_623_DATA 0x02800000 +#define DDRSS_PHY_624_DATA 0x80800000 +#define DDRSS_PHY_625_DATA 0x000D2010 +#define DDRSS_PHY_626_DATA 0x76543210 +#define DDRSS_PHY_627_DATA 0x00000008 +#define DDRSS_PHY_628_DATA 0x02800280 +#define DDRSS_PHY_629_DATA 0x02800280 +#define DDRSS_PHY_630_DATA 0x02800280 +#define DDRSS_PHY_631_DATA 0x02800280 +#define DDRSS_PHY_632_DATA 0x00000280 +#define DDRSS_PHY_633_DATA 0x0000A000 +#define DDRSS_PHY_634_DATA 0x00A000A0 +#define DDRSS_PHY_635_DATA 0x00A000A0 +#define DDRSS_PHY_636_DATA 0x00A000A0 +#define DDRSS_PHY_637_DATA 0x00A000A0 +#define DDRSS_PHY_638_DATA 0x00A000A0 +#define DDRSS_PHY_639_DATA 0x00A000A0 +#define DDRSS_PHY_640_DATA 0x00A000A0 +#define DDRSS_PHY_641_DATA 0x00A000A0 +#define DDRSS_PHY_642_DATA 0x006D00A0 +#define DDRSS_PHY_643_DATA 0x01A00005 +#define DDRSS_PHY_644_DATA 0x00000000 +#define DDRSS_PHY_645_DATA 0x00000000 +#define DDRSS_PHY_646_DATA 0x00080200 +#define DDRSS_PHY_647_DATA 0x00000000 +#define DDRSS_PHY_648_DATA 0x20202020 +#define DDRSS_PHY_649_DATA 0x20202020 +#define DDRSS_PHY_650_DATA 0xF0F02020 +#define DDRSS_PHY_651_DATA 0x00000000 +#define DDRSS_PHY_652_DATA 0x00000000 +#define DDRSS_PHY_653_DATA 0x00000000 +#define DDRSS_PHY_654_DATA 0x00000000 +#define DDRSS_PHY_655_DATA 0x00000000 +#define DDRSS_PHY_656_DATA 0x00000000 +#define DDRSS_PHY_657_DATA 0x00000000 +#define DDRSS_PHY_658_DATA 0x00000000 +#define DDRSS_PHY_659_DATA 0x00000000 +#define DDRSS_PHY_660_DATA 0x00000000 +#define DDRSS_PHY_661_DATA 0x00000000 +#define DDRSS_PHY_662_DATA 0x00000000 +#define DDRSS_PHY_663_DATA 0x00000000 +#define DDRSS_PHY_664_DATA 0x00000000 +#define DDRSS_PHY_665_DATA 0x00000000 +#define DDRSS_PHY_666_DATA 0x00000000 +#define DDRSS_PHY_667_DATA 0x00000000 +#define DDRSS_PHY_668_DATA 0x00000000 +#define DDRSS_PHY_669_DATA 0x00000000 +#define DDRSS_PHY_670_DATA 0x00000000 +#define DDRSS_PHY_671_DATA 0x00000000 +#define DDRSS_PHY_672_DATA 0x00000000 +#define DDRSS_PHY_673_DATA 0x00000000 +#define DDRSS_PHY_674_DATA 0x00000000 +#define DDRSS_PHY_675_DATA 0x00000000 +#define DDRSS_PHY_676_DATA 0x00000000 +#define DDRSS_PHY_677_DATA 0x00000000 +#define DDRSS_PHY_678_DATA 0x00000000 +#define DDRSS_PHY_679_DATA 0x00000000 +#define DDRSS_PHY_680_DATA 0x00000000 +#define DDRSS_PHY_681_DATA 0x00000000 +#define DDRSS_PHY_682_DATA 0x00000000 +#define DDRSS_PHY_683_DATA 0x00000000 +#define DDRSS_PHY_684_DATA 0x00000000 +#define DDRSS_PHY_685_DATA 0x00000000 +#define DDRSS_PHY_686_DATA 0x00000000 +#define DDRSS_PHY_687_DATA 0x00000000 +#define DDRSS_PHY_688_DATA 0x00000000 +#define DDRSS_PHY_689_DATA 0x00000000 +#define DDRSS_PHY_690_DATA 0x00000000 +#define DDRSS_PHY_691_DATA 0x00000000 +#define DDRSS_PHY_692_DATA 0x00000000 +#define DDRSS_PHY_693_DATA 0x00000000 +#define DDRSS_PHY_694_DATA 0x00000000 +#define DDRSS_PHY_695_DATA 0x00000000 +#define DDRSS_PHY_696_DATA 0x00000000 +#define DDRSS_PHY_697_DATA 0x00000000 +#define DDRSS_PHY_698_DATA 0x00000000 +#define DDRSS_PHY_699_DATA 0x00000000 +#define DDRSS_PHY_700_DATA 0x00000000 +#define DDRSS_PHY_701_DATA 0x00000000 +#define DDRSS_PHY_702_DATA 0x00000000 +#define DDRSS_PHY_703_DATA 0x00000000 +#define DDRSS_PHY_704_DATA 0x00000000 +#define DDRSS_PHY_705_DATA 0x00000000 +#define DDRSS_PHY_706_DATA 0x00000000 +#define DDRSS_PHY_707_DATA 0x00000000 +#define DDRSS_PHY_708_DATA 0x00000000 +#define DDRSS_PHY_709_DATA 0x00000000 +#define DDRSS_PHY_710_DATA 0x00000000 +#define DDRSS_PHY_711_DATA 0x00000000 +#define DDRSS_PHY_712_DATA 0x00000000 +#define DDRSS_PHY_713_DATA 0x00000000 +#define DDRSS_PHY_714_DATA 0x00000000 +#define DDRSS_PHY_715_DATA 0x00000000 +#define DDRSS_PHY_716_DATA 0x00000000 +#define DDRSS_PHY_717_DATA 0x00000000 +#define DDRSS_PHY_718_DATA 0x00000000 +#define DDRSS_PHY_719_DATA 0x00000000 +#define DDRSS_PHY_720_DATA 0x00000000 +#define DDRSS_PHY_721_DATA 0x00000000 +#define DDRSS_PHY_722_DATA 0x00000000 +#define DDRSS_PHY_723_DATA 0x00000000 +#define DDRSS_PHY_724_DATA 0x00000000 +#define DDRSS_PHY_725_DATA 0x00000000 +#define DDRSS_PHY_726_DATA 0x00000000 +#define DDRSS_PHY_727_DATA 0x00000000 +#define DDRSS_PHY_728_DATA 0x00000000 +#define DDRSS_PHY_729_DATA 0x00000000 +#define DDRSS_PHY_730_DATA 0x00000000 +#define DDRSS_PHY_731_DATA 0x00000000 +#define DDRSS_PHY_732_DATA 0x00000000 +#define DDRSS_PHY_733_DATA 0x00000000 +#define DDRSS_PHY_734_DATA 0x00000000 +#define DDRSS_PHY_735_DATA 0x00000000 +#define DDRSS_PHY_736_DATA 0x00000000 +#define DDRSS_PHY_737_DATA 0x00000000 +#define DDRSS_PHY_738_DATA 0x00000000 +#define DDRSS_PHY_739_DATA 0x00000000 +#define DDRSS_PHY_740_DATA 0x00000000 +#define DDRSS_PHY_741_DATA 0x00000000 +#define DDRSS_PHY_742_DATA 0x00000000 +#define DDRSS_PHY_743_DATA 0x00000000 +#define DDRSS_PHY_744_DATA 0x00000000 +#define DDRSS_PHY_745_DATA 0x00000000 +#define DDRSS_PHY_746_DATA 0x00000000 +#define DDRSS_PHY_747_DATA 0x00000000 +#define DDRSS_PHY_748_DATA 0x00000000 +#define DDRSS_PHY_749_DATA 0x00000000 +#define DDRSS_PHY_750_DATA 0x00000000 +#define DDRSS_PHY_751_DATA 0x00000000 +#define DDRSS_PHY_752_DATA 0x00000000 +#define DDRSS_PHY_753_DATA 0x00000000 +#define DDRSS_PHY_754_DATA 0x00000000 +#define DDRSS_PHY_755_DATA 0x00000000 +#define DDRSS_PHY_756_DATA 0x00000000 +#define DDRSS_PHY_757_DATA 0x00000000 +#define DDRSS_PHY_758_DATA 0x00000000 +#define DDRSS_PHY_759_DATA 0x00000000 +#define DDRSS_PHY_760_DATA 0x00000000 +#define DDRSS_PHY_761_DATA 0x00000000 +#define DDRSS_PHY_762_DATA 0x00000000 +#define DDRSS_PHY_763_DATA 0x00000000 +#define DDRSS_PHY_764_DATA 0x00000000 +#define DDRSS_PHY_765_DATA 0x00000000 +#define DDRSS_PHY_766_DATA 0x00000000 +#define DDRSS_PHY_767_DATA 0x00000000 +#define DDRSS_PHY_768_DATA 0x000004F0 +#define DDRSS_PHY_769_DATA 0x00000000 +#define DDRSS_PHY_770_DATA 0x00030200 +#define DDRSS_PHY_771_DATA 0x00000000 +#define DDRSS_PHY_772_DATA 0x00000000 +#define DDRSS_PHY_773_DATA 0x01030000 +#define DDRSS_PHY_774_DATA 0x00010000 +#define DDRSS_PHY_775_DATA 0x01030004 +#define DDRSS_PHY_776_DATA 0x01000000 +#define DDRSS_PHY_777_DATA 0x00000000 +#define DDRSS_PHY_778_DATA 0x00000000 +#define DDRSS_PHY_779_DATA 0x01000001 +#define DDRSS_PHY_780_DATA 0x00000100 +#define DDRSS_PHY_781_DATA 0x000800C0 +#define DDRSS_PHY_782_DATA 0x060100CC +#define DDRSS_PHY_783_DATA 0x00030066 +#define DDRSS_PHY_784_DATA 0x00000000 +#define DDRSS_PHY_785_DATA 0x00000001 +#define DDRSS_PHY_786_DATA 0x0000AAAA +#define DDRSS_PHY_787_DATA 0x00005555 +#define DDRSS_PHY_788_DATA 0x0000B5B5 +#define DDRSS_PHY_789_DATA 0x00004A4A +#define DDRSS_PHY_790_DATA 0x00005656 +#define DDRSS_PHY_791_DATA 0x0000A9A9 +#define DDRSS_PHY_792_DATA 0x0000A9A9 +#define DDRSS_PHY_793_DATA 0x0000B5B5 +#define DDRSS_PHY_794_DATA 0x00000000 +#define DDRSS_PHY_795_DATA 0x00000000 +#define DDRSS_PHY_796_DATA 0x2A000000 +#define DDRSS_PHY_797_DATA 0x00000808 +#define DDRSS_PHY_798_DATA 0x0F000000 +#define DDRSS_PHY_799_DATA 0x00000F0F +#define DDRSS_PHY_800_DATA 0x10200000 +#define DDRSS_PHY_801_DATA 0x0C002004 +#define DDRSS_PHY_802_DATA 0x00000000 +#define DDRSS_PHY_803_DATA 0x00000000 +#define DDRSS_PHY_804_DATA 0x55555555 +#define DDRSS_PHY_805_DATA 0xAAAAAAAA +#define DDRSS_PHY_806_DATA 0x55555555 +#define DDRSS_PHY_807_DATA 0xAAAAAAAA +#define DDRSS_PHY_808_DATA 0x00005555 +#define DDRSS_PHY_809_DATA 0x01000100 +#define DDRSS_PHY_810_DATA 0x00800180 +#define DDRSS_PHY_811_DATA 0x00000000 +#define DDRSS_PHY_812_DATA 0x00000000 +#define DDRSS_PHY_813_DATA 0x00000000 +#define DDRSS_PHY_814_DATA 0x00000000 +#define DDRSS_PHY_815_DATA 0x00000000 +#define DDRSS_PHY_816_DATA 0x00000000 +#define DDRSS_PHY_817_DATA 0x00000000 +#define DDRSS_PHY_818_DATA 0x00000000 +#define DDRSS_PHY_819_DATA 0x00000000 +#define DDRSS_PHY_820_DATA 0x00000000 +#define DDRSS_PHY_821_DATA 0x00000000 +#define DDRSS_PHY_822_DATA 0x00000000 +#define DDRSS_PHY_823_DATA 0x00000000 +#define DDRSS_PHY_824_DATA 0x00000000 +#define DDRSS_PHY_825_DATA 0x00000000 +#define DDRSS_PHY_826_DATA 0x00000000 +#define DDRSS_PHY_827_DATA 0x00000000 +#define DDRSS_PHY_828_DATA 0x00000000 +#define DDRSS_PHY_829_DATA 0x00000000 +#define DDRSS_PHY_830_DATA 0x00000000 +#define DDRSS_PHY_831_DATA 0x00000000 +#define DDRSS_PHY_832_DATA 0x00000000 +#define DDRSS_PHY_833_DATA 0x00000000 +#define DDRSS_PHY_834_DATA 0x00000104 +#define DDRSS_PHY_835_DATA 0x00000120 +#define DDRSS_PHY_836_DATA 0x00000000 +#define DDRSS_PHY_837_DATA 0x00000000 +#define DDRSS_PHY_838_DATA 0x00000000 +#define DDRSS_PHY_839_DATA 0x00000000 +#define DDRSS_PHY_840_DATA 0x00000000 +#define DDRSS_PHY_841_DATA 0x00000000 +#define DDRSS_PHY_842_DATA 0x00000000 +#define DDRSS_PHY_843_DATA 0x00000001 +#define DDRSS_PHY_844_DATA 0x07FF0000 +#define DDRSS_PHY_845_DATA 0x0080081F +#define DDRSS_PHY_846_DATA 0x00081020 +#define DDRSS_PHY_847_DATA 0x04010000 +#define DDRSS_PHY_848_DATA 0x00000000 +#define DDRSS_PHY_849_DATA 0x00000000 +#define DDRSS_PHY_850_DATA 0x00000000 +#define DDRSS_PHY_851_DATA 0x00000100 +#define DDRSS_PHY_852_DATA 0x01CC0C01 +#define DDRSS_PHY_853_DATA 0x0003CC0C +#define DDRSS_PHY_854_DATA 0x20000140 +#define DDRSS_PHY_855_DATA 0x07FF0200 +#define DDRSS_PHY_856_DATA 0x0000DD01 +#define DDRSS_PHY_857_DATA 0x10100303 +#define DDRSS_PHY_858_DATA 0x10101010 +#define DDRSS_PHY_859_DATA 0x10101010 +#define DDRSS_PHY_860_DATA 0x00041010 +#define DDRSS_PHY_861_DATA 0x00100010 +#define DDRSS_PHY_862_DATA 0x00100010 +#define DDRSS_PHY_863_DATA 0x00100010 +#define DDRSS_PHY_864_DATA 0x00100010 +#define DDRSS_PHY_865_DATA 0x00050010 +#define DDRSS_PHY_866_DATA 0x51517041 +#define DDRSS_PHY_867_DATA 0x31C06000 +#define DDRSS_PHY_868_DATA 0x07AB0340 +#define DDRSS_PHY_869_DATA 0x00C0C001 +#define DDRSS_PHY_870_DATA 0x0D0C0001 +#define DDRSS_PHY_871_DATA 0x10001000 +#define DDRSS_PHY_872_DATA 0x0C063E42 +#define DDRSS_PHY_873_DATA 0x0F0C3201 +#define DDRSS_PHY_874_DATA 0x01000140 +#define DDRSS_PHY_875_DATA 0x0C000420 +#define DDRSS_PHY_876_DATA 0x000002DD +#define DDRSS_PHY_877_DATA 0x0A0000D0 +#define DDRSS_PHY_878_DATA 0x00030200 +#define DDRSS_PHY_879_DATA 0x02800000 +#define DDRSS_PHY_880_DATA 0x80800000 +#define DDRSS_PHY_881_DATA 0x000D2010 +#define DDRSS_PHY_882_DATA 0x76543210 +#define DDRSS_PHY_883_DATA 0x00000008 +#define DDRSS_PHY_884_DATA 0x02800280 +#define DDRSS_PHY_885_DATA 0x02800280 +#define DDRSS_PHY_886_DATA 0x02800280 +#define DDRSS_PHY_887_DATA 0x02800280 +#define DDRSS_PHY_888_DATA 0x00000280 +#define DDRSS_PHY_889_DATA 0x0000A000 +#define DDRSS_PHY_890_DATA 0x00A000A0 +#define DDRSS_PHY_891_DATA 0x00A000A0 +#define DDRSS_PHY_892_DATA 0x00A000A0 +#define DDRSS_PHY_893_DATA 0x00A000A0 +#define DDRSS_PHY_894_DATA 0x00A000A0 +#define DDRSS_PHY_895_DATA 0x00A000A0 +#define DDRSS_PHY_896_DATA 0x00A000A0 +#define DDRSS_PHY_897_DATA 0x00A000A0 +#define DDRSS_PHY_898_DATA 0x006D00A0 +#define DDRSS_PHY_899_DATA 0x01A00005 +#define DDRSS_PHY_900_DATA 0x00000000 +#define DDRSS_PHY_901_DATA 0x00000000 +#define DDRSS_PHY_902_DATA 0x00080200 +#define DDRSS_PHY_903_DATA 0x00000000 +#define DDRSS_PHY_904_DATA 0x20202020 +#define DDRSS_PHY_905_DATA 0x20202020 +#define DDRSS_PHY_906_DATA 0xF0F02020 +#define DDRSS_PHY_907_DATA 0x00000000 +#define DDRSS_PHY_908_DATA 0x00000000 +#define DDRSS_PHY_909_DATA 0x00000000 +#define DDRSS_PHY_910_DATA 0x00000000 +#define DDRSS_PHY_911_DATA 0x00000000 +#define DDRSS_PHY_912_DATA 0x00000000 +#define DDRSS_PHY_913_DATA 0x00000000 +#define DDRSS_PHY_914_DATA 0x00000000 +#define DDRSS_PHY_915_DATA 0x00000000 +#define DDRSS_PHY_916_DATA 0x00000000 +#define DDRSS_PHY_917_DATA 0x00000000 +#define DDRSS_PHY_918_DATA 0x00000000 +#define DDRSS_PHY_919_DATA 0x00000000 +#define DDRSS_PHY_920_DATA 0x00000000 +#define DDRSS_PHY_921_DATA 0x00000000 +#define DDRSS_PHY_922_DATA 0x00000000 +#define DDRSS_PHY_923_DATA 0x00000000 +#define DDRSS_PHY_924_DATA 0x00000000 +#define DDRSS_PHY_925_DATA 0x00000000 +#define DDRSS_PHY_926_DATA 0x00000000 +#define DDRSS_PHY_927_DATA 0x00000000 +#define DDRSS_PHY_928_DATA 0x00000000 +#define DDRSS_PHY_929_DATA 0x00000000 +#define DDRSS_PHY_930_DATA 0x00000000 +#define DDRSS_PHY_931_DATA 0x00000000 +#define DDRSS_PHY_932_DATA 0x00000000 +#define DDRSS_PHY_933_DATA 0x00000000 +#define DDRSS_PHY_934_DATA 0x00000000 +#define DDRSS_PHY_935_DATA 0x00000000 +#define DDRSS_PHY_936_DATA 0x00000000 +#define DDRSS_PHY_937_DATA 0x00000000 +#define DDRSS_PHY_938_DATA 0x00000000 +#define DDRSS_PHY_939_DATA 0x00000000 +#define DDRSS_PHY_940_DATA 0x00000000 +#define DDRSS_PHY_941_DATA 0x00000000 +#define DDRSS_PHY_942_DATA 0x00000000 +#define DDRSS_PHY_943_DATA 0x00000000 +#define DDRSS_PHY_944_DATA 0x00000000 +#define DDRSS_PHY_945_DATA 0x00000000 +#define DDRSS_PHY_946_DATA 0x00000000 +#define DDRSS_PHY_947_DATA 0x00000000 +#define DDRSS_PHY_948_DATA 0x00000000 +#define DDRSS_PHY_949_DATA 0x00000000 +#define DDRSS_PHY_950_DATA 0x00000000 +#define DDRSS_PHY_951_DATA 0x00000000 +#define DDRSS_PHY_952_DATA 0x00000000 +#define DDRSS_PHY_953_DATA 0x00000000 +#define DDRSS_PHY_954_DATA 0x00000000 +#define DDRSS_PHY_955_DATA 0x00000000 +#define DDRSS_PHY_956_DATA 0x00000000 +#define DDRSS_PHY_957_DATA 0x00000000 +#define DDRSS_PHY_958_DATA 0x00000000 +#define DDRSS_PHY_959_DATA 0x00000000 +#define DDRSS_PHY_960_DATA 0x00000000 +#define DDRSS_PHY_961_DATA 0x00000000 +#define DDRSS_PHY_962_DATA 0x00000000 +#define DDRSS_PHY_963_DATA 0x00000000 +#define DDRSS_PHY_964_DATA 0x00000000 +#define DDRSS_PHY_965_DATA 0x00000000 +#define DDRSS_PHY_966_DATA 0x00000000 +#define DDRSS_PHY_967_DATA 0x00000000 +#define DDRSS_PHY_968_DATA 0x00000000 +#define DDRSS_PHY_969_DATA 0x00000000 +#define DDRSS_PHY_970_DATA 0x00000000 +#define DDRSS_PHY_971_DATA 0x00000000 +#define DDRSS_PHY_972_DATA 0x00000000 +#define DDRSS_PHY_973_DATA 0x00000000 +#define DDRSS_PHY_974_DATA 0x00000000 +#define DDRSS_PHY_975_DATA 0x00000000 +#define DDRSS_PHY_976_DATA 0x00000000 +#define DDRSS_PHY_977_DATA 0x00000000 +#define DDRSS_PHY_978_DATA 0x00000000 +#define DDRSS_PHY_979_DATA 0x00000000 +#define DDRSS_PHY_980_DATA 0x00000000 +#define DDRSS_PHY_981_DATA 0x00000000 +#define DDRSS_PHY_982_DATA 0x00000000 +#define DDRSS_PHY_983_DATA 0x00000000 +#define DDRSS_PHY_984_DATA 0x00000000 +#define DDRSS_PHY_985_DATA 0x00000000 +#define DDRSS_PHY_986_DATA 0x00000000 +#define DDRSS_PHY_987_DATA 0x00000000 +#define DDRSS_PHY_988_DATA 0x00000000 +#define DDRSS_PHY_989_DATA 0x00000000 +#define DDRSS_PHY_990_DATA 0x00000000 +#define DDRSS_PHY_991_DATA 0x00000000 +#define DDRSS_PHY_992_DATA 0x00000000 +#define DDRSS_PHY_993_DATA 0x00000000 +#define DDRSS_PHY_994_DATA 0x00000000 +#define DDRSS_PHY_995_DATA 0x00000000 +#define DDRSS_PHY_996_DATA 0x00000000 +#define DDRSS_PHY_997_DATA 0x00000000 +#define DDRSS_PHY_998_DATA 0x00000000 +#define DDRSS_PHY_999_DATA 0x00000000 +#define DDRSS_PHY_1000_DATA 0x00000000 +#define DDRSS_PHY_1001_DATA 0x00000000 +#define DDRSS_PHY_1002_DATA 0x00000000 +#define DDRSS_PHY_1003_DATA 0x00000000 +#define DDRSS_PHY_1004_DATA 0x00000000 +#define DDRSS_PHY_1005_DATA 0x00000000 +#define DDRSS_PHY_1006_DATA 0x00000000 +#define DDRSS_PHY_1007_DATA 0x00000000 +#define DDRSS_PHY_1008_DATA 0x00000000 +#define DDRSS_PHY_1009_DATA 0x00000000 +#define DDRSS_PHY_1010_DATA 0x00000000 +#define DDRSS_PHY_1011_DATA 0x00000000 +#define DDRSS_PHY_1012_DATA 0x00000000 +#define DDRSS_PHY_1013_DATA 0x00000000 +#define DDRSS_PHY_1014_DATA 0x00000000 +#define DDRSS_PHY_1015_DATA 0x00000000 +#define DDRSS_PHY_1016_DATA 0x00000000 +#define DDRSS_PHY_1017_DATA 0x00000000 +#define DDRSS_PHY_1018_DATA 0x00000000 +#define DDRSS_PHY_1019_DATA 0x00000000 +#define DDRSS_PHY_1020_DATA 0x00000000 +#define DDRSS_PHY_1021_DATA 0x00000000 +#define DDRSS_PHY_1022_DATA 0x00000000 +#define DDRSS_PHY_1023_DATA 0x00000000 +#define DDRSS_PHY_1024_DATA 0x00000000 +#define DDRSS_PHY_1025_DATA 0x00000000 +#define DDRSS_PHY_1026_DATA 0x00000000 +#define DDRSS_PHY_1027_DATA 0x00000000 +#define DDRSS_PHY_1028_DATA 0x00000000 +#define DDRSS_PHY_1029_DATA 0x00000100 +#define DDRSS_PHY_1030_DATA 0x00000200 +#define DDRSS_PHY_1031_DATA 0x00000000 +#define DDRSS_PHY_1032_DATA 0x00000000 +#define DDRSS_PHY_1033_DATA 0x00000000 +#define DDRSS_PHY_1034_DATA 0x00000000 +#define DDRSS_PHY_1035_DATA 0x00400000 +#define DDRSS_PHY_1036_DATA 0x00000080 +#define DDRSS_PHY_1037_DATA 0x00DCBA98 +#define DDRSS_PHY_1038_DATA 0x03000000 +#define DDRSS_PHY_1039_DATA 0x00200000 +#define DDRSS_PHY_1040_DATA 0x00000000 +#define DDRSS_PHY_1041_DATA 0x00000000 +#define DDRSS_PHY_1042_DATA 0x00000000 +#define DDRSS_PHY_1043_DATA 0x00000000 +#define DDRSS_PHY_1044_DATA 0x00000000 +#define DDRSS_PHY_1045_DATA 0x0000002A +#define DDRSS_PHY_1046_DATA 0x00000015 +#define DDRSS_PHY_1047_DATA 0x00000015 +#define DDRSS_PHY_1048_DATA 0x0000002A +#define DDRSS_PHY_1049_DATA 0x00000033 +#define DDRSS_PHY_1050_DATA 0x0000000C +#define DDRSS_PHY_1051_DATA 0x0000000C +#define DDRSS_PHY_1052_DATA 0x00000033 +#define DDRSS_PHY_1053_DATA 0x00543210 +#define DDRSS_PHY_1054_DATA 0x003F0000 +#define DDRSS_PHY_1055_DATA 0x000F013F +#define DDRSS_PHY_1056_DATA 0x20202003 +#define DDRSS_PHY_1057_DATA 0x00202020 +#define DDRSS_PHY_1058_DATA 0x20008008 +#define DDRSS_PHY_1059_DATA 0x00000810 +#define DDRSS_PHY_1060_DATA 0x00000F00 +#define DDRSS_PHY_1061_DATA 0x00000000 +#define DDRSS_PHY_1062_DATA 0x00000000 +#define DDRSS_PHY_1063_DATA 0x00000000 +#define DDRSS_PHY_1064_DATA 0x000505FF +#define DDRSS_PHY_1065_DATA 0x00030000 +#define DDRSS_PHY_1066_DATA 0x00000300 +#define DDRSS_PHY_1067_DATA 0x00000300 +#define DDRSS_PHY_1068_DATA 0x00000300 +#define DDRSS_PHY_1069_DATA 0x00000300 +#define DDRSS_PHY_1070_DATA 0x00000300 +#define DDRSS_PHY_1071_DATA 0x42080010 +#define DDRSS_PHY_1072_DATA 0x0000803E +#define DDRSS_PHY_1073_DATA 0x00000001 +#define DDRSS_PHY_1074_DATA 0x01000102 +#define DDRSS_PHY_1075_DATA 0x00008000 +#define DDRSS_PHY_1076_DATA 0x00000000 +#define DDRSS_PHY_1077_DATA 0x00000000 +#define DDRSS_PHY_1078_DATA 0x00000000 +#define DDRSS_PHY_1079_DATA 0x00000000 +#define DDRSS_PHY_1080_DATA 0x00000000 +#define DDRSS_PHY_1081_DATA 0x00000000 +#define DDRSS_PHY_1082_DATA 0x00000000 +#define DDRSS_PHY_1083_DATA 0x00000000 +#define DDRSS_PHY_1084_DATA 0x00000000 +#define DDRSS_PHY_1085_DATA 0x00000000 +#define DDRSS_PHY_1086_DATA 0x00000000 +#define DDRSS_PHY_1087_DATA 0x00000000 +#define DDRSS_PHY_1088_DATA 0x00000000 +#define DDRSS_PHY_1089_DATA 0x00000000 +#define DDRSS_PHY_1090_DATA 0x00000000 +#define DDRSS_PHY_1091_DATA 0x00000000 +#define DDRSS_PHY_1092_DATA 0x00000000 +#define DDRSS_PHY_1093_DATA 0x00000000 +#define DDRSS_PHY_1094_DATA 0x00000000 +#define DDRSS_PHY_1095_DATA 0x00000000 +#define DDRSS_PHY_1096_DATA 0x00000000 +#define DDRSS_PHY_1097_DATA 0x00000000 +#define DDRSS_PHY_1098_DATA 0x00000000 +#define DDRSS_PHY_1099_DATA 0x00000000 +#define DDRSS_PHY_1100_DATA 0x00000000 +#define DDRSS_PHY_1101_DATA 0x00000000 +#define DDRSS_PHY_1102_DATA 0x00000000 +#define DDRSS_PHY_1103_DATA 0x00000000 +#define DDRSS_PHY_1104_DATA 0x00000000 +#define DDRSS_PHY_1105_DATA 0x00000000 +#define DDRSS_PHY_1106_DATA 0x00000000 +#define DDRSS_PHY_1107_DATA 0x00000000 +#define DDRSS_PHY_1108_DATA 0x00000000 +#define DDRSS_PHY_1109_DATA 0x00000000 +#define DDRSS_PHY_1110_DATA 0x00000000 +#define DDRSS_PHY_1111_DATA 0x00000000 +#define DDRSS_PHY_1112_DATA 0x00000000 +#define DDRSS_PHY_1113_DATA 0x00000000 +#define DDRSS_PHY_1114_DATA 0x00000000 +#define DDRSS_PHY_1115_DATA 0x00000000 +#define DDRSS_PHY_1116_DATA 0x00000000 +#define DDRSS_PHY_1117_DATA 0x00000000 +#define DDRSS_PHY_1118_DATA 0x00000000 +#define DDRSS_PHY_1119_DATA 0x00000000 +#define DDRSS_PHY_1120_DATA 0x00000000 +#define DDRSS_PHY_1121_DATA 0x00000000 +#define DDRSS_PHY_1122_DATA 0x00000000 +#define DDRSS_PHY_1123_DATA 0x00000000 +#define DDRSS_PHY_1124_DATA 0x00000000 +#define DDRSS_PHY_1125_DATA 0x00000000 +#define DDRSS_PHY_1126_DATA 0x00000000 +#define DDRSS_PHY_1127_DATA 0x00000000 +#define DDRSS_PHY_1128_DATA 0x00000000 +#define DDRSS_PHY_1129_DATA 0x00000000 +#define DDRSS_PHY_1130_DATA 0x00000000 +#define DDRSS_PHY_1131_DATA 0x00000000 +#define DDRSS_PHY_1132_DATA 0x00000000 +#define DDRSS_PHY_1133_DATA 0x00000000 +#define DDRSS_PHY_1134_DATA 0x00000000 +#define DDRSS_PHY_1135_DATA 0x00000000 +#define DDRSS_PHY_1136_DATA 0x00000000 +#define DDRSS_PHY_1137_DATA 0x00000000 +#define DDRSS_PHY_1138_DATA 0x00000000 +#define DDRSS_PHY_1139_DATA 0x00000000 +#define DDRSS_PHY_1140_DATA 0x00000000 +#define DDRSS_PHY_1141_DATA 0x00000000 +#define DDRSS_PHY_1142_DATA 0x00000000 +#define DDRSS_PHY_1143_DATA 0x00000000 +#define DDRSS_PHY_1144_DATA 0x00000000 +#define DDRSS_PHY_1145_DATA 0x00000000 +#define DDRSS_PHY_1146_DATA 0x00000000 +#define DDRSS_PHY_1147_DATA 0x00000000 +#define DDRSS_PHY_1148_DATA 0x00000000 +#define DDRSS_PHY_1149_DATA 0x00000000 +#define DDRSS_PHY_1150_DATA 0x00000000 +#define DDRSS_PHY_1151_DATA 0x00000000 +#define DDRSS_PHY_1152_DATA 0x00000000 +#define DDRSS_PHY_1153_DATA 0x00000000 +#define DDRSS_PHY_1154_DATA 0x00000000 +#define DDRSS_PHY_1155_DATA 0x00000000 +#define DDRSS_PHY_1156_DATA 0x00000000 +#define DDRSS_PHY_1157_DATA 0x00000000 +#define DDRSS_PHY_1158_DATA 0x00000000 +#define DDRSS_PHY_1159_DATA 0x00000000 +#define DDRSS_PHY_1160_DATA 0x00000000 +#define DDRSS_PHY_1161_DATA 0x00000000 +#define DDRSS_PHY_1162_DATA 0x00000000 +#define DDRSS_PHY_1163_DATA 0x00000000 +#define DDRSS_PHY_1164_DATA 0x00000000 +#define DDRSS_PHY_1165_DATA 0x00000000 +#define DDRSS_PHY_1166_DATA 0x00000000 +#define DDRSS_PHY_1167_DATA 0x00000000 +#define DDRSS_PHY_1168_DATA 0x00000000 +#define DDRSS_PHY_1169_DATA 0x00000000 +#define DDRSS_PHY_1170_DATA 0x00000000 +#define DDRSS_PHY_1171_DATA 0x00000000 +#define DDRSS_PHY_1172_DATA 0x00000000 +#define DDRSS_PHY_1173_DATA 0x00000000 +#define DDRSS_PHY_1174_DATA 0x00000000 +#define DDRSS_PHY_1175_DATA 0x00000000 +#define DDRSS_PHY_1176_DATA 0x00000000 +#define DDRSS_PHY_1177_DATA 0x00000000 +#define DDRSS_PHY_1178_DATA 0x00000000 +#define DDRSS_PHY_1179_DATA 0x00000000 +#define DDRSS_PHY_1180_DATA 0x00000000 +#define DDRSS_PHY_1181_DATA 0x00000000 +#define DDRSS_PHY_1182_DATA 0x00000000 +#define DDRSS_PHY_1183_DATA 0x00000000 +#define DDRSS_PHY_1184_DATA 0x00000000 +#define DDRSS_PHY_1185_DATA 0x00000000 +#define DDRSS_PHY_1186_DATA 0x00000000 +#define DDRSS_PHY_1187_DATA 0x00000000 +#define DDRSS_PHY_1188_DATA 0x00000000 +#define DDRSS_PHY_1189_DATA 0x00000000 +#define DDRSS_PHY_1190_DATA 0x00000000 +#define DDRSS_PHY_1191_DATA 0x00000000 +#define DDRSS_PHY_1192_DATA 0x00000000 +#define DDRSS_PHY_1193_DATA 0x00000000 +#define DDRSS_PHY_1194_DATA 0x00000000 +#define DDRSS_PHY_1195_DATA 0x00000000 +#define DDRSS_PHY_1196_DATA 0x00000000 +#define DDRSS_PHY_1197_DATA 0x00000000 +#define DDRSS_PHY_1198_DATA 0x00000000 +#define DDRSS_PHY_1199_DATA 0x00000000 +#define DDRSS_PHY_1200_DATA 0x00000000 +#define DDRSS_PHY_1201_DATA 0x00000000 +#define DDRSS_PHY_1202_DATA 0x00000000 +#define DDRSS_PHY_1203_DATA 0x00000000 +#define DDRSS_PHY_1204_DATA 0x00000000 +#define DDRSS_PHY_1205_DATA 0x00000000 +#define DDRSS_PHY_1206_DATA 0x00000000 +#define DDRSS_PHY_1207_DATA 0x00000000 +#define DDRSS_PHY_1208_DATA 0x00000000 +#define DDRSS_PHY_1209_DATA 0x00000000 +#define DDRSS_PHY_1210_DATA 0x00000000 +#define DDRSS_PHY_1211_DATA 0x00000000 +#define DDRSS_PHY_1212_DATA 0x00000000 +#define DDRSS_PHY_1213_DATA 0x00000000 +#define DDRSS_PHY_1214_DATA 0x00000000 +#define DDRSS_PHY_1215_DATA 0x00000000 +#define DDRSS_PHY_1216_DATA 0x00000000 +#define DDRSS_PHY_1217_DATA 0x00000000 +#define DDRSS_PHY_1218_DATA 0x00000000 +#define DDRSS_PHY_1219_DATA 0x00000000 +#define DDRSS_PHY_1220_DATA 0x00000000 +#define DDRSS_PHY_1221_DATA 0x00000000 +#define DDRSS_PHY_1222_DATA 0x00000000 +#define DDRSS_PHY_1223_DATA 0x00000000 +#define DDRSS_PHY_1224_DATA 0x00000000 +#define DDRSS_PHY_1225_DATA 0x00000000 +#define DDRSS_PHY_1226_DATA 0x00000000 +#define DDRSS_PHY_1227_DATA 0x00000000 +#define DDRSS_PHY_1228_DATA 0x00000000 +#define DDRSS_PHY_1229_DATA 0x00000000 +#define DDRSS_PHY_1230_DATA 0x00000000 +#define DDRSS_PHY_1231_DATA 0x00000000 +#define DDRSS_PHY_1232_DATA 0x00000000 +#define DDRSS_PHY_1233_DATA 0x00000000 +#define DDRSS_PHY_1234_DATA 0x00000000 +#define DDRSS_PHY_1235_DATA 0x00000000 +#define DDRSS_PHY_1236_DATA 0x00000000 +#define DDRSS_PHY_1237_DATA 0x00000000 +#define DDRSS_PHY_1238_DATA 0x00000000 +#define DDRSS_PHY_1239_DATA 0x00000000 +#define DDRSS_PHY_1240_DATA 0x00000000 +#define DDRSS_PHY_1241_DATA 0x00000000 +#define DDRSS_PHY_1242_DATA 0x00000000 +#define DDRSS_PHY_1243_DATA 0x00000000 +#define DDRSS_PHY_1244_DATA 0x00000000 +#define DDRSS_PHY_1245_DATA 0x00000000 +#define DDRSS_PHY_1246_DATA 0x00000000 +#define DDRSS_PHY_1247_DATA 0x00000000 +#define DDRSS_PHY_1248_DATA 0x00000000 +#define DDRSS_PHY_1249_DATA 0x00000000 +#define DDRSS_PHY_1250_DATA 0x00000000 +#define DDRSS_PHY_1251_DATA 0x00000000 +#define DDRSS_PHY_1252_DATA 0x00000000 +#define DDRSS_PHY_1253_DATA 0x00000000 +#define DDRSS_PHY_1254_DATA 0x00000000 +#define DDRSS_PHY_1255_DATA 0x00000000 +#define DDRSS_PHY_1256_DATA 0x00000000 +#define DDRSS_PHY_1257_DATA 0x00000000 +#define DDRSS_PHY_1258_DATA 0x00000000 +#define DDRSS_PHY_1259_DATA 0x00000000 +#define DDRSS_PHY_1260_DATA 0x00000000 +#define DDRSS_PHY_1261_DATA 0x00000000 +#define DDRSS_PHY_1262_DATA 0x00000000 +#define DDRSS_PHY_1263_DATA 0x00000000 +#define DDRSS_PHY_1264_DATA 0x00000000 +#define DDRSS_PHY_1265_DATA 0x00000000 +#define DDRSS_PHY_1266_DATA 0x00000000 +#define DDRSS_PHY_1267_DATA 0x00000000 +#define DDRSS_PHY_1268_DATA 0x00000000 +#define DDRSS_PHY_1269_DATA 0x00000000 +#define DDRSS_PHY_1270_DATA 0x00000000 +#define DDRSS_PHY_1271_DATA 0x00000000 +#define DDRSS_PHY_1272_DATA 0x00000000 +#define DDRSS_PHY_1273_DATA 0x00000000 +#define DDRSS_PHY_1274_DATA 0x00000000 +#define DDRSS_PHY_1275_DATA 0x00000000 +#define DDRSS_PHY_1276_DATA 0x00000000 +#define DDRSS_PHY_1277_DATA 0x00000000 +#define DDRSS_PHY_1278_DATA 0x00000000 +#define DDRSS_PHY_1279_DATA 0x00000000 +#define DDRSS_PHY_1280_DATA 0x00000000 +#define DDRSS_PHY_1281_DATA 0x00010100 +#define DDRSS_PHY_1282_DATA 0x00000000 +#define DDRSS_PHY_1283_DATA 0x00000000 +#define DDRSS_PHY_1284_DATA 0x00050000 +#define DDRSS_PHY_1285_DATA 0x04000000 +#define DDRSS_PHY_1286_DATA 0x00000055 +#define DDRSS_PHY_1287_DATA 0x00000000 +#define DDRSS_PHY_1288_DATA 0x00000000 +#define DDRSS_PHY_1289_DATA 0x00000000 +#define DDRSS_PHY_1290_DATA 0x00000000 +#define DDRSS_PHY_1291_DATA 0x00002001 +#define DDRSS_PHY_1292_DATA 0x0000400F +#define DDRSS_PHY_1293_DATA 0x50020028 +#define DDRSS_PHY_1294_DATA 0x01010000 +#define DDRSS_PHY_1295_DATA 0x80080001 +#define DDRSS_PHY_1296_DATA 0x10200000 +#define DDRSS_PHY_1297_DATA 0x00000008 +#define DDRSS_PHY_1298_DATA 0x00000000 +#define DDRSS_PHY_1299_DATA 0x01090E00 +#define DDRSS_PHY_1300_DATA 0x00040101 +#define DDRSS_PHY_1301_DATA 0x0000010F +#define DDRSS_PHY_1302_DATA 0x00000000 +#define DDRSS_PHY_1303_DATA 0x0000FFFF +#define DDRSS_PHY_1304_DATA 0x00000000 +#define DDRSS_PHY_1305_DATA 0x01010000 +#define DDRSS_PHY_1306_DATA 0x01080402 +#define DDRSS_PHY_1307_DATA 0x01200F02 +#define DDRSS_PHY_1308_DATA 0x00194280 +#define DDRSS_PHY_1309_DATA 0x00000004 +#define DDRSS_PHY_1310_DATA 0x00050000 +#define DDRSS_PHY_1311_DATA 0x00000000 +#define DDRSS_PHY_1312_DATA 0x00000000 +#define DDRSS_PHY_1313_DATA 0x00000000 +#define DDRSS_PHY_1314_DATA 0x00000000 +#define DDRSS_PHY_1315_DATA 0x00000000 +#define DDRSS_PHY_1316_DATA 0x00000000 +#define DDRSS_PHY_1317_DATA 0x01000000 +#define DDRSS_PHY_1318_DATA 0x00000705 +#define DDRSS_PHY_1319_DATA 0x00000054 +#define DDRSS_PHY_1320_DATA 0x00030820 +#define DDRSS_PHY_1321_DATA 0x00010820 +#define DDRSS_PHY_1322_DATA 0x00010820 +#define DDRSS_PHY_1323_DATA 0x00010820 +#define DDRSS_PHY_1324_DATA 0x00010820 +#define DDRSS_PHY_1325_DATA 0x00010820 +#define DDRSS_PHY_1326_DATA 0x00010820 +#define DDRSS_PHY_1327_DATA 0x00010820 +#define DDRSS_PHY_1328_DATA 0x00010820 +#define DDRSS_PHY_1329_DATA 0x00000000 +#define DDRSS_PHY_1330_DATA 0x00000074 +#define DDRSS_PHY_1331_DATA 0x00000400 +#define DDRSS_PHY_1332_DATA 0x00000108 +#define DDRSS_PHY_1333_DATA 0x00000000 +#define DDRSS_PHY_1334_DATA 0x00000000 +#define DDRSS_PHY_1335_DATA 0x00000000 +#define DDRSS_PHY_1336_DATA 0x00000000 +#define DDRSS_PHY_1337_DATA 0x00000000 +#define DDRSS_PHY_1338_DATA 0x03000000 +#define DDRSS_PHY_1339_DATA 0x00000000 +#define DDRSS_PHY_1340_DATA 0x00000000 +#define DDRSS_PHY_1341_DATA 0x00000000 +#define DDRSS_PHY_1342_DATA 0x04102006 +#define DDRSS_PHY_1343_DATA 0x00041020 +#define DDRSS_PHY_1344_DATA 0x01C98C98 +#define DDRSS_PHY_1345_DATA 0x3F400000 +#define DDRSS_PHY_1346_DATA 0x3F3F1F3F +#define DDRSS_PHY_1347_DATA 0x0000001F +#define DDRSS_PHY_1348_DATA 0x00000000 +#define DDRSS_PHY_1349_DATA 0x00000000 +#define DDRSS_PHY_1350_DATA 0x00000000 +#define DDRSS_PHY_1351_DATA 0x00010000 +#define DDRSS_PHY_1352_DATA 0x00000000 +#define DDRSS_PHY_1353_DATA 0x00000000 +#define DDRSS_PHY_1354_DATA 0x00000000 +#define DDRSS_PHY_1355_DATA 0x00000000 +#define DDRSS_PHY_1356_DATA 0x76543210 +#define DDRSS_PHY_1357_DATA 0x00010198 +#define DDRSS_PHY_1358_DATA 0x00000000 +#define DDRSS_PHY_1359_DATA 0x00000000 +#define DDRSS_PHY_1360_DATA 0x00000000 +#define DDRSS_PHY_1361_DATA 0x00040700 +#define DDRSS_PHY_1362_DATA 0x00000000 +#define DDRSS_PHY_1363_DATA 0x00000000 +#define DDRSS_PHY_1364_DATA 0x00000000 +#define DDRSS_PHY_1365_DATA 0x00000000 +#define DDRSS_PHY_1366_DATA 0x00000000 +#define DDRSS_PHY_1367_DATA 0x00000002 +#define DDRSS_PHY_1368_DATA 0x00000000 +#define DDRSS_PHY_1369_DATA 0x00000000 +#define DDRSS_PHY_1370_DATA 0x00000000 +#define DDRSS_PHY_1371_DATA 0x00000000 +#define DDRSS_PHY_1372_DATA 0x00000000 +#define DDRSS_PHY_1373_DATA 0x00000000 +#define DDRSS_PHY_1374_DATA 0x00080000 +#define DDRSS_PHY_1375_DATA 0x000007FF +#define DDRSS_PHY_1376_DATA 0x00000000 +#define DDRSS_PHY_1377_DATA 0x00000000 +#define DDRSS_PHY_1378_DATA 0x00000000 +#define DDRSS_PHY_1379_DATA 0x00000000 +#define DDRSS_PHY_1380_DATA 0x00000000 +#define DDRSS_PHY_1381_DATA 0x00000000 +#define DDRSS_PHY_1382_DATA 0x000FFFFF +#define DDRSS_PHY_1383_DATA 0x000FFFFF +#define DDRSS_PHY_1384_DATA 0x0000FFFF +#define DDRSS_PHY_1385_DATA 0xFFFFFFF0 +#define DDRSS_PHY_1386_DATA 0x030FFFFF +#define DDRSS_PHY_1387_DATA 0x01FFFFFF +#define DDRSS_PHY_1388_DATA 0x0000FFFF +#define DDRSS_PHY_1389_DATA 0x00000000 +#define DDRSS_PHY_1390_DATA 0x00000000 +#define DDRSS_PHY_1391_DATA 0x00000000 +#define DDRSS_PHY_1392_DATA 0x00000000 +#define DDRSS_PHY_1393_DATA 0x0001F7C5 +#define DDRSS_PHY_1394_DATA 0x00000005 +#define DDRSS_PHY_1395_DATA 0x00000000 +#define DDRSS_PHY_1396_DATA 0x00001142 +#define DDRSS_PHY_1397_DATA 0x010207AB +#define DDRSS_PHY_1398_DATA 0x01000080 +#define DDRSS_PHY_1399_DATA 0x03900390 +#define DDRSS_PHY_1400_DATA 0x03900390 +#define DDRSS_PHY_1401_DATA 0x00000390 +#define DDRSS_PHY_1402_DATA 0x00000390 +#define DDRSS_PHY_1403_DATA 0x00000390 +#define DDRSS_PHY_1404_DATA 0x00000390 +#define DDRSS_PHY_1405_DATA 0x00000005 +#define DDRSS_PHY_1406_DATA 0x01813FFF +#define DDRSS_PHY_1407_DATA 0x000000FF +#define DDRSS_PHY_1408_DATA 0x0C000DFF +#define DDRSS_PHY_1409_DATA 0x30000DFF +#define DDRSS_PHY_1410_DATA 0x3F0DFF11 +#define DDRSS_PHY_1411_DATA 0x000100F0 +#define DDRSS_PHY_1412_DATA 0x780DFFFF +#define DDRSS_PHY_1413_DATA 0x00007E31 +#define DDRSS_PHY_1414_DATA 0x000CBF11 +#define DDRSS_PHY_1415_DATA 0x01FF0010 +#define DDRSS_PHY_1416_DATA 0x000CBF11 +#define DDRSS_PHY_1417_DATA 0x01FF0010 +#define DDRSS_PHY_1418_DATA 0x3F0DFF11 +#define DDRSS_PHY_1419_DATA 0x01FF00F0 +#define DDRSS_PHY_1420_DATA 0x3F0DFF11 +#define DDRSS_PHY_1421_DATA 0x01FF00F0 +#define DDRSS_PHY_1422_DATA 0x20040006 diff --git a/arch/arm/dts/k3-j721e-ddr.dtsi b/arch/arm/dts/k3-j721e-ddr.dtsi new file mode 100644 index 0000000..21d6380 --- /dev/null +++ b/arch/arm/dts/k3-j721e-ddr.dtsi @@ -0,0 +1,2212 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ +*/ + +/ { + memorycontroller: memorycontroller@0298e000 { + compatible = "ti,j721e-ddrss"; + reg = <0x0 0x02990000 0x0 0x4000>, + <0x0 0x0114000 0x0 0x100>; + reg-names = "cfg", "ctrl_mmr_lp4"; + power-domains = <&k3_pds 47 TI_SCI_PD_SHARED>, + <&k3_pds 90 TI_SCI_PD_SHARED>; + clocks = <&k3_clks 47 2>, <&k3_clks 30 9>; + ti,ddr-freq1 = <DDRSS_PLL_FREQUENCY_1>; + ti,ddr-freq2 = <DDRSS_PLL_FREQUENCY_2>; + ti,ddr-fhs-cnt = <DDRSS_PLL_FHS_CNT>; + + u-boot,dm-spl; + + ti,ctl-data = < + DDRSS_CTL_00_DATA + DDRSS_CTL_01_DATA + DDRSS_CTL_02_DATA + DDRSS_CTL_03_DATA + DDRSS_CTL_04_DATA + DDRSS_CTL_05_DATA + DDRSS_CTL_06_DATA + DDRSS_CTL_07_DATA + DDRSS_CTL_08_DATA + DDRSS_CTL_09_DATA + DDRSS_CTL_10_DATA + DDRSS_CTL_11_DATA + DDRSS_CTL_12_DATA + DDRSS_CTL_13_DATA + DDRSS_CTL_14_DATA + DDRSS_CTL_15_DATA + DDRSS_CTL_16_DATA + DDRSS_CTL_17_DATA + DDRSS_CTL_18_DATA + DDRSS_CTL_19_DATA + DDRSS_CTL_20_DATA + DDRSS_CTL_21_DATA + DDRSS_CTL_22_DATA + DDRSS_CTL_23_DATA + DDRSS_CTL_24_DATA + DDRSS_CTL_25_DATA + DDRSS_CTL_26_DATA + DDRSS_CTL_27_DATA + DDRSS_CTL_28_DATA + DDRSS_CTL_29_DATA + DDRSS_CTL_30_DATA + DDRSS_CTL_31_DATA + DDRSS_CTL_32_DATA + DDRSS_CTL_33_DATA + DDRSS_CTL_34_DATA + DDRSS_CTL_35_DATA + DDRSS_CTL_36_DATA + DDRSS_CTL_37_DATA + DDRSS_CTL_38_DATA + DDRSS_CTL_39_DATA + DDRSS_CTL_40_DATA + DDRSS_CTL_41_DATA + DDRSS_CTL_42_DATA + DDRSS_CTL_43_DATA + DDRSS_CTL_44_DATA + DDRSS_CTL_45_DATA + DDRSS_CTL_46_DATA + DDRSS_CTL_47_DATA + DDRSS_CTL_48_DATA + DDRSS_CTL_49_DATA + DDRSS_CTL_50_DATA + DDRSS_CTL_51_DATA + DDRSS_CTL_52_DATA + DDRSS_CTL_53_DATA + DDRSS_CTL_54_DATA + DDRSS_CTL_55_DATA + DDRSS_CTL_56_DATA + DDRSS_CTL_57_DATA + DDRSS_CTL_58_DATA + DDRSS_CTL_59_DATA + DDRSS_CTL_60_DATA + DDRSS_CTL_61_DATA + DDRSS_CTL_62_DATA + DDRSS_CTL_63_DATA + DDRSS_CTL_64_DATA + DDRSS_CTL_65_DATA + DDRSS_CTL_66_DATA + DDRSS_CTL_67_DATA + DDRSS_CTL_68_DATA + DDRSS_CTL_69_DATA + DDRSS_CTL_70_DATA + DDRSS_CTL_71_DATA + DDRSS_CTL_72_DATA + DDRSS_CTL_73_DATA + DDRSS_CTL_74_DATA + DDRSS_CTL_75_DATA + DDRSS_CTL_76_DATA + DDRSS_CTL_77_DATA + DDRSS_CTL_78_DATA + DDRSS_CTL_79_DATA + DDRSS_CTL_80_DATA + DDRSS_CTL_81_DATA + DDRSS_CTL_82_DATA + DDRSS_CTL_83_DATA + DDRSS_CTL_84_DATA + DDRSS_CTL_85_DATA + DDRSS_CTL_86_DATA + DDRSS_CTL_87_DATA + DDRSS_CTL_88_DATA + DDRSS_CTL_89_DATA + DDRSS_CTL_90_DATA + DDRSS_CTL_91_DATA + DDRSS_CTL_92_DATA + DDRSS_CTL_93_DATA + DDRSS_CTL_94_DATA + DDRSS_CTL_95_DATA + DDRSS_CTL_96_DATA + DDRSS_CTL_97_DATA + DDRSS_CTL_98_DATA + DDRSS_CTL_99_DATA + DDRSS_CTL_100_DATA + DDRSS_CTL_101_DATA + DDRSS_CTL_102_DATA + DDRSS_CTL_103_DATA + DDRSS_CTL_104_DATA + DDRSS_CTL_105_DATA + DDRSS_CTL_106_DATA + DDRSS_CTL_107_DATA + DDRSS_CTL_108_DATA + DDRSS_CTL_109_DATA + DDRSS_CTL_110_DATA + DDRSS_CTL_111_DATA + DDRSS_CTL_112_DATA + DDRSS_CTL_113_DATA + DDRSS_CTL_114_DATA + DDRSS_CTL_115_DATA + DDRSS_CTL_116_DATA + DDRSS_CTL_117_DATA + DDRSS_CTL_118_DATA + DDRSS_CTL_119_DATA + DDRSS_CTL_120_DATA + DDRSS_CTL_121_DATA + DDRSS_CTL_122_DATA + DDRSS_CTL_123_DATA + DDRSS_CTL_124_DATA + DDRSS_CTL_125_DATA + DDRSS_CTL_126_DATA + DDRSS_CTL_127_DATA + DDRSS_CTL_128_DATA + DDRSS_CTL_129_DATA + DDRSS_CTL_130_DATA + DDRSS_CTL_131_DATA + DDRSS_CTL_132_DATA + DDRSS_CTL_133_DATA + DDRSS_CTL_134_DATA + DDRSS_CTL_135_DATA + DDRSS_CTL_136_DATA + DDRSS_CTL_137_DATA + DDRSS_CTL_138_DATA + DDRSS_CTL_139_DATA + DDRSS_CTL_140_DATA + DDRSS_CTL_141_DATA + DDRSS_CTL_142_DATA + DDRSS_CTL_143_DATA + DDRSS_CTL_144_DATA + DDRSS_CTL_145_DATA + DDRSS_CTL_146_DATA + DDRSS_CTL_147_DATA + DDRSS_CTL_148_DATA + DDRSS_CTL_149_DATA + DDRSS_CTL_150_DATA + DDRSS_CTL_151_DATA + DDRSS_CTL_152_DATA + DDRSS_CTL_153_DATA + DDRSS_CTL_154_DATA + DDRSS_CTL_155_DATA + DDRSS_CTL_156_DATA + DDRSS_CTL_157_DATA + DDRSS_CTL_158_DATA + DDRSS_CTL_159_DATA + DDRSS_CTL_160_DATA + DDRSS_CTL_161_DATA + DDRSS_CTL_162_DATA + DDRSS_CTL_163_DATA + DDRSS_CTL_164_DATA + DDRSS_CTL_165_DATA + DDRSS_CTL_166_DATA + DDRSS_CTL_167_DATA + DDRSS_CTL_168_DATA + DDRSS_CTL_169_DATA + DDRSS_CTL_170_DATA + DDRSS_CTL_171_DATA + DDRSS_CTL_172_DATA + DDRSS_CTL_173_DATA + DDRSS_CTL_174_DATA + DDRSS_CTL_175_DATA + DDRSS_CTL_176_DATA + DDRSS_CTL_177_DATA + DDRSS_CTL_178_DATA + DDRSS_CTL_179_DATA + DDRSS_CTL_180_DATA + DDRSS_CTL_181_DATA + DDRSS_CTL_182_DATA + DDRSS_CTL_183_DATA + DDRSS_CTL_184_DATA + DDRSS_CTL_185_DATA + DDRSS_CTL_186_DATA + DDRSS_CTL_187_DATA + DDRSS_CTL_188_DATA + DDRSS_CTL_189_DATA + DDRSS_CTL_190_DATA + DDRSS_CTL_191_DATA + DDRSS_CTL_192_DATA + DDRSS_CTL_193_DATA + DDRSS_CTL_194_DATA + DDRSS_CTL_195_DATA + DDRSS_CTL_196_DATA + DDRSS_CTL_197_DATA + DDRSS_CTL_198_DATA + DDRSS_CTL_199_DATA + DDRSS_CTL_200_DATA + DDRSS_CTL_201_DATA + DDRSS_CTL_202_DATA + DDRSS_CTL_203_DATA + DDRSS_CTL_204_DATA + DDRSS_CTL_205_DATA + DDRSS_CTL_206_DATA + DDRSS_CTL_207_DATA + DDRSS_CTL_208_DATA + DDRSS_CTL_209_DATA + DDRSS_CTL_210_DATA + DDRSS_CTL_211_DATA + DDRSS_CTL_212_DATA + DDRSS_CTL_213_DATA + DDRSS_CTL_214_DATA + DDRSS_CTL_215_DATA + DDRSS_CTL_216_DATA + DDRSS_CTL_217_DATA + DDRSS_CTL_218_DATA + DDRSS_CTL_219_DATA + DDRSS_CTL_220_DATA + DDRSS_CTL_221_DATA + DDRSS_CTL_222_DATA + DDRSS_CTL_223_DATA + DDRSS_CTL_224_DATA + DDRSS_CTL_225_DATA + DDRSS_CTL_226_DATA + DDRSS_CTL_227_DATA + DDRSS_CTL_228_DATA + DDRSS_CTL_229_DATA + DDRSS_CTL_230_DATA + DDRSS_CTL_231_DATA + DDRSS_CTL_232_DATA + DDRSS_CTL_233_DATA + DDRSS_CTL_234_DATA + DDRSS_CTL_235_DATA + DDRSS_CTL_236_DATA + DDRSS_CTL_237_DATA + DDRSS_CTL_238_DATA + DDRSS_CTL_239_DATA + DDRSS_CTL_240_DATA + DDRSS_CTL_241_DATA + DDRSS_CTL_242_DATA + DDRSS_CTL_243_DATA + DDRSS_CTL_244_DATA + DDRSS_CTL_245_DATA + DDRSS_CTL_246_DATA + DDRSS_CTL_247_DATA + DDRSS_CTL_248_DATA + DDRSS_CTL_249_DATA + DDRSS_CTL_250_DATA + DDRSS_CTL_251_DATA + DDRSS_CTL_252_DATA + DDRSS_CTL_253_DATA + DDRSS_CTL_254_DATA + DDRSS_CTL_255_DATA + DDRSS_CTL_256_DATA + DDRSS_CTL_257_DATA + DDRSS_CTL_258_DATA + DDRSS_CTL_259_DATA + DDRSS_CTL_260_DATA + DDRSS_CTL_261_DATA + DDRSS_CTL_262_DATA + DDRSS_CTL_263_DATA + DDRSS_CTL_264_DATA + DDRSS_CTL_265_DATA + DDRSS_CTL_266_DATA + DDRSS_CTL_267_DATA + DDRSS_CTL_268_DATA + DDRSS_CTL_269_DATA + DDRSS_CTL_270_DATA + DDRSS_CTL_271_DATA + DDRSS_CTL_272_DATA + DDRSS_CTL_273_DATA + DDRSS_CTL_274_DATA + DDRSS_CTL_275_DATA + DDRSS_CTL_276_DATA + DDRSS_CTL_277_DATA + DDRSS_CTL_278_DATA + DDRSS_CTL_279_DATA + DDRSS_CTL_280_DATA + DDRSS_CTL_281_DATA + DDRSS_CTL_282_DATA + DDRSS_CTL_283_DATA + DDRSS_CTL_284_DATA + DDRSS_CTL_285_DATA + DDRSS_CTL_286_DATA + DDRSS_CTL_287_DATA + DDRSS_CTL_288_DATA + DDRSS_CTL_289_DATA + DDRSS_CTL_290_DATA + DDRSS_CTL_291_DATA + DDRSS_CTL_292_DATA + DDRSS_CTL_293_DATA + DDRSS_CTL_294_DATA + DDRSS_CTL_295_DATA + DDRSS_CTL_296_DATA + DDRSS_CTL_297_DATA + DDRSS_CTL_298_DATA + DDRSS_CTL_299_DATA + DDRSS_CTL_300_DATA + DDRSS_CTL_301_DATA + DDRSS_CTL_302_DATA + DDRSS_CTL_303_DATA + DDRSS_CTL_304_DATA + DDRSS_CTL_305_DATA + DDRSS_CTL_306_DATA + DDRSS_CTL_307_DATA + DDRSS_CTL_308_DATA + DDRSS_CTL_309_DATA + DDRSS_CTL_310_DATA + DDRSS_CTL_311_DATA + DDRSS_CTL_312_DATA + DDRSS_CTL_313_DATA + DDRSS_CTL_314_DATA + DDRSS_CTL_315_DATA + DDRSS_CTL_316_DATA + DDRSS_CTL_317_DATA + DDRSS_CTL_318_DATA + DDRSS_CTL_319_DATA + DDRSS_CTL_320_DATA + DDRSS_CTL_321_DATA + DDRSS_CTL_322_DATA + DDRSS_CTL_323_DATA + DDRSS_CTL_324_DATA + DDRSS_CTL_325_DATA + DDRSS_CTL_326_DATA + DDRSS_CTL_327_DATA + DDRSS_CTL_328_DATA + DDRSS_CTL_329_DATA + DDRSS_CTL_330_DATA + DDRSS_CTL_331_DATA + DDRSS_CTL_332_DATA + DDRSS_CTL_333_DATA + DDRSS_CTL_334_DATA + DDRSS_CTL_335_DATA + DDRSS_CTL_336_DATA + DDRSS_CTL_337_DATA + DDRSS_CTL_338_DATA + DDRSS_CTL_339_DATA + DDRSS_CTL_340_DATA + DDRSS_CTL_341_DATA + DDRSS_CTL_342_DATA + DDRSS_CTL_343_DATA + DDRSS_CTL_344_DATA + DDRSS_CTL_345_DATA + DDRSS_CTL_346_DATA + DDRSS_CTL_347_DATA + DDRSS_CTL_348_DATA + DDRSS_CTL_349_DATA + DDRSS_CTL_350_DATA + DDRSS_CTL_351_DATA + DDRSS_CTL_352_DATA + DDRSS_CTL_353_DATA + DDRSS_CTL_354_DATA + DDRSS_CTL_355_DATA + DDRSS_CTL_356_DATA + DDRSS_CTL_357_DATA + DDRSS_CTL_358_DATA + DDRSS_CTL_359_DATA + DDRSS_CTL_360_DATA + DDRSS_CTL_361_DATA + DDRSS_CTL_362_DATA + DDRSS_CTL_363_DATA + DDRSS_CTL_364_DATA + DDRSS_CTL_365_DATA + DDRSS_CTL_366_DATA + DDRSS_CTL_367_DATA + DDRSS_CTL_368_DATA + DDRSS_CTL_369_DATA + DDRSS_CTL_370_DATA + DDRSS_CTL_371_DATA + DDRSS_CTL_372_DATA + DDRSS_CTL_373_DATA + DDRSS_CTL_374_DATA + DDRSS_CTL_375_DATA + DDRSS_CTL_376_DATA + DDRSS_CTL_377_DATA + DDRSS_CTL_378_DATA + DDRSS_CTL_379_DATA + DDRSS_CTL_380_DATA + DDRSS_CTL_381_DATA + DDRSS_CTL_382_DATA + DDRSS_CTL_383_DATA + DDRSS_CTL_384_DATA + DDRSS_CTL_385_DATA + DDRSS_CTL_386_DATA + DDRSS_CTL_387_DATA + DDRSS_CTL_388_DATA + DDRSS_CTL_389_DATA + DDRSS_CTL_390_DATA + DDRSS_CTL_391_DATA + DDRSS_CTL_392_DATA + DDRSS_CTL_393_DATA + DDRSS_CTL_394_DATA + DDRSS_CTL_395_DATA + DDRSS_CTL_396_DATA + DDRSS_CTL_397_DATA + DDRSS_CTL_398_DATA + DDRSS_CTL_399_DATA + DDRSS_CTL_400_DATA + DDRSS_CTL_401_DATA + DDRSS_CTL_402_DATA + DDRSS_CTL_403_DATA + DDRSS_CTL_404_DATA + DDRSS_CTL_405_DATA + DDRSS_CTL_406_DATA + DDRSS_CTL_407_DATA + DDRSS_CTL_408_DATA + DDRSS_CTL_409_DATA + DDRSS_CTL_410_DATA + DDRSS_CTL_411_DATA + DDRSS_CTL_412_DATA + DDRSS_CTL_413_DATA + DDRSS_CTL_414_DATA + DDRSS_CTL_415_DATA + DDRSS_CTL_416_DATA + DDRSS_CTL_417_DATA + DDRSS_CTL_418_DATA + DDRSS_CTL_419_DATA + DDRSS_CTL_420_DATA + DDRSS_CTL_421_DATA + DDRSS_CTL_422_DATA + DDRSS_CTL_423_DATA + DDRSS_CTL_424_DATA + DDRSS_CTL_425_DATA + DDRSS_CTL_426_DATA + DDRSS_CTL_427_DATA + DDRSS_CTL_428_DATA + DDRSS_CTL_429_DATA + DDRSS_CTL_430_DATA + DDRSS_CTL_431_DATA + DDRSS_CTL_432_DATA + DDRSS_CTL_433_DATA + DDRSS_CTL_434_DATA + DDRSS_CTL_435_DATA + DDRSS_CTL_436_DATA + DDRSS_CTL_437_DATA + DDRSS_CTL_438_DATA + DDRSS_CTL_439_DATA + DDRSS_CTL_440_DATA + DDRSS_CTL_441_DATA + DDRSS_CTL_442_DATA + DDRSS_CTL_443_DATA + DDRSS_CTL_444_DATA + DDRSS_CTL_445_DATA + DDRSS_CTL_446_DATA + DDRSS_CTL_447_DATA + DDRSS_CTL_448_DATA + DDRSS_CTL_449_DATA + DDRSS_CTL_450_DATA + DDRSS_CTL_451_DATA + DDRSS_CTL_452_DATA + DDRSS_CTL_453_DATA + DDRSS_CTL_454_DATA + DDRSS_CTL_455_DATA + DDRSS_CTL_456_DATA + DDRSS_CTL_457_DATA + DDRSS_CTL_458_DATA + >; + + ti,pi-data = < + DDRSS_PI_00_DATA + DDRSS_PI_01_DATA + DDRSS_PI_02_DATA + DDRSS_PI_03_DATA + DDRSS_PI_04_DATA + DDRSS_PI_05_DATA + DDRSS_PI_06_DATA + DDRSS_PI_07_DATA + DDRSS_PI_08_DATA + DDRSS_PI_09_DATA + DDRSS_PI_10_DATA + DDRSS_PI_11_DATA + DDRSS_PI_12_DATA + DDRSS_PI_13_DATA + DDRSS_PI_14_DATA + DDRSS_PI_15_DATA + DDRSS_PI_16_DATA + DDRSS_PI_17_DATA + DDRSS_PI_18_DATA + DDRSS_PI_19_DATA + DDRSS_PI_20_DATA + DDRSS_PI_21_DATA + DDRSS_PI_22_DATA + DDRSS_PI_23_DATA + DDRSS_PI_24_DATA + DDRSS_PI_25_DATA + DDRSS_PI_26_DATA + DDRSS_PI_27_DATA + DDRSS_PI_28_DATA + DDRSS_PI_29_DATA + DDRSS_PI_30_DATA + DDRSS_PI_31_DATA + DDRSS_PI_32_DATA + DDRSS_PI_33_DATA + DDRSS_PI_34_DATA + DDRSS_PI_35_DATA + DDRSS_PI_36_DATA + DDRSS_PI_37_DATA + DDRSS_PI_38_DATA + DDRSS_PI_39_DATA + DDRSS_PI_40_DATA + DDRSS_PI_41_DATA + DDRSS_PI_42_DATA + DDRSS_PI_43_DATA + DDRSS_PI_44_DATA + DDRSS_PI_45_DATA + DDRSS_PI_46_DATA + DDRSS_PI_47_DATA + DDRSS_PI_48_DATA + DDRSS_PI_49_DATA + DDRSS_PI_50_DATA + DDRSS_PI_51_DATA + DDRSS_PI_52_DATA + DDRSS_PI_53_DATA + DDRSS_PI_54_DATA + DDRSS_PI_55_DATA + DDRSS_PI_56_DATA + DDRSS_PI_57_DATA + DDRSS_PI_58_DATA + DDRSS_PI_59_DATA + DDRSS_PI_60_DATA + DDRSS_PI_61_DATA + DDRSS_PI_62_DATA + DDRSS_PI_63_DATA + DDRSS_PI_64_DATA + DDRSS_PI_65_DATA + DDRSS_PI_66_DATA + DDRSS_PI_67_DATA + DDRSS_PI_68_DATA + DDRSS_PI_69_DATA + DDRSS_PI_70_DATA + DDRSS_PI_71_DATA + DDRSS_PI_72_DATA + DDRSS_PI_73_DATA + DDRSS_PI_74_DATA + DDRSS_PI_75_DATA + DDRSS_PI_76_DATA + DDRSS_PI_77_DATA + DDRSS_PI_78_DATA + DDRSS_PI_79_DATA + DDRSS_PI_80_DATA + DDRSS_PI_81_DATA + DDRSS_PI_82_DATA + DDRSS_PI_83_DATA + DDRSS_PI_84_DATA + DDRSS_PI_85_DATA + DDRSS_PI_86_DATA + DDRSS_PI_87_DATA + DDRSS_PI_88_DATA + DDRSS_PI_89_DATA + DDRSS_PI_90_DATA + DDRSS_PI_91_DATA + DDRSS_PI_92_DATA + DDRSS_PI_93_DATA + DDRSS_PI_94_DATA + DDRSS_PI_95_DATA + DDRSS_PI_96_DATA + DDRSS_PI_97_DATA + DDRSS_PI_98_DATA + DDRSS_PI_99_DATA + DDRSS_PI_100_DATA + DDRSS_PI_101_DATA + DDRSS_PI_102_DATA + DDRSS_PI_103_DATA + DDRSS_PI_104_DATA + DDRSS_PI_105_DATA + DDRSS_PI_106_DATA + DDRSS_PI_107_DATA + DDRSS_PI_108_DATA + DDRSS_PI_109_DATA + DDRSS_PI_110_DATA + DDRSS_PI_111_DATA + DDRSS_PI_112_DATA + DDRSS_PI_113_DATA + DDRSS_PI_114_DATA + DDRSS_PI_115_DATA + DDRSS_PI_116_DATA + DDRSS_PI_117_DATA + DDRSS_PI_118_DATA + DDRSS_PI_119_DATA + DDRSS_PI_120_DATA + DDRSS_PI_121_DATA + DDRSS_PI_122_DATA + DDRSS_PI_123_DATA + DDRSS_PI_124_DATA + DDRSS_PI_125_DATA + DDRSS_PI_126_DATA + DDRSS_PI_127_DATA + DDRSS_PI_128_DATA + DDRSS_PI_129_DATA + DDRSS_PI_130_DATA + DDRSS_PI_131_DATA + DDRSS_PI_132_DATA + DDRSS_PI_133_DATA + DDRSS_PI_134_DATA + DDRSS_PI_135_DATA + DDRSS_PI_136_DATA + DDRSS_PI_137_DATA + DDRSS_PI_138_DATA + DDRSS_PI_139_DATA + DDRSS_PI_140_DATA + DDRSS_PI_141_DATA + DDRSS_PI_142_DATA + DDRSS_PI_143_DATA + DDRSS_PI_144_DATA + DDRSS_PI_145_DATA + DDRSS_PI_146_DATA + DDRSS_PI_147_DATA + DDRSS_PI_148_DATA + DDRSS_PI_149_DATA + DDRSS_PI_150_DATA + DDRSS_PI_151_DATA + DDRSS_PI_152_DATA + DDRSS_PI_153_DATA + DDRSS_PI_154_DATA + DDRSS_PI_155_DATA + DDRSS_PI_156_DATA + DDRSS_PI_157_DATA + DDRSS_PI_158_DATA + DDRSS_PI_159_DATA + DDRSS_PI_160_DATA + DDRSS_PI_161_DATA + DDRSS_PI_162_DATA + DDRSS_PI_163_DATA + DDRSS_PI_164_DATA + DDRSS_PI_165_DATA + DDRSS_PI_166_DATA + DDRSS_PI_167_DATA + DDRSS_PI_168_DATA + DDRSS_PI_169_DATA + DDRSS_PI_170_DATA + DDRSS_PI_171_DATA + DDRSS_PI_172_DATA + DDRSS_PI_173_DATA + DDRSS_PI_174_DATA + DDRSS_PI_175_DATA + DDRSS_PI_176_DATA + DDRSS_PI_177_DATA + DDRSS_PI_178_DATA + DDRSS_PI_179_DATA + DDRSS_PI_180_DATA + DDRSS_PI_181_DATA + DDRSS_PI_182_DATA + DDRSS_PI_183_DATA + DDRSS_PI_184_DATA + DDRSS_PI_185_DATA + DDRSS_PI_186_DATA + DDRSS_PI_187_DATA + DDRSS_PI_188_DATA + DDRSS_PI_189_DATA + DDRSS_PI_190_DATA + DDRSS_PI_191_DATA + DDRSS_PI_192_DATA + DDRSS_PI_193_DATA + DDRSS_PI_194_DATA + DDRSS_PI_195_DATA + DDRSS_PI_196_DATA + DDRSS_PI_197_DATA + DDRSS_PI_198_DATA + DDRSS_PI_199_DATA + DDRSS_PI_200_DATA + DDRSS_PI_201_DATA + DDRSS_PI_202_DATA + DDRSS_PI_203_DATA + DDRSS_PI_204_DATA + DDRSS_PI_205_DATA + DDRSS_PI_206_DATA + DDRSS_PI_207_DATA + DDRSS_PI_208_DATA + DDRSS_PI_209_DATA + DDRSS_PI_210_DATA + DDRSS_PI_211_DATA + DDRSS_PI_212_DATA + DDRSS_PI_213_DATA + DDRSS_PI_214_DATA + DDRSS_PI_215_DATA + DDRSS_PI_216_DATA + DDRSS_PI_217_DATA + DDRSS_PI_218_DATA + DDRSS_PI_219_DATA + DDRSS_PI_220_DATA + DDRSS_PI_221_DATA + DDRSS_PI_222_DATA + DDRSS_PI_223_DATA + DDRSS_PI_224_DATA + DDRSS_PI_225_DATA + DDRSS_PI_226_DATA + DDRSS_PI_227_DATA + DDRSS_PI_228_DATA + DDRSS_PI_229_DATA + DDRSS_PI_230_DATA + DDRSS_PI_231_DATA + DDRSS_PI_232_DATA + DDRSS_PI_233_DATA + DDRSS_PI_234_DATA + DDRSS_PI_235_DATA + DDRSS_PI_236_DATA + DDRSS_PI_237_DATA + DDRSS_PI_238_DATA + DDRSS_PI_239_DATA + DDRSS_PI_240_DATA + DDRSS_PI_241_DATA + DDRSS_PI_242_DATA + DDRSS_PI_243_DATA + DDRSS_PI_244_DATA + DDRSS_PI_245_DATA + DDRSS_PI_246_DATA + DDRSS_PI_247_DATA + DDRSS_PI_248_DATA + DDRSS_PI_249_DATA + DDRSS_PI_250_DATA + DDRSS_PI_251_DATA + DDRSS_PI_252_DATA + DDRSS_PI_253_DATA + DDRSS_PI_254_DATA + DDRSS_PI_255_DATA + DDRSS_PI_256_DATA + DDRSS_PI_257_DATA + DDRSS_PI_258_DATA + DDRSS_PI_259_DATA + DDRSS_PI_260_DATA + DDRSS_PI_261_DATA + DDRSS_PI_262_DATA + DDRSS_PI_263_DATA + DDRSS_PI_264_DATA + DDRSS_PI_265_DATA + DDRSS_PI_266_DATA + DDRSS_PI_267_DATA + DDRSS_PI_268_DATA + DDRSS_PI_269_DATA + DDRSS_PI_270_DATA + DDRSS_PI_271_DATA + DDRSS_PI_272_DATA + DDRSS_PI_273_DATA + DDRSS_PI_274_DATA + DDRSS_PI_275_DATA + DDRSS_PI_276_DATA + DDRSS_PI_277_DATA + DDRSS_PI_278_DATA + DDRSS_PI_279_DATA + DDRSS_PI_280_DATA + DDRSS_PI_281_DATA + DDRSS_PI_282_DATA + DDRSS_PI_283_DATA + DDRSS_PI_284_DATA + DDRSS_PI_285_DATA + DDRSS_PI_286_DATA + DDRSS_PI_287_DATA + DDRSS_PI_288_DATA + DDRSS_PI_289_DATA + DDRSS_PI_290_DATA + DDRSS_PI_291_DATA + DDRSS_PI_292_DATA + DDRSS_PI_293_DATA + DDRSS_PI_294_DATA + DDRSS_PI_295_DATA + DDRSS_PI_296_DATA + DDRSS_PI_297_DATA + DDRSS_PI_298_DATA + DDRSS_PI_299_DATA + >; + + ti,phy-data = < + DDRSS_PHY_00_DATA + DDRSS_PHY_01_DATA + DDRSS_PHY_02_DATA + DDRSS_PHY_03_DATA + DDRSS_PHY_04_DATA + DDRSS_PHY_05_DATA + DDRSS_PHY_06_DATA + DDRSS_PHY_07_DATA + DDRSS_PHY_08_DATA + DDRSS_PHY_09_DATA + DDRSS_PHY_10_DATA + DDRSS_PHY_11_DATA + DDRSS_PHY_12_DATA + DDRSS_PHY_13_DATA + DDRSS_PHY_14_DATA + DDRSS_PHY_15_DATA + DDRSS_PHY_16_DATA + DDRSS_PHY_17_DATA + DDRSS_PHY_18_DATA + DDRSS_PHY_19_DATA + DDRSS_PHY_20_DATA + DDRSS_PHY_21_DATA + DDRSS_PHY_22_DATA + DDRSS_PHY_23_DATA + DDRSS_PHY_24_DATA + DDRSS_PHY_25_DATA + DDRSS_PHY_26_DATA + DDRSS_PHY_27_DATA + DDRSS_PHY_28_DATA + DDRSS_PHY_29_DATA + DDRSS_PHY_30_DATA + DDRSS_PHY_31_DATA + DDRSS_PHY_32_DATA + DDRSS_PHY_33_DATA + DDRSS_PHY_34_DATA + DDRSS_PHY_35_DATA + DDRSS_PHY_36_DATA + DDRSS_PHY_37_DATA + DDRSS_PHY_38_DATA + DDRSS_PHY_39_DATA + DDRSS_PHY_40_DATA + DDRSS_PHY_41_DATA + DDRSS_PHY_42_DATA + DDRSS_PHY_43_DATA + DDRSS_PHY_44_DATA + DDRSS_PHY_45_DATA + DDRSS_PHY_46_DATA + DDRSS_PHY_47_DATA + DDRSS_PHY_48_DATA + DDRSS_PHY_49_DATA + DDRSS_PHY_50_DATA + DDRSS_PHY_51_DATA + DDRSS_PHY_52_DATA + DDRSS_PHY_53_DATA + DDRSS_PHY_54_DATA + DDRSS_PHY_55_DATA + DDRSS_PHY_56_DATA + DDRSS_PHY_57_DATA + DDRSS_PHY_58_DATA + DDRSS_PHY_59_DATA + DDRSS_PHY_60_DATA + DDRSS_PHY_61_DATA + DDRSS_PHY_62_DATA + DDRSS_PHY_63_DATA + DDRSS_PHY_64_DATA + DDRSS_PHY_65_DATA + DDRSS_PHY_66_DATA + DDRSS_PHY_67_DATA + DDRSS_PHY_68_DATA + DDRSS_PHY_69_DATA + DDRSS_PHY_70_DATA + DDRSS_PHY_71_DATA + DDRSS_PHY_72_DATA + DDRSS_PHY_73_DATA + DDRSS_PHY_74_DATA + DDRSS_PHY_75_DATA + DDRSS_PHY_76_DATA + DDRSS_PHY_77_DATA + DDRSS_PHY_78_DATA + DDRSS_PHY_79_DATA + DDRSS_PHY_80_DATA + DDRSS_PHY_81_DATA + DDRSS_PHY_82_DATA + DDRSS_PHY_83_DATA + DDRSS_PHY_84_DATA + DDRSS_PHY_85_DATA + DDRSS_PHY_86_DATA + DDRSS_PHY_87_DATA + DDRSS_PHY_88_DATA + DDRSS_PHY_89_DATA + DDRSS_PHY_90_DATA + DDRSS_PHY_91_DATA + DDRSS_PHY_92_DATA + DDRSS_PHY_93_DATA + DDRSS_PHY_94_DATA + DDRSS_PHY_95_DATA + DDRSS_PHY_96_DATA + DDRSS_PHY_97_DATA + DDRSS_PHY_98_DATA + DDRSS_PHY_99_DATA + DDRSS_PHY_100_DATA + DDRSS_PHY_101_DATA + DDRSS_PHY_102_DATA + DDRSS_PHY_103_DATA + DDRSS_PHY_104_DATA + DDRSS_PHY_105_DATA + DDRSS_PHY_106_DATA + DDRSS_PHY_107_DATA + DDRSS_PHY_108_DATA + DDRSS_PHY_109_DATA + DDRSS_PHY_110_DATA + DDRSS_PHY_111_DATA + DDRSS_PHY_112_DATA + DDRSS_PHY_113_DATA + DDRSS_PHY_114_DATA + DDRSS_PHY_115_DATA + DDRSS_PHY_116_DATA + DDRSS_PHY_117_DATA + DDRSS_PHY_118_DATA + DDRSS_PHY_119_DATA + DDRSS_PHY_120_DATA + DDRSS_PHY_121_DATA + DDRSS_PHY_122_DATA + DDRSS_PHY_123_DATA + DDRSS_PHY_124_DATA + DDRSS_PHY_125_DATA + DDRSS_PHY_126_DATA + DDRSS_PHY_127_DATA + DDRSS_PHY_128_DATA + DDRSS_PHY_129_DATA + DDRSS_PHY_130_DATA + DDRSS_PHY_131_DATA + DDRSS_PHY_132_DATA + DDRSS_PHY_133_DATA + DDRSS_PHY_134_DATA + DDRSS_PHY_135_DATA + DDRSS_PHY_136_DATA + DDRSS_PHY_137_DATA + DDRSS_PHY_138_DATA + DDRSS_PHY_139_DATA + DDRSS_PHY_140_DATA + DDRSS_PHY_141_DATA + DDRSS_PHY_142_DATA + DDRSS_PHY_143_DATA + DDRSS_PHY_144_DATA + DDRSS_PHY_145_DATA + DDRSS_PHY_146_DATA + DDRSS_PHY_147_DATA + DDRSS_PHY_148_DATA + DDRSS_PHY_149_DATA + DDRSS_PHY_150_DATA + DDRSS_PHY_151_DATA + DDRSS_PHY_152_DATA + DDRSS_PHY_153_DATA + DDRSS_PHY_154_DATA + DDRSS_PHY_155_DATA + DDRSS_PHY_156_DATA + DDRSS_PHY_157_DATA + DDRSS_PHY_158_DATA + DDRSS_PHY_159_DATA + DDRSS_PHY_160_DATA + DDRSS_PHY_161_DATA + DDRSS_PHY_162_DATA + DDRSS_PHY_163_DATA + DDRSS_PHY_164_DATA + DDRSS_PHY_165_DATA + DDRSS_PHY_166_DATA + DDRSS_PHY_167_DATA + DDRSS_PHY_168_DATA + DDRSS_PHY_169_DATA + DDRSS_PHY_170_DATA + DDRSS_PHY_171_DATA + DDRSS_PHY_172_DATA + DDRSS_PHY_173_DATA + DDRSS_PHY_174_DATA + DDRSS_PHY_175_DATA + DDRSS_PHY_176_DATA + DDRSS_PHY_177_DATA + DDRSS_PHY_178_DATA + DDRSS_PHY_179_DATA + DDRSS_PHY_180_DATA + DDRSS_PHY_181_DATA + DDRSS_PHY_182_DATA + DDRSS_PHY_183_DATA + DDRSS_PHY_184_DATA + DDRSS_PHY_185_DATA + DDRSS_PHY_186_DATA + DDRSS_PHY_187_DATA + DDRSS_PHY_188_DATA + DDRSS_PHY_189_DATA + DDRSS_PHY_190_DATA + DDRSS_PHY_191_DATA + DDRSS_PHY_192_DATA + DDRSS_PHY_193_DATA + DDRSS_PHY_194_DATA + DDRSS_PHY_195_DATA + DDRSS_PHY_196_DATA + DDRSS_PHY_197_DATA + DDRSS_PHY_198_DATA + DDRSS_PHY_199_DATA + DDRSS_PHY_200_DATA + DDRSS_PHY_201_DATA + DDRSS_PHY_202_DATA + DDRSS_PHY_203_DATA + DDRSS_PHY_204_DATA + DDRSS_PHY_205_DATA + DDRSS_PHY_206_DATA + DDRSS_PHY_207_DATA + DDRSS_PHY_208_DATA + DDRSS_PHY_209_DATA + DDRSS_PHY_210_DATA + DDRSS_PHY_211_DATA + DDRSS_PHY_212_DATA + DDRSS_PHY_213_DATA + DDRSS_PHY_214_DATA + DDRSS_PHY_215_DATA + DDRSS_PHY_216_DATA + DDRSS_PHY_217_DATA + DDRSS_PHY_218_DATA + DDRSS_PHY_219_DATA + DDRSS_PHY_220_DATA + DDRSS_PHY_221_DATA + DDRSS_PHY_222_DATA + DDRSS_PHY_223_DATA + DDRSS_PHY_224_DATA + DDRSS_PHY_225_DATA + DDRSS_PHY_226_DATA + DDRSS_PHY_227_DATA + DDRSS_PHY_228_DATA + DDRSS_PHY_229_DATA + DDRSS_PHY_230_DATA + DDRSS_PHY_231_DATA + DDRSS_PHY_232_DATA + DDRSS_PHY_233_DATA + DDRSS_PHY_234_DATA + DDRSS_PHY_235_DATA + DDRSS_PHY_236_DATA + DDRSS_PHY_237_DATA + DDRSS_PHY_238_DATA + DDRSS_PHY_239_DATA + DDRSS_PHY_240_DATA + DDRSS_PHY_241_DATA + DDRSS_PHY_242_DATA + DDRSS_PHY_243_DATA + DDRSS_PHY_244_DATA + DDRSS_PHY_245_DATA + DDRSS_PHY_246_DATA + DDRSS_PHY_247_DATA + DDRSS_PHY_248_DATA + DDRSS_PHY_249_DATA + DDRSS_PHY_250_DATA + DDRSS_PHY_251_DATA + DDRSS_PHY_252_DATA + DDRSS_PHY_253_DATA + DDRSS_PHY_254_DATA + DDRSS_PHY_255_DATA + DDRSS_PHY_256_DATA + DDRSS_PHY_257_DATA + DDRSS_PHY_258_DATA + DDRSS_PHY_259_DATA + DDRSS_PHY_260_DATA + DDRSS_PHY_261_DATA + DDRSS_PHY_262_DATA + DDRSS_PHY_263_DATA + DDRSS_PHY_264_DATA + DDRSS_PHY_265_DATA + DDRSS_PHY_266_DATA + DDRSS_PHY_267_DATA + DDRSS_PHY_268_DATA + DDRSS_PHY_269_DATA + DDRSS_PHY_270_DATA + DDRSS_PHY_271_DATA + DDRSS_PHY_272_DATA + DDRSS_PHY_273_DATA + DDRSS_PHY_274_DATA + DDRSS_PHY_275_DATA + DDRSS_PHY_276_DATA + DDRSS_PHY_277_DATA + DDRSS_PHY_278_DATA + DDRSS_PHY_279_DATA + DDRSS_PHY_280_DATA + DDRSS_PHY_281_DATA + DDRSS_PHY_282_DATA + DDRSS_PHY_283_DATA + DDRSS_PHY_284_DATA + DDRSS_PHY_285_DATA + DDRSS_PHY_286_DATA + DDRSS_PHY_287_DATA + DDRSS_PHY_288_DATA + DDRSS_PHY_289_DATA + DDRSS_PHY_290_DATA + DDRSS_PHY_291_DATA + DDRSS_PHY_292_DATA + DDRSS_PHY_293_DATA + DDRSS_PHY_294_DATA + DDRSS_PHY_295_DATA + DDRSS_PHY_296_DATA + DDRSS_PHY_297_DATA + DDRSS_PHY_298_DATA + DDRSS_PHY_299_DATA + DDRSS_PHY_300_DATA + DDRSS_PHY_301_DATA + DDRSS_PHY_302_DATA + DDRSS_PHY_303_DATA + DDRSS_PHY_304_DATA + DDRSS_PHY_305_DATA + DDRSS_PHY_306_DATA + DDRSS_PHY_307_DATA + DDRSS_PHY_308_DATA + DDRSS_PHY_309_DATA + DDRSS_PHY_310_DATA + DDRSS_PHY_311_DATA + DDRSS_PHY_312_DATA + DDRSS_PHY_313_DATA + DDRSS_PHY_314_DATA + DDRSS_PHY_315_DATA + DDRSS_PHY_316_DATA + DDRSS_PHY_317_DATA + DDRSS_PHY_318_DATA + DDRSS_PHY_319_DATA + DDRSS_PHY_320_DATA + DDRSS_PHY_321_DATA + DDRSS_PHY_322_DATA + DDRSS_PHY_323_DATA + DDRSS_PHY_324_DATA + DDRSS_PHY_325_DATA + DDRSS_PHY_326_DATA + DDRSS_PHY_327_DATA + DDRSS_PHY_328_DATA + DDRSS_PHY_329_DATA + DDRSS_PHY_330_DATA + DDRSS_PHY_331_DATA + DDRSS_PHY_332_DATA + DDRSS_PHY_333_DATA + DDRSS_PHY_334_DATA + DDRSS_PHY_335_DATA + DDRSS_PHY_336_DATA + DDRSS_PHY_337_DATA + DDRSS_PHY_338_DATA + DDRSS_PHY_339_DATA + DDRSS_PHY_340_DATA + DDRSS_PHY_341_DATA + DDRSS_PHY_342_DATA + DDRSS_PHY_343_DATA + DDRSS_PHY_344_DATA + DDRSS_PHY_345_DATA + DDRSS_PHY_346_DATA + DDRSS_PHY_347_DATA + DDRSS_PHY_348_DATA + DDRSS_PHY_349_DATA + DDRSS_PHY_350_DATA + DDRSS_PHY_351_DATA + DDRSS_PHY_352_DATA + DDRSS_PHY_353_DATA + DDRSS_PHY_354_DATA + DDRSS_PHY_355_DATA + DDRSS_PHY_356_DATA + DDRSS_PHY_357_DATA + DDRSS_PHY_358_DATA + DDRSS_PHY_359_DATA + DDRSS_PHY_360_DATA + DDRSS_PHY_361_DATA + DDRSS_PHY_362_DATA + DDRSS_PHY_363_DATA + DDRSS_PHY_364_DATA + DDRSS_PHY_365_DATA + DDRSS_PHY_366_DATA + DDRSS_PHY_367_DATA + DDRSS_PHY_368_DATA + DDRSS_PHY_369_DATA + DDRSS_PHY_370_DATA + DDRSS_PHY_371_DATA + DDRSS_PHY_372_DATA + DDRSS_PHY_373_DATA + DDRSS_PHY_374_DATA + DDRSS_PHY_375_DATA + DDRSS_PHY_376_DATA + DDRSS_PHY_377_DATA + DDRSS_PHY_378_DATA + DDRSS_PHY_379_DATA + DDRSS_PHY_380_DATA + DDRSS_PHY_381_DATA + DDRSS_PHY_382_DATA + DDRSS_PHY_383_DATA + DDRSS_PHY_384_DATA + DDRSS_PHY_385_DATA + DDRSS_PHY_386_DATA + DDRSS_PHY_387_DATA + DDRSS_PHY_388_DATA + DDRSS_PHY_389_DATA + DDRSS_PHY_390_DATA + DDRSS_PHY_391_DATA + DDRSS_PHY_392_DATA + DDRSS_PHY_393_DATA + DDRSS_PHY_394_DATA + DDRSS_PHY_395_DATA + DDRSS_PHY_396_DATA + DDRSS_PHY_397_DATA + DDRSS_PHY_398_DATA + DDRSS_PHY_399_DATA + DDRSS_PHY_400_DATA + DDRSS_PHY_401_DATA + DDRSS_PHY_402_DATA + DDRSS_PHY_403_DATA + DDRSS_PHY_404_DATA + DDRSS_PHY_405_DATA + DDRSS_PHY_406_DATA + DDRSS_PHY_407_DATA + DDRSS_PHY_408_DATA + DDRSS_PHY_409_DATA + DDRSS_PHY_410_DATA + DDRSS_PHY_411_DATA + DDRSS_PHY_412_DATA + DDRSS_PHY_413_DATA + DDRSS_PHY_414_DATA + DDRSS_PHY_415_DATA + DDRSS_PHY_416_DATA + DDRSS_PHY_417_DATA + DDRSS_PHY_418_DATA + DDRSS_PHY_419_DATA + DDRSS_PHY_420_DATA + DDRSS_PHY_421_DATA + DDRSS_PHY_422_DATA + DDRSS_PHY_423_DATA + DDRSS_PHY_424_DATA + DDRSS_PHY_425_DATA + DDRSS_PHY_426_DATA + DDRSS_PHY_427_DATA + DDRSS_PHY_428_DATA + DDRSS_PHY_429_DATA + DDRSS_PHY_430_DATA + DDRSS_PHY_431_DATA + DDRSS_PHY_432_DATA + DDRSS_PHY_433_DATA + DDRSS_PHY_434_DATA + DDRSS_PHY_435_DATA + DDRSS_PHY_436_DATA + DDRSS_PHY_437_DATA + DDRSS_PHY_438_DATA + DDRSS_PHY_439_DATA + DDRSS_PHY_440_DATA + DDRSS_PHY_441_DATA + DDRSS_PHY_442_DATA + DDRSS_PHY_443_DATA + DDRSS_PHY_444_DATA + DDRSS_PHY_445_DATA + DDRSS_PHY_446_DATA + DDRSS_PHY_447_DATA + DDRSS_PHY_448_DATA + DDRSS_PHY_449_DATA + DDRSS_PHY_450_DATA + DDRSS_PHY_451_DATA + DDRSS_PHY_452_DATA + DDRSS_PHY_453_DATA + DDRSS_PHY_454_DATA + DDRSS_PHY_455_DATA + DDRSS_PHY_456_DATA + DDRSS_PHY_457_DATA + DDRSS_PHY_458_DATA + DDRSS_PHY_459_DATA + DDRSS_PHY_460_DATA + DDRSS_PHY_461_DATA + DDRSS_PHY_462_DATA + DDRSS_PHY_463_DATA + DDRSS_PHY_464_DATA + DDRSS_PHY_465_DATA + DDRSS_PHY_466_DATA + DDRSS_PHY_467_DATA + DDRSS_PHY_468_DATA + DDRSS_PHY_469_DATA + DDRSS_PHY_470_DATA + DDRSS_PHY_471_DATA + DDRSS_PHY_472_DATA + DDRSS_PHY_473_DATA + DDRSS_PHY_474_DATA + DDRSS_PHY_475_DATA + DDRSS_PHY_476_DATA + DDRSS_PHY_477_DATA + DDRSS_PHY_478_DATA + DDRSS_PHY_479_DATA + DDRSS_PHY_480_DATA + DDRSS_PHY_481_DATA + DDRSS_PHY_482_DATA + DDRSS_PHY_483_DATA + DDRSS_PHY_484_DATA + DDRSS_PHY_485_DATA + DDRSS_PHY_486_DATA + DDRSS_PHY_487_DATA + DDRSS_PHY_488_DATA + DDRSS_PHY_489_DATA + DDRSS_PHY_490_DATA + DDRSS_PHY_491_DATA + DDRSS_PHY_492_DATA + DDRSS_PHY_493_DATA + DDRSS_PHY_494_DATA + DDRSS_PHY_495_DATA + DDRSS_PHY_496_DATA + DDRSS_PHY_497_DATA + DDRSS_PHY_498_DATA + DDRSS_PHY_499_DATA + DDRSS_PHY_500_DATA + DDRSS_PHY_501_DATA + DDRSS_PHY_502_DATA + DDRSS_PHY_503_DATA + DDRSS_PHY_504_DATA + DDRSS_PHY_505_DATA + DDRSS_PHY_506_DATA + DDRSS_PHY_507_DATA + DDRSS_PHY_508_DATA + DDRSS_PHY_509_DATA + DDRSS_PHY_510_DATA + DDRSS_PHY_511_DATA + DDRSS_PHY_512_DATA + DDRSS_PHY_513_DATA + DDRSS_PHY_514_DATA + DDRSS_PHY_515_DATA + DDRSS_PHY_516_DATA + DDRSS_PHY_517_DATA + DDRSS_PHY_518_DATA + DDRSS_PHY_519_DATA + DDRSS_PHY_520_DATA + DDRSS_PHY_521_DATA + DDRSS_PHY_522_DATA + DDRSS_PHY_523_DATA + DDRSS_PHY_524_DATA + DDRSS_PHY_525_DATA + DDRSS_PHY_526_DATA + DDRSS_PHY_527_DATA + DDRSS_PHY_528_DATA + DDRSS_PHY_529_DATA + DDRSS_PHY_530_DATA + DDRSS_PHY_531_DATA + DDRSS_PHY_532_DATA + DDRSS_PHY_533_DATA + DDRSS_PHY_534_DATA + DDRSS_PHY_535_DATA + DDRSS_PHY_536_DATA + DDRSS_PHY_537_DATA + DDRSS_PHY_538_DATA + DDRSS_PHY_539_DATA + DDRSS_PHY_540_DATA + DDRSS_PHY_541_DATA + DDRSS_PHY_542_DATA + DDRSS_PHY_543_DATA + DDRSS_PHY_544_DATA + DDRSS_PHY_545_DATA + DDRSS_PHY_546_DATA + DDRSS_PHY_547_DATA + DDRSS_PHY_548_DATA + DDRSS_PHY_549_DATA + DDRSS_PHY_550_DATA + DDRSS_PHY_551_DATA + DDRSS_PHY_552_DATA + DDRSS_PHY_553_DATA + DDRSS_PHY_554_DATA + DDRSS_PHY_555_DATA + DDRSS_PHY_556_DATA + DDRSS_PHY_557_DATA + DDRSS_PHY_558_DATA + DDRSS_PHY_559_DATA + DDRSS_PHY_560_DATA + DDRSS_PHY_561_DATA + DDRSS_PHY_562_DATA + DDRSS_PHY_563_DATA + DDRSS_PHY_564_DATA + DDRSS_PHY_565_DATA + DDRSS_PHY_566_DATA + DDRSS_PHY_567_DATA + DDRSS_PHY_568_DATA + DDRSS_PHY_569_DATA + DDRSS_PHY_570_DATA + DDRSS_PHY_571_DATA + DDRSS_PHY_572_DATA + DDRSS_PHY_573_DATA + DDRSS_PHY_574_DATA + DDRSS_PHY_575_DATA + DDRSS_PHY_576_DATA + DDRSS_PHY_577_DATA + DDRSS_PHY_578_DATA + DDRSS_PHY_579_DATA + DDRSS_PHY_580_DATA + DDRSS_PHY_581_DATA + DDRSS_PHY_582_DATA + DDRSS_PHY_583_DATA + DDRSS_PHY_584_DATA + DDRSS_PHY_585_DATA + DDRSS_PHY_586_DATA + DDRSS_PHY_587_DATA + DDRSS_PHY_588_DATA + DDRSS_PHY_589_DATA + DDRSS_PHY_590_DATA + DDRSS_PHY_591_DATA + DDRSS_PHY_592_DATA + DDRSS_PHY_593_DATA + DDRSS_PHY_594_DATA + DDRSS_PHY_595_DATA + DDRSS_PHY_596_DATA + DDRSS_PHY_597_DATA + DDRSS_PHY_598_DATA + DDRSS_PHY_599_DATA + DDRSS_PHY_600_DATA + DDRSS_PHY_601_DATA + DDRSS_PHY_602_DATA + DDRSS_PHY_603_DATA + DDRSS_PHY_604_DATA + DDRSS_PHY_605_DATA + DDRSS_PHY_606_DATA + DDRSS_PHY_607_DATA + DDRSS_PHY_608_DATA + DDRSS_PHY_609_DATA + DDRSS_PHY_610_DATA + DDRSS_PHY_611_DATA + DDRSS_PHY_612_DATA + DDRSS_PHY_613_DATA + DDRSS_PHY_614_DATA + DDRSS_PHY_615_DATA + DDRSS_PHY_616_DATA + DDRSS_PHY_617_DATA + DDRSS_PHY_618_DATA + DDRSS_PHY_619_DATA + DDRSS_PHY_620_DATA + DDRSS_PHY_621_DATA + DDRSS_PHY_622_DATA + DDRSS_PHY_623_DATA + DDRSS_PHY_624_DATA + DDRSS_PHY_625_DATA + DDRSS_PHY_626_DATA + DDRSS_PHY_627_DATA + DDRSS_PHY_628_DATA + DDRSS_PHY_629_DATA + DDRSS_PHY_630_DATA + DDRSS_PHY_631_DATA + DDRSS_PHY_632_DATA + DDRSS_PHY_633_DATA + DDRSS_PHY_634_DATA + DDRSS_PHY_635_DATA + DDRSS_PHY_636_DATA + DDRSS_PHY_637_DATA + DDRSS_PHY_638_DATA + DDRSS_PHY_639_DATA + DDRSS_PHY_640_DATA + DDRSS_PHY_641_DATA + DDRSS_PHY_642_DATA + DDRSS_PHY_643_DATA + DDRSS_PHY_644_DATA + DDRSS_PHY_645_DATA + DDRSS_PHY_646_DATA + DDRSS_PHY_647_DATA + DDRSS_PHY_648_DATA + DDRSS_PHY_649_DATA + DDRSS_PHY_650_DATA + DDRSS_PHY_651_DATA + DDRSS_PHY_652_DATA + DDRSS_PHY_653_DATA + DDRSS_PHY_654_DATA + DDRSS_PHY_655_DATA + DDRSS_PHY_656_DATA + DDRSS_PHY_657_DATA + DDRSS_PHY_658_DATA + DDRSS_PHY_659_DATA + DDRSS_PHY_660_DATA + DDRSS_PHY_661_DATA + DDRSS_PHY_662_DATA + DDRSS_PHY_663_DATA + DDRSS_PHY_664_DATA + DDRSS_PHY_665_DATA + DDRSS_PHY_666_DATA + DDRSS_PHY_667_DATA + DDRSS_PHY_668_DATA + DDRSS_PHY_669_DATA + DDRSS_PHY_670_DATA + DDRSS_PHY_671_DATA + DDRSS_PHY_672_DATA + DDRSS_PHY_673_DATA + DDRSS_PHY_674_DATA + DDRSS_PHY_675_DATA + DDRSS_PHY_676_DATA + DDRSS_PHY_677_DATA + DDRSS_PHY_678_DATA + DDRSS_PHY_679_DATA + DDRSS_PHY_680_DATA + DDRSS_PHY_681_DATA + DDRSS_PHY_682_DATA + DDRSS_PHY_683_DATA + DDRSS_PHY_684_DATA + DDRSS_PHY_685_DATA + DDRSS_PHY_686_DATA + DDRSS_PHY_687_DATA + DDRSS_PHY_688_DATA + DDRSS_PHY_689_DATA + DDRSS_PHY_690_DATA + DDRSS_PHY_691_DATA + DDRSS_PHY_692_DATA + DDRSS_PHY_693_DATA + DDRSS_PHY_694_DATA + DDRSS_PHY_695_DATA + DDRSS_PHY_696_DATA + DDRSS_PHY_697_DATA + DDRSS_PHY_698_DATA + DDRSS_PHY_699_DATA + DDRSS_PHY_700_DATA + DDRSS_PHY_701_DATA + DDRSS_PHY_702_DATA + DDRSS_PHY_703_DATA + DDRSS_PHY_704_DATA + DDRSS_PHY_705_DATA + DDRSS_PHY_706_DATA + DDRSS_PHY_707_DATA + DDRSS_PHY_708_DATA + DDRSS_PHY_709_DATA + DDRSS_PHY_710_DATA + DDRSS_PHY_711_DATA + DDRSS_PHY_712_DATA + DDRSS_PHY_713_DATA + DDRSS_PHY_714_DATA + DDRSS_PHY_715_DATA + DDRSS_PHY_716_DATA + DDRSS_PHY_717_DATA + DDRSS_PHY_718_DATA + DDRSS_PHY_719_DATA + DDRSS_PHY_720_DATA + DDRSS_PHY_721_DATA + DDRSS_PHY_722_DATA + DDRSS_PHY_723_DATA + DDRSS_PHY_724_DATA + DDRSS_PHY_725_DATA + DDRSS_PHY_726_DATA + DDRSS_PHY_727_DATA + DDRSS_PHY_728_DATA + DDRSS_PHY_729_DATA + DDRSS_PHY_730_DATA + DDRSS_PHY_731_DATA + DDRSS_PHY_732_DATA + DDRSS_PHY_733_DATA + DDRSS_PHY_734_DATA + DDRSS_PHY_735_DATA + DDRSS_PHY_736_DATA + DDRSS_PHY_737_DATA + DDRSS_PHY_738_DATA + DDRSS_PHY_739_DATA + DDRSS_PHY_740_DATA + DDRSS_PHY_741_DATA + DDRSS_PHY_742_DATA + DDRSS_PHY_743_DATA + DDRSS_PHY_744_DATA + DDRSS_PHY_745_DATA + DDRSS_PHY_746_DATA + DDRSS_PHY_747_DATA + DDRSS_PHY_748_DATA + DDRSS_PHY_749_DATA + DDRSS_PHY_750_DATA + DDRSS_PHY_751_DATA + DDRSS_PHY_752_DATA + DDRSS_PHY_753_DATA + DDRSS_PHY_754_DATA + DDRSS_PHY_755_DATA + DDRSS_PHY_756_DATA + DDRSS_PHY_757_DATA + DDRSS_PHY_758_DATA + DDRSS_PHY_759_DATA + DDRSS_PHY_760_DATA + DDRSS_PHY_761_DATA + DDRSS_PHY_762_DATA + DDRSS_PHY_763_DATA + DDRSS_PHY_764_DATA + DDRSS_PHY_765_DATA + DDRSS_PHY_766_DATA + DDRSS_PHY_767_DATA + DDRSS_PHY_768_DATA + DDRSS_PHY_769_DATA + DDRSS_PHY_770_DATA + DDRSS_PHY_771_DATA + DDRSS_PHY_772_DATA + DDRSS_PHY_773_DATA + DDRSS_PHY_774_DATA + DDRSS_PHY_775_DATA + DDRSS_PHY_776_DATA + DDRSS_PHY_777_DATA + DDRSS_PHY_778_DATA + DDRSS_PHY_779_DATA + DDRSS_PHY_780_DATA + DDRSS_PHY_781_DATA + DDRSS_PHY_782_DATA + DDRSS_PHY_783_DATA + DDRSS_PHY_784_DATA + DDRSS_PHY_785_DATA + DDRSS_PHY_786_DATA + DDRSS_PHY_787_DATA + DDRSS_PHY_788_DATA + DDRSS_PHY_789_DATA + DDRSS_PHY_790_DATA + DDRSS_PHY_791_DATA + DDRSS_PHY_792_DATA + DDRSS_PHY_793_DATA + DDRSS_PHY_794_DATA + DDRSS_PHY_795_DATA + DDRSS_PHY_796_DATA + DDRSS_PHY_797_DATA + DDRSS_PHY_798_DATA + DDRSS_PHY_799_DATA + DDRSS_PHY_800_DATA + DDRSS_PHY_801_DATA + DDRSS_PHY_802_DATA + DDRSS_PHY_803_DATA + DDRSS_PHY_804_DATA + DDRSS_PHY_805_DATA + DDRSS_PHY_806_DATA + DDRSS_PHY_807_DATA + DDRSS_PHY_808_DATA + DDRSS_PHY_809_DATA + DDRSS_PHY_810_DATA + DDRSS_PHY_811_DATA + DDRSS_PHY_812_DATA + DDRSS_PHY_813_DATA + DDRSS_PHY_814_DATA + DDRSS_PHY_815_DATA + DDRSS_PHY_816_DATA + DDRSS_PHY_817_DATA + DDRSS_PHY_818_DATA + DDRSS_PHY_819_DATA + DDRSS_PHY_820_DATA + DDRSS_PHY_821_DATA + DDRSS_PHY_822_DATA + DDRSS_PHY_823_DATA + DDRSS_PHY_824_DATA + DDRSS_PHY_825_DATA + DDRSS_PHY_826_DATA + DDRSS_PHY_827_DATA + DDRSS_PHY_828_DATA + DDRSS_PHY_829_DATA + DDRSS_PHY_830_DATA + DDRSS_PHY_831_DATA + DDRSS_PHY_832_DATA + DDRSS_PHY_833_DATA + DDRSS_PHY_834_DATA + DDRSS_PHY_835_DATA + DDRSS_PHY_836_DATA + DDRSS_PHY_837_DATA + DDRSS_PHY_838_DATA + DDRSS_PHY_839_DATA + DDRSS_PHY_840_DATA + DDRSS_PHY_841_DATA + DDRSS_PHY_842_DATA + DDRSS_PHY_843_DATA + DDRSS_PHY_844_DATA + DDRSS_PHY_845_DATA + DDRSS_PHY_846_DATA + DDRSS_PHY_847_DATA + DDRSS_PHY_848_DATA + DDRSS_PHY_849_DATA + DDRSS_PHY_850_DATA + DDRSS_PHY_851_DATA + DDRSS_PHY_852_DATA + DDRSS_PHY_853_DATA + DDRSS_PHY_854_DATA + DDRSS_PHY_855_DATA + DDRSS_PHY_856_DATA + DDRSS_PHY_857_DATA + DDRSS_PHY_858_DATA + DDRSS_PHY_859_DATA + DDRSS_PHY_860_DATA + DDRSS_PHY_861_DATA + DDRSS_PHY_862_DATA + DDRSS_PHY_863_DATA + DDRSS_PHY_864_DATA + DDRSS_PHY_865_DATA + DDRSS_PHY_866_DATA + DDRSS_PHY_867_DATA + DDRSS_PHY_868_DATA + DDRSS_PHY_869_DATA + DDRSS_PHY_870_DATA + DDRSS_PHY_871_DATA + DDRSS_PHY_872_DATA + DDRSS_PHY_873_DATA + DDRSS_PHY_874_DATA + DDRSS_PHY_875_DATA + DDRSS_PHY_876_DATA + DDRSS_PHY_877_DATA + DDRSS_PHY_878_DATA + DDRSS_PHY_879_DATA + DDRSS_PHY_880_DATA + DDRSS_PHY_881_DATA + DDRSS_PHY_882_DATA + DDRSS_PHY_883_DATA + DDRSS_PHY_884_DATA + DDRSS_PHY_885_DATA + DDRSS_PHY_886_DATA + DDRSS_PHY_887_DATA + DDRSS_PHY_888_DATA + DDRSS_PHY_889_DATA + DDRSS_PHY_890_DATA + DDRSS_PHY_891_DATA + DDRSS_PHY_892_DATA + DDRSS_PHY_893_DATA + DDRSS_PHY_894_DATA + DDRSS_PHY_895_DATA + DDRSS_PHY_896_DATA + DDRSS_PHY_897_DATA + DDRSS_PHY_898_DATA + DDRSS_PHY_899_DATA + DDRSS_PHY_900_DATA + DDRSS_PHY_901_DATA + DDRSS_PHY_902_DATA + DDRSS_PHY_903_DATA + DDRSS_PHY_904_DATA + DDRSS_PHY_905_DATA + DDRSS_PHY_906_DATA + DDRSS_PHY_907_DATA + DDRSS_PHY_908_DATA + DDRSS_PHY_909_DATA + DDRSS_PHY_910_DATA + DDRSS_PHY_911_DATA + DDRSS_PHY_912_DATA + DDRSS_PHY_913_DATA + DDRSS_PHY_914_DATA + DDRSS_PHY_915_DATA + DDRSS_PHY_916_DATA + DDRSS_PHY_917_DATA + DDRSS_PHY_918_DATA + DDRSS_PHY_919_DATA + DDRSS_PHY_920_DATA + DDRSS_PHY_921_DATA + DDRSS_PHY_922_DATA + DDRSS_PHY_923_DATA + DDRSS_PHY_924_DATA + DDRSS_PHY_925_DATA + DDRSS_PHY_926_DATA + DDRSS_PHY_927_DATA + DDRSS_PHY_928_DATA + DDRSS_PHY_929_DATA + DDRSS_PHY_930_DATA + DDRSS_PHY_931_DATA + DDRSS_PHY_932_DATA + DDRSS_PHY_933_DATA + DDRSS_PHY_934_DATA + DDRSS_PHY_935_DATA + DDRSS_PHY_936_DATA + DDRSS_PHY_937_DATA + DDRSS_PHY_938_DATA + DDRSS_PHY_939_DATA + DDRSS_PHY_940_DATA + DDRSS_PHY_941_DATA + DDRSS_PHY_942_DATA + DDRSS_PHY_943_DATA + DDRSS_PHY_944_DATA + DDRSS_PHY_945_DATA + DDRSS_PHY_946_DATA + DDRSS_PHY_947_DATA + DDRSS_PHY_948_DATA + DDRSS_PHY_949_DATA + DDRSS_PHY_950_DATA + DDRSS_PHY_951_DATA + DDRSS_PHY_952_DATA + DDRSS_PHY_953_DATA + DDRSS_PHY_954_DATA + DDRSS_PHY_955_DATA + DDRSS_PHY_956_DATA + DDRSS_PHY_957_DATA + DDRSS_PHY_958_DATA + DDRSS_PHY_959_DATA + DDRSS_PHY_960_DATA + DDRSS_PHY_961_DATA + DDRSS_PHY_962_DATA + DDRSS_PHY_963_DATA + DDRSS_PHY_964_DATA + DDRSS_PHY_965_DATA + DDRSS_PHY_966_DATA + DDRSS_PHY_967_DATA + DDRSS_PHY_968_DATA + DDRSS_PHY_969_DATA + DDRSS_PHY_970_DATA + DDRSS_PHY_971_DATA + DDRSS_PHY_972_DATA + DDRSS_PHY_973_DATA + DDRSS_PHY_974_DATA + DDRSS_PHY_975_DATA + DDRSS_PHY_976_DATA + DDRSS_PHY_977_DATA + DDRSS_PHY_978_DATA + DDRSS_PHY_979_DATA + DDRSS_PHY_980_DATA + DDRSS_PHY_981_DATA + DDRSS_PHY_982_DATA + DDRSS_PHY_983_DATA + DDRSS_PHY_984_DATA + DDRSS_PHY_985_DATA + DDRSS_PHY_986_DATA + DDRSS_PHY_987_DATA + DDRSS_PHY_988_DATA + DDRSS_PHY_989_DATA + DDRSS_PHY_990_DATA + DDRSS_PHY_991_DATA + DDRSS_PHY_992_DATA + DDRSS_PHY_993_DATA + DDRSS_PHY_994_DATA + DDRSS_PHY_995_DATA + DDRSS_PHY_996_DATA + DDRSS_PHY_997_DATA + DDRSS_PHY_998_DATA + DDRSS_PHY_999_DATA + DDRSS_PHY_1000_DATA + DDRSS_PHY_1001_DATA + DDRSS_PHY_1002_DATA + DDRSS_PHY_1003_DATA + DDRSS_PHY_1004_DATA + DDRSS_PHY_1005_DATA + DDRSS_PHY_1006_DATA + DDRSS_PHY_1007_DATA + DDRSS_PHY_1008_DATA + DDRSS_PHY_1009_DATA + DDRSS_PHY_1010_DATA + DDRSS_PHY_1011_DATA + DDRSS_PHY_1012_DATA + DDRSS_PHY_1013_DATA + DDRSS_PHY_1014_DATA + DDRSS_PHY_1015_DATA + DDRSS_PHY_1016_DATA + DDRSS_PHY_1017_DATA + DDRSS_PHY_1018_DATA + DDRSS_PHY_1019_DATA + DDRSS_PHY_1020_DATA + DDRSS_PHY_1021_DATA + DDRSS_PHY_1022_DATA + DDRSS_PHY_1023_DATA + DDRSS_PHY_1024_DATA + DDRSS_PHY_1025_DATA + DDRSS_PHY_1026_DATA + DDRSS_PHY_1027_DATA + DDRSS_PHY_1028_DATA + DDRSS_PHY_1029_DATA + DDRSS_PHY_1030_DATA + DDRSS_PHY_1031_DATA + DDRSS_PHY_1032_DATA + DDRSS_PHY_1033_DATA + DDRSS_PHY_1034_DATA + DDRSS_PHY_1035_DATA + DDRSS_PHY_1036_DATA + DDRSS_PHY_1037_DATA + DDRSS_PHY_1038_DATA + DDRSS_PHY_1039_DATA + DDRSS_PHY_1040_DATA + DDRSS_PHY_1041_DATA + DDRSS_PHY_1042_DATA + DDRSS_PHY_1043_DATA + DDRSS_PHY_1044_DATA + DDRSS_PHY_1045_DATA + DDRSS_PHY_1046_DATA + DDRSS_PHY_1047_DATA + DDRSS_PHY_1048_DATA + DDRSS_PHY_1049_DATA + DDRSS_PHY_1050_DATA + DDRSS_PHY_1051_DATA + DDRSS_PHY_1052_DATA + DDRSS_PHY_1053_DATA + DDRSS_PHY_1054_DATA + DDRSS_PHY_1055_DATA + DDRSS_PHY_1056_DATA + DDRSS_PHY_1057_DATA + DDRSS_PHY_1058_DATA + DDRSS_PHY_1059_DATA + DDRSS_PHY_1060_DATA + DDRSS_PHY_1061_DATA + DDRSS_PHY_1062_DATA + DDRSS_PHY_1063_DATA + DDRSS_PHY_1064_DATA + DDRSS_PHY_1065_DATA + DDRSS_PHY_1066_DATA + DDRSS_PHY_1067_DATA + DDRSS_PHY_1068_DATA + DDRSS_PHY_1069_DATA + DDRSS_PHY_1070_DATA + DDRSS_PHY_1071_DATA + DDRSS_PHY_1072_DATA + DDRSS_PHY_1073_DATA + DDRSS_PHY_1074_DATA + DDRSS_PHY_1075_DATA + DDRSS_PHY_1076_DATA + DDRSS_PHY_1077_DATA + DDRSS_PHY_1078_DATA + DDRSS_PHY_1079_DATA + DDRSS_PHY_1080_DATA + DDRSS_PHY_1081_DATA + DDRSS_PHY_1082_DATA + DDRSS_PHY_1083_DATA + DDRSS_PHY_1084_DATA + DDRSS_PHY_1085_DATA + DDRSS_PHY_1086_DATA + DDRSS_PHY_1087_DATA + DDRSS_PHY_1088_DATA + DDRSS_PHY_1089_DATA + DDRSS_PHY_1090_DATA + DDRSS_PHY_1091_DATA + DDRSS_PHY_1092_DATA + DDRSS_PHY_1093_DATA + DDRSS_PHY_1094_DATA + DDRSS_PHY_1095_DATA + DDRSS_PHY_1096_DATA + DDRSS_PHY_1097_DATA + DDRSS_PHY_1098_DATA + DDRSS_PHY_1099_DATA + DDRSS_PHY_1100_DATA + DDRSS_PHY_1101_DATA + DDRSS_PHY_1102_DATA + DDRSS_PHY_1103_DATA + DDRSS_PHY_1104_DATA + DDRSS_PHY_1105_DATA + DDRSS_PHY_1106_DATA + DDRSS_PHY_1107_DATA + DDRSS_PHY_1108_DATA + DDRSS_PHY_1109_DATA + DDRSS_PHY_1110_DATA + DDRSS_PHY_1111_DATA + DDRSS_PHY_1112_DATA + DDRSS_PHY_1113_DATA + DDRSS_PHY_1114_DATA + DDRSS_PHY_1115_DATA + DDRSS_PHY_1116_DATA + DDRSS_PHY_1117_DATA + DDRSS_PHY_1118_DATA + DDRSS_PHY_1119_DATA + DDRSS_PHY_1120_DATA + DDRSS_PHY_1121_DATA + DDRSS_PHY_1122_DATA + DDRSS_PHY_1123_DATA + DDRSS_PHY_1124_DATA + DDRSS_PHY_1125_DATA + DDRSS_PHY_1126_DATA + DDRSS_PHY_1127_DATA + DDRSS_PHY_1128_DATA + DDRSS_PHY_1129_DATA + DDRSS_PHY_1130_DATA + DDRSS_PHY_1131_DATA + DDRSS_PHY_1132_DATA + DDRSS_PHY_1133_DATA + DDRSS_PHY_1134_DATA + DDRSS_PHY_1135_DATA + DDRSS_PHY_1136_DATA + DDRSS_PHY_1137_DATA + DDRSS_PHY_1138_DATA + DDRSS_PHY_1139_DATA + DDRSS_PHY_1140_DATA + DDRSS_PHY_1141_DATA + DDRSS_PHY_1142_DATA + DDRSS_PHY_1143_DATA + DDRSS_PHY_1144_DATA + DDRSS_PHY_1145_DATA + DDRSS_PHY_1146_DATA + DDRSS_PHY_1147_DATA + DDRSS_PHY_1148_DATA + DDRSS_PHY_1149_DATA + DDRSS_PHY_1150_DATA + DDRSS_PHY_1151_DATA + DDRSS_PHY_1152_DATA + DDRSS_PHY_1153_DATA + DDRSS_PHY_1154_DATA + DDRSS_PHY_1155_DATA + DDRSS_PHY_1156_DATA + DDRSS_PHY_1157_DATA + DDRSS_PHY_1158_DATA + DDRSS_PHY_1159_DATA + DDRSS_PHY_1160_DATA + DDRSS_PHY_1161_DATA + DDRSS_PHY_1162_DATA + DDRSS_PHY_1163_DATA + DDRSS_PHY_1164_DATA + DDRSS_PHY_1165_DATA + DDRSS_PHY_1166_DATA + DDRSS_PHY_1167_DATA + DDRSS_PHY_1168_DATA + DDRSS_PHY_1169_DATA + DDRSS_PHY_1170_DATA + DDRSS_PHY_1171_DATA + DDRSS_PHY_1172_DATA + DDRSS_PHY_1173_DATA + DDRSS_PHY_1174_DATA + DDRSS_PHY_1175_DATA + DDRSS_PHY_1176_DATA + DDRSS_PHY_1177_DATA + DDRSS_PHY_1178_DATA + DDRSS_PHY_1179_DATA + DDRSS_PHY_1180_DATA + DDRSS_PHY_1181_DATA + DDRSS_PHY_1182_DATA + DDRSS_PHY_1183_DATA + DDRSS_PHY_1184_DATA + DDRSS_PHY_1185_DATA + DDRSS_PHY_1186_DATA + DDRSS_PHY_1187_DATA + DDRSS_PHY_1188_DATA + DDRSS_PHY_1189_DATA + DDRSS_PHY_1190_DATA + DDRSS_PHY_1191_DATA + DDRSS_PHY_1192_DATA + DDRSS_PHY_1193_DATA + DDRSS_PHY_1194_DATA + DDRSS_PHY_1195_DATA + DDRSS_PHY_1196_DATA + DDRSS_PHY_1197_DATA + DDRSS_PHY_1198_DATA + DDRSS_PHY_1199_DATA + DDRSS_PHY_1200_DATA + DDRSS_PHY_1201_DATA + DDRSS_PHY_1202_DATA + DDRSS_PHY_1203_DATA + DDRSS_PHY_1204_DATA + DDRSS_PHY_1205_DATA + DDRSS_PHY_1206_DATA + DDRSS_PHY_1207_DATA + DDRSS_PHY_1208_DATA + DDRSS_PHY_1209_DATA + DDRSS_PHY_1210_DATA + DDRSS_PHY_1211_DATA + DDRSS_PHY_1212_DATA + DDRSS_PHY_1213_DATA + DDRSS_PHY_1214_DATA + DDRSS_PHY_1215_DATA + DDRSS_PHY_1216_DATA + DDRSS_PHY_1217_DATA + DDRSS_PHY_1218_DATA + DDRSS_PHY_1219_DATA + DDRSS_PHY_1220_DATA + DDRSS_PHY_1221_DATA + DDRSS_PHY_1222_DATA + DDRSS_PHY_1223_DATA + DDRSS_PHY_1224_DATA + DDRSS_PHY_1225_DATA + DDRSS_PHY_1226_DATA + DDRSS_PHY_1227_DATA + DDRSS_PHY_1228_DATA + DDRSS_PHY_1229_DATA + DDRSS_PHY_1230_DATA + DDRSS_PHY_1231_DATA + DDRSS_PHY_1232_DATA + DDRSS_PHY_1233_DATA + DDRSS_PHY_1234_DATA + DDRSS_PHY_1235_DATA + DDRSS_PHY_1236_DATA + DDRSS_PHY_1237_DATA + DDRSS_PHY_1238_DATA + DDRSS_PHY_1239_DATA + DDRSS_PHY_1240_DATA + DDRSS_PHY_1241_DATA + DDRSS_PHY_1242_DATA + DDRSS_PHY_1243_DATA + DDRSS_PHY_1244_DATA + DDRSS_PHY_1245_DATA + DDRSS_PHY_1246_DATA + DDRSS_PHY_1247_DATA + DDRSS_PHY_1248_DATA + DDRSS_PHY_1249_DATA + DDRSS_PHY_1250_DATA + DDRSS_PHY_1251_DATA + DDRSS_PHY_1252_DATA + DDRSS_PHY_1253_DATA + DDRSS_PHY_1254_DATA + DDRSS_PHY_1255_DATA + DDRSS_PHY_1256_DATA + DDRSS_PHY_1257_DATA + DDRSS_PHY_1258_DATA + DDRSS_PHY_1259_DATA + DDRSS_PHY_1260_DATA + DDRSS_PHY_1261_DATA + DDRSS_PHY_1262_DATA + DDRSS_PHY_1263_DATA + DDRSS_PHY_1264_DATA + DDRSS_PHY_1265_DATA + DDRSS_PHY_1266_DATA + DDRSS_PHY_1267_DATA + DDRSS_PHY_1268_DATA + DDRSS_PHY_1269_DATA + DDRSS_PHY_1270_DATA + DDRSS_PHY_1271_DATA + DDRSS_PHY_1272_DATA + DDRSS_PHY_1273_DATA + DDRSS_PHY_1274_DATA + DDRSS_PHY_1275_DATA + DDRSS_PHY_1276_DATA + DDRSS_PHY_1277_DATA + DDRSS_PHY_1278_DATA + DDRSS_PHY_1279_DATA + DDRSS_PHY_1280_DATA + DDRSS_PHY_1281_DATA + DDRSS_PHY_1282_DATA + DDRSS_PHY_1283_DATA + DDRSS_PHY_1284_DATA + DDRSS_PHY_1285_DATA + DDRSS_PHY_1286_DATA + DDRSS_PHY_1287_DATA + DDRSS_PHY_1288_DATA + DDRSS_PHY_1289_DATA + DDRSS_PHY_1290_DATA + DDRSS_PHY_1291_DATA + DDRSS_PHY_1292_DATA + DDRSS_PHY_1293_DATA + DDRSS_PHY_1294_DATA + DDRSS_PHY_1295_DATA + DDRSS_PHY_1296_DATA + DDRSS_PHY_1297_DATA + DDRSS_PHY_1298_DATA + DDRSS_PHY_1299_DATA + DDRSS_PHY_1300_DATA + DDRSS_PHY_1301_DATA + DDRSS_PHY_1302_DATA + DDRSS_PHY_1303_DATA + DDRSS_PHY_1304_DATA + DDRSS_PHY_1305_DATA + DDRSS_PHY_1306_DATA + DDRSS_PHY_1307_DATA + DDRSS_PHY_1308_DATA + DDRSS_PHY_1309_DATA + DDRSS_PHY_1310_DATA + DDRSS_PHY_1311_DATA + DDRSS_PHY_1312_DATA + DDRSS_PHY_1313_DATA + DDRSS_PHY_1314_DATA + DDRSS_PHY_1315_DATA + DDRSS_PHY_1316_DATA + DDRSS_PHY_1317_DATA + DDRSS_PHY_1318_DATA + DDRSS_PHY_1319_DATA + DDRSS_PHY_1320_DATA + DDRSS_PHY_1321_DATA + DDRSS_PHY_1322_DATA + DDRSS_PHY_1323_DATA + DDRSS_PHY_1324_DATA + DDRSS_PHY_1325_DATA + DDRSS_PHY_1326_DATA + DDRSS_PHY_1327_DATA + DDRSS_PHY_1328_DATA + DDRSS_PHY_1329_DATA + DDRSS_PHY_1330_DATA + DDRSS_PHY_1331_DATA + DDRSS_PHY_1332_DATA + DDRSS_PHY_1333_DATA + DDRSS_PHY_1334_DATA + DDRSS_PHY_1335_DATA + DDRSS_PHY_1336_DATA + DDRSS_PHY_1337_DATA + DDRSS_PHY_1338_DATA + DDRSS_PHY_1339_DATA + DDRSS_PHY_1340_DATA + DDRSS_PHY_1341_DATA + DDRSS_PHY_1342_DATA + DDRSS_PHY_1343_DATA + DDRSS_PHY_1344_DATA + DDRSS_PHY_1345_DATA + DDRSS_PHY_1346_DATA + DDRSS_PHY_1347_DATA + DDRSS_PHY_1348_DATA + DDRSS_PHY_1349_DATA + DDRSS_PHY_1350_DATA + DDRSS_PHY_1351_DATA + DDRSS_PHY_1352_DATA + DDRSS_PHY_1353_DATA + DDRSS_PHY_1354_DATA + DDRSS_PHY_1355_DATA + DDRSS_PHY_1356_DATA + DDRSS_PHY_1357_DATA + DDRSS_PHY_1358_DATA + DDRSS_PHY_1359_DATA + DDRSS_PHY_1360_DATA + DDRSS_PHY_1361_DATA + DDRSS_PHY_1362_DATA + DDRSS_PHY_1363_DATA + DDRSS_PHY_1364_DATA + DDRSS_PHY_1365_DATA + DDRSS_PHY_1366_DATA + DDRSS_PHY_1367_DATA + DDRSS_PHY_1368_DATA + DDRSS_PHY_1369_DATA + DDRSS_PHY_1370_DATA + DDRSS_PHY_1371_DATA + DDRSS_PHY_1372_DATA + DDRSS_PHY_1373_DATA + DDRSS_PHY_1374_DATA + DDRSS_PHY_1375_DATA + DDRSS_PHY_1376_DATA + DDRSS_PHY_1377_DATA + DDRSS_PHY_1378_DATA + DDRSS_PHY_1379_DATA + DDRSS_PHY_1380_DATA + DDRSS_PHY_1381_DATA + DDRSS_PHY_1382_DATA + DDRSS_PHY_1383_DATA + DDRSS_PHY_1384_DATA + DDRSS_PHY_1385_DATA + DDRSS_PHY_1386_DATA + DDRSS_PHY_1387_DATA + DDRSS_PHY_1388_DATA + DDRSS_PHY_1389_DATA + DDRSS_PHY_1390_DATA + DDRSS_PHY_1391_DATA + DDRSS_PHY_1392_DATA + DDRSS_PHY_1393_DATA + DDRSS_PHY_1394_DATA + DDRSS_PHY_1395_DATA + DDRSS_PHY_1396_DATA + DDRSS_PHY_1397_DATA + DDRSS_PHY_1398_DATA + DDRSS_PHY_1399_DATA + DDRSS_PHY_1400_DATA + DDRSS_PHY_1401_DATA + DDRSS_PHY_1402_DATA + DDRSS_PHY_1403_DATA + DDRSS_PHY_1404_DATA + DDRSS_PHY_1405_DATA + DDRSS_PHY_1406_DATA + DDRSS_PHY_1407_DATA + DDRSS_PHY_1408_DATA + DDRSS_PHY_1409_DATA + DDRSS_PHY_1410_DATA + DDRSS_PHY_1411_DATA + DDRSS_PHY_1412_DATA + DDRSS_PHY_1413_DATA + DDRSS_PHY_1414_DATA + DDRSS_PHY_1415_DATA + DDRSS_PHY_1416_DATA + DDRSS_PHY_1417_DATA + DDRSS_PHY_1418_DATA + DDRSS_PHY_1419_DATA + DDRSS_PHY_1420_DATA + DDRSS_PHY_1421_DATA + DDRSS_PHY_1422_DATA + >; + }; +}; diff --git a/arch/arm/dts/k3-j721e-main.dtsi b/arch/arm/dts/k3-j721e-main.dtsi index 6bd59ba..3a07632 100644 --- a/arch/arm/dts/k3-j721e-main.dtsi +++ b/arch/arm/dts/k3-j721e-main.dtsi @@ -339,4 +339,28 @@ ti,sci-proc-ids = <0x30 0xFF>; resets = <&k3_reset 15 1>; }; + + ufs_wrapper: ufs-wrapper@4e80000 { + compatible = "ti,j721e-ufs"; + reg = <0x0 0x4e80000 0x0 0x100>; + power-domains = <&k3_pds 277 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 277 1>; + assigned-clocks = <&k3_clks 277 1>; + assigned-clock-parents = <&k3_clks 277 4>; + ranges; + #address-cells = <2>; + #size-cells = <2>; + + ufs@4e84000 { + compatible = "cdns,ufshc-m31-16nm", "jedec,ufs-2.0"; + reg = <0x0 0x4e84000 0x0 0x10000>; + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; + freq-table-hz = <0 0>, <0 0>; + clocks = <&k3_clks 277 0>, <&k3_clks 277 1>; + clock-names = "core_clk", "phy_clk"; + assigned-clocks = <&k3_clks 277 1>; + assigned-clock-parents = <&k3_clks 277 4>; + dma-coherent; + }; + }; }; diff --git a/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi b/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi index b958b5b..92beeea 100644 --- a/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi +++ b/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi @@ -107,4 +107,30 @@ loczrama = <1>; }; }; + + fss: fss@47000000 { + compatible = "syscon", "simple-mfd"; + reg = <0x0 0x47000000 0x0 0x100>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + hbmc_mux: hbmc-mux { + compatible = "mmio-mux"; + #mux-control-cells = <1>; + mux-reg-masks = <0x4 0x2>; /* HBMC select */ + }; + + hbmc: hyperbus@47034000 { + compatible = "ti,j721e-hbmc", "ti,am654-hbmc"; + reg = <0x0 0x47034000 0x0 0x100>, + <0x5 0x00000000 0x1 0x0000000>; + power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; + #address-cells = <2>; + #size-cells = <1>; + mux-controls = <&hbmc_mux 0>; + assigned-clocks = <&k3_clks 102 0>; + assigned-clock-rates = <250000000>; + }; + }; }; diff --git a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts index 815e334..54d7998 100644 --- a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts +++ b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts @@ -6,6 +6,8 @@ /dts-v1/; #include "k3-j721e-som-p0.dtsi" +#include "k3-j721e-ddr-evm-lp4-3733.dtsi" +#include "k3-j721e-ddr.dtsi" / { aliases { diff --git a/arch/arm/dts/k3-j721e-som-p0.dtsi b/arch/arm/dts/k3-j721e-som-p0.dtsi index 1884fc7..1e1519f 100644 --- a/arch/arm/dts/k3-j721e-som-p0.dtsi +++ b/arch/arm/dts/k3-j721e-som-p0.dtsi @@ -27,3 +27,37 @@ }; }; }; + +&wkup_pmx0 { + mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-pins-default { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 1) /* (E20) MCU_OSPI0_CLK.MCU_HYPERBUS0_CK */ + J721E_WKUP_IOPAD(0x4, PIN_OUTPUT, 1) /* (C21) MCU_OSPI0_LBCLKO.MCU_HYPERBUS0_CKn */ + J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 1) /* (F19) MCU_OSPI0_CSn0.MCU_HYPERBUS0_CSn0 */ + J721E_WKUP_IOPAD(0x54, PIN_OUTPUT, 3) /* (E22) MCU_OSPI1_CSn1.MCU_HYPERBUS0_CSn1 */ + J721E_WKUP_IOPAD(0x30, PIN_OUTPUT, 1) /* (E19) MCU_OSPI0_CSn1.MCU_HYPERBUS0_RESETn */ + J721E_WKUP_IOPAD(0x8, PIN_INPUT, 1) /* (D21) MCU_OSPI0_DQS.MCU_HYPERBUS0_RWDS */ + J721E_WKUP_IOPAD(0xc, PIN_INPUT, 1) /* (D20) MCU_OSPI0_D0.MCU_HYPERBUS0_DQ0 */ + J721E_WKUP_IOPAD(0x10, PIN_INPUT, 1) /* (G19) MCU_OSPI0_D1.MCU_HYPERBUS0_DQ1 */ + J721E_WKUP_IOPAD(0x14, PIN_INPUT, 1) /* (G20) MCU_OSPI0_D2.MCU_HYPERBUS0_DQ2 */ + J721E_WKUP_IOPAD(0x18, PIN_INPUT, 1) /* (F20) MCU_OSPI0_D3.MCU_HYPERBUS0_DQ3 */ + J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 1) /* (F21) MCU_OSPI0_D4.MCU_HYPERBUS0_DQ4 */ + J721E_WKUP_IOPAD(0x20, PIN_INPUT, 1) /* (E21) MCU_OSPI0_D5.MCU_HYPERBUS0_DQ5 */ + J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* (B22) MCU_OSPI0_D6.MCU_HYPERBUS0_DQ6 */ + J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* (G21) MCU_OSPI0_D7.MCU_HYPERBUS0_DQ7 */ + >; + }; +}; + +&hbmc { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_fss0_hpb0_pins_default>; + ranges = <0x0 0x0 0x5 0x0 0x4000000>, /* 64MB Flash on CS0 */ + <0x1 0x0 0x5 0x4000000 0x800000>; /* 8MB RAM on CS1 */ + + flash@0,0 { + compatible = "cypress,hyperflash", "cfi-flash"; + reg = <0x0 0x0 0x4000000>; + }; +}; diff --git a/arch/arm/dts/keystone-k2e-evm-u-boot.dtsi b/arch/arm/dts/keystone-k2e-evm-u-boot.dtsi index aecb4dd..c94165f 100644 --- a/arch/arm/dts/keystone-k2e-evm-u-boot.dtsi +++ b/arch/arm/dts/keystone-k2e-evm-u-boot.dtsi @@ -7,8 +7,40 @@ soc { u-boot,dm-pre-reloc; }; + aliases { + usb0 = &usb; + usb1 = &usb1; + }; }; &i2c1 { u-boot,dm-pre-reloc; }; + +&usb_phy { + #phy-cells = <0>; + psc-domain = <2>; +}; + +&usb { + dwc3@2690000 { + phys = <&usb_phy>; + dr_mode = "host"; + snps,u2ss_inp3_quirk; + status = "okay"; + }; +}; + +&usb1_phy { + #phy-cells = <0>; + psc-domain = <1>; +}; + +&usb1 { + dwc3@25010000 { + phys = <&usb1_phy>; + dr_mode = "peripheral"; + snps,u2ss_inp3_quirk; + status = "okay"; + }; +}; diff --git a/arch/arm/dts/keystone-k2g-evm-u-boot.dtsi b/arch/arm/dts/keystone-k2g-evm-u-boot.dtsi index 80f1f60..e8e7009 100644 --- a/arch/arm/dts/keystone-k2g-evm-u-boot.dtsi +++ b/arch/arm/dts/keystone-k2g-evm-u-boot.dtsi @@ -7,6 +7,10 @@ soc { u-boot,dm-pre-reloc; }; + aliases { + usb0 = &usb0; + usb1 = &usb1; + }; }; &i2c0 { @@ -16,3 +20,27 @@ &i2c1 { u-boot,dm-pre-reloc; }; + +&usb0_phy { + compatible = "ti,keystone-usbphy"; + #phy-cells = <0>; + reg = <0x2620738 24>; + psc-domain = <25>; +}; + +&usb0 { + phys = <&usb0_phy>; + snps,u2ss_inp3_quirk; +}; + +&usb1_phy { + compatible = "ti,keystone-usbphy"; + #phy-cells = <0>; + reg = <0x2620750 24>; + psc-domain = <26>; +}; + +&usb1 { + phys = <&usb1_phy>; + snps,u2ss_inp3_quirk; +}; diff --git a/arch/arm/dts/keystone-k2hk-evm-u-boot.dtsi b/arch/arm/dts/keystone-k2hk-evm-u-boot.dtsi index aecb4dd..1c2f349 100644 --- a/arch/arm/dts/keystone-k2hk-evm-u-boot.dtsi +++ b/arch/arm/dts/keystone-k2hk-evm-u-boot.dtsi @@ -12,3 +12,17 @@ &i2c1 { u-boot,dm-pre-reloc; }; + +&usb_phy { + #phy-cells = <0>; + psc-domain = <2>; +}; + +&usb { + dwc3@2690000 { + phys = <&usb_phy>; + dr_mode = "host"; + snps,u2ss_inp3_quirk; + status = "okay"; + }; +}; diff --git a/arch/arm/dts/keystone-k2l-evm-u-boot.dtsi b/arch/arm/dts/keystone-k2l-evm-u-boot.dtsi new file mode 100644 index 0000000..0a507d0 --- /dev/null +++ b/arch/arm/dts/keystone-k2l-evm-u-boot.dtsi @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ + */ + +&usb_phy { + #phy-cells = <0>; + psc-domain = <2>; +}; + +&usb { + dwc3@2690000 { + phys = <&usb_phy>; + dr_mode = "host"; + snps,u2ss_inp3_quirk; + status = "okay"; + }; +}; diff --git a/arch/arm/dts/omap5-u-boot.dtsi b/arch/arm/dts/omap5-u-boot.dtsi index 1b1d765..39071e2 100644 --- a/arch/arm/dts/omap5-u-boot.dtsi +++ b/arch/arm/dts/omap5-u-boot.dtsi @@ -22,6 +22,7 @@ ocp2scp@4a080000 { compatible = "ti,omap-ocp2scp", "simple-bus"; + u-boot,dm-spl; }; ocp2scp@4a090000 { diff --git a/arch/arm/dts/sam9x60.dtsi b/arch/arm/dts/sam9x60.dtsi index e01539e..41ac1f1 100644 --- a/arch/arm/dts/sam9x60.dtsi +++ b/arch/arm/dts/sam9x60.dtsi @@ -73,6 +73,16 @@ status = "disabled"; }; + flx0: flexcom@f801c600 { + compatible = "atmel,sama5d2-flexcom"; + reg = <0xf801c000 0x200>; + clocks = <&flx0_clk>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xf801c000 0x800>; + status = "disabled"; + }; + macb0: ethernet@f802c000 { compatible = "cdns,sam9x60-macb", "cdns,macb"; reg = <0xf802c000 0x100>; @@ -221,6 +231,11 @@ reg = <3>; }; + flx0_clk: flx0_clk { + #clock-cells = <0>; + reg = <5>; + }; + pioD_clk: pioD_clk { #clock-cells = <0>; reg = <44>; diff --git a/arch/arm/dts/sam9x60ek.dts b/arch/arm/dts/sam9x60ek.dts index bed59f3..8767de9 100644 --- a/arch/arm/dts/sam9x60ek.dts +++ b/arch/arm/dts/sam9x60ek.dts @@ -15,6 +15,7 @@ chosen { stdout-path = &dbgu; + i2c0 = &flx0; }; onewire_tm: onewire { @@ -45,6 +46,28 @@ }; }; + flx0: flexcom@f801c600 { + atmel,flexcom-mode = <3>; + status = "okay"; + + i2c@600 { + compatible = "atmel,sama5d2-i2c"; + reg = <0x600 0x200>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flx0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&flx0_clk>; + status = "okay"; + + eeprom@53 { + compatible = "atmel,24c32"; + reg = <0x53>; + pagesize = <16>; + }; + }; + }; + pinctrl { pinctrl_qspi: qspi { atmel,pins = @@ -56,6 +79,12 @@ AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; }; + pinctrl_flx0: flx0_default { + atmel,pins = + <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE + AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE>; + }; + pinctrl_onewire_tm_default: onewire_tm_default { atmel,pins = <AT91_PIOD 14 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; diff --git a/arch/arm/dts/sun50i-a64-olinuxino-emmc.dts b/arch/arm/dts/sun50i-a64-olinuxino-emmc.dts new file mode 100644 index 0000000..96ab022 --- /dev/null +++ b/arch/arm/dts/sun50i-a64-olinuxino-emmc.dts @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2018 Martin Ayotte <martinayotte@gmail.com> + * Copyright (C) 2019 Sunil Mohan Adapa <sunil@medhas.org> + */ + +#include "sun50i-a64-olinuxino.dts" + +/ { + model = "Olimex A64-Olinuxino-eMMC"; + compatible = "olimex,a64-olinuxino-emmc", "allwinner,sun50i-a64"; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins>; + vmmc-supply = <®_dcdc1>; + vqmmc-supply = <®_dcdc1>; + bus-width = <8>; + non-removable; + cap-mmc-hw-reset; + status = "okay"; +}; diff --git a/arch/arm/dts/sun50i-a64-sopine-baseboard-u-boot.dtsi b/arch/arm/dts/sun50i-a64-sopine-baseboard-u-boot.dtsi new file mode 100644 index 0000000..02b1ae0 --- /dev/null +++ b/arch/arm/dts/sun50i-a64-sopine-baseboard-u-boot.dtsi @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Jagan Teki <jagan@amarulasolutions.com> + */ + +#include "sunxi-u-boot.dtsi" + +/ { + aliases { + spi0 = &spi0; + }; +}; diff --git a/arch/arm/dts/sun50i-h6-beelink-gs1.dts b/arch/arm/dts/sun50i-h6-beelink-gs1.dts index 54b0882..0dc33c9 100644 --- a/arch/arm/dts/sun50i-h6-beelink-gs1.dts +++ b/arch/arm/dts/sun50i-h6-beelink-gs1.dts @@ -14,6 +14,7 @@ compatible = "azw,beelink-gs1", "allwinner,sun50i-h6"; aliases { + ethernet0 = &emac; serial0 = &uart0; }; @@ -21,6 +22,17 @@ stdout-path = "serial0:115200n8"; }; + connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + leds { compatible = "gpio-leds"; @@ -41,6 +53,40 @@ }; }; +&de { + status = "okay"; +}; + +&ehci0 { + status = "okay"; +}; + +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&ext_rgmii_pins>; + phy-mode = "rgmii"; + phy-handle = <&ext_rgmii_phy>; + phy-supply = <®_aldo2>; + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&mdio { + ext_rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; +}; + &mmc0 { vmmc-supply = <®_cldo1>; cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; @@ -57,6 +103,15 @@ status = "okay"; }; +&ohci0 { + status = "okay"; +}; + +&pio { + vcc-pd-supply = <®_cldo1>; + vcc-pg-supply = <®_aldo1>; +}; + &r_i2c { status = "okay"; @@ -177,8 +232,29 @@ }; }; +&r_pio { + /* + * PL0 and PL1 are used for PMIC I2C + * don't enable the pl-supply else + * it will fail at boot + * + * vcc-pl-supply = <®_aldo1>; + */ + vcc-pm-supply = <®_aldo1>; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_ph_pins>; status = "okay"; }; + +&usb2otg { + dr_mode = "host"; + status = "okay"; +}; + +&usb2phy { + usb0_vbus-supply = <®_vcc5v>; + status = "okay"; +}; diff --git a/arch/arm/dts/sun50i-h6-pine-h64.dts b/arch/arm/dts/sun50i-h6-pine-h64.dts index 4802902..1898345 100644 --- a/arch/arm/dts/sun50i-h6-pine-h64.dts +++ b/arch/arm/dts/sun50i-h6-pine-h64.dts @@ -127,6 +127,12 @@ status = "okay"; }; +&pio { + vcc-pc-supply = <®_bldo2>; + vcc-pd-supply = <®_cldo1>; + vcc-pg-supply = <®_aldo1>; +}; + &r_i2c { status = "okay"; @@ -243,10 +249,16 @@ pcf8563: rtc@51 { compatible = "nxp,pcf8563"; reg = <0x51>; + interrupt-parent = <&r_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; #clock-cells = <0>; }; }; +&r_pio { + vcc-pm-supply = <®_aldo1>; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_ph_pins>; diff --git a/arch/arm/dts/sun50i-h6.dtsi b/arch/arm/dts/sun50i-h6.dtsi index e0dc4a0..a117f47 100644 --- a/arch/arm/dts/sun50i-h6.dtsi +++ b/arch/arm/dts/sun50i-h6.dtsi @@ -101,7 +101,7 @@ #size-cells = <1>; ranges; - display-engine@1000000 { + bus@1000000 { compatible = "allwinner,sun50i-h6-de3", "allwinner,sun50i-a64-de2"; reg = <0x1000000 0x400000>; @@ -203,11 +203,32 @@ #reset-cells = <1>; }; + dma: dma-controller@3002000 { + compatible = "allwinner,sun50i-h6-dma"; + reg = <0x03002000 0x1000>; + interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>; + clock-names = "bus", "mbus"; + dma-channels = <16>; + dma-requests = <46>; + resets = <&ccu RST_BUS_DMA>; + #dma-cells = <1>; + }; + sid: sid@3006000 { compatible = "allwinner,sun50i-h6-sid"; reg = <0x03006000 0x400>; }; + watchdog: watchdog@30090a0 { + compatible = "allwinner,sun50i-h6-wdt", + "allwinner,sun6i-a31-wdt"; + reg = <0x030090a0 0x20>; + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; + /* Broken on some H6 boards */ + status = "disabled"; + }; + pio: pinctrl@300b000 { compatible = "allwinner,sun50i-h6-pinctrl"; reg = <0x0300b000 0x400>; @@ -243,6 +264,18 @@ bias-pull-up; }; + /* + * /omit-if-no-ref/ isn't supported by U-boot + * keep this comment to avoid bad sync with Linux + */ + mmc1_pins: mmc1-pins { + pins = "PG0", "PG1", "PG2", "PG3", + "PG4", "PG5"; + function = "mmc1"; + drive-strength = <30>; + bias-pull-up; + }; + mmc2_pins: mmc2-pins { pins = "PC1", "PC4", "PC5", "PC6", "PC7", "PC8", "PC9", "PC10", @@ -294,6 +327,8 @@ resets = <&ccu RST_BUS_MMC1>; reset-names = "ahb"; interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -445,7 +480,6 @@ resets = <&ccu RST_BUS_OHCI3>, <&ccu RST_BUS_EHCI3>; phys = <&usb2phy 3>; - phy-names = "usb"; status = "disabled"; }; @@ -457,7 +491,6 @@ <&ccu CLK_USB_OHCI3>; resets = <&ccu RST_BUS_OHCI3>; phys = <&usb2phy 3>; - phy-names = "usb"; status = "disabled"; }; @@ -613,6 +646,13 @@ #reset-cells = <1>; }; + r_watchdog: watchdog@7020400 { + compatible = "allwinner,sun50i-h6-wdt", + "allwinner,sun6i-a31-wdt"; + reg = <0x07020400 0x20>; + interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; + }; + r_intc: interrupt-controller@7021000 { compatible = "allwinner,sun50i-h6-r-intc", "allwinner,sun6i-a31-r-intc"; diff --git a/arch/arm/dts/versal-mini-emmc1.dts b/arch/arm/dts/versal-mini-emmc1.dts index 9ecb1ce..4e0758f 100644 --- a/arch/arm/dts/versal-mini-emmc1.dts +++ b/arch/arm/dts/versal-mini-emmc1.dts @@ -35,7 +35,7 @@ #size-cells = <0x2>; ranges; - sdhci1: sdhci@f105000 { + sdhci1: sdhci@f1050000 { compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a"; status = "okay"; reg = <0x0 0xf1050000 0x0 0x10000>; diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi index e1b0816..07dfa0d 100644 --- a/arch/arm/dts/zynq-7000.dtsi +++ b/arch/arm/dts/zynq-7000.dtsi @@ -213,6 +213,33 @@ #size-cells = <0>; }; + smcc: memory-controller@e000e000 { + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + clock-names = "memclk", "apb_pclk"; + clocks = <&clkc 11>, <&clkc 44>; + compatible = "arm,pl353-smc-r2p1", "arm,primecell"; + interrupt-parent = <&intc>; + interrupts = <0 18 4>; + ranges ; + reg = <0xe000e000 0x1000>; + nand0: flash@e1000000 { + status = "disabled"; + compatible = "arm,pl353-nand-r2p1"; + reg = <0xe1000000 0x1000000>; + #address-cells = <1>; + #size-cells = <1>; + }; + nor0: flash@e2000000 { + status = "disabled"; + compatible = "cfi-flash"; + reg = <0xe2000000 0x2000000>; + #address-cells = <1>; + #size-cells = <1>; + }; + }; + gem0: ethernet@e000b000 { compatible = "cdns,zynq-gem", "cdns,gem"; reg = <0xe000b000 0x1000>; diff --git a/arch/arm/dts/zynqmp-clk-ccf.dtsi b/arch/arm/dts/zynqmp-clk-ccf.dtsi index 247a35f..998298c 100644 --- a/arch/arm/dts/zynqmp-clk-ccf.dtsi +++ b/arch/arm/dts/zynqmp-clk-ccf.dtsi @@ -7,29 +7,30 @@ * Michal Simek <michal.simek@xilinx.com> */ +#include <dt-bindings/clock/xlnx-zynqmp-clk.h> / { fclk0: fclk0 { - status = "disabled"; + status = "okay"; compatible = "xlnx,fclk"; - clocks = <&clkc 71>; + clocks = <&zynqmp_clk PL0_REF>; }; fclk1: fclk1 { - status = "disabled"; + status = "okay"; compatible = "xlnx,fclk"; - clocks = <&clkc 72>; + clocks = <&zynqmp_clk PL1_REF>; }; fclk2: fclk2 { - status = "disabled"; + status = "okay"; compatible = "xlnx,fclk"; - clocks = <&clkc 73>; + clocks = <&zynqmp_clk PL2_REF>; }; fclk3: fclk3 { - status = "disabled"; + status = "okay"; compatible = "xlnx,fclk"; - clocks = <&clkc 74>; + clocks = <&zynqmp_clk PL3_REF>; }; pss_ref_clk: pss_ref_clk { @@ -67,35 +68,6 @@ clock-frequency = <27000000>; }; - clkc: clkc { - u-boot,dm-pre-reloc; - #clock-cells = <1>; - compatible = "xlnx,zynqmp-clkc"; - clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>, <&aux_ref_clk>, <>_crx_ref_clk>; - clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk", "aux_ref_clk", "gt_crx_ref_clk"; - clock-output-names = "iopll", "rpll", "apll", "dpll", - "vpll", "iopll_to_fpd", "rpll_to_fpd", - "apll_to_lpd", "dpll_to_lpd", "vpll_to_lpd", - "acpu", "acpu_half", "dbf_fpd", "dbf_lpd", - "dbg_trace", "dbg_tstmp", "dp_video_ref", - "dp_audio_ref", "dp_stc_ref", "gdma_ref", - "dpdma_ref", "ddr_ref", "sata_ref", "pcie_ref", - "gpu_ref", "gpu_pp0_ref", "gpu_pp1_ref", - "topsw_main", "topsw_lsbus", "gtgref0_ref", - "lpd_switch", "lpd_lsbus", "usb0_bus_ref", - "usb1_bus_ref", "usb3_dual_ref", "usb0", - "usb1", "cpu_r5", "cpu_r5_core", "csu_spb", - "csu_pll", "pcap", "iou_switch", "gem_tsu_ref", - "gem_tsu", "gem0_ref", "gem1_ref", "gem2_ref", - "gem3_ref", "gem0_tx", "gem1_tx", "gem2_tx", - "gem3_tx", "qspi_ref", "sdio0_ref", "sdio1_ref", - "uart0_ref", "uart1_ref", "spi0_ref", - "spi1_ref", "nand_ref", "i2c0_ref", "i2c1_ref", - "can0_ref", "can1_ref", "can0", "can1", - "dll_ref", "adma_ref", "timestamp_ref", - "ams_ref", "pl0", "pl1", "pl2", "pl3", "wdt"; - }; - dp_aclk: dp_aclk { compatible = "fixed-clock"; #clock-cells = <0>; @@ -104,202 +76,214 @@ }; }; +&zynqmp_firmware { + zynqmp_clk: clock-controller { + u-boot,dm-pre-reloc; + #clock-cells = <1>; + compatible = "xlnx,zynqmp-clk"; + clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>, + <&aux_ref_clk>, <>_crx_ref_clk>; + clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk", + "aux_ref_clk", "gt_crx_ref_clk"; + }; +}; + &can0 { - clocks = <&clkc 63>, <&clkc 31>; + clocks = <&zynqmp_clk CAN0_REF>, <&zynqmp_clk LPD_LSBUS>; }; &can1 { - clocks = <&clkc 64>, <&clkc 31>; + clocks = <&zynqmp_clk CAN1_REF>, <&zynqmp_clk LPD_LSBUS>; }; &cpu0 { - clocks = <&clkc 10>; + clocks = <&zynqmp_clk ACPU>; }; &fpd_dma_chan1 { - clocks = <&clkc 19>, <&clkc 31>; + clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &fpd_dma_chan2 { - clocks = <&clkc 19>, <&clkc 31>; + clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &fpd_dma_chan3 { - clocks = <&clkc 19>, <&clkc 31>; + clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &fpd_dma_chan4 { - clocks = <&clkc 19>, <&clkc 31>; + clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &fpd_dma_chan5 { - clocks = <&clkc 19>, <&clkc 31>; + clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &fpd_dma_chan6 { - clocks = <&clkc 19>, <&clkc 31>; + clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &fpd_dma_chan7 { - clocks = <&clkc 19>, <&clkc 31>; + clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &fpd_dma_chan8 { - clocks = <&clkc 19>, <&clkc 31>; + clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &gpu { - clocks = <&clkc 24>, <&clkc 25>, <&clkc 26>; + clocks = <&zynqmp_clk GPU_REF>, <&zynqmp_clk GPU_PP0_REF>, <&zynqmp_clk GPU_PP1_REF>; }; &lpd_dma_chan1 { - clocks = <&clkc 68>, <&clkc 31>; + clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &lpd_dma_chan2 { - clocks = <&clkc 68>, <&clkc 31>; + clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &lpd_dma_chan3 { - clocks = <&clkc 68>, <&clkc 31>; + clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &lpd_dma_chan4 { - clocks = <&clkc 68>, <&clkc 31>; + clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &lpd_dma_chan5 { - clocks = <&clkc 68>, <&clkc 31>; + clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &lpd_dma_chan6 { - clocks = <&clkc 68>, <&clkc 31>; + clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &lpd_dma_chan7 { - clocks = <&clkc 68>, <&clkc 31>; + clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &lpd_dma_chan8 { - clocks = <&clkc 68>, <&clkc 31>; + clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &nand0 { - clocks = <&clkc 60>, <&clkc 31>; + clocks = <&zynqmp_clk NAND_REF>, <&zynqmp_clk LPD_LSBUS>; }; &gem0 { - clocks = <&clkc 31>, <&clkc 49>, <&clkc 45>, <&clkc 49>, <&clkc 44>; + clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM0_REF>, <&zynqmp_clk GEM0_TX>, + <&zynqmp_clk GEM0_RX>, <&zynqmp_clk GEM_TSU>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; }; &gem1 { - clocks = <&clkc 31>, <&clkc 50>, <&clkc 46>, <&clkc 50>, <&clkc 44>; + clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM1_REF>, <&zynqmp_clk GEM1_TX>, + <&zynqmp_clk GEM1_RX>, <&zynqmp_clk GEM_TSU>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; }; &gem2 { - clocks = <&clkc 31>, <&clkc 51>, <&clkc 47>, <&clkc 51>, <&clkc 44>; + clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM2_REF>, <&zynqmp_clk GEM2_TX>, + <&zynqmp_clk GEM2_RX>, <&zynqmp_clk GEM_TSU>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; }; &gem3 { - clocks = <&clkc 31>, <&clkc 52>, <&clkc 48>, <&clkc 52>, <&clkc 44>; + clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM3_REF>, <&zynqmp_clk GEM3_TX>, + <&zynqmp_clk GEM3_RX>, <&zynqmp_clk GEM_TSU>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; }; &gpio { - clocks = <&clkc 31>; + clocks = <&zynqmp_clk LPD_LSBUS>; }; &i2c0 { - clocks = <&clkc 61>; + clocks = <&zynqmp_clk I2C0_REF>; }; &i2c1 { - clocks = <&clkc 62>; + clocks = <&zynqmp_clk I2C1_REF>; }; &pcie { - clocks = <&clkc 23>; + clocks = <&zynqmp_clk PCIE_REF>; }; &qspi { - clocks = <&clkc 53>, <&clkc 31>; + clocks = <&zynqmp_clk QSPI_REF>, <&zynqmp_clk LPD_LSBUS>; }; &sata { - clocks = <&clkc 22>; + clocks = <&zynqmp_clk SATA_REF>; }; &sdhci0 { - clocks = <&clkc 54>, <&clkc 31>; + clocks = <&zynqmp_clk SDIO0_REF>, <&zynqmp_clk LPD_LSBUS>; }; &sdhci1 { - clocks = <&clkc 55>, <&clkc 31>; + clocks = <&zynqmp_clk SDIO1_REF>, <&zynqmp_clk LPD_LSBUS>; }; &spi0 { - clocks = <&clkc 58>, <&clkc 31>; + clocks = <&zynqmp_clk SPI0_REF>, <&zynqmp_clk LPD_LSBUS>; }; &spi1 { - clocks = <&clkc 59>, <&clkc 31>; + clocks = <&zynqmp_clk SPI1_REF>, <&zynqmp_clk LPD_LSBUS>; }; &ttc0 { - clocks = <&clkc 31>; + clocks = <&zynqmp_clk LPD_LSBUS>; }; &ttc1 { - clocks = <&clkc 31>; + clocks = <&zynqmp_clk LPD_LSBUS>; }; &ttc2 { - clocks = <&clkc 31>; + clocks = <&zynqmp_clk LPD_LSBUS>; }; &ttc3 { - clocks = <&clkc 31>; + clocks = <&zynqmp_clk LPD_LSBUS>; }; &uart0 { - clocks = <&clkc 56>, <&clkc 31>; + clocks = <&zynqmp_clk UART0_REF>, <&zynqmp_clk LPD_LSBUS>; }; &uart1 { - clocks = <&clkc 57>, <&clkc 31>; + clocks = <&zynqmp_clk UART1_REF>, <&zynqmp_clk LPD_LSBUS>; }; &usb0 { - clocks = <&clkc 32>, <&clkc 34>; + clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>; }; &usb1 { - clocks = <&clkc 33>, <&clkc 34>; + clocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>; }; &watchdog0 { - clocks = <&clkc 75>; -}; - -&xilinx_ams { - clocks = <&clkc 70>; + clocks = <&zynqmp_clk WDT>; }; -&xilinx_drm { - clocks = <&clkc 16>; +&lpd_watchdog { + clocks = <&zynqmp_clk LPD_WDT>; }; -&xlnx_dp { - clocks = <&dp_aclk>, <&clkc 17>; +&xilinx_ams { + clocks = <&zynqmp_clk AMS_REF>; }; &xlnx_dpdma { - clocks = <&clkc 20>; + clocks = <&zynqmp_clk DPDMA_REF>; }; &xlnx_dp_snd_codec0 { - clocks = <&clkc 17>; + clocks = <&zynqmp_clk DP_AUDIO_REF>; }; diff --git a/arch/arm/dts/zynqmp-clk.dtsi b/arch/arm/dts/zynqmp-clk.dtsi index c70f85a..9ef55ad 100644 --- a/arch/arm/dts/zynqmp-clk.dtsi +++ b/arch/arm/dts/zynqmp-clk.dtsi @@ -223,6 +223,10 @@ clocks = <&clk100>; }; +&lpd_watchdog { + clocks = <&clk250>; +}; + &xilinx_drm { clocks = <&drm_clock>; }; diff --git a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts new file mode 100644 index 0000000..39b5d7f --- /dev/null +++ b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts @@ -0,0 +1,559 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for Xilinx Versal a2197 RevA System Controller + * + * (C) Copyright 2019, Xilinx, Inc. + * + * Michal Simek <michal.simek@xilinx.com> + */ +/dts-v1/; + +#include "zynqmp.dtsi" +#include "zynqmp-clk-ccf.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/phy/phy.h> + +/ { + model = "Versal System Controller on a2197 Eval board RevA"; /* VCK190/VMK180 */ + compatible = "xlnx,zynqmp-e-a2197-00-revA", "xlnx,zynqmp-a2197-revA", + "xlnx,zynqmp-a2197", "xlnx,zynqmp"; + + aliases { + ethernet0 = &gem0; + gpio0 = &gpio; + i2c0 = &i2c0; + i2c1 = &i2c1; + mmc0 = &sdhci1; + rtc0 = &rtc; + serial0 = &uart0; + serial1 = &dcc; + }; + + chosen { + bootargs = "earlycon"; + stdout-path = "serial0:115200n8"; + xlnx,eeprom = <&eeprom>; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; + + ina226-vccint { + compatible = "iio-hwmon"; + io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>; + }; + ina226-vcc-soc { + compatible = "iio-hwmon"; + io-channels = <&vcc_soc 0>, <&vcc_soc 1>, <&vcc_soc 2>, <&vcc_soc 3>; + }; + ina226-vcc-pmc { + compatible = "iio-hwmon"; + io-channels = <&vcc_pmc 0>, <&vcc_pmc 1>, <&vcc_pmc 2>, <&vcc_pmc 3>; + }; + ina226-vcc-ram { + compatible = "iio-hwmon"; + io-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>; + }; + ina226-vcc-pslp { + compatible = "iio-hwmon"; + io-channels = <&vcc_pslp 0>, <&vcc_pslp 1>, <&vcc_pslp 2>, <&vcc_pslp 3>; + }; + ina226-vcc-psfp { + compatible = "iio-hwmon"; + io-channels = <&vcc_psfp 0>, <&vcc_psfp 1>, <&vcc_psfp 2>, <&vcc_psfp 3>; + }; + ina226-vccaux { + compatible = "iio-hwmon"; + io-channels = <&vccaux 0>, <&vccaux 1>, <&vccaux 2>, <&vccaux 3>; + }; + ina226-vccaux-pmc { + compatible = "iio-hwmon"; + io-channels = <&vccaux_pmc 0>, <&vccaux_pmc 1>, <&vccaux_pmc 2>, <&vccaux_pmc 3>; + }; + ina226-vcco-500 { + compatible = "iio-hwmon"; + io-channels = <&vcco_500 0>, <&vcco_500 1>, <&vcco_500 2>, <&vcco_500 3>; + }; + ina226-vcco-501 { + compatible = "iio-hwmon"; + io-channels = <&vcco_501 0>, <&vcco_501 1>, <&vcco_501 2>, <&vcco_501 3>; + }; + ina226-vcco-502 { + compatible = "iio-hwmon"; + io-channels = <&vcco_502 0>, <&vcco_502 1>, <&vcco_502 2>, <&vcco_502 3>; + }; + ina226-vcco-503 { + compatible = "iio-hwmon"; + io-channels = <&vcco_503 0>, <&vcco_503 1>, <&vcco_503 2>, <&vcco_503 3>; + }; + ina226-vcc-1v8 { + compatible = "iio-hwmon"; + io-channels = <&vcc_1v8 0>, <&vcc_1v8 1>, <&vcc_1v8 2>, <&vcc_1v8 3>; + }; + ina226-vcc-3v3 { + compatible = "iio-hwmon"; + io-channels = <&vcc_3v3 0>, <&vcc_3v3 1>, <&vcc_3v3 2>, <&vcc_3v3 3>; + }; + ina226-vcc-1v2-ddr4 { + compatible = "iio-hwmon"; + io-channels = <&vcc_1v2_ddr4 0>, <&vcc_1v2_ddr4 1>, <&vcc_1v2_ddr4 2>, <&vcc_1v2_ddr4 3>; + }; + ina226-vcc-1v1-lp4 { + compatible = "iio-hwmon"; + io-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>; + }; + ina226-vadj-fmc { + compatible = "iio-hwmon"; + io-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>; + }; + ina226-mgtyavcc { + compatible = "iio-hwmon"; + io-channels = <&mgtyavcc 0>, <&mgtyavcc 1>, <&mgtyavcc 2>, <&mgtyavcc 3>; + }; + ina226-mgtyavtt { + compatible = "iio-hwmon"; + io-channels = <&mgtyavtt 0>, <&mgtyavtt 1>, <&mgtyavtt 2>, <&mgtyavtt 3>; + }; + ina226-mgtyvccaux { + compatible = "iio-hwmon"; + io-channels = <&mgtyvccaux 0>, <&mgtyvccaux 1>, <&mgtyvccaux 2>, <&mgtyvccaux 3>; + }; +}; + +&uart0 { /* uart0 MIO38-39 */ + status = "okay"; + u-boot,dm-pre-reloc; +}; + +&sdhci1 { /* sd1 MIO45-51 cd in place */ + status = "okay"; + no-1-8-v; + disable-wp; + xlnx,mio_bank = <1>; +}; + +&gem0 { + status = "okay"; + phy-handle = <&phy0>; + phy-mode = "sgmii"; + is-internal-pcspma; + phy0: ethernet-phy@0 { /* u131 M88E1512 */ + reg = <0>; + }; +}; + +&gpio { + status = "okay"; + gpio-line-names = "", "", "", "", "", /* 0 - 4 */ + "", "", "DC_SYS_CTRL0", "DC_SYS_CTRL1", "DC_SYS_CTRL2", /* 5 - 9 */ + "DC_SYS_CTRL3", "ZU4_TRIGGER", "SYSCTLR_PB", "", "", /* 10 - 14 */ + "", "", "", "", "", /* 15 - 19 */ + "", "", "", "", "", /* 20 - 24 */ + "", "", "", "", "", /* 25 - 29 */ + "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ + "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ + "", "", "ETH_RESET_B", "", "", /* 40 - 44 */ + "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ + "SD1_CMD", "SD1_CLK", "", "", "", /* 50 - 54 */ + "", "", "", "", "", /* 55 - 59 */ + "", "", "", "", "", /* 60 - 64 */ + "", "", "", "", "", /* 65 - 69 */ + "", "", "", "", "", /* 70 - 74 */ + "", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ + "", "", /* 78 - 79 */ + "", "", "", "", "", /* 80 - 84 */ + "", "", "", "", "", /* 85 -89 */ + "", "", "", "", "", /* 90 - 94 */ + "", "", "", "", "", /* 95 - 99 */ + "", "", "", "", "", /* 100 - 104 */ + "", "", "", "", "", /* 105 - 109 */ + "", "", "", "", "", /* 110 - 114 */ + "", "", "", "", "", /* 115 - 119 */ + "", "", "", "", "", /* 120 - 124 */ + "", "", "", "", "", /* 125 - 129 */ + "", "", "", "", "", /* 130 - 134 */ + "", "", "", "", "", /* 135 - 139 */ + "", "", "", "", "", /* 140 - 144 */ + "", "", "", "", "", /* 145 - 149 */ + "", "", "", "", "", /* 150 - 154 */ + "", "", "", "", "", /* 155 - 159 */ + "", "", "", "", "", /* 160 - 164 */ + "", "", "", "", "", /* 165 - 169 */ + "", "", "", ""; /* 170 - 174 */ +}; + +&i2c0 { /* MIO 34-35 - can't stay here */ + status = "okay"; + clock-frequency = <400000>; + i2c-mux@74 { /* u33 */ + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x74>; + /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ + i2c@0 { /* PMBUS */ + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + /* u152 IR35215 0x16/0x46 vcc_soc */ + /* u160 IRPS5401 0x17/0x47 */ + /* u167 IRPS5401 0x1c/0x4c */ + /* u175 IRPS5401 0x1d/0x4d */ + /* u179 ir38164 0x19/0x49 vcco_500 */ + /* u181 ir38164 0x1a/0x4a vcco_501 */ + /* u183 ir38164 0x1b/0x4b vcco_502 */ + /* u185 ir38164 0x1e/0x4e vadj_fmc */ + /* u187 ir38164 0x1F/0x4f mgtyavcc */ + /* u189 ir38164 0x20/0x50 mgtyavtt */ + /* u194 ir38164 0x13/0x43 vdd1_1v8_lp4 */ + /* u195 ir38164 0x14/0x44 vdd2_1v8_lp4 */ + }; + i2c@1 { /* PMBUS1_INA226 */ + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + /* FIXME check alerts coming to SC */ + vccint: ina226@40 { /* u65 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-vccint"; + reg = <0x40>; + shunt-resistor = <5000>; /* R440 */ + /* 0.78V @ 32A 1 of 6 Phases*/ + }; + vcc_soc: ina226@41 { /* u161 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-vcc-soc"; + reg = <0x41>; + shunt-resistor = <2000>; /* R1186 */ + /* 0.78V @ 18A */ + }; + vcc_pmc: ina226@42 { /* u163 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-vcc-pmc"; + reg = <0x42>; + shunt-resistor = <5000>; /* R1214 */ + /* 0.78V @ 500mA */ + }; + vcc_ram: ina226@43 { /* u162 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-vcc-ram"; + reg = <0x43>; + shunt-resistor = <5000>; /* r1221 */ + /* 0.78V @ 4A */ + }; + vcc_pslp: ina226@44 { /* u165 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-vcc-pslp"; + reg = <0x44>; + shunt-resistor = <5000>; /* R1216 */ + /* 0.78V @ 1A */ + }; + vcc_psfp: ina226@45 { /* u164 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-vcc-psfp"; + reg = <0x45>; + shunt-resistor = <5000>; /* R1219 */ + /* 0.78V @ 2A */ + }; + }; + i2c@2 { /* PCIE_CLK */ + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + clock_8t49n287: clock-generator@d8 { /* u39 8T49N240 */ + #clock-cells = <1>; /* author David Cater <david.cater@idt.com>*/ + compatible = "idt,8t49n240", "idt,8t49n241"; /* FIXME no driver for 240 */ + reg = <0xd8>; + /* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */ + /* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */ + }; + }; + i2c@3 { /* PMBUS2_INA226 */ + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + /* FIXME check alerts coming to SC */ + vccaux: ina226@40 { /* u166 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-vccaux"; + reg = <0x40>; + shunt-resistor = <5000>; /* R382 */ + /* 1.5V @ 3A */ + }; + vccaux_pmc: ina226@41 { /* u168 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-vccaux-pmc"; + reg = <0x41>; + shunt-resistor = <5000>; /* R1246 */ + /* 1.5V @ 500mA */ + }; + vcco_500: ina226@42 { /* u178 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-vcco-500"; + reg = <0x42>; + shunt-resistor = <2000>; /* R1300 */ + /* 3.3V @ 5A */ + }; + vcco_501: ina226@43 { /* u180 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-vcco-501"; + reg = <0x43>; + shunt-resistor = <2000>; /* R1313 */ + /* 3.3V @ 5A */ + }; + vcco_502: ina226@44 { /* u182 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-vcco-502"; + reg = <0x44>; + shunt-resistor = <2000>; /* R1330 */ + /* 3.3V @ 5A */ + }; + vcco_503: ina226@45 { /* u172 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-vcco-503"; + reg = <0x45>; + shunt-resistor = <5000>; /* R1229 */ + /* 1.8V @ 2A */ + }; + vcc_1v8: ina226@46 { /* u173 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-vcc-1v8"; + reg = <0x46>; + shunt-resistor = <5000>; /* R400 */ + /* 1.8V @ 6A */ + }; + vcc_3v3: ina226@47 { /* u174 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-vcc-3v3"; + reg = <0x47>; + shunt-resistor = <5000>; /* R1232 */ + /* 3.3V @ 500mA */ + }; + vcc_1v2_ddr4: ina226@48 { /* u176 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-vcc-1v2-ddr4"; + reg = <0x48>; + shunt-resistor = <5000>; /* R1275 */ + /* 1.2V @ 4A */ + }; + vcc1v1_lp4: ina226@49 { /* u177 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-vcc1v1-lp4"; + reg = <0x49>; + shunt-resistor = <5000>; /* R1286 */ + /* 1.1V @ 4A */ + }; + vadj_fmc: ina226@4a { /* u184 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-vadj-fmc"; + reg = <0x4a>; + shunt-resistor = <2000>; /* R1350 */ + /* 1.5V @ 10A */ + }; + mgtyavcc: ina226@4b { /* u186 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-mgtyavcc"; + reg = <0x4b>; + shunt-resistor = <2000>; /* R1367 */ + /* 0.88V @ 6A */ + }; + mgtyavtt: ina226@4c { /* u188 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-mgtyavtt"; + reg = <0x4c>; + shunt-resistor = <2000>; /* R1384 */ + /* 1.2V @ 10A */ + }; + mgtyvccaux: ina226@4d { /* u234 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-mgtyvccaux"; + reg = <0x4d>; + shunt-resistor = <5000>; /* r1679 */ + /* 1.5V @ 500mA */ + }; + }; + i2c@4 { /* LP_I2C_SM */ + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + /* FIXME wires ready but chip is missing */ + }; + i2c@5 { /* zSFP_SI570 */ + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + si570_zsfp: clock-generator@5d { /* u192 */ + #clock-cells = <0>; + compatible = "silabs,si570"; + reg = <0x5d>; + temperature-stability = <50>; + factory-fout = <156250000>; + clock-frequency = <156250000>; + clock-output-names = "si570_hsdp_clk"; + }; + }; + i2c@6 { /* USER_SI570_1 */ + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + si570_user1_clk: clock-generator@5d { /* u205 */ + #clock-cells = <0>; + compatible = "silabs,si570"; + reg = <0x5f>; + temperature-stability = <50>; + factory-fout = <100000000>; + clock-frequency = <100000000>; + clock-output-names = "si570_user1"; + }; + + }; + i2c@7 { /* USER_SI570_2 */ + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + /* FIXME wires ready but chip is missing */ + }; + }; +}; + +&i2c1 { /* i2c1 MIO 36-37 */ + status = "okay"; + clock-frequency = <400000>; + + i2c-mux@74 { /* u35 */ + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x74>; + /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */ + dc_i2c: i2c@0 { /* DC_I2C */ + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + /* Use for storing information about SC board */ + eeprom: eeprom@54 { /* u34 - m24128 16kB */ + compatible = "st,24c128", "atmel,24c128"; + reg = <0x54>; /* 0x5c too */ + }; + si570_ref_clk: clock-generator@5d { /* u32 */ + #clock-cells = <0>; + compatible = "silabs,si570"; + reg = <0x5d>; + temperature-stability = <50>; + factory-fout = <33333333>; + clock-frequency = <33333333>; + clock-output-names = "ref_clk"; + }; + /* and connector J212D */ + }; + fmc1: i2c@1 { /* FMCP1_IIC */ + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + /* FIXME connection to Samtec J51C */ + /* expected eeprom 0x50 FMC cards */ + }; + fmc2: i2c@2 { /* FMCP2_IIC */ + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + /* FIXME connection to Samtec J53C */ + /* expected eeprom 0x50 FMC cards */ + }; + i2c@3 { /* DDR4_DIMM1 */ + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + si570_ddr_dimm1: clock-generator@60 { /* u2 */ + #clock-cells = <0>; + compatible = "silabs,si570"; + reg = <0x60>; + temperature-stability = <50>; + factory-fout = <200000000>; + clock-frequency = <200000000>; + clock-output-names = "si570_ddrdimm1_clk"; + }; + }; + i2c@4 { /* LPDDR4_SI570_CLK2 */ + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + si570_ddr_dimm2: clock-generator@60 { /* u3 */ + #clock-cells = <0>; + compatible = "silabs,si570"; + reg = <0x60>; + temperature-stability = <50>; + factory-fout = <200000000>; + clock-frequency = <200000000>; + clock-output-names = "si570_lpddr4_clk2"; + }; + }; + i2c@5 { /* LPDDR4_SI570_CLK1 */ + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + si570_lpddr4: clock-generator@60 { /* u4 */ + #clock-cells = <0>; + compatible = "silabs,si570"; + reg = <0x60>; + temperature-stability = <50>; + factory-fout = <200000000>; + clock-frequency = <200000000>; + clock-output-names = "si570_lpddr4_clk1"; + }; + }; + i2c@6 { /* HSDP_SI570 */ + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + si570_hsdp: clock-generator@5d { /* u5 */ + #clock-cells = <0>; + compatible = "silabs,si570"; + reg = <0x5d>; + temperature-stability = <50>; + factory-fout = <156250000>; + clock-frequency = <156250000>; + clock-output-names = "si570_hsdp_clk"; + }; + }; + i2c@7 { /* 8A34001 - U219B and J310 connector */ + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; +}; + +&xilinx_ams { + status = "okay"; +}; + +&ams_ps { + status = "okay"; +}; + +&ams_pl { + status = "okay"; +}; diff --git a/arch/arm/dts/zynqmp-a2197-g-revA.dts b/arch/arm/dts/zynqmp-g-a2197-00-revA.dts index c6072b5..09da60b 100644 --- a/arch/arm/dts/zynqmp-a2197-g-revA.dts +++ b/arch/arm/dts/zynqmp-g-a2197-00-revA.dts @@ -14,7 +14,7 @@ / { model = "Versal System Controller on a2197 MGT Char board RevA"; - compatible = "xlnx,zynqmp-a2197-g-revA", "xlnx,zynqmp-a2197-revA", + compatible = "xlnx,zynqmp-g-a2197-00-revA", "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; aliases { @@ -38,6 +38,31 @@ device_type = "memory"; reg = <0x0 0x0 0x0 0x80000000>; }; + + ina226-u74 { + compatible = "iio-hwmon"; + io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>; + }; + ina226-u75 { + compatible = "iio-hwmon"; + io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>; + }; + ina226-u78 { + compatible = "iio-hwmon"; + io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>; + }; + ina226-u79 { + compatible = "iio-hwmon"; + io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>; + }; + ina226-u82 { + compatible = "iio-hwmon"; + io-channels = <&u82 0>, <&u82 1>, <&u82 2>, <&u82 3>; + }; + ina226-u84 { + compatible = "iio-hwmon"; + io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>; + }; }; &sdhci0 { /* emmc MIO 13-23 16GB */ @@ -58,7 +83,7 @@ phy-handle = <&phy0>; phy-mode = "sgmii"; is-internal-pcspma; - phy0: phy@0 { /* marwell m88e1512 */ + phy0: ethernet-phy@0 { /* marwell m88e1512 */ reg = <0>; reset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>; /* xlnx,phy-type = <PHY_TYPE_SGMII>; */ @@ -198,38 +223,50 @@ compatible = "ti,tps544b25"; reg = <0x20>; }; - ina226@40 { /* u74 */ + u74: ina226@40 { /* u74 */ compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-u74"; reg = <0x40>; shunt-resistor = <1000>; }; - ina226@41 { /* u75 */ + u75: ina226@41 { /* u75 */ compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-u75"; reg = <0x41>; shunt-resistor = <1000>; }; - ina226@42 { /* u78 */ + u78: ina226@42 { /* u78 */ compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-u78"; reg = <0x42>; shunt-resistor = <5000>; }; - ina226@43 { /* u79 */ + u79: ina226@43 { /* u79 */ compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-u79"; reg = <0x43>; shunt-resistor = <1000>; }; - ina226@44 { /* u82 */ + u82: ina226@44 { /* u82 */ compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-u82"; reg = <0x44>; shunt-resistor = <1000>; }; - ina226@45 { /* u84 */ + u84: ina226@45 { /* u84 */ compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-u84"; reg = <0x45>; shunt-resistor = <5000>; }; tps53681@c0 { /* u53 - FIXME name - don't know what it does - also vcc_io_soc */ - compatible = "ti,tps53681"; /* FIXME no linux driver */ + compatible = "ti,tps53681", "ti,tps53679"; reg = <0xc0>; }; }; diff --git a/arch/arm/dts/zynqmp-a2197-m-revA.dts b/arch/arm/dts/zynqmp-m-a2197-01-revA.dts index e4b45ea..e295bac 100644 --- a/arch/arm/dts/zynqmp-a2197-m-revA.dts +++ b/arch/arm/dts/zynqmp-m-a2197-01-revA.dts @@ -14,7 +14,7 @@ / { model = "Versal System Controller on a2197 Memory Char board RevA"; - compatible = "xlnx,zynqmp-a2197-m-revA", "xlnx,zynqmp-a2197-revA", + compatible = "xlnx,zynqmp-m-a2197-01-revA", "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; aliases { @@ -43,13 +43,38 @@ device_type = "memory"; reg = <0x0 0x0 0x0 0x80000000>; /* FIXME don't know how big memory is there */ }; + + ina226-vcc-aux { + compatible = "iio-hwmon"; + io-channels = <&vcc_aux 0>, <&vcc_aux 1>, <&vcc_aux 2>, <&vcc_aux 3>; + }; + ina226-vcc-ram { + compatible = "iio-hwmon"; + io-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>; + }; + ina226-vcc1v1-lp4 { + compatible = "iio-hwmon"; + io-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>; + }; + ina226-vcc1v2-lp4 { + compatible = "iio-hwmon"; + io-channels = <&vcc1v2_lp4 0>, <&vcc1v2_lp4 1>, <&vcc1v2_lp4 2>, <&vcc1v2_lp4 3>; + }; + ina226-vdd1-1v8-lp4 { + compatible = "iio-hwmon"; + io-channels = <&vdd1_1v8_lp4 0>, <&vdd1_1v8_lp4 1>, <&vdd1_1v8_lp4 2>, <&vdd1_1v8_lp4 3>; + }; + ina226-vcc0v6-lp4 { + compatible = "iio-hwmon"; + io-channels = <&vcc0v6_lp4 0>, <&vcc0v6_lp4 1>, <&vcc0v6_lp4 2>, <&vcc0v6_lp4 3>; + }; }; &qspi { status = "okay"; is-dual = <1>; flash@0 { - compatible = "m25p80", "spi-flash"; /* 32MB */ + compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; @@ -89,7 +114,7 @@ phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; - phy0: phy@0 { /* marwell m88e1512 - SGMII */ + phy0: ethernet-phy@0 { /* marwell m88e1512 - SGMII */ reg = <0>; /* xlnx,phy-type = <PHY_TYPE_SGMII>; */ }; @@ -183,31 +208,43 @@ reg = <1>; vcc_aux: ina226@42 { /* u86 */ compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-vcc-aux"; reg = <0x42>; shunt-resistor = <5000>; }; vcc_ram: ina226@43 { /* u81 */ compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-vcc-ram"; reg = <0x43>; shunt-resistor = <5000>; }; vcc1v1_lp4: ina226@46 { /* u96 */ compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-vcc1v1-lp4"; reg = <0x46>; shunt-resistor = <5000>; }; vcc1v2_lp4: ina226@47 { /* u98 */ compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-vcc1v2-lp4"; reg = <0x47>; shunt-resistor = <5000>; }; vdd1_1v8_lp4: ina226@48 { /* u100 */ compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-vdd1-1v8-lp4"; reg = <0x48>; shunt-resistor = <5000>; }; vcc0v6_lp4: ina226@49 { /* u101 */ compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-vcc0v6-lp4"; reg = <0x49>; shunt-resistor = <5000>; }; @@ -217,7 +254,7 @@ #size-cells = <0>; reg = <2>; reg_vccint: tps53681@c0 { /* u69 */ - compatible = "ti,tps53681"; /* FIXME no linux driver */ + compatible = "ti,tps53681", "ti,tps53679"; reg = <0xc0>; }; reg_vcc_pmc: tps544@7 { /* u80 */ @@ -289,7 +326,7 @@ reg = <0x51>; }; - i2c-mux@74 { /* u35 */ + i2c-mux@74 { /* u47 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; @@ -354,19 +391,14 @@ }; }; }; - i2c@1 { /* UTIL_PMBUS - FIXME incorrect schematics */ - #address-cells = <1>; - #size-cells = <0>; - /* reg = <1>; */ - }; i2c@2 { /* C0_LP4 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; - si570_c0_lp4: clock-generator@5d { /* u10 */ + si570_c0_lp4: clock-generator@55 { /* u10 */ #clock-cells = <0>; compatible = "silabs,si570"; - reg = <0x5d>; /* FIXME addr */ + reg = <0x55>; temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; @@ -391,10 +423,10 @@ #address-cells = <1>; #size-cells = <0>; reg = <4>; - si570_c2_lp4: clock-generator@5d { /* u10 */ + si570_c2_lp4: clock-generator@55 { /* u10 */ #clock-cells = <0>; compatible = "silabs,si570"; - reg = <0x5d>; /* FIXME addr */ + reg = <0x55>; temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; @@ -405,10 +437,10 @@ #address-cells = <1>; #size-cells = <0>; reg = <5>; - si570_c3_lp4: clock-generator@5d { /* u15 */ + si570_c3_lp4: clock-generator@55 { /* u15 */ #clock-cells = <0>; compatible = "silabs,si570"; - reg = <0x5d>; /* FIXME addr */ + reg = <0x55>; temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; @@ -424,8 +456,8 @@ compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; - factory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */ - clock-frequency = <33333333>; + factory-fout = <156250000>; + clock-frequency = <156250000>; clock-output-names = "HSDP_SI570"; }; }; diff --git a/arch/arm/dts/zynqmp-m-a2197-02-revA.dts b/arch/arm/dts/zynqmp-m-a2197-02-revA.dts new file mode 100644 index 0000000..bd2c1a4 --- /dev/null +++ b/arch/arm/dts/zynqmp-m-a2197-02-revA.dts @@ -0,0 +1,496 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for Xilinx Versal a2197 RevA System Controller + * + * (C) Copyright 2019, Xilinx, Inc. + * + * Michal Simek <michal.simek@xilinx.com> + */ +/dts-v1/; + +#include "zynqmp.dtsi" +#include "zynqmp-clk-ccf.dtsi" +#include <dt-bindings/gpio/gpio.h> + +/ { + model = "Versal System Controller on a2197 Memory Char board RevA"; + compatible = "xlnx,zynqmp-m-a2197-02-revA", "xlnx,zynqmp-a2197-revA", + "xlnx,zynqmp-a2197", "xlnx,zynqmp"; + + aliases { + ethernet0 = &gem0; + gpio0 = &gpio; + i2c0 = &i2c0; + i2c1 = &i2c1; + mmc0 = &sdhci0; + mmc1 = &sdhci1; + rtc0 = &rtc; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &dcc; + usb0 = &usb0; + usb1 = &usb1; + spi0 = &qspi; + }; + + chosen { + bootargs = "earlycon"; + stdout-path = "serial0:115200n8"; + xlnx,eeprom = <&eeprom>; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; /* FIXME don't know how big memory is there */ + }; + + ina226-vcc-aux { + compatible = "iio-hwmon"; + io-channels = <&vcc_aux 0>, <&vcc_aux 1>, <&vcc_aux 2>, <&vcc_aux 3>; + }; + ina226-vcc-ram { + compatible = "iio-hwmon"; + io-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>; + }; + ina226-vcc1v1-lp4 { + compatible = "iio-hwmon"; + io-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>; + }; + ina226-vcc1v2-lp4 { + compatible = "iio-hwmon"; + io-channels = <&vcc1v2_lp4 0>, <&vcc1v2_lp4 1>, <&vcc1v2_lp4 2>, <&vcc1v2_lp4 3>; + }; + ina226-vdd1-1v8-lp4 { + compatible = "iio-hwmon"; + io-channels = <&vdd1_1v8_lp4 0>, <&vdd1_1v8_lp4 1>, <&vdd1_1v8_lp4 2>, <&vdd1_1v8_lp4 3>; + }; +}; + +&qspi { + status = "okay"; + is-dual = <1>; + flash@0 { + compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ + #address-cells = <1>; + #size-cells = <1>; + reg = <0x0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + spi-max-frequency = <108000000>; + }; +}; + +&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */ + status = "okay"; + non-removable; + disable-wp; + bus-width = <8>; + xlnx,mio_bank = <0>; /* FIXME tap delay */ +}; + +&uart0 { /* uart0 MIO38-39 */ + status = "okay"; + u-boot,dm-pre-reloc; +}; + +&uart1 { /* uart1 MIO40-41 */ + status = "okay"; + u-boot,dm-pre-reloc; +}; + +&sdhci1 { /* sd1 MIO45-51 cd in place */ + status = "disable"; + no-1-8-v; + disable-wp; + xlnx,mio_bank = <1>; +}; + +&gem0 { + status = "okay"; + phy-handle = <&phy0>; + phy-mode = "sgmii"; + phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; + phy0: ethernet-phy@0 { /* marwell m88e1512 - SGMII */ + reg = <0>; + }; +}; + +&gpio { + status = "okay"; + gpio-line-names = "SCLK_OUT", "MISO_MO1", "MO2", "MO3", "MOSI_MIO0", /* 0 - 4 */ + "N_SS_OUT", "", "SYS_CTRL0", "SYS_CTRL1", "SYS_CTRL2", /* 5 - 9 */ + "SYS_CTRL3", "SYS_CTRL4", "SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ + "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ + "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ + "", "RXD0_IN", "TXD0_OUT", "TXD1_OUT", "RXD1_IN", /* 25 - 29 */ + "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ + "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ + "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */ + "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ + "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ + "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ + "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */ + "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */ + "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */ + "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ + "", "", "", "", "", /* 78 - 79 */ + "", "", "", "", "", /* 80 - 84 */ + "", "", "", "", "", /* 85 -89 */ + "", "", "", "", "", /* 90 - 94 */ + "", "", "", "", "", /* 95 - 99 */ + "", "", "", "", "", /* 100 - 104 */ + "", "", "", "", "", /* 105 - 109 */ + "", "", "", "", "", /* 110 - 114 */ + "", "", "", "", "", /* 115 - 119 */ + "", "", "", "", "", /* 120 - 124 */ + "", "", "", "", "", /* 125 - 129 */ + "", "", "", "", "", /* 130 - 134 */ + "", "", "", "", "", /* 135 - 139 */ + "", "", "", "", "", /* 140 - 144 */ + "", "", "", "", "", /* 145 - 149 */ + "", "", "", "", "", /* 150 - 154 */ + "", "", "", "", "", /* 155 - 159 */ + "", "", "", "", "", /* 160 - 164 */ + "", "", "", "", "", /* 165 - 169 */ + "", "", "", ""; /* 170 - 174 */ +}; + +&i2c0 { /* MIO 34-35 - can't stay here */ + status = "okay"; + clock-frequency = <400000>; + i2c-mux@74 { /* u46 */ + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x74>; + /* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */ + i2c@0 { /* PMBUS must be enabled via SW21 */ + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + reg_vcc1v2_lp4: tps544@15 { /* u97 */ + compatible = "ti,tps544b25"; + reg = <0x15>; + }; + reg_vcc1v1_lp4: tps544@16 { /* u95 */ + compatible = "ti,tps544b25"; + reg = <0x16>; + }; + reg_vdd1_1v8_lp4: tps544@17 { /* u99 */ + compatible = "ti,tps544b25"; + reg = <0x17>; + }; + /* UTIL_PMBUS connection */ + reg_vcc1v8: tps544@13 { /* u92 */ + compatible = "ti,tps544b25"; + reg = <0x13>; + }; + reg_vcc3v3: tps544@14 { /* u93 */ + compatible = "ti,tps544b25"; + reg = <0x14>; + }; + reg_vcc5v0: tps544@1e { /* u94 */ + compatible = "ti,tps544b25"; + reg = <0x1e>; + }; + reg_vpp_2v5_ddr4: tps544@1x { /* u3007 */ + compatible = "ti,tps544b25"; + reg = <0x17>; /* FIXME wrong in schematics */ + }; + }; + i2c@1 { /* PMBUS_INA226 */ + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + vcc_aux: ina226@42 { /* u86 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-vcc-aux"; + reg = <0x42>; + shunt-resistor = <5000>; + }; + vcc_ram: ina226@43 { /* u81 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-vcc-ram"; + reg = <0x43>; + shunt-resistor = <5000>; + }; + vcc1v1_lp4: ina226@46 { /* u96 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-vcc1v1-lp4"; + reg = <0x46>; + shunt-resistor = <5000>; + }; + vcc1v2_lp4: ina226@47 { /* u98 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-vcc1v2-lp4"; + reg = <0x47>; + shunt-resistor = <5000>; + }; + vdd1_1v8_lp4: ina226@48 { /* u100 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-vdd1-1v8-lp4"; + reg = <0x48>; + shunt-resistor = <5000>; + }; + }; + i2c@2 { /* PMBUS1 */ + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + reg_vccint: tps53681@c0 { /* u69 */ + compatible = "ti,tps53681", "ti,tps53679"; + reg = <0xc0>; + }; + reg_vcc_pmc: tps544@7 { /* u80 */ + compatible = "ti,tps544b25"; + reg = <0x7>; + }; + reg_vcc_ram: tps544@8 { /* u82 */ + compatible = "ti,tps544b25"; + reg = <0x8>; + }; + reg_vcc_pslp: tps544@9 { /* u83 */ + compatible = "ti,tps544b25"; + reg = <0x9>; + }; + reg_vcc_psfp: tps544@a { /* u84 */ + compatible = "ti,tps544b25"; + reg = <0xa>; + }; + reg_vccaux: tps544@d { /* u85 */ + compatible = "ti,tps544b25"; + reg = <0xd>; + }; + reg_vccaux_pmc: tps544@e { /* u87 */ + compatible = "ti,tps544b25"; + reg = <0xe>; + }; + reg_vcco_500: tps544@f { /* u88 */ + compatible = "ti,tps544b25"; + reg = <0xf>; + }; + reg_vcco_501: tps544@10 { /* u89 */ + compatible = "ti,tps544b25"; + reg = <0x10>; + }; + reg_vcco_502: tps544@11 { /* u90 */ + compatible = "ti,tps544b25"; + reg = <0x11>; + }; + reg_vcco_503: tps544@12 { /* u91 */ + compatible = "ti,tps544b25"; + reg = <0x12>; + }; + }; + i2c@3 { /* MEM PMBUS - FIXME bug in schematics */ + #address-cells = <1>; + #size-cells = <0>; + /* reg = <3>; */ + }; + i2c@4 { /* LP_I2C_SM */ + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + /* connected to U20G */ + }; + i2c@5 { /* C0_DDR4_RDIMM */ + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + i2c@6 { /* C2_DDR5_RDIMM */ + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + i2c@7 { /* C3_DDR4_UDIMM */ + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; +}; + +/* TODO sysctrl via J239 */ +/* TODO samtec J212G/H via J242 */ +/* TODO teensy via U30 PCA9543A bus 1 */ +&i2c1 { /* i2c1 MIO 36-37 */ + status = "okay"; + clock-frequency = <400000>; + + /* Must be enabled via J242 */ + eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */ + compatible = "atmel,24c02"; + reg = <0x51>; + }; + + i2c-mux@74 { /* u47 */ + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x74>; + /* FIXME reset connected to SYSCTRL_IIC_MUX1_RESET */ + dc_i2c: i2c@0 { /* DC_I2C */ + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + /* Use for storing information about SC board */ + eeprom: eeprom@54 { /* u51 - m24128 16kB FIXME addr */ + compatible = "atmel,24c08"; + reg = <0x54>; + }; + si570_ref_clk: clock-generator@5d { /* u26 */ + #clock-cells = <0>; + compatible = "silabs,si570"; + reg = <0x5d>; /* FIXME addr */ + temperature-stability = <50>; + factory-fout = <156250000>; /* FIXME every chip can be different */ + clock-frequency = <33333333>; + clock-output-names = "REF_CLK"; /* FIXME */ + }; + /* Connection via Samtec U20D */ + /* Use for storing information about X-PRC card */ + x_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */ + compatible = "atmel,24c02"; + reg = <0x52>; + }; + + /* Use for setting up certain features on X-PRC card */ + x_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */ + compatible = "nxp,pca9534"; + reg = <0x22>; + gpio-controller; /* IRQ not connected */ + #gpio-cells = <2>; + gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", + "", "", "", ""; + gtr_sel0 { + gpio-hog; + gpios = <0 0>; + input; /* FIXME add meaning */ + line-name = "sw4_1"; + }; + gtr_sel1 { + gpio-hog; + gpios = <1 0>; + input; /* FIXME add meaning */ + line-name = "sw4_2"; + }; + gtr_sel2 { + gpio-hog; + gpios = <2 0>; + input; /* FIXME add meaning */ + line-name = "sw4_3"; + }; + gtr_sel3 { + gpio-hog; + gpios = <3 0>; + input; /* FIXME add meaning */ + line-name = "sw4_4"; + }; + }; + }; + i2c@2 { /* C0_DDR4 */ + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + si570_c0_ddr4: clock-generator@55 { /* u4 */ + #clock-cells = <0>; + compatible = "silabs,si570"; + reg = <0x55>; + temperature-stability = <50>; + factory-fout = <30000000>; + clock-frequency = <30000000>; + clock-output-names = "C0_DD4_SI570_CLK"; + }; + }; + i2c@3 { /* C1_RLD3 */ + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + si570_c1_lp4: clock-generator@55 { /* u7 */ + #clock-cells = <0>; + compatible = "silabs,si570"; + reg = <0x55>; + temperature-stability = <50>; + factory-fout = <30000000>; + clock-frequency = <30000000>; + clock-output-names = "C1_RLD3_SI570_CLK"; + }; + }; + i2c@4 { /* C2_DDR5 */ + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + si570_c2_lp4: clock-generator@55 { /* u10 */ + #clock-cells = <0>; + compatible = "silabs,si570"; + reg = <0x55>; + temperature-stability = <50>; + factory-fout = <30000000>; + clock-frequency = <30000000>; + clock-output-names = "C2_DDR5_SI570_CLK"; + }; + }; + i2c@5 { /* C3_DDR4 */ + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + si570_c3_lp4: clock-generator@55 { /* u15 */ + #clock-cells = <0>; + compatible = "silabs,si570"; + reg = <0x55>; + temperature-stability = <50>; + factory-fout = <30000000>; + clock-frequency = <30000000>; + clock-output-names = "C3_LP4_SI570_CLK"; + }; + }; + i2c@6 { /* HSDP_SI570 */ + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + si570_hsdp: clock-generator@5d { /* u19 */ + #clock-cells = <0>; + compatible = "silabs,si570"; + reg = <0x5d>; + temperature-stability = <50>; + factory-fout = <156250000>; + clock-frequency = <156250000>; + clock-output-names = "HSDP_SI570"; + }; + }; + }; +}; + +&usb0 { + status = "okay"; + xlnx,usb-polarity = <0>; + xlnx,usb-reset-mode = <0>; +}; + +&dwc3_0 { + status = "okay"; + dr_mode = "host"; + /* dr_mode = "peripheral"; */ + maximum-speed = "high-speed"; +}; + +&usb1 { + status = "disabled"; /* not at mem board */ + xlnx,usb-polarity = <0>; + xlnx,usb-reset-mode = <0>; +}; + +&dwc3_1 { + /delete-property/ phy-names ; + /delete-property/ phys ; + maximum-speed = "high-speed"; + snps,dis_u2_susphy_quirk ; + snps,dis_u3_susphy_quirk ; + status = "disabled"; +}; diff --git a/arch/arm/dts/zynqmp-m-a2197-03-revA.dts b/arch/arm/dts/zynqmp-m-a2197-03-revA.dts new file mode 100644 index 0000000..700197c --- /dev/null +++ b/arch/arm/dts/zynqmp-m-a2197-03-revA.dts @@ -0,0 +1,486 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for Xilinx Versal a2197 RevA System Controller + * + * (C) Copyright 2019, Xilinx, Inc. + * + * Michal Simek <michal.simek@xilinx.com> + */ +/dts-v1/; + +#include "zynqmp.dtsi" +#include "zynqmp-clk-ccf.dtsi" +#include <dt-bindings/gpio/gpio.h> + +/ { + model = "Versal System Controller on a2197 Memory Char board RevA"; + compatible = "xlnx,zynqmp-m-a2197-03-revA", "xlnx,zynqmp-a2197-revA", + "xlnx,zynqmp-a2197", "xlnx,zynqmp"; + + aliases { + ethernet0 = &gem0; + gpio0 = &gpio; + i2c0 = &i2c0; + i2c1 = &i2c1; + mmc0 = &sdhci0; + mmc1 = &sdhci1; + rtc0 = &rtc; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &dcc; + usb0 = &usb0; + usb1 = &usb1; + spi0 = &qspi; + }; + + chosen { + bootargs = "earlycon"; + stdout-path = "serial0:115200n8"; + xlnx,eeprom = <&eeprom>; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; /* FIXME don't know how big memory is there */ + }; + + ina226-vcc-aux { + compatible = "iio-hwmon"; + io-channels = <&vcc_aux 0>, <&vcc_aux 1>, <&vcc_aux 2>, <&vcc_aux 3>; + }; + ina226-vcc-ram { + compatible = "iio-hwmon"; + io-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>; + }; + ina226-vcc1v1-lp4 { + compatible = "iio-hwmon"; + io-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>; + }; + ina226-vcc1v2-lp4 { + compatible = "iio-hwmon"; + io-channels = <&vcc1v2_lp4 0>, <&vcc1v2_lp4 1>, <&vcc1v2_lp4 2>, <&vcc1v2_lp4 3>; + }; + ina226-vdd1-1v8-lp4 { + compatible = "iio-hwmon"; + io-channels = <&vdd1_1v8_lp4 0>, <&vdd1_1v8_lp4 1>, <&vdd1_1v8_lp4 2>, <&vdd1_1v8_lp4 3>; + }; +}; + +&qspi { + status = "okay"; + is-dual = <1>; + flash@0 { + compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ + #address-cells = <1>; + #size-cells = <1>; + reg = <0x0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + spi-max-frequency = <108000000>; + }; +}; + +&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */ + status = "okay"; + non-removable; + disable-wp; + bus-width = <8>; + xlnx,mio_bank = <0>; /* FIXME tap delay */ +}; + +&uart0 { /* uart0 MIO38-39 */ + status = "okay"; + u-boot,dm-pre-reloc; +}; + +&uart1 { /* uart1 MIO40-41 */ + status = "okay"; + u-boot,dm-pre-reloc; +}; + +&sdhci1 { /* sd1 MIO45-51 cd in place */ + status = "disable"; + no-1-8-v; + disable-wp; + xlnx,mio_bank = <1>; +}; + +&gem0 { + status = "okay"; + phy-handle = <&phy0>; + phy-mode = "sgmii"; + phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; + phy0: ethernet-phy@0 { /* marwell m88e1512 - SGMII */ + reg = <0>; + }; +}; + +&gpio { + status = "okay"; + gpio-line-names = "SCLK_OUT", "MISO_MO1", "MO2", "MO3", "MOSI_MIO0", /* 0 - 4 */ + "N_SS_OUT", "", "SYS_CTRL0", "SYS_CTRL1", "SYS_CTRL2", /* 5 - 9 */ + "SYS_CTRL3", "SYS_CTRL4", "SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ + "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ + "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ + "", "RXD0_IN", "TXD0_OUT", "TXD1_OUT", "RXD1_IN", /* 25 - 29 */ + "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ + "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ + "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */ + "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ + "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ + "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ + "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */ + "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */ + "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */ + "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ + "", "", "", "", "", /* 78 - 79 */ + "", "", "", "", "", /* 80 - 84 */ + "", "", "", "", "", /* 85 -89 */ + "", "", "", "", "", /* 90 - 94 */ + "", "", "", "", "", /* 95 - 99 */ + "", "", "", "", "", /* 100 - 104 */ + "", "", "", "", "", /* 105 - 109 */ + "", "", "", "", "", /* 110 - 114 */ + "", "", "", "", "", /* 115 - 119 */ + "", "", "", "", "", /* 120 - 124 */ + "", "", "", "", "", /* 125 - 129 */ + "", "", "", "", "", /* 130 - 134 */ + "", "", "", "", "", /* 135 - 139 */ + "", "", "", "", "", /* 140 - 144 */ + "", "", "", "", "", /* 145 - 149 */ + "", "", "", "", "", /* 150 - 154 */ + "", "", "", "", "", /* 155 - 159 */ + "", "", "", "", "", /* 160 - 164 */ + "", "", "", "", "", /* 165 - 169 */ + "", "", "", ""; /* 170 - 174 */ +}; + +&i2c0 { /* MIO 34-35 - can't stay here */ + status = "okay"; + clock-frequency = <400000>; + i2c-mux@74 { /* u46 */ + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x74>; + /* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */ + i2c@0 { /* PMBUS must be enabled via SW21 */ + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + reg_vcc1v2_lp4: tps544@15 { /* u97 */ + compatible = "ti,tps544b25"; + reg = <0x15>; + }; + reg_vcc1v1_lp4: tps544@16 { /* u95 */ + compatible = "ti,tps544b25"; + reg = <0x16>; + }; + reg_vdd1_1v8_lp4: tps544@17 { /* u99 */ + compatible = "ti,tps544b25"; + reg = <0x17>; + }; + /* UTIL_PMBUS connection */ + reg_vcc1v8: tps544@13 { /* u92 */ + compatible = "ti,tps544b25"; + reg = <0x13>; + }; + reg_vcc3v3: tps544@14 { /* u93 */ + compatible = "ti,tps544b25"; + reg = <0x14>; + }; + reg_vcc5v0: tps544@1e { /* u94 */ + compatible = "ti,tps544b25"; + reg = <0x1e>; + }; + reg_vpp_2v5_ddr4: tps544@1x { /* u3007 */ + compatible = "ti,tps544b25"; + reg = <0x17>; /* FIXME wrong in schematics */ + }; + }; + i2c@1 { /* PMBUS_INA226 */ + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + vcc_aux: ina226@42 { /* u86 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-vcc-aux"; + reg = <0x42>; + shunt-resistor = <5000>; + }; + vcc_ram: ina226@43 { /* u81 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-vcc-ram"; + reg = <0x43>; + shunt-resistor = <5000>; + }; + vcc1v1_lp4: ina226@46 { /* u96 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-vcc1v1-lp4"; + reg = <0x46>; + shunt-resistor = <5000>; + }; + vcc1v2_lp4: ina226@47 { /* u98 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-vcc1v2-lp4"; + reg = <0x47>; + shunt-resistor = <5000>; + }; + vdd1_1v8_lp4: ina226@48 { /* u100 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-vdd1-1v8-lp4"; + reg = <0x48>; + shunt-resistor = <5000>; + }; + }; + i2c@2 { /* PMBUS1 */ + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + reg_vccint: tps53681@c0 { /* u69 */ + compatible = "ti,tps53681", "ti,tps53679"; + reg = <0xc0>; + }; + reg_vcc_pmc: tps544@7 { /* u80 */ + compatible = "ti,tps544b25"; + reg = <0x7>; + }; + reg_vcc_ram: tps544@8 { /* u82 */ + compatible = "ti,tps544b25"; + reg = <0x8>; + }; + reg_vcc_pslp: tps544@9 { /* u83 */ + compatible = "ti,tps544b25"; + reg = <0x9>; + }; + reg_vcc_psfp: tps544@a { /* u84 */ + compatible = "ti,tps544b25"; + reg = <0xa>; + }; + reg_vccaux: tps544@d { /* u85 */ + compatible = "ti,tps544b25"; + reg = <0xd>; + }; + reg_vccaux_pmc: tps544@e { /* u87 */ + compatible = "ti,tps544b25"; + reg = <0xe>; + }; + reg_vcco_500: tps544@f { /* u88 */ + compatible = "ti,tps544b25"; + reg = <0xf>; + }; + reg_vcco_501: tps544@10 { /* u89 */ + compatible = "ti,tps544b25"; + reg = <0x10>; + }; + reg_vcco_502: tps544@11 { /* u90 */ + compatible = "ti,tps544b25"; + reg = <0x11>; + }; + reg_vcco_503: tps544@12 { /* u91 */ + compatible = "ti,tps544b25"; + reg = <0x12>; + }; + }; + i2c@3 { /* MEM PMBUS - FIXME bug in schematics */ + #address-cells = <1>; + #size-cells = <0>; + /* reg = <3>; */ + }; + i2c@4 { /* LP_I2C_SM */ + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + /* connected to U20G */ + }; + i2c@5 { /* DDR4_SODIMM */ + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + }; +}; + +/* TODO sysctrl via J239 */ +/* TODO samtec J212G/H via J242 */ +/* TODO teensy via U30 PCA9543A bus 1 */ +&i2c1 { /* i2c1 MIO 36-37 */ + status = "okay"; + clock-frequency = <400000>; + + /* Must be enabled via J242 */ + eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */ + compatible = "atmel,24c02"; + reg = <0x51>; + }; + + i2c-mux@74 { /* u47 */ + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x74>; + /* FIXME reset connected to SYSCTRL_IIC_MUX1_RESET */ + dc_i2c: i2c@0 { /* DC_I2C */ + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + /* Use for storing information about SC board */ + eeprom: eeprom@54 { /* u51 - m24128 16kB FIXME addr */ + compatible = "atmel,24c08"; + reg = <0x54>; + }; + si570_ref_clk: clock-generator@5d { /* u26 */ + #clock-cells = <0>; + compatible = "silabs,si570"; + reg = <0x5d>; /* FIXME addr */ + temperature-stability = <50>; + factory-fout = <156250000>; /* FIXME every chip can be different */ + clock-frequency = <33333333>; + clock-output-names = "REF_CLK"; /* FIXME */ + }; + /* Connection via Samtec U20D */ + /* Use for storing information about X-PRC card */ + x_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */ + compatible = "atmel,24c02"; + reg = <0x52>; + }; + + /* Use for setting up certain features on X-PRC card */ + x_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */ + compatible = "nxp,pca9534"; + reg = <0x22>; + gpio-controller; /* IRQ not connected */ + #gpio-cells = <2>; + gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", + "", "", "", ""; + gtr_sel0 { + gpio-hog; + gpios = <0 0>; + input; /* FIXME add meaning */ + line-name = "sw4_1"; + }; + gtr_sel1 { + gpio-hog; + gpios = <1 0>; + input; /* FIXME add meaning */ + line-name = "sw4_2"; + }; + gtr_sel2 { + gpio-hog; + gpios = <2 0>; + input; /* FIXME add meaning */ + line-name = "sw4_3"; + }; + gtr_sel3 { + gpio-hog; + gpios = <3 0>; + input; /* FIXME add meaning */ + line-name = "sw4_4"; + }; + }; + }; + i2c@2 { /* C0_DDR4 */ + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + si570_c0_ddr4: clock-generator@55 { /* u4 */ + #clock-cells = <0>; + compatible = "silabs,si570"; + reg = <0x55>; + temperature-stability = <50>; + factory-fout = <30000000>; + clock-frequency = <30000000>; + clock-output-names = "C0_DD4_SI570_CLK"; + }; + }; + i2c@3 { /* C1_SODIMM */ + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + si570_c1_lp4: clock-generator@55 { /* u7 */ + #clock-cells = <0>; + compatible = "silabs,si570"; + reg = <0x55>; + temperature-stability = <50>; + factory-fout = <30000000>; + clock-frequency = <30000000>; + clock-output-names = "C1_SODIMM_SI570_CLK"; + }; + }; + i2c@4 { /* C2_QDRIV */ + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + si570_c2_lp4: clock-generator@55 { /* u10 */ + #clock-cells = <0>; + compatible = "silabs,si570"; + reg = <0x55>; + temperature-stability = <50>; + factory-fout = <30000000>; + clock-frequency = <30000000>; + clock-output-names = "C2_QDRIV_SI570_CLK"; + }; + }; + i2c@5 { /* C3_DDR4 */ + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + si570_c3_lp4: clock-generator@55 { /* u15 */ + #clock-cells = <0>; + compatible = "silabs,si570"; + reg = <0x55>; + temperature-stability = <50>; + factory-fout = <30000000>; + clock-frequency = <30000000>; + clock-output-names = "C3_LP4_SI570_CLK"; + }; + }; + i2c@6 { /* HSDP_SI570 */ + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + si570_hsdp: clock-generator@5d { /* u19 */ + #clock-cells = <0>; + compatible = "silabs,si570"; + reg = <0x5d>; + temperature-stability = <50>; + factory-fout = <156250000>; + clock-frequency = <156250000>; + clock-output-names = "HSDP_SI570"; + }; + }; + }; +}; + +&usb0 { + status = "okay"; + xlnx,usb-polarity = <0>; + xlnx,usb-reset-mode = <0>; +}; + +&dwc3_0 { + status = "okay"; + dr_mode = "host"; + /* dr_mode = "peripheral"; */ + maximum-speed = "high-speed"; +}; + +&usb1 { + status = "disabled"; /* not at mem board */ + xlnx,usb-polarity = <0>; + xlnx,usb-reset-mode = <0>; +}; + +&dwc3_1 { + /delete-property/ phy-names ; + /delete-property/ phys ; + maximum-speed = "high-speed"; + snps,dis_u2_susphy_quirk ; + snps,dis_u3_susphy_quirk ; + status = "disabled"; +}; diff --git a/arch/arm/dts/zynqmp-a2197-p-revA.dts b/arch/arm/dts/zynqmp-p-a2197-00-revA.dts index 322b36e..d49b632 100644 --- a/arch/arm/dts/zynqmp-a2197-p-revA.dts +++ b/arch/arm/dts/zynqmp-p-a2197-00-revA.dts @@ -14,7 +14,7 @@ / { model = "Versal System Controller on a2197 Processor Char board RevA"; /* Tenzing */ - compatible = "xlnx,zynqmp-a2197-p-revA", "xlnx,zynqmp-a2197-revA", + compatible = "xlnx,zynqmp-p-a2197-00-revA", "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; aliases { @@ -41,7 +41,7 @@ memory@0 { device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>; /* FIXME don't know how big memory is there */ + reg = <0x0 0x0 0x0 0x80000000>; }; }; @@ -76,7 +76,7 @@ phy-mode = "sgmii"; /* DTG generates this properly 1512 */ is-internal-pcspma; /* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */ - phy0: phy@0 { + phy0: ethernet-phy@0 { reg = <0>; }; }; @@ -155,9 +155,9 @@ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xa>; }; - reg_vccint: tps53681@c0 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */ - compatible = "ti,tps53681"; /* FIXME no linux driver */ - reg = <0xc0>; + reg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */ + compatible = "ti,tps53681", "ti,tps53679"; + reg = <0x60>; /* vccint, vcc_io_soc */ }; }; @@ -165,7 +165,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <1>; - /* FIXME check alerts comming to SC */ + /* FIXME check alerts coming to SC */ vcc_fmc: ina226@42 { /* u81 */ compatible = "ti,ina226"; reg = <0x42>; @@ -387,9 +387,9 @@ compatible = "silabs,si570"; reg = <0x5d>; /* 570JAC000900DG */ temperature-stability = <50>; - factory-fout = <156250000>; /* FIXME every chip can be different */ + factory-fout = <33333333>; clock-frequency = <33333333>; - clock-output-names = "REF_CLK"; /* FIXME */ + clock-output-names = "ref_clk"; }; /* Connection via Samtec J212D */ /* Use for storing information about X-PRC card */ @@ -455,9 +455,9 @@ compatible = "silabs,si570"; reg = <0x60>; /* 570BAB000299DG */ temperature-stability = <50>; - factory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */ - clock-frequency = <33333333>; - clock-output-names = "REF_CLK"; /* FIXME */ + factory-fout = <200000000>; + clock-frequency = <200000000>; + clock-output-names = "si570_ddrdimm1_clk"; }; /* 0x50 SPD? */ }; @@ -470,9 +470,9 @@ compatible = "silabs,si570"; reg = <0x60>; /* 570BAB000299DG */ temperature-stability = <50>; - factory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */ - clock-frequency = <33333333>; - clock-output-names = "REF_CLK"; /* FIXME */ + factory-fout = <200000000>; + clock-frequency = <200000000>; + clock-output-names = "si570_ddrdimm2_clk"; }; /* 0x50 SPD? */ }; @@ -485,9 +485,9 @@ compatible = "silabs,si570"; reg = <0x60>; /* 570BAB000299DG */ temperature-stability = <50>; - factory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */ - clock-frequency = <33333333>; - clock-output-names = "LPDDR4_SI570_CLK"; + factory-fout = <200000000>; + clock-frequency = <200000000>; + clock-output-names = "si570_lpddr4_clk"; }; }; i2c@6 { /* HSDP_SI570 */ @@ -499,9 +499,9 @@ compatible = "silabs,si570"; reg = <0x5d>; /* 570JAC000900DG */ temperature-stability = <50>; - factory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */ - clock-frequency = <33333333>; - clock-output-names = "HSDP_SI570"; + factory-fout = <156250000>; + clock-frequency = <156250000>; + clock-output-names = "si570_hsdp_clk"; }; }; i2c@7 { /* PCIE_CLK */ diff --git a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts index 8824f5c..bb6a94e 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts @@ -75,7 +75,7 @@ status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; - phy0: phy@0 { + phy0: ethernet-phy@0 { reg = <0>; }; }; diff --git a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts index afa90a8..1cc8aaa 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts @@ -85,11 +85,12 @@ status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; - phy0: phy@5 { + phy0: ethernet-phy@5 { reg = <5>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; + ti,dp83867-rxctrl-strap-quirk; }; }; @@ -118,56 +119,66 @@ &nand0 { status = "okay"; arasan,has-mdma; - num-cs = <2>; - partition@0 { /* for testing purpose */ - label = "nand-fsbl-uboot"; - reg = <0x0 0x0 0x400000>; - }; - partition@1 { /* for testing purpose */ - label = "nand-linux"; - reg = <0x0 0x400000 0x1400000>; - }; - partition@2 { /* for testing purpose */ - label = "nand-device-tree"; - reg = <0x0 0x1800000 0x400000>; - }; - partition@3 { /* for testing purpose */ - label = "nand-rootfs"; - reg = <0x0 0x1C00000 0x1400000>; - }; - partition@4 { /* for testing purpose */ - label = "nand-bitstream"; - reg = <0x0 0x3000000 0x400000>; - }; - partition@5 { /* for testing purpose */ - label = "nand-misc"; - reg = <0x0 0x3400000 0xFCC00000>; - }; + nand@0 { + reg = <0x0>; + #address-cells = <0x2>; + #size-cells = <0x1>; - partition@6 { /* for testing purpose */ - label = "nand1-fsbl-uboot"; - reg = <0x1 0x0 0x400000>; - }; - partition@7 { /* for testing purpose */ - label = "nand1-linux"; - reg = <0x1 0x400000 0x1400000>; - }; - partition@8 { /* for testing purpose */ - label = "nand1-device-tree"; - reg = <0x1 0x1800000 0x400000>; - }; - partition@9 { /* for testing purpose */ - label = "nand1-rootfs"; - reg = <0x1 0x1C00000 0x1400000>; - }; - partition@10 { /* for testing purpose */ - label = "nand1-bitstream"; - reg = <0x1 0x3000000 0x400000>; + partition@0 { /* for testing purpose */ + label = "nand-fsbl-uboot"; + reg = <0x0 0x0 0x400000>; + }; + partition@1 { /* for testing purpose */ + label = "nand-linux"; + reg = <0x0 0x400000 0x1400000>; + }; + partition@2 { /* for testing purpose */ + label = "nand-device-tree"; + reg = <0x0 0x1800000 0x400000>; + }; + partition@3 { /* for testing purpose */ + label = "nand-rootfs"; + reg = <0x0 0x1c00000 0x1400000>; + }; + partition@4 { /* for testing purpose */ + label = "nand-bitstream"; + reg = <0x0 0x3000000 0x400000>; + }; + partition@5 { /* for testing purpose */ + label = "nand-misc"; + reg = <0x0 0x3400000 0xfcc00000>; + }; }; - partition@11 { /* for testing purpose */ - label = "nand1-misc"; - reg = <0x1 0x3400000 0xFCC00000>; + nand@1 { + reg = <0x1>; + #address-cells = <0x2>; + #size-cells = <0x1>; + + partition@0 { /* for testing purpose */ + label = "nand1-fsbl-uboot"; + reg = <0x0 0x0 0x400000>; + }; + partition@1 { /* for testing purpose */ + label = "nand1-linux"; + reg = <0x0 0x400000 0x1400000>; + }; + partition@2 { /* for testing purpose */ + label = "nand1-device-tree"; + reg = <0x0 0x1800000 0x400000>; + }; + partition@3 { /* for testing purpose */ + label = "nand1-rootfs"; + reg = <0x0 0x1c00000 0x1400000>; + }; + partition@4 { /* for testing purpose */ + label = "nand1-bitstream"; + reg = <0x0 0x3000000 0x400000>; + }; + partition@5 { /* for testing purpose */ + label = "nand1-misc"; + reg = <0x0 0x3400000 0xfcc00000>; + }; }; }; diff --git a/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts b/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts index d6a0103..2ead8dd 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts @@ -76,7 +76,7 @@ status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; - phy0: phy@0 { /* VSC8211 */ + phy0: ethernet-phy@0 { /* VSC8211 */ reg = <0>; }; }; diff --git a/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts b/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts index 0632b18..12c0173 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts @@ -73,7 +73,7 @@ status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; - phy0: phy@0 { + phy0: ethernet-phy@0 { reg = <0>; }; }; diff --git a/arch/arm/dts/zynqmp-zcu100-revC.dts b/arch/arm/dts/zynqmp-zcu100-revC.dts index 5285f62..14aa98d 100644 --- a/arch/arm/dts/zynqmp-zcu100-revC.dts +++ b/arch/arm/dts/zynqmp-zcu100-revC.dts @@ -124,6 +124,11 @@ compatible = "mmc-pwrseq-simple"; reset-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; /* WIFI_EN */ }; + + ina226 { + compatible = "iio-hwmon"; + io-channels = <&u35 0>, <&u35 1>, <&u35 2>, <&u35 3>; + }; }; &dcc { @@ -216,8 +221,9 @@ #size-cells = <0>; reg = <5>; /* PS_PMBUS */ - ina226@40 { /* u35 */ + u35: ina226@40 { /* u35 */ compatible = "ti,ina226"; + #io-channel-cells = <1>; reg = <0x40>; shunt-resistor = <10000>; /* MIO31 is alert which should be routed to PMUFW */ diff --git a/arch/arm/dts/zynqmp-zcu102-rev1.0.dts b/arch/arm/dts/zynqmp-zcu102-rev1.0.dts index 6647e97..6c702f26 100644 --- a/arch/arm/dts/zynqmp-zcu102-rev1.0.dts +++ b/arch/arm/dts/zynqmp-zcu102-rev1.0.dts @@ -34,3 +34,7 @@ reg = <0xe0 0x3>; }; }; + +&sdhci1 { + /delete-property/ no-1-8-v; +}; diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts b/arch/arm/dts/zynqmp-zcu102-revA.dts index 6e22871..78110c4 100644 --- a/arch/arm/dts/zynqmp-zcu102-revA.dts +++ b/arch/arm/dts/zynqmp-zcu102-revA.dts @@ -64,6 +64,79 @@ linux,default-trigger = "heartbeat"; }; }; + + ina226-u76 { + compatible = "iio-hwmon"; + io-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>; + }; + ina226-u77 { + compatible = "iio-hwmon"; + io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>; + }; + ina226-u78 { + compatible = "iio-hwmon"; + io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>; + }; + ina226-u87 { + compatible = "iio-hwmon"; + io-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>; + }; + ina226-u85 { + compatible = "iio-hwmon"; + io-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>; + }; + ina226-u86 { + compatible = "iio-hwmon"; + io-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>; + }; + ina226-u93 { + compatible = "iio-hwmon"; + io-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>; + }; + ina226-u88 { + compatible = "iio-hwmon"; + io-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>; + }; + ina226-u15 { + compatible = "iio-hwmon"; + io-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>; + }; + ina226-u92 { + compatible = "iio-hwmon"; + io-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>; + }; + ina226-u79 { + compatible = "iio-hwmon"; + io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>; + }; + ina226-u81 { + compatible = "iio-hwmon"; + io-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>; + }; + ina226-u80 { + compatible = "iio-hwmon"; + io-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>; + }; + ina226-u84 { + compatible = "iio-hwmon"; + io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>; + }; + ina226-u16 { + compatible = "iio-hwmon"; + io-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>; + }; + ina226-u65 { + compatible = "iio-hwmon"; + io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>; + }; + ina226-u74 { + compatible = "iio-hwmon"; + io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>; + }; + ina226-u75 { + compatible = "iio-hwmon"; + io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>; + }; }; &can1 { @@ -110,11 +183,13 @@ status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; - phy0: phy@21 { + phy0: ethernet-phy@21 { reg = <21>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; + ti,dp83867-rxctrl-strap-quirk; + /* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */ }; }; @@ -133,21 +208,11 @@ tca6416_u97: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; - gpio-controller; + gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; - /* - * IRQ not connected - * Lines: - * 0 - PS_GTR_LAN_SEL0 - * 1 - PS_GTR_LAN_SEL1 - * 2 - PS_GTR_LAN_SEL2 - * 3 - PS_GTR_LAN_SEL3 - * 4 - PCI_CLK_DIR_SEL - * 5 - IIC_MUX_RESET_B - * 6 - GEM3_EXP_RESET_B - * 7, 10 - 17 - not connected - */ - + gpio-line-names = "PS_GTR_LAN_SEL0", "PS_GTR_LAN_SEL1", "PS_GTR_LAN_SEL2", "PS_GTR_LAN_SEL3", + "PCI_CLK_DIR_SEL", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B", + "", "", "", "", "", "", "", "", ""; gtr_sel0 { gpio-hog; gpios = <0 0>; @@ -177,27 +242,12 @@ tca6416_u61: gpio@21 { compatible = "ti,tca6416"; reg = <0x21>; - gpio-controller; + gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; - /* - * IRQ not connected - * Lines: - * 0 - VCCPSPLL_EN - * 1 - MGTRAVCC_EN - * 2 - MGTRAVTT_EN - * 3 - VCCPSDDRPLL_EN - * 4 - MIO26_PMU_INPUT_LS - * 5 - PL_PMBUS_ALERT - * 6 - PS_PMBUS_ALERT - * 7 - MAXIM_PMBUS_ALERT - * 10 - PL_DDR4_VTERM_EN - * 11 - PL_DDR4_VPP_2V5_EN - * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON - * 13 - PS_DIMM_SUSPEND_EN - * 14 - PS_DDR4_VTERM_EN - * 15 - PS_DDR4_VPP_2V5_EN - * 16 - 17 - not connected - */ + gpio-line-names = "VCCPSPLL_EN", "MGTRAVCC_EN", "MGTRAVTT_EN", "VCCPSDDRPLL_EN", "MIO26_PMU_INPUT_LS", + "PL_PMBUS_ALERT", "PS_PMBUS_ALERT", "MAXIM_PMBUS_ALERT", "PL_DDR4_VTERM_EN", + "PL_DDR4_VPP_2V5_EN", "PS_DIMM_VDDQ_TO_PSVCCO_ON", "PS_DIMM_SUSPEND_EN", + "PS_DDR4_VTERM_EN", "PS_DDR4_VPP_2V5_EN", "", ""; }; i2c-mux@75 { /* u60 */ @@ -210,53 +260,73 @@ #size-cells = <0>; reg = <0>; /* PS_PMBUS */ - ina226@40 { /* u76 */ + u76: ina226@40 { /* u76 */ compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-u76"; reg = <0x40>; shunt-resistor = <5000>; }; - ina226@41 { /* u77 */ + u77: ina226@41 { /* u77 */ compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-u77"; reg = <0x41>; shunt-resistor = <5000>; }; - ina226@42 { /* u78 */ + u78: ina226@42 { /* u78 */ compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-u78"; reg = <0x42>; shunt-resistor = <5000>; }; - ina226@43 { /* u87 */ + u87: ina226@43 { /* u87 */ compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-u87"; reg = <0x43>; shunt-resistor = <5000>; }; - ina226@44 { /* u85 */ + u85: ina226@44 { /* u85 */ compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-u85"; reg = <0x44>; shunt-resistor = <5000>; }; - ina226@45 { /* u86 */ + u86: ina226@45 { /* u86 */ compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-u86"; reg = <0x45>; shunt-resistor = <5000>; }; - ina226@46 { /* u93 */ + u93: ina226@46 { /* u93 */ compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-u93"; reg = <0x46>; shunt-resistor = <5000>; }; - ina226@47 { /* u88 */ + u88: ina226@47 { /* u88 */ compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-u88"; reg = <0x47>; shunt-resistor = <5000>; }; - ina226@4a { /* u15 */ + u15: ina226@4a { /* u15 */ compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-u15"; reg = <0x4a>; shunt-resistor = <5000>; }; - ina226@4b { /* u92 */ + u92: ina226@4b { /* u92 */ compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-u92"; reg = <0x4b>; shunt-resistor = <5000>; }; @@ -266,43 +336,59 @@ #size-cells = <0>; reg = <1>; /* PL_PMBUS */ - ina226@40 { /* u79 */ + u79: ina226@40 { /* u79 */ compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-u79"; reg = <0x40>; shunt-resistor = <2000>; }; - ina226@41 { /* u81 */ + u81: ina226@41 { /* u81 */ compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-u81"; reg = <0x41>; shunt-resistor = <5000>; }; - ina226@42 { /* u80 */ + u80: ina226@42 { /* u80 */ compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-u80"; reg = <0x42>; shunt-resistor = <5000>; }; - ina226@43 { /* u84 */ + u84: ina226@43 { /* u84 */ compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-u84"; reg = <0x43>; shunt-resistor = <5000>; }; - ina226@44 { /* u16 */ + u16: ina226@44 { /* u16 */ compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-u16"; reg = <0x44>; shunt-resistor = <5000>; }; - ina226@45 { /* u65 */ + u65: ina226@45 { /* u65 */ compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-u65"; reg = <0x45>; shunt-resistor = <5000>; }; - ina226@46 { /* u74 */ + u74: ina226@46 { /* u74 */ compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-u74"; reg = <0x46>; shunt-resistor = <5000>; }; - ina226@47 { /* u75 */ + u75: ina226@47 { /* u75 */ compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-u75"; reg = <0x47>; shunt-resistor = <5000>; }; diff --git a/arch/arm/dts/zynqmp-zcu102-revB.dts b/arch/arm/dts/zynqmp-zcu102-revB.dts index af4d868..2132024 100644 --- a/arch/arm/dts/zynqmp-zcu102-revB.dts +++ b/arch/arm/dts/zynqmp-zcu102-revB.dts @@ -16,11 +16,13 @@ &gem3 { phy-handle = <&phyc>; - phyc: phy@c { + phyc: ethernet-phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; + ti,dp83867-rxctrl-strap-quirk; + /* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */ }; /* Cleanup from RevA */ /delete-node/ phy@21; diff --git a/arch/arm/dts/zynqmp-zcu104-revA.dts b/arch/arm/dts/zynqmp-zcu104-revA.dts index c7a3cdc..82557c8 100644 --- a/arch/arm/dts/zynqmp-zcu104-revA.dts +++ b/arch/arm/dts/zynqmp-zcu104-revA.dts @@ -50,15 +50,48 @@ status = "okay"; }; +&fpd_dma_chan1 { + status = "okay"; +}; + +&fpd_dma_chan2 { + status = "okay"; +}; + +&fpd_dma_chan3 { + status = "okay"; +}; + +&fpd_dma_chan4 { + status = "okay"; +}; + +&fpd_dma_chan5 { + status = "okay"; +}; + +&fpd_dma_chan6 { + status = "okay"; +}; + +&fpd_dma_chan7 { + status = "okay"; +}; + +&fpd_dma_chan8 { + status = "okay"; +}; + &gem3 { status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; - phy0: phy@c { + phy0: ethernet-phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; + ti,dp83867-rxctrl-strap-quirk; }; }; diff --git a/arch/arm/dts/zynqmp-zcu104-revC.dts b/arch/arm/dts/zynqmp-zcu104-revC.dts index 7df16b0..e0e7dac 100644 --- a/arch/arm/dts/zynqmp-zcu104-revC.dts +++ b/arch/arm/dts/zynqmp-zcu104-revC.dts @@ -41,6 +41,11 @@ device_type = "memory"; reg = <0x0 0x0 0x0 0x80000000>; }; + + ina226 { + compatible = "iio-hwmon"; + io-channels = <&u183 0>, <&u183 1>, <&u183 2>, <&u183 3>; + }; }; &can1 { @@ -51,15 +56,48 @@ status = "okay"; }; +&fpd_dma_chan1 { + status = "okay"; +}; + +&fpd_dma_chan2 { + status = "okay"; +}; + +&fpd_dma_chan3 { + status = "okay"; +}; + +&fpd_dma_chan4 { + status = "okay"; +}; + +&fpd_dma_chan5 { + status = "okay"; +}; + +&fpd_dma_chan6 { + status = "okay"; +}; + +&fpd_dma_chan7 { + status = "okay"; +}; + +&fpd_dma_chan8 { + status = "okay"; +}; + &gem3 { status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; - phy0: phy@c { + phy0: ethernet-phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; + ti,dp83867-rxctrl-strap-quirk; }; }; @@ -150,8 +188,9 @@ #address-cells = <1>; #size-cells = <0>; reg = <3>; - ina226@40 { /* u183 */ + u183: ina226@40 { /* u183 */ compatible = "ti,ina226"; + #io-channel-cells = <1>; reg = <0x40>; shunt-resistor = <5000>; }; diff --git a/arch/arm/dts/zynqmp-zcu106-revA.dts b/arch/arm/dts/zynqmp-zcu106-revA.dts index 9fd3953..b4dd101 100644 --- a/arch/arm/dts/zynqmp-zcu106-revA.dts +++ b/arch/arm/dts/zynqmp-zcu106-revA.dts @@ -64,6 +64,79 @@ linux,default-trigger = "heartbeat"; }; }; + + ina226-u76 { + compatible = "iio-hwmon"; + io-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>; + }; + ina226-u77 { + compatible = "iio-hwmon"; + io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>; + }; + ina226-u78 { + compatible = "iio-hwmon"; + io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>; + }; + ina226-u87 { + compatible = "iio-hwmon"; + io-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>; + }; + ina226-u85 { + compatible = "iio-hwmon"; + io-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>; + }; + ina226-u86 { + compatible = "iio-hwmon"; + io-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>; + }; + ina226-u93 { + compatible = "iio-hwmon"; + io-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>; + }; + ina226-u88 { + compatible = "iio-hwmon"; + io-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>; + }; + ina226-u15 { + compatible = "iio-hwmon"; + io-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>; + }; + ina226-u92 { + compatible = "iio-hwmon"; + io-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>; + }; + ina226-u79 { + compatible = "iio-hwmon"; + io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>; + }; + ina226-u81 { + compatible = "iio-hwmon"; + io-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>; + }; + ina226-u80 { + compatible = "iio-hwmon"; + io-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>; + }; + ina226-u84 { + compatible = "iio-hwmon"; + io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>; + }; + ina226-u16 { + compatible = "iio-hwmon"; + io-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>; + }; + ina226-u65 { + compatible = "iio-hwmon"; + io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>; + }; + ina226-u74 { + compatible = "iio-hwmon"; + io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>; + }; + ina226-u75 { + compatible = "iio-hwmon"; + io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>; + }; }; &can1 { @@ -110,11 +183,12 @@ status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; - phy0: phy@c { + phy0: ethernet-phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; + ti,dp83867-rxctrl-strap-quirk; }; }; @@ -184,53 +258,73 @@ #size-cells = <0>; reg = <0>; /* PS_PMBUS */ - ina226@40 { /* u76 */ + u76: ina226@40 { /* u76 */ compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-u76"; reg = <0x40>; shunt-resistor = <5000>; }; - ina226@41 { /* u77 */ + u77: ina226@41 { /* u77 */ compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-u77"; reg = <0x41>; shunt-resistor = <5000>; }; - ina226@42 { /* u78 */ + u78: ina226@42 { /* u78 */ compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-u78"; reg = <0x42>; shunt-resistor = <5000>; }; - ina226@43 { /* u87 */ + u87: ina226@43 { /* u87 */ compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-u87"; reg = <0x43>; shunt-resistor = <5000>; }; - ina226@44 { /* u85 */ + u85: ina226@44 { /* u85 */ compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-u85"; reg = <0x44>; shunt-resistor = <5000>; }; - ina226@45 { /* u86 */ + u86: ina226@45 { /* u86 */ compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-u86"; reg = <0x45>; shunt-resistor = <5000>; }; - ina226@46 { /* u93 */ + u93: ina226@46 { /* u93 */ compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-u93"; reg = <0x46>; shunt-resistor = <5000>; }; - ina226@47 { /* u88 */ + u88: ina226@47 { /* u88 */ compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-u88"; reg = <0x47>; shunt-resistor = <5000>; }; - ina226@4a { /* u15 */ + u15: ina226@4a { /* u15 */ compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-u15"; reg = <0x4a>; shunt-resistor = <5000>; }; - ina226@4b { /* u92 */ + u92: ina226@4b { /* u92 */ compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-u92"; reg = <0x4b>; shunt-resistor = <5000>; }; @@ -240,43 +334,59 @@ #size-cells = <0>; reg = <1>; /* PL_PMBUS */ - ina226@40 { /* u79 */ + u79: ina226@40 { /* u79 */ compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-u79"; reg = <0x40>; shunt-resistor = <2000>; }; - ina226@41 { /* u81 */ + u81: ina226@41 { /* u81 */ compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-u81"; reg = <0x41>; shunt-resistor = <5000>; }; - ina226@42 { /* u80 */ + u80: ina226@42 { /* u80 */ compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-u80"; reg = <0x42>; shunt-resistor = <5000>; }; - ina226@43 { /* u84 */ + u84: ina226@43 { /* u84 */ compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-u84"; reg = <0x43>; shunt-resistor = <5000>; }; - ina226@44 { /* u16 */ + u16: ina226@44 { /* u16 */ compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-u16"; reg = <0x44>; shunt-resistor = <5000>; }; - ina226@45 { /* u65 */ + u65: ina226@45 { /* u65 */ compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-u65"; reg = <0x45>; shunt-resistor = <5000>; }; - ina226@46 { /* u74 */ + u74: ina226@46 { /* u74 */ compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-u74"; reg = <0x46>; shunt-resistor = <5000>; }; - ina226@47 { /* u75 */ + u75: ina226@47 { /* u75 */ compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-u75"; reg = <0x47>; shunt-resistor = <5000>; }; diff --git a/arch/arm/dts/zynqmp-zcu111-revA.dts b/arch/arm/dts/zynqmp-zcu111-revA.dts index 2e28a39..aabf73d 100644 --- a/arch/arm/dts/zynqmp-zcu111-revA.dts +++ b/arch/arm/dts/zynqmp-zcu111-revA.dts @@ -64,6 +64,63 @@ linux,default-trigger = "heartbeat"; }; }; + + ina226-u67 { + compatible = "iio-hwmon"; + io-channels = <&u67 0>, <&u67 1>, <&u67 2>, <&u67 3>; + }; + ina226-u59 { + compatible = "iio-hwmon"; + io-channels = <&u59 0>, <&u59 1>, <&u59 2>, <&u59 3>; + }; + ina226-u61 { + compatible = "iio-hwmon"; + io-channels = <&u61 0>, <&u61 1>, <&u61 2>, <&u61 3>; + }; + ina226-u60 { + compatible = "iio-hwmon"; + io-channels = <&u60 0>, <&u60 1>, <&u60 2>, <&u60 3>; + }; + ina226-u64 { + compatible = "iio-hwmon"; + io-channels = <&u64 0>, <&u64 1>, <&u64 2>, <&u64 3>; + }; + ina226-u69 { + compatible = "iio-hwmon"; + io-channels = <&u69 0>, <&u69 1>, <&u69 2>, <&u69 3>; + }; + ina226-u66 { + compatible = "iio-hwmon"; + io-channels = <&u66 0>, <&u66 1>, <&u66 2>, <&u66 3>; + }; + ina226-u65 { + compatible = "iio-hwmon"; + io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>; + }; + ina226-u63 { + compatible = "iio-hwmon"; + io-channels = <&u63 0>, <&u63 1>, <&u63 2>, <&u63 3>; + }; + ina226-u3 { + compatible = "iio-hwmon"; + io-channels = <&u3 0>, <&u3 1>, <&u3 2>, <&u3 3>; + }; + ina226-u71 { + compatible = "iio-hwmon"; + io-channels = <&u71 0>, <&u71 1>, <&u71 2>, <&u71 3>; + }; + ina226-u77 { + compatible = "iio-hwmon"; + io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>; + }; + ina226-u73 { + compatible = "iio-hwmon"; + io-channels = <&u73 0>, <&u73 1>, <&u73 2>, <&u73 3>; + }; + ina226-u79 { + compatible = "iio-hwmon"; + io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>; + }; }; &dcc { @@ -106,11 +163,12 @@ status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; - phy0: phy@c { + phy0: ethernet-phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; + ti,dp83867-rxctrl-strap-quirk; }; }; @@ -160,73 +218,101 @@ reg = <0>; /* PS_PMBUS */ /* PMBUS_ALERT done via pca9544 */ - ina226@40 { /* u67 */ + u67: ina226@40 { /* u67 */ compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-u67"; reg = <0x40>; shunt-resistor = <2000>; }; - ina226@41 { /* u59 */ + u59: ina226@41 { /* u59 */ compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-u59"; reg = <0x41>; shunt-resistor = <5000>; }; - ina226@42 { /* u61 */ + u61: ina226@42 { /* u61 */ compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-u61"; reg = <0x42>; shunt-resistor = <5000>; }; - ina226@43 { /* u60 */ + u60: ina226@43 { /* u60 */ compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-u60"; reg = <0x43>; shunt-resistor = <5000>; }; - ina226@45 { /* u64 */ + u64: ina226@45 { /* u64 */ compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-u64"; reg = <0x45>; shunt-resistor = <5000>; }; - ina226@46 { /* u69 */ + u69: ina226@46 { /* u69 */ compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-u69"; reg = <0x46>; shunt-resistor = <2000>; }; - ina226@47 { /* u66 */ + u66: ina226@47 { /* u66 */ compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-u66"; reg = <0x47>; shunt-resistor = <5000>; }; - ina226@48 { /* u65 */ + u65: ina226@48 { /* u65 */ compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-u65"; reg = <0x48>; shunt-resistor = <5000>; }; - ina226@49 { /* u63 */ + u63: ina226@49 { /* u63 */ compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-u63"; reg = <0x49>; shunt-resistor = <5000>; }; - ina226@4a { /* u3 */ + u3: ina226@4a { /* u3 */ compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-u3"; reg = <0x4a>; shunt-resistor = <5000>; }; - ina226@4b { /* u71 */ + u71: ina226@4b { /* u71 */ compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-u71"; reg = <0x4b>; shunt-resistor = <5000>; }; - ina226@4c { /* u77 */ + u77: ina226@4c { /* u77 */ compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-u77"; reg = <0x4c>; shunt-resistor = <5000>; }; - ina226@4d { /* u73 */ + u73: ina226@4d { /* u73 */ compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-u73"; reg = <0x4d>; shunt-resistor = <5000>; }; - ina226@4e { /* u79 */ + u79: ina226@4e { /* u79 */ compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-u79"; reg = <0x4e>; shunt-resistor = <5000>; }; @@ -332,7 +418,7 @@ reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; - clock-frequency = <148500000>; + clock-frequency = <156250000>; clock-output-names = "si570_mgt"; }; }; diff --git a/arch/arm/dts/zynqmp-zcu216-revA.dts b/arch/arm/dts/zynqmp-zcu216-revA.dts new file mode 100644 index 0000000..dd9cd7b --- /dev/null +++ b/arch/arm/dts/zynqmp-zcu216-revA.dts @@ -0,0 +1,592 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * dts file for Xilinx ZynqMP ZCU216 + * + * (C) Copyright 2017 - 2019, Xilinx, Inc. + * + * Michal Simek <michal.simek@xilinx.com> + */ + +/dts-v1/; + +#include "zynqmp.dtsi" +#include "zynqmp-clk-ccf.dtsi" +#include <dt-bindings/input/input.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/phy/phy.h> + +/ { + model = "ZynqMP ZCU216 RevA"; + compatible = "xlnx,zynqmp-zcu216-revA", "xlnx,zynqmp-zcu216", "xlnx,zynqmp"; + + aliases { + ethernet0 = &gem3; + gpio0 = &gpio; + i2c0 = &i2c0; + i2c1 = &i2c1; + mmc0 = &sdhci1; + rtc0 = &rtc; + serial0 = &uart0; + serial1 = &dcc; + spi0 = &qspi; + usb0 = &usb0; + }; + + chosen { + bootargs = "earlycon"; + stdout-path = "serial0:115200n8"; + xlnx,eeprom = <&eeprom>; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + sw19 { + label = "sw19"; + gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; + linux,code = <KEY_DOWN>; + gpio-key,wakeup; + autorepeat; + }; + }; + + leds { + compatible = "gpio-leds"; + heartbeat_led { + label = "heartbeat"; + gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + ina226-vccint { + compatible = "iio-hwmon"; + io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>; + }; + ina226-vccint-io-bram-ps { + compatible = "iio-hwmon"; + io-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>; + }; + ina226-vcc1v8 { + compatible = "iio-hwmon"; + io-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>; + }; + ina226-vcc1v2 { + compatible = "iio-hwmon"; + io-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>; + }; + ina226-vadj-fmc { + compatible = "iio-hwmon"; + io-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>; + }; + ina226-mgtavcc { + compatible = "iio-hwmon"; + io-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>; + }; + ina226-mgt1v2 { + compatible = "iio-hwmon"; + io-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>; + }; + ina226-mgt1v8 { + compatible = "iio-hwmon"; + io-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>; + }; + ina226-vccint-ams { + compatible = "iio-hwmon"; + io-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>; + }; + ina226-dac-avtt { + compatible = "iio-hwmon"; + io-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>; + }; + ina226-dac-avccaux { + compatible = "iio-hwmon"; + io-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>, <&dac_avccaux 3>; + }; + ina226-adc-avcc { + compatible = "iio-hwmon"; + io-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>; + }; + ina226-adc-avccaux { + compatible = "iio-hwmon"; + io-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>, <&adc_avccaux 3>; + }; + ina226-dac-avcc { + compatible = "iio-hwmon"; + io-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>; + }; +}; + +&dcc { + status = "okay"; +}; + +&fpd_dma_chan1 { + status = "okay"; +}; + +&fpd_dma_chan2 { + status = "okay"; +}; + +&fpd_dma_chan3 { + status = "okay"; +}; + +&fpd_dma_chan4 { + status = "okay"; +}; + +&fpd_dma_chan5 { + status = "okay"; +}; + +&fpd_dma_chan6 { + status = "okay"; +}; + +&fpd_dma_chan7 { + status = "okay"; +}; + +&fpd_dma_chan8 { + status = "okay"; +}; + +&gem3 { + status = "okay"; + phy-handle = <&phy0>; + phy-mode = "rgmii-id"; + phy0: ethernet-phy@c { + reg = <0xc>; + ti,rx-internal-delay = <0x8>; + ti,tx-internal-delay = <0xa>; + ti,fifo-depth = <0x1>; + ti,dp83867-rxctrl-strap-quirk; + }; +}; + +&gpio { + status = "okay"; + gpio-line-names = "QSPI_LWR_CLK", "QSPI_LWR_DQ1", "QSPI_LWR_DQ2", "QSPI_LWR_DQ3", "QSPI_LWR_DQ0", /* 0 - 4 */ + "QSPI_LWR_CS_B", "", "QSPI_UPR_CS_B", "QSPI_UPR_DQ0", "QSPI_UPR_DQ1", /* 5 - 9 */ + "QSPI_UPR_DQ2", "QSPI_UPR_DQ3", "QSPI_UPR_CLK", "PS_GPIO2", "I2C0_SCL", /* 10 - 14 */ + "I2C0_SDA", "I2C1_SCL", "I2C1_SDA", "UART0_TXD", "UART0_RXD", /* 15 - 19 */ + "", "", "BUTTON", "LED", "", /* 20 - 24 */ + "", "PMU_INPUT", "", "", "", /* 25 - 29 */ + "", "", "PMU_GPO0", "PMU_GPO1", "PMU_GPO2", /* 30 - 34 */ + "PMU_GPO3", "PMU_GPO4", "PMU_GPO5", "PS_GPIO1", "SDIO_SEL", /* 35 - 39 */ + "SDIO_DIR_CMD", "SDIO_DIR_DAT0", "SDIO_DIR_DAT1", "", "", /* 40 - 44 */ + "SDIO_DETECT", "SDIO_DAT0", "SDIO_DAT1", "SDIO_DAT2", "SDIO_DAT3", /* 45 - 49 */ + "SDIO_CMD", "SDIO_CLK", "USB_CLK", "USB_DIR", "USB_DATA2", /* 50 - 54 */ + "USB_NXT", "USB_DATA0", "USB_DATA1", "USB_STP", "USB_DATA3", /* 55 - 59 */ + "USB_DATA4", "USB_DATA5", "USB_DATA6", "USB_DATA7", "ENET_TX_CLK", /* 60 - 64 */ + "ENET_TX_D0", "ENET_TX_D1", "ENET_TX_D2", "ENET_TX_D3", "ENET_TX_CTRL", /* 65 - 69 */ + "ENET_RX_CLK", "ENET_RX_D0", "ENET_RX_D1", "ENET_RX_D2", "ENET_RX_D3", /* 70 - 74 */ + "ENET_RX_CTRL", "ENET_MDC", "ENET_MDIO", /* 75 - 77, MIO end and EMIO start */ + "", "", /* 78 - 79 */ + "", "", "", "", "", /* 80 - 84 */ + "", "", "", "", "", /* 85 -89 */ + "", "", "", "", "", /* 90 - 94 */ + "", "", "", "", "", /* 95 - 99 */ + "", "", "", "", "", /* 100 - 104 */ + "", "", "", "", "", /* 105 - 109 */ + "", "", "", "", "", /* 110 - 114 */ + "", "", "", "", "", /* 115 - 119 */ + "", "", "", "", "", /* 120 - 124 */ + "", "", "", "", "", /* 125 - 129 */ + "", "", "", "", "", /* 130 - 134 */ + "", "", "", "", "", /* 135 - 139 */ + "", "", "", "", "", /* 140 - 144 */ + "", "", "", "", "", /* 145 - 149 */ + "", "", "", "", "", /* 150 - 154 */ + "", "", "", "", "", /* 155 - 159 */ + "", "", "", "", "", /* 160 - 164 */ + "", "", "", "", "", /* 165 - 169 */ + "", "", "", ""; /* 170 - 174 */ +}; + +&gpu { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <400000>; + + tca6416_u15: gpio@20 { /* u15 */ + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; /* interrupt not connected */ + #gpio-cells = <2>; + gpio-line-names = "MAX6643_OT_B", "MAX6643_FANFAIL_B", "MIO26_PMU_INPUT_LS", "", /* 0 - 3 */ + "", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B", "MAX6643_FULL_SPEED", /* 4 - 7 */ + "FMCP_HSPC_PRSNT_M2C_B", "", "", "VCCINT_VRHOT_B", /* 10 - 13 */ + "", "8A34001_EXP_RST_B", "IRPS5401_ALERT_B", "INA226_PMBUS_ALERT"; /* 14 - 17 */ + }; + + i2c-mux@75 { /* u17 */ + compatible = "nxp,pca9544"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x75>; + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + /* PS_PMBUS */ + /* PMBUS_ALERT done via pca9544 */ + vccint: ina226@40 { /* u65 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-vccint"; + reg = <0x40>; + shunt-resistor = <5000>; + }; + vccint_io_bram_ps: ina226@41 { /* u57 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-vccint-io-bram-ps"; + reg = <0x41>; + shunt-resistor = <2000>; + }; + vcc1v8: ina226@42 { /* u60 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-vcc1v8"; + reg = <0x42>; + shunt-resistor = <2000>; + }; + vcc1v2: ina226@43 { /* u58 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-vcc1v2"; + reg = <0x43>; + shunt-resistor = <5000>; + }; + vadj_fmc: ina226@45 { /* u62 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-vadj-fmc"; + reg = <0x45>; + shunt-resistor = <5000>; + }; + mgtavcc: ina226@46 { /* u67 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-mgtavcc"; + reg = <0x46>; + shunt-resistor = <2000>; + }; + mgt1v2: ina226@47 { /* u63 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-mgt1v2"; + reg = <0x47>; + shunt-resistor = <5000>; + }; + mgt1v8: ina226@48 { /* u64 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-mgt1v8"; + reg = <0x48>; + shunt-resistor = <5000>; + }; + vccint_ams: ina226@49 { /* u61 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-vccint-ams"; + reg = <0x49>; + shunt-resistor = <2000>; + }; + dac_avtt: ina226@4a { /* u59 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-dac-avtt"; + reg = <0x4a>; + shunt-resistor = <5000>; + }; + dac_avccaux: ina226@4b { /* u124 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-dac-avccaux"; + reg = <0x4b>; + shunt-resistor = <5000>; + }; + adc_avcc: ina226@4c { /* u75 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-adc-avcc"; + reg = <0x4c>; + shunt-resistor = <5000>; + }; + adc_avccaux: ina226@4d { /* u71 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-adc-avccaux"; + reg = <0x4d>; + shunt-resistor = <5000>; + }; + dac_avcc: ina226@4e { /* u77 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-dac-avcc"; + reg = <0x4e>; + shunt-resistor = <5000>; + }; + }; + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + /* NC */ + }; + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + /* u104 - ir35215 0x10/0x40 */ + /* u127 - ir38164 0x1b/0x4b */ + /* u112 - ir38164 0x13/0x43 */ + /* u123 - ir38164 0x1c/0x4c */ + + irps5401_44: irps54012@44 { /* IRPS5401 - u53 */ + #clock-cells = <0>; + compatible = "infineon,irps5401"; + reg = <0x44>; /* i2c addr 0x14 */ + }; + irps5401_45: irps54012@45 { /* IRPS5401 - u55 */ + #clock-cells = <0>; + compatible = "infineon,irps5401"; + reg = <0x45>; /* i2c addr 0x15 */ + }; + /* J21 header too */ + + }; + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + /* SYSMON */ + }; + }; + /* u38 MPS430 */ +}; + +&i2c1 { + status = "okay"; + clock-frequency = <400000>; + + i2c-mux@74 { + compatible = "nxp,pca9548"; /* u20 */ + #address-cells = <1>; + #size-cells = <0>; + reg = <0x74>; + /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ + i2c_eeprom: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + /* + * IIC_EEPROM 1kB memory which uses 256B blocks + * where every block has different address. + * 0 - 256B address 0x54 + * 256B - 512B address 0x55 + * 512B - 768B address 0x56 + * 768B - 1024B address 0x57 + */ + eeprom: eeprom@54 { /* u21 */ + compatible = "atmel,24c08"; + reg = <0x54>; + }; + }; + i2c_si5341: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + si5341: clock-generator@36 { /* SI5341 - u43 */ + compatible = "si5341"; + reg = <0x36>; + }; + + }; + i2c_si570_user_c0: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + si570_1: clock-generator@5d { /* USER C0 SI570 - u47 */ + #clock-cells = <0>; + compatible = "silabs,si570"; + reg = <0x5d>; + temperature-stability = <50>; + factory-fout = <300000000>; + clock-frequency = <300000000>; + clock-output-names = "si570_user_c0"; + }; + }; + i2c_si570_mgt: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + si570_2: clock-generator@5d { /* USER MGT SI570 - u48 */ + #clock-cells = <0>; + compatible = "silabs,si570"; + reg = <0x5d>; + temperature-stability = <50>; + factory-fout = <156250000>; + clock-frequency = <148500000>; + clock-output-names = "si570_mgt"; + }; + }; + i2c_8a34001: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + /* U409B - 8a34001 */ + }; + i2c_clk104: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + /* CLK104_SDA */ + }; + i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + /* RFMCP connector */ + }; + /* 7 NC */ + }; + + i2c-mux@75 { + compatible = "nxp,pca9548"; /* u22 */ + #address-cells = <1>; + #size-cells = <0>; + reg = <0x75>; + /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + /* FMCP_HSPC_IIC */ + }; + i2c_si570_user_c1: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + si570_3: clock-generator@5d { /* USER C1 SI570 - u130 */ + #clock-cells = <0>; + compatible = "silabs,si570"; + reg = <0x5d>; + temperature-stability = <50>; + factory-fout = <300000000>; + clock-frequency = <300000000>; + clock-output-names = "si570_user_c1"; + }; + }; + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + /* SYSMON */ + }; + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + /* DDR4 SODIMM */ + }; + i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + /* SFP3 */ + }; + i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + /* SFP2 */ + }; + i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + /* SFP1 */ + }; + i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + /* SFP0 */ + }; + }; + /* MSP430 */ +}; + +&qspi { + status = "okay"; + is-dual = <1>; + flash@0 { + compatible = "m25p80", "jedec,spi-nor"; /* U11 and U12 MT25QU02GCBBE12 1Gb */ + #address-cells = <1>; + #size-cells = <1>; + reg = <0x0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ + spi-max-frequency = <108000000>; /* Based on DC1 spec */ + }; +}; + +&rtc { + status = "okay"; +}; + +&sata { + status = "okay"; + /* SATA OOB timing settings */ + ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; + ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; + ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; + ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; + ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; + ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; + ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; + ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; + phy-names = "sata-phy"; + phys = <&lane3 PHY_TYPE_SATA 1 3 125000000>; +}; + +/* SD1 with level shifter */ +&sdhci1 { + status = "okay"; + disable-wp; + xlnx,mio_bank = <1>; +}; + +&serdes { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +/* ULPI SMSC USB3320 */ +&usb0 { + status = "okay"; +}; + +&dwc3_0 { + status = "okay"; + dr_mode = "host"; + snps,usb3_lpm_capable; + phy-names = "usb3-phy"; + phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>; +}; diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 8e35171..b453941 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -12,6 +12,9 @@ * the License, or (at your option) any later version. */ +#include <dt-bindings/power/xlnx-zynqmp-power.h> +#include <dt-bindings/reset/xlnx-zynqmp-resets.h> + / { compatible = "xlnx,zynqmp"; #address-cells = <2>; @@ -112,7 +115,7 @@ <0x0 0xff9905e0 0x0 0x20>, <0x0 0xff990e80 0x0 0x20>, <0x0 0xff990ea0 0x0 0x20>; - reg-names = "local_request_region" , "local_response_region", + reg-names = "local_request_region", "local_response_region", "remote_request_region", "remote_response_region"; #mbox-cells = <1>; xlnx,ipi-id = <4>; @@ -140,7 +143,7 @@ }; firmware { - zynqmp-firmware { + zynqmp_firmware: zynqmp-firmware { compatible = "xlnx,zynqmp-firmware"; method = "smc"; #power-domain-cells = <0x1>; @@ -154,6 +157,11 @@ mboxes = <&ipi_mailbox_pmu1 0>, <&ipi_mailbox_pmu1 1>; mbox-names = "tx", "rx"; }; + + zynqmp_reset: reset-controller { + compatible = "xlnx,zynqmp-reset"; + #reset-cells = <1>; + }; }; }; @@ -279,6 +287,7 @@ interrupt-parent = <&gic>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; + power-domains = <&zynqmp_firmware PD_CAN_0>; }; can1: can@ff070000 { @@ -290,6 +299,7 @@ interrupt-parent = <&gic>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; + power-domains = <&zynqmp_firmware PD_CAN_1>; }; cci: cci@fd6e0000 { @@ -322,6 +332,7 @@ xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14e8>; + power-domains = <&zynqmp_firmware PD_GDMA>; }; fpd_dma_chan2: dma@fd510000 { @@ -334,6 +345,7 @@ xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14e9>; + power-domains = <&zynqmp_firmware PD_GDMA>; }; fpd_dma_chan3: dma@fd520000 { @@ -346,6 +358,7 @@ xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14ea>; + power-domains = <&zynqmp_firmware PD_GDMA>; }; fpd_dma_chan4: dma@fd530000 { @@ -358,6 +371,7 @@ xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14eb>; + power-domains = <&zynqmp_firmware PD_GDMA>; }; fpd_dma_chan5: dma@fd540000 { @@ -370,6 +384,7 @@ xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14ec>; + power-domains = <&zynqmp_firmware PD_GDMA>; }; fpd_dma_chan6: dma@fd550000 { @@ -382,6 +397,7 @@ xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14ed>; + power-domains = <&zynqmp_firmware PD_GDMA>; }; fpd_dma_chan7: dma@fd560000 { @@ -394,6 +410,7 @@ xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14ee>; + power-domains = <&zynqmp_firmware PD_GDMA>; }; fpd_dma_chan8: dma@fd570000 { @@ -406,6 +423,7 @@ xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14ef>; + power-domains = <&zynqmp_firmware PD_GDMA>; }; gpu: gpu@fd4b0000 { @@ -416,6 +434,7 @@ interrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>; interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP0", "IRQPPMMU0", "IRQPP1", "IRQPPMMU1"; clock-names = "gpu", "gpu_pp0", "gpu_pp1"; + power-domains = <&zynqmp_firmware PD_GPU>; }; /* LPDDMA default allows only secured access. inorder to enable @@ -432,6 +451,7 @@ xlnx,bus-width = <64>; #stream-id-cells = <1>; iommus = <&smmu 0x868>; + power-domains = <&zynqmp_firmware PD_ADMA>; }; lpd_dma_chan2: dma@ffa90000 { @@ -444,6 +464,7 @@ xlnx,bus-width = <64>; #stream-id-cells = <1>; iommus = <&smmu 0x869>; + power-domains = <&zynqmp_firmware PD_ADMA>; }; lpd_dma_chan3: dma@ffaa0000 { @@ -456,6 +477,7 @@ xlnx,bus-width = <64>; #stream-id-cells = <1>; iommus = <&smmu 0x86a>; + power-domains = <&zynqmp_firmware PD_ADMA>; }; lpd_dma_chan4: dma@ffab0000 { @@ -468,6 +490,7 @@ xlnx,bus-width = <64>; #stream-id-cells = <1>; iommus = <&smmu 0x86b>; + power-domains = <&zynqmp_firmware PD_ADMA>; }; lpd_dma_chan5: dma@ffac0000 { @@ -480,6 +503,7 @@ xlnx,bus-width = <64>; #stream-id-cells = <1>; iommus = <&smmu 0x86c>; + power-domains = <&zynqmp_firmware PD_ADMA>; }; lpd_dma_chan6: dma@ffad0000 { @@ -492,6 +516,7 @@ xlnx,bus-width = <64>; #stream-id-cells = <1>; iommus = <&smmu 0x86d>; + power-domains = <&zynqmp_firmware PD_ADMA>; }; lpd_dma_chan7: dma@ffae0000 { @@ -504,6 +529,7 @@ xlnx,bus-width = <64>; #stream-id-cells = <1>; iommus = <&smmu 0x86e>; + power-domains = <&zynqmp_firmware PD_ADMA>; }; lpd_dma_chan8: dma@ffaf0000 { @@ -516,6 +542,7 @@ xlnx,bus-width = <64>; #stream-id-cells = <1>; iommus = <&smmu 0x86f>; + power-domains = <&zynqmp_firmware PD_ADMA>; }; mc: memory-controller@fd070000 { @@ -532,14 +559,15 @@ clock-names = "clk_sys", "clk_flash"; interrupt-parent = <&gic>; interrupts = <0 14 4>; - #address-cells = <2>; - #size-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x872>; + power-domains = <&zynqmp_firmware PD_NAND>; }; gem0: ethernet@ff0b0000 { - compatible = "cdns,zynqmp-gem"; + compatible = "cdns,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 57 4>, <0 57 4>; @@ -549,10 +577,11 @@ #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x874>; + power-domains = <&zynqmp_firmware PD_ETH_0>; }; gem1: ethernet@ff0c0000 { - compatible = "cdns,zynqmp-gem"; + compatible = "cdns,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 59 4>, <0 59 4>; @@ -562,10 +591,11 @@ #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x875>; + power-domains = <&zynqmp_firmware PD_ETH_1>; }; gem2: ethernet@ff0d0000 { - compatible = "cdns,zynqmp-gem"; + compatible = "cdns,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 61 4>, <0 61 4>; @@ -575,10 +605,11 @@ #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x876>; + power-domains = <&zynqmp_firmware PD_ETH_2>; }; gem3: ethernet@ff0e0000 { - compatible = "cdns,zynqmp-gem"; + compatible = "cdns,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 63 4>, <0 63 4>; @@ -588,6 +619,7 @@ #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x877>; + power-domains = <&zynqmp_firmware PD_ETH_3>; }; gpio: gpio@ff0a0000 { @@ -600,6 +632,7 @@ #interrupt-cells = <2>; reg = <0x0 0xff0a0000 0x0 0x1000>; gpio-controller; + power-domains = <&zynqmp_firmware PD_GPIO>; }; i2c0: i2c@ff020000 { @@ -610,6 +643,7 @@ reg = <0x0 0xff020000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; + power-domains = <&zynqmp_firmware PD_I2C_0>; }; i2c1: i2c@ff030000 { @@ -620,6 +654,7 @@ reg = <0x0 0xff030000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; + power-domains = <&zynqmp_firmware PD_I2C_1>; }; ocm: memory-controller@ff960000 { @@ -658,6 +693,7 @@ <0x0 0x0 0x0 0x2 &pcie_intc 0x2>, <0x0 0x0 0x0 0x3 &pcie_intc 0x3>, <0x0 0x0 0x0 0x4 &pcie_intc 0x4>; + power-domains = <&zynqmp_firmware PD_PCIE>; pcie_intc: legacy-interrupt-controller { interrupt-controller; #address-cells = <0>; @@ -679,6 +715,7 @@ #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x873>; + power-domains = <&zynqmp_firmware PD_QSPI>; }; rtc: rtc@ffa60000 { @@ -700,10 +737,18 @@ reg-names = "serdes", "siou", "lpd"; nvmem-cells = <&soc_revision>; nvmem-cell-names = "soc_revision"; - resets = <&rst 16>, <&rst 59>, <&rst 60>, - <&rst 61>, <&rst 62>, <&rst 63>, - <&rst 64>, <&rst 3>, <&rst 29>, - <&rst 30>, <&rst 31>, <&rst 32>; + resets = <&zynqmp_reset ZYNQMP_RESET_SATA>, + <&zynqmp_reset ZYNQMP_RESET_USB0_CORERESET>, + <&zynqmp_reset ZYNQMP_RESET_USB1_CORERESET>, + <&zynqmp_reset ZYNQMP_RESET_USB0_HIBERRESET>, + <&zynqmp_reset ZYNQMP_RESET_USB1_HIBERRESET>, + <&zynqmp_reset ZYNQMP_RESET_USB0_APB>, + <&zynqmp_reset ZYNQMP_RESET_USB1_APB>, + <&zynqmp_reset ZYNQMP_RESET_DP>, + <&zynqmp_reset ZYNQMP_RESET_GEM0>, + <&zynqmp_reset ZYNQMP_RESET_GEM1>, + <&zynqmp_reset ZYNQMP_RESET_GEM2>, + <&zynqmp_reset ZYNQMP_RESET_GEM3>; reset-names = "sata_rst", "usb0_crst", "usb1_crst", "usb0_hibrst", "usb1_hibrst", "usb0_apbrst", "usb1_apbrst", "dp_rst", "gem0_rst", @@ -728,6 +773,7 @@ reg = <0x0 0xfd0c0000 0x0 0x2000>; interrupt-parent = <&gic>; interrupts = <0 133 4>; + power-domains = <&zynqmp_firmware PD_SATA>; #stream-id-cells = <4>; iommus = <&smmu 0x4c0>, <&smmu 0x4c1>, <&smmu 0x4c2>, <&smmu 0x4c3>; @@ -745,6 +791,7 @@ xlnx,device_id = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x870>; + power-domains = <&zynqmp_firmware PD_SD_0>; nvmem-cells = <&soc_revision>; nvmem-cell-names = "soc_revision"; }; @@ -760,6 +807,7 @@ xlnx,device_id = <1>; #stream-id-cells = <1>; iommus = <&smmu 0x871>; + power-domains = <&zynqmp_firmware PD_SD_1>; nvmem-cells = <&soc_revision>; nvmem-cell-names = "soc_revision"; }; @@ -793,6 +841,7 @@ clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; + power-domains = <&zynqmp_firmware PD_SPI_0>; }; spi1: spi@ff050000 { @@ -804,6 +853,7 @@ clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; + power-domains = <&zynqmp_firmware PD_SPI_1>; }; ttc0: timer@ff110000 { @@ -813,6 +863,7 @@ interrupts = <0 36 4>, <0 37 4>, <0 38 4>; reg = <0x0 0xff110000 0x0 0x1000>; timer-width = <32>; + power-domains = <&zynqmp_firmware PD_TTC_0>; }; ttc1: timer@ff120000 { @@ -822,6 +873,7 @@ interrupts = <0 39 4>, <0 40 4>, <0 41 4>; reg = <0x0 0xff120000 0x0 0x1000>; timer-width = <32>; + power-domains = <&zynqmp_firmware PD_TTC_1>; }; ttc2: timer@ff130000 { @@ -831,6 +883,7 @@ interrupts = <0 42 4>, <0 43 4>, <0 44 4>; reg = <0x0 0xff130000 0x0 0x1000>; timer-width = <32>; + power-domains = <&zynqmp_firmware PD_TTC_2>; }; ttc3: timer@ff140000 { @@ -840,6 +893,7 @@ interrupts = <0 45 4>, <0 46 4>, <0 47 4>; reg = <0x0 0xff140000 0x0 0x1000>; timer-width = <32>; + power-domains = <&zynqmp_firmware PD_TTC_3>; }; uart0: serial@ff000000 { @@ -850,6 +904,7 @@ interrupts = <0 21 4>; reg = <0x0 0xff000000 0x0 0x1000>; clock-names = "uart_clk", "pclk"; + power-domains = <&zynqmp_firmware PD_UART_0>; }; uart1: serial@ff010000 { @@ -860,6 +915,7 @@ interrupts = <0 22 4>; reg = <0x0 0xff010000 0x0 0x1000>; clock-names = "uart_clk", "pclk"; + power-domains = <&zynqmp_firmware PD_UART_1>; }; usb0: usb0@ff9d0000 { @@ -869,6 +925,7 @@ compatible = "xlnx,zynqmp-dwc3"; reg = <0x0 0xff9d0000 0x0 0x100>; clock-names = "bus_clk", "ref_clk"; + power-domains = <&zynqmp_firmware PD_USB_0>; ranges; nvmem-cells = <&soc_revision>; nvmem-cell-names = "soc_revision"; @@ -894,6 +951,7 @@ compatible = "xlnx,zynqmp-dwc3"; reg = <0x0 0xff9e0000 0x0 0x100>; clock-names = "bus_clk", "ref_clk"; + power-domains = <&zynqmp_firmware PD_USB_1>; ranges; nvmem-cells = <&soc_revision>; nvmem-cell-names = "soc_revision"; @@ -922,6 +980,15 @@ reset-on-timeout; }; + lpd_watchdog: watchdog@ff150000 { + compatible = "cdns,wdt-r1p2"; + status = "disabled"; + interrupt-parent = <&gic>; + interrupts = <0 52 1>; + reg = <0x0 0xff150000 0x0 0x1000>; + timeout-sec = <10>; + }; + xilinx_ams: ams@ffa50000 { compatible = "xlnx,zynqmp-ams"; status = "disabled"; @@ -986,6 +1053,7 @@ interrupts = <0 122 4>; interrupt-parent = <&gic>; clock-names = "axi_clk"; + power-domains = <&zynqmp_firmware PD_DP>; dma-channels = <6>; #dma-cells = <1>; dma-video0channel { diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index 3a59abb..862ec2e 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -409,6 +409,12 @@ struct ccsr_gur { #define SCFG_SNPCNFGCR_SECWRSNP 0x40000000 #define SCFG_SNPCNFGCR_SATARDSNP 0x00800000 #define SCFG_SNPCNFGCR_SATAWRSNP 0x00400000 +#define SCFG_SNPCNFGCR_USB1RDSNP 0x00200000 +#define SCFG_SNPCNFGCR_USB1WRSNP 0x00100000 +#define SCFG_SNPCNFGCR_USB2RDSNP 0x00008000 +#define SCFG_SNPCNFGCR_USB2WRSNP 0x00010000 +#define SCFG_SNPCNFGCR_USB3RDSNP 0x00002000 +#define SCFG_SNPCNFGCR_USB3WRSNP 0x00004000 /* RGMIIPCR bit definitions*/ #define SCFG_RGMIIPCR_EN_AUTO BIT(3) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h index 234440b..35719d7 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright 2017 NXP + * Copyright 2017-2019 NXP * Copyright 2015 Freescale Semiconductor */ @@ -83,6 +83,9 @@ enum boot_src get_boot_src(void); /* LS1043A/LS1023A 23x23 package silicon has different value of VAR_PER */ #define SVR_LS1043A_P23 0x879202 #define SVR_LS1023A_P23 0x87920A +#define SVR_LS1017A 0x870B24 +#define SVR_LS1018A 0x870B20 +#define SVR_LS1027A 0x870B04 #define SVR_LS1028A 0x870B00 #define SVR_LS1046A 0x870700 #define SVR_LS1026A 0x870708 @@ -100,9 +103,9 @@ enum boot_src get_boot_src(void); #define SVR_LS2044A 0x870930 #define SVR_LS2081A 0x870918 #define SVR_LS2041A 0x870914 -#define SVR_LX2160A 0x873601 -#define SVR_LX2120A 0x873621 -#define SVR_LX2080A 0x873603 +#define SVR_LX2160A 0x873600 +#define SVR_LX2120A 0x873620 +#define SVR_LX2080A 0x873602 #define SVR_MAJ(svr) (((svr) >> 4) & 0xf) #define SVR_MIN(svr) (((svr) >> 0) & 0xf) @@ -112,6 +115,9 @@ enum boot_src get_boot_src(void); #ifdef CONFIG_ARCH_LX2160A #define IS_C_PROCESSOR(svr) (!((svr >> 12) & 0x1)) #endif +#ifdef CONFIG_ARCH_LS1028A +#define IS_MULTIMEDIA_EN(svr) (!((svr >> 10) & 0x1)) +#endif #define IS_SVR_REV(svr, maj, min) \ ((SVR_MAJ(svr) == (maj)) && (SVR_MIN(svr) == (min))) #define SVR_DEV(svr) ((svr) >> 8) diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h index 137cd61..f2ba182 100644 --- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h @@ -155,7 +155,7 @@ struct ccsr_gur { #define SCFG_ETSECCMCR_GE0_CLK125 0x00000000 #define SCFG_ETSECCMCR_GE1_CLK125 0x08000000 #define SCFG_PIXCLKCR_PXCKEN 0x80000000 -#define SCFG_QSPI_CLKSEL 0xc0100000 +#define SCFG_QSPI_CLKSEL 0x50100000 #define SCFG_SNPCNFGCR_SEC_RD_WR 0xc0000000 #define SCFG_SNPCNFGCR_DCU_RD_WR 0x03000000 #define SCFG_SNPCNFGCR_SATA_RD_WR 0x00c00000 diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h index 0a1da02..49a8a66 100644 --- a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h +++ b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h @@ -315,6 +315,7 @@ struct dram_para { u8 cols; u8 rows; u8 ranks; + u8 bus_full_width; const u8 dx_read_delays[NR_OF_BYTE_LANES][RD_LINES_PER_BYTE_LANE]; const u8 dx_write_delays[NR_OF_BYTE_LANES][WR_LINES_PER_BYTE_LANE]; }; diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h index 40a3f84..a646ea6 100644 --- a/arch/arm/include/asm/arch-sunxi/gpio.h +++ b/arch/arm/include/asm/arch-sunxi/gpio.h @@ -73,6 +73,9 @@ struct sunxi_gpio_reg { struct sunxi_gpio_int gpio_int; }; +#define SUN50I_H6_GPIO_POW_MOD_SEL 0x340 +#define SUN50I_H6_GPIO_POW_MOD_VAL 0x348 + #define BANK_TO_GPIO(bank) (((bank) < SUNXI_GPIO_L) ? \ &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank] : \ &((struct sunxi_gpio_reg *)SUNXI_R_PIO_BASE)->gpio_bank[(bank) - SUNXI_GPIO_L]) diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c index 1638f1e..488358a 100644 --- a/arch/arm/lib/bootm.c +++ b/arch/arm/lib/bootm.c @@ -224,6 +224,8 @@ static void do_nonsec_virt_switch(void) } #endif +__weak void board_prep_linux(bootm_headers_t *images) { } + /* Subcommand: PREP */ static void boot_prep_linux(bootm_headers_t *images) { @@ -270,6 +272,8 @@ static void boot_prep_linux(bootm_headers_t *images) printf("FDT and ATAGS support not compiled in - hanging\n"); hang(); } + + board_prep_linux(images); } __weak bool armv7_boot_nonsec_default(void) diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c index f8274b3..bf631b7 100644 --- a/arch/arm/mach-k3/common.c +++ b/arch/arm/mach-k3/common.c @@ -233,3 +233,14 @@ int print_cpuinfo(void) return 0; } #endif + +#ifdef CONFIG_ARM64 +void board_prep_linux(bootm_headers_t *images) +{ + debug("Linux kernel Image start = 0x%lx end = 0x%lx\n", + images->os.start, images->os.end); + __asm_flush_dcache_range(images->os.start, + ROUND(images->os.end, + CONFIG_SYS_CACHELINE_SIZE)); +} +#endif diff --git a/arch/arm/mach-k3/j721e_init.c b/arch/arm/mach-k3/j721e_init.c index 733e414..5e38132 100644 --- a/arch/arm/mach-k3/j721e_init.c +++ b/arch/arm/mach-k3/j721e_init.c @@ -73,7 +73,7 @@ static void store_boot_index_from_rom(void) void board_init_f(ulong dummy) { -#if defined(CONFIG_K3_LOAD_SYSFW) +#if defined(CONFIG_K3_J721E_DDRSS) || defined(CONFIG_K3_LOAD_SYSFW) struct udevice *dev; int ret; #endif @@ -117,6 +117,12 @@ void board_init_f(ulong dummy) /* Prepare console output */ preloader_console_init(); #endif + +#if defined(CONFIG_K3_J721E_DDRSS) + ret = uclass_get_device(UCLASS_RAM, 0, &dev); + if (ret) + panic("DRAM init failed: %d\n", ret); +#endif } u32 spl_boot_mode(const u32 boot_device) diff --git a/arch/arm/mach-keystone/include/mach/psc_defs.h b/arch/arm/mach-keystone/include/mach/psc_defs.h index dfc22d5..f164f95 100644 --- a/arch/arm/mach-keystone/include/mach/psc_defs.h +++ b/arch/arm/mach-keystone/include/mach/psc_defs.h @@ -94,7 +94,7 @@ static inline u32 boot_set_bitfield(u32 z, u32 f, u32 x, u32 y) * Timeout limit on checking PTSTAT. This is the number of times the * wait function will be called before giving up. */ -#define PSC_PTSTAT_TIMEOUT_LIMIT 100 +#define PSC_PTSTAT_TIMEOUT_LIMIT 100000 u32 psc_get_domain_num(u32 mod_num); int psc_enable_module(u32 mod_num); diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-mvebu/Makefile index 8228a17..b739520 100644 --- a/arch/arm/mach-mvebu/Makefile +++ b/arch/arm/mach-mvebu/Makefile @@ -58,10 +58,10 @@ KWB_REPLACE += SEC_FUSE_DUMP KWB_CFG_SEC_FUSE_DUMP = a38x endif -$(src)/kwbimage.cfg: $(src)/kwbimage.cfg.in include/autoconf.mk \ +$(obj)/kwbimage.cfg: $(src)/kwbimage.cfg.in include/autoconf.mk \ include/config/auto.conf $(Q)sed -ne '$(foreach V,$(KWB_REPLACE),s/^#@$(V)/$(V) $(KWB_CFG_$(V))/;)p' \ - <$< >$(dir $<)$(@F) + <$< >$(dir $@)$(@F) endif # CONFIG_SPL_BUILD obj-y += gpio.o diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index ffdf09f..16d41b8 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -275,7 +275,10 @@ config MACH_SUN9I config MACH_SUN50I bool "sun50i (Allwinner A64)" select ARM64 + select SPI select DM_I2C + select DM_SPI if SPI + select DM_SPI_FLASH select PHY_SUN4I_USB select SUN6I_PRCM select SUNXI_DE2 diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c index 8e9bb63..db50636 100644 --- a/arch/arm/mach-sunxi/board.c +++ b/arch/arm/mach-sunxi/board.c @@ -65,6 +65,7 @@ struct mm_region *mem_map = sunxi_mem_map; static int gpio_init(void) { + __maybe_unused uint val; #if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F) #if defined(CONFIG_MACH_SUN4I) || \ defined(CONFIG_MACH_SUN7I) || \ @@ -139,6 +140,14 @@ static int gpio_init(void) #error Unsupported console port number. Please fix pin mux settings in board.c #endif +#ifdef CONFIG_MACH_SUN50I_H6 + /* Update PIO power bias configuration by copy hardware detected value */ + val = readl(SUNXI_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_VAL); + writel(val, SUNXI_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_SEL); + val = readl(SUNXI_R_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_VAL); + writel(val, SUNXI_R_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_SEL); +#endif + return 0; } diff --git a/arch/arm/mach-sunxi/clock_sun6i.c b/arch/arm/mach-sunxi/clock_sun6i.c index 1628f3a..6ca38f7 100644 --- a/arch/arm/mach-sunxi/clock_sun6i.c +++ b/arch/arm/mach-sunxi/clock_sun6i.c @@ -118,7 +118,7 @@ void clock_set_pll1(unsigned int clk) if (clk > 1152000000) { k = 2; } else if (clk > 768000000) { - k = 3; + k = 4; m = 2; } diff --git a/arch/arm/mach-sunxi/dram_sun50i_h6.c b/arch/arm/mach-sunxi/dram_sun50i_h6.c index 2a8275d..9375db7 100644 --- a/arch/arm/mach-sunxi/dram_sun50i_h6.c +++ b/arch/arm/mach-sunxi/dram_sun50i_h6.c @@ -201,6 +201,9 @@ static void mctl_set_addrmap(struct dram_para *para) u8 rows = para->rows; u8 ranks = para->ranks; + if (!para->bus_full_width) + cols -= 1; + /* Ranks */ if (ranks == 2) mctl_ctl->addrmap[0] = rows + cols - 3; @@ -213,6 +216,10 @@ static void mctl_set_addrmap(struct dram_para *para) /* Columns */ mctl_ctl->addrmap[2] = 0; switch (cols) { + case 7: + mctl_ctl->addrmap[3] = 0x1F1F1F00; + mctl_ctl->addrmap[4] = 0x1F1F; + break; case 8: mctl_ctl->addrmap[3] = 0x1F1F0000; mctl_ctl->addrmap[4] = 0x1F1F; @@ -300,13 +307,16 @@ static void mctl_com_init(struct dram_para *para) reg_val = 0x3f00; clrsetbits_le32(&mctl_com->unk_0x008, 0x3f00, reg_val); - /* TODO: half DQ, DDR4 */ - reg_val = MSTR_BUSWIDTH_FULL | MSTR_BURST_LENGTH(8) | - MSTR_ACTIVE_RANKS(para->ranks); + /* TODO: DDR4 */ + reg_val = MSTR_BURST_LENGTH(8) | MSTR_ACTIVE_RANKS(para->ranks); if (para->type == SUNXI_DRAM_TYPE_LPDDR3) reg_val |= MSTR_DEVICETYPE_LPDDR3; if (para->type == SUNXI_DRAM_TYPE_DDR3) reg_val |= MSTR_DEVICETYPE_DDR3 | MSTR_2TMODE; + if (para->bus_full_width) + reg_val |= MSTR_BUSWIDTH_FULL; + else + reg_val |= MSTR_BUSWIDTH_HALF; writel(reg_val | BIT(31), &mctl_ctl->mstr); if (para->type == SUNXI_DRAM_TYPE_LPDDR3) @@ -333,7 +343,10 @@ static void mctl_com_init(struct dram_para *para) } writel(reg_val, &mctl_ctl->odtcfg); - /* TODO: half DQ */ + if (!para->bus_full_width) { + writel(0x0, &mctl_phy->dx[2].gcr[0]); + writel(0x0, &mctl_phy->dx[3].gcr[0]); + } } static void mctl_bit_delay_set(struct dram_para *para) @@ -514,22 +527,35 @@ static void mctl_channel_init(struct dram_para *para) if (readl(&mctl_phy->pgsr[0]) & 0x400000) { - /* - * Detect single rank. - * TODO: also detect half DQ. - */ + /* Check for single rank and optionally half DQ. */ if ((readl(&mctl_phy->dx[0].rsr[0]) & 0x3) == 2 && - (readl(&mctl_phy->dx[1].rsr[0]) & 0x3) == 2 && - (readl(&mctl_phy->dx[2].rsr[0]) & 0x3) == 2 && - (readl(&mctl_phy->dx[3].rsr[0]) & 0x3) == 2) { + (readl(&mctl_phy->dx[1].rsr[0]) & 0x3) == 2) { para->ranks = 1; + + if ((readl(&mctl_phy->dx[2].rsr[0]) & 0x3) != 2 || + (readl(&mctl_phy->dx[3].rsr[0]) & 0x3) != 2) + para->bus_full_width = 0; + /* Restart DRAM initialization from scratch. */ mctl_core_init(para); return; } - else { - panic("This DRAM setup is currently not supported.\n"); + + /* + * Check for dual rank and half DQ. NOTE: This combination + * is highly unlikely and was not tested. Condition is the + * same as in libdram, though. + */ + if ((readl(&mctl_phy->dx[0].rsr[0]) & 0x3) == 0 && + (readl(&mctl_phy->dx[1].rsr[0]) & 0x3) == 0) { + para->bus_full_width = 0; + + /* Restart DRAM initialization from scratch. */ + mctl_core_init(para); + return; } + + panic("This DRAM setup is currently not supported.\n"); } if (readl(&mctl_phy->pgsr[0]) & 0xff00000) { @@ -557,11 +583,8 @@ static void mctl_channel_init(struct dram_para *para) static void mctl_auto_detect_dram_size(struct dram_para *para) { - /* TODO: non-LPDDR3, half DQ */ - /* - * Detect rank number by the code in mctl_channel_init. Furtherly - * when DQ detection is available it will also be executed there. - */ + /* TODO: non-(LP)DDR3 */ + /* Detect rank number and half DQ by the code in mctl_channel_init. */ mctl_core_init(para); /* detect row address bits */ @@ -570,8 +593,9 @@ static void mctl_auto_detect_dram_size(struct dram_para *para) mctl_core_init(para); for (para->rows = 13; para->rows < 18; para->rows++) { - /* 8 banks, 8 bit per byte and 32 bit width */ - if (mctl_mem_matches((1 << (para->rows + para->cols + 5)))) + /* 8 banks, 8 bit per byte and 16/32 bit width */ + if (mctl_mem_matches((1 << (para->rows + para->cols + + 4 + para->bus_full_width)))) break; } @@ -580,18 +604,21 @@ static void mctl_auto_detect_dram_size(struct dram_para *para) mctl_core_init(para); for (para->cols = 8; para->cols < 11; para->cols++) { - /* 8 bits per byte and 32 bit width */ - if (mctl_mem_matches(1 << (para->cols + 2))) + /* 8 bits per byte and 16/32 bit width */ + if (mctl_mem_matches(1 << (para->cols + 1 + + para->bus_full_width))) break; } } unsigned long mctl_calc_size(struct dram_para *para) { - /* TODO: non-LPDDR3, half DQ */ + u8 width = para->bus_full_width ? 4 : 2; + + /* TODO: non-(LP)DDR3 */ - /* 8 banks, 32-bit (4 byte) data width */ - return (1ULL << (para->cols + para->rows + 3)) * 4 * para->ranks; + /* 8 banks */ + return (1ULL << (para->cols + para->rows + 3)) * width * para->ranks; } #define SUN50I_H6_LPDDR3_DX_WRITE_DELAYS \ @@ -625,6 +652,7 @@ unsigned long sunxi_dram_init(void) .ranks = 2, .cols = 11, .rows = 14, + .bus_full_width = 1, #ifdef CONFIG_SUNXI_DRAM_H6_LPDDR3 .type = SUNXI_DRAM_TYPE_LPDDR3, .dx_read_delays = SUN50I_H6_LPDDR3_DX_READ_DELAYS, diff --git a/arch/arm/mach-versal/cpu.c b/arch/arm/mach-versal/cpu.c index 49f1e51..6ee6cd4 100644 --- a/arch/arm/mach-versal/cpu.c +++ b/arch/arm/mach-versal/cpu.c @@ -107,28 +107,3 @@ int reserve_mmu(void) return 0; } #endif - -int versal_pm_request(u32 api_id, u32 arg0, u32 arg1, u32 arg2, - u32 arg3, u32 *ret_payload) -{ - struct pt_regs regs; - - if (current_el() == 3) - return 0; - - regs.regs[0] = PM_SIP_SVC | api_id; - regs.regs[1] = ((u64)arg1 << 32) | arg0; - regs.regs[2] = ((u64)arg3 << 32) | arg2; - - smc_call(®s); - - if (ret_payload) { - ret_payload[0] = (u32)regs.regs[0]; - ret_payload[1] = upper_32_bits(regs.regs[0]); - ret_payload[2] = (u32)regs.regs[1]; - ret_payload[3] = upper_32_bits(regs.regs[1]); - ret_payload[4] = (u32)regs.regs[2]; - } - - return regs.regs[0]; -} diff --git a/arch/arm/mach-versal/include/mach/sys_proto.h b/arch/arm/mach-versal/include/mach/sys_proto.h index 2f5ad02..31af049 100644 --- a/arch/arm/mach-versal/include/mach/sys_proto.h +++ b/arch/arm/mach-versal/include/mach/sys_proto.h @@ -8,65 +8,7 @@ enum { TCM_SPLIT, }; -enum pm_api_id { - PM_GET_API_VERSION = 1, - PM_SET_CONFIGURATION, - PM_GET_NODE_STATUS, - PM_GET_OPERATING_CHARACTERISTIC, - PM_REGISTER_NOTIFIER, - PM_REQUEST_SUSPEND, - PM_SELF_SUSPEND, - PM_FORCE_POWERDOWN, - PM_ABORT_SUSPEND, - PM_REQUEST_WAKEUP, - PM_SET_WAKEUP_SOURCE, - PM_SYSTEM_SHUTDOWN, - PM_REQUEST_NODE, - PM_RELEASE_NODE, - PM_SET_REQUIREMENT, - PM_SET_MAX_LATENCY, - PM_RESET_ASSERT, - PM_RESET_GET_STATUS, - PM_MMIO_WRITE, - PM_MMIO_READ, - PM_PM_INIT_FINALIZE, - PM_FPGA_LOAD, - PM_FPGA_GET_STATUS, - PM_GET_CHIPID, - PM_SECURE_SHA = 26, - PM_SECURE_RSA, - PM_PINCTRL_REQUEST, - PM_PINCTRL_RELEASE, - PM_PINCTRL_GET_FUNCTION, - PM_PINCTRL_SET_FUNCTION, - PM_PINCTRL_CONFIG_PARAM_GET, - PM_PINCTRL_CONFIG_PARAM_SET, - PM_IOCTL, - PM_QUERY_DATA, - PM_CLOCK_ENABLE, - PM_CLOCK_DISABLE, - PM_CLOCK_GETSTATE, - PM_CLOCK_SETDIVIDER, - PM_CLOCK_GETDIVIDER, - PM_CLOCK_SETRATE, - PM_CLOCK_GETRATE, - PM_CLOCK_SETPARENT, - PM_CLOCK_GETPARENT, - PM_SECURE_IMAGE, - PM_FPGA_READ = 46, - PM_SECURE_AES, - PM_CLOCK_PLL_GETPARAM = 49, - PM_REGISTER_ACCESS = 52, - PM_EFUSE_ACCESS, - PM_FEATURE_CHECK = 63, - PM_API_MAX, -}; - -#define PM_SIP_SVC 0xC2000000 #define PAYLOAD_ARG_CNT 4U void tcm_init(u8 mode); void mem_map_fill(void); - -int versal_pm_request(u32 api_id, u32 arg0, u32 arg1, u32 arg2, - u32 arg3, u32 *ret_payload); diff --git a/arch/arm/mach-zynqmp/cpu.c b/arch/arm/mach-zynqmp/cpu.c index bb21cbc..b90d08b 100644 --- a/arch/arm/mach-zynqmp/cpu.c +++ b/arch/arm/mach-zynqmp/cpu.c @@ -151,35 +151,6 @@ unsigned int zynqmp_get_silicon_version(void) return ZYNQMP_CSU_VERSION_SILICON; } -#define ZYNQMP_MMIO_READ 0xC2000014 -#define ZYNQMP_MMIO_WRITE 0xC2000013 - -int __maybe_unused invoke_smc(u32 pm_api_id, u32 arg0, u32 arg1, u32 arg2, - u32 arg3, u32 *ret_payload) -{ - /* - * Added SIP service call Function Identifier - * Make sure to stay in x0 register - */ - struct pt_regs regs; - - regs.regs[0] = pm_api_id; - regs.regs[1] = ((u64)arg1 << 32) | arg0; - regs.regs[2] = ((u64)arg3 << 32) | arg2; - - smc_call(®s); - - if (ret_payload != NULL) { - ret_payload[0] = (u32)regs.regs[0]; - ret_payload[1] = upper_32_bits(regs.regs[0]); - ret_payload[2] = (u32)regs.regs[1]; - ret_payload[3] = upper_32_bits(regs.regs[1]); - ret_payload[4] = (u32)regs.regs[2]; - } - - return regs.regs[0]; -} - static int zynqmp_mmio_rawwrite(const u32 address, const u32 mask, const u32 value) @@ -211,28 +182,34 @@ int zynqmp_mmio_write(const u32 address, { if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3) return zynqmp_mmio_rawwrite(address, mask, value); +#if defined(CONFIG_ZYNQMP_FIRMWARE) else - return invoke_smc(ZYNQMP_MMIO_WRITE, address, mask, - value, 0, NULL); + return xilinx_pm_request(PM_MMIO_WRITE, address, mask, + value, 0, NULL); +#endif return -EINVAL; } int zynqmp_mmio_read(const u32 address, u32 *value) { - u32 ret_payload[PAYLOAD_ARG_CNT]; - u32 ret; + u32 ret = -EINVAL; if (!value) - return -EINVAL; + return ret; if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3) { ret = zynqmp_mmio_rawread(address, value); - } else { - ret = invoke_smc(ZYNQMP_MMIO_READ, address, 0, 0, - 0, ret_payload); + } +#if defined(CONFIG_ZYNQMP_FIRMWARE) + else { + u32 ret_payload[PAYLOAD_ARG_CNT]; + + ret = xilinx_pm_request(PM_MMIO_READ, address, 0, 0, + 0, ret_payload); *value = ret_payload[1]; } +#endif return ret; } diff --git a/arch/arm/mach-zynqmp/include/mach/sys_proto.h b/arch/arm/mach-zynqmp/include/mach/sys_proto.h index 69e729f..10b7076 100644 --- a/arch/arm/mach-zynqmp/include/mach/sys_proto.h +++ b/arch/arm/mach-zynqmp/include/mach/sys_proto.h @@ -50,8 +50,6 @@ void handoff_setup(void); int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value); int zynqmp_mmio_read(const u32 address, u32 *value); -int invoke_smc(u32 pm_api_id, u32 arg0, u32 arg1, u32 arg2, u32 arg3, - u32 *ret_payload); void initialize_tcm(bool mode); void mem_map_fill(void); diff --git a/arch/microblaze/cpu/start.S b/arch/microblaze/cpu/start.S index 22903e3..cbec299 100644 --- a/arch/microblaze/cpu/start.S +++ b/arch/microblaze/cpu/start.S @@ -244,7 +244,7 @@ relocate_code: bneid r12, 1b addi r5, r5, 4 /* Increment to next loc - relocate code */ - /* R23 points to the base address. */ + /* R23 points to the base address. */ add r23, r0, r7 /* Move reloc addr to r23 */ addi r24, r0, CONFIG_SYS_TEXT_BASE /* Get reloc offset */ rsub r23, r24, r23 /* keep - this is already here gd->reloc_off */ diff --git a/arch/microblaze/lib/bootm.c b/arch/microblaze/lib/bootm.c index 11e5347..01c5d57 100644 --- a/arch/microblaze/lib/bootm.c +++ b/arch/microblaze/lib/bootm.c @@ -66,12 +66,15 @@ static void boot_jump_linux(bootm_headers_t *images, int flag) thekernel = (void (*)(char *, ulong, ulong))images->ep; -#ifdef DEBUG - printf("## Transferring control to Linux (at address 0x%08lx) ", - (ulong)thekernel); - printf("cmdline 0x%08lx, ramdisk 0x%08lx, FDT 0x%08lx...\n", - cmdline, rd_start, dt); -#endif + debug("## Transferring control to Linux (at address 0x%08lx) ", + (ulong)thekernel); + debug("cmdline 0x%08lx, ramdisk 0x%08lx, FDT 0x%08lx...\n", + cmdline, rd_start, dt); + bootstage_mark(BOOTSTAGE_ID_RUN_OS); + + printf("\nStarting kernel ...%s\n\n", fake ? + "(fake run for tracing)" : ""); + bootstage_mark_name(BOOTSTAGE_ID_BOOTM_HANDOFF, "start_kernel"); #ifdef XILINX_USE_DCACHE flush_cache(0, XILINX_DCACHE_BYTE_SIZE); @@ -92,7 +95,7 @@ static void boot_jump_linux(bootm_headers_t *images, int flag) static void boot_prep_linux(bootm_headers_t *images) { if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len) { - printf("using: FDT\n"); + debug("using: FDT\n"); if (image_setup_linux(images)) { printf("FDT creation failed! hanging..."); hang(); diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index e3e7945..eb1f67d 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -76,12 +76,18 @@ config ARCH_BMIPS config ARCH_MTMIPS bool "Support MediaTek MIPS platforms" + select CLK imply CMD_DM select DISPLAY_CPUINFO select DM imply DM_ETH imply DM_GPIO + select DM_RESET select DM_SERIAL + select PINCTRL + select PINMUX + select PINCONF + select RESET_MTMIPS imply DM_SPI imply DM_SPI_FLASH select LAST_STAGE_INIT @@ -408,9 +414,17 @@ config SYS_ICACHE_LINE_SIZE help The size of L1 Icache lines, if known at compile time. +config SYS_SCACHE_LINE_SIZE + int + default 0 + help + The size of L2 cache lines, if known at compile time. + + config SYS_CACHE_SIZE_AUTO def_bool y if SYS_DCACHE_SIZE = 0 && SYS_ICACHE_SIZE = 0 && \ - SYS_DCACHE_LINE_SIZE = 0 && SYS_ICACHE_LINE_SIZE = 0 + SYS_DCACHE_LINE_SIZE = 0 && SYS_ICACHE_LINE_SIZE = 0 && \ + SYS_SCACHE_LINE_SIZE = 0 help Select this (or let it be auto-selected by not defining any cache sizes) in order to allow U-Boot to automatically detect the sizes diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile index e2de1da..c9d7559 100644 --- a/arch/mips/dts/Makefile +++ b/arch/mips/dts/Makefile @@ -10,6 +10,7 @@ dtb-$(CONFIG_TARGET_BOSTON) += img,boston.dtb dtb-$(CONFIG_TARGET_MALTA) += mti,malta.dtb dtb-$(CONFIG_TARGET_PIC32MZDASK) += pic32mzda_sk.dtb dtb-$(CONFIG_TARGET_XILFPGA) += nexys4ddr.dtb +dtb-$(CONFIG_BOARD_BROADCOM_BCM968380GERG) += brcm,bcm968380gerg.dtb dtb-$(CONFIG_BOARD_COMTREND_AR5315U) += comtrend,ar-5315u.dtb dtb-$(CONFIG_BOARD_COMTREND_AR5387UN) += comtrend,ar-5387un.dtb dtb-$(CONFIG_BOARD_COMTREND_CT5361) += comtrend,ct-5361.dtb @@ -19,10 +20,9 @@ dtb-$(CONFIG_BOARD_HUAWEI_HG556A) += huawei,hg556a.dtb dtb-$(CONFIG_BOARD_NETGEAR_CG3100D) += netgear,cg3100d.dtb dtb-$(CONFIG_BOARD_NETGEAR_DGND3700V2) += netgear,dgnd3700v2.dtb dtb-$(CONFIG_BOARD_SAGEM_FAST1704) += sagem,f@st1704.dtb +dtb-$(CONFIG_BOARD_SFR_NB4_SER) += sfr,nb4-ser.dtb dtb-$(CONFIG_BOARD_TPLINK_WDR4300) += tplink_wdr4300.dtb dtb-$(CONFIG_TARGET_JZ4780_CI20) += ci20.dtb -dtb-$(CONFIG_SOC_BMIPS_BCM6358) += sfr,nb4-ser.dtb -dtb-$(CONFIG_SOC_BMIPS_BCM6838) += brcm,bcm968380gerg.dtb dtb-$(CONFIG_SOC_LUTON) += luton_pcb090.dtb luton_pcb091.dtb dtb-$(CONFIG_SOC_OCELOT) += ocelot_pcb120.dtb ocelot_pcb123.dtb dtb-$(CONFIG_SOC_JR2) += jr2_pcb110.dtb jr2_pcb111.dtb serval2_pcb112.dtb diff --git a/arch/mips/dts/brcm,bcm63268.dtsi b/arch/mips/dts/brcm,bcm63268.dtsi index f8a72ef..5294242 100644 --- a/arch/mips/dts/brcm,bcm63268.dtsi +++ b/arch/mips/dts/brcm,bcm63268.dtsi @@ -141,6 +141,24 @@ status = "disabled"; }; + nand: nand-controller@10000200 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,nand-bcm6368", + "brcm,brcmnand-v4.0", + "brcm,brcmnand"; + reg-names = "nand", + "nand-cache", + "nand-int-base"; + reg = <0x10000200 0x180>, + <0x10000600 0x200>, + <0x100000b0 0x10>; + clocks = <&periph_clk BCM63268_CLK_NAND>; + clock-names = "nand"; + + status = "disabled"; + }; + periph_pwr: power-controller@1000184c { compatible = "brcm,bcm6328-power-domain"; reg = <0x1000184c 0x4>; diff --git a/arch/mips/dts/brcm,bcm6328.dtsi b/arch/mips/dts/brcm,bcm6328.dtsi index 50beed4..350c0e9 100644 --- a/arch/mips/dts/brcm,bcm6328.dtsi +++ b/arch/mips/dts/brcm,bcm6328.dtsi @@ -124,6 +124,22 @@ status = "disabled"; }; + nand: nand-controller@10000200 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,nand-bcm6368", + "brcm,brcmnand-v2.2", + "brcm,brcmnand"; + reg-names = "nand", + "nand-cache", + "nand-int-base"; + reg = <0x10000200 0x180>, + <0x10000400 0x200>, + <0x100000b0 0x10>; + + status = "disabled"; + }; + leds: led-controller@10000800 { compatible = "brcm,bcm6328-leds"; reg = <0x10000800 0x24>; diff --git a/arch/mips/dts/brcm,bcm6362.dtsi b/arch/mips/dts/brcm,bcm6362.dtsi index c77b80a..71598f9 100644 --- a/arch/mips/dts/brcm,bcm6362.dtsi +++ b/arch/mips/dts/brcm,bcm6362.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2018 Ãlvaro Fernández Rojas <noltari@gmail.com> + * Copyright (C) 2018 Álvaro Fernández Rojas <noltari@gmail.com> */ #include <dt-bindings/clock/bcm6362-clock.h> @@ -135,6 +135,24 @@ status = "disabled"; }; + nand: nand-controller@10000200 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,nand-bcm6368", + "brcm,brcmnand-v2.2", + "brcm,brcmnand"; + reg-names = "nand", + "nand-cache", + "nand-int-base"; + reg = <0x10000200 0x180>, + <0x10000600 0x200>, + <0x100000b0 0x10>; + clocks = <&periph_clk BCM6362_CLK_NAND>; + clock-names = "nand"; + + status = "disabled"; + }; + lsspi: spi@10000800 { compatible = "brcm,bcm6358-spi"; reg = <0x10000800 0x70c>; diff --git a/arch/mips/dts/brcm,bcm6368.dtsi b/arch/mips/dts/brcm,bcm6368.dtsi index 89590d6..69be650 100644 --- a/arch/mips/dts/brcm,bcm6368.dtsi +++ b/arch/mips/dts/brcm,bcm6368.dtsi @@ -146,6 +146,24 @@ status = "disabled"; }; + nand: nand-controller@10000200 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,nand-bcm6368", + "brcm,brcmnand-v2.1", + "brcm,brcmnand"; + reg-names = "nand", + "nand-cache", + "nand-int-base"; + reg = <0x10000200 0x180>, + <0x10000600 0x200>, + <0x100000b0 0x10>; + clocks = <&periph_clk BCM6368_CLK_NAND>; + clock-names = "nand"; + + status = "disabled"; + }; + spi: spi@10000800 { compatible = "brcm,bcm6358-spi"; reg = <0x10000800 0x70c>; diff --git a/arch/mips/dts/comtrend,vr-3032u.dts b/arch/mips/dts/comtrend,vr-3032u.dts index 512cb52..110119b 100644 --- a/arch/mips/dts/comtrend,vr-3032u.dts +++ b/arch/mips/dts/comtrend,vr-3032u.dts @@ -99,6 +99,19 @@ }; }; +&nand { + status = "okay"; + + nandcs@0 { + compatible = "brcm,nandcs"; + reg = <0>; + nand-ecc-strength = <15>; + nand-ecc-step-size = <512>; + nand-on-flash-bbt; + brcm,nand-oob-sector-size = <64>; + }; +}; + &ohci { status = "okay"; }; diff --git a/arch/mips/dts/gardena-smart-gateway-mt7688.dts b/arch/mips/dts/gardena-smart-gateway-mt7688.dts index eedde89..b7b5a24 100644 --- a/arch/mips/dts/gardena-smart-gateway-mt7688.dts +++ b/arch/mips/dts/gardena-smart-gateway-mt7688.dts @@ -85,15 +85,26 @@ }; }; +&pinctrl { + state_default: pin_state { + p0led { + groups = "p0led_a"; + function = "led"; + }; + }; +}; + &uart0 { status = "okay"; - clock-frequency = <40000000>; }; &spi0 { status = "okay"; num-cs = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&spi_dual_pins>; + spi-flash@0 { #address-cells = <1>; #size-cells = <1>; @@ -110,3 +121,9 @@ reg = <1>; }; }; + +ð { + pinctrl-names = "default"; + pinctrl-0 = <&ephy_iot_mode>; + mediatek,poll-link-phy = <0>; +}; diff --git a/arch/mips/dts/linkit-smart-7688.dts b/arch/mips/dts/linkit-smart-7688.dts index bb10402..f154aae 100644 --- a/arch/mips/dts/linkit-smart-7688.dts +++ b/arch/mips/dts/linkit-smart-7688.dts @@ -26,9 +26,17 @@ }; }; +&pinctrl { + state_default: pin_state { + p0led { + groups = "p0led_a"; + function = "led"; + }; + }; +}; + &uart2 { status = "okay"; - clock-frequency = <40000000>; }; &spi0 { @@ -43,3 +51,9 @@ reg = <0>; }; }; + +ð { + pinctrl-names = "default"; + pinctrl-0 = <&ephy_iot_mode>; + mediatek,poll-link-phy = <0>; +}; diff --git a/arch/mips/dts/mt7628a.dtsi b/arch/mips/dts/mt7628a.dtsi index 1e7d0a6..76a80c8 100644 --- a/arch/mips/dts/mt7628a.dtsi +++ b/arch/mips/dts/mt7628a.dtsi @@ -1,4 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 +#include <dt-bindings/clock/mt7628-clk.h> +#include <dt-bindings/reset/mt7628-reset.h> / { #address-cells = <1>; @@ -16,11 +18,6 @@ }; }; - resetc: reset-controller { - compatible = "ralink,rt2880-reset"; - #reset-cells = <1>; - }; - cpuintc: interrupt-controller { #address-cells = <0>; #interrupt-cells = <1>; @@ -28,6 +25,14 @@ compatible = "mti,cpu-interrupt-controller"; }; + clk48m: clk48m@0 { + compatible = "fixed-clock"; + + clock-frequency = <48000000>; + + #clock-cells = <0>; + }; + palmbus@10000000 { compatible = "palmbus", "simple-bus"; reg = <0x10000000 0x200000>; @@ -48,11 +53,175 @@ mask = <0x1>; }; + clkctrl: clkctrl@0x2c { + reg = <0x2c 0x8>, <0x10 0x4>; + reg-names = "syscfg0", "clkcfg"; + compatible = "mediatek,mt7628-clk"; + #clock-cells = <1>; + u-boot,dm-pre-reloc; + }; + + rstctrl: rstctrl@0x34 { + reg = <0x34 0x4>; + compatible = "mediatek,mtmips-reset"; + #reset-cells = <1>; + }; + + pinctrl: pinctrl@60 { + compatible = "mediatek,mt7628-pinctrl"; + reg = <0x3c 0x2c>, <0x1300 0x100>; + reg-names = "gpiomode", "padconf"; + + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pin_state { + }; + + spi_single_pins: spi_single_pins { + groups = "spi"; + function = "spi"; + }; + + spi_dual_pins: spi_dual_pins { + spi_master_pins { + groups = "spi"; + function = "spi"; + }; + + spi_cs1_pin { + groups = "spi cs1"; + function = "spi cs1"; + }; + }; + + uart0_pins: uart0_pins { + groups = "uart0"; + function = "uart0"; + }; + + uart1_pins: uart1_pins { + groups = "uart1"; + function = "uart1"; + }; + + uart2_pins: uart2_pins { + groups = "uart2"; + function = "uart2"; + }; + + i2c_pins: i2c_pins { + groups = "i2c"; + function = "i2c"; + }; + + ephy_iot_mode: ephy_iot_mode { + ephy4_1_dis { + groups = "ephy4_1_pad"; + function = "digital"; + }; + + ephy0_en { + groups = "ephy0"; + function = "enable"; + }; + }; + + ephy_router_mode: ephy_router_mode { + ephy4_1_en { + groups = "ephy4_1_pad"; + function = "analog"; + }; + + ephy0_en { + groups = "ephy0"; + function = "enable"; + }; + }; + + sd_iot_mode: sd_iot_mode { + ephy4_1_dis { + groups = "ephy4_1_pad"; + function = "digital"; + }; + + sdxc_en { + groups = "sdmode"; + function = "sdxc"; + }; + + sdxc_iot_mode { + groups = "sd router"; + function = "iot"; + }; + + sd_clk_pad { + pins = "sd_clk"; + drive-strength-4g = <8>; + }; + }; + + sd_router_mode: sd_router_mode { + sdxc_router_mode { + groups = "sd router"; + function = "router"; + }; + + sdxc_map_pins { + groups = "gpio0", "i2s", "sdmode", \ + "i2c", "uart1"; + function = "gpio"; + }; + + sd_clk_pad { + pins = "gpio0"; + drive-strength-28 = <8>; + }; + }; + + emmc_iot_8bit_mode: emmc_iot_8bit_mode { + ephy4_1_dis { + groups = "ephy4_1_pad"; + function = "digital"; + }; + + emmc_en { + groups = "sdmode"; + function = "sdxc"; + }; + + emmc_iot_mode { + groups = "sd router"; + function = "iot"; + }; + + emmc_d4_d5 { + groups = "uart2"; + function = "sdxc d5 d4"; + }; + + emmc_d6 { + groups = "pwm1"; + function = "sdxc d6"; + }; + + emmc_d7 { + groups = "pwm0"; + function = "sdxc d7"; + }; + + sd_clk_pad { + pins = "sd_clk"; + drive-strength-4g = <8>; + }; + }; + }; + watchdog: watchdog@100 { compatible = "ralink,mt7628a-wdt", "mediatek,mt7621-wdt"; reg = <0x100 0x30>; - resets = <&resetc 8>; + resets = <&rstctrl MT7628_TIMER_RST>; reset-names = "wdt"; interrupt-parent = <&intc>; @@ -66,7 +235,7 @@ interrupt-controller; #interrupt-cells = <1>; - resets = <&resetc 9>; + resets = <&rstctrl MT7628_INT_RST>; reset-names = "intc"; interrupt-parent = <&cpuintc>; @@ -89,6 +258,9 @@ compatible = "mtk,mt7628-gpio", "mtk,mt7621-gpio"; reg = <0x600 0x100>; + resets = <&rstctrl MT7628_PIO_RST>; + reset-names = "pio"; + interrupt-parent = <&intc>; interrupts = <6>; @@ -117,17 +289,26 @@ spi0: spi@b00 { compatible = "ralink,mt7621-spi"; reg = <0xb00 0x40>; + + resets = <&rstctrl MT7628_SPI_RST>; + reset-names = "spi"; + #address-cells = <1>; #size-cells = <0>; - clock-frequency = <200000000>; + clocks = <&clkctrl CLK_SPI>; }; uart0: uartlite@c00 { - compatible = "ns16550a"; + compatible = "mediatek,hsuart", "ns16550a"; reg = <0xc00 0x100>; - resets = <&resetc 12>; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + + clocks = <&clkctrl CLK_UART0>; + + resets = <&rstctrl MT7628_UART0_RST>; reset-names = "uart0"; interrupt-parent = <&intc>; @@ -137,10 +318,15 @@ }; uart1: uart1@d00 { - compatible = "ns16550a"; + compatible = "mediatek,hsuart", "ns16550a"; reg = <0xd00 0x100>; - resets = <&resetc 19>; + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; + + clocks = <&clkctrl CLK_UART1>; + + resets = <&rstctrl MT7628_UART1_RST>; reset-names = "uart1"; interrupt-parent = <&intc>; @@ -150,10 +336,15 @@ }; uart2: uart2@e00 { - compatible = "ns16550a"; + compatible = "mediatek,hsuart", "ns16550a"; reg = <0xe00 0x100>; - resets = <&resetc 20>; + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; + + clocks = <&clkctrl CLK_UART2>; + + resets = <&rstctrl MT7628_UART2_RST>; reset-names = "uart2"; interrupt-parent = <&intc>; @@ -163,11 +354,14 @@ }; }; - eth@10110000 { + eth: eth@10110000 { compatible = "mediatek,mt7628-eth"; reg = <0x10100000 0x10000 0x10110000 0x8000>; + resets = <&rstctrl MT7628_EPHY_RST>; + reset-names = "ephy"; + syscon = <&sysc>; }; @@ -178,8 +372,12 @@ #phy-cells = <0>; ralink,sysctl = <&sysc>; - resets = <&resetc 22 &resetc 25>; - reset-names = "host", "device"; + + resets = <&rstctrl MT7628_UPHY_RST>; + reset-names = "phy"; + + clocks = <&clkctrl CLK_UPHY>; + clock-names = "cg"; }; ehci@101c0000 { @@ -192,4 +390,18 @@ interrupt-parent = <&intc>; interrupts = <18>; }; + + mmc: mmc@10130000 { + compatible = "mediatek,mt7620-mmc"; + reg = <0x10130000 0x4000>; + builtin-cd = <1>; + r_smpl = <1>; + + clocks = <&clk48m>, <&clkctrl CLK_SDXC>; + clock-names = "source", "hclk"; + + resets = <&rstctrl MT7628_SDXC_RST>; + + status = "disabled"; + }; }; diff --git a/arch/mips/dts/netgear,dgnd3700v2.dts b/arch/mips/dts/netgear,dgnd3700v2.dts index 2b72491..88fca64 100644 --- a/arch/mips/dts/netgear,dgnd3700v2.dts +++ b/arch/mips/dts/netgear,dgnd3700v2.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2018 Ãlvaro Fernández Rojas <noltari@gmail.com> + * Copyright (C) 2018 Álvaro Fernández Rojas <noltari@gmail.com> */ /dts-v1/; diff --git a/arch/mips/lib/cache.c b/arch/mips/lib/cache.c index d56fd1e..0ddae30 100644 --- a/arch/mips/lib/cache.c +++ b/arch/mips/lib/cache.c @@ -87,7 +87,7 @@ static inline unsigned long scache_line_size(void) #ifdef CONFIG_MIPS_L2_CACHE return gd->arch.l2_line_size; #else - return 0; + return CONFIG_SYS_SCACHE_LINE_SIZE; #endif } diff --git a/arch/mips/mach-mtmips/Kconfig b/arch/mips/mach-mtmips/Kconfig index 4af2d54..c8dcf19 100644 --- a/arch/mips/mach-mtmips/Kconfig +++ b/arch/mips/mach-mtmips/Kconfig @@ -13,6 +13,8 @@ choice config SOC_MT7628 bool "MT7628" select MIPS_L1_CACHE_SHIFT_5 + select PINCTRL_MT7628 + select MTK_SERIAL help This supports MediaTek MT7628/MT7688. diff --git a/board/Marvell/db-88f6281-bp/Makefile b/board/Marvell/db-88f6281-bp/Makefile index e6aa7e3..003e9f6 100644 --- a/board/Marvell/db-88f6281-bp/Makefile +++ b/board/Marvell/db-88f6281-bp/Makefile @@ -4,9 +4,9 @@ obj-y := db-88f6281-bp.o extra-y := kwbimage.cfg quiet_cmd_sed = SED $@ - cmd_sed = sed $(SEDFLAGS_$(@F)) $< >$(dir $<)$(@F) + cmd_sed = sed $(SEDFLAGS_$(@F)) $< >$(dir $@)$(@F) SEDFLAGS_kwbimage.cfg = -e "s/^\#@BOOT_FROM.*/BOOT_FROM $(if $(CONFIG_CMD_NAND),nand,spi)/" -$(src)/kwbimage.cfg: $(src)/kwbimage.cfg.in include/autoconf.mk \ +$(obj)/kwbimage.cfg: $(src)/kwbimage.cfg.in include/autoconf.mk \ include/config/auto.conf $(call if_changed,sed) diff --git a/board/Marvell/db-xc3-24g4xg/Makefile b/board/Marvell/db-xc3-24g4xg/Makefile index 4dd5790..24e8200 100644 --- a/board/Marvell/db-xc3-24g4xg/Makefile +++ b/board/Marvell/db-xc3-24g4xg/Makefile @@ -6,9 +6,9 @@ obj-y := db-xc3-24g4xg.o extra-y := kwbimage.cfg quiet_cmd_sed = SED $@ - cmd_sed = sed $(SEDFLAGS_$(@F)) $< >$(dir $<)$(@F) + cmd_sed = sed $(SEDFLAGS_$(@F)) $< >$(dir $@)$(@F) SEDFLAGS_kwbimage.cfg =-e "s|^BINARY.*|BINARY $(srctree)/$(@D)/binary.0 0000005b 00000068|" -$(src)/kwbimage.cfg: $(src)/kwbimage.cfg.in include/autoconf.mk \ +$(obj)/kwbimage.cfg: $(src)/kwbimage.cfg.in include/autoconf.mk \ include/config/auto.conf $(call if_changed,sed) diff --git a/board/atmel/sam9x60ek/sam9x60ek.c b/board/atmel/sam9x60ek/sam9x60ek.c index 182b3ae..7be1dd5 100644 --- a/board/atmel/sam9x60ek/sam9x60ek.c +++ b/board/atmel/sam9x60ek/sam9x60ek.c @@ -106,6 +106,18 @@ int board_early_init_f(void) } #endif +#define MAC24AA_MAC_OFFSET 0xfa + +#ifdef CONFIG_MISC_INIT_R +int misc_init_r(void) +{ +#ifdef CONFIG_I2C_EEPROM + at91_set_ethaddr(MAC24AA_MAC_OFFSET); +#endif + return 0; +} +#endif + int board_init(void) { /* address of boot parameters */ diff --git a/board/freescale/ls1028a/ls1028a.c b/board/freescale/ls1028a/ls1028a.c index 0959714..a9606b8 100644 --- a/board/freescale/ls1028a/ls1028a.c +++ b/board/freescale/ls1028a/ls1028a.c @@ -63,6 +63,10 @@ int board_init(void) gd->env_addr = (ulong)&default_environment[0]; #endif +#ifdef CONFIG_FSL_CAAM + sec_init(); +#endif + #ifdef CONFIG_FSL_LS_PPA ppa_init(); #endif diff --git a/board/mikrotik/crs305-1g-4s/Makefile b/board/mikrotik/crs305-1g-4s/Makefile index 895331b..c03f534 100644 --- a/board/mikrotik/crs305-1g-4s/Makefile +++ b/board/mikrotik/crs305-1g-4s/Makefile @@ -6,9 +6,9 @@ obj-y := crs305-1g-4s.o extra-y := kwbimage.cfg quiet_cmd_sed = SED $@ - cmd_sed = sed $(SEDFLAGS_$(@F)) $< >$(dir $<)$(@F) + cmd_sed = sed $(SEDFLAGS_$(@F)) $< >$(dir $@)$(@F) SEDFLAGS_kwbimage.cfg =-e "s|^BINARY.*|BINARY $(srctree)/$(@D)/binary.0 0000005b 00000068|" -$(src)/kwbimage.cfg: $(src)/kwbimage.cfg.in include/autoconf.mk \ +$(obj)/kwbimage.cfg: $(src)/kwbimage.cfg.in include/autoconf.mk \ include/config/auto.conf $(call if_changed,sed) diff --git a/board/netgear/dgnd3700v2/MAINTAINERS b/board/netgear/dgnd3700v2/MAINTAINERS index 998077b..aaa51c1 100644 --- a/board/netgear/dgnd3700v2/MAINTAINERS +++ b/board/netgear/dgnd3700v2/MAINTAINERS @@ -1,5 +1,5 @@ NETGEAR DGND3700V2 BOARD -M: Ãlvaro Fernández Rojas <noltari@gmail.com> +M: Álvaro Fernández Rojas <noltari@gmail.com> S: Maintained F: board/netgear/dgnd3700v2/ F: include/configs/netgear_dgnd3700v2.h diff --git a/board/netgear/dgnd3700v2/dgnd3700v2.c b/board/netgear/dgnd3700v2/dgnd3700v2.c index f8fc70e..6840a21 100644 --- a/board/netgear/dgnd3700v2/dgnd3700v2.c +++ b/board/netgear/dgnd3700v2/dgnd3700v2.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2018 Ãlvaro Fernández Rojas <noltari@gmail.com> + * Copyright (C) 2018 Álvaro Fernández Rojas <noltari@gmail.com> */ #include <common.h> diff --git a/board/st/stm32mp1/stm32mp1.c b/board/st/stm32mp1/stm32mp1.c index 18f9b84..126af30 100644 --- a/board/st/stm32mp1/stm32mp1.c +++ b/board/st/stm32mp1/stm32mp1.c @@ -233,6 +233,23 @@ int g_dnl_board_usb_cable_connected(void) return dwc2_udc_B_session_valid(dwc2_udc_otg); } + +#define STM32MP1_G_DNL_DFU_PRODUCT_NUM 0xdf11 +#define STM32MP1_G_DNL_FASTBOOT_PRODUCT_NUM 0x0afb + +int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name) +{ + if (!strcmp(name, "usb_dnl_dfu")) + put_unaligned(STM32MP1_G_DNL_DFU_PRODUCT_NUM, &dev->idProduct); + else if (!strcmp(name, "usb_dnl_fastboot")) + put_unaligned(STM32MP1_G_DNL_FASTBOOT_PRODUCT_NUM, + &dev->idProduct); + else + put_unaligned(CONFIG_USB_GADGET_PRODUCT_NUM, &dev->idProduct); + + return 0; +} + #endif /* CONFIG_USB_GADGET */ #ifdef CONFIG_LED diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS index 88f1353..a2adf89 100644 --- a/board/sunxi/MAINTAINERS +++ b/board/sunxi/MAINTAINERS @@ -106,6 +106,11 @@ M: Jagan Teki <jagan@amarulasolutions.com> S: Maintained F: configs/a64-olinuxino_defconfig +A64-OLINUXINO-EMMC BOARD +M: Sunil Mohan Adapa <sunil@medhas.org> +S: Maintained +F: configs/a64-olinuxino-emmc_defconfig + A80 OPTIMUS BOARD M: Chen-Yu Tsai <wens@csie.org> S: Maintained diff --git a/board/ti/j721e/Kconfig b/board/ti/j721e/Kconfig index c2deb69..88097df 100644 --- a/board/ti/j721e/Kconfig +++ b/board/ti/j721e/Kconfig @@ -21,6 +21,7 @@ config TARGET_J721E_R5_EVM select K3_LOAD_SYSFW select RAM select SPL_RAM + select K3_J721E_DDRSS imply SYS_K3_SPL_ATF endchoice diff --git a/board/ti/ks2_evm/board.c b/board/ti/ks2_evm/board.c index e9bc680..e3305fb 100644 --- a/board/ti/ks2_evm/board.c +++ b/board/ti/ks2_evm/board.c @@ -67,20 +67,7 @@ struct image_header *spl_get_load_buffer(ssize_t offset, size_t size) int board_init(void) { -#if CONFIG_IS_ENABLED(DM_USB) - int rc = psc_enable_module(KS2_LPSC_USB); - - if (rc) - puts("Cannot enable USB0 module"); -#ifdef KS2_LPSC_USB_1 - rc = psc_enable_module(KS2_LPSC_USB_1); - if (rc) - puts("Cannot enable USB1 module"); -#endif -#endif - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; - return 0; } diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c index 7cfe69d..8a216ed 100644 --- a/board/xilinx/zynq/board.c +++ b/board/xilinx/zynq/board.c @@ -19,13 +19,6 @@ DECLARE_GLOBAL_DATA_PTR; -#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_BOARD_EARLY_INIT_F) -int board_early_init_f(void) -{ - return 0; -} -#endif - int board_init(void) { return 0; diff --git a/board/xilinx/zynqmp/cmds.c b/board/xilinx/zynqmp/cmds.c index f53a1b6..d3bb57a 100644 --- a/board/xilinx/zynqmp/cmds.c +++ b/board/xilinx/zynqmp/cmds.c @@ -51,8 +51,8 @@ static int do_zynqmp_verify_secure(cmd_tbl_t *cmdtp, int flag, int argc, (ulong)(key_ptr + KEY_PTR_LEN)); } - ret = invoke_smc(ZYNQMP_SIP_SVC_PM_SECURE_IMG_LOAD, src_lo, src_hi, - key_lo, key_hi, ret_payload); + ret = xilinx_pm_request(PM_SECURE_IMAGE, src_lo, src_hi, + key_lo, key_hi, ret_payload); if (ret) { printf("Failed: secure op status:0x%x\n", ret); } else { diff --git a/cmd/Kconfig b/cmd/Kconfig index 07060c6..b08a709 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -1168,6 +1168,7 @@ config CMD_SDRAM config CMD_SF bool "sf" depends on DM_SPI_FLASH || SPI_FLASH + default y if DM_SPI_FLASH help SPI Flash support @@ -1205,6 +1206,13 @@ config CMD_TSI148 This provides various sub-commands to initialise and configure the Turndra tsi148 device. See the command help for full details. +config CMD_UFS + bool "Enable UFS - Universal Flash Subsystem commands" + depends on UFS + help + "This provides commands to initialise and configure universal flash + subsystem devices" + config CMD_UNIVERSE bool "universe - Command to set up the Turndra Universe controller" help diff --git a/cmd/Makefile b/cmd/Makefile index ac843b4..2d723ea 100644 --- a/cmd/Makefile +++ b/cmd/Makefile @@ -144,7 +144,7 @@ obj-$(CONFIG_CMD_UNZIP) += unzip.o obj-$(CONFIG_CMD_VIRTIO) += virtio.o obj-$(CONFIG_CMD_WDT) += wdt.o obj-$(CONFIG_CMD_LZMADEC) += lzmadec.o - +obj-$(CONFIG_CMD_UFS) += ufs.o obj-$(CONFIG_CMD_USB) += usb.o disk.o obj-$(CONFIG_CMD_FASTBOOT) += fastboot.o obj-$(CONFIG_CMD_FS_UUID) += fs_uuid.o diff --git a/cmd/booti.c b/cmd/booti.c index c36b023..841eff1 100644 --- a/cmd/booti.c +++ b/cmd/booti.c @@ -48,6 +48,9 @@ static int booti_start(cmd_tbl_t *cmdtp, int flag, int argc, } images->ep = relocated_addr; + images->os.start = relocated_addr; + images->os.end = relocated_addr + image_size; + lmb_reserve(&images->lmb, images->ep, le32_to_cpu(image_size)); /* diff --git a/cmd/ufs.c b/cmd/ufs.c new file mode 100644 index 0000000..5b25788 --- /dev/null +++ b/cmd/ufs.c @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: GPL-2.0+ +/** + * ufs.c - UFS specific U-boot commands + * + * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com + * + */ +#include <common.h> +#include <command.h> +#include <ufs.h> + +static int do_ufs(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + int dev, ret; + + if (argc >= 2) { + if (!strcmp(argv[1], "init")) { + if (argc == 3) { + dev = simple_strtoul(argv[2], NULL, 10); + ret = ufs_probe_dev(dev); + if (ret) + return CMD_RET_FAILURE; + } else { + ufs_probe(); + } + + return CMD_RET_SUCCESS; + } + } + + return CMD_RET_USAGE; +} + +U_BOOT_CMD(ufs, 3, 1, do_ufs, + "UFS sub system", + "init [dev] - init UFS subsystem\n" +); diff --git a/common/command.c b/common/command.c index 4b887a2..ceca992 100644 --- a/common/command.c +++ b/common/command.c @@ -496,6 +496,11 @@ void fixup_cmdtable(cmd_tbl_t *cmdtp, int size) for (i = 0; i < size; i++) { ulong addr; + addr = (ulong)(cmdtp->cmd_rep) + gd->reloc_off; + cmdtp->cmd_rep = + (int (*)(struct cmd_tbl_s *, int, int, + char * const [], int *))addr; + addr = (ulong)(cmdtp->cmd) + gd->reloc_off; #ifdef DEBUG_COMMANDS printf("Command \"%s\": 0x%08lx => 0x%08lx\n", diff --git a/common/hash.c b/common/hash.c index d33e329..d0d825e 100644 --- a/common/hash.c +++ b/common/hash.c @@ -30,6 +30,12 @@ #include <u-boot/sha256.h> #include <u-boot/md5.h> +#if !defined(USE_HOSTCC) && defined(CONFIG_NEEDS_MANUAL_RELOC) +DECLARE_GLOBAL_DATA_PTR; +#endif + +static void reloc_update(void); + #if defined(CONFIG_SHA1) && !defined(CONFIG_SHA_PROG_HW_ACCEL) static int hash_init_sha1(struct hash_algo *algo, void **ctxp) { @@ -215,10 +221,31 @@ static struct hash_algo hash_algo[] = { #define multi_hash() 0 #endif +static void reloc_update(void) +{ +#if !defined(USE_HOSTCC) && defined(CONFIG_NEEDS_MANUAL_RELOC) + int i; + static bool done; + + if (!done) { + done = true; + for (i = 0; i < ARRAY_SIZE(hash_algo); i++) { + hash_algo[i].name += gd->reloc_off; + hash_algo[i].hash_func_ws += gd->reloc_off; + hash_algo[i].hash_init += gd->reloc_off; + hash_algo[i].hash_update += gd->reloc_off; + hash_algo[i].hash_finish += gd->reloc_off; + } + } +#endif +} + int hash_lookup_algo(const char *algo_name, struct hash_algo **algop) { int i; + reloc_update(); + for (i = 0; i < ARRAY_SIZE(hash_algo); i++) { if (!strcmp(algo_name, hash_algo[i].name)) { *algop = &hash_algo[i]; @@ -235,6 +262,8 @@ int hash_progressive_lookup_algo(const char *algo_name, { int i; + reloc_update(); + for (i = 0; i < ARRAY_SIZE(hash_algo); i++) { if (!strcmp(algo_name, hash_algo[i].name)) { if (hash_algo[i].hash_init) { diff --git a/common/image-sig.c b/common/image-sig.c index 004fbc5..639a112 100644 --- a/common/image-sig.c +++ b/common/image-sig.c @@ -89,6 +89,21 @@ struct checksum_algo *image_get_checksum_algo(const char *full_name) int i; const char *name; +#if !defined(USE_HOSTCC) && defined(CONFIG_NEEDS_MANUAL_RELOC) + static bool done; + + if (!done) { + done = true; + for (i = 0; i < ARRAY_SIZE(checksum_algos); i++) { + checksum_algos[i].name += gd->reloc_off; +#if IMAGE_ENABLE_SIGN + checksum_algos[i].calculate_sign += gd->reloc_off; +#endif + checksum_algos[i].calculate += gd->reloc_off; + } + } +#endif + for (i = 0; i < ARRAY_SIZE(checksum_algos); i++) { name = checksum_algos[i].name; /* Make sure names match and next char is a comma */ @@ -105,6 +120,20 @@ struct crypto_algo *image_get_crypto_algo(const char *full_name) int i; const char *name; +#if !defined(USE_HOSTCC) && defined(CONFIG_NEEDS_MANUAL_RELOC) + static bool done; + + if (!done) { + done = true; + for (i = 0; i < ARRAY_SIZE(crypto_algos); i++) { + crypto_algos[i].name += gd->reloc_off; + crypto_algos[i].sign += gd->reloc_off; + crypto_algos[i].add_verify_data += gd->reloc_off; + crypto_algos[i].verify += gd->reloc_off; + } + } +#endif + /* Move name to after the comma */ name = strchr(full_name, ','); if (!name) diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c index 34e1e73..2ede096 100644 --- a/common/spl/spl_mmc.c +++ b/common/spl/spl_mmc.c @@ -343,8 +343,6 @@ int spl_mmc_load(struct spl_image_info *spl_image, } } - raw_sect = spl_mmc_get_uboot_raw_sector(mmc); - boot_mode = spl_boot_mode(bootdev->boot_device); err = -EINVAL; switch (boot_mode) { @@ -383,6 +381,9 @@ int spl_mmc_load(struct spl_image_info *spl_image, if (!err) return err; } + + raw_sect = spl_mmc_get_uboot_raw_sector(mmc); + #ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION err = mmc_load_image_raw_partition(spl_image, mmc, raw_part, raw_sect); diff --git a/configs/a64-olinuxino-emmc_defconfig b/configs/a64-olinuxino-emmc_defconfig new file mode 100644 index 0000000..56153e3 --- /dev/null +++ b/configs/a64-olinuxino-emmc_defconfig @@ -0,0 +1,17 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_SPL=y +CONFIG_MACH_SUN50I=y +CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y +CONFIG_MMC_SUNXI_SLOT_EXTRA=2 +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y +# CONFIG_CMD_FLASH is not set +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_SPL_EFI_PARTITION is not set +CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-olinuxino-emmc" +CONFIG_SUN8I_EMAC=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_OHCI_HCD=y +CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/aristainetos2_defconfig b/configs/aristainetos2_defconfig index 18ef5d2..0bfc117 100644 --- a/configs/aristainetos2_defconfig +++ b/configs/aristainetos2_defconfig @@ -44,6 +44,7 @@ CONFIG_SF_DEFAULT_CS=1 CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_MTD=y CONFIG_MTD_UBI_FASTMAP=y CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1 CONFIG_PHYLIB=y diff --git a/configs/aristainetos2b_defconfig b/configs/aristainetos2b_defconfig index 1054c05..e2da747 100644 --- a/configs/aristainetos2b_defconfig +++ b/configs/aristainetos2b_defconfig @@ -42,6 +42,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_MTD=y CONFIG_MTD_UBI_FASTMAP=y CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1 CONFIG_PHYLIB=y diff --git a/configs/aristainetos_defconfig b/configs/aristainetos_defconfig index 4080a7b..5caf95c 100644 --- a/configs/aristainetos_defconfig +++ b/configs/aristainetos_defconfig @@ -43,6 +43,7 @@ CONFIG_SF_DEFAULT_BUS=3 CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_MTD=y CONFIG_MTD_UBI_FASTMAP=y CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1 CONFIG_PHYLIB=y diff --git a/configs/avnet_ultra96_rev1_defconfig b/configs/avnet_ultra96_rev1_defconfig index b5e61e6..bd60000 100644 --- a/configs/avnet_ultra96_rev1_defconfig +++ b/configs/avnet_ultra96_rev1_defconfig @@ -58,6 +58,7 @@ CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_ISSI=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y @@ -73,7 +74,6 @@ CONFIG_ZYNQ_SPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_XHCI_ZYNQMP=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GADGET=y CONFIG_USB_DWC3_GENERIC=y diff --git a/configs/cm_fx6_defconfig b/configs/cm_fx6_defconfig index eed0558..fbaf79d 100644 --- a/configs/cm_fx6_defconfig +++ b/configs/cm_fx6_defconfig @@ -72,6 +72,7 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_SST=y CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_MTD=y CONFIG_PHYLIB=y CONFIG_MII=y CONFIG_DM_PMIC=y diff --git a/configs/comtrend_vr3032u_ram_defconfig b/configs/comtrend_vr3032u_ram_defconfig index 34a1502..c53d499 100644 --- a/configs/comtrend_vr3032u_ram_defconfig +++ b/configs/comtrend_vr3032u_ram_defconfig @@ -25,6 +25,7 @@ CONFIG_CMD_LICENSE=y CONFIG_CMD_MEMINFO=y # CONFIG_CMD_FLASH is not set # CONFIG_CMD_LOADS is not set +CONFIG_CMD_NAND=y CONFIG_CMD_USB=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y @@ -37,6 +38,10 @@ CONFIG_DM_GPIO=y CONFIG_LED=y CONFIG_LED_BCM6328=y CONFIG_LED_BLINK=y +CONFIG_MTD=y +CONFIG_NAND=y +CONFIG_NAND_BRCMNAND=y +CONFIG_NAND_BRCMNAND_6368=y CONFIG_DM_ETH=y CONFIG_BCM6368_ETH=y CONFIG_PHY=y diff --git a/configs/dra7xx_evm_defconfig b/configs/dra7xx_evm_defconfig index 868030d..88d160d 100644 --- a/configs/dra7xx_evm_defconfig +++ b/configs/dra7xx_evm_defconfig @@ -25,8 +25,11 @@ CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_DMA_SUPPORT=y CONFIG_SPL_OS_BOOT=y +CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000 +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_DFU=y CONFIG_CMD_SPL=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_NAND=y @@ -39,7 +42,7 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="dra7-evm" CONFIG_OF_LIST="dra7-evm dra72-evm dra72-evm-revc dra71-evm dra76-evm" CONFIG_SPL_MULTI_DTB_FIT=y -CONFIG_SPL_MULTI_DTB_FIT_UNCOMPRESS_SZ=0x9000 +CONFIG_SPL_MULTI_DTB_FIT_UNCOMPRESS_SZ=0xA000 CONFIG_OF_SPL_REMOVE_PROPS="clocks clock-names interrupt-parent" # CONFIG_ENV_IS_IN_FAT is not set CONFIG_ENV_IS_IN_MMC=y @@ -85,6 +88,7 @@ CONFIG_MII=y CONFIG_DRIVER_TI_CPSW=y CONFIG_SPL_PHY=y CONFIG_PIPE3_PHY=y +CONFIG_SPL_PIPE3_PHY=y CONFIG_OMAP_USB2_PHY=y CONFIG_PMIC_PALMAS=y CONFIG_PMIC_LP873X=y @@ -107,7 +111,9 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GADGET=y +CONFIG_USB_DWC3_OMAP=y CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_DWC3_PHY_OMAP=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" CONFIG_USB_GADGET_VENDOR_NUM=0x0451 diff --git a/configs/dra7xx_hs_evm_defconfig b/configs/dra7xx_hs_evm_defconfig index 7a5c3e7..ca904d8 100644 --- a/configs/dra7xx_hs_evm_defconfig +++ b/configs/dra7xx_hs_evm_defconfig @@ -30,8 +30,11 @@ CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_DMA_SUPPORT=y # CONFIG_SPL_NAND_SUPPORT is not set +CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000 +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_DFU=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_NAND=y CONFIG_CMD_MTDPARTS=y @@ -42,7 +45,7 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="dra7-evm" CONFIG_OF_LIST="dra7-evm dra72-evm dra72-evm-revc dra71-evm dra76-evm" CONFIG_SPL_MULTI_DTB_FIT=y -CONFIG_SPL_MULTI_DTB_FIT_UNCOMPRESS_SZ=0x9000 +CONFIG_SPL_MULTI_DTB_FIT_UNCOMPRESS_SZ=0xA000 CONFIG_OF_SPL_REMOVE_PROPS="clocks clock-names interrupt-parent" # CONFIG_ENV_IS_IN_FAT is not set CONFIG_ENV_IS_IN_MMC=y @@ -88,6 +91,7 @@ CONFIG_MII=y CONFIG_DRIVER_TI_CPSW=y CONFIG_SPL_PHY=y CONFIG_PIPE3_PHY=y +CONFIG_SPL_PIPE3_PHY=y CONFIG_OMAP_USB2_PHY=y CONFIG_PMIC_PALMAS=y CONFIG_PMIC_LP873X=y @@ -110,7 +114,9 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GADGET=y +CONFIG_USB_DWC3_OMAP=y CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_DWC3_PHY_OMAP=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" CONFIG_USB_GADGET_VENDOR_NUM=0x0451 diff --git a/configs/evb-rk3328_defconfig b/configs/evb-rk3328_defconfig index 3761077..f161c40 100644 --- a/configs/evb-rk3328_defconfig +++ b/configs/evb-rk3328_defconfig @@ -86,6 +86,7 @@ CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_GENERIC=y CONFIG_USB_DWC2=y CONFIG_USB_DWC3=y +# CONFIG_USB_DWC3_GADGET is not set CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Rockchip" CONFIG_USB_GADGET_VENDOR_NUM=0x2207 diff --git a/configs/gardena-smart-gateway-mt7688-ram_defconfig b/configs/gardena-smart-gateway-mt7688-ram_defconfig index 03f9d99..be92c3c 100644 --- a/configs/gardena-smart-gateway-mt7688-ram_defconfig +++ b/configs/gardena-smart-gateway-mt7688-ram_defconfig @@ -45,7 +45,6 @@ CONFIG_NET_RANDOM_ETHADDR=y # CONFIG_DM_DEVICE_REMOVE is not set CONFIG_HAVE_BLOCK_DEVICE=y CONFIG_BOOTCOUNT_LIMIT=y -CONFIG_CLK=y CONFIG_LED=y CONFIG_LED_BLINK=y CONFIG_LED_GPIO=y @@ -60,14 +59,8 @@ CONFIG_SPI_FLASH_WINBOND=y CONFIG_SPI_FLASH_XMC=y CONFIG_SPI_FLASH_MTD=y CONFIG_MTD_UBI_BEB_LIMIT=22 -CONFIG_PHYLIB=y -CONFIG_PHY_FIXED=y CONFIG_MT7628_ETH=y CONFIG_PHY=y -CONFIG_POWER_DOMAIN=y -CONFIG_RAM=y -CONFIG_DM_RESET=y -CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_MT7621_SPI=y CONFIG_SYSRESET_SYSCON=y diff --git a/configs/gardena-smart-gateway-mt7688_defconfig b/configs/gardena-smart-gateway-mt7688_defconfig index 6cb8fc0..7e61a40 100644 --- a/configs/gardena-smart-gateway-mt7688_defconfig +++ b/configs/gardena-smart-gateway-mt7688_defconfig @@ -48,7 +48,6 @@ CONFIG_NET_RANDOM_ETHADDR=y # CONFIG_DM_DEVICE_REMOVE is not set CONFIG_HAVE_BLOCK_DEVICE=y CONFIG_BOOTCOUNT_LIMIT=y -CONFIG_CLK=y CONFIG_LED=y CONFIG_LED_BLINK=y CONFIG_LED_GPIO=y @@ -63,14 +62,8 @@ CONFIG_SPI_FLASH_WINBOND=y CONFIG_SPI_FLASH_XMC=y CONFIG_SPI_FLASH_MTD=y CONFIG_MTD_UBI_BEB_LIMIT=22 -CONFIG_PHYLIB=y -CONFIG_PHY_FIXED=y CONFIG_MT7628_ETH=y CONFIG_PHY=y -CONFIG_POWER_DOMAIN=y -CONFIG_RAM=y -CONFIG_DM_RESET=y -CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_MT7621_SPI=y CONFIG_SYSRESET_SYSCON=y diff --git a/configs/j721e_evm_a72_defconfig b/configs/j721e_evm_a72_defconfig index 6729e03..b79fe14 100644 --- a/configs/j721e_evm_a72_defconfig +++ b/configs/j721e_evm_a72_defconfig @@ -34,13 +34,15 @@ CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_CMD_ASKENV=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y CONFIG_CMD_REMOTEPROC=y CONFIG_CMD_SF=y +CONFIG_CMD_UFS=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_CMD_EXT4_WRITE=y # CONFIG_ISO_PARTITION is not set -# CONFIG_EFI_PARTITION is not set +# CONFIG_SPL_EFI_PARTITION is not set CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="k3-j721e-common-proc-board" @@ -63,6 +65,15 @@ CONFIG_MISC=y CONFIG_DM_MMC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_AM654=y +CONFIG_MTD=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_MTD_DEVICE=y +CONFIG_FLASH_CFI_DRIVER=y +CONFIG_CFI_FLASH=y +CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y +CONFIG_FLASH_CFI_MTD=y +CONFIG_SYS_FLASH_CFI=y +CONFIG_HBMC_AM654=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y @@ -77,6 +88,8 @@ CONFIG_REMOTEPROC_TI_K3_DSP=y CONFIG_REMOTEPROC_TI_K3_R5F=y CONFIG_DM_RESET=y CONFIG_RESET_TI_SCI=y +CONFIG_SCSI=y +CONFIG_DM_SCSI=y CONFIG_DM_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y @@ -84,4 +97,9 @@ CONFIG_CADENCE_QSPI=y CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y CONFIG_SYSRESET_TI_SCI=y +CONFIG_UFS=y +CONFIG_CADENCE_UFS=y +CONFIG_TI_J721E_UFS=y CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_MTDIDS_DEFAULT="nor0=47040000.spi.0,nor0=47034000.hyperbus" +CONFIG_MTDPARTS_DEFAULT="mtdparts=47034000.hyperbus:512k(hbmc.tiboot3),2m(hbmc.tispl),4m(hbmc.u-boot),256k(hbmc.env),1m(hbmc.sysfw),-@8m(hbmc.rootfs)" diff --git a/configs/k2g_evm_defconfig b/configs/k2g_evm_defconfig index 2780451..865a643 100644 --- a/configs/k2g_evm_defconfig +++ b/configs/k2g_evm_defconfig @@ -63,6 +63,7 @@ CONFIG_MII=y CONFIG_DRIVER_TI_KEYSTONE_NET=y CONFIG_PHY=y CONFIG_NOP_PHY=y +CONFIG_KEYSTONE_USB_PHY=y CONFIG_REMOTEPROC_TI_POWER=y CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y @@ -73,9 +74,7 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_DM_USB_GADGET=y CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC3=y -CONFIG_USB_DWC3_GADGET=y CONFIG_USB_DWC3_GENERIC=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_DOWNLOAD=y diff --git a/configs/khadas-vim3_defconfig b/configs/khadas-vim3_defconfig index cd37f78..81ac42e 100644 --- a/configs/khadas-vim3_defconfig +++ b/configs/khadas-vim3_defconfig @@ -44,6 +44,7 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC3=y +# CONFIG_USB_DWC3_GADGET is not set CONFIG_USB_DWC3_MESON_G12A=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e diff --git a/configs/linkit-smart-7688-ram_defconfig b/configs/linkit-smart-7688-ram_defconfig index 8402147..3760ee4 100644 --- a/configs/linkit-smart-7688-ram_defconfig +++ b/configs/linkit-smart-7688-ram_defconfig @@ -35,7 +35,6 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_NET_RANDOM_ETHADDR=y # CONFIG_DM_DEVICE_REMOVE is not set CONFIG_BLK=y -CONFIG_CLK=y CONFIG_LED=y CONFIG_LED_BLINK=y CONFIG_LED_GPIO=y @@ -46,15 +45,9 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_SPI_FLASH_MTD=y -CONFIG_PHYLIB=y -CONFIG_PHY_FIXED=y CONFIG_MT7628_ETH=y CONFIG_PHY=y CONFIG_MT76X8_USB_PHY=y -CONFIG_POWER_DOMAIN=y -CONFIG_RAM=y -CONFIG_DM_RESET=y -CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_MT7621_SPI=y CONFIG_SYSRESET_SYSCON=y diff --git a/configs/linkit-smart-7688_defconfig b/configs/linkit-smart-7688_defconfig index 5d80051..9a8ac02 100644 --- a/configs/linkit-smart-7688_defconfig +++ b/configs/linkit-smart-7688_defconfig @@ -39,7 +39,6 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_NET_RANDOM_ETHADDR=y # CONFIG_DM_DEVICE_REMOVE is not set CONFIG_BLK=y -CONFIG_CLK=y CONFIG_LED=y CONFIG_LED_BLINK=y CONFIG_LED_GPIO=y @@ -50,15 +49,9 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_SPI_FLASH_MTD=y -CONFIG_PHYLIB=y -CONFIG_PHY_FIXED=y CONFIG_MT7628_ETH=y CONFIG_PHY=y CONFIG_MT76X8_USB_PHY=y -CONFIG_POWER_DOMAIN=y -CONFIG_RAM=y -CONFIG_DM_RESET=y -CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_MT7621_SPI=y CONFIG_SYSRESET_SYSCON=y diff --git a/configs/odroid-n2_defconfig b/configs/odroid-n2_defconfig index abd945a..1caa391 100644 --- a/configs/odroid-n2_defconfig +++ b/configs/odroid-n2_defconfig @@ -44,6 +44,7 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC3=y +# CONFIG_USB_DWC3_GADGET is not set CONFIG_USB_DWC3_MESON_G12A=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e diff --git a/configs/rock64-rk3328_defconfig b/configs/rock64-rk3328_defconfig index 3ab0af1..60a0d14 100644 --- a/configs/rock64-rk3328_defconfig +++ b/configs/rock64-rk3328_defconfig @@ -88,6 +88,7 @@ CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_GENERIC=y CONFIG_USB_DWC2=y CONFIG_USB_DWC3=y +# CONFIG_USB_DWC3_GADGET is not set CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Rockchip" CONFIG_USB_GADGET_VENDOR_NUM=0x2207 diff --git a/configs/sam9x60ek_mmc_defconfig b/configs/sam9x60ek_mmc_defconfig index 0d3746a..7173501 100644 --- a/configs/sam9x60ek_mmc_defconfig +++ b/configs/sam9x60ek_mmc_defconfig @@ -15,10 +15,13 @@ CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="mem=256M console=ttyS0,115200 root=/dev/mmcblk0p2 rw rootfstype=ext4 rootwait" CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_MISC_INIT_R=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot> " CONFIG_CMD_BOOTZ=y +CONFIG_CMD_DM=y +CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y @@ -35,6 +38,10 @@ CONFIG_CLK_AT91=y CONFIG_AT91_GENERIC_CLK=y CONFIG_DM_GPIO=y CONFIG_AT91_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_AT91=y +CONFIG_I2C_EEPROM=y +CONFIG_MICROCHIP_FLEXCOM=y CONFIG_DM_MMC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ATMEL=y diff --git a/configs/sam9x60ek_nandflash_defconfig b/configs/sam9x60ek_nandflash_defconfig index cdba103..63966b5 100644 --- a/configs/sam9x60ek_nandflash_defconfig +++ b/configs/sam9x60ek_nandflash_defconfig @@ -14,10 +14,13 @@ CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,768k(uboot)ro,256k(env_redundant),256k(env),512k(dtb),6M(kernel)ro,-(rootfs) rootfstype=ubifs ubi.mtd=12 root=ubi0:rootfs rw" CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_MISC_INIT_R=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot> " CONFIG_CMD_BOOTZ=y +CONFIG_CMD_DM=y +CONFIG_CMD_I2C=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y @@ -37,6 +40,10 @@ CONFIG_CLK_AT91=y CONFIG_AT91_GENERIC_CLK=y CONFIG_DM_GPIO=y CONFIG_AT91_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_AT91=y +CONFIG_I2C_EEPROM=y +CONFIG_MICROCHIP_FLEXCOM=y CONFIG_DM_MMC=y CONFIG_GENERIC_ATMEL_MCI=y CONFIG_PHY_MICREL=y diff --git a/configs/sam9x60ek_qspiflash_defconfig b/configs/sam9x60ek_qspiflash_defconfig index e1b292e..eed7b77 100644 --- a/configs/sam9x60ek_qspiflash_defconfig +++ b/configs/sam9x60ek_qspiflash_defconfig @@ -16,10 +16,13 @@ CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,768k(uboot)ro,256k(env_redundant),256k(env),512k(dtb),6M(kernel)ro,-(rootfs) rootfstype=ubifs ubi.mtd=12 root=ubi0:rootfs rw" CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_MISC_INIT_R=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot> " CONFIG_CMD_BOOTZ=y +CONFIG_CMD_DM=y +CONFIG_CMD_I2C=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y @@ -48,6 +51,10 @@ CONFIG_CLK_AT91=y CONFIG_AT91_GENERIC_CLK=y CONFIG_DM_GPIO=y CONFIG_AT91_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_AT91=y +CONFIG_I2C_EEPROM=y +CONFIG_MICROCHIP_FLEXCOM=y CONFIG_DM_MMC=y CONFIG_GENERIC_ATMEL_MCI=y CONFIG_MTD=y diff --git a/configs/sei510_defconfig b/configs/sei510_defconfig index 9df04c3..302480e 100644 --- a/configs/sei510_defconfig +++ b/configs/sei510_defconfig @@ -65,6 +65,7 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC3=y +# CONFIG_USB_DWC3_GADGET is not set CONFIG_USB_DWC3_MESON_G12A=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_VENDOR_NUM=0x18d1 diff --git a/configs/sei610_defconfig b/configs/sei610_defconfig index 520a683..1f36722 100644 --- a/configs/sei610_defconfig +++ b/configs/sei610_defconfig @@ -62,6 +62,7 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC3=y +# CONFIG_USB_DWC3_GADGET is not set CONFIG_USB_DWC3_MESON_G12A=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_VENDOR_NUM=0x18d1 diff --git a/configs/socfpga_arria5_defconfig b/configs/socfpga_arria5_defconfig index 9325467..51f559c 100644 --- a/configs/socfpga_arria5_defconfig +++ b/configs/socfpga_arria5_defconfig @@ -47,6 +47,7 @@ CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_SPI_FLASH_MTD=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DM_ETH=y diff --git a/configs/socfpga_cyclone5_defconfig b/configs/socfpga_cyclone5_defconfig index 8e5b2e2..c648113 100644 --- a/configs/socfpga_cyclone5_defconfig +++ b/configs/socfpga_cyclone5_defconfig @@ -48,6 +48,7 @@ CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_SPI_FLASH_MTD=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DM_ETH=y diff --git a/configs/socfpga_dbm_soc1_defconfig b/configs/socfpga_dbm_soc1_defconfig index c73f382..414f131 100644 --- a/configs/socfpga_dbm_soc1_defconfig +++ b/configs/socfpga_dbm_soc1_defconfig @@ -46,6 +46,7 @@ CONFIG_SYS_I2C_DW=y CONFIG_DM_MMC=y CONFIG_MMC_DW=y CONFIG_MTD_DEVICE=y +CONFIG_SPI_FLASH_MTD=y CONFIG_DM_ETH=y CONFIG_PHY_GIGE=y CONFIG_ETH_DESIGNWARE=y diff --git a/configs/socfpga_de0_nano_soc_defconfig b/configs/socfpga_de0_nano_soc_defconfig index 80ccb33..6eb052e 100644 --- a/configs/socfpga_de0_nano_soc_defconfig +++ b/configs/socfpga_de0_nano_soc_defconfig @@ -43,6 +43,7 @@ CONFIG_SYS_I2C_DW=y CONFIG_DM_MMC=y CONFIG_MMC_DW=y CONFIG_MTD_DEVICE=y +CONFIG_SPI_FLASH_MTD=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DM_ETH=y diff --git a/configs/socfpga_de10_nano_defconfig b/configs/socfpga_de10_nano_defconfig index 98e80b7..6b8b5b4 100644 --- a/configs/socfpga_de10_nano_defconfig +++ b/configs/socfpga_de10_nano_defconfig @@ -39,6 +39,7 @@ CONFIG_SYS_I2C_DW=y CONFIG_DM_MMC=y CONFIG_MMC_DW=y CONFIG_MTD_DEVICE=y +CONFIG_SPI_FLASH_MTD=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DM_ETH=y diff --git a/configs/socfpga_is1_defconfig b/configs/socfpga_is1_defconfig index 99cdb26..38b9f6c 100644 --- a/configs/socfpga_is1_defconfig +++ b/configs/socfpga_is1_defconfig @@ -43,6 +43,7 @@ CONFIG_SYS_I2C_DW=y CONFIG_MTD_DEVICE=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_MTD=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DM_ETH=y diff --git a/configs/socfpga_mcvevk_defconfig b/configs/socfpga_mcvevk_defconfig index e977cd7..605ffd7 100644 --- a/configs/socfpga_mcvevk_defconfig +++ b/configs/socfpga_mcvevk_defconfig @@ -42,6 +42,7 @@ CONFIG_DM_I2C=y CONFIG_SYS_I2C_DW=y CONFIG_DM_MMC=y CONFIG_MMC_DW=y +CONFIG_SPI_FLASH_MTD=y CONFIG_DM_ETH=y CONFIG_PHY_GIGE=y CONFIG_ETH_DESIGNWARE=y diff --git a/configs/socfpga_sockit_defconfig b/configs/socfpga_sockit_defconfig index b570b9d..cae6f7b 100644 --- a/configs/socfpga_sockit_defconfig +++ b/configs/socfpga_sockit_defconfig @@ -48,6 +48,7 @@ CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_SPI_FLASH_MTD=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DM_ETH=y diff --git a/configs/socfpga_socrates_defconfig b/configs/socfpga_socrates_defconfig index 9eac00e..9cb1daa 100644 --- a/configs/socfpga_socrates_defconfig +++ b/configs/socfpga_socrates_defconfig @@ -48,6 +48,7 @@ CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_MTD=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DM_ETH=y diff --git a/configs/socfpga_sr1500_defconfig b/configs/socfpga_sr1500_defconfig index 092347a..c48bbb0 100644 --- a/configs/socfpga_sr1500_defconfig +++ b/configs/socfpga_sr1500_defconfig @@ -49,6 +49,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_SPEED=100000000 CONFIG_SPI_FLASH_STMICRO=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_SPI_FLASH_MTD=y CONFIG_PHY_MARVELL=y CONFIG_DM_ETH=y CONFIG_PHY_GIGE=y diff --git a/configs/socfpga_vining_fpga_defconfig b/configs/socfpga_vining_fpga_defconfig index a9c594e..80733ba 100644 --- a/configs/socfpga_vining_fpga_defconfig +++ b/configs/socfpga_vining_fpga_defconfig @@ -72,6 +72,7 @@ CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_SPI_FLASH_MTD=y CONFIG_MTD_UBI_FASTMAP=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y diff --git a/configs/sopine_baseboard_defconfig b/configs/sopine_baseboard_defconfig index 5833234..c9123fd 100644 --- a/configs/sopine_baseboard_defconfig +++ b/configs/sopine_baseboard_defconfig @@ -10,6 +10,7 @@ CONFIG_DRAM_ZQ=3881949 CONFIG_MMC0_CD_PIN="" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_SPL_SPI_SUNXI=y +CONFIG_SPI_FLASH_WINBOND=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_USE_PREBOOT=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x8000 diff --git a/configs/stm32f429-discovery_defconfig b/configs/stm32f429-discovery_defconfig index 3c35015..45fdb9d 100644 --- a/configs/stm32f429-discovery_defconfig +++ b/configs/stm32f429-discovery_defconfig @@ -21,5 +21,6 @@ CONFIG_CMD_TIMER=y CONFIG_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="stm32f429-disco" CONFIG_ENV_IS_IN_FLASH=y +# CONFIG_NET is not set # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y diff --git a/configs/stm32f429-evaluation_defconfig b/configs/stm32f429-evaluation_defconfig index 51f587f..2b118a0 100644 --- a/configs/stm32f429-evaluation_defconfig +++ b/configs/stm32f429-evaluation_defconfig @@ -17,12 +17,12 @@ CONFIG_CMD_GPT=y # CONFIG_RANDOM_UUID is not set CONFIG_CMD_MMC=y # CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_MII is not set CONFIG_CMD_CACHE=y CONFIG_CMD_TIMER=y # CONFIG_ISO_PARTITION is not set CONFIG_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="stm32429i-eval" +# CONFIG_NET is not set CONFIG_DM_MMC=y CONFIG_ARM_PL180_MMCI=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/stm32f469-discovery_defconfig b/configs/stm32f469-discovery_defconfig index dcd0697..5cedb76 100644 --- a/configs/stm32f469-discovery_defconfig +++ b/configs/stm32f469-discovery_defconfig @@ -18,12 +18,12 @@ CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y # CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_MII is not set CONFIG_CMD_CACHE=y CONFIG_CMD_TIMER=y # CONFIG_ISO_PARTITION is not set CONFIG_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="stm32f469-disco" +# CONFIG_NET is not set CONFIG_DM_MMC=y CONFIG_ARM_PL180_MMCI=y CONFIG_MTD=y diff --git a/configs/stm32h743-disco_defconfig b/configs/stm32h743-disco_defconfig index 1053dbc..64aba95 100644 --- a/configs/stm32h743-disco_defconfig +++ b/configs/stm32h743-disco_defconfig @@ -24,6 +24,7 @@ CONFIG_CMD_EXT4_WRITE=y # CONFIG_ISO_PARTITION is not set CONFIG_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="stm32h743i-disco" +# CONFIG_NET is not set CONFIG_DM_MMC=y CONFIG_STM32_SDMMC2=y # CONFIG_PINCTRL_FULL is not set diff --git a/configs/stm32h743-eval_defconfig b/configs/stm32h743-eval_defconfig index 4d88ed3..e148014 100644 --- a/configs/stm32h743-eval_defconfig +++ b/configs/stm32h743-eval_defconfig @@ -24,6 +24,7 @@ CONFIG_CMD_EXT4_WRITE=y # CONFIG_ISO_PARTITION is not set CONFIG_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="stm32h743i-eval" +# CONFIG_NET is not set CONFIG_DM_MMC=y CONFIG_STM32_SDMMC2=y # CONFIG_PINCTRL_FULL is not set diff --git a/configs/stm32mp15_basic_defconfig b/configs/stm32mp15_basic_defconfig index c54feb0..2a54e71 100644 --- a/configs/stm32mp15_basic_defconfig +++ b/configs/stm32mp15_basic_defconfig @@ -90,6 +90,7 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_WINBOND=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_SPI_FLASH_MTD=y +CONFIG_SPL_SPI_FLASH_MTD=y CONFIG_DM_ETH=y CONFIG_DWC_ETH_QOS=y CONFIG_PHY=y diff --git a/configs/u200_defconfig b/configs/u200_defconfig index ced6ca8..009d564 100644 --- a/configs/u200_defconfig +++ b/configs/u200_defconfig @@ -44,6 +44,7 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC3=y +# CONFIG_USB_DWC3_GADGET is not set CONFIG_USB_DWC3_MESON_G12A=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e diff --git a/configs/xilinx_versal_mini_defconfig b/configs/xilinx_versal_mini_defconfig index 742aa12..afcbed3 100644 --- a/configs/xilinx_versal_mini_defconfig +++ b/configs/xilinx_versal_mini_defconfig @@ -4,7 +4,7 @@ CONFIG_SYS_ICACHE_OFF=y CONFIG_ARCH_VERSAL=y CONFIG_SYS_TEXT_BASE=0xFFFC0000 CONFIG_ENV_SIZE=0x80 -CONFIG_NR_DRAM_BANKS=1 +CONFIG_NR_DRAM_BANKS=3 CONFIG_SYS_MALLOC_LEN=0x2000 CONFIG_SYS_MEM_RSVD_FOR_MMU=y CONFIG_COUNTER_FREQUENCY=2720000 @@ -20,7 +20,6 @@ CONFIG_BOARD_EARLY_INIT_R=y # CONFIG_SYS_LONGHELP is not set CONFIG_SYS_PROMPT="Versal> " # CONFIG_AUTOBOOT is not set -# CONFIG_CMD_BDI is not set # CONFIG_CMD_CONSOLE is not set # CONFIG_CMD_BOOTD is not set # CONFIG_CMD_BOOTM is not set diff --git a/configs/xilinx_versal_virt_defconfig b/configs/xilinx_versal_virt_defconfig index 3ff23a2..1717039 100644 --- a/configs/xilinx_versal_virt_defconfig +++ b/configs/xilinx_versal_virt_defconfig @@ -1,13 +1,13 @@ CONFIG_ARM=y CONFIG_ARCH_VERSAL=y CONFIG_SYS_TEXT_BASE=0x8000000 -CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_SYS_MALLOC_F_LEN=0x100000 CONFIG_COUNTER_FREQUENCY=62500000 CONFIG_ENV_VARS_UBOOT_CONFIG=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set -CONFIG_BOOTDELAY=-1 +CONFIG_BOOTDELAY=5 CONFIG_SUPPORT_RAW_INITRD=y # CONFIG_BOARD_LATE_INIT is not set # CONFIG_DISPLAY_CPUINFO is not set @@ -17,11 +17,15 @@ CONFIG_SYS_PROMPT="Versal> " CONFIG_CMD_BOOTMENU=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DFU=y CONFIG_CMD_DM=y # CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y +CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_TFTPPUT=y CONFIG_CMD_MII=y @@ -43,11 +47,19 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_IP_DEFRAG=y CONFIG_TFTP_BLOCKSIZE=4096 CONFIG_CLK_VERSAL=y +CONFIG_DFU_RAM=y +CONFIG_FPGA_XILINX=y +CONFIG_FPGA_VERSALPL=y CONFIG_DM_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_CADENCE=y +CONFIG_MISC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y +CONFIG_ZYNQ_SDHCI_MIN_FREQ=100000 CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y @@ -68,5 +80,23 @@ CONFIG_ZYNQ_GEM=y CONFIG_PL01X_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GADGET=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_ULPI_VIEWPORT=y +CONFIG_USB_ULPI=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Xilinx" +CONFIG_USB_GADGET_VENDOR_NUM=0x03FD +CONFIG_USB_GADGET_PRODUCT_NUM=0x0300 +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_FUNCTION_THOR=y CONFIG_FAT_WRITE=y +CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/xilinx_zynqmp_a2197_revA_defconfig b/configs/xilinx_zynqmp_a2197_revA_defconfig index 3498483..e5e2b54 100644 --- a/configs/xilinx_zynqmp_a2197_revA_defconfig +++ b/configs/xilinx_zynqmp_a2197_revA_defconfig @@ -43,7 +43,7 @@ CONFIG_CMD_TIMER=y CONFIG_CMD_EXT4_WRITE=y CONFIG_SPL_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="zynqmp-a2197-revA" -CONFIG_OF_LIST="zynqmp-a2197-revA zynqmp-a2197-g-revA zynqmp-a2197-p-revA zynqmp-a2197-m-revA" +CONFIG_OF_LIST="zynqmp-a2197-revA zynqmp-g-a2197-00-revA zynqmp-p-a2197-00-revA zynqmp-m-a2197-01-revA zynqmp-m-a2197-02-revA zynqmp-m-a2197-03-revA" CONFIG_ENV_IS_IN_FAT=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM=y diff --git a/configs/xilinx_zynqmp_a2197_g_revA_defconfig b/configs/xilinx_zynqmp_e_a2197_00_revA_defconfig index 47a98c6..33f9f44 100644 --- a/configs/xilinx_zynqmp_a2197_g_revA_defconfig +++ b/configs/xilinx_zynqmp_e_a2197_00_revA_defconfig @@ -42,7 +42,7 @@ CONFIG_CMD_TIME=y CONFIG_CMD_TIMER=y CONFIG_CMD_EXT4_WRITE=y CONFIG_SPL_OF_CONTROL=y -CONFIG_DEFAULT_DEVICE_TREE="zynqmp-a2197-g-revA" +CONFIG_DEFAULT_DEVICE_TREE="zynqmp-e-a2197-00-revA" CONFIG_ENV_IS_IN_FAT=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM=y diff --git a/configs/xilinx_zynqmp_a2197_m_revA_defconfig b/configs/xilinx_zynqmp_g_a2197_00_revA_defconfig index fb4020b..9cc9191 100644 --- a/configs/xilinx_zynqmp_a2197_m_revA_defconfig +++ b/configs/xilinx_zynqmp_g_a2197_00_revA_defconfig @@ -42,7 +42,7 @@ CONFIG_CMD_TIME=y CONFIG_CMD_TIMER=y CONFIG_CMD_EXT4_WRITE=y CONFIG_SPL_OF_CONTROL=y -CONFIG_DEFAULT_DEVICE_TREE="zynqmp-a2197-m-revA" +CONFIG_DEFAULT_DEVICE_TREE="zynqmp-g-a2197-00-revA" CONFIG_ENV_IS_IN_FAT=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM=y diff --git a/configs/xilinx_zynqmp_m_a2197_01_revA_defconfig b/configs/xilinx_zynqmp_m_a2197_01_revA_defconfig new file mode 100644 index 0000000..ea6c6b9 --- /dev/null +++ b/configs/xilinx_zynqmp_m_a2197_01_revA_defconfig @@ -0,0 +1,115 @@ +CONFIG_ARM=y +CONFIG_ARCH_ZYNQMP=y +CONFIG_SYS_TEXT_BASE=0x8000000 +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_SPL=y +CONFIG_DEBUG_UART_BASE=0xff000000 +CONFIG_DEBUG_UART_CLOCK=100000000 +CONFIG_IDENT_STRING=" Xilinx ZynqMP SC for Versal" +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI_SUPPORT=y +CONFIG_ZYNQMP_USB=y +CONFIG_DEBUG_UART=y +CONFIG_AHCI=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_LOAD_FIT=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_BOARD_EARLY_INIT_R=y +CONFIG_SPL_OS_BOOT=y +CONFIG_SPL_RAM_SUPPORT=y +CONFIG_SPL_RAM_DEVICE=y +CONFIG_SPL_ATF=y +CONFIG_CMD_THOR_DOWNLOAD=y +CONFIG_CMD_MEMTEST=y +CONFIG_SYS_ALT_MEMTEST=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DFU=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_FPGA_LOADBP=y +CONFIG_CMD_FPGA_LOADP=y +CONFIG_CMD_FPGA_LOAD_SECURE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SDRAM=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_TIME=y +CONFIG_CMD_TIMER=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="zynqmp-m-a2197-01-revA" +CONFIG_ENV_IS_IN_FAT=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SCSI_AHCI=y +CONFIG_SATA_CEVA=y +CONFIG_CLK_ZYNQMP=y +CONFIG_DFU_RAM=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_FASTBOOT_CMD_OEM_FORMAT=y +CONFIG_FPGA_XILINX=y +CONFIG_FPGA_ZYNQMPPL=y +CONFIG_DM_GPIO=y +CONFIG_XILINX_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_CADENCE=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_MISC=y +CONFIG_I2C_EEPROM=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x0 +CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0 +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ZYNQ=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SF_DUAL_FLASH=y +CONFIG_SPI_FLASH_ISSI=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_PHY_MARVELL=y +CONFIG_PHY_NATSEMI=y +CONFIG_PHY_REALTEK=y +CONFIG_PHY_TI=y +CONFIG_PHY_VITESSE=y +CONFIG_PHY_FIXED=y +CONFIG_PHY_GIGE=y +CONFIG_MII=y +CONFIG_ZYNQ_GEM=y +CONFIG_SCSI=y +CONFIG_DM_SCSI=y +CONFIG_DEBUG_UART_ZYNQ=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_ZYNQ_SERIAL=y +CONFIG_SPI=y +CONFIG_ZYNQMP_GQSPI=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_XHCI_ZYNQMP=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GADGET=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_ULPI_VIEWPORT=y +CONFIG_USB_ULPI=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Xilinx" +CONFIG_USB_GADGET_VENDOR_NUM=0x03FD +CONFIG_USB_GADGET_PRODUCT_NUM=0x0300 +CONFIG_USB_FUNCTION_THOR=y +CONFIG_SPL_GZIP=y +CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/xilinx_zynqmp_m_a2197_02_revA_defconfig b/configs/xilinx_zynqmp_m_a2197_02_revA_defconfig new file mode 100644 index 0000000..c77faf5 --- /dev/null +++ b/configs/xilinx_zynqmp_m_a2197_02_revA_defconfig @@ -0,0 +1,115 @@ +CONFIG_ARM=y +CONFIG_ARCH_ZYNQMP=y +CONFIG_SYS_TEXT_BASE=0x8000000 +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_SPL=y +CONFIG_DEBUG_UART_BASE=0xff000000 +CONFIG_DEBUG_UART_CLOCK=100000000 +CONFIG_IDENT_STRING=" Xilinx ZynqMP SC for Versal" +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI_SUPPORT=y +CONFIG_ZYNQMP_USB=y +CONFIG_DEBUG_UART=y +CONFIG_AHCI=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_LOAD_FIT=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_BOARD_EARLY_INIT_R=y +CONFIG_SPL_OS_BOOT=y +CONFIG_SPL_RAM_SUPPORT=y +CONFIG_SPL_RAM_DEVICE=y +CONFIG_SPL_ATF=y +CONFIG_CMD_THOR_DOWNLOAD=y +CONFIG_CMD_MEMTEST=y +CONFIG_SYS_ALT_MEMTEST=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DFU=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_FPGA_LOADBP=y +CONFIG_CMD_FPGA_LOADP=y +CONFIG_CMD_FPGA_LOAD_SECURE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SDRAM=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_TIME=y +CONFIG_CMD_TIMER=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="zynqmp-m-a2197-02-revA" +CONFIG_ENV_IS_IN_FAT=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SCSI_AHCI=y +CONFIG_SATA_CEVA=y +CONFIG_CLK_ZYNQMP=y +CONFIG_DFU_RAM=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_FASTBOOT_CMD_OEM_FORMAT=y +CONFIG_FPGA_XILINX=y +CONFIG_FPGA_ZYNQMPPL=y +CONFIG_DM_GPIO=y +CONFIG_XILINX_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_CADENCE=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_MISC=y +CONFIG_I2C_EEPROM=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x0 +CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0 +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ZYNQ=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SF_DUAL_FLASH=y +CONFIG_SPI_FLASH_ISSI=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_PHY_MARVELL=y +CONFIG_PHY_NATSEMI=y +CONFIG_PHY_REALTEK=y +CONFIG_PHY_TI=y +CONFIG_PHY_VITESSE=y +CONFIG_PHY_FIXED=y +CONFIG_PHY_GIGE=y +CONFIG_MII=y +CONFIG_ZYNQ_GEM=y +CONFIG_SCSI=y +CONFIG_DM_SCSI=y +CONFIG_DEBUG_UART_ZYNQ=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_ZYNQ_SERIAL=y +CONFIG_SPI=y +CONFIG_ZYNQMP_GQSPI=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_XHCI_ZYNQMP=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GADGET=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_ULPI_VIEWPORT=y +CONFIG_USB_ULPI=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Xilinx" +CONFIG_USB_GADGET_VENDOR_NUM=0x03FD +CONFIG_USB_GADGET_PRODUCT_NUM=0x0300 +CONFIG_USB_FUNCTION_THOR=y +CONFIG_SPL_GZIP=y +CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/xilinx_zynqmp_m_a2197_03_revA_defconfig b/configs/xilinx_zynqmp_m_a2197_03_revA_defconfig new file mode 100644 index 0000000..3b57535 --- /dev/null +++ b/configs/xilinx_zynqmp_m_a2197_03_revA_defconfig @@ -0,0 +1,115 @@ +CONFIG_ARM=y +CONFIG_ARCH_ZYNQMP=y +CONFIG_SYS_TEXT_BASE=0x8000000 +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_SPL=y +CONFIG_DEBUG_UART_BASE=0xff000000 +CONFIG_DEBUG_UART_CLOCK=100000000 +CONFIG_IDENT_STRING=" Xilinx ZynqMP SC for Versal" +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI_SUPPORT=y +CONFIG_ZYNQMP_USB=y +CONFIG_DEBUG_UART=y +CONFIG_AHCI=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_LOAD_FIT=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_BOARD_EARLY_INIT_R=y +CONFIG_SPL_OS_BOOT=y +CONFIG_SPL_RAM_SUPPORT=y +CONFIG_SPL_RAM_DEVICE=y +CONFIG_SPL_ATF=y +CONFIG_CMD_THOR_DOWNLOAD=y +CONFIG_CMD_MEMTEST=y +CONFIG_SYS_ALT_MEMTEST=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DFU=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_FPGA_LOADBP=y +CONFIG_CMD_FPGA_LOADP=y +CONFIG_CMD_FPGA_LOAD_SECURE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SDRAM=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_TIME=y +CONFIG_CMD_TIMER=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="zynqmp-m-a2197-03-revA" +CONFIG_ENV_IS_IN_FAT=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SCSI_AHCI=y +CONFIG_SATA_CEVA=y +CONFIG_CLK_ZYNQMP=y +CONFIG_DFU_RAM=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_FASTBOOT_CMD_OEM_FORMAT=y +CONFIG_FPGA_XILINX=y +CONFIG_FPGA_ZYNQMPPL=y +CONFIG_DM_GPIO=y +CONFIG_XILINX_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_CADENCE=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_MISC=y +CONFIG_I2C_EEPROM=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x0 +CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0 +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ZYNQ=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SF_DUAL_FLASH=y +CONFIG_SPI_FLASH_ISSI=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_PHY_MARVELL=y +CONFIG_PHY_NATSEMI=y +CONFIG_PHY_REALTEK=y +CONFIG_PHY_TI=y +CONFIG_PHY_VITESSE=y +CONFIG_PHY_FIXED=y +CONFIG_PHY_GIGE=y +CONFIG_MII=y +CONFIG_ZYNQ_GEM=y +CONFIG_SCSI=y +CONFIG_DM_SCSI=y +CONFIG_DEBUG_UART_ZYNQ=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_ZYNQ_SERIAL=y +CONFIG_SPI=y +CONFIG_ZYNQMP_GQSPI=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_XHCI_ZYNQMP=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GADGET=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_ULPI_VIEWPORT=y +CONFIG_USB_ULPI=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Xilinx" +CONFIG_USB_GADGET_VENDOR_NUM=0x03FD +CONFIG_USB_GADGET_PRODUCT_NUM=0x0300 +CONFIG_USB_FUNCTION_THOR=y +CONFIG_SPL_GZIP=y +CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/xilinx_zynqmp_mini_nand_single_defconfig b/configs/xilinx_zynqmp_mini_nand_single_defconfig new file mode 100644 index 0000000..f2c2b17 --- /dev/null +++ b/configs/xilinx_zynqmp_mini_nand_single_defconfig @@ -0,0 +1,51 @@ +CONFIG_ARM=y +CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_mini_nand" +CONFIG_SYS_ICACHE_OFF=y +CONFIG_ARCH_ZYNQMP=y +CONFIG_SYS_TEXT_BASE=0x10000 +CONFIG_ENV_SIZE=0x80 +CONFIG_NR_DRAM_BANKS=1 +# CONFIG_CMD_ZYNQMP is not set +CONFIG_FIT=y +CONFIG_SUPPORT_RAW_INITRD=y +# CONFIG_BOARD_LATE_INIT is not set +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_BOARD_EARLY_INIT_R=y +# CONFIG_CMDLINE_EDITING is not set +# CONFIG_AUTO_COMPLETE is not set +# CONFIG_SYS_LONGHELP is not set +# CONFIG_AUTOBOOT is not set +# CONFIG_CMD_BDI is not set +# CONFIG_CMD_CONSOLE is not set +# CONFIG_CMD_BOOTD is not set +# CONFIG_CMD_BOOTM is not set +# CONFIG_CMD_BOOTI is not set +# CONFIG_CMD_GO is not set +# CONFIG_CMD_RUN is not set +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_EDITENV is not set +# CONFIG_CMD_SAVEENV is not set +# CONFIG_CMD_ENV_EXISTS is not set +# CONFIG_CMD_CRC32 is not set +# CONFIG_CMD_DM is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +# CONFIG_CMD_ECHO is not set +# CONFIG_CMD_ITEST is not set +# CONFIG_CMD_SOURCE is not set +# CONFIG_CMD_SETEXPR is not set +# CONFIG_MP is not set +# CONFIG_PARTITIONS is not set +CONFIG_OF_EMBED=y +CONFIG_DEFAULT_DEVICE_TREE="zynqmp-mini-nand" +# CONFIG_NET is not set +# CONFIG_DM_WARN is not set +# CONFIG_DM_DEVICE_REMOVE is not set +# CONFIG_MMC is not set +CONFIG_NAND=y +CONFIG_NAND_ARASAN=y +# CONFIG_EFI_LOADER is not set diff --git a/configs/xilinx_zynqmp_mini_qspi_defconfig b/configs/xilinx_zynqmp_mini_qspi_defconfig index 383f868..2afd746 100644 --- a/configs/xilinx_zynqmp_mini_qspi_defconfig +++ b/configs/xilinx_zynqmp_mini_qspi_defconfig @@ -55,11 +55,13 @@ CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y # CONFIG_MMC is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_ISSI=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_WINBOND=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_SPI=y CONFIG_ZYNQMP_GQSPI=y # CONFIG_EFI_LOADER is not set diff --git a/configs/xilinx_zynqmp_a2197_p_revA_defconfig b/configs/xilinx_zynqmp_p_a2197_00_revA_defconfig index d19c6b3..a7c4c79 100644 --- a/configs/xilinx_zynqmp_a2197_p_revA_defconfig +++ b/configs/xilinx_zynqmp_p_a2197_00_revA_defconfig @@ -43,7 +43,7 @@ CONFIG_CMD_TIME=y CONFIG_CMD_TIMER=y CONFIG_CMD_EXT4_WRITE=y CONFIG_SPL_OF_CONTROL=y -CONFIG_DEFAULT_DEVICE_TREE="zynqmp-a2197-p-revA" +CONFIG_DEFAULT_DEVICE_TREE="zynqmp-p-a2197-00-revA" CONFIG_ENV_IS_IN_FAT=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM=y diff --git a/configs/xilinx_zynqmp_zc1232_revA_defconfig b/configs/xilinx_zynqmp_zc1232_revA_defconfig index 255217d..c86ab5c 100644 --- a/configs/xilinx_zynqmp_zc1232_revA_defconfig +++ b/configs/xilinx_zynqmp_zc1232_revA_defconfig @@ -36,6 +36,7 @@ CONFIG_FPGA_ZYNQMPPL=y CONFIG_MISC=y # CONFIG_MMC is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_ISSI=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y diff --git a/configs/xilinx_zynqmp_zc1254_revA_defconfig b/configs/xilinx_zynqmp_zc1254_revA_defconfig index e058195..f1d127d 100644 --- a/configs/xilinx_zynqmp_zc1254_revA_defconfig +++ b/configs/xilinx_zynqmp_zc1254_revA_defconfig @@ -36,6 +36,7 @@ CONFIG_FPGA_ZYNQMPPL=y CONFIG_MISC=y # CONFIG_MMC is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_ISSI=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y diff --git a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig index bbf387a..dab2082 100644 --- a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig +++ b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig @@ -61,6 +61,7 @@ CONFIG_MMC_HS200_SUPPORT=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_ISSI=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y @@ -84,7 +85,6 @@ CONFIG_ZYNQMP_GQSPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_XHCI_ZYNQMP=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GADGET=y CONFIG_USB_DWC3_GENERIC=y diff --git a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig index d5434ee..a201057 100644 --- a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig +++ b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig @@ -75,7 +75,6 @@ CONFIG_SPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_XHCI_ZYNQMP=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GADGET=y CONFIG_USB_DWC3_GENERIC=y diff --git a/configs/xilinx_zynqmp_zc1751_xm017_dc3_defconfig b/configs/xilinx_zynqmp_zc1751_xm017_dc3_defconfig index 4ff5229..0d1e0f0 100644 --- a/configs/xilinx_zynqmp_zc1751_xm017_dc3_defconfig +++ b/configs/xilinx_zynqmp_zc1751_xm017_dc3_defconfig @@ -72,7 +72,6 @@ CONFIG_SPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_XHCI_ZYNQMP=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GADGET=y CONFIG_USB_DWC3_GENERIC=y diff --git a/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig b/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig index a5a7fc2..75aa35b 100644 --- a/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig +++ b/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig @@ -46,6 +46,7 @@ CONFIG_MISC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_ISSI=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y diff --git a/configs/xilinx_zynqmp_zcu100_revC_defconfig b/configs/xilinx_zynqmp_zcu100_revC_defconfig index fc917f0..335c8af 100644 --- a/configs/xilinx_zynqmp_zcu100_revC_defconfig +++ b/configs/xilinx_zynqmp_zcu100_revC_defconfig @@ -57,6 +57,7 @@ CONFIG_MISC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_ISSI=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y @@ -72,7 +73,6 @@ CONFIG_ZYNQ_SPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_XHCI_ZYNQMP=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GADGET=y CONFIG_USB_DWC3_GENERIC=y diff --git a/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig b/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig index b64956d..70e451c 100644 --- a/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig +++ b/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig @@ -75,6 +75,7 @@ CONFIG_MMC_UHS_SUPPORT=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_ISSI=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y @@ -100,7 +101,6 @@ CONFIG_ZYNQMP_GQSPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_XHCI_ZYNQMP=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GADGET=y CONFIG_USB_DWC3_GENERIC=y diff --git a/configs/xilinx_zynqmp_zcu102_revA_defconfig b/configs/xilinx_zynqmp_zcu102_revA_defconfig index 8b1a1ce..899da92 100644 --- a/configs/xilinx_zynqmp_zcu102_revA_defconfig +++ b/configs/xilinx_zynqmp_zcu102_revA_defconfig @@ -74,6 +74,7 @@ CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0 CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_ISSI=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y @@ -99,7 +100,6 @@ CONFIG_ZYNQMP_GQSPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_XHCI_ZYNQMP=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GADGET=y CONFIG_USB_DWC3_GENERIC=y diff --git a/configs/xilinx_zynqmp_zcu102_revB_defconfig b/configs/xilinx_zynqmp_zcu102_revB_defconfig index 2aab26d..7da2f89 100644 --- a/configs/xilinx_zynqmp_zcu102_revB_defconfig +++ b/configs/xilinx_zynqmp_zcu102_revB_defconfig @@ -74,6 +74,7 @@ CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0 CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_ISSI=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y @@ -99,7 +100,6 @@ CONFIG_ZYNQMP_GQSPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_XHCI_ZYNQMP=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GADGET=y CONFIG_USB_DWC3_GENERIC=y diff --git a/configs/xilinx_zynqmp_zcu104_revA_defconfig b/configs/xilinx_zynqmp_zcu104_revA_defconfig index 07e58b1..a0ba15c 100644 --- a/configs/xilinx_zynqmp_zcu104_revA_defconfig +++ b/configs/xilinx_zynqmp_zcu104_revA_defconfig @@ -58,6 +58,7 @@ CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0 CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_ISSI=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y @@ -83,7 +84,6 @@ CONFIG_ZYNQMP_GQSPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_XHCI_ZYNQMP=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GADGET=y CONFIG_USB_DWC3_GENERIC=y diff --git a/configs/xilinx_zynqmp_zcu104_revC_defconfig b/configs/xilinx_zynqmp_zcu104_revC_defconfig index 4829df6..cd45bd8 100644 --- a/configs/xilinx_zynqmp_zcu104_revC_defconfig +++ b/configs/xilinx_zynqmp_zcu104_revC_defconfig @@ -62,6 +62,7 @@ CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0 CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_ISSI=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y @@ -87,7 +88,6 @@ CONFIG_ZYNQMP_GQSPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_XHCI_ZYNQMP=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GADGET=y CONFIG_USB_DWC3_GENERIC=y diff --git a/configs/xilinx_zynqmp_zcu106_revA_defconfig b/configs/xilinx_zynqmp_zcu106_revA_defconfig index 72b3ce1..461e2ec 100644 --- a/configs/xilinx_zynqmp_zcu106_revA_defconfig +++ b/configs/xilinx_zynqmp_zcu106_revA_defconfig @@ -68,6 +68,7 @@ CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0 CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_ISSI=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y @@ -93,7 +94,6 @@ CONFIG_ZYNQMP_GQSPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_XHCI_ZYNQMP=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GADGET=y CONFIG_USB_DWC3_GENERIC=y diff --git a/configs/xilinx_zynqmp_zcu111_revA_defconfig b/configs/xilinx_zynqmp_zcu111_revA_defconfig index de739ed..4800d7d 100644 --- a/configs/xilinx_zynqmp_zcu111_revA_defconfig +++ b/configs/xilinx_zynqmp_zcu111_revA_defconfig @@ -60,6 +60,7 @@ CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0 CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_ISSI=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y @@ -85,7 +86,6 @@ CONFIG_ZYNQMP_GQSPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_XHCI_ZYNQMP=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GADGET=y CONFIG_USB_DWC3_GENERIC=y diff --git a/configs/xilinx_zynqmp_zcu1275_revA_defconfig b/configs/xilinx_zynqmp_zcu1275_revA_defconfig index d86c5d1..cd28dbe 100644 --- a/configs/xilinx_zynqmp_zcu1275_revA_defconfig +++ b/configs/xilinx_zynqmp_zcu1275_revA_defconfig @@ -36,6 +36,7 @@ CONFIG_FPGA_ZYNQMPPL=y CONFIG_MISC=y # CONFIG_MMC is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_ISSI=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y diff --git a/configs/xilinx_zynqmp_zcu1275_revB_defconfig b/configs/xilinx_zynqmp_zcu1275_revB_defconfig index 957b883..5030912 100644 --- a/configs/xilinx_zynqmp_zcu1275_revB_defconfig +++ b/configs/xilinx_zynqmp_zcu1275_revB_defconfig @@ -39,6 +39,7 @@ CONFIG_MISC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_ISSI=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y @@ -46,6 +47,10 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_WINBOND=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_PHY_MARVELL=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ90X1=y +CONFIG_PHY_XILINX_GMII2RGMII=y +CONFIG_MII=y CONFIG_ZYNQ_GEM=y CONFIG_DEBUG_UART_ZYNQ=y CONFIG_DEBUG_UART_ANNOUNCE=y diff --git a/configs/xilinx_zynqmp_zcu216_revA_defconfig b/configs/xilinx_zynqmp_zcu216_revA_defconfig new file mode 100644 index 0000000..4854ebcf --- /dev/null +++ b/configs/xilinx_zynqmp_zcu216_revA_defconfig @@ -0,0 +1,98 @@ +CONFIG_ARM=y +CONFIG_ARCH_ZYNQMP=y +CONFIG_SYS_TEXT_BASE=0x8000000 +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_SPL=y +CONFIG_DEBUG_UART_BASE=0xff000000 +CONFIG_DEBUG_UART_CLOCK=100000000 +CONFIG_ZYNQMP_USB=y +CONFIG_DEBUG_UART=y +CONFIG_AHCI=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_LOAD_FIT=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_SPL_OS_BOOT=y +CONFIG_SPL_RAM_SUPPORT=y +CONFIG_SPL_RAM_DEVICE=y +CONFIG_SPL_ATF=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DFU=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_FPGA_LOADBP=y +CONFIG_CMD_FPGA_LOADP=y +CONFIG_CMD_FPGA_LOAD_SECURE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_TIME=y +CONFIG_CMD_TIMER=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu111-revA" +CONFIG_ENV_IS_IN_FAT=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SCSI_AHCI=y +CONFIG_SATA_CEVA=y +CONFIG_CLK_ZYNQMP=y +CONFIG_DFU_RAM=y +CONFIG_FPGA_XILINX=y +CONFIG_FPGA_ZYNQMPPL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_CADENCE=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_MISC=y +CONFIG_I2C_EEPROM=y +CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0x20 +CONFIG_SYS_I2C_EEPROM_ADDR=0x0 +CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0 +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ZYNQ=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SF_DUAL_FLASH=y +CONFIG_SPI_FLASH_ISSI=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_PHY_MARVELL=y +CONFIG_PHY_NATSEMI=y +CONFIG_PHY_REALTEK=y +CONFIG_PHY_TI=y +CONFIG_PHY_VITESSE=y +CONFIG_PHY_FIXED=y +CONFIG_PHY_GIGE=y +CONFIG_MII=y +CONFIG_ZYNQ_GEM=y +CONFIG_SCSI=y +CONFIG_DM_SCSI=y +CONFIG_DEBUG_UART_ZYNQ=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_ZYNQ_SERIAL=y +CONFIG_SPI=y +CONFIG_ZYNQMP_GQSPI=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_XHCI_ZYNQMP=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GADGET=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_ULPI_VIEWPORT=y +CONFIG_USB_ULPI=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/zynq_cc108_defconfig b/configs/zynq_cc108_defconfig index 495c5df..3980c5e 100644 --- a/configs/zynq_cc108_defconfig +++ b/configs/zynq_cc108_defconfig @@ -18,6 +18,7 @@ CONFIG_USE_PREBOOT=y CONFIG_SPL_STACK_R=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000 +# CONFIG_BOOTM_NETBSD is not set CONFIG_CMD_DFU=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y diff --git a/configs/zynq_cse_qspi_defconfig b/configs/zynq_cse_qspi_defconfig index 0cc6976..f638556 100644 --- a/configs/zynq_cse_qspi_defconfig +++ b/configs/zynq_cse_qspi_defconfig @@ -32,6 +32,7 @@ CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000 # CONFIG_CMD_BOOTD is not set # CONFIG_CMD_BOOTM is not set # CONFIG_CMD_ELF is not set +# CONFIG_CMD_FDT is not set # CONFIG_CMD_GO is not set # CONFIG_CMD_RUN is not set # CONFIG_CMD_IMI is not set @@ -41,6 +42,7 @@ CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000 # CONFIG_CMD_IMPORTENV is not set # CONFIG_CMD_EDITENV is not set # CONFIG_CMD_SAVEENV is not set +# CONFIG_CMD_ENV_EXISTS is not set # CONFIG_CMD_CRC32 is not set # CONFIG_CMD_CLK is not set # CONFIG_CMD_DM is not set @@ -67,6 +69,7 @@ CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_WINBOND=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_DEBUG_UART_ARM_DCC=y CONFIG_ZYNQ_QSPI=y # CONFIG_EFI_LOADER is not set diff --git a/configs/zynq_dlc20_rev1_0_defconfig b/configs/zynq_dlc20_rev1_0_defconfig index 00d1a59..9272a3f 100644 --- a/configs/zynq_dlc20_rev1_0_defconfig +++ b/configs/zynq_dlc20_rev1_0_defconfig @@ -16,11 +16,11 @@ CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_USE_PREBOOT=y -CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_STACK_R=y CONFIG_SPL_OS_BOOT=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000 +# CONFIG_BOOTM_NETBSD is not set CONFIG_CMD_THOR_DOWNLOAD=y CONFIG_CMD_DFU=y # CONFIG_CMD_FLASH is not set diff --git a/configs/zynq_microzed_defconfig b/configs/zynq_microzed_defconfig index 751d373..3724b8e 100644 --- a/configs/zynq_microzed_defconfig +++ b/configs/zynq_microzed_defconfig @@ -16,6 +16,7 @@ CONFIG_SPL_STACK_R=y CONFIG_SPL_OS_BOOT=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000 +# CONFIG_BOOTM_NETBSD is not set CONFIG_CMD_THOR_DOWNLOAD=y CONFIG_CMD_DFU=y # CONFIG_CMD_FLASH is not set diff --git a/configs/zynq_minized_defconfig b/configs/zynq_minized_defconfig index d9657f9..e3acee1 100644 --- a/configs/zynq_minized_defconfig +++ b/configs/zynq_minized_defconfig @@ -16,6 +16,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_USE_PREBOOT=y CONFIG_SPL_STACK_R=y CONFIG_SPL_OS_BOOT=y +# CONFIG_BOOTM_NETBSD is not set CONFIG_CMD_THOR_DOWNLOAD=y CONFIG_CMD_DFU=y # CONFIG_CMD_FLASH is not set diff --git a/configs/zynq_picozed_defconfig b/configs/zynq_picozed_defconfig index c72307a..b550b90 100644 --- a/configs/zynq_picozed_defconfig +++ b/configs/zynq_picozed_defconfig @@ -10,6 +10,7 @@ CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds" CONFIG_USE_PREBOOT=y CONFIG_SPL_STACK_R=y CONFIG_SPL_OS_BOOT=y +# CONFIG_BOOTM_NETBSD is not set CONFIG_CMD_THOR_DOWNLOAD=y CONFIG_CMD_DFU=y # CONFIG_CMD_FLASH is not set diff --git a/configs/zynq_virt_defconfig b/configs/zynq_virt_defconfig index 58ce970..807e71f 100644 --- a/configs/zynq_virt_defconfig +++ b/configs/zynq_virt_defconfig @@ -16,6 +16,7 @@ CONFIG_SPL_STACK_R=y CONFIG_SPL_OS_BOOT=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000 +# CONFIG_BOOTM_NETBSD is not set CONFIG_CMD_THOR_DOWNLOAD=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_DFU=y diff --git a/configs/zynq_z_turn_defconfig b/configs/zynq_z_turn_defconfig index 799277c..a231dca 100644 --- a/configs/zynq_z_turn_defconfig +++ b/configs/zynq_z_turn_defconfig @@ -19,6 +19,7 @@ CONFIG_SPL_STACK_R=y CONFIG_SPL_OS_BOOT=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000 +# CONFIG_BOOTM_NETBSD is not set CONFIG_CMD_THOR_DOWNLOAD=y CONFIG_CMD_DFU=y # CONFIG_CMD_FLASH is not set diff --git a/configs/zynq_zc702_defconfig b/configs/zynq_zc702_defconfig index 74e8b3e..f64bf18 100644 --- a/configs/zynq_zc702_defconfig +++ b/configs/zynq_zc702_defconfig @@ -20,6 +20,7 @@ CONFIG_SPL_STACK_R=y CONFIG_SPL_OS_BOOT=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000 +# CONFIG_BOOTM_NETBSD is not set CONFIG_CMD_THOR_DOWNLOAD=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_DFU=y diff --git a/configs/zynq_zc706_defconfig b/configs/zynq_zc706_defconfig index f831039..36a9204 100644 --- a/configs/zynq_zc706_defconfig +++ b/configs/zynq_zc706_defconfig @@ -23,6 +23,7 @@ CONFIG_SPL_FPGA_SUPPORT=y CONFIG_SPL_OS_BOOT=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000 +# CONFIG_BOOTM_NETBSD is not set CONFIG_CMD_THOR_DOWNLOAD=y CONFIG_CMD_DFU=y # CONFIG_CMD_FLASH is not set diff --git a/configs/zynq_zc770_xm010_defconfig b/configs/zynq_zc770_xm010_defconfig index 301bc2d..fff8ddc 100644 --- a/configs/zynq_zc770_xm010_defconfig +++ b/configs/zynq_zc770_xm010_defconfig @@ -20,6 +20,7 @@ CONFIG_SPL_STACK_R=y CONFIG_SPL_OS_BOOT=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000 +# CONFIG_BOOTM_NETBSD is not set # CONFIG_CMD_FLASH is not set CONFIG_CMD_FPGA_LOADBP=y CONFIG_CMD_FPGA_LOADFS=y diff --git a/configs/zynq_zc770_xm011_defconfig b/configs/zynq_zc770_xm011_defconfig index 8bc49ea..72fceeb 100644 --- a/configs/zynq_zc770_xm011_defconfig +++ b/configs/zynq_zc770_xm011_defconfig @@ -19,6 +19,7 @@ CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_USE_PREBOOT=y CONFIG_SPL_STACK_R=y CONFIG_SPL_OS_BOOT=y +# CONFIG_BOOTM_NETBSD is not set # CONFIG_CMD_FLASH is not set CONFIG_CMD_FPGA_LOADBP=y CONFIG_CMD_FPGA_LOADFS=y diff --git a/configs/zynq_zc770_xm011_x16_defconfig b/configs/zynq_zc770_xm011_x16_defconfig index 70429a2..279dfed 100644 --- a/configs/zynq_zc770_xm011_x16_defconfig +++ b/configs/zynq_zc770_xm011_x16_defconfig @@ -19,6 +19,7 @@ CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_USE_PREBOOT=y CONFIG_SPL_STACK_R=y CONFIG_SPL_OS_BOOT=y +# CONFIG_BOOTM_NETBSD is not set # CONFIG_CMD_FLASH is not set CONFIG_CMD_FPGA_LOADBP=y CONFIG_CMD_FPGA_LOADFS=y diff --git a/configs/zynq_zc770_xm012_defconfig b/configs/zynq_zc770_xm012_defconfig index 78cdd9c..997836c 100644 --- a/configs/zynq_zc770_xm012_defconfig +++ b/configs/zynq_zc770_xm012_defconfig @@ -16,6 +16,7 @@ CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_USE_PREBOOT=y CONFIG_SPL_STACK_R=y CONFIG_SPL_OS_BOOT=y +# CONFIG_BOOTM_NETBSD is not set CONFIG_CMD_IMLS=y CONFIG_CMD_FPGA_LOADBP=y CONFIG_CMD_FPGA_LOADFS=y diff --git a/configs/zynq_zc770_xm013_defconfig b/configs/zynq_zc770_xm013_defconfig index c667878..674a715 100644 --- a/configs/zynq_zc770_xm013_defconfig +++ b/configs/zynq_zc770_xm013_defconfig @@ -18,6 +18,7 @@ CONFIG_SPL_STACK_R=y CONFIG_SPL_OS_BOOT=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000 +# CONFIG_BOOTM_NETBSD is not set # CONFIG_CMD_FLASH is not set CONFIG_CMD_FPGA_LOADBP=y CONFIG_CMD_FPGA_LOADFS=y diff --git a/configs/zynq_zed_defconfig b/configs/zynq_zed_defconfig index 38bf3e4..cfc637b 100644 --- a/configs/zynq_zed_defconfig +++ b/configs/zynq_zed_defconfig @@ -19,6 +19,7 @@ CONFIG_SPL_STACK_R=y CONFIG_SPL_OS_BOOT=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000 +# CONFIG_BOOTM_NETBSD is not set CONFIG_CMD_THOR_DOWNLOAD=y CONFIG_CMD_DFU=y # CONFIG_CMD_FLASH is not set diff --git a/configs/zynq_zybo_defconfig b/configs/zynq_zybo_defconfig index 71d1638..3eaa4b4 100644 --- a/configs/zynq_zybo_defconfig +++ b/configs/zynq_zybo_defconfig @@ -19,6 +19,7 @@ CONFIG_SPL_STACK_R=y CONFIG_SPL_OS_BOOT=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000 +# CONFIG_BOOTM_NETBSD is not set CONFIG_CMD_THOR_DOWNLOAD=y CONFIG_CMD_DFU=y # CONFIG_CMD_FLASH is not set diff --git a/configs/zynq_zybo_z7_defconfig b/configs/zynq_zybo_z7_defconfig index 0cc525c..bb193e4 100644 --- a/configs/zynq_zybo_z7_defconfig +++ b/configs/zynq_zybo_z7_defconfig @@ -19,6 +19,7 @@ CONFIG_SPL_STACK_R=y CONFIG_SPL_OS_BOOT=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000 +# CONFIG_BOOTM_NETBSD is not set CONFIG_CMD_THOR_DOWNLOAD=y CONFIG_CMD_DFU=y # CONFIG_CMD_FLASH is not set diff --git a/doc/build/index.rst b/doc/build/index.rst new file mode 100644 index 0000000..e4e3411 --- /dev/null +++ b/doc/build/index.rst @@ -0,0 +1,9 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Build U-Boot +============ + +.. toctree:: + :maxdepth: 2 + + tools diff --git a/doc/build/tools.rst b/doc/build/tools.rst new file mode 100644 index 0000000..c06f915 --- /dev/null +++ b/doc/build/tools.rst @@ -0,0 +1,47 @@ +.. SPDX-License-Identifier: GPL-2.0+ +.. sectionauthor:: Bin Meng <bmeng.cn@gmail.com> + +Host tools +========== + +Building tools for Linux +------------------------ + +To allow distributions to distribute all possible tools in a generic way, +avoiding the need of specific tools building for each machine, a tools only +defconfig file is provided. + +Using this, we can build the tools by doing:: + + $ make tools-only_defconfig + $ make tools-only + +Building tools for Windows +-------------------------- +If you wish to generate Windows versions of the utilities in the tools directory +you can use MSYS2, a software distro and building platform for Windows. + +Download the MSYS2 installer from https://www.msys2.org. Make sure you have +installed all required packages below in order to build these host tools:: + + * gcc (9.1.0) + * make (4.2.1) + * bison (3.4.2) + * diffutils (3.7) + * openssl-devel (1.1.1.d) + +Note the version numbers in these parentheses above are the package versions +at the time being when writing this document. The MSYS2 installer tested is +http://repo.msys2.org/distrib/x86_64/msys2-x86_64-20190524.exe. + +There are 3 MSYS subsystems installed: MSYS2, MinGW32 and MinGW64. Each +subsystem provides an environment to build Windows applications. The MSYS2 +environment is for building POSIX compliant software on Windows using an +emulation layer. The MinGW32/64 subsystems are for building native Windows +applications using a linux toolchain (gcc, bash, etc), targeting respectively +32 and 64 bit Windows. + +Launch the MSYS2 shell of the MSYS2 environment, and do the following:: + + $ make tools-only_defconfig + $ make tools-only NO_SDL=1 diff --git a/doc/device-tree-bindings/memory-controller/k3-j721e-ddrss.txt b/doc/device-tree-bindings/memory-controller/k3-j721e-ddrss.txt new file mode 100644 index 0000000..873a0e7 --- /dev/null +++ b/doc/device-tree-bindings/memory-controller/k3-j721e-ddrss.txt @@ -0,0 +1,2241 @@ +Texas Instruments' K3 J721E DDRSS +================================== +The J721E DDR subsystem comprises DDR controller, DDR PHY and wrapper +logic to integrate these blocks in the device. The DDR subsystem is +used to provide an interface to external SDRAM devices which can be +utilized for storing program or data. + +DDRSS device node: +================== +Required properties: +-------------------- +- compatible: Shall be: "ti,j721e-ddrss" +- reg-names cfg - Map the controller configuration region + ctrl_mmr_lp4 - Map LP4 register region in ctrl mmr +- reg: Contains the register map per reg-names. +- power-domains: Should contain two entries: + - an entry to TISCI DDR CFG device + - an entry to TISCI DDR DATA. + This property is as per the binding, + doc/device-tree-bindings/power/ti,sci-pm-domain.txt +- clocks: Should contain two entries. + - An entry to DDRSS clock + - An rntry to SoC bypass clock + Should be defined as per the appropriate clock bindings + consumer usage in + doc/device-tree-bindings/clock/ti,sci-clk.txt +- ti,ddr-freq1: First frequency set point +- ti,ddr-freq2: Second frequency set point +- ti,ddr-fhs-cnt: Number of times to communicate to DDR for frequency handshake. +- ti,ctl-data: An array containing the controller settings. +- ti,pi-data: An array containing the phy independent block settings +- ti,phy-data: An array containing the ddr phy settings. + +Example (J721E): +================ + +memorycontroller: memorycontroller@0298e000 { + compatible = "ti,j721e-ddrss"; + reg = <0x0 0x02990000 0x0 0x4000>, + <0x0 0x0114000 0x0 0x100>; + reg-names = "cfg", "ctrl_mmr_lp4"; + power-domains = <&k3_pds 47 TI_SCI_PD_SHARED>, + <&k3_pds 90 TI_SCI_PD_SHARED>; + clocks = <&k3_clks 47 2>, <&k3_clks 30 9>; + ti,ddr-freq1 = <DDRSS_PLL_FREQUENCY_1>; + ti,ddr-freq2 = <DDRSS_PLL_FREQUENCY_2>; + ti,ddr-fhs-cnt = <DDRSS_PLL_FHS_CNT>; + + u-boot,dm-spl; + + ti,ctl-data = < + DDRSS_CTL_00_DATA + DDRSS_CTL_01_DATA + DDRSS_CTL_02_DATA + DDRSS_CTL_03_DATA + DDRSS_CTL_04_DATA + DDRSS_CTL_05_DATA + DDRSS_CTL_06_DATA + DDRSS_CTL_07_DATA + DDRSS_CTL_08_DATA + DDRSS_CTL_09_DATA + DDRSS_CTL_10_DATA + DDRSS_CTL_11_DATA + DDRSS_CTL_12_DATA + DDRSS_CTL_13_DATA + DDRSS_CTL_14_DATA + DDRSS_CTL_15_DATA + DDRSS_CTL_16_DATA + DDRSS_CTL_17_DATA + DDRSS_CTL_18_DATA + DDRSS_CTL_19_DATA + DDRSS_CTL_20_DATA + DDRSS_CTL_21_DATA + DDRSS_CTL_22_DATA + DDRSS_CTL_23_DATA + DDRSS_CTL_24_DATA + DDRSS_CTL_25_DATA + DDRSS_CTL_26_DATA + DDRSS_CTL_27_DATA + DDRSS_CTL_28_DATA + DDRSS_CTL_29_DATA + DDRSS_CTL_30_DATA + DDRSS_CTL_31_DATA + DDRSS_CTL_32_DATA + DDRSS_CTL_33_DATA + DDRSS_CTL_34_DATA + DDRSS_CTL_35_DATA + DDRSS_CTL_36_DATA + DDRSS_CTL_37_DATA + DDRSS_CTL_38_DATA + DDRSS_CTL_39_DATA + DDRSS_CTL_40_DATA + DDRSS_CTL_41_DATA + DDRSS_CTL_42_DATA + DDRSS_CTL_43_DATA + DDRSS_CTL_44_DATA + DDRSS_CTL_45_DATA + DDRSS_CTL_46_DATA + DDRSS_CTL_47_DATA + DDRSS_CTL_48_DATA + DDRSS_CTL_49_DATA + DDRSS_CTL_50_DATA + DDRSS_CTL_51_DATA + DDRSS_CTL_52_DATA + DDRSS_CTL_53_DATA + DDRSS_CTL_54_DATA + DDRSS_CTL_55_DATA + DDRSS_CTL_56_DATA + DDRSS_CTL_57_DATA + DDRSS_CTL_58_DATA + DDRSS_CTL_59_DATA + DDRSS_CTL_60_DATA + DDRSS_CTL_61_DATA + DDRSS_CTL_62_DATA + DDRSS_CTL_63_DATA + DDRSS_CTL_64_DATA + DDRSS_CTL_65_DATA + DDRSS_CTL_66_DATA + DDRSS_CTL_67_DATA + DDRSS_CTL_68_DATA + DDRSS_CTL_69_DATA + DDRSS_CTL_70_DATA + DDRSS_CTL_71_DATA + DDRSS_CTL_72_DATA + DDRSS_CTL_73_DATA + DDRSS_CTL_74_DATA + DDRSS_CTL_75_DATA + DDRSS_CTL_76_DATA + DDRSS_CTL_77_DATA + DDRSS_CTL_78_DATA + DDRSS_CTL_79_DATA + DDRSS_CTL_80_DATA + DDRSS_CTL_81_DATA + DDRSS_CTL_82_DATA + DDRSS_CTL_83_DATA + DDRSS_CTL_84_DATA + DDRSS_CTL_85_DATA + DDRSS_CTL_86_DATA + DDRSS_CTL_87_DATA + DDRSS_CTL_88_DATA + DDRSS_CTL_89_DATA + DDRSS_CTL_90_DATA + DDRSS_CTL_91_DATA + DDRSS_CTL_92_DATA + DDRSS_CTL_93_DATA + DDRSS_CTL_94_DATA + DDRSS_CTL_95_DATA + DDRSS_CTL_96_DATA + DDRSS_CTL_97_DATA + DDRSS_CTL_98_DATA + DDRSS_CTL_99_DATA + DDRSS_CTL_100_DATA + DDRSS_CTL_101_DATA + DDRSS_CTL_102_DATA + DDRSS_CTL_103_DATA + DDRSS_CTL_104_DATA + DDRSS_CTL_105_DATA + DDRSS_CTL_106_DATA + DDRSS_CTL_107_DATA + DDRSS_CTL_108_DATA + DDRSS_CTL_109_DATA + DDRSS_CTL_110_DATA + DDRSS_CTL_111_DATA + DDRSS_CTL_112_DATA + DDRSS_CTL_113_DATA + DDRSS_CTL_114_DATA + DDRSS_CTL_115_DATA + DDRSS_CTL_116_DATA + DDRSS_CTL_117_DATA + DDRSS_CTL_118_DATA + DDRSS_CTL_119_DATA + DDRSS_CTL_120_DATA + DDRSS_CTL_121_DATA + DDRSS_CTL_122_DATA + DDRSS_CTL_123_DATA + DDRSS_CTL_124_DATA + DDRSS_CTL_125_DATA + DDRSS_CTL_126_DATA + DDRSS_CTL_127_DATA + DDRSS_CTL_128_DATA + DDRSS_CTL_129_DATA + DDRSS_CTL_130_DATA + DDRSS_CTL_131_DATA + DDRSS_CTL_132_DATA + DDRSS_CTL_133_DATA + DDRSS_CTL_134_DATA + DDRSS_CTL_135_DATA + DDRSS_CTL_136_DATA + DDRSS_CTL_137_DATA + DDRSS_CTL_138_DATA + DDRSS_CTL_139_DATA + DDRSS_CTL_140_DATA + DDRSS_CTL_141_DATA + DDRSS_CTL_142_DATA + DDRSS_CTL_143_DATA + DDRSS_CTL_144_DATA + DDRSS_CTL_145_DATA + DDRSS_CTL_146_DATA + DDRSS_CTL_147_DATA + DDRSS_CTL_148_DATA + DDRSS_CTL_149_DATA + DDRSS_CTL_150_DATA + DDRSS_CTL_151_DATA + DDRSS_CTL_152_DATA + DDRSS_CTL_153_DATA + DDRSS_CTL_154_DATA + DDRSS_CTL_155_DATA + DDRSS_CTL_156_DATA + DDRSS_CTL_157_DATA + DDRSS_CTL_158_DATA + DDRSS_CTL_159_DATA + DDRSS_CTL_160_DATA + DDRSS_CTL_161_DATA + DDRSS_CTL_162_DATA + DDRSS_CTL_163_DATA + DDRSS_CTL_164_DATA + DDRSS_CTL_165_DATA + DDRSS_CTL_166_DATA + DDRSS_CTL_167_DATA + DDRSS_CTL_168_DATA + DDRSS_CTL_169_DATA + DDRSS_CTL_170_DATA + DDRSS_CTL_171_DATA + DDRSS_CTL_172_DATA + DDRSS_CTL_173_DATA + DDRSS_CTL_174_DATA + DDRSS_CTL_175_DATA + DDRSS_CTL_176_DATA + DDRSS_CTL_177_DATA + DDRSS_CTL_178_DATA + DDRSS_CTL_179_DATA + DDRSS_CTL_180_DATA + DDRSS_CTL_181_DATA + DDRSS_CTL_182_DATA + DDRSS_CTL_183_DATA + DDRSS_CTL_184_DATA + DDRSS_CTL_185_DATA + DDRSS_CTL_186_DATA + DDRSS_CTL_187_DATA + DDRSS_CTL_188_DATA + DDRSS_CTL_189_DATA + DDRSS_CTL_190_DATA + DDRSS_CTL_191_DATA + DDRSS_CTL_192_DATA + DDRSS_CTL_193_DATA + DDRSS_CTL_194_DATA + DDRSS_CTL_195_DATA + DDRSS_CTL_196_DATA + DDRSS_CTL_197_DATA + DDRSS_CTL_198_DATA + DDRSS_CTL_199_DATA + DDRSS_CTL_200_DATA + DDRSS_CTL_201_DATA + DDRSS_CTL_202_DATA + DDRSS_CTL_203_DATA + DDRSS_CTL_204_DATA + DDRSS_CTL_205_DATA + DDRSS_CTL_206_DATA + DDRSS_CTL_207_DATA + DDRSS_CTL_208_DATA + DDRSS_CTL_209_DATA + DDRSS_CTL_210_DATA + DDRSS_CTL_211_DATA + DDRSS_CTL_212_DATA + DDRSS_CTL_213_DATA + DDRSS_CTL_214_DATA + DDRSS_CTL_215_DATA + DDRSS_CTL_216_DATA + DDRSS_CTL_217_DATA + DDRSS_CTL_218_DATA + DDRSS_CTL_219_DATA + DDRSS_CTL_220_DATA + DDRSS_CTL_221_DATA + DDRSS_CTL_222_DATA + DDRSS_CTL_223_DATA + DDRSS_CTL_224_DATA + DDRSS_CTL_225_DATA + DDRSS_CTL_226_DATA + DDRSS_CTL_227_DATA + DDRSS_CTL_228_DATA + DDRSS_CTL_229_DATA + DDRSS_CTL_230_DATA + DDRSS_CTL_231_DATA + DDRSS_CTL_232_DATA + DDRSS_CTL_233_DATA + DDRSS_CTL_234_DATA + DDRSS_CTL_235_DATA + DDRSS_CTL_236_DATA + DDRSS_CTL_237_DATA + DDRSS_CTL_238_DATA + DDRSS_CTL_239_DATA + DDRSS_CTL_240_DATA + DDRSS_CTL_241_DATA + DDRSS_CTL_242_DATA + DDRSS_CTL_243_DATA + DDRSS_CTL_244_DATA + DDRSS_CTL_245_DATA + DDRSS_CTL_246_DATA + DDRSS_CTL_247_DATA + DDRSS_CTL_248_DATA + DDRSS_CTL_249_DATA + DDRSS_CTL_250_DATA + DDRSS_CTL_251_DATA + DDRSS_CTL_252_DATA + DDRSS_CTL_253_DATA + DDRSS_CTL_254_DATA + DDRSS_CTL_255_DATA + DDRSS_CTL_256_DATA + DDRSS_CTL_257_DATA + DDRSS_CTL_258_DATA + DDRSS_CTL_259_DATA + DDRSS_CTL_260_DATA + DDRSS_CTL_261_DATA + DDRSS_CTL_262_DATA + DDRSS_CTL_263_DATA + DDRSS_CTL_264_DATA + DDRSS_CTL_265_DATA + DDRSS_CTL_266_DATA + DDRSS_CTL_267_DATA + DDRSS_CTL_268_DATA + DDRSS_CTL_269_DATA + DDRSS_CTL_270_DATA + DDRSS_CTL_271_DATA + DDRSS_CTL_272_DATA + DDRSS_CTL_273_DATA + DDRSS_CTL_274_DATA + DDRSS_CTL_275_DATA + DDRSS_CTL_276_DATA + DDRSS_CTL_277_DATA + DDRSS_CTL_278_DATA + DDRSS_CTL_279_DATA + DDRSS_CTL_280_DATA + DDRSS_CTL_281_DATA + DDRSS_CTL_282_DATA + DDRSS_CTL_283_DATA + DDRSS_CTL_284_DATA + DDRSS_CTL_285_DATA + DDRSS_CTL_286_DATA + DDRSS_CTL_287_DATA + DDRSS_CTL_288_DATA + DDRSS_CTL_289_DATA + DDRSS_CTL_290_DATA + DDRSS_CTL_291_DATA + DDRSS_CTL_292_DATA + DDRSS_CTL_293_DATA + DDRSS_CTL_294_DATA + DDRSS_CTL_295_DATA + DDRSS_CTL_296_DATA + DDRSS_CTL_297_DATA + DDRSS_CTL_298_DATA + DDRSS_CTL_299_DATA + DDRSS_CTL_300_DATA + DDRSS_CTL_301_DATA + DDRSS_CTL_302_DATA + DDRSS_CTL_303_DATA + DDRSS_CTL_304_DATA + DDRSS_CTL_305_DATA + DDRSS_CTL_306_DATA + DDRSS_CTL_307_DATA + DDRSS_CTL_308_DATA + DDRSS_CTL_309_DATA + DDRSS_CTL_310_DATA + DDRSS_CTL_311_DATA + DDRSS_CTL_312_DATA + DDRSS_CTL_313_DATA + DDRSS_CTL_314_DATA + DDRSS_CTL_315_DATA + DDRSS_CTL_316_DATA + DDRSS_CTL_317_DATA + DDRSS_CTL_318_DATA + DDRSS_CTL_319_DATA + DDRSS_CTL_320_DATA + DDRSS_CTL_321_DATA + DDRSS_CTL_322_DATA + DDRSS_CTL_323_DATA + DDRSS_CTL_324_DATA + DDRSS_CTL_325_DATA + DDRSS_CTL_326_DATA + DDRSS_CTL_327_DATA + DDRSS_CTL_328_DATA + DDRSS_CTL_329_DATA + DDRSS_CTL_330_DATA + DDRSS_CTL_331_DATA + DDRSS_CTL_332_DATA + DDRSS_CTL_333_DATA + DDRSS_CTL_334_DATA + DDRSS_CTL_335_DATA + DDRSS_CTL_336_DATA + DDRSS_CTL_337_DATA + DDRSS_CTL_338_DATA + DDRSS_CTL_339_DATA + DDRSS_CTL_340_DATA + DDRSS_CTL_341_DATA + DDRSS_CTL_342_DATA + DDRSS_CTL_343_DATA + DDRSS_CTL_344_DATA + DDRSS_CTL_345_DATA + DDRSS_CTL_346_DATA + DDRSS_CTL_347_DATA + DDRSS_CTL_348_DATA + DDRSS_CTL_349_DATA + DDRSS_CTL_350_DATA + DDRSS_CTL_351_DATA + DDRSS_CTL_352_DATA + DDRSS_CTL_353_DATA + DDRSS_CTL_354_DATA + DDRSS_CTL_355_DATA + DDRSS_CTL_356_DATA + DDRSS_CTL_357_DATA + DDRSS_CTL_358_DATA + DDRSS_CTL_359_DATA + DDRSS_CTL_360_DATA + DDRSS_CTL_361_DATA + DDRSS_CTL_362_DATA + DDRSS_CTL_363_DATA + DDRSS_CTL_364_DATA + DDRSS_CTL_365_DATA + DDRSS_CTL_366_DATA + DDRSS_CTL_367_DATA + DDRSS_CTL_368_DATA + DDRSS_CTL_369_DATA + DDRSS_CTL_370_DATA + DDRSS_CTL_371_DATA + DDRSS_CTL_372_DATA + DDRSS_CTL_373_DATA + DDRSS_CTL_374_DATA + DDRSS_CTL_375_DATA + DDRSS_CTL_376_DATA + DDRSS_CTL_377_DATA + DDRSS_CTL_378_DATA + DDRSS_CTL_379_DATA + DDRSS_CTL_380_DATA + DDRSS_CTL_381_DATA + DDRSS_CTL_382_DATA + DDRSS_CTL_383_DATA + DDRSS_CTL_384_DATA + DDRSS_CTL_385_DATA + DDRSS_CTL_386_DATA + DDRSS_CTL_387_DATA + DDRSS_CTL_388_DATA + DDRSS_CTL_389_DATA + DDRSS_CTL_390_DATA + DDRSS_CTL_391_DATA + DDRSS_CTL_392_DATA + DDRSS_CTL_393_DATA + DDRSS_CTL_394_DATA + DDRSS_CTL_395_DATA + DDRSS_CTL_396_DATA + DDRSS_CTL_397_DATA + DDRSS_CTL_398_DATA + DDRSS_CTL_399_DATA + DDRSS_CTL_400_DATA + DDRSS_CTL_401_DATA + DDRSS_CTL_402_DATA + DDRSS_CTL_403_DATA + DDRSS_CTL_404_DATA + DDRSS_CTL_405_DATA + DDRSS_CTL_406_DATA + DDRSS_CTL_407_DATA + DDRSS_CTL_408_DATA + DDRSS_CTL_409_DATA + DDRSS_CTL_410_DATA + DDRSS_CTL_411_DATA + DDRSS_CTL_412_DATA + DDRSS_CTL_413_DATA + DDRSS_CTL_414_DATA + DDRSS_CTL_415_DATA + DDRSS_CTL_416_DATA + DDRSS_CTL_417_DATA + DDRSS_CTL_418_DATA + DDRSS_CTL_419_DATA + DDRSS_CTL_420_DATA + DDRSS_CTL_421_DATA + DDRSS_CTL_422_DATA + DDRSS_CTL_423_DATA + DDRSS_CTL_424_DATA + DDRSS_CTL_425_DATA + DDRSS_CTL_426_DATA + DDRSS_CTL_427_DATA + DDRSS_CTL_428_DATA + DDRSS_CTL_429_DATA + DDRSS_CTL_430_DATA + DDRSS_CTL_431_DATA + DDRSS_CTL_432_DATA + DDRSS_CTL_433_DATA + DDRSS_CTL_434_DATA + DDRSS_CTL_435_DATA + DDRSS_CTL_436_DATA + DDRSS_CTL_437_DATA + DDRSS_CTL_438_DATA + DDRSS_CTL_439_DATA + DDRSS_CTL_440_DATA + DDRSS_CTL_441_DATA + DDRSS_CTL_442_DATA + DDRSS_CTL_443_DATA + DDRSS_CTL_444_DATA + DDRSS_CTL_445_DATA + DDRSS_CTL_446_DATA + DDRSS_CTL_447_DATA + DDRSS_CTL_448_DATA + DDRSS_CTL_449_DATA + DDRSS_CTL_450_DATA + DDRSS_CTL_451_DATA + DDRSS_CTL_452_DATA + DDRSS_CTL_453_DATA + DDRSS_CTL_454_DATA + DDRSS_CTL_455_DATA + DDRSS_CTL_456_DATA + DDRSS_CTL_457_DATA + DDRSS_CTL_458_DATA + >; + + ti,pi-data = < + DDRSS_PI_00_DATA + DDRSS_PI_01_DATA + DDRSS_PI_02_DATA + DDRSS_PI_03_DATA + DDRSS_PI_04_DATA + DDRSS_PI_05_DATA + DDRSS_PI_06_DATA + DDRSS_PI_07_DATA + DDRSS_PI_08_DATA + DDRSS_PI_09_DATA + DDRSS_PI_10_DATA + DDRSS_PI_11_DATA + DDRSS_PI_12_DATA + DDRSS_PI_13_DATA + DDRSS_PI_14_DATA + DDRSS_PI_15_DATA + DDRSS_PI_16_DATA + DDRSS_PI_17_DATA + DDRSS_PI_18_DATA + DDRSS_PI_19_DATA + DDRSS_PI_20_DATA + DDRSS_PI_21_DATA + DDRSS_PI_22_DATA + DDRSS_PI_23_DATA + DDRSS_PI_24_DATA + DDRSS_PI_25_DATA + DDRSS_PI_26_DATA + DDRSS_PI_27_DATA + DDRSS_PI_28_DATA + DDRSS_PI_29_DATA + DDRSS_PI_30_DATA + DDRSS_PI_31_DATA + DDRSS_PI_32_DATA + DDRSS_PI_33_DATA + DDRSS_PI_34_DATA + DDRSS_PI_35_DATA + DDRSS_PI_36_DATA + DDRSS_PI_37_DATA + DDRSS_PI_38_DATA + DDRSS_PI_39_DATA + DDRSS_PI_40_DATA + DDRSS_PI_41_DATA + DDRSS_PI_42_DATA + DDRSS_PI_43_DATA + DDRSS_PI_44_DATA + DDRSS_PI_45_DATA + DDRSS_PI_46_DATA + DDRSS_PI_47_DATA + DDRSS_PI_48_DATA + DDRSS_PI_49_DATA + DDRSS_PI_50_DATA + DDRSS_PI_51_DATA + DDRSS_PI_52_DATA + DDRSS_PI_53_DATA + DDRSS_PI_54_DATA + DDRSS_PI_55_DATA + DDRSS_PI_56_DATA + DDRSS_PI_57_DATA + DDRSS_PI_58_DATA + DDRSS_PI_59_DATA + DDRSS_PI_60_DATA + DDRSS_PI_61_DATA + DDRSS_PI_62_DATA + DDRSS_PI_63_DATA + DDRSS_PI_64_DATA + DDRSS_PI_65_DATA + DDRSS_PI_66_DATA + DDRSS_PI_67_DATA + DDRSS_PI_68_DATA + DDRSS_PI_69_DATA + DDRSS_PI_70_DATA + DDRSS_PI_71_DATA + DDRSS_PI_72_DATA + DDRSS_PI_73_DATA + DDRSS_PI_74_DATA + DDRSS_PI_75_DATA + DDRSS_PI_76_DATA + DDRSS_PI_77_DATA + DDRSS_PI_78_DATA + DDRSS_PI_79_DATA + DDRSS_PI_80_DATA + DDRSS_PI_81_DATA + DDRSS_PI_82_DATA + DDRSS_PI_83_DATA + DDRSS_PI_84_DATA + DDRSS_PI_85_DATA + DDRSS_PI_86_DATA + DDRSS_PI_87_DATA + DDRSS_PI_88_DATA + DDRSS_PI_89_DATA + DDRSS_PI_90_DATA + DDRSS_PI_91_DATA + DDRSS_PI_92_DATA + DDRSS_PI_93_DATA + DDRSS_PI_94_DATA + DDRSS_PI_95_DATA + DDRSS_PI_96_DATA + DDRSS_PI_97_DATA + DDRSS_PI_98_DATA + DDRSS_PI_99_DATA + DDRSS_PI_100_DATA + DDRSS_PI_101_DATA + DDRSS_PI_102_DATA + DDRSS_PI_103_DATA + DDRSS_PI_104_DATA + DDRSS_PI_105_DATA + DDRSS_PI_106_DATA + DDRSS_PI_107_DATA + DDRSS_PI_108_DATA + DDRSS_PI_109_DATA + DDRSS_PI_110_DATA + DDRSS_PI_111_DATA + DDRSS_PI_112_DATA + DDRSS_PI_113_DATA + DDRSS_PI_114_DATA + DDRSS_PI_115_DATA + DDRSS_PI_116_DATA + DDRSS_PI_117_DATA + DDRSS_PI_118_DATA + DDRSS_PI_119_DATA + DDRSS_PI_120_DATA + DDRSS_PI_121_DATA + DDRSS_PI_122_DATA + DDRSS_PI_123_DATA + DDRSS_PI_124_DATA + DDRSS_PI_125_DATA + DDRSS_PI_126_DATA + DDRSS_PI_127_DATA + DDRSS_PI_128_DATA + DDRSS_PI_129_DATA + DDRSS_PI_130_DATA + DDRSS_PI_131_DATA + DDRSS_PI_132_DATA + DDRSS_PI_133_DATA + DDRSS_PI_134_DATA + DDRSS_PI_135_DATA + DDRSS_PI_136_DATA + DDRSS_PI_137_DATA + DDRSS_PI_138_DATA + DDRSS_PI_139_DATA + DDRSS_PI_140_DATA + DDRSS_PI_141_DATA + DDRSS_PI_142_DATA + DDRSS_PI_143_DATA + DDRSS_PI_144_DATA + DDRSS_PI_145_DATA + DDRSS_PI_146_DATA + DDRSS_PI_147_DATA + DDRSS_PI_148_DATA + DDRSS_PI_149_DATA + DDRSS_PI_150_DATA + DDRSS_PI_151_DATA + DDRSS_PI_152_DATA + DDRSS_PI_153_DATA + DDRSS_PI_154_DATA + DDRSS_PI_155_DATA + DDRSS_PI_156_DATA + DDRSS_PI_157_DATA + DDRSS_PI_158_DATA + DDRSS_PI_159_DATA + DDRSS_PI_160_DATA + DDRSS_PI_161_DATA + DDRSS_PI_162_DATA + DDRSS_PI_163_DATA + DDRSS_PI_164_DATA + DDRSS_PI_165_DATA + DDRSS_PI_166_DATA + DDRSS_PI_167_DATA + DDRSS_PI_168_DATA + DDRSS_PI_169_DATA + DDRSS_PI_170_DATA + DDRSS_PI_171_DATA + DDRSS_PI_172_DATA + DDRSS_PI_173_DATA + DDRSS_PI_174_DATA + DDRSS_PI_175_DATA + DDRSS_PI_176_DATA + DDRSS_PI_177_DATA + DDRSS_PI_178_DATA + DDRSS_PI_179_DATA + DDRSS_PI_180_DATA + DDRSS_PI_181_DATA + DDRSS_PI_182_DATA + DDRSS_PI_183_DATA + DDRSS_PI_184_DATA + DDRSS_PI_185_DATA + DDRSS_PI_186_DATA + DDRSS_PI_187_DATA + DDRSS_PI_188_DATA + DDRSS_PI_189_DATA + DDRSS_PI_190_DATA + DDRSS_PI_191_DATA + DDRSS_PI_192_DATA + DDRSS_PI_193_DATA + DDRSS_PI_194_DATA + DDRSS_PI_195_DATA + DDRSS_PI_196_DATA + DDRSS_PI_197_DATA + DDRSS_PI_198_DATA + DDRSS_PI_199_DATA + DDRSS_PI_200_DATA + DDRSS_PI_201_DATA + DDRSS_PI_202_DATA + DDRSS_PI_203_DATA + DDRSS_PI_204_DATA + DDRSS_PI_205_DATA + DDRSS_PI_206_DATA + DDRSS_PI_207_DATA + DDRSS_PI_208_DATA + DDRSS_PI_209_DATA + DDRSS_PI_210_DATA + DDRSS_PI_211_DATA + DDRSS_PI_212_DATA + DDRSS_PI_213_DATA + DDRSS_PI_214_DATA + DDRSS_PI_215_DATA + DDRSS_PI_216_DATA + DDRSS_PI_217_DATA + DDRSS_PI_218_DATA + DDRSS_PI_219_DATA + DDRSS_PI_220_DATA + DDRSS_PI_221_DATA + DDRSS_PI_222_DATA + DDRSS_PI_223_DATA + DDRSS_PI_224_DATA + DDRSS_PI_225_DATA + DDRSS_PI_226_DATA + DDRSS_PI_227_DATA + DDRSS_PI_228_DATA + DDRSS_PI_229_DATA + DDRSS_PI_230_DATA + DDRSS_PI_231_DATA + DDRSS_PI_232_DATA + DDRSS_PI_233_DATA + DDRSS_PI_234_DATA + DDRSS_PI_235_DATA + DDRSS_PI_236_DATA + DDRSS_PI_237_DATA + DDRSS_PI_238_DATA + DDRSS_PI_239_DATA + DDRSS_PI_240_DATA + DDRSS_PI_241_DATA + DDRSS_PI_242_DATA + DDRSS_PI_243_DATA + DDRSS_PI_244_DATA + DDRSS_PI_245_DATA + DDRSS_PI_246_DATA + DDRSS_PI_247_DATA + DDRSS_PI_248_DATA + DDRSS_PI_249_DATA + DDRSS_PI_250_DATA + DDRSS_PI_251_DATA + DDRSS_PI_252_DATA + DDRSS_PI_253_DATA + DDRSS_PI_254_DATA + DDRSS_PI_255_DATA + DDRSS_PI_256_DATA + DDRSS_PI_257_DATA + DDRSS_PI_258_DATA + DDRSS_PI_259_DATA + DDRSS_PI_260_DATA + DDRSS_PI_261_DATA + DDRSS_PI_262_DATA + DDRSS_PI_263_DATA + DDRSS_PI_264_DATA + DDRSS_PI_265_DATA + DDRSS_PI_266_DATA + DDRSS_PI_267_DATA + DDRSS_PI_268_DATA + DDRSS_PI_269_DATA + DDRSS_PI_270_DATA + DDRSS_PI_271_DATA + DDRSS_PI_272_DATA + DDRSS_PI_273_DATA + DDRSS_PI_274_DATA + DDRSS_PI_275_DATA + DDRSS_PI_276_DATA + DDRSS_PI_277_DATA + DDRSS_PI_278_DATA + DDRSS_PI_279_DATA + DDRSS_PI_280_DATA + DDRSS_PI_281_DATA + DDRSS_PI_282_DATA + DDRSS_PI_283_DATA + DDRSS_PI_284_DATA + DDRSS_PI_285_DATA + DDRSS_PI_286_DATA + DDRSS_PI_287_DATA + DDRSS_PI_288_DATA + DDRSS_PI_289_DATA + DDRSS_PI_290_DATA + DDRSS_PI_291_DATA + DDRSS_PI_292_DATA + DDRSS_PI_293_DATA + DDRSS_PI_294_DATA + DDRSS_PI_295_DATA + DDRSS_PI_296_DATA + DDRSS_PI_297_DATA + DDRSS_PI_298_DATA + DDRSS_PI_299_DATA + >; + + ti,phy-data = < + DDRSS_PHY_00_DATA + DDRSS_PHY_01_DATA + DDRSS_PHY_02_DATA + DDRSS_PHY_03_DATA + DDRSS_PHY_04_DATA + DDRSS_PHY_05_DATA + DDRSS_PHY_06_DATA + DDRSS_PHY_07_DATA + DDRSS_PHY_08_DATA + DDRSS_PHY_09_DATA + DDRSS_PHY_10_DATA + DDRSS_PHY_11_DATA + DDRSS_PHY_12_DATA + DDRSS_PHY_13_DATA + DDRSS_PHY_14_DATA + DDRSS_PHY_15_DATA + DDRSS_PHY_16_DATA + DDRSS_PHY_17_DATA + DDRSS_PHY_18_DATA + DDRSS_PHY_19_DATA + DDRSS_PHY_20_DATA + DDRSS_PHY_21_DATA + DDRSS_PHY_22_DATA + DDRSS_PHY_23_DATA + DDRSS_PHY_24_DATA + DDRSS_PHY_25_DATA + DDRSS_PHY_26_DATA + DDRSS_PHY_27_DATA + DDRSS_PHY_28_DATA + DDRSS_PHY_29_DATA + DDRSS_PHY_30_DATA + DDRSS_PHY_31_DATA + DDRSS_PHY_32_DATA + DDRSS_PHY_33_DATA + DDRSS_PHY_34_DATA + DDRSS_PHY_35_DATA + DDRSS_PHY_36_DATA + DDRSS_PHY_37_DATA + DDRSS_PHY_38_DATA + DDRSS_PHY_39_DATA + DDRSS_PHY_40_DATA + DDRSS_PHY_41_DATA + DDRSS_PHY_42_DATA + DDRSS_PHY_43_DATA + DDRSS_PHY_44_DATA + DDRSS_PHY_45_DATA + DDRSS_PHY_46_DATA + DDRSS_PHY_47_DATA + DDRSS_PHY_48_DATA + DDRSS_PHY_49_DATA + DDRSS_PHY_50_DATA + DDRSS_PHY_51_DATA + DDRSS_PHY_52_DATA + DDRSS_PHY_53_DATA + DDRSS_PHY_54_DATA + DDRSS_PHY_55_DATA + DDRSS_PHY_56_DATA + DDRSS_PHY_57_DATA + DDRSS_PHY_58_DATA + DDRSS_PHY_59_DATA + DDRSS_PHY_60_DATA + DDRSS_PHY_61_DATA + DDRSS_PHY_62_DATA + DDRSS_PHY_63_DATA + DDRSS_PHY_64_DATA + DDRSS_PHY_65_DATA + DDRSS_PHY_66_DATA + DDRSS_PHY_67_DATA + DDRSS_PHY_68_DATA + DDRSS_PHY_69_DATA + DDRSS_PHY_70_DATA + DDRSS_PHY_71_DATA + DDRSS_PHY_72_DATA + DDRSS_PHY_73_DATA + DDRSS_PHY_74_DATA + DDRSS_PHY_75_DATA + DDRSS_PHY_76_DATA + DDRSS_PHY_77_DATA + DDRSS_PHY_78_DATA + DDRSS_PHY_79_DATA + DDRSS_PHY_80_DATA + DDRSS_PHY_81_DATA + DDRSS_PHY_82_DATA + DDRSS_PHY_83_DATA + DDRSS_PHY_84_DATA + DDRSS_PHY_85_DATA + DDRSS_PHY_86_DATA + DDRSS_PHY_87_DATA + DDRSS_PHY_88_DATA + DDRSS_PHY_89_DATA + DDRSS_PHY_90_DATA + DDRSS_PHY_91_DATA + DDRSS_PHY_92_DATA + DDRSS_PHY_93_DATA + DDRSS_PHY_94_DATA + DDRSS_PHY_95_DATA + DDRSS_PHY_96_DATA + DDRSS_PHY_97_DATA + DDRSS_PHY_98_DATA + DDRSS_PHY_99_DATA + DDRSS_PHY_100_DATA + DDRSS_PHY_101_DATA + DDRSS_PHY_102_DATA + DDRSS_PHY_103_DATA + DDRSS_PHY_104_DATA + DDRSS_PHY_105_DATA + DDRSS_PHY_106_DATA + DDRSS_PHY_107_DATA + DDRSS_PHY_108_DATA + DDRSS_PHY_109_DATA + DDRSS_PHY_110_DATA + DDRSS_PHY_111_DATA + DDRSS_PHY_112_DATA + DDRSS_PHY_113_DATA + DDRSS_PHY_114_DATA + DDRSS_PHY_115_DATA + DDRSS_PHY_116_DATA + DDRSS_PHY_117_DATA + DDRSS_PHY_118_DATA + DDRSS_PHY_119_DATA + DDRSS_PHY_120_DATA + DDRSS_PHY_121_DATA + DDRSS_PHY_122_DATA + DDRSS_PHY_123_DATA + DDRSS_PHY_124_DATA + DDRSS_PHY_125_DATA + DDRSS_PHY_126_DATA + DDRSS_PHY_127_DATA + DDRSS_PHY_128_DATA + DDRSS_PHY_129_DATA + DDRSS_PHY_130_DATA + DDRSS_PHY_131_DATA + DDRSS_PHY_132_DATA + DDRSS_PHY_133_DATA + DDRSS_PHY_134_DATA + DDRSS_PHY_135_DATA + DDRSS_PHY_136_DATA + DDRSS_PHY_137_DATA + DDRSS_PHY_138_DATA + DDRSS_PHY_139_DATA + DDRSS_PHY_140_DATA + DDRSS_PHY_141_DATA + DDRSS_PHY_142_DATA + DDRSS_PHY_143_DATA + DDRSS_PHY_144_DATA + DDRSS_PHY_145_DATA + DDRSS_PHY_146_DATA + DDRSS_PHY_147_DATA + DDRSS_PHY_148_DATA + DDRSS_PHY_149_DATA + DDRSS_PHY_150_DATA + DDRSS_PHY_151_DATA + DDRSS_PHY_152_DATA + DDRSS_PHY_153_DATA + DDRSS_PHY_154_DATA + DDRSS_PHY_155_DATA + DDRSS_PHY_156_DATA + DDRSS_PHY_157_DATA + DDRSS_PHY_158_DATA + DDRSS_PHY_159_DATA + DDRSS_PHY_160_DATA + DDRSS_PHY_161_DATA + DDRSS_PHY_162_DATA + DDRSS_PHY_163_DATA + DDRSS_PHY_164_DATA + DDRSS_PHY_165_DATA + DDRSS_PHY_166_DATA + DDRSS_PHY_167_DATA + DDRSS_PHY_168_DATA + DDRSS_PHY_169_DATA + DDRSS_PHY_170_DATA + DDRSS_PHY_171_DATA + DDRSS_PHY_172_DATA + DDRSS_PHY_173_DATA + DDRSS_PHY_174_DATA + DDRSS_PHY_175_DATA + DDRSS_PHY_176_DATA + DDRSS_PHY_177_DATA + DDRSS_PHY_178_DATA + DDRSS_PHY_179_DATA + DDRSS_PHY_180_DATA + DDRSS_PHY_181_DATA + DDRSS_PHY_182_DATA + DDRSS_PHY_183_DATA + DDRSS_PHY_184_DATA + DDRSS_PHY_185_DATA + DDRSS_PHY_186_DATA + DDRSS_PHY_187_DATA + DDRSS_PHY_188_DATA + DDRSS_PHY_189_DATA + DDRSS_PHY_190_DATA + DDRSS_PHY_191_DATA + DDRSS_PHY_192_DATA + DDRSS_PHY_193_DATA + DDRSS_PHY_194_DATA + DDRSS_PHY_195_DATA + DDRSS_PHY_196_DATA + DDRSS_PHY_197_DATA + DDRSS_PHY_198_DATA + DDRSS_PHY_199_DATA + DDRSS_PHY_200_DATA + DDRSS_PHY_201_DATA + DDRSS_PHY_202_DATA + DDRSS_PHY_203_DATA + DDRSS_PHY_204_DATA + DDRSS_PHY_205_DATA + DDRSS_PHY_206_DATA + DDRSS_PHY_207_DATA + DDRSS_PHY_208_DATA + DDRSS_PHY_209_DATA + DDRSS_PHY_210_DATA + DDRSS_PHY_211_DATA + DDRSS_PHY_212_DATA + DDRSS_PHY_213_DATA + DDRSS_PHY_214_DATA + DDRSS_PHY_215_DATA + DDRSS_PHY_216_DATA + DDRSS_PHY_217_DATA + DDRSS_PHY_218_DATA + DDRSS_PHY_219_DATA + DDRSS_PHY_220_DATA + DDRSS_PHY_221_DATA + DDRSS_PHY_222_DATA + DDRSS_PHY_223_DATA + DDRSS_PHY_224_DATA + DDRSS_PHY_225_DATA + DDRSS_PHY_226_DATA + DDRSS_PHY_227_DATA + DDRSS_PHY_228_DATA + DDRSS_PHY_229_DATA + DDRSS_PHY_230_DATA + DDRSS_PHY_231_DATA + DDRSS_PHY_232_DATA + DDRSS_PHY_233_DATA + DDRSS_PHY_234_DATA + DDRSS_PHY_235_DATA + DDRSS_PHY_236_DATA + DDRSS_PHY_237_DATA + DDRSS_PHY_238_DATA + DDRSS_PHY_239_DATA + DDRSS_PHY_240_DATA + DDRSS_PHY_241_DATA + DDRSS_PHY_242_DATA + DDRSS_PHY_243_DATA + DDRSS_PHY_244_DATA + DDRSS_PHY_245_DATA + DDRSS_PHY_246_DATA + DDRSS_PHY_247_DATA + DDRSS_PHY_248_DATA + DDRSS_PHY_249_DATA + DDRSS_PHY_250_DATA + DDRSS_PHY_251_DATA + DDRSS_PHY_252_DATA + DDRSS_PHY_253_DATA + DDRSS_PHY_254_DATA + DDRSS_PHY_255_DATA + DDRSS_PHY_256_DATA + DDRSS_PHY_257_DATA + DDRSS_PHY_258_DATA + DDRSS_PHY_259_DATA + DDRSS_PHY_260_DATA + DDRSS_PHY_261_DATA + DDRSS_PHY_262_DATA + DDRSS_PHY_263_DATA + DDRSS_PHY_264_DATA + DDRSS_PHY_265_DATA + DDRSS_PHY_266_DATA + DDRSS_PHY_267_DATA + DDRSS_PHY_268_DATA + DDRSS_PHY_269_DATA + DDRSS_PHY_270_DATA + DDRSS_PHY_271_DATA + DDRSS_PHY_272_DATA + DDRSS_PHY_273_DATA + DDRSS_PHY_274_DATA + DDRSS_PHY_275_DATA + DDRSS_PHY_276_DATA + DDRSS_PHY_277_DATA + DDRSS_PHY_278_DATA + DDRSS_PHY_279_DATA + DDRSS_PHY_280_DATA + DDRSS_PHY_281_DATA + DDRSS_PHY_282_DATA + DDRSS_PHY_283_DATA + DDRSS_PHY_284_DATA + DDRSS_PHY_285_DATA + DDRSS_PHY_286_DATA + DDRSS_PHY_287_DATA + DDRSS_PHY_288_DATA + DDRSS_PHY_289_DATA + DDRSS_PHY_290_DATA + DDRSS_PHY_291_DATA + DDRSS_PHY_292_DATA + DDRSS_PHY_293_DATA + DDRSS_PHY_294_DATA + DDRSS_PHY_295_DATA + DDRSS_PHY_296_DATA + DDRSS_PHY_297_DATA + DDRSS_PHY_298_DATA + DDRSS_PHY_299_DATA + DDRSS_PHY_300_DATA + DDRSS_PHY_301_DATA + DDRSS_PHY_302_DATA + DDRSS_PHY_303_DATA + DDRSS_PHY_304_DATA + DDRSS_PHY_305_DATA + DDRSS_PHY_306_DATA + DDRSS_PHY_307_DATA + DDRSS_PHY_308_DATA + DDRSS_PHY_309_DATA + DDRSS_PHY_310_DATA + DDRSS_PHY_311_DATA + DDRSS_PHY_312_DATA + DDRSS_PHY_313_DATA + DDRSS_PHY_314_DATA + DDRSS_PHY_315_DATA + DDRSS_PHY_316_DATA + DDRSS_PHY_317_DATA + DDRSS_PHY_318_DATA + DDRSS_PHY_319_DATA + DDRSS_PHY_320_DATA + DDRSS_PHY_321_DATA + DDRSS_PHY_322_DATA + DDRSS_PHY_323_DATA + DDRSS_PHY_324_DATA + DDRSS_PHY_325_DATA + DDRSS_PHY_326_DATA + DDRSS_PHY_327_DATA + DDRSS_PHY_328_DATA + DDRSS_PHY_329_DATA + DDRSS_PHY_330_DATA + DDRSS_PHY_331_DATA + DDRSS_PHY_332_DATA + DDRSS_PHY_333_DATA + DDRSS_PHY_334_DATA + DDRSS_PHY_335_DATA + DDRSS_PHY_336_DATA + DDRSS_PHY_337_DATA + DDRSS_PHY_338_DATA + DDRSS_PHY_339_DATA + DDRSS_PHY_340_DATA + DDRSS_PHY_341_DATA + DDRSS_PHY_342_DATA + DDRSS_PHY_343_DATA + DDRSS_PHY_344_DATA + DDRSS_PHY_345_DATA + DDRSS_PHY_346_DATA + DDRSS_PHY_347_DATA + DDRSS_PHY_348_DATA + DDRSS_PHY_349_DATA + DDRSS_PHY_350_DATA + DDRSS_PHY_351_DATA + DDRSS_PHY_352_DATA + DDRSS_PHY_353_DATA + DDRSS_PHY_354_DATA + DDRSS_PHY_355_DATA + DDRSS_PHY_356_DATA + DDRSS_PHY_357_DATA + DDRSS_PHY_358_DATA + DDRSS_PHY_359_DATA + DDRSS_PHY_360_DATA + DDRSS_PHY_361_DATA + DDRSS_PHY_362_DATA + DDRSS_PHY_363_DATA + DDRSS_PHY_364_DATA + DDRSS_PHY_365_DATA + DDRSS_PHY_366_DATA + DDRSS_PHY_367_DATA + DDRSS_PHY_368_DATA + DDRSS_PHY_369_DATA + DDRSS_PHY_370_DATA + DDRSS_PHY_371_DATA + DDRSS_PHY_372_DATA + DDRSS_PHY_373_DATA + DDRSS_PHY_374_DATA + DDRSS_PHY_375_DATA + DDRSS_PHY_376_DATA + DDRSS_PHY_377_DATA + DDRSS_PHY_378_DATA + DDRSS_PHY_379_DATA + DDRSS_PHY_380_DATA + DDRSS_PHY_381_DATA + DDRSS_PHY_382_DATA + DDRSS_PHY_383_DATA + DDRSS_PHY_384_DATA + DDRSS_PHY_385_DATA + DDRSS_PHY_386_DATA + DDRSS_PHY_387_DATA + DDRSS_PHY_388_DATA + DDRSS_PHY_389_DATA + DDRSS_PHY_390_DATA + DDRSS_PHY_391_DATA + DDRSS_PHY_392_DATA + DDRSS_PHY_393_DATA + DDRSS_PHY_394_DATA + DDRSS_PHY_395_DATA + DDRSS_PHY_396_DATA + DDRSS_PHY_397_DATA + DDRSS_PHY_398_DATA + DDRSS_PHY_399_DATA + DDRSS_PHY_400_DATA + DDRSS_PHY_401_DATA + DDRSS_PHY_402_DATA + DDRSS_PHY_403_DATA + DDRSS_PHY_404_DATA + DDRSS_PHY_405_DATA + DDRSS_PHY_406_DATA + DDRSS_PHY_407_DATA + DDRSS_PHY_408_DATA + DDRSS_PHY_409_DATA + DDRSS_PHY_410_DATA + DDRSS_PHY_411_DATA + DDRSS_PHY_412_DATA + DDRSS_PHY_413_DATA + DDRSS_PHY_414_DATA + DDRSS_PHY_415_DATA + DDRSS_PHY_416_DATA + DDRSS_PHY_417_DATA + DDRSS_PHY_418_DATA + DDRSS_PHY_419_DATA + DDRSS_PHY_420_DATA + DDRSS_PHY_421_DATA + DDRSS_PHY_422_DATA + DDRSS_PHY_423_DATA + DDRSS_PHY_424_DATA + DDRSS_PHY_425_DATA + DDRSS_PHY_426_DATA + DDRSS_PHY_427_DATA + DDRSS_PHY_428_DATA + DDRSS_PHY_429_DATA + DDRSS_PHY_430_DATA + DDRSS_PHY_431_DATA + DDRSS_PHY_432_DATA + DDRSS_PHY_433_DATA + DDRSS_PHY_434_DATA + DDRSS_PHY_435_DATA + DDRSS_PHY_436_DATA + DDRSS_PHY_437_DATA + DDRSS_PHY_438_DATA + DDRSS_PHY_439_DATA + DDRSS_PHY_440_DATA + DDRSS_PHY_441_DATA + DDRSS_PHY_442_DATA + DDRSS_PHY_443_DATA + DDRSS_PHY_444_DATA + DDRSS_PHY_445_DATA + DDRSS_PHY_446_DATA + DDRSS_PHY_447_DATA + DDRSS_PHY_448_DATA + DDRSS_PHY_449_DATA + DDRSS_PHY_450_DATA + DDRSS_PHY_451_DATA + DDRSS_PHY_452_DATA + DDRSS_PHY_453_DATA + DDRSS_PHY_454_DATA + DDRSS_PHY_455_DATA + DDRSS_PHY_456_DATA + DDRSS_PHY_457_DATA + DDRSS_PHY_458_DATA + DDRSS_PHY_459_DATA + DDRSS_PHY_460_DATA + DDRSS_PHY_461_DATA + DDRSS_PHY_462_DATA + DDRSS_PHY_463_DATA + DDRSS_PHY_464_DATA + DDRSS_PHY_465_DATA + DDRSS_PHY_466_DATA + DDRSS_PHY_467_DATA + DDRSS_PHY_468_DATA + DDRSS_PHY_469_DATA + DDRSS_PHY_470_DATA + DDRSS_PHY_471_DATA + DDRSS_PHY_472_DATA + DDRSS_PHY_473_DATA + DDRSS_PHY_474_DATA + DDRSS_PHY_475_DATA + DDRSS_PHY_476_DATA + DDRSS_PHY_477_DATA + DDRSS_PHY_478_DATA + DDRSS_PHY_479_DATA + DDRSS_PHY_480_DATA + DDRSS_PHY_481_DATA + DDRSS_PHY_482_DATA + DDRSS_PHY_483_DATA + DDRSS_PHY_484_DATA + DDRSS_PHY_485_DATA + DDRSS_PHY_486_DATA + DDRSS_PHY_487_DATA + DDRSS_PHY_488_DATA + DDRSS_PHY_489_DATA + DDRSS_PHY_490_DATA + DDRSS_PHY_491_DATA + DDRSS_PHY_492_DATA + DDRSS_PHY_493_DATA + DDRSS_PHY_494_DATA + DDRSS_PHY_495_DATA + DDRSS_PHY_496_DATA + DDRSS_PHY_497_DATA + DDRSS_PHY_498_DATA + DDRSS_PHY_499_DATA + DDRSS_PHY_500_DATA + DDRSS_PHY_501_DATA + DDRSS_PHY_502_DATA + DDRSS_PHY_503_DATA + DDRSS_PHY_504_DATA + DDRSS_PHY_505_DATA + DDRSS_PHY_506_DATA + DDRSS_PHY_507_DATA + DDRSS_PHY_508_DATA + DDRSS_PHY_509_DATA + DDRSS_PHY_510_DATA + DDRSS_PHY_511_DATA + DDRSS_PHY_512_DATA + DDRSS_PHY_513_DATA + DDRSS_PHY_514_DATA + DDRSS_PHY_515_DATA + DDRSS_PHY_516_DATA + DDRSS_PHY_517_DATA + DDRSS_PHY_518_DATA + DDRSS_PHY_519_DATA + DDRSS_PHY_520_DATA + DDRSS_PHY_521_DATA + DDRSS_PHY_522_DATA + DDRSS_PHY_523_DATA + DDRSS_PHY_524_DATA + DDRSS_PHY_525_DATA + DDRSS_PHY_526_DATA + DDRSS_PHY_527_DATA + DDRSS_PHY_528_DATA + DDRSS_PHY_529_DATA + DDRSS_PHY_530_DATA + DDRSS_PHY_531_DATA + DDRSS_PHY_532_DATA + DDRSS_PHY_533_DATA + DDRSS_PHY_534_DATA + DDRSS_PHY_535_DATA + DDRSS_PHY_536_DATA + DDRSS_PHY_537_DATA + DDRSS_PHY_538_DATA + DDRSS_PHY_539_DATA + DDRSS_PHY_540_DATA + DDRSS_PHY_541_DATA + DDRSS_PHY_542_DATA + DDRSS_PHY_543_DATA + DDRSS_PHY_544_DATA + DDRSS_PHY_545_DATA + DDRSS_PHY_546_DATA + DDRSS_PHY_547_DATA + DDRSS_PHY_548_DATA + DDRSS_PHY_549_DATA + DDRSS_PHY_550_DATA + DDRSS_PHY_551_DATA + DDRSS_PHY_552_DATA + DDRSS_PHY_553_DATA + DDRSS_PHY_554_DATA + DDRSS_PHY_555_DATA + DDRSS_PHY_556_DATA + DDRSS_PHY_557_DATA + DDRSS_PHY_558_DATA + DDRSS_PHY_559_DATA + DDRSS_PHY_560_DATA + DDRSS_PHY_561_DATA + DDRSS_PHY_562_DATA + DDRSS_PHY_563_DATA + DDRSS_PHY_564_DATA + DDRSS_PHY_565_DATA + DDRSS_PHY_566_DATA + DDRSS_PHY_567_DATA + DDRSS_PHY_568_DATA + DDRSS_PHY_569_DATA + DDRSS_PHY_570_DATA + DDRSS_PHY_571_DATA + DDRSS_PHY_572_DATA + DDRSS_PHY_573_DATA + DDRSS_PHY_574_DATA + DDRSS_PHY_575_DATA + DDRSS_PHY_576_DATA + DDRSS_PHY_577_DATA + DDRSS_PHY_578_DATA + DDRSS_PHY_579_DATA + DDRSS_PHY_580_DATA + DDRSS_PHY_581_DATA + DDRSS_PHY_582_DATA + DDRSS_PHY_583_DATA + DDRSS_PHY_584_DATA + DDRSS_PHY_585_DATA + DDRSS_PHY_586_DATA + DDRSS_PHY_587_DATA + DDRSS_PHY_588_DATA + DDRSS_PHY_589_DATA + DDRSS_PHY_590_DATA + DDRSS_PHY_591_DATA + DDRSS_PHY_592_DATA + DDRSS_PHY_593_DATA + DDRSS_PHY_594_DATA + DDRSS_PHY_595_DATA + DDRSS_PHY_596_DATA + DDRSS_PHY_597_DATA + DDRSS_PHY_598_DATA + DDRSS_PHY_599_DATA + DDRSS_PHY_600_DATA + DDRSS_PHY_601_DATA + DDRSS_PHY_602_DATA + DDRSS_PHY_603_DATA + DDRSS_PHY_604_DATA + DDRSS_PHY_605_DATA + DDRSS_PHY_606_DATA + DDRSS_PHY_607_DATA + DDRSS_PHY_608_DATA + DDRSS_PHY_609_DATA + DDRSS_PHY_610_DATA + DDRSS_PHY_611_DATA + DDRSS_PHY_612_DATA + DDRSS_PHY_613_DATA + DDRSS_PHY_614_DATA + DDRSS_PHY_615_DATA + DDRSS_PHY_616_DATA + DDRSS_PHY_617_DATA + DDRSS_PHY_618_DATA + DDRSS_PHY_619_DATA + DDRSS_PHY_620_DATA + DDRSS_PHY_621_DATA + DDRSS_PHY_622_DATA + DDRSS_PHY_623_DATA + DDRSS_PHY_624_DATA + DDRSS_PHY_625_DATA + DDRSS_PHY_626_DATA + DDRSS_PHY_627_DATA + DDRSS_PHY_628_DATA + DDRSS_PHY_629_DATA + DDRSS_PHY_630_DATA + DDRSS_PHY_631_DATA + DDRSS_PHY_632_DATA + DDRSS_PHY_633_DATA + DDRSS_PHY_634_DATA + DDRSS_PHY_635_DATA + DDRSS_PHY_636_DATA + DDRSS_PHY_637_DATA + DDRSS_PHY_638_DATA + DDRSS_PHY_639_DATA + DDRSS_PHY_640_DATA + DDRSS_PHY_641_DATA + DDRSS_PHY_642_DATA + DDRSS_PHY_643_DATA + DDRSS_PHY_644_DATA + DDRSS_PHY_645_DATA + DDRSS_PHY_646_DATA + DDRSS_PHY_647_DATA + DDRSS_PHY_648_DATA + DDRSS_PHY_649_DATA + DDRSS_PHY_650_DATA + DDRSS_PHY_651_DATA + DDRSS_PHY_652_DATA + DDRSS_PHY_653_DATA + DDRSS_PHY_654_DATA + DDRSS_PHY_655_DATA + DDRSS_PHY_656_DATA + DDRSS_PHY_657_DATA + DDRSS_PHY_658_DATA + DDRSS_PHY_659_DATA + DDRSS_PHY_660_DATA + DDRSS_PHY_661_DATA + DDRSS_PHY_662_DATA + DDRSS_PHY_663_DATA + DDRSS_PHY_664_DATA + DDRSS_PHY_665_DATA + DDRSS_PHY_666_DATA + DDRSS_PHY_667_DATA + DDRSS_PHY_668_DATA + DDRSS_PHY_669_DATA + DDRSS_PHY_670_DATA + DDRSS_PHY_671_DATA + DDRSS_PHY_672_DATA + DDRSS_PHY_673_DATA + DDRSS_PHY_674_DATA + DDRSS_PHY_675_DATA + DDRSS_PHY_676_DATA + DDRSS_PHY_677_DATA + DDRSS_PHY_678_DATA + DDRSS_PHY_679_DATA + DDRSS_PHY_680_DATA + DDRSS_PHY_681_DATA + DDRSS_PHY_682_DATA + DDRSS_PHY_683_DATA + DDRSS_PHY_684_DATA + DDRSS_PHY_685_DATA + DDRSS_PHY_686_DATA + DDRSS_PHY_687_DATA + DDRSS_PHY_688_DATA + DDRSS_PHY_689_DATA + DDRSS_PHY_690_DATA + DDRSS_PHY_691_DATA + DDRSS_PHY_692_DATA + DDRSS_PHY_693_DATA + DDRSS_PHY_694_DATA + DDRSS_PHY_695_DATA + DDRSS_PHY_696_DATA + DDRSS_PHY_697_DATA + DDRSS_PHY_698_DATA + DDRSS_PHY_699_DATA + DDRSS_PHY_700_DATA + DDRSS_PHY_701_DATA + DDRSS_PHY_702_DATA + DDRSS_PHY_703_DATA + DDRSS_PHY_704_DATA + DDRSS_PHY_705_DATA + DDRSS_PHY_706_DATA + DDRSS_PHY_707_DATA + DDRSS_PHY_708_DATA + DDRSS_PHY_709_DATA + DDRSS_PHY_710_DATA + DDRSS_PHY_711_DATA + DDRSS_PHY_712_DATA + DDRSS_PHY_713_DATA + DDRSS_PHY_714_DATA + DDRSS_PHY_715_DATA + DDRSS_PHY_716_DATA + DDRSS_PHY_717_DATA + DDRSS_PHY_718_DATA + DDRSS_PHY_719_DATA + DDRSS_PHY_720_DATA + DDRSS_PHY_721_DATA + DDRSS_PHY_722_DATA + DDRSS_PHY_723_DATA + DDRSS_PHY_724_DATA + DDRSS_PHY_725_DATA + DDRSS_PHY_726_DATA + DDRSS_PHY_727_DATA + DDRSS_PHY_728_DATA + DDRSS_PHY_729_DATA + DDRSS_PHY_730_DATA + DDRSS_PHY_731_DATA + DDRSS_PHY_732_DATA + DDRSS_PHY_733_DATA + DDRSS_PHY_734_DATA + DDRSS_PHY_735_DATA + DDRSS_PHY_736_DATA + DDRSS_PHY_737_DATA + DDRSS_PHY_738_DATA + DDRSS_PHY_739_DATA + DDRSS_PHY_740_DATA + DDRSS_PHY_741_DATA + DDRSS_PHY_742_DATA + DDRSS_PHY_743_DATA + DDRSS_PHY_744_DATA + DDRSS_PHY_745_DATA + DDRSS_PHY_746_DATA + DDRSS_PHY_747_DATA + DDRSS_PHY_748_DATA + DDRSS_PHY_749_DATA + DDRSS_PHY_750_DATA + DDRSS_PHY_751_DATA + DDRSS_PHY_752_DATA + DDRSS_PHY_753_DATA + DDRSS_PHY_754_DATA + DDRSS_PHY_755_DATA + DDRSS_PHY_756_DATA + DDRSS_PHY_757_DATA + DDRSS_PHY_758_DATA + DDRSS_PHY_759_DATA + DDRSS_PHY_760_DATA + DDRSS_PHY_761_DATA + DDRSS_PHY_762_DATA + DDRSS_PHY_763_DATA + DDRSS_PHY_764_DATA + DDRSS_PHY_765_DATA + DDRSS_PHY_766_DATA + DDRSS_PHY_767_DATA + DDRSS_PHY_768_DATA + DDRSS_PHY_769_DATA + DDRSS_PHY_770_DATA + DDRSS_PHY_771_DATA + DDRSS_PHY_772_DATA + DDRSS_PHY_773_DATA + DDRSS_PHY_774_DATA + DDRSS_PHY_775_DATA + DDRSS_PHY_776_DATA + DDRSS_PHY_777_DATA + DDRSS_PHY_778_DATA + DDRSS_PHY_779_DATA + DDRSS_PHY_780_DATA + DDRSS_PHY_781_DATA + DDRSS_PHY_782_DATA + DDRSS_PHY_783_DATA + DDRSS_PHY_784_DATA + DDRSS_PHY_785_DATA + DDRSS_PHY_786_DATA + DDRSS_PHY_787_DATA + DDRSS_PHY_788_DATA + DDRSS_PHY_789_DATA + DDRSS_PHY_790_DATA + DDRSS_PHY_791_DATA + DDRSS_PHY_792_DATA + DDRSS_PHY_793_DATA + DDRSS_PHY_794_DATA + DDRSS_PHY_795_DATA + DDRSS_PHY_796_DATA + DDRSS_PHY_797_DATA + DDRSS_PHY_798_DATA + DDRSS_PHY_799_DATA + DDRSS_PHY_800_DATA + DDRSS_PHY_801_DATA + DDRSS_PHY_802_DATA + DDRSS_PHY_803_DATA + DDRSS_PHY_804_DATA + DDRSS_PHY_805_DATA + DDRSS_PHY_806_DATA + DDRSS_PHY_807_DATA + DDRSS_PHY_808_DATA + DDRSS_PHY_809_DATA + DDRSS_PHY_810_DATA + DDRSS_PHY_811_DATA + DDRSS_PHY_812_DATA + DDRSS_PHY_813_DATA + DDRSS_PHY_814_DATA + DDRSS_PHY_815_DATA + DDRSS_PHY_816_DATA + DDRSS_PHY_817_DATA + DDRSS_PHY_818_DATA + DDRSS_PHY_819_DATA + DDRSS_PHY_820_DATA + DDRSS_PHY_821_DATA + DDRSS_PHY_822_DATA + DDRSS_PHY_823_DATA + DDRSS_PHY_824_DATA + DDRSS_PHY_825_DATA + DDRSS_PHY_826_DATA + DDRSS_PHY_827_DATA + DDRSS_PHY_828_DATA + DDRSS_PHY_829_DATA + DDRSS_PHY_830_DATA + DDRSS_PHY_831_DATA + DDRSS_PHY_832_DATA + DDRSS_PHY_833_DATA + DDRSS_PHY_834_DATA + DDRSS_PHY_835_DATA + DDRSS_PHY_836_DATA + DDRSS_PHY_837_DATA + DDRSS_PHY_838_DATA + DDRSS_PHY_839_DATA + DDRSS_PHY_840_DATA + DDRSS_PHY_841_DATA + DDRSS_PHY_842_DATA + DDRSS_PHY_843_DATA + DDRSS_PHY_844_DATA + DDRSS_PHY_845_DATA + DDRSS_PHY_846_DATA + DDRSS_PHY_847_DATA + DDRSS_PHY_848_DATA + DDRSS_PHY_849_DATA + DDRSS_PHY_850_DATA + DDRSS_PHY_851_DATA + DDRSS_PHY_852_DATA + DDRSS_PHY_853_DATA + DDRSS_PHY_854_DATA + DDRSS_PHY_855_DATA + DDRSS_PHY_856_DATA + DDRSS_PHY_857_DATA + DDRSS_PHY_858_DATA + DDRSS_PHY_859_DATA + DDRSS_PHY_860_DATA + DDRSS_PHY_861_DATA + DDRSS_PHY_862_DATA + DDRSS_PHY_863_DATA + DDRSS_PHY_864_DATA + DDRSS_PHY_865_DATA + DDRSS_PHY_866_DATA + DDRSS_PHY_867_DATA + DDRSS_PHY_868_DATA + DDRSS_PHY_869_DATA + DDRSS_PHY_870_DATA + DDRSS_PHY_871_DATA + DDRSS_PHY_872_DATA + DDRSS_PHY_873_DATA + DDRSS_PHY_874_DATA + DDRSS_PHY_875_DATA + DDRSS_PHY_876_DATA + DDRSS_PHY_877_DATA + DDRSS_PHY_878_DATA + DDRSS_PHY_879_DATA + DDRSS_PHY_880_DATA + DDRSS_PHY_881_DATA + DDRSS_PHY_882_DATA + DDRSS_PHY_883_DATA + DDRSS_PHY_884_DATA + DDRSS_PHY_885_DATA + DDRSS_PHY_886_DATA + DDRSS_PHY_887_DATA + DDRSS_PHY_888_DATA + DDRSS_PHY_889_DATA + DDRSS_PHY_890_DATA + DDRSS_PHY_891_DATA + DDRSS_PHY_892_DATA + DDRSS_PHY_893_DATA + DDRSS_PHY_894_DATA + DDRSS_PHY_895_DATA + DDRSS_PHY_896_DATA + DDRSS_PHY_897_DATA + DDRSS_PHY_898_DATA + DDRSS_PHY_899_DATA + DDRSS_PHY_900_DATA + DDRSS_PHY_901_DATA + DDRSS_PHY_902_DATA + DDRSS_PHY_903_DATA + DDRSS_PHY_904_DATA + DDRSS_PHY_905_DATA + DDRSS_PHY_906_DATA + DDRSS_PHY_907_DATA + DDRSS_PHY_908_DATA + DDRSS_PHY_909_DATA + DDRSS_PHY_910_DATA + DDRSS_PHY_911_DATA + DDRSS_PHY_912_DATA + DDRSS_PHY_913_DATA + DDRSS_PHY_914_DATA + DDRSS_PHY_915_DATA + DDRSS_PHY_916_DATA + DDRSS_PHY_917_DATA + DDRSS_PHY_918_DATA + DDRSS_PHY_919_DATA + DDRSS_PHY_920_DATA + DDRSS_PHY_921_DATA + DDRSS_PHY_922_DATA + DDRSS_PHY_923_DATA + DDRSS_PHY_924_DATA + DDRSS_PHY_925_DATA + DDRSS_PHY_926_DATA + DDRSS_PHY_927_DATA + DDRSS_PHY_928_DATA + DDRSS_PHY_929_DATA + DDRSS_PHY_930_DATA + DDRSS_PHY_931_DATA + DDRSS_PHY_932_DATA + DDRSS_PHY_933_DATA + DDRSS_PHY_934_DATA + DDRSS_PHY_935_DATA + DDRSS_PHY_936_DATA + DDRSS_PHY_937_DATA + DDRSS_PHY_938_DATA + DDRSS_PHY_939_DATA + DDRSS_PHY_940_DATA + DDRSS_PHY_941_DATA + DDRSS_PHY_942_DATA + DDRSS_PHY_943_DATA + DDRSS_PHY_944_DATA + DDRSS_PHY_945_DATA + DDRSS_PHY_946_DATA + DDRSS_PHY_947_DATA + DDRSS_PHY_948_DATA + DDRSS_PHY_949_DATA + DDRSS_PHY_950_DATA + DDRSS_PHY_951_DATA + DDRSS_PHY_952_DATA + DDRSS_PHY_953_DATA + DDRSS_PHY_954_DATA + DDRSS_PHY_955_DATA + DDRSS_PHY_956_DATA + DDRSS_PHY_957_DATA + DDRSS_PHY_958_DATA + DDRSS_PHY_959_DATA + DDRSS_PHY_960_DATA + DDRSS_PHY_961_DATA + DDRSS_PHY_962_DATA + DDRSS_PHY_963_DATA + DDRSS_PHY_964_DATA + DDRSS_PHY_965_DATA + DDRSS_PHY_966_DATA + DDRSS_PHY_967_DATA + DDRSS_PHY_968_DATA + DDRSS_PHY_969_DATA + DDRSS_PHY_970_DATA + DDRSS_PHY_971_DATA + DDRSS_PHY_972_DATA + DDRSS_PHY_973_DATA + DDRSS_PHY_974_DATA + DDRSS_PHY_975_DATA + DDRSS_PHY_976_DATA + DDRSS_PHY_977_DATA + DDRSS_PHY_978_DATA + DDRSS_PHY_979_DATA + DDRSS_PHY_980_DATA + DDRSS_PHY_981_DATA + DDRSS_PHY_982_DATA + DDRSS_PHY_983_DATA + DDRSS_PHY_984_DATA + DDRSS_PHY_985_DATA + DDRSS_PHY_986_DATA + DDRSS_PHY_987_DATA + DDRSS_PHY_988_DATA + DDRSS_PHY_989_DATA + DDRSS_PHY_990_DATA + DDRSS_PHY_991_DATA + DDRSS_PHY_992_DATA + DDRSS_PHY_993_DATA + DDRSS_PHY_994_DATA + DDRSS_PHY_995_DATA + DDRSS_PHY_996_DATA + DDRSS_PHY_997_DATA + DDRSS_PHY_998_DATA + DDRSS_PHY_999_DATA + DDRSS_PHY_1000_DATA + DDRSS_PHY_1001_DATA + DDRSS_PHY_1002_DATA + DDRSS_PHY_1003_DATA + DDRSS_PHY_1004_DATA + DDRSS_PHY_1005_DATA + DDRSS_PHY_1006_DATA + DDRSS_PHY_1007_DATA + DDRSS_PHY_1008_DATA + DDRSS_PHY_1009_DATA + DDRSS_PHY_1010_DATA + DDRSS_PHY_1011_DATA + DDRSS_PHY_1012_DATA + DDRSS_PHY_1013_DATA + DDRSS_PHY_1014_DATA + DDRSS_PHY_1015_DATA + DDRSS_PHY_1016_DATA + DDRSS_PHY_1017_DATA + DDRSS_PHY_1018_DATA + DDRSS_PHY_1019_DATA + DDRSS_PHY_1020_DATA + DDRSS_PHY_1021_DATA + DDRSS_PHY_1022_DATA + DDRSS_PHY_1023_DATA + DDRSS_PHY_1024_DATA + DDRSS_PHY_1025_DATA + DDRSS_PHY_1026_DATA + DDRSS_PHY_1027_DATA + DDRSS_PHY_1028_DATA + DDRSS_PHY_1029_DATA + DDRSS_PHY_1030_DATA + DDRSS_PHY_1031_DATA + DDRSS_PHY_1032_DATA + DDRSS_PHY_1033_DATA + DDRSS_PHY_1034_DATA + DDRSS_PHY_1035_DATA + DDRSS_PHY_1036_DATA + DDRSS_PHY_1037_DATA + DDRSS_PHY_1038_DATA + DDRSS_PHY_1039_DATA + DDRSS_PHY_1040_DATA + DDRSS_PHY_1041_DATA + DDRSS_PHY_1042_DATA + DDRSS_PHY_1043_DATA + DDRSS_PHY_1044_DATA + DDRSS_PHY_1045_DATA + DDRSS_PHY_1046_DATA + DDRSS_PHY_1047_DATA + DDRSS_PHY_1048_DATA + DDRSS_PHY_1049_DATA + DDRSS_PHY_1050_DATA + DDRSS_PHY_1051_DATA + DDRSS_PHY_1052_DATA + DDRSS_PHY_1053_DATA + DDRSS_PHY_1054_DATA + DDRSS_PHY_1055_DATA + DDRSS_PHY_1056_DATA + DDRSS_PHY_1057_DATA + DDRSS_PHY_1058_DATA + DDRSS_PHY_1059_DATA + DDRSS_PHY_1060_DATA + DDRSS_PHY_1061_DATA + DDRSS_PHY_1062_DATA + DDRSS_PHY_1063_DATA + DDRSS_PHY_1064_DATA + DDRSS_PHY_1065_DATA + DDRSS_PHY_1066_DATA + DDRSS_PHY_1067_DATA + DDRSS_PHY_1068_DATA + DDRSS_PHY_1069_DATA + DDRSS_PHY_1070_DATA + DDRSS_PHY_1071_DATA + DDRSS_PHY_1072_DATA + DDRSS_PHY_1073_DATA + DDRSS_PHY_1074_DATA + DDRSS_PHY_1075_DATA + DDRSS_PHY_1076_DATA + DDRSS_PHY_1077_DATA + DDRSS_PHY_1078_DATA + DDRSS_PHY_1079_DATA + DDRSS_PHY_1080_DATA + DDRSS_PHY_1081_DATA + DDRSS_PHY_1082_DATA + DDRSS_PHY_1083_DATA + DDRSS_PHY_1084_DATA + DDRSS_PHY_1085_DATA + DDRSS_PHY_1086_DATA + DDRSS_PHY_1087_DATA + DDRSS_PHY_1088_DATA + DDRSS_PHY_1089_DATA + DDRSS_PHY_1090_DATA + DDRSS_PHY_1091_DATA + DDRSS_PHY_1092_DATA + DDRSS_PHY_1093_DATA + DDRSS_PHY_1094_DATA + DDRSS_PHY_1095_DATA + DDRSS_PHY_1096_DATA + DDRSS_PHY_1097_DATA + DDRSS_PHY_1098_DATA + DDRSS_PHY_1099_DATA + DDRSS_PHY_1100_DATA + DDRSS_PHY_1101_DATA + DDRSS_PHY_1102_DATA + DDRSS_PHY_1103_DATA + DDRSS_PHY_1104_DATA + DDRSS_PHY_1105_DATA + DDRSS_PHY_1106_DATA + DDRSS_PHY_1107_DATA + DDRSS_PHY_1108_DATA + DDRSS_PHY_1109_DATA + DDRSS_PHY_1110_DATA + DDRSS_PHY_1111_DATA + DDRSS_PHY_1112_DATA + DDRSS_PHY_1113_DATA + DDRSS_PHY_1114_DATA + DDRSS_PHY_1115_DATA + DDRSS_PHY_1116_DATA + DDRSS_PHY_1117_DATA + DDRSS_PHY_1118_DATA + DDRSS_PHY_1119_DATA + DDRSS_PHY_1120_DATA + DDRSS_PHY_1121_DATA + DDRSS_PHY_1122_DATA + DDRSS_PHY_1123_DATA + DDRSS_PHY_1124_DATA + DDRSS_PHY_1125_DATA + DDRSS_PHY_1126_DATA + DDRSS_PHY_1127_DATA + DDRSS_PHY_1128_DATA + DDRSS_PHY_1129_DATA + DDRSS_PHY_1130_DATA + DDRSS_PHY_1131_DATA + DDRSS_PHY_1132_DATA + DDRSS_PHY_1133_DATA + DDRSS_PHY_1134_DATA + DDRSS_PHY_1135_DATA + DDRSS_PHY_1136_DATA + DDRSS_PHY_1137_DATA + DDRSS_PHY_1138_DATA + DDRSS_PHY_1139_DATA + DDRSS_PHY_1140_DATA + DDRSS_PHY_1141_DATA + DDRSS_PHY_1142_DATA + DDRSS_PHY_1143_DATA + DDRSS_PHY_1144_DATA + DDRSS_PHY_1145_DATA + DDRSS_PHY_1146_DATA + DDRSS_PHY_1147_DATA + DDRSS_PHY_1148_DATA + DDRSS_PHY_1149_DATA + DDRSS_PHY_1150_DATA + DDRSS_PHY_1151_DATA + DDRSS_PHY_1152_DATA + DDRSS_PHY_1153_DATA + DDRSS_PHY_1154_DATA + DDRSS_PHY_1155_DATA + DDRSS_PHY_1156_DATA + DDRSS_PHY_1157_DATA + DDRSS_PHY_1158_DATA + DDRSS_PHY_1159_DATA + DDRSS_PHY_1160_DATA + DDRSS_PHY_1161_DATA + DDRSS_PHY_1162_DATA + DDRSS_PHY_1163_DATA + DDRSS_PHY_1164_DATA + DDRSS_PHY_1165_DATA + DDRSS_PHY_1166_DATA + DDRSS_PHY_1167_DATA + DDRSS_PHY_1168_DATA + DDRSS_PHY_1169_DATA + DDRSS_PHY_1170_DATA + DDRSS_PHY_1171_DATA + DDRSS_PHY_1172_DATA + DDRSS_PHY_1173_DATA + DDRSS_PHY_1174_DATA + DDRSS_PHY_1175_DATA + DDRSS_PHY_1176_DATA + DDRSS_PHY_1177_DATA + DDRSS_PHY_1178_DATA + DDRSS_PHY_1179_DATA + DDRSS_PHY_1180_DATA + DDRSS_PHY_1181_DATA + DDRSS_PHY_1182_DATA + DDRSS_PHY_1183_DATA + DDRSS_PHY_1184_DATA + DDRSS_PHY_1185_DATA + DDRSS_PHY_1186_DATA + DDRSS_PHY_1187_DATA + DDRSS_PHY_1188_DATA + DDRSS_PHY_1189_DATA + DDRSS_PHY_1190_DATA + DDRSS_PHY_1191_DATA + DDRSS_PHY_1192_DATA + DDRSS_PHY_1193_DATA + DDRSS_PHY_1194_DATA + DDRSS_PHY_1195_DATA + DDRSS_PHY_1196_DATA + DDRSS_PHY_1197_DATA + DDRSS_PHY_1198_DATA + DDRSS_PHY_1199_DATA + DDRSS_PHY_1200_DATA + DDRSS_PHY_1201_DATA + DDRSS_PHY_1202_DATA + DDRSS_PHY_1203_DATA + DDRSS_PHY_1204_DATA + DDRSS_PHY_1205_DATA + DDRSS_PHY_1206_DATA + DDRSS_PHY_1207_DATA + DDRSS_PHY_1208_DATA + DDRSS_PHY_1209_DATA + DDRSS_PHY_1210_DATA + DDRSS_PHY_1211_DATA + DDRSS_PHY_1212_DATA + DDRSS_PHY_1213_DATA + DDRSS_PHY_1214_DATA + DDRSS_PHY_1215_DATA + DDRSS_PHY_1216_DATA + DDRSS_PHY_1217_DATA + DDRSS_PHY_1218_DATA + DDRSS_PHY_1219_DATA + DDRSS_PHY_1220_DATA + DDRSS_PHY_1221_DATA + DDRSS_PHY_1222_DATA + DDRSS_PHY_1223_DATA + DDRSS_PHY_1224_DATA + DDRSS_PHY_1225_DATA + DDRSS_PHY_1226_DATA + DDRSS_PHY_1227_DATA + DDRSS_PHY_1228_DATA + DDRSS_PHY_1229_DATA + DDRSS_PHY_1230_DATA + DDRSS_PHY_1231_DATA + DDRSS_PHY_1232_DATA + DDRSS_PHY_1233_DATA + DDRSS_PHY_1234_DATA + DDRSS_PHY_1235_DATA + DDRSS_PHY_1236_DATA + DDRSS_PHY_1237_DATA + DDRSS_PHY_1238_DATA + DDRSS_PHY_1239_DATA + DDRSS_PHY_1240_DATA + DDRSS_PHY_1241_DATA + DDRSS_PHY_1242_DATA + DDRSS_PHY_1243_DATA + DDRSS_PHY_1244_DATA + DDRSS_PHY_1245_DATA + DDRSS_PHY_1246_DATA + DDRSS_PHY_1247_DATA + DDRSS_PHY_1248_DATA + DDRSS_PHY_1249_DATA + DDRSS_PHY_1250_DATA + DDRSS_PHY_1251_DATA + DDRSS_PHY_1252_DATA + DDRSS_PHY_1253_DATA + DDRSS_PHY_1254_DATA + DDRSS_PHY_1255_DATA + DDRSS_PHY_1256_DATA + DDRSS_PHY_1257_DATA + DDRSS_PHY_1258_DATA + DDRSS_PHY_1259_DATA + DDRSS_PHY_1260_DATA + DDRSS_PHY_1261_DATA + DDRSS_PHY_1262_DATA + DDRSS_PHY_1263_DATA + DDRSS_PHY_1264_DATA + DDRSS_PHY_1265_DATA + DDRSS_PHY_1266_DATA + DDRSS_PHY_1267_DATA + DDRSS_PHY_1268_DATA + DDRSS_PHY_1269_DATA + DDRSS_PHY_1270_DATA + DDRSS_PHY_1271_DATA + DDRSS_PHY_1272_DATA + DDRSS_PHY_1273_DATA + DDRSS_PHY_1274_DATA + DDRSS_PHY_1275_DATA + DDRSS_PHY_1276_DATA + DDRSS_PHY_1277_DATA + DDRSS_PHY_1278_DATA + DDRSS_PHY_1279_DATA + DDRSS_PHY_1280_DATA + DDRSS_PHY_1281_DATA + DDRSS_PHY_1282_DATA + DDRSS_PHY_1283_DATA + DDRSS_PHY_1284_DATA + DDRSS_PHY_1285_DATA + DDRSS_PHY_1286_DATA + DDRSS_PHY_1287_DATA + DDRSS_PHY_1288_DATA + DDRSS_PHY_1289_DATA + DDRSS_PHY_1290_DATA + DDRSS_PHY_1291_DATA + DDRSS_PHY_1292_DATA + DDRSS_PHY_1293_DATA + DDRSS_PHY_1294_DATA + DDRSS_PHY_1295_DATA + DDRSS_PHY_1296_DATA + DDRSS_PHY_1297_DATA + DDRSS_PHY_1298_DATA + DDRSS_PHY_1299_DATA + DDRSS_PHY_1300_DATA + DDRSS_PHY_1301_DATA + DDRSS_PHY_1302_DATA + DDRSS_PHY_1303_DATA + DDRSS_PHY_1304_DATA + DDRSS_PHY_1305_DATA + DDRSS_PHY_1306_DATA + DDRSS_PHY_1307_DATA + DDRSS_PHY_1308_DATA + DDRSS_PHY_1309_DATA + DDRSS_PHY_1310_DATA + DDRSS_PHY_1311_DATA + DDRSS_PHY_1312_DATA + DDRSS_PHY_1313_DATA + DDRSS_PHY_1314_DATA + DDRSS_PHY_1315_DATA + DDRSS_PHY_1316_DATA + DDRSS_PHY_1317_DATA + DDRSS_PHY_1318_DATA + DDRSS_PHY_1319_DATA + DDRSS_PHY_1320_DATA + DDRSS_PHY_1321_DATA + DDRSS_PHY_1322_DATA + DDRSS_PHY_1323_DATA + DDRSS_PHY_1324_DATA + DDRSS_PHY_1325_DATA + DDRSS_PHY_1326_DATA + DDRSS_PHY_1327_DATA + DDRSS_PHY_1328_DATA + DDRSS_PHY_1329_DATA + DDRSS_PHY_1330_DATA + DDRSS_PHY_1331_DATA + DDRSS_PHY_1332_DATA + DDRSS_PHY_1333_DATA + DDRSS_PHY_1334_DATA + DDRSS_PHY_1335_DATA + DDRSS_PHY_1336_DATA + DDRSS_PHY_1337_DATA + DDRSS_PHY_1338_DATA + DDRSS_PHY_1339_DATA + DDRSS_PHY_1340_DATA + DDRSS_PHY_1341_DATA + DDRSS_PHY_1342_DATA + DDRSS_PHY_1343_DATA + DDRSS_PHY_1344_DATA + DDRSS_PHY_1345_DATA + DDRSS_PHY_1346_DATA + DDRSS_PHY_1347_DATA + DDRSS_PHY_1348_DATA + DDRSS_PHY_1349_DATA + DDRSS_PHY_1350_DATA + DDRSS_PHY_1351_DATA + DDRSS_PHY_1352_DATA + DDRSS_PHY_1353_DATA + DDRSS_PHY_1354_DATA + DDRSS_PHY_1355_DATA + DDRSS_PHY_1356_DATA + DDRSS_PHY_1357_DATA + DDRSS_PHY_1358_DATA + DDRSS_PHY_1359_DATA + DDRSS_PHY_1360_DATA + DDRSS_PHY_1361_DATA + DDRSS_PHY_1362_DATA + DDRSS_PHY_1363_DATA + DDRSS_PHY_1364_DATA + DDRSS_PHY_1365_DATA + DDRSS_PHY_1366_DATA + DDRSS_PHY_1367_DATA + DDRSS_PHY_1368_DATA + DDRSS_PHY_1369_DATA + DDRSS_PHY_1370_DATA + DDRSS_PHY_1371_DATA + DDRSS_PHY_1372_DATA + DDRSS_PHY_1373_DATA + DDRSS_PHY_1374_DATA + DDRSS_PHY_1375_DATA + DDRSS_PHY_1376_DATA + DDRSS_PHY_1377_DATA + DDRSS_PHY_1378_DATA + DDRSS_PHY_1379_DATA + DDRSS_PHY_1380_DATA + DDRSS_PHY_1381_DATA + DDRSS_PHY_1382_DATA + DDRSS_PHY_1383_DATA + DDRSS_PHY_1384_DATA + DDRSS_PHY_1385_DATA + DDRSS_PHY_1386_DATA + DDRSS_PHY_1387_DATA + DDRSS_PHY_1388_DATA + DDRSS_PHY_1389_DATA + DDRSS_PHY_1390_DATA + DDRSS_PHY_1391_DATA + DDRSS_PHY_1392_DATA + DDRSS_PHY_1393_DATA + DDRSS_PHY_1394_DATA + DDRSS_PHY_1395_DATA + DDRSS_PHY_1396_DATA + DDRSS_PHY_1397_DATA + DDRSS_PHY_1398_DATA + DDRSS_PHY_1399_DATA + DDRSS_PHY_1400_DATA + DDRSS_PHY_1401_DATA + DDRSS_PHY_1402_DATA + DDRSS_PHY_1403_DATA + DDRSS_PHY_1404_DATA + DDRSS_PHY_1405_DATA + DDRSS_PHY_1406_DATA + DDRSS_PHY_1407_DATA + DDRSS_PHY_1408_DATA + DDRSS_PHY_1409_DATA + DDRSS_PHY_1410_DATA + DDRSS_PHY_1411_DATA + DDRSS_PHY_1412_DATA + DDRSS_PHY_1413_DATA + DDRSS_PHY_1414_DATA + DDRSS_PHY_1415_DATA + DDRSS_PHY_1416_DATA + DDRSS_PHY_1417_DATA + DDRSS_PHY_1418_DATA + DDRSS_PHY_1419_DATA + DDRSS_PHY_1420_DATA + DDRSS_PHY_1421_DATA + DDRSS_PHY_1422_DATA + >; +}; diff --git a/doc/driver-model/spi-howto.rst b/doc/driver-model/spi-howto.rst index 5540eb7..9631a50 100644 --- a/doc/driver-model/spi-howto.rst +++ b/doc/driver-model/spi-howto.rst @@ -116,7 +116,7 @@ Put this code at the bottom of your existing driver file: static int exynos_cs_info(struct udevice *bus, uint cs, struct spi_cs_info *info) { - return -ENODEV; + return -EINVAL; } static const struct dm_spi_ops exynos_spi_ops = { @@ -633,9 +633,9 @@ is not obvious from outside the driver. In this case you can provide a method for cs_info() to deal with this. If you don't provide it, then the device tree will be used to determine what chip selects are valid. -Return -ENODEV if the supplied chip select is invalid, or 0 if it is valid. -If you don't provide the cs_info() method, -ENODEV is assumed for all -chip selects that do not appear in the device tree. +Return -EINVAL if the supplied chip select is invalid, or 0 if it is valid. +If you don't provide the cs_info() method, 0 is assumed for all chip selects +that do not appear in the device tree. Test it diff --git a/doc/index.rst b/doc/index.rst index 458f0d2..206a045 100644 --- a/doc/index.rst +++ b/doc/index.rst @@ -15,6 +15,17 @@ if you want to help out. .. toctree:: :maxdepth: 2 +User-oriented documentation +--------------------------- + +The following manuals are written for *users* of the U-Boot - those who are +trying to get it to work optimally on a given system. + +.. toctree:: + :maxdepth: 2 + + build/index + Unified Extensible Firmware (UEFI) ---------------------------------- diff --git a/drivers/Kconfig b/drivers/Kconfig index 350acf8..9d99ce0 100644 --- a/drivers/Kconfig +++ b/drivers/Kconfig @@ -118,6 +118,8 @@ source "drivers/tpm/Kconfig" source "drivers/usb/Kconfig" +source "drivers/ufs/Kconfig" + source "drivers/video/Kconfig" source "drivers/virtio/Kconfig" diff --git a/drivers/Makefile b/drivers/Makefile index a4bb5e4..0befedd 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -111,6 +111,7 @@ obj-y += soc/ obj-y += thermal/ obj-$(CONFIG_TEE) += tee/ obj-y += axi/ +obj-y += ufs/ obj-$(CONFIG_W1) += w1/ obj-$(CONFIG_W1_EEPROM) += w1-eeprom/ diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 8de6777..06131ed 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -16,6 +16,7 @@ obj-y += imx/ obj-y += tegra/ obj-$(CONFIG_ARCH_ASPEED) += aspeed/ obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/ +obj-$(CONFIG_ARCH_MTMIPS) += mtmips/ obj-$(CONFIG_ARCH_MESON) += meson/ obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/ obj-$(CONFIG_ARCH_SOCFPGA) += altera/ diff --git a/drivers/clk/clk_versal.c b/drivers/clk/clk_versal.c index df87645..7e97b0c 100644 --- a/drivers/clk/clk_versal.c +++ b/drivers/clk/clk_versal.c @@ -12,6 +12,7 @@ #include <clk.h> #include <dm.h> #include <asm/arch/sys_proto.h> +#include <zynqmp_firmware.h> #define MAX_PARENT 100 #define MAX_NODES 6 @@ -362,7 +363,7 @@ static u32 versal_clock_get_div(u32 clk_id) u32 ret_payload[PAYLOAD_ARG_CNT]; u32 div; - versal_pm_request(PM_CLOCK_GETDIVIDER, clk_id, 0, 0, 0, ret_payload); + xilinx_pm_request(PM_CLOCK_GETDIVIDER, clk_id, 0, 0, 0, ret_payload); div = ret_payload[1]; return div; @@ -372,7 +373,7 @@ static u32 versal_clock_set_div(u32 clk_id, u32 div) { u32 ret_payload[PAYLOAD_ARG_CNT]; - versal_pm_request(PM_CLOCK_SETDIVIDER, clk_id, div, 0, 0, ret_payload); + xilinx_pm_request(PM_CLOCK_SETDIVIDER, clk_id, div, 0, 0, ret_payload); return div; } @@ -382,7 +383,7 @@ static u64 versal_clock_ref(u32 clk_id) u32 ret_payload[PAYLOAD_ARG_CNT]; int ref; - versal_pm_request(PM_CLOCK_GETPARENT, clk_id, 0, 0, 0, ret_payload); + xilinx_pm_request(PM_CLOCK_GETPARENT, clk_id, 0, 0, 0, ret_payload); ref = ret_payload[0]; if (!(ref & 1)) return ref_clk; @@ -401,7 +402,7 @@ static u64 versal_clock_get_pll_rate(u32 clk_id) u32 parent_rate, parent_id; u32 id = clk_id & 0xFFF; - versal_pm_request(PM_CLOCK_GETSTATE, clk_id, 0, 0, 0, ret_payload); + xilinx_pm_request(PM_CLOCK_GETSTATE, clk_id, 0, 0, 0, ret_payload); res = ret_payload[1]; if (!res) { printf("0%x PLL not enabled\n", clk_id); @@ -411,9 +412,9 @@ static u64 versal_clock_get_pll_rate(u32 clk_id) parent_id = clock[clock[id].parent[0].id].clk_id; parent_rate = versal_clock_ref(parent_id); - versal_pm_request(PM_CLOCK_GETDIVIDER, clk_id, 0, 0, 0, ret_payload); + xilinx_pm_request(PM_CLOCK_GETDIVIDER, clk_id, 0, 0, 0, ret_payload); fbdiv = ret_payload[1]; - versal_pm_request(PM_CLOCK_PLL_GETPARAM, clk_id, 2, 0, 0, ret_payload); + xilinx_pm_request(PM_CLOCK_PLL_GETPARAM, clk_id, 2, 0, 0, ret_payload); frac = ret_payload[1]; freq = (fbdiv * parent_rate) >> (1 << frac); @@ -440,7 +441,7 @@ static u32 versal_clock_get_parentid(u32 clk_id) u32 id = clk_id & 0xFFF; if (versal_clock_mux(clk_id)) { - versal_pm_request(PM_CLOCK_GETPARENT, clk_id, 0, 0, 0, + xilinx_pm_request(PM_CLOCK_GETPARENT, clk_id, 0, 0, 0, ret_payload); parent_id = ret_payload[1]; } diff --git a/drivers/clk/clk_zynqmp.c b/drivers/clk/clk_zynqmp.c index 167f3f7..72fc39f 100644 --- a/drivers/clk/clk_zynqmp.c +++ b/drivers/clk/clk_zynqmp.c @@ -702,7 +702,6 @@ static struct clk_ops zynqmp_clk_ops = { static const struct udevice_id zynqmp_clk_ids[] = { { .compatible = "xlnx,zynqmp-clk" }, - { .compatible = "xlnx,zynqmp-clkc" }, { } }; diff --git a/drivers/clk/mtmips/Makefile b/drivers/clk/mtmips/Makefile new file mode 100644 index 0000000..e193841 --- /dev/null +++ b/drivers/clk/mtmips/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0 + +obj-$(CONFIG_SOC_MT7628) += clk-mt7628.o diff --git a/drivers/clk/mtmips/clk-mt7628.c b/drivers/clk/mtmips/clk-mt7628.c new file mode 100644 index 0000000..35780de --- /dev/null +++ b/drivers/clk/mtmips/clk-mt7628.c @@ -0,0 +1,158 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 MediaTek Inc. All Rights Reserved. + * + * Author: Weijie Gao <weijie.gao@mediatek.com> + */ + +#include <common.h> +#include <clk-uclass.h> +#include <dm.h> +#include <dt-bindings/clock/mt7628-clk.h> +#include <linux/bitops.h> +#include <linux/io.h> + +/* SYSCFG0 */ +#define XTAL_40M_SEL BIT(6) + +/* CLKCFG0 */ +#define CLKCFG0_REG 0x0 +#define PERI_CLK_FROM_XTAL_SEL BIT(4) +#define CPU_PLL_FROM_BBP BIT(1) +#define CPU_PLL_FROM_XTAL BIT(0) + +/* CLKCFG1 */ +#define CLKCFG1_REG 0x4 + +#define CLK_SRC_CPU -1 +#define CLK_SRC_CPU_D2 -2 +#define CLK_SRC_SYS -3 +#define CLK_SRC_XTAL -4 +#define CLK_SRC_PERI -5 + +struct mt7628_clk_priv { + void __iomem *base; + int cpu_clk; + int sys_clk; + int xtal_clk; +}; + +static const int mt7628_clks[] = { + [CLK_SYS] = CLK_SRC_SYS, + [CLK_CPU] = CLK_SRC_CPU, + [CLK_XTAL] = CLK_SRC_XTAL, + [CLK_PWM] = CLK_SRC_PERI, + [CLK_MIPS_CNT] = CLK_SRC_CPU_D2, + [CLK_UART2] = CLK_SRC_PERI, + [CLK_UART1] = CLK_SRC_PERI, + [CLK_UART0] = CLK_SRC_PERI, + [CLK_SPI] = CLK_SRC_SYS, + [CLK_I2C] = CLK_SRC_PERI, +}; + +static ulong mt7628_clk_get_rate(struct clk *clk) +{ + struct mt7628_clk_priv *priv = dev_get_priv(clk->dev); + u32 val; + + if (clk->id >= ARRAY_SIZE(mt7628_clks)) + return 0; + + switch (mt7628_clks[clk->id]) { + case CLK_SRC_CPU: + return priv->cpu_clk; + case CLK_SRC_CPU_D2: + return priv->cpu_clk / 2; + case CLK_SRC_SYS: + return priv->sys_clk; + case CLK_SRC_XTAL: + return priv->xtal_clk; + case CLK_SRC_PERI: + val = readl(priv->base + CLKCFG0_REG); + if (val & PERI_CLK_FROM_XTAL_SEL) + return priv->xtal_clk; + else + return 40000000; + default: + return mt7628_clks[clk->id]; + } +} + +static int mt7628_clk_enable(struct clk *clk) +{ + struct mt7628_clk_priv *priv = dev_get_priv(clk->dev); + + if (clk->id > 31) + return -1; + + setbits_32(priv->base + CLKCFG1_REG, BIT(clk->id)); + + return 0; +} + +static int mt7628_clk_disable(struct clk *clk) +{ + struct mt7628_clk_priv *priv = dev_get_priv(clk->dev); + + if (clk->id > 31) + return -1; + + clrbits_32(priv->base + CLKCFG1_REG, BIT(clk->id)); + + return 0; +} + +const struct clk_ops mt7628_clk_ops = { + .enable = mt7628_clk_enable, + .disable = mt7628_clk_disable, + .get_rate = mt7628_clk_get_rate, +}; + +static int mt7628_clk_probe(struct udevice *dev) +{ + struct mt7628_clk_priv *priv = dev_get_priv(dev); + void __iomem *syscfg_base; + u32 val; + + priv->base = (void __iomem *)dev_remap_addr_index(dev, 0); + if (!priv->base) + return -EINVAL; + + syscfg_base = (void __iomem *)dev_remap_addr_index(dev, 1); + if (!syscfg_base) + return -EINVAL; + + val = readl(syscfg_base); + if (val & XTAL_40M_SEL) + priv->xtal_clk = 40000000; + else + priv->xtal_clk = 25000000; + + val = readl(priv->base + CLKCFG0_REG); + if (val & CPU_PLL_FROM_BBP) + priv->cpu_clk = 480000000; + else if (val & CPU_PLL_FROM_XTAL) + priv->cpu_clk = priv->xtal_clk; + else if (priv->xtal_clk == 40000000) + priv->cpu_clk = 580000000; /* (xtal_freq / 2) * 29 */ + else + priv->cpu_clk = 575000000; /* xtal_freq * 23 */ + + priv->sys_clk = priv->cpu_clk / 3; + + return 0; +} + +static const struct udevice_id mt7628_clk_ids[] = { + { .compatible = "mediatek,mt7628-clk" }, + { } +}; + +U_BOOT_DRIVER(mt7628_clk) = { + .name = "mt7628-clk", + .id = UCLASS_CLK, + .of_match = mt7628_clk_ids, + .probe = mt7628_clk_probe, + .priv_auto_alloc_size = sizeof(struct mt7628_clk_priv), + .ops = &mt7628_clk_ops, +}; diff --git a/drivers/crypto/rsa_mod_exp/mod_exp_uclass.c b/drivers/crypto/rsa_mod_exp/mod_exp_uclass.c index 93deaa7..e91fe64 100644 --- a/drivers/crypto/rsa_mod_exp/mod_exp_uclass.c +++ b/drivers/crypto/rsa_mod_exp/mod_exp_uclass.c @@ -13,10 +13,23 @@ #include <asm/io.h> #include <linux/list.h> +#if !defined(USE_HOSTCC) && defined(CONFIG_NEEDS_MANUAL_RELOC) +DECLARE_GLOBAL_DATA_PTR; +#endif + int rsa_mod_exp(struct udevice *dev, const uint8_t *sig, uint32_t sig_len, struct key_prop *node, uint8_t *out) { - const struct mod_exp_ops *ops = device_get_ops(dev); + struct mod_exp_ops *ops = (struct mod_exp_ops *)device_get_ops(dev); + +#if !defined(USE_HOSTCC) && defined(CONFIG_NEEDS_MANUAL_RELOC) + static bool done; + + if (!done) { + done = true; + ops->mod_exp += gd->reloc_off; + } +#endif if (!ops->mod_exp) return -ENOSYS; diff --git a/drivers/firmware/firmware-zynqmp.c b/drivers/firmware/firmware-zynqmp.c index 15e82ac..dea58b5 100644 --- a/drivers/firmware/firmware-zynqmp.c +++ b/drivers/firmware/firmware-zynqmp.c @@ -7,10 +7,10 @@ #include <common.h> #include <dm.h> +#include <zynqmp_firmware.h> #if defined(CONFIG_ZYNQMP_IPI) #include <mailbox.h> -#include <zynqmp_firmware.h> #include <asm/arch/sys_proto.h> #define PMUFW_PAYLOAD_ARG_CNT 8 @@ -54,7 +54,7 @@ static int send_req(const u32 *req, size_t req_len, u32 *res, size_t res_maxlen) if (IS_ENABLED(CONFIG_SPL_BUILD)) return ipi_req(req, req_len, res, res_maxlen); - return invoke_smc(req[0] + PM_SIP_SVC, 0, 0, 0, 0, res); + return xilinx_pm_request(req[0], 0, 0, 0, 0, res); } unsigned int zynqmp_firmware_version(void) @@ -110,19 +110,19 @@ void zynqmp_pmufw_load_config_object(const void *cfg_obj, size_t size) static int zynqmp_power_probe(struct udevice *dev) { - int ret = 0; + int ret; debug("%s, (dev=%p)\n", __func__, dev); ret = mbox_get_by_name(dev, "tx", &zynqmp_power.tx_chan); if (ret) { - debug("%s, cannot tx mailbox\n", __func__); + debug("%s: Cannot find tx mailbox\n", __func__); return ret; } ret = mbox_get_by_name(dev, "rx", &zynqmp_power.rx_chan); if (ret) { - debug("%s, cannot rx mailbox\n", __func__); + debug("%s: Cannot find rx mailbox\n", __func__); return ret; } @@ -147,6 +147,37 @@ U_BOOT_DRIVER(zynqmp_power) = { }; #endif +int __maybe_unused xilinx_pm_request(u32 api_id, u32 arg0, u32 arg1, u32 arg2, + u32 arg3, u32 *ret_payload) +{ + /* + * Added SIP service call Function Identifier + * Make sure to stay in x0 register + */ + struct pt_regs regs; + + if (current_el() == 3) { + printf("%s: Can't call SMC from EL3 context\n", __func__); + return -EPERM; + } + + regs.regs[0] = PM_SIP_SVC | api_id; + regs.regs[1] = ((u64)arg1 << 32) | arg0; + regs.regs[2] = ((u64)arg3 << 32) | arg2; + + smc_call(®s); + + if (ret_payload) { + ret_payload[0] = (u32)regs.regs[0]; + ret_payload[1] = upper_32_bits(regs.regs[0]); + ret_payload[2] = (u32)regs.regs[1]; + ret_payload[3] = upper_32_bits(regs.regs[1]); + ret_payload[4] = (u32)regs.regs[2]; + } + + return regs.regs[0]; +} + static const struct udevice_id zynqmp_firmware_ids[] = { { .compatible = "xlnx,zynqmp-firmware" }, { .compatible = "xlnx,versal-firmware"}, diff --git a/drivers/fpga/versalpl.c b/drivers/fpga/versalpl.c index 69617a9..4bcc213 100644 --- a/drivers/fpga/versalpl.c +++ b/drivers/fpga/versalpl.c @@ -8,6 +8,7 @@ #include <asm/arch/sys_proto.h> #include <memalign.h> #include <versalpl.h> +#include <zynqmp_firmware.h> static ulong versal_align_dma_buffer(ulong *buf, u32 len) { @@ -38,7 +39,7 @@ static int versal_load(xilinx_desc *desc, const void *buf, size_t bsize, buf_lo = lower_32_bits(bin_buf); buf_hi = upper_32_bits(bin_buf); - ret = versal_pm_request(VERSAL_PM_LOAD_PDI, VERSAL_PM_PDI_TYPE, buf_lo, + ret = xilinx_pm_request(VERSAL_PM_LOAD_PDI, VERSAL_PM_PDI_TYPE, buf_lo, buf_hi, 0, ret_payload); if (ret) puts("PL FPGA LOAD fail\n"); diff --git a/drivers/fpga/zynqmppl.c b/drivers/fpga/zynqmppl.c index c267027..d129b54 100644 --- a/drivers/fpga/zynqmppl.c +++ b/drivers/fpga/zynqmppl.c @@ -227,11 +227,12 @@ static int zynqmp_load(xilinx_desc *desc, const void *buf, size_t bsize, buf_hi = upper_32_bits(bin_buf); if (xilfpga_old) - ret = invoke_smc(ZYNQMP_SIP_SVC_PM_FPGA_LOAD, buf_lo, buf_hi, - (u32)(uintptr_t)bsizeptr, bstype, ret_payload); + ret = xilinx_pm_request(ZYNQMP_SIP_SVC_PM_FPGA_LOAD, buf_lo, + buf_hi, (u32)(uintptr_t)bsizeptr, + bstype, ret_payload); else - ret = invoke_smc(ZYNQMP_SIP_SVC_PM_FPGA_LOAD, buf_lo, buf_hi, - (u32)bsize, 0, ret_payload); + ret = xilinx_pm_request(ZYNQMP_SIP_SVC_PM_FPGA_LOAD, buf_lo, + buf_hi, (u32)bsize, 0, ret_payload); if (ret) puts("PL FPGA LOAD fail\n"); @@ -272,7 +273,8 @@ static int zynqmp_loads(xilinx_desc *desc, const void *buf, size_t bsize, buf_lo = lower_32_bits((ulong)buf); buf_hi = upper_32_bits((ulong)buf); - ret = invoke_smc(ZYNQMP_SIP_SVC_PM_FPGA_LOAD, buf_lo, buf_hi, + ret = xilinx_pm_request(ZYNQMP_SIP_SVC_PM_FPGA_LOAD, buf_lo, + buf_hi, (u32)(uintptr_t)fpga_sec_info->userkey_addr, flag, ret_payload); if (ret) @@ -289,8 +291,8 @@ static int zynqmp_pcap_info(xilinx_desc *desc) int ret; u32 ret_payload[PAYLOAD_ARG_CNT]; - ret = invoke_smc(ZYNQMP_SIP_SVC_PM_FPGA_STATUS, 0, 0, 0, - 0, ret_payload); + ret = xilinx_pm_request(ZYNQMP_SIP_SVC_PM_FPGA_STATUS, 0, 0, 0, + 0, ret_payload); if (!ret) printf("PCAP status\t0x%x\n", ret_payload[1]); diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 39f2c7e..c1ad5d6 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -301,7 +301,7 @@ config MVEBU_GPIO config ZYNQ_GPIO bool "Zynq GPIO driver" - depends on DM_GPIO && (ARCH_ZYNQ || ARCH_ZYNQMP) + depends on DM_GPIO && (ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_VERSAL) default y help Supports GPIO access on Zynq SoC. diff --git a/drivers/gpio/zynq_gpio.c b/drivers/gpio/zynq_gpio.c index a760c5b..fe3b2c3 100644 --- a/drivers/gpio/zynq_gpio.c +++ b/drivers/gpio/zynq_gpio.c @@ -93,6 +93,9 @@ /* GPIO upper 16 bit mask */ #define ZYNQ_GPIO_UPPER_MASK 0xFFFF0000 +#define PMC_GPIO_NR_GPIOS 116 +#define PMC_GPIO_MAX_BANK 5 + struct zynq_gpio_platdata { phys_addr_t base; const struct zynq_platform_data *p_data; @@ -114,6 +117,33 @@ struct zynq_platform_data { u32 bank_max[ZYNQMP_GPIO_MAX_BANK]; }; +#define VERSAL_GPIO_NR_GPIOS 58 +#define VERSAL_GPIO_MAX_BANK 4 + +static const struct zynq_platform_data versal_gpio_def = { + .label = "versal_gpio", + .ngpio = VERSAL_GPIO_NR_GPIOS, + .max_bank = VERSAL_GPIO_MAX_BANK, + .bank_min[0] = 0, + .bank_max[0] = 25, + .bank_min[3] = 26, + .bank_max[3] = 57, +}; + +static const struct zynq_platform_data pmc_gpio_def = { + .label = "pmc_gpio", + .ngpio = PMC_GPIO_NR_GPIOS, + .max_bank = PMC_GPIO_MAX_BANK, + .bank_min[0] = 0, + .bank_max[0] = 25, + .bank_min[1] = 26, + .bank_max[1] = 51, + .bank_min[3] = 52, + .bank_max[3] = 83, + .bank_min[4] = 84, + .bank_max[4] = 115, +}; + static const struct zynq_platform_data zynqmp_gpio_def = { .label = "zynqmp_gpio", .ngpio = ZYNQMP_GPIO_NR_GPIOS, @@ -329,6 +359,10 @@ static const struct udevice_id zynq_gpio_ids[] = { .data = (ulong)&zynq_gpio_def}, { .compatible = "xlnx,zynqmp-gpio-1.0", .data = (ulong)&zynqmp_gpio_def}, + { .compatible = "xlnx,versal-gpio-1.0", + .data = (ulong)&versal_gpio_def}, + { .compatible = "xlnx,pmc-gpio-1.0", + .data = (ulong)&pmc_gpio_def }, { } }; diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index ba50893..4985ea0 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -412,4 +412,13 @@ config IHS_FPGA by the devices. This driver supports both CON and CPU variants of the devices, depending on the device tree entry. +config MICROCHIP_FLEXCOM + bool "Enable Microchip Flexcom driver" + depends on MISC + help + The Atmel Flexcom is just a wrapper which embeds a SPI controller, + an I2C controller and an USART. + Only one function can be used at a time and is chosen at boot time + according to the device tree. + endmenu diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index 0001d10..f612636 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -65,3 +65,4 @@ obj-$(CONFIG_TWL4030_LED) += twl4030_led.o obj-$(CONFIG_VEXPRESS_CONFIG) += vexpress_config.o obj-$(CONFIG_WINBOND_W83627) += winbond_w83627.o obj-$(CONFIG_JZ4780_EFUSE) += jz4780_efuse.o +obj-$(CONFIG_MICROCHIP_FLEXCOM) += microchip_flexcom.o diff --git a/drivers/misc/microchip_flexcom.c b/drivers/misc/microchip_flexcom.c new file mode 100644 index 0000000..1bc19ed --- /dev/null +++ b/drivers/misc/microchip_flexcom.c @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2019, Microchip Technology, Inc. + * Author: Eugen Hristev <eugen.hristev@microchip.com> + */ + +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <misc.h> +#include <asm/io.h> + +struct microchip_flexcom_regs { + u32 cr; +}; + +struct microchip_flexcom_platdata { + struct microchip_flexcom_regs *regs; + u32 flexcom_mode; +}; + +static int microchip_flexcom_ofdata_to_platdata(struct udevice *dev) +{ + struct microchip_flexcom_platdata *plat = dev_get_platdata(dev); + int ret; + + plat->regs = map_physmem(devfdt_get_addr(dev), + sizeof(struct microchip_flexcom_regs), + MAP_NOCACHE); + + ret = dev_read_u32(dev, "atmel,flexcom-mode", &plat->flexcom_mode); + + if (IS_ERR_VALUE(ret)) { + debug("Missing atmel,flexcom-mode property\n"); + return ret; + } + + /* + * The mode must have only 2 bits. If any other bits are set, + * the value is not supported. + */ + if (plat->flexcom_mode & 0xfffffffc) { + debug("Wrong atmel,flexcom-mode property\n"); + return -EINVAL; + } + + writel(plat->flexcom_mode, &plat->regs->cr); + + return 0; +} + +static const struct udevice_id microchip_flexcom_ids[] = { + { .compatible = "atmel,sama5d2-flexcom" }, + { .compatible = "microchip,flexcom" }, + {} +}; + +U_BOOT_DRIVER(microchip_flexcom) = { + .name = "microchip_flexcom", + .id = UCLASS_MISC, + .of_match = microchip_flexcom_ids, + .ofdata_to_platdata = microchip_flexcom_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct microchip_flexcom_platdata), +}; diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index 18af076..85fd190 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -698,7 +698,7 @@ config FTSDC010_SDIO config MMC_MTK bool "MediaTek SD/MMC Card Interface support" - depends on ARCH_MEDIATEK + depends on ARCH_MEDIATEK || ARCH_MTMIPS depends on BLK && DM_MMC depends on OF_CONTROL help diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 28d2312..cd357ea 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -23,10 +23,6 @@ #include <asm/io.h> #include <dm.h> -#if !CONFIG_IS_ENABLED(BLK) -#include "mmc_private.h" -#endif - DECLARE_GLOBAL_DATA_PTR; #define SDHCI_IRQ_EN_BITS (IRQSTATEN_CC | IRQSTATEN_TC | \ @@ -35,7 +31,6 @@ DECLARE_GLOBAL_DATA_PTR; IRQSTATEN_CIE | IRQSTATEN_DTOE | IRQSTATEN_DCE | \ IRQSTATEN_DEBE | IRQSTATEN_BRR | IRQSTATEN_BWR | \ IRQSTATEN_DINT) -#define ESDHC_DRIVER_STAGE_VALUE 0xffffffff struct fsl_esdhc { uint dsaddr; /* SDMA system address register */ @@ -98,7 +93,7 @@ struct fsl_esdhc_priv { struct clk per_clk; unsigned int clock; unsigned int bus_width; -#if !CONFIG_IS_ENABLED(BLK) +#if !CONFIG_IS_ENABLED(DM_MMC) struct mmc *mmc; #endif struct udevice *dev; @@ -506,7 +501,6 @@ static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock) struct fsl_esdhc *regs = priv->esdhc_regs; int div = 1; int pre_div = 2; - int ddr_pre_div = mmc->ddr_mode ? 2 : 1; unsigned int sdhc_clk = priv->sdhc_clk; u32 time_out; u32 value; @@ -515,10 +509,10 @@ static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock) if (clock < mmc->cfg->f_min) clock = mmc->cfg->f_min; - while (sdhc_clk / (16 * pre_div * ddr_pre_div) > clock && pre_div < 256) + while (sdhc_clk / (16 * pre_div) > clock && pre_div < 256) pre_div *= 2; - while (sdhc_clk / (div * pre_div * ddr_pre_div) > clock && div < 16) + while (sdhc_clk / (div * pre_div) > clock && div < 16) div++; pre_div >>= 1; @@ -778,9 +772,6 @@ static int fsl_esdhc_init(struct fsl_esdhc_priv *priv, cfg->host_caps = MMC_MODE_4BIT; cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT; -#ifdef CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE - cfg->host_caps |= MMC_MODE_DDR_52MHz; -#endif if (priv->bus_width > 0) { if (priv->bus_width < 8) @@ -960,9 +951,6 @@ static int fsl_esdhc_probe(struct udevice *dev) fdt_addr_t addr; unsigned int val; struct mmc *mmc; -#if !CONFIG_IS_ENABLED(BLK) - struct blk_desc *bdesc; -#endif int ret; addr = dev_read_addr(dev); @@ -1028,32 +1016,12 @@ static int fsl_esdhc_probe(struct udevice *dev) mmc = &plat->mmc; mmc->cfg = &plat->cfg; mmc->dev = dev; -#if !CONFIG_IS_ENABLED(BLK) - mmc->priv = priv; - - /* Setup dsr related values */ - mmc->dsr_imp = 0; - mmc->dsr = ESDHC_DRIVER_STAGE_VALUE; - /* Setup the universal parts of the block interface just once */ - bdesc = mmc_get_blk_desc(mmc); - bdesc->if_type = IF_TYPE_MMC; - bdesc->removable = 1; - bdesc->devnum = mmc_get_next_devnum(); - bdesc->block_read = mmc_bread; - bdesc->block_write = mmc_bwrite; - bdesc->block_erase = mmc_berase; - - /* setup initial part type */ - bdesc->part_type = mmc->cfg->part_type; - mmc_list_add(mmc); -#endif upriv->mmc = mmc; return esdhc_init_common(priv, mmc); } -#if CONFIG_IS_ENABLED(DM_MMC) static int fsl_esdhc_get_cd(struct udevice *dev) { struct fsl_esdhc_priv *priv = dev_get_priv(dev); @@ -1086,30 +1054,25 @@ static const struct dm_mmc_ops fsl_esdhc_ops = { .execute_tuning = fsl_esdhc_execute_tuning, #endif }; -#endif static const struct udevice_id fsl_esdhc_ids[] = { { .compatible = "fsl,esdhc", }, { /* sentinel */ } }; -#if CONFIG_IS_ENABLED(BLK) static int fsl_esdhc_bind(struct udevice *dev) { struct fsl_esdhc_plat *plat = dev_get_platdata(dev); return mmc_bind(dev, &plat->mmc, &plat->cfg); } -#endif U_BOOT_DRIVER(fsl_esdhc) = { .name = "fsl-esdhc-mmc", .id = UCLASS_MMC, .of_match = fsl_esdhc_ids, .ops = &fsl_esdhc_ops, -#if CONFIG_IS_ENABLED(BLK) .bind = fsl_esdhc_bind, -#endif .probe = fsl_esdhc_probe, .platdata_auto_alloc_size = sizeof(struct fsl_esdhc_plat), .priv_auto_alloc_size = sizeof(struct fsl_esdhc_priv), diff --git a/drivers/mmc/mtk-sd.c b/drivers/mmc/mtk-sd.c index f555357..ffd647f 100644 --- a/drivers/mmc/mtk-sd.c +++ b/drivers/mmc/mtk-sd.c @@ -217,6 +217,7 @@ struct mtk_sd_regs { struct msdc_compatible { u8 clk_div_bits; + u8 sclk_cycle_shift; bool pad_tune0; bool async_fifo; bool data_tune; @@ -269,6 +270,7 @@ struct msdc_host { /* whether to use gpio detection or built-in hw detection */ bool builtin_cd; + bool cd_active_high; /* card detection / write protection GPIOs */ #if CONFIG_IS_ENABLED(DM_GPIO) @@ -664,7 +666,7 @@ static int msdc_ops_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, static void msdc_set_timeout(struct msdc_host *host, u32 ns, u32 clks) { - u32 timeout, clk_ns; + u32 timeout, clk_ns, shift; u32 mode = 0; host->timeout_ns = ns; @@ -673,10 +675,11 @@ static void msdc_set_timeout(struct msdc_host *host, u32 ns, u32 clks) if (host->sclk == 0) { timeout = 0; } else { + shift = host->dev_comp->sclk_cycle_shift; clk_ns = 1000000000UL / host->sclk; timeout = (ns + clk_ns - 1) / clk_ns + clks; /* unit is 1048576 sclk cycles */ - timeout = (timeout + (0x1 << 20) - 1) >> 20; + timeout = (timeout + (0x1 << shift) - 1) >> shift; if (host->dev_comp->clk_div_bits == 8) mode = (readl(&host->base->msdc_cfg) & MSDC_CFG_CKMOD_M) >> MSDC_CFG_CKMOD_S; @@ -850,7 +853,9 @@ static int msdc_ops_get_cd(struct udevice *dev) if (host->builtin_cd) { val = readl(&host->base->msdc_ps); - return !(val & MSDC_PS_CDSTS); + val = !!(val & MSDC_PS_CDSTS); + + return !val ^ host->cd_active_high; } #if CONFIG_IS_ENABLED(DM_GPIO) @@ -1301,7 +1306,7 @@ static int msdc_drv_probe(struct udevice *dev) host->mmc = &plat->mmc; host->timeout_ns = 100000000; - host->timeout_clks = 3 * 1048576; + host->timeout_clks = 3 * (1 << host->dev_comp->sclk_cycle_shift); #ifdef CONFIG_PINCTRL pinctrl_select_state(dev, "default"); @@ -1353,6 +1358,7 @@ static int msdc_ofdata_to_platdata(struct udevice *dev) host->latch_ck = dev_read_u32_default(dev, "latch-ck", 0); host->r_smpl = dev_read_u32_default(dev, "r_smpl", 0); host->builtin_cd = dev_read_u32_default(dev, "builtin-cd", 0); + host->cd_active_high = dev_read_bool(dev, "cd-active-high"); return 0; } @@ -1374,8 +1380,20 @@ static const struct dm_mmc_ops msdc_ops = { #endif }; +static const struct msdc_compatible mt7620_compat = { + .clk_div_bits = 8, + .sclk_cycle_shift = 16, + .pad_tune0 = false, + .async_fifo = false, + .data_tune = false, + .busy_check = false, + .stop_clk_fix = false, + .enhance_rx = false +}; + static const struct msdc_compatible mt7623_compat = { .clk_div_bits = 12, + .sclk_cycle_shift = 20, .pad_tune0 = true, .async_fifo = true, .data_tune = true, @@ -1386,6 +1404,7 @@ static const struct msdc_compatible mt7623_compat = { static const struct msdc_compatible mt8516_compat = { .clk_div_bits = 12, + .sclk_cycle_shift = 20, .pad_tune0 = true, .async_fifo = true, .data_tune = true, @@ -1395,6 +1414,7 @@ static const struct msdc_compatible mt8516_compat = { static const struct msdc_compatible mt8183_compat = { .clk_div_bits = 12, + .sclk_cycle_shift = 20, .pad_tune0 = true, .async_fifo = true, .data_tune = true, @@ -1403,6 +1423,7 @@ static const struct msdc_compatible mt8183_compat = { }; static const struct udevice_id msdc_ids[] = { + { .compatible = "mediatek,mt7620-mmc", .data = (ulong)&mt7620_compat }, { .compatible = "mediatek,mt7623-mmc", .data = (ulong)&mt7623_compat }, { .compatible = "mediatek,mt8516-mmc", .data = (ulong)&mt8516_compat }, { .compatible = "mediatek,mt8183-mmc", .data = (ulong)&mt8183_compat }, diff --git a/drivers/mtd/Kconfig b/drivers/mtd/Kconfig index 0050fb2..37f379d 100644 --- a/drivers/mtd/Kconfig +++ b/drivers/mtd/Kconfig @@ -94,6 +94,13 @@ config RENESAS_RPC_HF This enables access to Hyperflash memory through the Renesas RCar Gen3 RPC controller. +config HBMC_AM654 + bool "HyperBus controller driver for AM65x SoC" + depends on SYSCON + help + This is the driver for HyperBus controller on TI's AM65x and + other SoCs + source "drivers/mtd/nand/Kconfig" source "drivers/mtd/spi/Kconfig" diff --git a/drivers/mtd/Makefile b/drivers/mtd/Makefile index 22ceda9..293079d 100644 --- a/drivers/mtd/Makefile +++ b/drivers/mtd/Makefile @@ -18,5 +18,6 @@ obj-$(CONFIG_FLASH_PIC32) += pic32_flash.o obj-$(CONFIG_ST_SMI) += st_smi.o obj-$(CONFIG_STM32_FLASH) += stm32_flash.o obj-$(CONFIG_RENESAS_RPC_HF) += renesas_rpc_hf.o +obj-$(CONFIG_HBMC_AM654) += hbmc-am654.o obj-y += nand/ diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c index c59254c..0574fa6 100644 --- a/drivers/mtd/cfi_flash.c +++ b/drivers/mtd/cfi_flash.c @@ -178,7 +178,8 @@ __maybe_weak u64 flash_read64(void *addr) /*----------------------------------------------------------------------- */ #if defined(CONFIG_ENV_IS_IN_FLASH) || defined(CONFIG_ENV_ADDR_REDUND) || \ - (CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE) + (defined(CONFIG_SYS_MONITOR_BASE) && \ + (CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE)) static flash_info_t *flash_get_info(ulong base) { int i; @@ -2329,7 +2330,8 @@ static void flash_protect_default(void) #endif /* Monitor protection ON by default */ -#if (CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE) && \ +#if defined(CONFIG_SYS_MONITOR_BASE) && \ + (CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE) && \ (!defined(CONFIG_MONITOR_IS_IN_RAM)) flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE, diff --git a/drivers/mtd/hbmc-am654.c b/drivers/mtd/hbmc-am654.c new file mode 100644 index 0000000..5a560f1 --- /dev/null +++ b/drivers/mtd/hbmc-am654.c @@ -0,0 +1,105 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ +// Author: Vignesh Raghavendra <vigneshr@ti.com> + +#include <common.h> +#include <asm/io.h> +#include <dm.h> +#include <regmap.h> +#include <syscon.h> + +#define FSS_SYSC_REG 0x4 + +#define HYPERBUS_CALIB_COUNT 25 + +struct am654_hbmc_priv { + void __iomem *mmiobase; + bool calibrated; +}; + +/* Calibrate by looking for "QRY" string within the CFI space */ +static int am654_hyperbus_calibrate(struct udevice *dev) +{ + struct am654_hbmc_priv *priv = dev_get_priv(dev); + int count = HYPERBUS_CALIB_COUNT; + int pass_count = 0; + u16 qry[3]; + + if (priv->calibrated) + return 0; + + writew(0xF0, priv->mmiobase); + writew(0x98, priv->mmiobase + 0xaa); + + while (count--) { + qry[0] = readw(priv->mmiobase + 0x20); + qry[1] = readw(priv->mmiobase + 0x22); + qry[2] = readw(priv->mmiobase + 0x24); + + if (qry[0] == 'Q' && qry[1] == 'R' && qry[2] == 'Y') + pass_count++; + else + pass_count = 0; + if (pass_count == 5) + break; + } + writew(0xF0, priv->mmiobase); + writew(0xFF, priv->mmiobase); + + return pass_count == 5; +} + +static int am654_select_hbmc(struct udevice *dev) +{ + struct regmap *regmap = syscon_get_regmap(dev_get_parent(dev)); + + return regmap_update_bits(regmap, FSS_SYSC_REG, 0x2, 0x2); +} + +static int am654_hbmc_bind(struct udevice *dev) +{ + return dm_scan_fdt_dev(dev); +} + +static int am654_hbmc_probe(struct udevice *dev) +{ + struct am654_hbmc_priv *priv = dev_get_priv(dev); + int ret; + + priv->mmiobase = devfdt_remap_addr_index(dev, 1); + if (dev_read_bool(dev, "mux-controls")) { + ret = am654_select_hbmc(dev); + if (ret) { + dev_err(dev, "Failed to select HBMC mux\n"); + return ret; + } + } + + if (!priv->calibrated) { + ret = am654_hyperbus_calibrate(dev); + if (!ret) { + dev_err(dev, "Calibration Failed\n"); + return -EIO; + } + } + priv->calibrated = true; + + return 0; +} + +static const struct udevice_id am654_hbmc_dt_ids[] = { + { + .compatible = "ti,am654-hbmc", + }, + { /* end of table */ } +}; + +U_BOOT_DRIVER(hbmc_am654) = { + .name = "hbmc-am654", + .id = UCLASS_MTD, + .of_match = am654_hbmc_dt_ids, + .probe = am654_hbmc_probe, + .bind = am654_hbmc_bind, + .priv_auto_alloc_size = sizeof(struct am654_hbmc_priv), +}; diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index a129f44..2000826 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -72,6 +72,12 @@ config NAND_BRCMNAND Enable the driver for NAND flash on platforms using a Broadcom NAND controller. +config NAND_BRCMNAND_6368 + bool "Support Broadcom NAND controller on bcm6368" + depends on NAND_BRCMNAND && ARCH_BMIPS + help + Enable support for broadcom nand driver on bcm6368. + config NAND_BRCMNAND_6838 bool "Support Broadcom NAND controller on bcm6838" depends on NAND_BRCMNAND && ARCH_BMIPS && SOC_BMIPS_BCM6838 diff --git a/drivers/mtd/nand/raw/brcmnand/Makefile b/drivers/mtd/nand/raw/brcmnand/Makefile index a2363cc..7e70b85 100644 --- a/drivers/mtd/nand/raw/brcmnand/Makefile +++ b/drivers/mtd/nand/raw/brcmnand/Makefile @@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0+ +obj-$(CONFIG_NAND_BRCMNAND_6368) += bcm6368_nand.o obj-$(CONFIG_NAND_BRCMNAND_63158) += bcm63158_nand.o obj-$(CONFIG_NAND_BRCMNAND_6838) += bcm6838_nand.o obj-$(CONFIG_NAND_BRCMNAND_6858) += bcm6858_nand.o diff --git a/drivers/mtd/nand/raw/brcmnand/bcm6368_nand.c b/drivers/mtd/nand/raw/brcmnand/bcm6368_nand.c new file mode 100644 index 0000000..e2f5452 --- /dev/null +++ b/drivers/mtd/nand/raw/brcmnand/bcm6368_nand.c @@ -0,0 +1,117 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include <common.h> +#include <asm/io.h> +#include <memalign.h> +#include <nand.h> +#include <linux/errno.h> +#include <linux/io.h> +#include <linux/ioport.h> +#include <dm.h> + +#include "brcmnand.h" + +struct bcm6368_nand_soc { + struct brcmnand_soc soc; + void __iomem *base; +}; + +#define soc_to_priv(_soc) container_of(_soc, struct bcm6368_nand_soc, soc) + +#define BCM6368_NAND_INT 0x00 +#define BCM6368_NAND_STATUS_SHIFT 0 +#define BCM6368_NAND_STATUS_MASK (0xfff << BCM6368_NAND_STATUS_SHIFT) +#define BCM6368_NAND_ENABLE_SHIFT 16 +#define BCM6368_NAND_ENABLE_MASK (0xffff << BCM6368_NAND_ENABLE_SHIFT) + +enum { + BCM6368_NP_READ = BIT(0), + BCM6368_BLOCK_ERASE = BIT(1), + BCM6368_COPY_BACK = BIT(2), + BCM6368_PAGE_PGM = BIT(3), + BCM6368_CTRL_READY = BIT(4), + BCM6368_DEV_RBPIN = BIT(5), + BCM6368_ECC_ERR_UNC = BIT(6), + BCM6368_ECC_ERR_CORR = BIT(7), +}; + +static bool bcm6368_nand_intc_ack(struct brcmnand_soc *soc) +{ + struct bcm6368_nand_soc *priv = soc_to_priv(soc); + void __iomem *mmio = priv->base + BCM6368_NAND_INT; + u32 val = brcmnand_readl(mmio); + + if (val & (BCM6368_CTRL_READY << BCM6368_NAND_STATUS_SHIFT)) { + /* Ack interrupt */ + val &= ~BCM6368_NAND_STATUS_MASK; + val |= BCM6368_CTRL_READY << BCM6368_NAND_STATUS_SHIFT; + brcmnand_writel(val, mmio); + return true; + } + + return false; +} + +static void bcm6368_nand_intc_set(struct brcmnand_soc *soc, bool en) +{ + struct bcm6368_nand_soc *priv = soc_to_priv(soc); + void __iomem *mmio = priv->base + BCM6368_NAND_INT; + u32 val = brcmnand_readl(mmio); + + /* Don't ack any interrupts */ + val &= ~BCM6368_NAND_STATUS_MASK; + + if (en) + val |= BCM6368_CTRL_READY << BCM6368_NAND_ENABLE_SHIFT; + else + val &= ~(BCM6368_CTRL_READY << BCM6368_NAND_ENABLE_SHIFT); + + brcmnand_writel(val, mmio); +} + +static int bcm6368_nand_probe(struct udevice *dev) +{ + struct bcm6368_nand_soc *priv = dev_get_priv(dev); + struct brcmnand_soc *soc = &priv->soc; + + priv->base = dev_remap_addr_name(dev, "nand-int-base"); + if (!priv->base) + return -EINVAL; + + soc->ctlrdy_ack = bcm6368_nand_intc_ack; + soc->ctlrdy_set_enabled = bcm6368_nand_intc_set; + + /* Disable and ack all interrupts */ + brcmnand_writel(0, priv->base + BCM6368_NAND_INT); + brcmnand_writel(BCM6368_NAND_STATUS_MASK, + priv->base + BCM6368_NAND_INT); + + return brcmnand_probe(dev, soc); +} + +static const struct udevice_id bcm6368_nand_dt_ids[] = { + { + .compatible = "brcm,nand-bcm6368", + }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(bcm6368_nand) = { + .name = "bcm6368-nand", + .id = UCLASS_MTD, + .of_match = bcm6368_nand_dt_ids, + .probe = bcm6368_nand_probe, + .priv_auto_alloc_size = sizeof(struct bcm6368_nand_soc), +}; + +void board_nand_init(void) +{ + struct udevice *dev; + int ret; + + ret = uclass_get_device_by_driver(UCLASS_MTD, + DM_GET_DRIVER(bcm6368_nand), &dev); + if (ret && ret != -ENODEV) + pr_err("Failed to initialize %s. (error %d)\n", dev->name, + ret); +} diff --git a/drivers/mtd/nand/raw/brcmnand/brcmnand.c b/drivers/mtd/nand/raw/brcmnand/brcmnand.c index faa6da4..0745929 100644 --- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c +++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c @@ -888,183 +888,131 @@ static inline bool is_hamming_ecc(struct brcmnand_controller *ctrl, } /* - * Set mtd->ooblayout to the appropriate mtd_ooblayout_ops given - * the layout/configuration. - * Returns -ERRCODE on failure. + * Returns a nand_ecclayout strucutre for the given layout/configuration. + * Returns NULL on failure. */ -static int brcmnand_hamming_ooblayout_ecc(struct mtd_info *mtd, int section, - struct mtd_oob_region *oobregion) +static struct nand_ecclayout *brcmnand_create_layout(int ecc_level, + struct brcmnand_host *host) { - struct nand_chip *chip = mtd_to_nand(mtd); - struct brcmnand_host *host = nand_get_controller_data(chip); - struct brcmnand_cfg *cfg = &host->hwcfg; - int sas = cfg->spare_area_size << cfg->sector_size_1k; - int sectors = cfg->page_size / (512 << cfg->sector_size_1k); - - if (section >= sectors) - return -ERANGE; - - oobregion->offset = (section * sas) + 6; - oobregion->length = 3; - - return 0; -} - -static int brcmnand_hamming_ooblayout_free(struct mtd_info *mtd, int section, - struct mtd_oob_region *oobregion) -{ - struct nand_chip *chip = mtd_to_nand(mtd); - struct brcmnand_host *host = nand_get_controller_data(chip); struct brcmnand_cfg *cfg = &host->hwcfg; - int sas = cfg->spare_area_size << cfg->sector_size_1k; - int sectors = cfg->page_size / (512 << cfg->sector_size_1k); + int i, j; + struct nand_ecclayout *layout; + int req; + int sectors; + int sas; + int idx1, idx2; - if (section >= sectors * 2) - return -ERANGE; - - oobregion->offset = (section / 2) * sas; - - if (section & 1) { - oobregion->offset += 9; - oobregion->length = 7; - } else { - oobregion->length = 6; - - /* First sector of each page may have BBI */ - if (!section) { - /* - * Small-page NAND use byte 6 for BBI while large-page - * NAND use byte 0. - */ - if (cfg->page_size > 512) - oobregion->offset++; - oobregion->length--; +#ifndef __UBOOT__ + layout = devm_kzalloc(&host->pdev->dev, sizeof(*layout), GFP_KERNEL); +#else + layout = devm_kzalloc(host->pdev, sizeof(*layout), GFP_KERNEL); +#endif + if (!layout) + return NULL; + + sectors = cfg->page_size / (512 << cfg->sector_size_1k); + sas = cfg->spare_area_size << cfg->sector_size_1k; + + /* Hamming */ + if (is_hamming_ecc(host->ctrl, cfg)) { + for (i = 0, idx1 = 0, idx2 = 0; i < sectors; i++) { + /* First sector of each page may have BBI */ + if (i == 0) { + layout->oobfree[idx2].offset = i * sas + 1; + /* Small-page NAND use byte 6 for BBI */ + if (cfg->page_size == 512) + layout->oobfree[idx2].offset--; + layout->oobfree[idx2].length = 5; + } else { + layout->oobfree[idx2].offset = i * sas; + layout->oobfree[idx2].length = 6; + } + idx2++; + layout->eccpos[idx1++] = i * sas + 6; + layout->eccpos[idx1++] = i * sas + 7; + layout->eccpos[idx1++] = i * sas + 8; + layout->oobfree[idx2].offset = i * sas + 9; + layout->oobfree[idx2].length = 7; + idx2++; + /* Leave zero-terminated entry for OOBFREE */ + if (idx1 >= MTD_MAX_ECCPOS_ENTRIES_LARGE || + idx2 >= MTD_MAX_OOBFREE_ENTRIES_LARGE - 1) + break; } - } - - return 0; -} - -static const struct mtd_ooblayout_ops brcmnand_hamming_ooblayout_ops = { - .ecc = brcmnand_hamming_ooblayout_ecc, - .free = brcmnand_hamming_ooblayout_free, -}; - -static int brcmnand_bch_ooblayout_ecc(struct mtd_info *mtd, int section, - struct mtd_oob_region *oobregion) -{ - struct nand_chip *chip = mtd_to_nand(mtd); - struct brcmnand_host *host = nand_get_controller_data(chip); - struct brcmnand_cfg *cfg = &host->hwcfg; - int sas = cfg->spare_area_size << cfg->sector_size_1k; - int sectors = cfg->page_size / (512 << cfg->sector_size_1k); - - if (section >= sectors) - return -ERANGE; - oobregion->offset = (section * (sas + 1)) - chip->ecc.bytes; - oobregion->length = chip->ecc.bytes; - - return 0; -} - -static int brcmnand_bch_ooblayout_free_lp(struct mtd_info *mtd, int section, - struct mtd_oob_region *oobregion) -{ - struct nand_chip *chip = mtd_to_nand(mtd); - struct brcmnand_host *host = nand_get_controller_data(chip); - struct brcmnand_cfg *cfg = &host->hwcfg; - int sas = cfg->spare_area_size << cfg->sector_size_1k; - int sectors = cfg->page_size / (512 << cfg->sector_size_1k); - - if (section >= sectors) - return -ERANGE; - - if (sas <= chip->ecc.bytes) - return 0; - - oobregion->offset = section * sas; - oobregion->length = sas - chip->ecc.bytes; - - if (!section) { - oobregion->offset++; - oobregion->length--; + return layout; } - return 0; -} - -static int brcmnand_bch_ooblayout_free_sp(struct mtd_info *mtd, int section, - struct mtd_oob_region *oobregion) -{ - struct nand_chip *chip = mtd_to_nand(mtd); - struct brcmnand_host *host = nand_get_controller_data(chip); - struct brcmnand_cfg *cfg = &host->hwcfg; - int sas = cfg->spare_area_size << cfg->sector_size_1k; + /* + * CONTROLLER_VERSION: + * < v5.0: ECC_REQ = ceil(BCH_T * 13/8) + * >= v5.0: ECC_REQ = ceil(BCH_T * 14/8) + * But we will just be conservative. + */ + req = DIV_ROUND_UP(ecc_level * 14, 8); + if (req >= sas) { + dev_err(&host->pdev->dev, + "error: ECC too large for OOB (ECC bytes %d, spare sector %d)\n", + req, sas); + return NULL; + } - if (section > 1 || sas - chip->ecc.bytes < 6 || - (section && sas - chip->ecc.bytes == 6)) - return -ERANGE; + layout->eccbytes = req * sectors; + for (i = 0, idx1 = 0, idx2 = 0; i < sectors; i++) { + for (j = sas - req; j < sas && idx1 < + MTD_MAX_ECCPOS_ENTRIES_LARGE; j++, idx1++) + layout->eccpos[idx1] = i * sas + j; - if (!section) { - oobregion->offset = 0; - oobregion->length = 5; - } else { - oobregion->offset = 6; - oobregion->length = sas - chip->ecc.bytes - 6; + /* First sector of each page may have BBI */ + if (i == 0) { + if (cfg->page_size == 512 && (sas - req >= 6)) { + /* Small-page NAND use byte 6 for BBI */ + layout->oobfree[idx2].offset = 0; + layout->oobfree[idx2].length = 5; + idx2++; + if (sas - req > 6) { + layout->oobfree[idx2].offset = 6; + layout->oobfree[idx2].length = + sas - req - 6; + idx2++; + } + } else if (sas > req + 1) { + layout->oobfree[idx2].offset = i * sas + 1; + layout->oobfree[idx2].length = sas - req - 1; + idx2++; + } + } else if (sas > req) { + layout->oobfree[idx2].offset = i * sas; + layout->oobfree[idx2].length = sas - req; + idx2++; + } + /* Leave zero-terminated entry for OOBFREE */ + if (idx1 >= MTD_MAX_ECCPOS_ENTRIES_LARGE || + idx2 >= MTD_MAX_OOBFREE_ENTRIES_LARGE - 1) + break; } - return 0; + return layout; } -static const struct mtd_ooblayout_ops brcmnand_bch_lp_ooblayout_ops = { - .ecc = brcmnand_bch_ooblayout_ecc, - .free = brcmnand_bch_ooblayout_free_lp, -}; - -static const struct mtd_ooblayout_ops brcmnand_bch_sp_ooblayout_ops = { - .ecc = brcmnand_bch_ooblayout_ecc, - .free = brcmnand_bch_ooblayout_free_sp, -}; - -static int brcmstb_choose_ecc_layout(struct brcmnand_host *host) +static struct nand_ecclayout *brcmstb_choose_ecc_layout( + struct brcmnand_host *host) { + struct nand_ecclayout *layout; struct brcmnand_cfg *p = &host->hwcfg; - struct mtd_info *mtd = nand_to_mtd(&host->chip); - struct nand_ecc_ctrl *ecc = &host->chip.ecc; unsigned int ecc_level = p->ecc_level; - int sas = p->spare_area_size << p->sector_size_1k; - int sectors = p->page_size / (512 << p->sector_size_1k); if (p->sector_size_1k) ecc_level <<= 1; - if (is_hamming_ecc(host->ctrl, p)) { - ecc->bytes = 3 * sectors; - mtd_set_ooblayout(mtd, &brcmnand_hamming_ooblayout_ops); - return 0; - } - - /* - * CONTROLLER_VERSION: - * < v5.0: ECC_REQ = ceil(BCH_T * 13/8) - * >= v5.0: ECC_REQ = ceil(BCH_T * 14/8) - * But we will just be conservative. - */ - ecc->bytes = DIV_ROUND_UP(ecc_level * 14, 8); - if (p->page_size == 512) - mtd_set_ooblayout(mtd, &brcmnand_bch_sp_ooblayout_ops); - else - mtd_set_ooblayout(mtd, &brcmnand_bch_lp_ooblayout_ops); - - if (ecc->bytes >= sas) { + layout = brcmnand_create_layout(ecc_level, host); + if (!layout) { dev_err(&host->pdev->dev, - "error: ECC too large for OOB (ECC bytes %d, spare sector %d)\n", - ecc->bytes, sas); - return -EINVAL; + "no proper ecc_layout for this NAND cfg\n"); + return NULL; } - return 0; + return layout; } static void brcmnand_wp(struct mtd_info *mtd, int wp) @@ -2383,9 +2331,9 @@ static int brcmnand_init_cs(struct brcmnand_host *host, ofnode dn) /* only use our internal HW threshold */ mtd->bitflip_threshold = 1; - ret = brcmstb_choose_ecc_layout(host); - if (ret) - return ret; + chip->ecc.layout = brcmstb_choose_ecc_layout(host); + if (!chip->ecc.layout) + return -ENXIO; ret = nand_scan_tail(mtd); if (ret) diff --git a/drivers/mtd/spi/Kconfig b/drivers/mtd/spi/Kconfig index d3b007a..d77f818 100644 --- a/drivers/mtd/spi/Kconfig +++ b/drivers/mtd/spi/Kconfig @@ -3,6 +3,7 @@ menu "SPI Flash Support" config DM_SPI_FLASH bool "Enable Driver Model for SPI flash" depends on DM && DM_SPI + imply SPI_FLASH help Enable driver model for SPI flash. This SPI flash interface (spi_flash_probe(), spi_flash_write(), etc.) is then @@ -26,11 +27,10 @@ config SPI_FLASH_SANDBOX stored in a file on the host filesystem. config SPI_FLASH - bool "Legacy SPI Flash Interface support" - depends on SPI + bool "SPI Flash Core Interface support" select SPI_MEM help - Enable the legacy SPI flash support. This will include basic + Enable the SPI flash Core support. This will include basic standard support for things like probing, read / write, and erasing through cmd_sf interface. @@ -196,4 +196,12 @@ config SPI_FLASH_MTD If unsure, say N +config SPL_SPI_FLASH_MTD + bool "SPI flash MTD support for SPL" + depends on SPI_FLASH + help + Enable the MTD support for the SPI flash layer in SPL. + + If unsure, say N + endmenu # menu "SPI Flash Support" diff --git a/drivers/mtd/spi/Makefile b/drivers/mtd/spi/Makefile index 20db101..b5dfa30 100644 --- a/drivers/mtd/spi/Makefile +++ b/drivers/mtd/spi/Makefile @@ -19,5 +19,5 @@ endif obj-$(CONFIG_SPI_FLASH) += spi-nor.o obj-$(CONFIG_SPI_FLASH_DATAFLASH) += sf_dataflash.o -obj-$(CONFIG_SPI_FLASH_MTD) += sf_mtd.o +obj-$(CONFIG_$(SPL_)SPI_FLASH_MTD) += sf_mtd.o obj-$(CONFIG_SPI_FLASH_SANDBOX) += sandbox.o diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h index bb8c19a..5c64303 100644 --- a/drivers/mtd/spi/sf_internal.h +++ b/drivers/mtd/spi/sf_internal.h @@ -77,7 +77,7 @@ extern const struct flash_info spi_nor_ids[]; int spi_flash_cmd_get_sw_write_prot(struct spi_flash *flash); -#ifdef CONFIG_SPI_FLASH_MTD +#if CONFIG_IS_ENABLED(SPI_FLASH_MTD) int spi_flash_mtd_register(struct spi_flash *flash); void spi_flash_mtd_unregister(void); #endif diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c index 73297e1..f051e47 100644 --- a/drivers/mtd/spi/sf_probe.c +++ b/drivers/mtd/spi/sf_probe.c @@ -44,7 +44,7 @@ static int spi_flash_probe_slave(struct spi_flash *flash) if (ret) goto err_read_id; -#ifdef CONFIG_SPI_FLASH_MTD +#if CONFIG_IS_ENABLED(SPI_FLASH_MTD) ret = spi_flash_mtd_register(flash); #endif @@ -83,7 +83,7 @@ struct spi_flash *spi_flash_probe(unsigned int busnum, unsigned int cs, void spi_flash_free(struct spi_flash *flash) { -#ifdef CONFIG_SPI_FLASH_MTD +#if CONFIG_IS_ENABLED(SPI_FLASH_MTD) spi_flash_mtd_unregister(); #endif spi_free_slave(flash->spi); @@ -152,7 +152,7 @@ static int spi_flash_std_probe(struct udevice *dev) static int spi_flash_std_remove(struct udevice *dev) { -#ifdef CONFIG_SPI_FLASH_MTD +#if CONFIG_IS_ENABLED(SPI_FLASH_MTD) spi_flash_mtd_unregister(); #endif return 0; diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index 990e39d..5a8c084 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -380,12 +380,12 @@ static int spi_nor_fsr_ready(struct spi_nor *nor) if (fsr & (FSR_E_ERR | FSR_P_ERR)) { if (fsr & FSR_E_ERR) - dev_dbg(nor->dev, "Erase operation failed.\n"); + dev_err(nor->dev, "Erase operation failed.\n"); else - dev_dbg(nor->dev, "Program operation failed.\n"); + dev_err(nor->dev, "Program operation failed.\n"); if (fsr & FSR_PT_ERR) - dev_dbg(nor->dev, + dev_err(nor->dev, "Attempted to modify a protected sector.\n"); nor->write_reg(nor, SPINOR_OP_CLFSR, NULL, 0); @@ -1916,7 +1916,7 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor, erasesize = 1U << erasesize; opcode = (half >> 8) & 0xff; -#ifdef CONFIG_MTD_SPI_NOR_USE_4K_SECTORS +#ifdef CONFIG_SPI_FLASH_USE_4K_SECTORS if (erasesize == SZ_4K) { nor->erase_opcode = opcode; mtd->erasesize = erasesize; diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index 6996c0a..d3b8457 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -58,7 +58,7 @@ * All newly added entries should describe *hardware* and should use SECT_4K * (or SECT_4K_PMC) if hardware supports erasing 4 KiB sectors. For usage * scenarios excluding small sectors there is config option that can be - * disabled: CONFIG_MTD_SPI_NOR_USE_4K_SECTORS. + * disabled: CONFIG_SPI_FLASH_USE_4K_SECTORS. * For historical (and compatibility) reasons (before we got above config) some * old entries may be missing 4K flag. */ @@ -75,6 +75,7 @@ const struct flash_info spi_nor_ids[] = { { INFO("at45db161d", 0x1f2600, 0, 64 * 1024, 32, SECT_4K) }, { INFO("at45db321d", 0x1f2700, 0, 64 * 1024, 64, SECT_4K) }, { INFO("at45db641d", 0x1f2800, 0, 64 * 1024, 128, SECT_4K) }, + { INFO("at25sl321", 0x1f4216, 0, 64 * 1024, 64, SECT_4K) }, { INFO("at26df081a", 0x1f4501, 0, 64 * 1024, 16, SECT_4K) }, #endif #ifdef CONFIG_SPI_FLASH_EON /* EON */ @@ -128,6 +129,8 @@ const struct flash_info spi_nor_ids[] = { SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { INFO("is25wp128", 0x9d7018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, + { INFO("is25wp256", 0x9d7019, 0, 64 * 1024, 512, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, #endif #ifdef CONFIG_SPI_FLASH_MACRONIX /* MACRONIX */ /* Macronix */ @@ -161,12 +164,16 @@ const struct flash_info spi_nor_ids[] = { { INFO("n25q064a", 0x20bb17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) }, { INFO("n25q128a11", 0x20bb18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) }, { INFO("n25q128a13", 0x20ba18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) }, - { INFO("n25q256a", 0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, - { INFO("n25q256ax1", 0x20bb19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, + { INFO6("mt25ql256a", 0x20ba19, 0x104400, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | USE_FSR) }, + { INFO("n25q256a", 0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_FSR) }, + { INFO6("mt25qu256a", 0x20bb19, 0x104400, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | USE_FSR) }, + { INFO("n25q256ax1", 0x20bb19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ | USE_FSR) }, { INFO6("mt25qu512a", 0x20bb20, 0x104400, 64 * 1024, 1024, - SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, - { INFO("n25q512a", 0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, - { INFO("n25q512ax3", 0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, + SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | + USE_FSR) }, + { INFO("n25q512a", 0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, + { INFO6("mt25ql512a", 0x20ba20, 0x104400, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, + { INFO("n25q512ax3", 0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, { INFO("n25q00", 0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, { INFO("n25q00a", 0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, { INFO("mt25qu02g", 0x20bb22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 2ce3092..eb3d7ed 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -322,6 +322,7 @@ config MACB_ZYNQ config MT7628_ETH bool "MediaTek MT7628 Ethernet Interface" depends on SOC_MT7628 + select PHYLIB help The MediaTek MT7628 ethernet interface is used on MT7628 and MT7688 based boards. diff --git a/drivers/net/mt7628-eth.c b/drivers/net/mt7628-eth.c index 7833b2f..a1d12f6 100644 --- a/drivers/net/mt7628-eth.c +++ b/drivers/net/mt7628-eth.c @@ -18,23 +18,12 @@ #include <malloc.h> #include <miiphy.h> #include <net.h> -#include <regmap.h> -#include <syscon.h> +#include <reset.h> #include <wait_bit.h> #include <asm/io.h> #include <linux/bitfield.h> #include <linux/err.h> -/* System controller register */ -#define MT7628_RSTCTRL_REG 0x34 -#define RSTCTRL_EPHY_RST BIT(24) - -#define MT7628_AGPIO_CFG_REG 0x3c -#define MT7628_EPHY_GPIO_AIO_EN GENMASK(20, 17) -#define MT7628_EPHY_P0_DIS BIT(16) - -#define MT7628_GPIO2_MODE_REG 0x64 - /* Ethernet frame engine register */ #define PDMA_RELATED 0x0800 @@ -68,6 +57,11 @@ /* Ethernet switch register */ #define MT7628_SWITCH_FCT0 0x0008 #define MT7628_SWITCH_PFC1 0x0014 +#define MT7628_SWITCH_PVIDC0 0x0040 +#define MT7628_SWITCH_PVIDC1 0x0044 +#define MT7628_SWITCH_PVIDC2 0x0048 +#define MT7628_SWITCH_PVIDC3 0x004c +#define MT7628_SWITCH_VMSC0 0x0070 #define MT7628_SWITCH_FPA 0x0084 #define MT7628_SWITCH_SOCPC 0x008c #define MT7628_SWITCH_POC0 0x0090 @@ -122,6 +116,7 @@ struct fe_tx_dma { #define NUM_RX_DESC 256 #define NUM_TX_DESC 4 +#define NUM_PHYS 5 #define PADDING_LENGTH 60 @@ -131,13 +126,9 @@ struct fe_tx_dma { #define CONFIG_DMA_STOP_TIMEOUT 100 #define CONFIG_TX_DMA_TIMEOUT 100 -#define LINK_DELAY_TIME 500 /* 500 ms */ -#define LINK_TIMEOUT 10000 /* 10 seconds */ - struct mt7628_eth_dev { void __iomem *base; /* frame engine base address */ void __iomem *eth_sw_base; /* switch base address */ - struct regmap *sysctrl_regmap; /* system-controller reg-map */ struct mii_dev *bus; @@ -150,8 +141,16 @@ struct mt7628_eth_dev { int rx_dma_idx; /* Point to the next TXD in TXD Ring0 CPU wants to use */ int tx_dma_idx; + + struct reset_ctl rst_ephy; + + struct phy_device *phy; + + int wan_port; }; +static int mt7628_eth_free_pkt(struct udevice *dev, uchar *packet, int length); + static int mdio_wait_read(struct mt7628_eth_dev *priv, u32 mask, bool mask_set) { void __iomem *base = priv->eth_sw_base; @@ -280,6 +279,9 @@ static void mt7628_ephy_init(struct mt7628_eth_dev *priv) static void rt305x_esw_init(struct mt7628_eth_dev *priv) { void __iomem *base = priv->eth_sw_base; + void __iomem *reg; + u32 val = 0, pvid; + int i; /* * FC_RLS_TH=200, FC_SET_TH=160 @@ -301,20 +303,28 @@ static void rt305x_esw_init(struct mt7628_eth_dev *priv) /* 1us cycle number=125 (FE's clock=125Mhz) */ writel(0x7d000000, base + MT7628_SWITCH_BMU_CTRL); - /* Configure analog GPIO setup */ - regmap_update_bits(priv->sysctrl_regmap, MT7628_AGPIO_CFG_REG, - MT7628_EPHY_P0_DIS, MT7628_EPHY_GPIO_AIO_EN); + /* LAN/WAN partition, WAN port will be unusable in u-boot network */ + if (priv->wan_port >= 0 && priv->wan_port < 6) { + for (i = 0; i < 8; i++) { + pvid = i == priv->wan_port ? 2 : 1; + reg = base + MT7628_SWITCH_PVIDC0 + (i / 2) * 4; + if (i % 2 == 0) { + val = pvid; + } else { + val |= (pvid << 12); + writel(val, reg); + } + } - /* Reset PHY */ - regmap_update_bits(priv->sysctrl_regmap, MT7628_RSTCTRL_REG, - 0, RSTCTRL_EPHY_RST); - regmap_update_bits(priv->sysctrl_regmap, MT7628_RSTCTRL_REG, - RSTCTRL_EPHY_RST, 0); - mdelay(10); + val = 0xffff407f; + val |= 1 << (8 + priv->wan_port); + val &= ~(1 << priv->wan_port); + writel(val, base + MT7628_SWITCH_VMSC0); + } - /* Set P0 EPHY LED mode */ - regmap_update_bits(priv->sysctrl_regmap, MT7628_GPIO2_MODE_REG, - 0x0ffc0ffc, 0x05540554); + /* Reset PHY */ + reset_assert(&priv->rst_ephy); + reset_deassert(&priv->rst_ephy); mdelay(10); mt7628_ephy_init(priv); @@ -424,6 +434,7 @@ static int mt7628_eth_recv(struct udevice *dev, int flags, uchar **packetp) length = FIELD_GET(RX_DMA_PLEN0, priv->rx_ring[idx].rxd2); if (length == 0 || length > MTK_QDMA_PAGE_SIZE) { printf("%s: invalid length (%d bytes)\n", __func__, length); + mt7628_eth_free_pkt(dev, NULL, 0); return -EIO; } @@ -458,20 +469,13 @@ static int mt7628_eth_free_pkt(struct udevice *dev, uchar *packet, int length) return 0; } -static int phy_link_up(struct mt7628_eth_dev *priv) -{ - u32 val; - - mii_mgr_read(priv, 0x00, MII_BMSR, &val); - return !!(val & BMSR_LSTATUS); -} - static int mt7628_eth_start(struct udevice *dev) { struct mt7628_eth_dev *priv = dev_get_priv(dev); void __iomem *base = priv->base; uchar packet[MTK_QDMA_PAGE_SIZE]; uchar *packetp; + int ret; int i; for (i = 0; i < NUM_RX_DESC; i++) { @@ -514,25 +518,13 @@ static int mt7628_eth_start(struct udevice *dev) wmb(); eth_dma_start(priv); - /* Check if link is not up yet */ - if (!phy_link_up(priv)) { - /* Wait for link to come up */ - - printf("Waiting for link to come up ."); - for (i = 0; i < (LINK_TIMEOUT / LINK_DELAY_TIME); i++) { - mdelay(LINK_DELAY_TIME); - if (phy_link_up(priv)) { - mdelay(100); /* Ensure all is ready */ - break; - } - - printf("."); - } + if (priv->phy) { + ret = phy_startup(priv->phy); + if (ret) + return ret; - if (phy_link_up(priv)) - printf(" done\n"); - else - printf(" timeout! Trying anyways\n"); + if (!priv->phy->link) + return -EAGAIN; } /* @@ -558,8 +550,8 @@ static void mt7628_eth_stop(struct udevice *dev) static int mt7628_eth_probe(struct udevice *dev) { struct mt7628_eth_dev *priv = dev_get_priv(dev); - struct udevice *syscon; struct mii_dev *bus; + int poll_link_phy; int ret; int i; @@ -573,19 +565,15 @@ static int mt7628_eth_probe(struct udevice *dev) if (IS_ERR(priv->eth_sw_base)) return PTR_ERR(priv->eth_sw_base); - /* Get system controller regmap */ - ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, - "syscon", &syscon); + /* Reset controller */ + ret = reset_get_by_name(dev, "ephy", &priv->rst_ephy); if (ret) { - pr_err("unable to find syscon device\n"); + pr_err("unable to find reset controller for ethernet PHYs\n"); return ret; } - priv->sysctrl_regmap = syscon_get_regmap(syscon); - if (!priv->sysctrl_regmap) { - pr_err("unable to find regmap\n"); - return -ENODEV; - } + /* WAN port will be isolated from LAN ports */ + priv->wan_port = dev_read_u32_default(dev, "mediatek,wan-port", -1); /* Put rx and tx rings into KSEG1 area (uncached) */ priv->tx_ring = (struct fe_tx_dma *) @@ -613,6 +601,25 @@ static int mt7628_eth_probe(struct udevice *dev) if (ret) return ret; + poll_link_phy = dev_read_u32_default(dev, "mediatek,poll-link-phy", -1); + if (poll_link_phy >= 0) { + if (poll_link_phy >= NUM_PHYS) { + pr_err("invalid phy %d for poll-link-phy\n", + poll_link_phy); + return ret; + } + + priv->phy = phy_connect(bus, poll_link_phy, dev, + PHY_INTERFACE_MODE_MII); + if (!priv->phy) { + pr_err("failed to probe phy %d\n", poll_link_phy); + return -ENODEV; + } + + priv->phy->advertising = priv->phy->supported; + phy_config(priv->phy); + } + /* Switch configuration */ rt305x_esw_init(priv); diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index e317373..a72f34f 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -200,6 +200,7 @@ config KEYSTONE_USB_PHY config MT76X8_USB_PHY bool "MediaTek MT76x8 (7628/88) USB PHY support" depends on PHY + depends on SOC_MT7628 help Support the USB PHY in MT76x8 SoCs diff --git a/drivers/phy/keystone-usb-phy.c b/drivers/phy/keystone-usb-phy.c index e8146ca..14ac6bb 100644 --- a/drivers/phy/keystone-usb-phy.c +++ b/drivers/phy/keystone-usb-phy.c @@ -9,6 +9,7 @@ #include <dm/device.h> #include <generic-phy.h> #include <asm/io.h> +#include <asm/arch/psc_defs.h> /* USB PHY control register offsets */ #define USB_PHY_CTL_UTMI 0x0000 @@ -22,15 +23,25 @@ #define PHY_REF_SSP_EN BIT(29) struct keystone_usb_phy { + u32 psc_domain; void __iomem *reg; }; static int keystone_usb_init(struct phy *phy) { u32 val; + int rc; struct udevice *dev = phy->dev; struct keystone_usb_phy *keystone = dev_get_priv(dev); + /* Release USB from reset */ + rc = psc_enable_module(keystone->psc_domain); + if (rc) { + debug("Cannot enable USB module"); + return -rc; + } + mdelay(10); + /* * VBUSVLDEXTSEL has a default value of 1 in BootCfg but shouldn't. * It should always be cleared because our USB PHY has an onchip VBUS @@ -72,13 +83,24 @@ static int keystone_usb_power_off(struct phy *phy) static int keystone_usb_exit(struct phy *phy) { + struct udevice *dev = phy->dev; + struct keystone_usb_phy *keystone = dev_get_priv(dev); + + if (psc_disable_module(keystone->psc_domain)) + debug("failed to disable USB module!\n"); + return 0; } static int keystone_usb_phy_probe(struct udevice *dev) { + int rc; struct keystone_usb_phy *keystone = dev_get_priv(dev); + rc = dev_read_u32(dev, "psc-domain", &keystone->psc_domain); + if (rc) + return rc; + keystone->reg = dev_remap_addr_index(dev, 0); if (!keystone->reg) { pr_err("unable to remap usb phy\n"); diff --git a/drivers/phy/mt76x8-usb-phy.c b/drivers/phy/mt76x8-usb-phy.c index 268da8e..1e7c5f3 100644 --- a/drivers/phy/mt76x8-usb-phy.c +++ b/drivers/phy/mt76x8-usb-phy.c @@ -6,93 +6,185 @@ * Copyright (C) 2017 John Crispin <john@phrozen.org> */ +#include <clk.h> #include <common.h> #include <dm.h> #include <generic-phy.h> -#include <regmap.h> -#include <reset-uclass.h> -#include <syscon.h> +#include <reset.h> #include <asm/io.h> - -#define RT_SYSC_REG_SYSCFG1 0x014 -#define RT_SYSC_REG_CLKCFG1 0x030 -#define RT_SYSC_REG_USB_PHY_CFG 0x05c +#include <linux/bitops.h> #define OFS_U2_PHY_AC0 0x800 +#define USBPLL_FBDIV_S 16 +#define USBPLL_FBDIV_M GENMASK(22, 16) +#define BG_TRIM_S 8 +#define BG_TRIM_M GENMASK(11, 8) +#define BG_RBSEL_S 6 +#define BG_RBSEL_M GENMASK(7, 6) +#define BG_RASEL_S 4 +#define BG_RASEL_M GENMASK(5, 4) +#define BGR_DIV_S 2 +#define BGR_DIV_M GENMASK(3, 2) +#define CHP_EN BIT(1) + #define OFS_U2_PHY_AC1 0x804 +#define VRT_VREF_SEL_S 28 +#define VRT_VREF_SEL_M GENMASK(30, 28) +#define TERM_VREF_SEL_S 24 +#define TERM_VREF_SEL_M GENMASK(26, 24) +#define USBPLL_RSVD BIT(4) +#define USBPLL_ACCEN BIT(3) +#define USBPLL_LF BIT(2) + #define OFS_U2_PHY_AC2 0x808 + #define OFS_U2_PHY_ACR0 0x810 -#define OFS_U2_PHY_ACR1 0x814 -#define OFS_U2_PHY_ACR2 0x818 +#define HSTX_SRCAL_EN BIT(23) +#define HSTX_SRCTRL_S 16 +#define HSTX_SRCTRL_M GENMASK(18, 16) + #define OFS_U2_PHY_ACR3 0x81C -#define OFS_U2_PHY_ACR4 0x820 -#define OFS_U2_PHY_AMON0 0x824 +#define HSTX_DBIST_S 28 +#define HSTX_DBIST_M GENMASK(31, 28) +#define HSRX_BIAS_EN_SEL_S 20 +#define HSRX_BIAS_EN_SEL_M GENMASK(21, 20) + #define OFS_U2_PHY_DCR0 0x860 -#define OFS_U2_PHY_DCR1 0x864 +#define PHYD_RESERVE_S 8 +#define PHYD_RESERVE_M GENMASK(23, 8) +#define CDR_FILT_S 0 +#define CDR_FILT_M GENMASK(3, 0) + #define OFS_U2_PHY_DTM0 0x868 -#define OFS_U2_PHY_DTM1 0x86C +#define FORCE_USB_CLKEN BIT(25) + +#define OFS_FM_CR0 0xf00 +#define FREQDET_EN BIT(24) +#define CYCLECNT_S 0 +#define CYCLECNT_M GENMASK(23, 0) -#define RT_RSTCTRL_UDEV BIT(25) -#define RT_RSTCTRL_UHST BIT(22) -#define RT_SYSCFG1_USB0_HOST_MODE BIT(10) +#define OFS_FM_MONR0 0xf0c -#define MT7620_CLKCFG1_UPHY0_CLK_EN BIT(25) -#define MT7620_CLKCFG1_UPHY1_CLK_EN BIT(22) -#define RT_CLKCFG1_UPHY1_CLK_EN BIT(20) -#define RT_CLKCFG1_UPHY0_CLK_EN BIT(18) +#define OFS_FM_MONR1 0xf10 +#define FRCK_EN BIT(8) -#define USB_PHY_UTMI_8B60M BIT(1) -#define UDEV_WAKEUP BIT(0) +#define U2_SR_COEF_7628 32 struct mt76x8_usb_phy { - u32 clk; void __iomem *base; - struct regmap *sysctl; + struct clk cg; /* for clock gating */ + struct reset_ctl rst_phy; }; -static void u2_phy_w32(struct mt76x8_usb_phy *phy, u32 val, u32 reg) +static void phy_w32(struct mt76x8_usb_phy *phy, u32 reg, u32 val) { writel(val, phy->base + reg); } -static u32 u2_phy_r32(struct mt76x8_usb_phy *phy, u32 reg) +static u32 phy_r32(struct mt76x8_usb_phy *phy, u32 reg) { return readl(phy->base + reg); } +static void phy_rmw32(struct mt76x8_usb_phy *phy, u32 reg, u32 clr, u32 set) +{ + clrsetbits_32(phy->base + reg, clr, set); +} + static void mt76x8_usb_phy_init(struct mt76x8_usb_phy *phy) { - u2_phy_r32(phy, OFS_U2_PHY_AC2); - u2_phy_r32(phy, OFS_U2_PHY_ACR0); - u2_phy_r32(phy, OFS_U2_PHY_DCR0); - - u2_phy_w32(phy, 0x00ffff02, OFS_U2_PHY_DCR0); - u2_phy_r32(phy, OFS_U2_PHY_DCR0); - u2_phy_w32(phy, 0x00555502, OFS_U2_PHY_DCR0); - u2_phy_r32(phy, OFS_U2_PHY_DCR0); - u2_phy_w32(phy, 0x00aaaa02, OFS_U2_PHY_DCR0); - u2_phy_r32(phy, OFS_U2_PHY_DCR0); - u2_phy_w32(phy, 0x00000402, OFS_U2_PHY_DCR0); - u2_phy_r32(phy, OFS_U2_PHY_DCR0); - u2_phy_w32(phy, 0x0048086a, OFS_U2_PHY_AC0); - u2_phy_w32(phy, 0x4400001c, OFS_U2_PHY_AC1); - u2_phy_w32(phy, 0xc0200000, OFS_U2_PHY_ACR3); - u2_phy_w32(phy, 0x02000000, OFS_U2_PHY_DTM0); + phy_r32(phy, OFS_U2_PHY_AC2); + phy_r32(phy, OFS_U2_PHY_ACR0); + phy_r32(phy, OFS_U2_PHY_DCR0); + + phy_w32(phy, OFS_U2_PHY_DCR0, + (0xffff << PHYD_RESERVE_S) | (2 << CDR_FILT_S)); + phy_r32(phy, OFS_U2_PHY_DCR0); + + phy_w32(phy, OFS_U2_PHY_DCR0, + (0x5555 << PHYD_RESERVE_S) | (2 << CDR_FILT_S)); + phy_r32(phy, OFS_U2_PHY_DCR0); + + phy_w32(phy, OFS_U2_PHY_DCR0, + (0xaaaa << PHYD_RESERVE_S) | (2 << CDR_FILT_S)); + phy_r32(phy, OFS_U2_PHY_DCR0); + + phy_w32(phy, OFS_U2_PHY_DCR0, + (4 << PHYD_RESERVE_S) | (2 << CDR_FILT_S)); + phy_r32(phy, OFS_U2_PHY_DCR0); + + phy_w32(phy, OFS_U2_PHY_AC0, + (0x48 << USBPLL_FBDIV_S) | (8 << BG_TRIM_S) | + (1 << BG_RBSEL_S) | (2 << BG_RASEL_S) | (2 << BGR_DIV_S) | + CHP_EN); + + phy_w32(phy, OFS_U2_PHY_AC1, + (4 << VRT_VREF_SEL_S) | (4 << TERM_VREF_SEL_S) | USBPLL_RSVD | + USBPLL_ACCEN | USBPLL_LF); + + phy_w32(phy, OFS_U2_PHY_ACR3, + (12 << HSTX_DBIST_S) | (2 << HSRX_BIAS_EN_SEL_S)); + + phy_w32(phy, OFS_U2_PHY_DTM0, FORCE_USB_CLKEN); +} + +static void mt76x8_usb_phy_sr_calibrate(struct mt76x8_usb_phy *phy) +{ + u32 fmout, tmp = 4; + int i; + + /* Enable HS TX SR calibration */ + phy_rmw32(phy, OFS_U2_PHY_ACR0, 0, HSTX_SRCAL_EN); + mdelay(1); + + /* Enable free run clock */ + phy_rmw32(phy, OFS_FM_MONR1, 0, FRCK_EN); + + /* Set cycle count = 0x400 */ + phy_rmw32(phy, OFS_FM_CR0, CYCLECNT_M, 0x400 << CYCLECNT_S); + + /* Enable frequency meter */ + phy_rmw32(phy, OFS_FM_CR0, 0, FREQDET_EN); + + /* Wait for FM detection done, set timeout to 10ms */ + for (i = 0; i < 10; i++) { + fmout = phy_r32(phy, OFS_FM_MONR0); + + if (fmout) + break; + + mdelay(1); + } + + /* Disable frequency meter */ + phy_rmw32(phy, OFS_FM_CR0, FREQDET_EN, 0); + + /* Disable free run clock */ + phy_rmw32(phy, OFS_FM_MONR1, FRCK_EN, 0); + + /* Disable HS TX SR calibration */ + phy_rmw32(phy, OFS_U2_PHY_ACR0, HSTX_SRCAL_EN, 0); + mdelay(1); + + if (fmout) { + /* + * set reg = (1024 / FM_OUT) * 25 * 0.028 + * (round to the nearest digits) + */ + tmp = (((1024 * 25 * U2_SR_COEF_7628) / fmout) + 500) / 1000; + } + + phy_rmw32(phy, OFS_U2_PHY_ACR0, HSTX_SRCTRL_M, + (tmp << HSTX_SRCTRL_S) & HSTX_SRCTRL_M); } static int mt76x8_usb_phy_power_on(struct phy *_phy) { struct mt76x8_usb_phy *phy = dev_get_priv(_phy->dev); - u32 t; - /* enable the phy */ - regmap_update_bits(phy->sysctl, RT_SYSC_REG_CLKCFG1, - phy->clk, phy->clk); + clk_enable(&phy->cg); - /* setup host mode */ - regmap_update_bits(phy->sysctl, RT_SYSC_REG_SYSCFG1, - RT_SYSCFG1_USB0_HOST_MODE, - RT_SYSCFG1_USB0_HOST_MODE); + reset_deassert(&phy->rst_phy); /* * The SDK kernel had a delay of 100ms. however on device @@ -100,17 +192,8 @@ static int mt76x8_usb_phy_power_on(struct phy *_phy) */ mdelay(10); - if (phy->base) - mt76x8_usb_phy_init(phy); - - /* print some status info */ - regmap_read(phy->sysctl, RT_SYSC_REG_USB_PHY_CFG, &t); - printf("remote usb device wakeup %s\n", - (t & UDEV_WAKEUP) ? "enabled" : "disabled"); - if (t & USB_PHY_UTMI_8B60M) - printf("UTMI 8bit 60MHz\n"); - else - printf("UTMI 16bit 30MHz\n"); + mt76x8_usb_phy_init(phy); + mt76x8_usb_phy_sr_calibrate(phy); return 0; } @@ -119,9 +202,9 @@ static int mt76x8_usb_phy_power_off(struct phy *_phy) { struct mt76x8_usb_phy *phy = dev_get_priv(_phy->dev); - /* disable the phy */ - regmap_update_bits(phy->sysctl, RT_SYSC_REG_CLKCFG1, - phy->clk, 0); + clk_disable(&phy->cg); + + reset_assert(&phy->rst_phy); return 0; } @@ -129,15 +212,21 @@ static int mt76x8_usb_phy_power_off(struct phy *_phy) static int mt76x8_usb_phy_probe(struct udevice *dev) { struct mt76x8_usb_phy *phy = dev_get_priv(dev); - - phy->sysctl = syscon_regmap_lookup_by_phandle(dev, "ralink,sysctl"); - if (IS_ERR(phy->sysctl)) - return PTR_ERR(phy->sysctl); + int ret; phy->base = dev_read_addr_ptr(dev); if (!phy->base) return -EINVAL; + /* clock gate */ + ret = clk_get_by_name(dev, "cg", &phy->cg); + if (ret) + return ret; + + ret = reset_get_by_name(dev, "phy", &phy->rst_phy); + if (ret) + return ret; + return 0; } diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index deee924..eadcfd6 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -269,6 +269,7 @@ source "drivers/pinctrl/exynos/Kconfig" source "drivers/pinctrl/mediatek/Kconfig" source "drivers/pinctrl/meson/Kconfig" source "drivers/pinctrl/mscc/Kconfig" +source "drivers/pinctrl/mtmips/Kconfig" source "drivers/pinctrl/mvebu/Kconfig" source "drivers/pinctrl/nxp/Kconfig" source "drivers/pinctrl/renesas/Kconfig" diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index 4b080b7..ce0879a 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -9,6 +9,7 @@ obj-y += nxp/ obj-$(CONFIG_$(SPL_)PINCTRL_ROCKCHIP) += rockchip/ obj-$(CONFIG_ARCH_ASPEED) += aspeed/ obj-$(CONFIG_ARCH_ATH79) += ath79/ +obj-$(CONFIG_ARCH_MTMIPS) += mtmips/ obj-$(CONFIG_ARCH_RMOBILE) += renesas/ obj-$(CONFIG_PINCTRL_SANDBOX) += pinctrl-sandbox.o diff --git a/drivers/pinctrl/mtmips/Kconfig b/drivers/pinctrl/mtmips/Kconfig new file mode 100644 index 0000000..8482a38 --- /dev/null +++ b/drivers/pinctrl/mtmips/Kconfig @@ -0,0 +1,13 @@ + +config PINCTRL_MTMIPS + depends on ARCH_MTMIPS + bool + +config PINCTRL_MT7628 + bool "MediaTek MT7628 pin control driver" + select PINCTRL_MTMIPS + depends on SOC_MT7628 && PINCTRL_GENERIC + help + Support pin multiplexing control on MediaTek MT7628. + The driver is controlled by a device tree node which contains + the pin mux functions for each available pin groups. diff --git a/drivers/pinctrl/mtmips/Makefile b/drivers/pinctrl/mtmips/Makefile new file mode 100644 index 0000000..3ba5c0c --- /dev/null +++ b/drivers/pinctrl/mtmips/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0 + +# Core +obj-$(CONFIG_PINCTRL_MTMIPS) += pinctrl-mtmips-common.o + +# SoC Drivers +obj-$(CONFIG_PINCTRL_MT7628) += pinctrl-mt7628.o diff --git a/drivers/pinctrl/mtmips/pinctrl-mt7628.c b/drivers/pinctrl/mtmips/pinctrl-mt7628.c new file mode 100644 index 0000000..fc9d8b5 --- /dev/null +++ b/drivers/pinctrl/mtmips/pinctrl-mt7628.c @@ -0,0 +1,585 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 MediaTek Inc. All Rights Reserved. + * + * Author: Weijie Gao <weijie.gao@mediatek.com> + */ + +#include <common.h> +#include <dm.h> +#include <dm/pinctrl.h> +#include <linux/bitops.h> +#include <linux/io.h> + +#include "pinctrl-mtmips-common.h" + +DECLARE_GLOBAL_DATA_PTR; + +#define AGPIO_OFS 0 +#define GPIOMODE1_OFS 0x24 +#define GPIOMODE2_OFS 0x28 + +#define EPHY4_1_PAD_SHIFT 17 +#define EPHY4_1_PAD_MASK 0x0f +#define EPHY0_SHIFT 16 +#define RF_OLT_MODE_SHIFT 12 +#define N9_EINT_SRC_SHIFT 9 +#define WLED_OD_SHIFT 8 +#define REF_CLKO_PAD_SHIFT 4 +#define I2S_CLK_PAD_SHIFT 3 +#define I2S_WS_PAD_SHIFT 2 +#define I2S_SDO_PAD_SHIFT 1 +#define I2S_SDI_PAD_SHIFT 0 + +#define GM4_MASK 3 + +#define P4LED_K_SHIFT 26 +#define P3LED_K_SHIFT 24 +#define P2LED_K_SHIFT 22 +#define P1LED_K_SHIFT 20 +#define P0LED_K_SHIFT 18 +#define WLED_K_SHIFT 16 +#define P4LED_A_SHIFT 10 +#define P3LED_A_SHIFT 8 +#define P2LED_A_SHIFT 6 +#define P1LED_A_SHIFT 4 +#define P0LED_A_SHIFT 2 +#define WLED_A_SHIFT 0 + +#define PWM1_SHIFT 30 +#define PWM0_SHIFT 28 +#define UART2_SHIFT 26 +#define UART1_SHIFT 24 +#define I2C_SHIFT 20 +#define REFCLK_SHIFT 18 +#define PERST_SHIFT 16 +#define ESD_SHIFT 15 +#define WDT_SHIFT 14 +#define SPI_SHIFT 12 +#define SDMODE_SHIFT 10 +#define UART0_SHIFT 8 +#define I2S_SHIFT 6 +#define SPI_CS1_SHIFT 4 +#define SPIS_SHIFT 2 +#define GPIO0_SHIFT 0 + +#define PAD_PU_G0_REG 0x00 +#define PAD_PU_G1_REG 0x04 +#define PAD_PD_G0_REG 0x10 +#define PAD_PD_G1_REG 0x14 +#define PAD_SR_G0_REG 0x20 +#define PAD_SR_G1_REG 0x24 +#define PAD_SMT_G0_REG 0x30 +#define PAD_SMT_G1_REG 0x34 +#define PAD_E2_G0_REG 0x40 +#define PAD_E2_G1_REG 0x44 +#define PAD_E4_G0_REG 0x50 +#define PAD_E4_G1_REG 0x54 +#define PAD_E8_G0_REG 0x60 +#define PAD_E8_G1_REG 0x64 + +#define PIN_CONFIG_DRIVE_STRENGTH_28 (PIN_CONFIG_END + 1) +#define PIN_CONFIG_DRIVE_STRENGTH_4G (PIN_CONFIG_END + 2) + +struct mt7628_pinctrl_priv { + struct mtmips_pinctrl_priv mp; + + void __iomem *pcbase; +}; + +#if CONFIG_IS_ENABLED(PINMUX) +static const struct mtmips_pmx_func ephy4_1_pad_grp[] = { + FUNC("digital", 0xf), + FUNC("analog", 0), +}; + +static const struct mtmips_pmx_func ephy0_grp[] = { + FUNC("disable", 1), + FUNC("enable", 0), +}; + +static const struct mtmips_pmx_func rf_olt_grp[] = { + FUNC("enable", 1), + FUNC("disable", 0), +}; + +static const struct mtmips_pmx_func n9_eint_src_grp[] = { + FUNC("gpio", 1), + FUNC("utif", 0), +}; + +static const struct mtmips_pmx_func wlen_od_grp[] = { + FUNC("enable", 1), + FUNC("disable", 0), +}; + +static const struct mtmips_pmx_func ref_clko_grp[] = { + FUNC("digital", 1), + FUNC("analog", 0), +}; + +static const struct mtmips_pmx_func i2s_clk_grp[] = { + FUNC("digital", 1), + FUNC("analog", 0), +}; + +static const struct mtmips_pmx_func i2s_ws_grp[] = { + FUNC("digital", 1), + FUNC("analog", 0), +}; + +static const struct mtmips_pmx_func i2s_sdo_grp[] = { + FUNC("digital", 1), + FUNC("analog", 0), +}; + +static const struct mtmips_pmx_func i2s_sdi_grp[] = { + FUNC("digital", 1), + FUNC("analog", 0), +}; + +static const struct mtmips_pmx_func pwm1_grp[] = { + FUNC("sdxc d6", 3), + FUNC("utif", 2), + FUNC("gpio", 1), + FUNC("pwm1", 0), +}; + +static const struct mtmips_pmx_func pwm0_grp[] = { + FUNC("sdxc d7", 3), + FUNC("utif", 2), + FUNC("gpio", 1), + FUNC("pwm0", 0), +}; + +static const struct mtmips_pmx_func uart2_grp[] = { + FUNC("sdxc d5 d4", 3), + FUNC("pwm", 2), + FUNC("gpio", 1), + FUNC("uart2", 0), +}; + +static const struct mtmips_pmx_func uart1_grp[] = { + FUNC("sw_r", 3), + FUNC("pwm", 2), + FUNC("gpio", 1), + FUNC("uart1", 0), +}; + +static const struct mtmips_pmx_func i2c_grp[] = { + FUNC("-", 3), + FUNC("debug", 2), + FUNC("gpio", 1), + FUNC("i2c", 0), +}; + +static const struct mtmips_pmx_func refclk_grp[] = { + FUNC("gpio", 1), + FUNC("refclk", 0), +}; + +static const struct mtmips_pmx_func perst_grp[] = { + FUNC("gpio", 1), + FUNC("perst", 0), +}; + +static const struct mtmips_pmx_func esd_grp[] = { + FUNC("router", 1), + FUNC("iot", 0), +}; + +static const struct mtmips_pmx_func wdt_grp[] = { + FUNC("gpio", 1), + FUNC("wdt", 0), +}; + +static const struct mtmips_pmx_func spi_grp[] = { + FUNC("gpio", 1), + FUNC("spi", 0), +}; + +static const struct mtmips_pmx_func sd_mode_grp[] = { + FUNC("n9 jtag", 3), + FUNC("utif1", 2), + FUNC("gpio", 1), + FUNC("sdxc", 0), +}; + +static const struct mtmips_pmx_func uart0_grp[] = { + FUNC("-", 3), + FUNC("-", 2), + FUNC("gpio", 1), + FUNC("uart0", 0), +}; + +static const struct mtmips_pmx_func i2s_grp[] = { + FUNC("antenna", 3), + FUNC("pcm", 2), + FUNC("gpio", 1), + FUNC("i2s", 0), +}; + +static const struct mtmips_pmx_func spi_cs1_grp[] = { + FUNC("-", 3), + FUNC("refclk", 2), + FUNC("gpio", 1), + FUNC("spi cs1", 0), +}; + +static const struct mtmips_pmx_func spis_grp[] = { + FUNC("pwm_uart2", 3), + FUNC("utif", 2), + FUNC("gpio", 1), + FUNC("spis", 0), +}; + +static const struct mtmips_pmx_func gpio0_grp[] = { + FUNC("perst", 3), + FUNC("refclk", 2), + FUNC("gpio", 1), + FUNC("gpio0", 0), +}; + +static const struct mtmips_pmx_func wled_a_grp[] = { + FUNC("-", 3), + FUNC("-", 2), + FUNC("gpio", 1), + FUNC("led", 0), +}; + +static const struct mtmips_pmx_func p0led_a_grp[] = { + FUNC("jtag", 3), + FUNC("rsvd", 2), + FUNC("gpio", 1), + FUNC("led", 0), +}; + +static const struct mtmips_pmx_func p1led_a_grp[] = { + FUNC("jtag", 3), + FUNC("utif", 2), + FUNC("gpio", 1), + FUNC("led", 0), +}; + +static const struct mtmips_pmx_func p2led_a_grp[] = { + FUNC("jtag", 3), + FUNC("utif", 2), + FUNC("gpio", 1), + FUNC("led", 0), +}; + +static const struct mtmips_pmx_func p3led_a_grp[] = { + FUNC("jtag", 3), + FUNC("utif", 2), + FUNC("gpio", 1), + FUNC("led", 0), +}; + +static const struct mtmips_pmx_func p4led_a_grp[] = { + FUNC("jtag", 3), + FUNC("utif", 2), + FUNC("gpio", 1), + FUNC("led", 0), +}; + +static const struct mtmips_pmx_func wled_k_grp[] = { + FUNC("-", 3), + FUNC("-", 2), + FUNC("gpio", 1), + FUNC("led", 0), +}; + +static const struct mtmips_pmx_func p0led_k_grp[] = { + FUNC("jtag", 3), + FUNC("rsvd", 2), + FUNC("gpio", 1), + FUNC("led", 0), +}; + +static const struct mtmips_pmx_func p1led_k_grp[] = { + FUNC("jtag", 3), + FUNC("utif", 2), + FUNC("gpio", 1), + FUNC("led", 0), +}; + +static const struct mtmips_pmx_func p2led_k_grp[] = { + FUNC("jtag", 3), + FUNC("utif", 2), + FUNC("gpio", 1), + FUNC("led", 0), +}; + +static const struct mtmips_pmx_func p3led_k_grp[] = { + FUNC("jtag", 3), + FUNC("utif", 2), + FUNC("gpio", 1), + FUNC("led", 0), +}; + +static const struct mtmips_pmx_func p4led_k_grp[] = { + FUNC("jtag", 3), + FUNC("utif", 2), + FUNC("gpio", 1), + FUNC("led", 0), +}; + +static const struct mtmips_pmx_group mt7628_pinmux_data[] = { + GRP("ephy4_1_pad", ephy4_1_pad_grp, AGPIO_OFS, EPHY4_1_PAD_SHIFT, + EPHY4_1_PAD_MASK), + GRP("ephy0", ephy0_grp, AGPIO_OFS, EPHY0_SHIFT, 1), + GRP("rf_olt", rf_olt_grp, AGPIO_OFS, RF_OLT_MODE_SHIFT, 1), + GRP("n9_eint_src", n9_eint_src_grp, AGPIO_OFS, N9_EINT_SRC_SHIFT, 1), + GRP("wlen_od", wlen_od_grp, AGPIO_OFS, WLED_OD_SHIFT, 1), + GRP("ref_clko_pad", ref_clko_grp, AGPIO_OFS, REF_CLKO_PAD_SHIFT, 1), + GRP("i2s_clk_pad", i2s_clk_grp, AGPIO_OFS, I2S_CLK_PAD_SHIFT, 1), + GRP("i2s_ws_pad", i2s_ws_grp, AGPIO_OFS, I2S_WS_PAD_SHIFT, 1), + GRP("i2s_sdo_pad", i2s_sdo_grp, AGPIO_OFS, I2S_SDO_PAD_SHIFT, 1), + GRP("i2s_sdi_pad", i2s_sdi_grp, AGPIO_OFS, I2S_SDI_PAD_SHIFT, 1), + GRP("pwm1", pwm1_grp, GPIOMODE1_OFS, PWM1_SHIFT, GM4_MASK), + GRP("pwm0", pwm0_grp, GPIOMODE1_OFS, PWM0_SHIFT, GM4_MASK), + GRP("uart2", uart2_grp, GPIOMODE1_OFS, UART2_SHIFT, GM4_MASK), + GRP("uart1", uart1_grp, GPIOMODE1_OFS, UART1_SHIFT, GM4_MASK), + GRP("i2c", i2c_grp, GPIOMODE1_OFS, I2C_SHIFT, GM4_MASK), + GRP("refclk", refclk_grp, GPIOMODE1_OFS, REFCLK_SHIFT, 1), + GRP("perst", perst_grp, GPIOMODE1_OFS, PERST_SHIFT, 1), + GRP("sd router", esd_grp, GPIOMODE1_OFS, ESD_SHIFT, 1), + GRP("wdt", wdt_grp, GPIOMODE1_OFS, WDT_SHIFT, 1), + GRP("spi", spi_grp, GPIOMODE1_OFS, SPI_SHIFT, 1), + GRP("sdmode", sd_mode_grp, GPIOMODE1_OFS, SDMODE_SHIFT, GM4_MASK), + GRP("uart0", uart0_grp, GPIOMODE1_OFS, UART0_SHIFT, GM4_MASK), + GRP("i2s", i2s_grp, GPIOMODE1_OFS, I2S_SHIFT, GM4_MASK), + GRP("spi cs1", spi_cs1_grp, GPIOMODE1_OFS, SPI_CS1_SHIFT, GM4_MASK), + GRP("spis", spis_grp, GPIOMODE1_OFS, SPIS_SHIFT, GM4_MASK), + GRP("gpio0", gpio0_grp, GPIOMODE1_OFS, GPIO0_SHIFT, GM4_MASK), + GRP("wled_a", wled_a_grp, GPIOMODE2_OFS, WLED_A_SHIFT, GM4_MASK), + GRP("p0led_a", p0led_a_grp, GPIOMODE2_OFS, P0LED_A_SHIFT, GM4_MASK), + GRP("p1led_a", p1led_a_grp, GPIOMODE2_OFS, P1LED_A_SHIFT, GM4_MASK), + GRP("p2led_a", p2led_a_grp, GPIOMODE2_OFS, P2LED_A_SHIFT, GM4_MASK), + GRP("p3led_a", p3led_a_grp, GPIOMODE2_OFS, P3LED_A_SHIFT, GM4_MASK), + GRP("p4led_a", p4led_a_grp, GPIOMODE2_OFS, P4LED_A_SHIFT, GM4_MASK), + GRP("wled_k", wled_k_grp, GPIOMODE2_OFS, WLED_K_SHIFT, GM4_MASK), + GRP("p0led_k", p0led_k_grp, GPIOMODE2_OFS, P0LED_K_SHIFT, GM4_MASK), + GRP("p1led_k", p1led_k_grp, GPIOMODE2_OFS, P1LED_K_SHIFT, GM4_MASK), + GRP("p2led_k", p2led_k_grp, GPIOMODE2_OFS, P2LED_K_SHIFT, GM4_MASK), + GRP("p3led_k", p3led_k_grp, GPIOMODE2_OFS, P3LED_K_SHIFT, GM4_MASK), + GRP("p4led_k", p4led_k_grp, GPIOMODE2_OFS, P4LED_K_SHIFT, GM4_MASK), +}; + +static int mt7628_get_groups_count(struct udevice *dev) +{ + return ARRAY_SIZE(mt7628_pinmux_data); +} + +static const char *mt7628_get_group_name(struct udevice *dev, + unsigned int selector) +{ + return mt7628_pinmux_data[selector].name; +} +#endif /* CONFIG_IS_ENABLED(PINMUX) */ + +#if CONFIG_IS_ENABLED(PINCONF) +static const struct pinconf_param mt7628_conf_params[] = { + { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 }, + { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 }, + { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 }, + { "input-schmitt-enable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 1 }, + { "input-schmitt-disable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 0 }, + { "drive-strength-28", PIN_CONFIG_DRIVE_STRENGTH_28, 0 }, + { "drive-strength-4g", PIN_CONFIG_DRIVE_STRENGTH_4G, 0 }, + { "slew-rate", PIN_CONFIG_SLEW_RATE, 0 }, +}; + +static const char *const mt7628_pins[] = { + "i2s_sdi", + "i2s_sdo", + "i2s_ws", + "i2s_clk", + "i2s_sclk", + "i2c_sd", + "spi_cs1", + "spi_clk", + "spi_mosi", + "spi_miso", + "spi_cs0", + "gpio0", + "uart0_txd", + "uart0_rxd", + "spis_cs", + "spis_clk", + "spis_miso", + "spis_mosi", + "pwm_ch0", + "pwm_ch1", + "uart2_txd", + "uart2_rxd", + "sd_wp", + "sd_cd", + "sd_d1", + "sd_d0", + "sd_clk", + "sd_cmd", + "sd_d3", + "sd_d2", + "ephy_led4_k", + "ephy_led3_k", + "ephy_led2_k", + "ephy_led1_k", + "ephy_led0_k", + "wled_k", + "perst_n", + "co_clko", + "wdt", + "ephy_led4_a", + "ephy_led3_a", + "ephy_led2_a", + "ephy_led1_a", + "ephy_led0_a", + "wled_a", + "uart1_txd", + "uart1_rxd", +}; + +static const u32 mt7628_drv_strength_28_tbl[] = {2, 4, 6, 8}; +static const u32 mt7628_drv_strength_4g_tbl[] = {4, 8, 12, 16}; + +static int mt7628_set_drv_strength(void __iomem *base, u32 val, u32 bit, + const u32 tbl[], u32 reg_lo, u32 reg_hi) +{ + int i; + + for (i = 0; i < 4; i++) + if (tbl[i] == val) + break; + + if (i >= 4) + return -EINVAL; + + clrsetbits_32(base + reg_lo, BIT(bit), (i & 1) << bit); + clrsetbits_32(base + reg_hi, BIT(bit), ((i >> 1) & 1) << bit); + + return 0; +} + +static int mt7628_get_pins_count(struct udevice *dev) +{ + return ARRAY_SIZE(mt7628_pins); +} + +static const char *mt7628_get_pin_name(struct udevice *dev, + unsigned int selector) +{ + return mt7628_pins[selector]; +} + +static int mt7628_pinconf_set(struct udevice *dev, unsigned int pin_selector, + unsigned int param, unsigned int argument) +{ + struct mt7628_pinctrl_priv *priv = dev_get_priv(dev); + u32 offs, bit; + int ret = 0; + + offs = (pin_selector / 32) * 4; + bit = pin_selector % 32; + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + clrbits_32(priv->pcbase + offs + PAD_PU_G0_REG, BIT(bit)); + clrbits_32(priv->pcbase + offs + PAD_PD_G0_REG, BIT(bit)); + break; + case PIN_CONFIG_BIAS_PULL_UP: + setbits_32(priv->pcbase + offs + PAD_PU_G0_REG, BIT(bit)); + clrbits_32(priv->pcbase + offs + PAD_PD_G0_REG, BIT(bit)); + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + clrbits_32(priv->pcbase + offs + PAD_PU_G0_REG, BIT(bit)); + setbits_32(priv->pcbase + offs + PAD_PD_G0_REG, BIT(bit)); + break; + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: + clrsetbits_32(priv->pcbase + offs + PAD_SMT_G0_REG, + BIT(bit), (!!argument) << bit); + break; + case PIN_CONFIG_DRIVE_STRENGTH_28: + ret = mt7628_set_drv_strength(priv->pcbase + offs, argument, + bit, mt7628_drv_strength_28_tbl, + PAD_E2_G0_REG, PAD_E4_G0_REG); + break; + case PIN_CONFIG_DRIVE_STRENGTH_4G: + ret = mt7628_set_drv_strength(priv->pcbase + offs, argument, + bit, mt7628_drv_strength_4g_tbl, + PAD_E4_G0_REG, PAD_E8_G0_REG); + break; + case PIN_CONFIG_SLEW_RATE: + clrsetbits_32(priv->pcbase + offs + PAD_SR_G0_REG, + BIT(bit), (!!argument) << bit); + break; + default: + ret = -EINVAL; + } + + return ret; +} +#endif + +static int mt7628_pinctrl_probe(struct udevice *dev) +{ + struct mt7628_pinctrl_priv *priv = dev_get_priv(dev); + int ret = 0; + +#if CONFIG_IS_ENABLED(PINMUX) + ret = mtmips_pinctrl_probe(&priv->mp, ARRAY_SIZE(mt7628_pinmux_data), + mt7628_pinmux_data); +#endif /* CONFIG_IS_ENABLED(PINMUX) */ + + return ret; +} + +static int mt7628_pinctrl_ofdata_to_platdata(struct udevice *dev) +{ + struct mt7628_pinctrl_priv *priv = dev_get_priv(dev); + + priv->mp.base = (void __iomem *)dev_remap_addr_index(dev, 0); + + if (!priv->mp.base) + return -EINVAL; + + priv->pcbase = (void __iomem *)dev_remap_addr_index(dev, 1); + + if (!priv->pcbase) + return -EINVAL; + + return 0; +} + +static const struct pinctrl_ops mt7628_pinctrl_ops = { +#if CONFIG_IS_ENABLED(PINMUX) + .get_groups_count = mt7628_get_groups_count, + .get_group_name = mt7628_get_group_name, + .get_functions_count = mtmips_get_functions_count, + .get_function_name = mtmips_get_function_name, + .pinmux_group_set = mtmips_pinmux_group_set, +#endif /* CONFIG_IS_ENABLED(PINMUX) */ +#if CONFIG_IS_ENABLED(PINCONF) + .pinconf_num_params = ARRAY_SIZE(mt7628_conf_params), + .pinconf_params = mt7628_conf_params, + .get_pins_count = mt7628_get_pins_count, + .get_pin_name = mt7628_get_pin_name, + .pinconf_set = mt7628_pinconf_set, +#endif /* CONFIG_IS_ENABLED(PINCONF) */ + .set_state = pinctrl_generic_set_state, +}; + +static const struct udevice_id mt7628_pinctrl_ids[] = { + { .compatible = "mediatek,mt7628-pinctrl" }, + { } +}; + +U_BOOT_DRIVER(mt7628_pinctrl) = { + .name = "mt7628-pinctrl", + .id = UCLASS_PINCTRL, + .of_match = mt7628_pinctrl_ids, + .ofdata_to_platdata = mt7628_pinctrl_ofdata_to_platdata, + .ops = &mt7628_pinctrl_ops, + .probe = mt7628_pinctrl_probe, + .priv_auto_alloc_size = sizeof(struct mt7628_pinctrl_priv), +}; diff --git a/drivers/pinctrl/mtmips/pinctrl-mtmips-common.c b/drivers/pinctrl/mtmips/pinctrl-mtmips-common.c new file mode 100644 index 0000000..ee6a9d1 --- /dev/null +++ b/drivers/pinctrl/mtmips/pinctrl-mtmips-common.c @@ -0,0 +1,87 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 MediaTek Inc. All Rights Reserved. + * + * Author: Weijie Gao <weijie.gao@mediatek.com> + */ + +#include <common.h> +#include <dm.h> +#include <dm/pinctrl.h> +#include <linux/io.h> + +#include "pinctrl-mtmips-common.h" + +static void mtmips_pinctrl_reg_set(struct mtmips_pinctrl_priv *priv, + u32 reg, u32 shift, u32 mask, u32 value) +{ + u32 val; + + val = readl(priv->base + reg); + val &= ~(mask << shift); + val |= value << shift; + writel(val, priv->base + reg); +} + +int mtmips_get_functions_count(struct udevice *dev) +{ + struct mtmips_pinctrl_priv *priv = dev_get_priv(dev); + + return priv->nfuncs; +} + +const char *mtmips_get_function_name(struct udevice *dev, unsigned int selector) +{ + struct mtmips_pinctrl_priv *priv = dev_get_priv(dev); + + return priv->funcs[selector]->name; +} + +int mtmips_pinmux_group_set(struct udevice *dev, unsigned int group_selector, + unsigned int func_selector) +{ + struct mtmips_pinctrl_priv *priv = dev_get_priv(dev); + const struct mtmips_pmx_group *grp = &priv->groups[group_selector]; + const struct mtmips_pmx_func *func = priv->funcs[func_selector]; + int i; + + if (!grp->nfuncs) + return 0; + + for (i = 0; i < grp->nfuncs; i++) { + if (!strcmp(grp->funcs[i].name, func->name)) { + mtmips_pinctrl_reg_set(priv, grp->reg, grp->shift, + grp->mask, grp->funcs[i].value); + return 0; + } + } + + return -EINVAL; +} + +int mtmips_pinctrl_probe(struct mtmips_pinctrl_priv *priv, u32 ngroups, + const struct mtmips_pmx_group *groups) +{ + int i, j, n; + + priv->ngroups = ngroups; + priv->groups = groups; + + priv->nfuncs = 0; + + for (i = 0; i < ngroups; i++) + priv->nfuncs += groups[i].nfuncs; + + priv->funcs = malloc(priv->nfuncs * sizeof(*priv->funcs)); + if (!priv->funcs) + return -ENOMEM; + + n = 0; + + for (i = 0; i < ngroups; i++) { + for (j = 0; j < groups[i].nfuncs; j++) + priv->funcs[n++] = &groups[i].funcs[j]; + } + + return 0; +} diff --git a/drivers/pinctrl/mtmips/pinctrl-mtmips-common.h b/drivers/pinctrl/mtmips/pinctrl-mtmips-common.h new file mode 100644 index 0000000..b51d8f0 --- /dev/null +++ b/drivers/pinctrl/mtmips/pinctrl-mtmips-common.h @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2019 MediaTek Inc. All Rights Reserved. + * + * Author: Weijie Gao <weijie.gao@mediatek.com> + */ + +#ifndef _PINCTRL_MTMIPS_COMMON_H_ +#define _PINCTRL_MTMIPS_COMMON_H_ + +#include <common.h> + +struct mtmips_pmx_func { + const char *name; + int value; +}; + +struct mtmips_pmx_group { + const char *name; + + u32 reg; + u32 shift; + char mask; + + int nfuncs; + const struct mtmips_pmx_func *funcs; +}; + +struct mtmips_pinctrl_priv { + void __iomem *base; + + u32 ngroups; + const struct mtmips_pmx_group *groups; + + u32 nfuncs; + const struct mtmips_pmx_func **funcs; +}; + +#define FUNC(name, value) { name, value } + +#define GRP(_name, _funcs, _reg, _shift, _mask) \ + { .name = (_name), .reg = (_reg), .shift = (_shift), .mask = (_mask), \ + .funcs = (_funcs), .nfuncs = ARRAY_SIZE(_funcs) } + +int mtmips_get_functions_count(struct udevice *dev); +const char *mtmips_get_function_name(struct udevice *dev, + unsigned int selector); +int mtmips_pinmux_group_set(struct udevice *dev, unsigned int group_selector, + unsigned int func_selector); +int mtmips_pinctrl_probe(struct mtmips_pinctrl_priv *priv, u32 ngroups, + const struct mtmips_pmx_group *groups); + +#endif /* _PINCTRL_MTMIPS_COMMON_H_ */ diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig index 568d8f2..bb431cc 100644 --- a/drivers/ram/Kconfig +++ b/drivers/ram/Kconfig @@ -54,5 +54,16 @@ config K3_AM654_DDRSS config add support for the initialization of the external SDRAM devices connected to DDR subsystem. +config K3_J721E_DDRSS + bool "Enable J721E DDRSS support" + depends on RAM + help + The J721E DDR subsystem comprises DDR controller, DDR PHY and + wrapper logic to integrate these blocks in the device. The DDR + subsystem is used to provide an interface to external SDRAM + devices which can be utilized for storing program or data. + Enabling this config adds support for the DDR memory controller + on J721E family of SoCs. + source "drivers/ram/rockchip/Kconfig" source "drivers/ram/stm32mp1/Kconfig" diff --git a/drivers/ram/Makefile b/drivers/ram/Makefile index 976ec66..4b77969 100644 --- a/drivers/ram/Makefile +++ b/drivers/ram/Makefile @@ -14,3 +14,4 @@ obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/ obj-$(CONFIG_K3_AM654_DDRSS) += k3-am654-ddrss.o obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/ +obj-$(CONFIG_K3_J721E_DDRSS) += k3-j721e/ diff --git a/drivers/ram/k3-am654-ddrss.c b/drivers/ram/k3-am654-ddrss.c index 7957f67..7015d8c 100644 --- a/drivers/ram/k3-am654-ddrss.c +++ b/drivers/ram/k3-am654-ddrss.c @@ -143,6 +143,7 @@ static void am654_ddrss_ctrl_configuration(struct am654_ddrss_desc *ddrss) ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG11, tmg->ddrctl_dramtmg11); ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG12, tmg->ddrctl_dramtmg12); ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG13, tmg->ddrctl_dramtmg13); + ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG14, tmg->ddrctl_dramtmg14); ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG15, tmg->ddrctl_dramtmg15); ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG17, tmg->ddrctl_dramtmg17); @@ -152,6 +153,7 @@ static void am654_ddrss_ctrl_configuration(struct am654_ddrss_desc *ddrss) ddrss_ctl_writel(DDRSS_DDRCTL_DFITMG0, reg->ddrctl_dfitmg0); ddrss_ctl_writel(DDRSS_DDRCTL_DFITMG1, reg->ddrctl_dfitmg1); ddrss_ctl_writel(DDRSS_DDRCTL_DFITMG2, reg->ddrctl_dfitmg2); + ddrss_ctl_writel(DDRSS_DDRCTL_DFIMISC, reg->ddrctl_dfimisc); ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP0, map->ddrctl_addrmap0); ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP1, map->ddrctl_addrmap1); @@ -204,11 +206,13 @@ static void am654_ddrss_phy_configuration(struct am654_ddrss_desc *ddrss) debug("%s: DDR phy register configuration started\n", __func__); + ddrss_phy_writel(DDRSS_DDRPHY_PGCR0, cfg->ddrphy_pgcr0); ddrss_phy_writel(DDRSS_DDRPHY_PGCR1, cfg->ddrphy_pgcr1); ddrss_phy_writel(DDRSS_DDRPHY_PGCR2, cfg->ddrphy_pgcr2); ddrss_phy_writel(DDRSS_DDRPHY_PGCR3, cfg->ddrphy_pgcr3); ddrss_phy_writel(DDRSS_DDRPHY_PGCR6, cfg->ddrphy_pgcr6); + ddrss_phy_writel(DDRSS_DDRPHY_PTR2, tmg->ddrphy_ptr2); ddrss_phy_writel(DDRSS_DDRPHY_PTR3, tmg->ddrphy_ptr3); ddrss_phy_writel(DDRSS_DDRPHY_PTR4, tmg->ddrphy_ptr4); ddrss_phy_writel(DDRSS_DDRPHY_PTR5, tmg->ddrphy_ptr5); @@ -240,6 +244,11 @@ static void am654_ddrss_phy_configuration(struct am654_ddrss_desc *ddrss) ddrss_phy_writel(DDRSS_DDRPHY_MR4, ctrl->ddrphy_mr4); ddrss_phy_writel(DDRSS_DDRPHY_MR5, ctrl->ddrphy_mr5); ddrss_phy_writel(DDRSS_DDRPHY_MR6, ctrl->ddrphy_mr6); + ddrss_phy_writel(DDRSS_DDRPHY_MR11, ctrl->ddrphy_mr11); + ddrss_phy_writel(DDRSS_DDRPHY_MR12, ctrl->ddrphy_mr12); + ddrss_phy_writel(DDRSS_DDRPHY_MR13, ctrl->ddrphy_mr13); + ddrss_phy_writel(DDRSS_DDRPHY_MR14, ctrl->ddrphy_mr14); + ddrss_phy_writel(DDRSS_DDRPHY_MR22, ctrl->ddrphy_mr22); ddrss_phy_writel(DDRSS_DDRPHY_VTCR0, ctrl->ddrphy_vtcr0); @@ -250,6 +259,8 @@ static void am654_ddrss_phy_configuration(struct am654_ddrss_desc *ddrss) ddrss_phy_writel(DDRSS_DDRPHY_DTCR0, ctrl->ddrphy_dtcr0); ddrss_phy_writel(DDRSS_DDRPHY_DTCR1, ctrl->ddrphy_dtcr1); + ddrss_phy_writel(DDRSS_DDRPHY_ACIOCR0, ioctl->ddrphy_aciocr0); + ddrss_phy_writel(DDRSS_DDRPHY_ACIOCR3, ioctl->ddrphy_aciocr3); ddrss_phy_writel(DDRSS_DDRPHY_ACIOCR5, ioctl->ddrphy_aciocr5); ddrss_phy_writel(DDRSS_DDRPHY_IOVCR0, ioctl->ddrphy_iovcr0); @@ -285,6 +296,10 @@ static void am654_ddrss_phy_configuration(struct am654_ddrss_desc *ddrss) ddrss_phy_writel(DDRSS_DDRPHY_DX8SL1DXCTL2, cfg->ddrphy_dx8sl1dxctl2); ddrss_phy_writel(DDRSS_DDRPHY_DX8SL2DXCTL2, cfg->ddrphy_dx8sl2dxctl2); + ddrss_phy_writel(DDRSS_DDRPHY_DX8SL0DQSCTL, cfg->ddrphy_dx8sl0dqsctl); + ddrss_phy_writel(DDRSS_DDRPHY_DX8SL1DQSCTL, cfg->ddrphy_dx8sl1dqsctl); + ddrss_phy_writel(DDRSS_DDRPHY_DX8SL2DQSCTL, cfg->ddrphy_dx8sl2dqsctl); + debug("%s: DDR phy register configuration completed\n", __func__); } @@ -354,13 +369,32 @@ int read_dqs_training(struct am654_ddrss_desc *ddrss) return 0; } -int rest_training(struct am654_ddrss_desc *ddrss) +int dqs2dq_training(struct am654_ddrss_desc *ddrss) { int ret; - u32 val; - u32 dgsl0, dgsl1, dgsl2, dgsl3, rddly, rd2wr_wr2rd; - debug("%s: Rest of the training started\n", __func__); + debug("%s: DQS2DQ training started\n", __func__); + + ret = __phy_builtin_init_routine(ddrss, PIR_DQS2DQ_MASK, + PGSR0_DQS2DQDONE_MASK, + PGSR0_DQS2DQERR_MASK); + if (ret) { + if (ret == -ETIMEDOUT) + printf("%s: ERROR: DQS2DQ training timedout\n", + __func__); + else + printf("%s:ERROR: DQS2DQ training failed\n", + __func__); + return ret; + } + + debug("%s: DQS2DQ training completed\n", __func__); + return 0; +} + +int write_leveling_adjustment(struct am654_ddrss_desc *ddrss) +{ + int ret; debug("%s: Write Leveling adjustment\n", __func__); ret = __phy_builtin_init_routine(ddrss, PIR_WLADJ_MASK, @@ -374,6 +408,14 @@ int rest_training(struct am654_ddrss_desc *ddrss) __func__); return ret; } + return 0; +} + +int rest_training(struct am654_ddrss_desc *ddrss) +{ + int ret; + + debug("%s: Rest of the training started\n", __func__); debug("%s: Read Deskew adjustment\n", __func__); ret = __phy_builtin_init_routine(ddrss, PIR_RDDSKW_MASK, @@ -422,7 +464,12 @@ int rest_training(struct am654_ddrss_desc *ddrss) __func__); return ret; } + return 0; +} +int VREF_training(struct am654_ddrss_desc *ddrss) +{ + int ret; debug("%s: VREF training\n", __func__); ret = __phy_builtin_init_routine(ddrss, PIR_VREF_MASK, PGSR0_VDONE_MASK, PGSR0_VERR_MASK); @@ -433,6 +480,56 @@ int rest_training(struct am654_ddrss_desc *ddrss) printf("%s: ERROR: VREF training failed\n", __func__); return ret; } + return 0; +} + +int enable_dqs_pd(struct am654_ddrss_desc *ddrss) +{ + u32 val; + + val = ddrss_phy_readl(DDRSS_DDRPHY_DX8SL0DQSCTL); + val &= ~0xFF; + val |= 0xF7; + ddrss_phy_writel(DDRSS_DDRPHY_DX8SL0DQSCTL, val); + + val = ddrss_phy_readl(DDRSS_DDRPHY_DX8SL1DQSCTL); + val &= ~0xFF; + val |= 0xF7; + ddrss_phy_writel(DDRSS_DDRPHY_DX8SL1DQSCTL, val); + + val = ddrss_phy_readl(DDRSS_DDRPHY_DX8SL2DQSCTL); + val &= ~0xFF; + val |= 0xF7; + ddrss_phy_writel(DDRSS_DDRPHY_DX8SL2DQSCTL, val); + + sdelay(16); + return 0; +} + +int disable_dqs_pd(struct am654_ddrss_desc *ddrss) +{ + u32 val; + + val = ddrss_phy_readl(DDRSS_DDRPHY_DX8SL0DQSCTL); + val &= ~0xFF; + ddrss_phy_writel(DDRSS_DDRPHY_DX8SL0DQSCTL, val); + + val = ddrss_phy_readl(DDRSS_DDRPHY_DX8SL1DQSCTL); + val &= ~0xFF; + ddrss_phy_writel(DDRSS_DDRPHY_DX8SL1DQSCTL, val); + + val = ddrss_phy_readl(DDRSS_DDRPHY_DX8SL2DQSCTL); + val &= ~0xFF; + ddrss_phy_writel(DDRSS_DDRPHY_DX8SL2DQSCTL, val); + + sdelay(16); + return 0; +} + +int cleanup_training(struct am654_ddrss_desc *ddrss) +{ + u32 val; + u32 dgsl0, dgsl1, dgsl2, dgsl3, rddly, rd2wr_wr2rd; ddrss_phy_writel(DDRSS_DDRPHY_RANKIDR, 0x00000000); dgsl0 = (ddrss_phy_readl(DDRSS_DDRPHY_DX0GTR0) & 0x1F) >> 2; @@ -528,10 +625,15 @@ int rest_training(struct am654_ddrss_desc *ddrss) static int am654_ddrss_init(struct am654_ddrss_desc *ddrss) { int ret; + u32 val; + struct ddrss_ss_reg_params *reg = &ddrss->params.ss_reg; + + debug("Starting DDR initialization...\n"); debug("%s(ddrss=%p)\n", __func__, ddrss); - ddrss_writel(ddrss->ddrss_ss_cfg, DDRSS_V2H_CTL_REG, 0x000073FF); + ddrss_writel(ddrss->ddrss_ss_cfg, DDRSS_V2H_CTL_REG, + reg->ddrss_v2h_ctl_reg); am654_ddrss_ctrl_configuration(ddrss); @@ -541,6 +643,7 @@ static int am654_ddrss_init(struct am654_ddrss_desc *ddrss) am654_ddrss_phy_configuration(ddrss); + debug("Starting DDR training...\n"); ret = __phy_builtin_init_routine(ddrss, PIR_PHY_INIT, 0x1, 0); if (ret) { dev_err(ddrss->dev, "PHY initialization failed %d\n", ret); @@ -561,15 +664,162 @@ static int am654_ddrss_init(struct am654_ddrss_desc *ddrss) return ret; } - ret = write_leveling(ddrss); - if (ret) - return ret; + val = am654_ddrss_get_type(ddrss); - ret = read_dqs_training(ddrss); - if (ret) - return ret; + switch (val) { + case DDR_TYPE_LPDDR4: + + ret = __phy_builtin_init_routine(ddrss, PIR_DRAM_INIT, + PGSR0_DRAM_INIT_MASK, 0); + if (ret) { + dev_err(ddrss->dev, "DRAM initialization failed %d\n", + ret); + return ret; + } + + /* must perform DRAM_INIT twice for LPDDR4 */ + ret = __phy_builtin_init_routine(ddrss, PIR_DRAM_INIT, + PGSR0_DRAM_INIT_MASK, 0); + if (ret) { + dev_err(ddrss->dev, "DRAM initialization failed %d\n", + ret); + return ret; + } + + ret = am654_ddrss_dram_wait_for_init_complt(ddrss); + if (ret) { + printf("%s: ERROR: DRAM Wait for init complete timedout\n", + __func__); + return ret; + } + + ret = write_leveling(ddrss); + if (ret) + return ret; + + ret = enable_dqs_pd(ddrss); + if (ret) + return ret; + + ret = read_dqs_training(ddrss); + if (ret) + return ret; + + ret = disable_dqs_pd(ddrss); + if (ret) + return ret; + + ret = dqs2dq_training(ddrss); + if (ret) + return ret; + + ret = write_leveling_adjustment(ddrss); + if (ret) + return ret; + + ret = rest_training(ddrss); + if (ret) + return ret; + + ret = VREF_training(ddrss); + if (ret) + return ret; + + debug("LPDDR4 training complete\n"); + break; + + case DDR_TYPE_DDR4: + + debug("Starting DDR4 training\n"); + + ret = __phy_builtin_init_routine(ddrss, PIR_DRAM_INIT, + PGSR0_DRAM_INIT_MASK, 0); + if (ret) { + dev_err(ddrss->dev, "DRAM initialization failed %d\n", + ret); + return ret; + } + + ret = am654_ddrss_dram_wait_for_init_complt(ddrss); + if (ret) { + printf("%s: ERROR: DRAM Wait for init complete timedout\n", + __func__); + return ret; + } + + ret = write_leveling(ddrss); + if (ret) + return ret; - ret = rest_training(ddrss); + ret = read_dqs_training(ddrss); + if (ret) + return ret; + + ret = write_leveling_adjustment(ddrss); + if (ret) + return ret; + + ret = rest_training(ddrss); + if (ret) + return ret; + + ret = VREF_training(ddrss); + if (ret) + return ret; + debug("DDR4 training complete\n"); + break; + + case DDR_TYPE_DDR3: + + debug("Starting DDR3 training\n"); + + ret = __phy_builtin_init_routine(ddrss, PIR_DRAM_INIT, + PGSR0_DRAM_INIT_MASK, 0); + if (ret) { + dev_err(ddrss->dev, "DRAM initialization failed %d\n", + ret); + return ret; + } + + ret = am654_ddrss_dram_wait_for_init_complt(ddrss); + if (ret) { + printf("%s: ERROR: DRAM Wait for init complete timedout\n", + __func__); + return ret; + } + + ret = write_leveling(ddrss); + if (ret) + return ret; + + ret = enable_dqs_pd(ddrss); + if (ret) + return ret; + + ret = read_dqs_training(ddrss); + if (ret) + return ret; + + ret = disable_dqs_pd(ddrss); + if (ret) + return ret; + + ret = write_leveling_adjustment(ddrss); + if (ret) + return ret; + + ret = rest_training(ddrss); + if (ret) + return ret; + + debug("DDR3 training complete\n"); + break; + default: + printf("%s: ERROR: Unsupported DDR type\n", __func__); + return -EINVAL; + } + + ret = cleanup_training(ddrss); if (ret) return ret; @@ -581,6 +831,8 @@ static int am654_ddrss_init(struct am654_ddrss_desc *ddrss) ddrss_phy_writel(DDRSS_DDRPHY_PGCR1, ddrss_phy_readl(DDRSS_DDRPHY_PGCR1) & ~0x40); + debug("Completed DDR training\n"); + return 0; } @@ -682,6 +934,14 @@ static int am654_ddrss_ofdata_to_priv(struct udevice *dev) } ddrss->ddrss_phy_cfg = (void *)reg; + ret = dev_read_u32_array(dev, "ti,ss-reg", + (u32 *)&ddrss->params.ss_reg, + sizeof(ddrss->params.ss_reg) / sizeof(u32)); + if (ret) { + dev_err(dev, "Cannot read ti,ss-reg params\n"); + return ret; + } + ret = dev_read_u32_array(dev, "ti,ctl-reg", (u32 *)&ddrss->params.ctl_reg, sizeof(ddrss->params.ctl_reg) / sizeof(u32)); diff --git a/drivers/ram/k3-am654-ddrss.h b/drivers/ram/k3-am654-ddrss.h index 78d73cd..94a7c91 100644 --- a/drivers/ram/k3-am654-ddrss.h +++ b/drivers/ram/k3-am654-ddrss.h @@ -996,6 +996,10 @@ PGSR0_DIDONE_MASK) #define PGSR0_DATA_TR_INIT_MASK (PGSR0_DRAM_INIT_MASK) +struct ddrss_ss_reg_params { + u32 ddrss_v2h_ctl_reg; +}; + struct ddrss_ddrctl_reg_params { u32 ddrctl_dfimisc; u32 ddrctl_dfitmg0; @@ -1111,12 +1115,15 @@ struct ddrss_ddrphy_cfg_params { u32 ddrphy_dx8sl0dxctl2; u32 ddrphy_dx8sl0iocr; u32 ddrphy_dx8sl0pllcr0; + u32 ddrphy_dx8sl0dqsctl; u32 ddrphy_dx8sl1dxctl2; u32 ddrphy_dx8sl1iocr; u32 ddrphy_dx8sl1pllcr0; + u32 ddrphy_dx8sl1dqsctl; u32 ddrphy_dx8sl2dxctl2; u32 ddrphy_dx8sl2iocr; u32 ddrphy_dx8sl2pllcr0; + u32 ddrphy_dx8sl2dqsctl; u32 ddrphy_dxccr; u32 ddrphy_odtcr; u32 ddrphy_pgcr0; @@ -1147,6 +1154,8 @@ struct ddrss_ddrphy_ctrl_params { }; struct ddrss_ddrphy_ioctl_params { + u32 ddrphy_aciocr0; + u32 ddrphy_aciocr3; u32 ddrphy_aciocr5; u32 ddrphy_iovcr0; }; @@ -1173,6 +1182,7 @@ struct ddrss_ddrphy_zq_params { }; struct ddrss_params { + struct ddrss_ss_reg_params ss_reg; struct ddrss_ddrctl_reg_params ctl_reg; struct ddrss_ddrctl_crc_params ctl_crc; struct ddrss_ddrctl_ecc_params ctl_ecc; diff --git a/drivers/ram/k3-j721e/Makefile b/drivers/ram/k3-j721e/Makefile new file mode 100644 index 0000000..d60cc62 --- /dev/null +++ b/drivers/ram/k3-j721e/Makefile @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ +# + +obj-$(CONFIG_K3_J721E_DDRSS) += k3-j721e-ddrss.o +obj-$(CONFIG_K3_J721E_DDRSS) += lpddr4_obj_if.o +obj-$(CONFIG_K3_J721E_DDRSS) += lpddr4.o diff --git a/drivers/ram/k3-j721e/cps_drv_lpddr4.h b/drivers/ram/k3-j721e/cps_drv_lpddr4.h new file mode 100644 index 0000000..706a5cd --- /dev/null +++ b/drivers/ram/k3-j721e/cps_drv_lpddr4.h @@ -0,0 +1,119 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/****************************************************************************** + * + * Copyright (C) 2017-2018 Cadence Design Systems, Inc. + * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ + * + * cps_drv_lpddr4.h + * Interface for the Register Accaess Layer of Cadence Platform Service (CPS) + ***************************************************************************** + */ + +#ifndef CPS_DRV_H_ +#define CPS_DRV_H_ + +#include <stddef.h> +#include <inttypes.h> +#include <asm/io.h> + +/** + * \brief Read a 32-bit value from memory. + * \param reg address of the memory mapped hardware register + * \return the value at the given address + */ +#define CPS_REG_READ(reg) (readl((volatile uint32_t*)(reg))) + +/** + * \brief Write a 32-bit address value to memory. + * \param reg address of the memory mapped hardware register + * \param value unsigned 32-bit value to write + */ +#define CPS_REG_WRITE(reg, value) (writel((uint32_t)(value), (volatile uint32_t*)(reg))) + +/** + * \brief Subtitue the value of fld macro and concatinate with required string + * \param fld field name + */ +#define CPS_FLD_MASK(fld) (fld ## _MASK) +#define CPS_FLD_SHIFT(fld) (fld ## _SHIFT) +#define CPS_FLD_WIDTH(fld) (fld ## _WIDTH) +#define CPS_FLD_WOCLR(fld) (fld ## _WOCLR) +#define CPS_FLD_WOSET(fld) (fld ## _WOSET) + +/** + * \brief Read a value of bit-field from the register value. + * \param reg register name + * \param fld field name + * \param reg_value register value + * \return bit-field value + */ +#define CPS_FLD_READ(fld, reg_value) (cps_fldread((uint32_t)(CPS_FLD_MASK(fld)), \ + (uint32_t)(CPS_FLD_SHIFT(fld)), \ + (uint32_t)(reg_value))) + +/** + * \brief Write a value of the bit-field into the register value. + * \param reg register name + * \param fld field name + * \param reg_value register value + * \param value value to be written to bit-field + * \return modified register value + */ +#define CPS_FLD_WRITE(fld, reg_value, value) (cps_fldwrite((uint32_t)(CPS_FLD_MASK(fld)), \ + (uint32_t)(CPS_FLD_SHIFT(fld)), \ + (uint32_t)(reg_value), (uint32_t)(value))) + +/** + * \brief Set bit within the register value. + * \param reg register name + * \param fld field name + * \param reg_value register value + * \return modified register value + */ +#define CPS_FLD_SET(fld, reg_value) (cps_fldset((uint32_t)(CPS_FLD_WIDTH(fld)), \ + (uint32_t)(CPS_FLD_MASK(fld)), \ + (uint32_t)(CPS_FLD_WOCLR(fld)), \ + (uint32_t)(reg_value))) + +static inline uint32_t cps_fldread(uint32_t mask, uint32_t shift, uint32_t reg_value) +{ + uint32_t result = (reg_value & mask) >> shift; + + return (result); +} + +/** + * \brief Write a value of the bit-field into the register value. + * \param mask mask for the bit-field + * \param shift bit-field shift from LSB + * \param reg_value register value + * \param value value to be written to bit-field + * \return modified register value + */ +static inline uint32_t cps_fldwrite(uint32_t mask, uint32_t shift, uint32_t reg_value, uint32_t value) +{ + uint32_t new_value = (value << shift) & mask; + + new_value = (reg_value & ~mask) | new_value; + return (new_value); +} + +/** + * \brief Set bit within the register value. + * \param width width of the bit-field + * \param mask mask for the bit-field + * \param is_woclr is bit-field has 'write one to clear' flag set + * \param reg_value register value + * \return modified register value + */ +static inline uint32_t cps_fldset(uint32_t width, uint32_t mask, uint32_t is_woclr, uint32_t reg_value) +{ + uint32_t new_value = reg_value; + /* Confirm the field to be bit and not write to clear type */ + if ((width == 1U) && (is_woclr == 0U)) { + new_value |= mask; + } + + return (new_value); +} +#endif /* CPS_DRV_H_ */ diff --git a/drivers/ram/k3-j721e/k3-j721e-ddrss.c b/drivers/ram/k3-j721e/k3-j721e-ddrss.c new file mode 100644 index 0000000..9feb0aa --- /dev/null +++ b/drivers/ram/k3-j721e/k3-j721e-ddrss.c @@ -0,0 +1,372 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Texas Instruments' J721E DDRSS driver + * + * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ + */ + +#include <common.h> +#include <clk.h> +#include <dm.h> +#include <ram.h> +#include <asm/io.h> +#include <power-domain.h> +#include <wait_bit.h> + +#include "lpddr4_obj_if.h" +#include "lpddr4_if.h" +#include "lpddr4_structs_if.h" +#include "lpddr4_ctl_regs.h" + +#define SRAM_MAX 512 + +#define CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS 0x80 +#define CTRLMMR_DDR4_FSP_CLKCHNG_ACK_OFFS 0xc0 + +struct j721e_ddrss_desc { + struct udevice *dev; + void __iomem *ddrss_ss_cfg; + void __iomem *ddrss_ctrl_mmr; + struct power_domain ddrcfg_pwrdmn; + struct power_domain ddrdata_pwrdmn; + struct clk ddr_clk; + struct clk osc_clk; + u32 ddr_freq1; + u32 ddr_freq2; + u32 ddr_fhs_cnt; +}; + +static LPDDR4_OBJ *driverdt; +static lpddr4_config config; +static lpddr4_privatedata pd; + +static struct j721e_ddrss_desc *ddrss; + +#define TH_MACRO_EXP(fld, str) (fld##str) + +#define TH_FLD_MASK(fld) TH_MACRO_EXP(fld, _MASK) +#define TH_FLD_SHIFT(fld) TH_MACRO_EXP(fld, _SHIFT) +#define TH_FLD_WIDTH(fld) TH_MACRO_EXP(fld, _WIDTH) +#define TH_FLD_WOCLR(fld) TH_MACRO_EXP(fld, _WOCLR) +#define TH_FLD_WOSET(fld) TH_MACRO_EXP(fld, _WOSET) + +#define str(s) #s +#define xstr(s) str(s) + +#define CTL_SHIFT 11 +#define PHY_SHIFT 11 +#define PI_SHIFT 10 + +#define TH_OFFSET_FROM_REG(REG, SHIFT, offset) do {\ + char *i, *pstr= xstr(REG); offset = 0;\ + for (i = &pstr[SHIFT]; *i != '\0'; ++i) {\ + offset = offset * 10 + (*i - '0'); }\ + } while (0) + +static void j721e_lpddr4_ack_freq_upd_req(void) +{ + unsigned int req_type, counter; + + debug("--->>> LPDDR4 Initialization is in progress ... <<<---\n"); + + for (counter = 0; counter < ddrss->ddr_fhs_cnt; counter++) { + if (wait_for_bit_le32(ddrss->ddrss_ctrl_mmr + + CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS, 0x80, + true, 10000, false)) { + printf("Timeout during frequency handshake\n"); + hang(); + } + + req_type = readl(ddrss->ddrss_ctrl_mmr + + CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS) & 0x03; + + debug("%s: received freq change req: req type = %d, req no. = %d \n", + __func__, req_type, counter); + + if (req_type == 1) + clk_set_rate(&ddrss->ddr_clk, ddrss->ddr_freq1); + else if (req_type == 2) + clk_set_rate(&ddrss->ddr_clk, ddrss->ddr_freq2); + else if (req_type == 0) + /* Put DDR pll in bypass mode */ + clk_set_rate(&ddrss->ddr_clk, + clk_get_rate(&ddrss->osc_clk)); + else + printf("%s: Invalid freq request type\n", __func__); + + writel(0x1, ddrss->ddrss_ctrl_mmr + + CTRLMMR_DDR4_FSP_CLKCHNG_ACK_OFFS); + if (wait_for_bit_le32(ddrss->ddrss_ctrl_mmr + + CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS, 0x80, + false, 10, false)) { + printf("Timeout during frequency handshake\n"); + hang(); + } + writel(0x0, ddrss->ddrss_ctrl_mmr + + CTRLMMR_DDR4_FSP_CLKCHNG_ACK_OFFS); + } +} + +static void j721e_lpddr4_info_handler(const lpddr4_privatedata * pd, + lpddr4_infotype infotype) +{ + if (infotype == LPDDR4_DRV_SOC_PLL_UPDATE) { + j721e_lpddr4_ack_freq_upd_req(); + } +} + +static int j721e_ddrss_power_on(struct j721e_ddrss_desc *ddrss) +{ + int ret; + + debug("%s(ddrss=%p)\n", __func__, ddrss); + + ret = power_domain_on(&ddrss->ddrcfg_pwrdmn); + if (ret) { + dev_err(ddrss->dev, "power_domain_on() failed: %d\n", ret); + return ret; + } + + ret = power_domain_on(&ddrss->ddrdata_pwrdmn); + if (ret) { + dev_err(ddrss->dev, "power_domain_on() failed: %d\n", ret); + return ret; + } + + return 0; +} + +static int j721e_ddrss_ofdata_to_priv(struct udevice *dev) +{ + struct j721e_ddrss_desc *ddrss = dev_get_priv(dev); + phys_addr_t reg; + int ret; + + debug("%s(dev=%p)\n", __func__, dev); + + reg = dev_read_addr_name(dev, "cfg"); + if (reg == FDT_ADDR_T_NONE) { + dev_err(dev, "No reg property for DDRSS wrapper logic\n"); + return -EINVAL; + } + ddrss->ddrss_ss_cfg = (void *)reg; + + reg = dev_read_addr_name(dev, "ctrl_mmr_lp4"); + if (reg == FDT_ADDR_T_NONE) { + dev_err(dev, "No reg property for CTRL MMR\n"); + return -EINVAL; + } + ddrss->ddrss_ctrl_mmr = (void *)reg; + + ret = power_domain_get_by_index(dev, &ddrss->ddrcfg_pwrdmn, 0); + if (ret) { + dev_err(dev, "power_domain_get() failed: %d\n", ret); + return ret; + } + + ret = power_domain_get_by_index(dev, &ddrss->ddrdata_pwrdmn, 1); + if (ret) { + dev_err(dev, "power_domain_get() failed: %d\n", ret); + return ret; + } + + ret = clk_get_by_index(dev, 0, &ddrss->ddr_clk); + if (ret) + dev_err(dev, "clk get failed%d\n", ret); + + ret = clk_get_by_index(dev, 1, &ddrss->osc_clk); + if (ret) + dev_err(dev, "clk get failed for osc clk %d\n", ret); + + ret = dev_read_u32(dev, "ti,ddr-freq1", &ddrss->ddr_freq1); + if (ret) + dev_err(dev, "ddr freq1 not populated %d\n", ret); + + ret = dev_read_u32(dev, "ti,ddr-freq2", &ddrss->ddr_freq2); + if (ret) + dev_err(dev, "ddr freq2 not populated %d\n", ret); + + ret = dev_read_u32(dev, "ti,ddr-fhs-cnt", &ddrss->ddr_fhs_cnt); + if (ret) + dev_err(dev, "ddr fhs cnt not populated %d\n", ret); + + /* Put DDR pll in bypass mode */ + ret = clk_set_rate(&ddrss->ddr_clk, clk_get_rate(&ddrss->osc_clk)); + if (ret) + dev_err(dev, "ddr clk bypass failed\n"); + + return ret; +} + +void j721e_lpddr4_probe(void) +{ + uint32_t status = 0U; + uint16_t configsize = 0U; + + status = driverdt->probe(&config, &configsize); + + if ((status != 0) || (configsize != sizeof(lpddr4_privatedata)) + || (configsize > SRAM_MAX)) { + printf("LPDDR4_Probe: FAIL\n"); + hang(); + } else { + debug("LPDDR4_Probe: PASS\n"); + } +} + +void j721e_lpddr4_init(void) +{ + uint32_t status = 0U; + + if ((sizeof(pd) != sizeof(lpddr4_privatedata)) + || (sizeof(pd) > SRAM_MAX)) { + printf("LPDDR4_Init: FAIL\n"); + hang(); + } + + config.ctlbase = (struct lpddr4_ctlregs_s *)ddrss->ddrss_ss_cfg; + config.infohandler = (lpddr4_infocallback) j721e_lpddr4_info_handler; + + status = driverdt->init(&pd, &config); + + if ((status > 0U) || + (pd.ctlbase != (struct lpddr4_ctlregs_s *)config.ctlbase) || + (pd.ctlinterrupthandler != config.ctlinterrupthandler) || + (pd.phyindepinterrupthandler != config.phyindepinterrupthandler)) { + printf("LPDDR4_Init: FAIL\n"); + hang(); + } else { + debug("LPDDR4_Init: PASS\n"); + } +} + +void populate_data_array_from_dt(lpddr4_reginitdata * reginit_data) +{ + int ret, i; + + ret = dev_read_u32_array(ddrss->dev, "ti,ctl-data", + (u32 *) reginit_data->denalictlreg, + LPDDR4_CTL_REG_COUNT); + if (ret) + printf("Error reading ctrl data\n"); + + for (i = 0; i < LPDDR4_CTL_REG_COUNT; i++) + reginit_data->updatectlreg[i] = true; + + ret = dev_read_u32_array(ddrss->dev, "ti,pi-data", + (u32 *) reginit_data->denaliphyindepreg, + LPDDR4_PHY_INDEP_REG_COUNT); + if (ret) + printf("Error reading PI data\n"); + + for (i = 0; i < LPDDR4_PHY_INDEP_REG_COUNT; i++) + reginit_data->updatephyindepreg[i] = true; + + ret = dev_read_u32_array(ddrss->dev, "ti,phy-data", + (u32 *) reginit_data->denaliphyreg, + LPDDR4_PHY_REG_COUNT); + if (ret) + printf("Error reading PHY data\n"); + + for (i = 0; i < LPDDR4_PHY_REG_COUNT; i++) + reginit_data->updatephyreg[i] = true; +} + +void j721e_lpddr4_hardware_reg_init(void) +{ + uint32_t status = 0U; + lpddr4_reginitdata reginitdata; + + populate_data_array_from_dt(®initdata); + + status = driverdt->writectlconfig(&pd, ®initdata); + if (!status) { + status = driverdt->writephyindepconfig(&pd, ®initdata); + } + if (!status) { + status = driverdt->writephyconfig(&pd, ®initdata); + } + if (status) { + printf(" ERROR: LPDDR4_HardwareRegInit failed!!\n"); + hang(); + } + + return; +} + +void j721e_lpddr4_start(void) +{ + uint32_t status = 0U; + uint32_t regval = 0U; + uint32_t offset = 0U; + + TH_OFFSET_FROM_REG(LPDDR4__START__REG, CTL_SHIFT, offset); + + status = driverdt->readreg(&pd, LPDDR4_CTL_REGS, offset, ®val); + if ((status > 0U) || ((regval & TH_FLD_MASK(LPDDR4__START__FLD)) != 0U)) { + printf("LPDDR4_StartTest: FAIL\n"); + hang(); + } + + status = driverdt->start(&pd); + if (status > 0U) { + printf("LPDDR4_StartTest: FAIL\n"); + hang(); + } + + status = driverdt->readreg(&pd, LPDDR4_CTL_REGS, offset, ®val); + if ((status > 0U) || ((regval & TH_FLD_MASK(LPDDR4__START__FLD)) != 1U)) { + printf("LPDDR4_Start: FAIL\n"); + hang(); + } else { + debug("LPDDR4_Start: PASS\n"); + } +} + +static int j721e_ddrss_probe(struct udevice *dev) +{ + int ret; + ddrss = dev_get_priv(dev); + + debug("%s(dev=%p)\n", __func__, dev); + + ret = j721e_ddrss_ofdata_to_priv(dev); + if (ret) + return ret; + + ddrss->dev = dev; + ret = j721e_ddrss_power_on(ddrss); + if (ret) + return ret; + + driverdt = lpddr4_getinstance(); + j721e_lpddr4_probe(); + j721e_lpddr4_init(); + j721e_lpddr4_hardware_reg_init(); + j721e_lpddr4_start(); + + return ret; +} + +static int j721e_ddrss_get_info(struct udevice *dev, struct ram_info *info) +{ + return 0; +} + +static struct ram_ops j721e_ddrss_ops = { + .get_info = j721e_ddrss_get_info, +}; + +static const struct udevice_id j721e_ddrss_ids[] = { + {.compatible = "ti,j721e-ddrss"}, + {} +}; + +U_BOOT_DRIVER(j721e_ddrss) = { + .name = "j721e_ddrss", + .id = UCLASS_RAM, + .of_match = j721e_ddrss_ids, + .ops = &j721e_ddrss_ops, + .probe = j721e_ddrss_probe, + .priv_auto_alloc_size = sizeof(struct j721e_ddrss_desc), +}; diff --git a/drivers/ram/k3-j721e/lpddr4.c b/drivers/ram/k3-j721e/lpddr4.c new file mode 100644 index 0000000..2c3892d --- /dev/null +++ b/drivers/ram/k3-j721e/lpddr4.c @@ -0,0 +1,2119 @@ +// SPDX-License-Identifier: BSD-3-Clause +/****************************************************************************** + * Copyright (C) 2012-2018 Cadence Design Systems, Inc. + * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ + * + * lpddr4.c + * + ***************************************************************************** + */ +#include "cps_drv_lpddr4.h" +#include "lpddr4_ctl_regs.h" +#include "lpddr4_if.h" +#include "lpddr4_private.h" +#include "lpddr4_sanity.h" +#include "lpddr4_structs_if.h" + +#define LPDDR4_CUSTOM_TIMEOUT_DELAY 100000000U + +/** + * Internal Function:Poll for status of interrupt received by the Controller. + * @param[in] pD Driver state info specific to this instance. + * @param[in] irqBit Interrupt status bit to be checked. + * @param[in] delay time delay. + * @return CDN_EOK on success (Interrupt status high). + * @return EIO on poll time out. + * @return EINVAL checking status was not successful. + */ +static uint32_t lpddr4_pollctlirq(const lpddr4_privatedata * pd, + lpddr4_ctlinterrupt irqbit, uint32_t delay) +{ + + uint32_t result = 0U; + uint32_t timeout = 0U; + bool irqstatus = false; + + /* Loop until irqStatus found to be 1 or if value of 'result' !=CDN_EOK */ + do { + if (++timeout == delay) { + result = EIO; + break; + } + /* cps_delayns(10000000U); */ + result = lpddr4_checkctlinterrupt(pd, irqbit, &irqstatus); + } while ((irqstatus == false) && (result == (uint32_t) CDN_EOK)); + + return result; +} + +/** + * Internal Function:Poll for status of interrupt received by the PHY Independent Module. + * @param[in] pD Driver state info specific to this instance. + * @param[in] irqBit Interrupt status bit to be checked. + * @param[in] delay time delay. + * @return CDN_EOK on success (Interrupt status high). + * @return EIO on poll time out. + * @return EINVAL checking status was not successful. + */ +static uint32_t lpddr4_pollphyindepirq(const lpddr4_privatedata * pd, + lpddr4_phyindepinterrupt irqbit, + uint32_t delay) +{ + + uint32_t result = 0U; + uint32_t timeout = 0U; + bool irqstatus = false; + + /* Loop until irqStatus found to be 1 or if value of 'result' !=CDN_EOK */ + do { + if (++timeout == delay) { + result = EIO; + break; + } + /* cps_delayns(10000000U); */ + result = lpddr4_checkphyindepinterrupt(pd, irqbit, &irqstatus); + } while ((irqstatus == false) && (result == (uint32_t) CDN_EOK)); + + return result; +} + +/** + * Internal Function:Trigger function to poll and Ack IRQs + * @param[in] pD Driver state info specific to this instance. + * @return CDN_EOK on success (Interrupt status high). + * @return EIO on poll time out. + * @return EINVAL checking status was not successful. + */ +static uint32_t lpddr4_pollandackirq(const lpddr4_privatedata * pd) +{ + uint32_t result = 0U; + + /* Wait for PhyIndependent module to finish up ctl init sequence */ + result = + lpddr4_pollphyindepirq(pd, LPDDR4_PHY_INDEP_INIT_DONE_BIT, + LPDDR4_CUSTOM_TIMEOUT_DELAY); + + /* Ack to clear the PhyIndependent interrupt bit */ + if (result == (uint32_t) CDN_EOK) { + result = + lpddr4_ackphyindepinterrupt(pd, + LPDDR4_PHY_INDEP_INIT_DONE_BIT); + } + /* Wait for the CTL end of initialization */ + if (result == (uint32_t) CDN_EOK) { + result = + lpddr4_pollctlirq(pd, LPDDR4_MC_INIT_DONE, + LPDDR4_CUSTOM_TIMEOUT_DELAY); + } + /* Ack to clear the Ctl interrupt bit */ + if (result == (uint32_t) CDN_EOK) { + result = lpddr4_ackctlinterrupt(pd, LPDDR4_MC_INIT_DONE); + } + return result; +} + +/** + * Internal Function: Controller start sequence. + * @param[in] pD Driver state info specific to this instance. + * @return CDN_EOK on success. + * @return EINVAL starting controller was not successful. + */ +static uint32_t lpddr4_startsequencecontroller(const lpddr4_privatedata * pd) +{ + uint32_t result = 0U; + uint32_t regval = 0U; + lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase; + lpddr4_infotype infotype; + + /* Set the PI_start to initiate leveling procedure */ + regval = + CPS_FLD_SET(LPDDR4__PI_START__FLD, + CPS_REG_READ(&(ctlregbase->LPDDR4__PI_START__REG))); + CPS_REG_WRITE((&(ctlregbase->LPDDR4__PI_START__REG)), regval); + + /* Set the Ctl_start */ + regval = + CPS_FLD_SET(LPDDR4__START__FLD, + CPS_REG_READ(&(ctlregbase->LPDDR4__START__REG))); + CPS_REG_WRITE(&(ctlregbase->LPDDR4__START__REG), regval); + + if (pd->infohandler != NULL) { + /* If a handler is registered, call it with the relevant information type */ + infotype = LPDDR4_DRV_SOC_PLL_UPDATE; + pd->infohandler(pd, infotype); + } + + result = lpddr4_pollandackirq(pd); + + return result; +} + +/** + * Internal Function: To add the offset to given address. + * @param[in] addr Address to which the offset has to be added. + * @param[in] regOffset The offset + * @return regAddr The address value after the summation. + */ +static volatile uint32_t *lpddr4_addoffset(volatile uint32_t * addr, + uint32_t regoffset) +{ + + volatile uint32_t *local_addr = addr; + /* Declaring as array to add the offset value. */ + volatile uint32_t *regaddr = &local_addr[regoffset]; + return regaddr; +} + +/** + * Checks configuration object. + * @param[in] config Driver/hardware configuration required. + * @param[out] configSize Size of memory allocations required. + * @return CDN_EOK on success (requirements structure filled). + * @return ENOTSUP if configuration cannot be supported due to driver/hardware constraints. + */ +uint32_t lpddr4_probe(const lpddr4_config * config, uint16_t * configsize) +{ + uint32_t result; + + result = (uint32_t) (lpddr4_probesf(config, configsize)); + if (result == (uint32_t) CDN_EOK) { + *configsize = (uint16_t) (sizeof(lpddr4_privatedata)); + } + return result; +} + +/** + * Init function to be called after LPDDR4_probe() to set up the driver configuration. + * Memory should be allocated for drv_data (using the size determined using LPDDR4_probe) before + * calling this API, init_settings should be initialized with base addresses for PHY Independent Module, + * Controller and PHY before calling this function. + * If callbacks are required for interrupt handling, these should also be configured in init_settings. + * @param[in] pD Driver state info specific to this instance. + * @param[in] cfg Specifies driver/hardware configuration. + * @return CDN_EOK on success + * @return EINVAL if illegal/inconsistent values in cfg. + * @return ENOTSUP if hardware has an inconsistent configuration or doesn't support feature(s) + * required by 'config' parameters. + */ +uint32_t lpddr4_init(lpddr4_privatedata * pd, const lpddr4_config * cfg) +{ + uint32_t result = 0U; + uint16_t productid = 0U; + uint32_t version[2] = { 0, 0 }; + + result = lpddr4_initsf(pd, cfg); + if (result == (uint32_t) CDN_EOK) { + /* Validate Magic number */ + lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) cfg->ctlbase; + productid = (uint16_t) (CPS_FLD_READ(LPDDR4__CONTROLLER_ID__FLD, + CPS_REG_READ(& + (ctlregbase-> + LPDDR4__CONTROLLER_ID__REG)))); + version[0] = + (uint32_t) (CPS_FLD_READ + (LPDDR4__CONTROLLER_VERSION_0__FLD, + CPS_REG_READ(& + (ctlregbase-> + LPDDR4__CONTROLLER_VERSION_0__REG)))); + version[1] = + (uint32_t) (CPS_FLD_READ + (LPDDR4__CONTROLLER_VERSION_1__FLD, + CPS_REG_READ(& + (ctlregbase-> + LPDDR4__CONTROLLER_VERSION_1__REG)))); + if ((productid == PRODUCT_ID) && (version[0] == VERSION_0) + && (version[1] == VERSION_1)) { + /* Populating configuration data to pD */ + pd->ctlbase = ctlregbase; + pd->infohandler = + (lpddr4_infocallback) cfg->infohandler; + pd->ctlinterrupthandler = + (lpddr4_ctlcallback) cfg->ctlinterrupthandler; + pd->phyindepinterrupthandler = + (lpddr4_phyindepcallback) cfg-> + phyindepinterrupthandler; + } else { + /* Magic number validation failed - Driver doesn't support given IP version */ + result = (uint32_t) EOPNOTSUPP; + } + } + return result; +} + +/** + * Start the driver. + * @param[in] pD Driver state info specific to this instance. + */ +uint32_t lpddr4_start(const lpddr4_privatedata * pd) +{ + uint32_t result = 0U; + uint32_t regval = 0U; + + result = lpddr4_startsf(pd); + if (result == (uint32_t) CDN_EOK) { + lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase; + + /* Enable PI as the initiator for DRAM */ + regval = + CPS_FLD_SET(LPDDR4__PI_INIT_LVL_EN__FLD, + CPS_REG_READ(& + (ctlregbase-> + LPDDR4__PI_INIT_LVL_EN__REG))); + regval = CPS_FLD_SET(LPDDR4__PI_NORMAL_LVL_SEQ__FLD, regval); + CPS_REG_WRITE((&(ctlregbase->LPDDR4__PI_INIT_LVL_EN__REG)), + regval); + + /* Start PI init sequence. */ + result = lpddr4_startsequencecontroller(pd); + } + return result; +} + +/** + * Read a register from the controller, PHY or PHY Independent Module + * @param[in] pD Driver state info specific to this instance. + * @param[in] cpp Indicates whether controller, PHY or PHY Independent Module register + * @param[in] regOffset Register offset + * @param[out] regValue Register value read + * @return CDN_EOK on success. + * @return EINVAL if regOffset if out of range or regValue is NULL + */ +uint32_t lpddr4_readreg(const lpddr4_privatedata * pd, lpddr4_regblock cpp, + uint32_t regoffset, uint32_t * regvalue) +{ + uint32_t result = 0U; + + result = lpddr4_readregsf(pd, cpp, regvalue); + if (result == (uint32_t) CDN_EOK) { + lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase; + + if (cpp == LPDDR4_CTL_REGS) { + if (regoffset >= LPDDR4_CTL_REG_COUNT) { + /* Return if user provider invalid register number */ + result = EINVAL; + } else { + *regvalue = + CPS_REG_READ(lpddr4_addoffset + (&(ctlregbase->DENALI_CTL_0), + regoffset)); + } + } else if (cpp == LPDDR4_PHY_REGS) { + if (regoffset >= LPDDR4_PHY_REG_COUNT) { + /* Return if user provider invalid register number */ + result = EINVAL; + } else { + *regvalue = + CPS_REG_READ(lpddr4_addoffset + (&(ctlregbase->DENALI_PHY_0), + regoffset)); + } + + } else { + if (regoffset >= LPDDR4_PHY_INDEP_REG_COUNT) { + /* Return if user provider invalid register number */ + result = EINVAL; + } else { + *regvalue = + CPS_REG_READ(lpddr4_addoffset + (&(ctlregbase->DENALI_PI_0), + regoffset)); + } + } + } + return result; +} + +uint32_t lpddr4_writereg(const lpddr4_privatedata * pd, lpddr4_regblock cpp, + uint32_t regoffset, uint32_t regvalue) +{ + uint32_t result = 0U; + + result = lpddr4_writeregsf(pd, cpp); + if (result == (uint32_t) CDN_EOK) { + lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase; + + if (cpp == LPDDR4_CTL_REGS) { + if (regoffset >= LPDDR4_CTL_REG_COUNT) { + /* Return if user provider invalid register number */ + result = EINVAL; + } else { + CPS_REG_WRITE(lpddr4_addoffset + (&(ctlregbase->DENALI_CTL_0), + regoffset), regvalue); + } + } else if (cpp == LPDDR4_PHY_REGS) { + if (regoffset >= LPDDR4_PHY_REG_COUNT) { + /* Return if user provider invalid register number */ + result = EINVAL; + } else { + CPS_REG_WRITE(lpddr4_addoffset + (&(ctlregbase->DENALI_PHY_0), + regoffset), regvalue); + } + } else { + if (regoffset >= LPDDR4_PHY_INDEP_REG_COUNT) { + /* Return if user provider invalid register number */ + result = EINVAL; + } else { + CPS_REG_WRITE(lpddr4_addoffset + (&(ctlregbase->DENALI_PI_0), + regoffset), regvalue); + } + } + } + + return result; +} + +static uint32_t lpddr4_checkmmrreaderror(const lpddr4_privatedata * pd, + uint64_t * mmrvalue, + uint8_t * mrrstatus) +{ + + uint64_t lowerdata; + lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase; + uint32_t result = (uint32_t) CDN_EOK; + + /* Check if mode register read error interrupt occurred */ + if (lpddr4_pollctlirq(pd, LPDDR4_MRR_ERROR, 100) == 0U) { + /* Mode register read error interrupt, read MRR status register and return. */ + *mrrstatus = + (uint8_t) CPS_FLD_READ(LPDDR4__MRR_ERROR_STATUS__FLD, + CPS_REG_READ(& + (ctlregbase-> + LPDDR4__MRR_ERROR_STATUS__REG))); + *mmrvalue = 0; + result = EIO; + } else { + *mrrstatus = 0; + /* Mode register read was successful, read DATA */ + lowerdata = + CPS_REG_READ(& + (ctlregbase-> + LPDDR4__PERIPHERAL_MRR_DATA_0__REG)); + *mmrvalue = + CPS_REG_READ(& + (ctlregbase-> + LPDDR4__PERIPHERAL_MRR_DATA_1__REG)); + *mmrvalue = (uint64_t) ((*mmrvalue << WORD_SHIFT) | lowerdata); + /* Acknowledge MR_READ_DONE interrupt to clear it */ + result = lpddr4_ackctlinterrupt(pd, LPDDR4_MR_READ_DONE); + } + return result; +} + +uint32_t lpddr4_getmmrregister(const lpddr4_privatedata * pd, + uint32_t readmoderegval, uint64_t * mmrvalue, + uint8_t * mmrstatus) +{ + + uint32_t result = 0U; + uint32_t tdelay = 1000U; + uint32_t regval = 0U; + + result = lpddr4_getmmrregistersf(pd, mmrvalue, mmrstatus); + if (result == (uint32_t) CDN_EOK) { + + lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase; + + /* Populate the calculated value to the register */ + regval = + CPS_FLD_WRITE(LPDDR4__READ_MODEREG__FLD, + CPS_REG_READ(& + (ctlregbase-> + LPDDR4__READ_MODEREG__REG)), + readmoderegval); + CPS_REG_WRITE(&(ctlregbase->LPDDR4__READ_MODEREG__REG), regval); + + /* Wait until the Read is done */ + result = lpddr4_pollctlirq(pd, LPDDR4_MR_READ_DONE, tdelay); + } + if (result == (uint32_t) CDN_EOK) { + result = lpddr4_checkmmrreaderror(pd, mmrvalue, mmrstatus); + } + return result; +} + +static uint32_t lpddr4_writemmrregister(const lpddr4_privatedata * pd, + uint32_t writemoderegval) +{ + + uint32_t result = (uint32_t) CDN_EOK; + uint32_t tdelay = 1000U; + uint32_t regval = 0U; + lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase; + + /* Populate the calculated value to the register */ + regval = + CPS_FLD_WRITE(LPDDR4__WRITE_MODEREG__FLD, + CPS_REG_READ(& + (ctlregbase-> + LPDDR4__WRITE_MODEREG__REG)), + writemoderegval); + CPS_REG_WRITE(&(ctlregbase->LPDDR4__WRITE_MODEREG__REG), regval); + + result = lpddr4_pollctlirq(pd, LPDDR4_MR_WRITE_DONE, tdelay); + + return result; +} + +uint32_t lpddr4_setmmrregister(const lpddr4_privatedata * pd, + uint32_t writemoderegval, uint8_t * mrwstatus) +{ + uint32_t result = 0U; + + result = lpddr4_setmmrregistersf(pd, mrwstatus); + if (result == (uint32_t) CDN_EOK) { + + /* Function call to trigger Mode register write */ + result = lpddr4_writemmrregister(pd, writemoderegval); + + if (result == (uint32_t) CDN_EOK) { + result = + lpddr4_ackctlinterrupt(pd, LPDDR4_MR_WRITE_DONE); + } + /* Read the status of mode register write */ + if (result == (uint32_t) CDN_EOK) { + lpddr4_ctlregs *ctlregbase = + (lpddr4_ctlregs *) pd->ctlbase; + *mrwstatus = + (uint8_t) CPS_FLD_READ(LPDDR4__MRW_STATUS__FLD, + CPS_REG_READ(& + (ctlregbase-> + LPDDR4__MRW_STATUS__REG))); + if ((*mrwstatus) != 0U) { + result = EIO; + } + } + } + + return result; +} + +uint32_t lpddr4_writectlconfig(const lpddr4_privatedata * pd, + const lpddr4_reginitdata * regvalues) +{ + uint32_t result; + uint32_t regnum; + + result = lpddr4_writectlconfigsf(pd, regvalues); + if (result == (uint32_t) CDN_EOK) { + + /* Iterate through CTL register numbers. */ + for (regnum = 0; regnum < LPDDR4_CTL_REG_COUNT; regnum++) { + /* Check if the user has requested update */ + if (regvalues->updatectlreg[regnum]) { + result = + lpddr4_writereg(pd, LPDDR4_CTL_REGS, regnum, + (uint32_t) (regvalues-> + denalictlreg + [regnum])); + } + } + } + return result; +} + +uint32_t lpddr4_writephyindepconfig(const lpddr4_privatedata * pd, + const lpddr4_reginitdata * regvalues) +{ + uint32_t result; + uint32_t regnum; + + result = lpddr4_writephyindepconfigsf(pd, regvalues); + if (result == (uint32_t) CDN_EOK) { + + /* Iterate through PHY Independent module register numbers. */ + for (regnum = 0; regnum < LPDDR4_PHY_INDEP_REG_COUNT; regnum++) { + /* Check if the user has requested update */ + if (regvalues->updatephyindepreg[regnum]) { + result = + lpddr4_writereg(pd, LPDDR4_PHY_INDEP_REGS, + regnum, + (uint32_t) (regvalues-> + denaliphyindepreg + [regnum])); + } + } + } + return result; +} + +uint32_t lpddr4_writephyconfig(const lpddr4_privatedata * pd, + const lpddr4_reginitdata * regvalues) +{ + uint32_t result; + uint32_t regnum; + + result = lpddr4_writephyconfigsf(pd, regvalues); + if (result == (uint32_t) CDN_EOK) { + + /* Iterate through PHY register numbers. */ + for (regnum = 0; regnum < LPDDR4_PHY_REG_COUNT; regnum++) { + /* Check if the user has requested update */ + if (regvalues->updatephyreg[regnum]) { + result = + lpddr4_writereg(pd, LPDDR4_PHY_REGS, regnum, + (uint32_t) (regvalues-> + denaliphyreg + [regnum])); + } + } + } + return result; +} + +uint32_t lpddr4_readctlconfig(const lpddr4_privatedata * pd, + lpddr4_reginitdata * regvalues) +{ + uint32_t result; + uint32_t regnum; + result = lpddr4_readctlconfigsf(pd, regvalues); + if (result == (uint32_t) CDN_EOK) { + /* Iterate through CTL register numbers. */ + for (regnum = 0; regnum < LPDDR4_CTL_REG_COUNT; regnum++) { + /* Check if the user has requested read (updateCtlReg=1) */ + if (regvalues->updatectlreg[regnum]) { + result = + lpddr4_readreg(pd, LPDDR4_CTL_REGS, regnum, + (uint32_t *) (®values-> + denalictlreg + [regnum])); + } + } + } + return result; +} + +uint32_t lpddr4_readphyindepconfig(const lpddr4_privatedata * pd, + lpddr4_reginitdata * regvalues) +{ + uint32_t result; + uint32_t regnum; + + result = lpddr4_readphyindepconfigsf(pd, regvalues); + if (result == (uint32_t) CDN_EOK) { + /* Iterate through PHY Independent module register numbers. */ + for (regnum = 0; regnum < LPDDR4_PHY_INDEP_REG_COUNT; regnum++) { + /* Check if the user has requested read (updateCtlReg=1) */ + if (regvalues->updatephyindepreg[regnum]) { + result = + lpddr4_readreg(pd, LPDDR4_PHY_INDEP_REGS, + regnum, + (uint32_t *) (®values-> + denaliphyindepreg + [regnum])); + } + } + } + return result; +} + +uint32_t lpddr4_readphyconfig(const lpddr4_privatedata * pd, + lpddr4_reginitdata * regvalues) +{ + uint32_t result; + uint32_t regnum; + + result = lpddr4_readphyconfigsf(pd, regvalues); + if (result == (uint32_t) CDN_EOK) { + /* Iterate through PHY register numbers. */ + for (regnum = 0; regnum < LPDDR4_PHY_REG_COUNT; regnum++) { + /* Check if the user has requested read (updateCtlReg=1) */ + if (regvalues->updatephyreg[regnum]) { + result = + lpddr4_readreg(pd, LPDDR4_PHY_REGS, regnum, + (uint32_t *) (®values-> + denaliphyreg + [regnum])); + } + } + } + return result; +} + +uint32_t lpddr4_getctlinterruptmask(const lpddr4_privatedata * pd, + uint64_t * mask) +{ + uint32_t result = 0U; + uint64_t lowermask = 0U; + + result = lpddr4_getctlinterruptmasksf(pd, mask); + if (result == (uint32_t) CDN_EOK) { + lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase; + /* Reading the lower mask register */ + lowermask = + (uint64_t) (CPS_FLD_READ + (LPDDR4__INT_MASK_0__FLD, + CPS_REG_READ(& + (ctlregbase-> + LPDDR4__INT_MASK_0__REG)))); + /* Reading the upper mask register */ + *mask = + (uint64_t) (CPS_FLD_READ + (LPDDR4__INT_MASK_1__FLD, + CPS_REG_READ(& + (ctlregbase-> + LPDDR4__INT_MASK_1__REG)))); + /* Concatenate both register informations */ + *mask = (uint64_t) ((*mask << WORD_SHIFT) | lowermask); + } + return result; +} + +uint32_t lpddr4_setctlinterruptmask(const lpddr4_privatedata * pd, + const uint64_t * mask) +{ + uint32_t result; + uint32_t regval = 0; + const uint64_t ui64one = 1ULL; + const uint32_t ui32irqcount = (uint32_t) LPDDR4_LOR_BITS + 1U; + + result = lpddr4_setctlinterruptmasksf(pd, mask); + if ((result == (uint32_t) CDN_EOK) && (ui32irqcount < 64U)) { + /* Return if the user given value is higher than the field width */ + if (*mask >= (ui64one << ui32irqcount)) { + result = EINVAL; + } + } + if (result == (uint32_t) CDN_EOK) { + lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase; + + /* Extracting the lower 32 bits and writing to lower mask register */ + regval = (uint32_t) (*mask & WORD_MASK); + regval = + CPS_FLD_WRITE(LPDDR4__INT_MASK_0__FLD, + CPS_REG_READ(& + (ctlregbase-> + LPDDR4__INT_MASK_0__REG)), + regval); + CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_MASK_0__REG), regval); + + /* Extracting the upper 32 bits and writing to upper mask register */ + regval = (uint32_t) ((*mask >> WORD_SHIFT) & WORD_MASK); + regval = + CPS_FLD_WRITE(LPDDR4__INT_MASK_1__FLD, + CPS_REG_READ(& + (ctlregbase-> + LPDDR4__INT_MASK_1__REG)), + regval); + CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_MASK_1__REG), regval); + } + return result; +} + +uint32_t lpddr4_checkctlinterrupt(const lpddr4_privatedata * pd, + lpddr4_ctlinterrupt intr, bool * irqstatus) +{ + uint32_t result; + uint32_t ctlirqstatus = 0; + uint32_t fieldshift = 0; + + /* NOTE:This function assume irq status is mentioned in NOT more than 2 registers. + * Value of 'interrupt' should be less than 64 */ + result = lpddr4_checkctlinterruptsf(pd, intr, irqstatus); + if (result == (uint32_t) CDN_EOK) { + lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase; + + if ((uint32_t) intr >= WORD_SHIFT) { + ctlirqstatus = + CPS_REG_READ(& + (ctlregbase-> + LPDDR4__INT_STATUS_1__REG)); + /* Reduce the shift value as we are considering upper register */ + fieldshift = (uint32_t) intr - ((uint32_t) WORD_SHIFT); + } else { + ctlirqstatus = + CPS_REG_READ(& + (ctlregbase-> + LPDDR4__INT_STATUS_0__REG)); + /* The shift value remains same for lower interrupt register */ + fieldshift = (uint32_t) intr; + } + + /* MISRA compliance (Shifting operation) check */ + if (fieldshift < WORD_SHIFT) { + if (((ctlirqstatus >> fieldshift) & BIT_MASK) > 0U) { + *irqstatus = true; + } else { + *irqstatus = false; + } + } + } + return result; +} + +uint32_t lpddr4_ackctlinterrupt(const lpddr4_privatedata * pd, + lpddr4_ctlinterrupt intr) +{ + uint32_t result = 0; + uint32_t regval = 0; + uint32_t localinterrupt = (uint32_t) intr; + + /* NOTE:This function assume irq status is mentioned in NOT more than 2 registers. + * Value of 'interrupt' should be less than 64 */ + result = lpddr4_ackctlinterruptsf(pd, intr); + if (result == (uint32_t) CDN_EOK) { + lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase; + + /* Check if the requested bit is in upper register */ + if (localinterrupt > WORD_SHIFT) { + localinterrupt = + (localinterrupt - (uint32_t) WORD_SHIFT); + regval = ((uint32_t) BIT_MASK << localinterrupt); + CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_1__REG), + regval); + } else { + regval = ((uint32_t) BIT_MASK << localinterrupt); + CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_0__REG), + regval); + } + } + + return result; +} + +uint32_t lpddr4_getphyindepinterruptmask(const lpddr4_privatedata * pd, + uint32_t * mask) +{ + uint32_t result; + + result = lpddr4_getphyindepinterruptmsf(pd, mask); + if (result == (uint32_t) CDN_EOK) { + lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase; + /* Reading mask register */ + *mask = + CPS_FLD_READ(LPDDR4__PI_INT_MASK__FLD, + CPS_REG_READ(& + (ctlregbase-> + LPDDR4__PI_INT_MASK__REG))); + } + return result; +} + +uint32_t lpddr4_setphyindepinterruptmask(const lpddr4_privatedata * pd, + const uint32_t * mask) +{ + uint32_t result; + uint32_t regval = 0; + const uint32_t ui32irqcount = + (uint32_t) LPDDR4_PHY_INDEP_DLL_LOCK_STATE_CHANGE_BIT + 1U; + + result = lpddr4_setphyindepinterruptmsf(pd, mask); + if ((result == (uint32_t) CDN_EOK) && (ui32irqcount < WORD_SHIFT)) { + /* Return if the user given value is higher than the field width */ + if (*mask >= (1U << ui32irqcount)) { + result = EINVAL; + } + } + if (result == (uint32_t) CDN_EOK) { + lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase; + + /* Writing to the user requested interrupt mask */ + regval = + CPS_FLD_WRITE(LPDDR4__PI_INT_MASK__FLD, + CPS_REG_READ(& + (ctlregbase-> + LPDDR4__PI_INT_MASK__REG)), + *mask); + CPS_REG_WRITE(&(ctlregbase->LPDDR4__PI_INT_MASK__REG), regval); + } + return result; +} + +uint32_t lpddr4_checkphyindepinterrupt(const lpddr4_privatedata * pd, + lpddr4_phyindepinterrupt intr, + bool * irqstatus) +{ + uint32_t result = 0; + uint32_t phyindepirqstatus = 0; + + result = lpddr4_checkphyindepinterrupsf(pd, intr, irqstatus); + /* Confirming that the value of interrupt is less than register width */ + if ((result == (uint32_t) CDN_EOK) && ((uint32_t) intr < WORD_SHIFT)) { + lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase; + + /* Reading the requested bit to check interrupt status */ + phyindepirqstatus = + CPS_REG_READ(&(ctlregbase->LPDDR4__PI_INT_STATUS__REG)); + *irqstatus = + (((phyindepirqstatus >> (uint32_t) intr) & BIT_MASK) > 0U); + } + return result; +} + +uint32_t lpddr4_ackphyindepinterrupt(const lpddr4_privatedata * pd, + lpddr4_phyindepinterrupt intr) +{ + uint32_t result = 0U; + uint32_t regval = 0U; + uint32_t ui32shiftinterrupt = (uint32_t) intr; + + result = lpddr4_ackphyindepinterruptsf(pd, intr); + /* Confirming that the value of interrupt is less than register width */ + if ((result == (uint32_t) CDN_EOK) && (ui32shiftinterrupt < WORD_SHIFT)) { + lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase; + + /* Write 1 to the requested bit to ACk the interrupt */ + regval = ((uint32_t) BIT_MASK << ui32shiftinterrupt); + CPS_REG_WRITE(&(ctlregbase->LPDDR4__PI_INT_ACK__REG), regval); + } + + return result; +} + +/* Check for caTrainingError */ +static void lpddr4_checkcatrainingerror(lpddr4_ctlregs * ctlregbase, + lpddr4_debuginfo * debuginfo, + bool * errfoundptr) +{ + + uint32_t regval; + uint32_t errbitmask = 0U; + uint32_t snum; + volatile uint32_t *regaddress; + + regaddress = + (volatile uint32_t + *)(&(ctlregbase->LPDDR4__PHY_ADR_CALVL_OBS1_0__REG)); + errbitmask = (CA_TRAIN_RL) | (NIBBLE_MASK); + /* PHY_ADR_CALVL_OBS1[4] – Right found + PHY_ADR_CALVL_OBS1[5] – left found + both the above fields should be high and below field should be zero. + PHY_ADR_CALVL_OBS1[3:0] – calvl_state + */ + for (snum = 0U; snum < ASLICE_NUM; snum++) { + regval = CPS_REG_READ(regaddress); + if ((regval & errbitmask) != CA_TRAIN_RL) { + debuginfo->catraingerror = true; + *errfoundptr = true; + } + regaddress = + lpddr4_addoffset(regaddress, (uint32_t) SLICE_WIDTH); + } +} + +/* Check for wrLvlError */ +static void lpddr4_checkwrlvlerror(lpddr4_ctlregs * ctlregbase, + lpddr4_debuginfo * debuginfo, + bool * errfoundptr) +{ + + uint32_t regval; + uint32_t errbitmask = 0U; + uint32_t snum; + volatile uint32_t *regaddress; + + regaddress = + (volatile uint32_t + *)(&(ctlregbase->LPDDR4__PHY_WRLVL_ERROR_OBS_0__REG)); + /* PHY_WRLVL_ERROR_OBS_X[1:0] should be zero */ + errbitmask = (BIT_MASK << 1) | (BIT_MASK); + for (snum = 0U; snum < DSLICE_NUM; snum++) { + regval = CPS_REG_READ(regaddress); + if ((regval & errbitmask) != 0U) { + debuginfo->wrlvlerror = true; + *errfoundptr = true; + } + regaddress = + lpddr4_addoffset(regaddress, (uint32_t) SLICE_WIDTH); + } +} + +/* Check for GateLvlError */ +static void lpddr4_checkgatelvlerror(lpddr4_ctlregs * ctlregbase, + lpddr4_debuginfo * debuginfo, + bool * errfoundptr) +{ + + uint32_t regval; + uint32_t errbitmask = 0U; + uint32_t snum; + volatile uint32_t *regaddress; + + regaddress = + (volatile uint32_t + *)(&(ctlregbase->LPDDR4__PHY_GTLVL_STATUS_OBS_0__REG)); + /* PHY_GTLVL_STATUS_OBS[6] – gate_level min error + * PHY_GTLVL_STATUS_OBS[7] – gate_level max error + * All the above bit fields should be zero */ + errbitmask = GATE_LVL_ERROR_FIELDS; + for (snum = 0U; snum < DSLICE_NUM; snum++) { + regval = CPS_REG_READ(regaddress); + if ((regval & errbitmask) != 0U) { + debuginfo->gatelvlerror = true; + *errfoundptr = true; + } + regaddress = + lpddr4_addoffset(regaddress, (uint32_t) SLICE_WIDTH); + } +} + +/* Check for ReadLvlError */ +static void lpddr4_checkreadlvlerror(lpddr4_ctlregs * ctlregbase, + lpddr4_debuginfo * debuginfo, + bool * errfoundptr) +{ + + uint32_t regval; + uint32_t errbitmask = 0U; + uint32_t snum; + volatile uint32_t *regaddress; + + regaddress = + (volatile uint32_t + *)(&(ctlregbase->LPDDR4__PHY_RDLVL_STATUS_OBS_0__REG)); + /* PHY_RDLVL_STATUS_OBS[23:16] – failed bits : should be zero. + PHY_RDLVL_STATUS_OBS[31:28] – rdlvl_state : should be zero */ + errbitmask = READ_LVL_ERROR_FIELDS; + for (snum = 0U; snum < DSLICE_NUM; snum++) { + regval = CPS_REG_READ(regaddress); + if ((regval & errbitmask) != 0U) { + debuginfo->readlvlerror = true; + *errfoundptr = true; + } + regaddress = + lpddr4_addoffset(regaddress, (uint32_t) SLICE_WIDTH); + } +} + +/* Check for DqTrainingError */ +static void lpddr4_checkdqtrainingerror(lpddr4_ctlregs * ctlregbase, + lpddr4_debuginfo * debuginfo, + bool * errfoundptr) +{ + + uint32_t regval; + uint32_t errbitmask = 0U; + uint32_t snum; + volatile uint32_t *regaddress; + + regaddress = + (volatile uint32_t + *)(&(ctlregbase->LPDDR4__PHY_WDQLVL_STATUS_OBS_0__REG)); + /* PHY_WDQLVL_STATUS_OBS[26:18] should all be zero. */ + errbitmask = DQ_LVL_STATUS; + for (snum = 0U; snum < DSLICE_NUM; snum++) { + regval = CPS_REG_READ(regaddress); + if ((regval & errbitmask) != 0U) { + debuginfo->dqtrainingerror = true; + *errfoundptr = true; + } + regaddress = + lpddr4_addoffset(regaddress, (uint32_t) SLICE_WIDTH); + } +} + +/** + * Internal Function:For checking errors in training/levelling sequence. + * @param[in] pD Driver state info specific to this instance. + * @param[in] debugInfo pointer to debug information. + * @param[out] errFoundPtr pointer to return if error found. + * @return CDN_EOK on success (Interrupt status high). + * @return EINVAL checking or unmasking was not successful. + */ +static bool lpddr4_checklvlerrors(const lpddr4_privatedata * pd, + lpddr4_debuginfo * debuginfo, bool errfound) +{ + + bool localerrfound = errfound; + + lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase; + + if (localerrfound == false) { + /* Check for ca training error */ + lpddr4_checkcatrainingerror(ctlregbase, debuginfo, + &localerrfound); + } + + if (localerrfound == false) { + /* Check for Write leveling error */ + lpddr4_checkwrlvlerror(ctlregbase, debuginfo, &localerrfound); + } + + if (localerrfound == false) { + /* Check for Gate leveling error */ + lpddr4_checkgatelvlerror(ctlregbase, debuginfo, &localerrfound); + } + + if (localerrfound == false) { + /* Check for Read leveling error */ + lpddr4_checkreadlvlerror(ctlregbase, debuginfo, &localerrfound); + } + + if (localerrfound == false) { + /* Check for DQ training error */ + lpddr4_checkdqtrainingerror(ctlregbase, debuginfo, + &localerrfound); + } + return localerrfound; +} + +static bool lpddr4_seterror(volatile uint32_t * reg, uint32_t errbitmask, + bool * errfoundptr, const uint32_t errorinfobits) +{ + + uint32_t regval = 0U; + + /* Read the respective observation register */ + regval = CPS_REG_READ(reg); + /* Compare the error bit values */ + if ((regval & errbitmask) != errorinfobits) { + *errfoundptr = true; + } + return *errfoundptr; +} + +static void lpddr4_seterrors(lpddr4_ctlregs * ctlregbase, + lpddr4_debuginfo * debuginfo, bool * errfoundptr) +{ + + uint32_t errbitmask = (BIT_MASK << 0x1U) | (BIT_MASK); + /* Check PLL observation registers for PLL lock errors */ + + debuginfo->pllerror = + lpddr4_seterror(&(ctlregbase->LPDDR4__PHY_PLL_OBS_0__REG), + errbitmask, errfoundptr, PLL_READY); + if (*errfoundptr == false) { + debuginfo->pllerror = + lpddr4_seterror(&(ctlregbase->LPDDR4__PHY_PLL_OBS_1__REG), + errbitmask, errfoundptr, PLL_READY); + } + + /* Check for IO Calibration errors */ + if (*errfoundptr == false) { + debuginfo->iocaliberror = + lpddr4_seterror(& + (ctlregbase-> + LPDDR4__PHY_CAL_RESULT_OBS_0__REG), + IO_CALIB_DONE, errfoundptr, IO_CALIB_DONE); + } + if (*errfoundptr == false) { + debuginfo->iocaliberror = + lpddr4_seterror(& + (ctlregbase-> + LPDDR4__PHY_CAL_RESULT2_OBS_0__REG), + IO_CALIB_DONE, errfoundptr, IO_CALIB_DONE); + } + if (*errfoundptr == false) { + debuginfo->iocaliberror = + lpddr4_seterror(& + (ctlregbase-> + LPDDR4__PHY_CAL_RESULT3_OBS_0__REG), + IO_CALIB_FIELD, errfoundptr, + IO_CALIB_STATE); + } +} + +static void lpddr4_setphysnapsettings(lpddr4_ctlregs * ctlregbase, + const bool errorfound) +{ + + uint32_t snum = 0U; + volatile uint32_t *regaddress; + uint32_t regval = 0U; + + /* Setting SC_PHY_SNAP_OBS_REGS_x to get a snapshot */ + if (errorfound == false) { + regaddress = + (volatile uint32_t + *)(&(ctlregbase->LPDDR4__SC_PHY_SNAP_OBS_REGS_0__REG)); + /* Iterate through each PHY Data Slice */ + for (snum = 0U; snum < DSLICE_NUM; snum++) { + regval = + CPS_FLD_SET(LPDDR4__SC_PHY_SNAP_OBS_REGS_0__FLD, + CPS_REG_READ(regaddress)); + CPS_REG_WRITE(regaddress, regval); + regaddress = + lpddr4_addoffset(regaddress, + (uint32_t) SLICE_WIDTH); + } + } +} + +static void lpddr4_setphyadrsnapsettings(lpddr4_ctlregs * ctlregbase, + const bool errorfound) +{ + + uint32_t snum = 0U; + volatile uint32_t *regaddress; + uint32_t regval = 0U; + + /* Setting SC_PHY ADR_SNAP_OBS_REGS_x to get a snapshot */ + if (errorfound == false) { + regaddress = + (volatile uint32_t + *)(&(ctlregbase->LPDDR4__SC_PHY_ADR_SNAP_OBS_REGS_0__REG)); + /* Iterate through each PHY Address Slice */ + for (snum = 0U; snum < ASLICE_NUM; snum++) { + regval = + CPS_FLD_SET(LPDDR4__SC_PHY_ADR_SNAP_OBS_REGS_0__FLD, + CPS_REG_READ(regaddress)); + CPS_REG_WRITE(regaddress, regval); + regaddress = + lpddr4_addoffset(regaddress, + (uint32_t) SLICE_WIDTH); + } + } +} + +static void lpddr4_setsettings(lpddr4_ctlregs * ctlregbase, + const bool errorfound) +{ + + /* Calling functions to enable snap shots of OBS registers */ + lpddr4_setphysnapsettings(ctlregbase, errorfound); + lpddr4_setphyadrsnapsettings(ctlregbase, errorfound); +} + +static void lpddr4_setrxoffseterror(lpddr4_ctlregs * ctlregbase, + lpddr4_debuginfo * debuginfo, + bool * errorfound) +{ + + volatile uint32_t *regaddress; + uint32_t snum = 0U; + uint32_t errbitmask = 0U; + uint32_t regval = 0U; + + /* Check for rxOffsetError */ + if (*errorfound == false) { + regaddress = + (volatile uint32_t + *)(&(ctlregbase->LPDDR4__PHY_RX_CAL_LOCK_OBS_0__REG)); + errbitmask = (RX_CAL_DONE) | (NIBBLE_MASK); + /* PHY_RX_CAL_LOCK_OBS_x[4] – RX_CAL_DONE : should be high + phy_rx_cal_lock_obs_x[3:0] – RX_CAL_STATE : should be zero. */ + for (snum = 0U; snum < DSLICE_NUM; snum++) { + regval = + CPS_FLD_READ(LPDDR4__PHY_RX_CAL_LOCK_OBS_0__FLD, + CPS_REG_READ(regaddress)); + if ((regval & errbitmask) != RX_CAL_DONE) { + debuginfo->rxoffseterror = true; + *errorfound = true; + } + regaddress = + lpddr4_addoffset(regaddress, + (uint32_t) SLICE_WIDTH); + } + } +} + +uint32_t lpddr4_getdebuginitinfo(const lpddr4_privatedata * pd, + lpddr4_debuginfo * debuginfo) +{ + + uint32_t result = 0U; + bool errorfound = false; + + /* Calling Sanity Function to verify the input variables */ + result = lpddr4_getdebuginitinfosf(pd, debuginfo); + if (result == (uint32_t) CDN_EOK) { + + lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase; + lpddr4_seterrors(ctlregbase, debuginfo, &errorfound); + /* Function to setup Snap for OBS registers */ + lpddr4_setsettings(ctlregbase, errorfound); + /* Function to check for Rx offset error */ + lpddr4_setrxoffseterror(ctlregbase, debuginfo, &errorfound); + /* Function Check various levelling errors */ + errorfound = lpddr4_checklvlerrors(pd, debuginfo, errorfound); + } + + if (errorfound == true) { + result = (uint32_t) EPROTO; + } + + return result; +} + +static void readpdwakeup(const lpddr4_ctlfspnum * fspnum, + lpddr4_ctlregs * ctlregbase, uint32_t * cycles) +{ + + /* Read the appropriate register, based on user given frequency. */ + if (*fspnum == LPDDR4_FSP_0) { + *cycles = + CPS_FLD_READ(LPDDR4__LPI_PD_WAKEUP_F0__FLD, + CPS_REG_READ(& + (ctlregbase-> + LPDDR4__LPI_PD_WAKEUP_F0__REG))); + } else if (*fspnum == LPDDR4_FSP_1) { + *cycles = + CPS_FLD_READ(LPDDR4__LPI_PD_WAKEUP_F1__FLD, + CPS_REG_READ(& + (ctlregbase-> + LPDDR4__LPI_PD_WAKEUP_F1__REG))); + } else { + /* Default register (sanity function already confirmed the variable value) */ + *cycles = + CPS_FLD_READ(LPDDR4__LPI_PD_WAKEUP_F2__FLD, + CPS_REG_READ(& + (ctlregbase-> + LPDDR4__LPI_PD_WAKEUP_F2__REG))); + } +} + +static void readsrshortwakeup(const lpddr4_ctlfspnum * fspnum, + lpddr4_ctlregs * ctlregbase, uint32_t * cycles) +{ + + /* Read the appropriate register, based on user given frequency. */ + if (*fspnum == LPDDR4_FSP_0) { + *cycles = + CPS_FLD_READ(LPDDR4__LPI_SR_SHORT_WAKEUP_F0__FLD, + CPS_REG_READ(& + (ctlregbase-> + LPDDR4__LPI_SR_SHORT_WAKEUP_F0__REG))); + } else if (*fspnum == LPDDR4_FSP_1) { + *cycles = + CPS_FLD_READ(LPDDR4__LPI_SR_SHORT_WAKEUP_F1__FLD, + CPS_REG_READ(& + (ctlregbase-> + LPDDR4__LPI_SR_SHORT_WAKEUP_F1__REG))); + } else { + /* Default register (sanity function already confirmed the variable value) */ + *cycles = + CPS_FLD_READ(LPDDR4__LPI_SR_SHORT_WAKEUP_F2__FLD, + CPS_REG_READ(& + (ctlregbase-> + LPDDR4__LPI_SR_SHORT_WAKEUP_F2__REG))); + } +} + +static void readsrlongwakeup(const lpddr4_ctlfspnum * fspnum, + lpddr4_ctlregs * ctlregbase, uint32_t * cycles) +{ + + /* Read the appropriate register, based on user given frequency. */ + if (*fspnum == LPDDR4_FSP_0) { + *cycles = + CPS_FLD_READ(LPDDR4__LPI_SR_LONG_WAKEUP_F0__FLD, + CPS_REG_READ(& + (ctlregbase-> + LPDDR4__LPI_SR_LONG_WAKEUP_F0__REG))); + } else if (*fspnum == LPDDR4_FSP_1) { + *cycles = + CPS_FLD_READ(LPDDR4__LPI_SR_LONG_WAKEUP_F1__FLD, + CPS_REG_READ(& + (ctlregbase-> + LPDDR4__LPI_SR_LONG_WAKEUP_F1__REG))); + } else { + /* Default register (sanity function already confirmed the variable value) */ + *cycles = + CPS_FLD_READ(LPDDR4__LPI_SR_LONG_WAKEUP_F2__FLD, + CPS_REG_READ(& + (ctlregbase-> + LPDDR4__LPI_SR_LONG_WAKEUP_F2__REG))); + } +} + +static void readsrlonggatewakeup(const lpddr4_ctlfspnum * fspnum, + lpddr4_ctlregs * ctlregbase, uint32_t * cycles) +{ + + /* Read the appropriate register, based on user given frequency. */ + if (*fspnum == LPDDR4_FSP_0) { + *cycles = + CPS_FLD_READ(LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0__FLD, + CPS_REG_READ(& + (ctlregbase-> + LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0__REG))); + } else if (*fspnum == LPDDR4_FSP_1) { + *cycles = + CPS_FLD_READ(LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1__FLD, + CPS_REG_READ(& + (ctlregbase-> + LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1__REG))); + } else { + /* Default register (sanity function already confirmed the variable value) */ + *cycles = + CPS_FLD_READ(LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2__FLD, + CPS_REG_READ(& + (ctlregbase-> + LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2__REG))); + } +} + +static void readsrdpshortwakeup(const lpddr4_ctlfspnum * fspnum, + lpddr4_ctlregs * ctlregbase, uint32_t * cycles) +{ + + /* Read the appropriate register, based on user given frequency. */ + if (*fspnum == LPDDR4_FSP_0) { + *cycles = + CPS_FLD_READ(LPDDR4__LPI_SRPD_SHORT_WAKEUP_F0__FLD, + CPS_REG_READ(& + (ctlregbase-> + LPDDR4__LPI_SRPD_SHORT_WAKEUP_F0__REG))); + } else if (*fspnum == LPDDR4_FSP_1) { + *cycles = + CPS_FLD_READ(LPDDR4__LPI_SRPD_SHORT_WAKEUP_F1__FLD, + CPS_REG_READ(& + (ctlregbase-> + LPDDR4__LPI_SRPD_SHORT_WAKEUP_F1__REG))); + } else { + /* Default register (sanity function already confirmed the variable value) */ + *cycles = + CPS_FLD_READ(LPDDR4__LPI_SRPD_SHORT_WAKEUP_F2__FLD, + CPS_REG_READ(& + (ctlregbase-> + LPDDR4__LPI_SRPD_SHORT_WAKEUP_F2__REG))); + } +} + +static void readsrdplongwakeup(const lpddr4_ctlfspnum * fspnum, + lpddr4_ctlregs * ctlregbase, uint32_t * cycles) +{ + + /* Read the appropriate register, based on user given frequency. */ + if (*fspnum == LPDDR4_FSP_0) { + *cycles = + CPS_FLD_READ(LPDDR4__LPI_SRPD_LONG_WAKEUP_F0__FLD, + CPS_REG_READ(& + (ctlregbase-> + LPDDR4__LPI_SRPD_LONG_WAKEUP_F0__REG))); + } else if (*fspnum == LPDDR4_FSP_1) { + *cycles = + CPS_FLD_READ(LPDDR4__LPI_SRPD_LONG_WAKEUP_F1__FLD, + CPS_REG_READ(& + (ctlregbase-> + LPDDR4__LPI_SRPD_LONG_WAKEUP_F1__REG))); + } else { + /* Default register (sanity function already confirmed the variable value) */ + *cycles = + CPS_FLD_READ(LPDDR4__LPI_SRPD_LONG_WAKEUP_F2__FLD, + CPS_REG_READ(& + (ctlregbase-> + LPDDR4__LPI_SRPD_LONG_WAKEUP_F2__REG))); + } +} + +static void readsrdplonggatewakeup(const lpddr4_ctlfspnum * fspnum, + lpddr4_ctlregs * ctlregbase, + uint32_t * cycles) +{ + + /* Read the appropriate register, based on user given frequency. */ + if (*fspnum == LPDDR4_FSP_0) { + *cycles = + CPS_FLD_READ + (LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0__FLD, + CPS_REG_READ(& + (ctlregbase-> + LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0__REG))); + } else if (*fspnum == LPDDR4_FSP_1) { + *cycles = + CPS_FLD_READ + (LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1__FLD, + CPS_REG_READ(& + (ctlregbase-> + LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1__REG))); + } else { + /* Default register (sanity function already confirmed the variable value) */ + *cycles = + CPS_FLD_READ + (LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2__FLD, + CPS_REG_READ(& + (ctlregbase-> + LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2__REG))); + } + +} + +static void lpddr4_readlpiwakeuptime(lpddr4_ctlregs * ctlregbase, + const lpddr4_lpiwakeupparam * + lpiwakeupparam, + const lpddr4_ctlfspnum * fspnum, + uint32_t * cycles) +{ + + /* Iterate through each of the Wake up parameter type */ + if (*lpiwakeupparam == LPDDR4_LPI_PD_WAKEUP_FN) { + /* Calling appropriate function for register read */ + readpdwakeup(fspnum, ctlregbase, cycles); + } else if (*lpiwakeupparam == LPDDR4_LPI_SR_SHORT_WAKEUP_FN) { + readsrshortwakeup(fspnum, ctlregbase, cycles); + } else if (*lpiwakeupparam == LPDDR4_LPI_SR_LONG_WAKEUP_FN) { + readsrlongwakeup(fspnum, ctlregbase, cycles); + } else if (*lpiwakeupparam == LPDDR4_LPI_SR_LONG_MCCLK_GATE_WAKEUP_FN) { + readsrlonggatewakeup(fspnum, ctlregbase, cycles); + } else if (*lpiwakeupparam == LPDDR4_LPI_SRPD_SHORT_WAKEUP_FN) { + readsrdpshortwakeup(fspnum, ctlregbase, cycles); + } else if (*lpiwakeupparam == LPDDR4_LPI_SRPD_LONG_WAKEUP_FN) { + readsrdplongwakeup(fspnum, ctlregbase, cycles); + } else { + /* Default function (sanity function already confirmed the variable value) */ + readsrdplonggatewakeup(fspnum, ctlregbase, cycles); + } +} + +uint32_t lpddr4_getlpiwakeuptime(const lpddr4_privatedata * pd, + const lpddr4_lpiwakeupparam * lpiwakeupparam, + const lpddr4_ctlfspnum * fspnum, + uint32_t * cycles) +{ + + uint32_t result = 0U; + + /* Calling Sanity Function to verify the input variables */ + result = lpddr4_getlpiwakeuptimesf(pd, lpiwakeupparam, fspnum, cycles); + if (result == (uint32_t) CDN_EOK) { + lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase; + lpddr4_readlpiwakeuptime(ctlregbase, lpiwakeupparam, fspnum, + cycles); + } + return result; +} + +static void writepdwakeup(const lpddr4_ctlfspnum * fspnum, + lpddr4_ctlregs * ctlregbase, const uint32_t * cycles) +{ + + uint32_t regval = 0U; + /* Write to appropriate register ,based on user given frequency. */ + if (*fspnum == LPDDR4_FSP_0) { + regval = + CPS_FLD_WRITE(LPDDR4__LPI_PD_WAKEUP_F0__FLD, + CPS_REG_READ(& + (ctlregbase-> + LPDDR4__LPI_PD_WAKEUP_F0__REG)), + *cycles); + CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_PD_WAKEUP_F0__REG), + regval); + } else if (*fspnum == LPDDR4_FSP_1) { + regval = + CPS_FLD_WRITE(LPDDR4__LPI_PD_WAKEUP_F1__FLD, + CPS_REG_READ(& + (ctlregbase-> + LPDDR4__LPI_PD_WAKEUP_F1__REG)), + *cycles); + CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_PD_WAKEUP_F1__REG), + regval); + } else { + /* Default register (sanity function already confirmed the variable value) */ + regval = + CPS_FLD_WRITE(LPDDR4__LPI_PD_WAKEUP_F2__FLD, + CPS_REG_READ(& + (ctlregbase-> + LPDDR4__LPI_PD_WAKEUP_F2__REG)), + *cycles); + CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_PD_WAKEUP_F2__REG), + regval); + } +} + +static void writesrshortwakeup(const lpddr4_ctlfspnum * fspnum, + lpddr4_ctlregs * ctlregbase, + const uint32_t * cycles) +{ + + uint32_t regval = 0U; + /* Write to appropriate register ,based on user given frequency. */ + if (*fspnum == LPDDR4_FSP_0) { + regval = + CPS_FLD_WRITE(LPDDR4__LPI_SR_SHORT_WAKEUP_F0__FLD, + CPS_REG_READ(& + (ctlregbase-> + LPDDR4__LPI_SR_SHORT_WAKEUP_F0__REG)), + *cycles); + CPS_REG_WRITE(& + (ctlregbase->LPDDR4__LPI_SR_SHORT_WAKEUP_F0__REG), + regval); + } else if (*fspnum == LPDDR4_FSP_1) { + regval = + CPS_FLD_WRITE(LPDDR4__LPI_SR_SHORT_WAKEUP_F1__FLD, + CPS_REG_READ(& + (ctlregbase-> + LPDDR4__LPI_SR_SHORT_WAKEUP_F1__REG)), + *cycles); + CPS_REG_WRITE(& + (ctlregbase->LPDDR4__LPI_SR_SHORT_WAKEUP_F1__REG), + regval); + } else { + /* Default register (sanity function already confirmed the variable value) */ + regval = + CPS_FLD_WRITE(LPDDR4__LPI_SR_SHORT_WAKEUP_F2__FLD, + CPS_REG_READ(& + (ctlregbase-> + LPDDR4__LPI_SR_SHORT_WAKEUP_F2__REG)), + *cycles); + CPS_REG_WRITE(& + (ctlregbase->LPDDR4__LPI_SR_SHORT_WAKEUP_F2__REG), + regval); + } +} + +static void writesrlongwakeup(const lpddr4_ctlfspnum * fspnum, + lpddr4_ctlregs * ctlregbase, + const uint32_t * cycles) +{ + + uint32_t regval = 0U; + /* Write to appropriate register ,based on user given frequency. */ + if (*fspnum == LPDDR4_FSP_0) { + regval = + CPS_FLD_WRITE(LPDDR4__LPI_SR_LONG_WAKEUP_F0__FLD, + CPS_REG_READ(& + (ctlregbase-> + LPDDR4__LPI_SR_LONG_WAKEUP_F0__REG)), + *cycles); + CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SR_LONG_WAKEUP_F0__REG), + regval); + } else if (*fspnum == LPDDR4_FSP_1) { + regval = + CPS_FLD_WRITE(LPDDR4__LPI_SR_LONG_WAKEUP_F1__FLD, + CPS_REG_READ(& + (ctlregbase-> + LPDDR4__LPI_SR_LONG_WAKEUP_F1__REG)), + *cycles); + CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SR_LONG_WAKEUP_F1__REG), + regval); + } else { + /* Default register (sanity function already confirmed the variable value) */ + regval = + CPS_FLD_WRITE(LPDDR4__LPI_SR_LONG_WAKEUP_F2__FLD, + CPS_REG_READ(& + (ctlregbase-> + LPDDR4__LPI_SR_LONG_WAKEUP_F2__REG)), + *cycles); + CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SR_LONG_WAKEUP_F2__REG), + regval); + } +} + +static void writesrlonggatewakeup(const lpddr4_ctlfspnum * fspnum, + lpddr4_ctlregs * ctlregbase, + const uint32_t * cycles) +{ + + uint32_t regval = 0U; + /* Write to appropriate register ,based on user given frequency. */ + if (*fspnum == LPDDR4_FSP_0) { + regval = + CPS_FLD_WRITE(LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0__FLD, + CPS_REG_READ(& + (ctlregbase-> + LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0__REG)), + *cycles); + CPS_REG_WRITE(& + (ctlregbase-> + LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0__REG), + regval); + } else if (*fspnum == LPDDR4_FSP_1) { + regval = + CPS_FLD_WRITE(LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1__FLD, + CPS_REG_READ(& + (ctlregbase-> + LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1__REG)), + *cycles); + CPS_REG_WRITE(& + (ctlregbase-> + LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1__REG), + regval); + } else { + /* Default register (sanity function already confirmed the variable value) */ + regval = + CPS_FLD_WRITE(LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2__FLD, + CPS_REG_READ(& + (ctlregbase-> + LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2__REG)), + *cycles); + CPS_REG_WRITE(& + (ctlregbase-> + LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2__REG), + regval); + } +} + +static void writesrdpshortwakeup(const lpddr4_ctlfspnum * fspnum, + lpddr4_ctlregs * ctlregbase, + const uint32_t * cycles) +{ + + uint32_t regval = 0U; + /* Write to appropriate register ,based on user given frequency. */ + if (*fspnum == LPDDR4_FSP_0) { + regval = + CPS_FLD_WRITE(LPDDR4__LPI_SRPD_SHORT_WAKEUP_F0__FLD, + CPS_REG_READ(& + (ctlregbase-> + LPDDR4__LPI_SRPD_SHORT_WAKEUP_F0__REG)), + *cycles); + CPS_REG_WRITE(& + (ctlregbase-> + LPDDR4__LPI_SRPD_SHORT_WAKEUP_F0__REG), regval); + } else if (*fspnum == LPDDR4_FSP_1) { + regval = + CPS_FLD_WRITE(LPDDR4__LPI_SRPD_SHORT_WAKEUP_F1__FLD, + CPS_REG_READ(& + (ctlregbase-> + LPDDR4__LPI_SRPD_SHORT_WAKEUP_F1__REG)), + *cycles); + CPS_REG_WRITE(& + (ctlregbase-> + LPDDR4__LPI_SRPD_SHORT_WAKEUP_F1__REG), regval); + } else { + /* Default register (sanity function already confirmed the variable value) */ + regval = + CPS_FLD_WRITE(LPDDR4__LPI_SRPD_SHORT_WAKEUP_F2__FLD, + CPS_REG_READ(& + (ctlregbase-> + LPDDR4__LPI_SRPD_SHORT_WAKEUP_F2__REG)), + *cycles); + CPS_REG_WRITE(& + (ctlregbase-> + LPDDR4__LPI_SRPD_SHORT_WAKEUP_F2__REG), regval); + } +} + +static void writesrdplongwakeup(const lpddr4_ctlfspnum * fspnum, + lpddr4_ctlregs * ctlregbase, + const uint32_t * cycles) +{ + + uint32_t regval = 0U; + /* Write to appropriate register ,based on user given frequency. */ + if (*fspnum == LPDDR4_FSP_0) { + regval = + CPS_FLD_WRITE(LPDDR4__LPI_SRPD_LONG_WAKEUP_F0__FLD, + CPS_REG_READ(& + (ctlregbase-> + LPDDR4__LPI_SRPD_LONG_WAKEUP_F0__REG)), + *cycles); + CPS_REG_WRITE(& + (ctlregbase-> + LPDDR4__LPI_SRPD_LONG_WAKEUP_F0__REG), regval); + } else if (*fspnum == LPDDR4_FSP_1) { + regval = + CPS_FLD_WRITE(LPDDR4__LPI_SRPD_LONG_WAKEUP_F1__FLD, + CPS_REG_READ(& + (ctlregbase-> + LPDDR4__LPI_SRPD_LONG_WAKEUP_F1__REG)), + *cycles); + CPS_REG_WRITE(& + (ctlregbase-> + LPDDR4__LPI_SRPD_LONG_WAKEUP_F1__REG), regval); + } else { + /* Default register (sanity function already confirmed the variable value) */ + regval = + CPS_FLD_WRITE(LPDDR4__LPI_SRPD_LONG_WAKEUP_F2__FLD, + CPS_REG_READ(& + (ctlregbase-> + LPDDR4__LPI_SRPD_LONG_WAKEUP_F2__REG)), + *cycles); + CPS_REG_WRITE(& + (ctlregbase-> + LPDDR4__LPI_SRPD_LONG_WAKEUP_F2__REG), regval); + } +} + +static void writesrdplonggatewakeup(const lpddr4_ctlfspnum * fspnum, + lpddr4_ctlregs * ctlregbase, + const uint32_t * cycles) +{ + + uint32_t regval = 0U; + /* Write to appropriate register ,based on user given frequency. */ + if (*fspnum == LPDDR4_FSP_0) { + regval = + CPS_FLD_WRITE + (LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0__FLD, + CPS_REG_READ(& + (ctlregbase-> + LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0__REG)), + *cycles); + CPS_REG_WRITE(& + (ctlregbase-> + LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0__REG), + regval); + } else if (*fspnum == LPDDR4_FSP_1) { + regval = + CPS_FLD_WRITE + (LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1__FLD, + CPS_REG_READ(& + (ctlregbase-> + LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1__REG)), + *cycles); + CPS_REG_WRITE(& + (ctlregbase-> + LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1__REG), + regval); + } else { + /* Default register (sanity function already confirmed the variable value) */ + regval = + CPS_FLD_WRITE + (LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2__FLD, + CPS_REG_READ(& + (ctlregbase-> + LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2__REG)), + *cycles); + CPS_REG_WRITE(& + (ctlregbase-> + LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2__REG), + regval); + } +} + +static void lpddr4_writelpiwakeuptime(lpddr4_ctlregs * ctlregbase, + const lpddr4_lpiwakeupparam * + lpiwakeupparam, + const lpddr4_ctlfspnum * fspnum, + const uint32_t * cycles) +{ + + /* Iterate through each of the Wake up parameter type */ + if (*lpiwakeupparam == LPDDR4_LPI_PD_WAKEUP_FN) { + /* Calling appropriate function for register write */ + writepdwakeup(fspnum, ctlregbase, cycles); + } else if (*lpiwakeupparam == LPDDR4_LPI_SR_SHORT_WAKEUP_FN) { + writesrshortwakeup(fspnum, ctlregbase, cycles); + } else if (*lpiwakeupparam == LPDDR4_LPI_SR_LONG_WAKEUP_FN) { + writesrlongwakeup(fspnum, ctlregbase, cycles); + } else if (*lpiwakeupparam == LPDDR4_LPI_SR_LONG_MCCLK_GATE_WAKEUP_FN) { + writesrlonggatewakeup(fspnum, ctlregbase, cycles); + } else if (*lpiwakeupparam == LPDDR4_LPI_SRPD_SHORT_WAKEUP_FN) { + writesrdpshortwakeup(fspnum, ctlregbase, cycles); + } else if (*lpiwakeupparam == LPDDR4_LPI_SRPD_LONG_WAKEUP_FN) { + writesrdplongwakeup(fspnum, ctlregbase, cycles); + } else { + /* Default function (sanity function already confirmed the variable value) */ + writesrdplonggatewakeup(fspnum, ctlregbase, cycles); + } +} + +uint32_t lpddr4_setlpiwakeuptime(const lpddr4_privatedata * pd, + const lpddr4_lpiwakeupparam * lpiwakeupparam, + const lpddr4_ctlfspnum * fspnum, + const uint32_t * cycles) +{ + uint32_t result = 0U; + + /* Calling Sanity Function to verify the input variables */ + result = lpddr4_setlpiwakeuptimesf(pd, lpiwakeupparam, fspnum, cycles); + if (result == (uint32_t) CDN_EOK) { + /* Return if the user given value is higher than the field width */ + if (*cycles > NIBBLE_MASK) { + result = EINVAL; + } + } + if (result == (uint32_t) CDN_EOK) { + lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase; + lpddr4_writelpiwakeuptime(ctlregbase, lpiwakeupparam, fspnum, + cycles); + } + return result; +} + +uint32_t lpddr4_geteccenable(const lpddr4_privatedata * pd, + lpddr4_eccenable * eccparam) +{ + uint32_t result = 0U; + uint32_t fldval = 0U; + + /* Calling Sanity Function to verify the input variables */ + result = lpddr4_geteccenablesf(pd, eccparam); + if (result == (uint32_t) CDN_EOK) { + lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase; + + /* Reading the ECC_Enable field from the register. */ + fldval = + CPS_FLD_READ(LPDDR4__ECC_ENABLE__FLD, + CPS_REG_READ(& + (ctlregbase-> + LPDDR4__ECC_ENABLE__REG))); + switch (fldval) { + case 3: + *eccparam = LPDDR4_ECC_ERR_DETECT_CORRECT; + break; + case 2: + *eccparam = LPDDR4_ECC_ERR_DETECT; + break; + case 1: + *eccparam = LPDDR4_ECC_ENABLED; + break; + default: + /* Default ECC (Sanity function already confirmed the value to be in expected range.) */ + *eccparam = LPDDR4_ECC_DISABLED; + break; + } + } + return result; +} + +uint32_t lpddr4_seteccenable(const lpddr4_privatedata * pd, + const lpddr4_eccenable * eccparam) +{ + + uint32_t result = 0U; + uint32_t regval = 0U; + + /* Calling Sanity Function to verify the input variables */ + result = lpddr4_seteccenablesf(pd, eccparam); + if (result == (uint32_t) CDN_EOK) { + lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase; + + /* Updating the ECC_Enable field based on the user given value. */ + regval = + CPS_FLD_WRITE(LPDDR4__ECC_ENABLE__FLD, + CPS_REG_READ(& + (ctlregbase-> + LPDDR4__ECC_ENABLE__REG)), + *eccparam); + CPS_REG_WRITE(&(ctlregbase->LPDDR4__ECC_ENABLE__REG), regval); + } + return result; +} + +uint32_t lpddr4_getreducmode(const lpddr4_privatedata * pd, + lpddr4_reducmode * mode) +{ + uint32_t result = 0U; + + /* Calling Sanity Function to verify the input variables */ + result = lpddr4_getreducmodesf(pd, mode); + if (result == (uint32_t) CDN_EOK) { + lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase; + /* Read the value of reduc parameter. */ + if (CPS_FLD_READ + (LPDDR4__REDUC__FLD, + CPS_REG_READ(&(ctlregbase->LPDDR4__REDUC__REG))) == 0U) { + *mode = LPDDR4_REDUC_ON; + } else { + *mode = LPDDR4_REDUC_OFF; + } + } + return result; +} + +uint32_t lpddr4_setreducmode(const lpddr4_privatedata * pd, + const lpddr4_reducmode * mode) +{ + uint32_t result = 0U; + uint32_t regval = 0U; + + /* Calling Sanity Function to verify the input variables */ + result = lpddr4_setreducmodesf(pd, mode); + if (result == (uint32_t) CDN_EOK) { + lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase; + /* Setting to enable Half data path. */ + regval = + CPS_FLD_WRITE(LPDDR4__REDUC__FLD, + CPS_REG_READ(& + (ctlregbase-> + LPDDR4__REDUC__REG)), *mode); + CPS_REG_WRITE(&(ctlregbase->LPDDR4__REDUC__REG), regval); + } + return result; +} + +uint32_t lpddr4_getdbireadmode(const lpddr4_privatedata * pd, bool * on_off) +{ + + uint32_t result = 0U; + + /* Calling Sanity Function to verify the input variables */ + result = lpddr4_getdbireadmodesf(pd, on_off); + + if (result == (uint32_t) CDN_EOK) { + lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase; + /* Reading the field value from the register. */ + if (CPS_FLD_READ + (LPDDR4__RD_DBI_EN__FLD, + CPS_REG_READ(&(ctlregbase->LPDDR4__RD_DBI_EN__REG))) == + 0U) { + *on_off = false; + } else { + *on_off = true; + } + } + return result; +} + +uint32_t lpddr4_getdbiwritemode(const lpddr4_privatedata * pd, bool * on_off) +{ + + uint32_t result = 0U; + + /* Calling Sanity Function to verify the input variables */ + result = lpddr4_getdbireadmodesf(pd, on_off); + + if (result == (uint32_t) CDN_EOK) { + lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase; + /* Reading the field value from the register. */ + if (CPS_FLD_READ + (LPDDR4__WR_DBI_EN__FLD, + CPS_REG_READ(&(ctlregbase->LPDDR4__WR_DBI_EN__REG))) == + 0U) { + *on_off = false; + } else { + *on_off = true; + } + } + return result; +} + +uint32_t lpddr4_setdbimode(const lpddr4_privatedata * pd, + const lpddr4_dbimode * mode) +{ + + uint32_t result = 0U; + uint32_t regval = 0U; + + /* Calling Sanity Function to verify the input variables */ + result = lpddr4_setdbimodesf(pd, mode); + + if (result == (uint32_t) CDN_EOK) { + lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase; + + /* Updating the appropriate field value based on the user given mode */ + if (*mode == LPDDR4_DBI_RD_ON) { + regval = + CPS_FLD_WRITE(LPDDR4__RD_DBI_EN__FLD, + CPS_REG_READ(& + (ctlregbase-> + LPDDR4__RD_DBI_EN__REG)), + 1U); + } else if (*mode == LPDDR4_DBI_RD_OFF) { + regval = + CPS_FLD_WRITE(LPDDR4__RD_DBI_EN__FLD, + CPS_REG_READ(& + (ctlregbase-> + LPDDR4__RD_DBI_EN__REG)), + 0U); + } else if (*mode == LPDDR4_DBI_WR_ON) { + regval = + CPS_FLD_WRITE(LPDDR4__WR_DBI_EN__FLD, + CPS_REG_READ(& + (ctlregbase-> + LPDDR4__WR_DBI_EN__REG)), + 1U); + } else { + /* Default field (Sanity function already confirmed the value to be in expected range.) */ + regval = + CPS_FLD_WRITE(LPDDR4__WR_DBI_EN__FLD, + CPS_REG_READ(& + (ctlregbase-> + LPDDR4__WR_DBI_EN__REG)), + 0U); + } + CPS_REG_WRITE(&(ctlregbase->LPDDR4__RD_DBI_EN__REG), regval); + } + return result; +} + +uint32_t lpddr4_getrefreshrate(const lpddr4_privatedata * pd, + const lpddr4_ctlfspnum * fspnum, + uint32_t * cycles) +{ + uint32_t result = 0U; + + /* Calling Sanity Function to verify the input variables */ + result = lpddr4_getrefreshratesf(pd, fspnum, cycles); + + if (result == (uint32_t) CDN_EOK) { + lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase; + + /* Selecting the appropriate register for the user requested Frequency */ + switch (*fspnum) { + case LPDDR4_FSP_2: + *cycles = + CPS_FLD_READ(LPDDR4__TREF_F2__FLD, + CPS_REG_READ(& + (ctlregbase-> + LPDDR4__TREF_F2__REG))); + break; + case LPDDR4_FSP_1: + *cycles = + CPS_FLD_READ(LPDDR4__TREF_F1__FLD, + CPS_REG_READ(& + (ctlregbase-> + LPDDR4__TREF_F1__REG))); + break; + default: + /* FSP_0 is considered as the default (sanity check already confirmed it as valid FSP) */ + *cycles = + CPS_FLD_READ(LPDDR4__TREF_F0__FLD, + CPS_REG_READ(& + (ctlregbase-> + LPDDR4__TREF_F0__REG))); + break; + } + } + return result; +} + +uint32_t lpddr4_setrefreshrate(const lpddr4_privatedata * pd, + const lpddr4_ctlfspnum * fspnum, + const uint32_t * cycles) +{ + uint32_t result = 0U; + uint32_t regval = 0U; + + /* Calling Sanity Function to verify the input variables */ + result = lpddr4_setrefreshratesf(pd, fspnum, cycles); + + if (result == (uint32_t) CDN_EOK) { + lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase; + + /* Selecting the appropriate register for the user requested Frequency */ + switch (*fspnum) { + case LPDDR4_FSP_2: + regval = + CPS_FLD_WRITE(LPDDR4__TREF_F2__FLD, + CPS_REG_READ(& + (ctlregbase-> + LPDDR4__TREF_F2__REG)), + *cycles); + CPS_REG_WRITE(&(ctlregbase->LPDDR4__TREF_F2__REG), + regval); + break; + case LPDDR4_FSP_1: + regval = + CPS_FLD_WRITE(LPDDR4__TREF_F1__FLD, + CPS_REG_READ(& + (ctlregbase-> + LPDDR4__TREF_F1__REG)), + *cycles); + CPS_REG_WRITE(&(ctlregbase->LPDDR4__TREF_F1__REG), + regval); + break; + default: + /* FSP_0 is considered as the default (sanity check already confirmed it as valid FSP) */ + regval = + CPS_FLD_WRITE(LPDDR4__TREF_F0__FLD, + CPS_REG_READ(& + (ctlregbase-> + LPDDR4__TREF_F0__REG)), + *cycles); + CPS_REG_WRITE(&(ctlregbase->LPDDR4__TREF_F0__REG), + regval); + break; + } + } + return result; +} + +uint32_t lpddr4_refreshperchipselect(const lpddr4_privatedata * pd, + const uint32_t trefinterval) +{ + uint32_t result = 0U; + uint32_t regval = 0U; + + /* Calling Sanity Function to verify the input variables */ + result = lpddr4_refreshperchipselectsf(pd); + + if (result == (uint32_t) CDN_EOK) { + lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase; + /* Setting tref_interval parameter to enable/disable Refresh per chip select. */ + regval = + CPS_FLD_WRITE(LPDDR4__TREF_INTERVAL__FLD, + CPS_REG_READ(& + (ctlregbase-> + LPDDR4__TREF_INTERVAL__REG)), + trefinterval); + CPS_REG_WRITE(&(ctlregbase->LPDDR4__TREF_INTERVAL__REG), + regval); + } + return result; +} diff --git a/drivers/ram/k3-j721e/lpddr4_address_slice_0_macros.h b/drivers/ram/k3-j721e/lpddr4_address_slice_0_macros.h new file mode 100644 index 0000000..bc8059e --- /dev/null +++ b/drivers/ram/k3-j721e/lpddr4_address_slice_0_macros.h @@ -0,0 +1,825 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/********************************************************************** + * Copyright (C) 2012-2019 Cadence Design Systems, Inc. + * + * THIS FILE IS AUTOMATICALLY GENERATED, DO NOT EDIT + * + ********************************************************************** + */ + +#ifndef REG_LPDDR4_ADDRESS_SLICE_0_MACROS_H_ +#define REG_LPDDR4_ADDRESS_SLICE_0_MACROS_H_ + +#define LPDDR4__DENALI_PHY_1024_READ_MASK 0x000107FFU +#define LPDDR4__DENALI_PHY_1024_WRITE_MASK 0x000107FFU +#define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0_WIDTH 11U +#define LPDDR4__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0__REG DENALI_PHY_1024 +#define LPDDR4__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_BYPASS_OVERRIDE_0_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_BYPASS_OVERRIDE_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_BYPASS_OVERRIDE_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_BYPASS_OVERRIDE_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_BYPASS_OVERRIDE_0_WOSET 0U +#define LPDDR4__PHY_ADR_CLK_BYPASS_OVERRIDE_0__REG DENALI_PHY_1024 +#define LPDDR4__PHY_ADR_CLK_BYPASS_OVERRIDE_0__FLD LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_BYPASS_OVERRIDE_0 + +#define LPDDR4__DENALI_PHY_1024__SC_PHY_ADR_MANUAL_CLEAR_0_MASK 0x07000000U +#define LPDDR4__DENALI_PHY_1024__SC_PHY_ADR_MANUAL_CLEAR_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_1024__SC_PHY_ADR_MANUAL_CLEAR_0_WIDTH 3U +#define LPDDR4__SC_PHY_ADR_MANUAL_CLEAR_0__REG DENALI_PHY_1024 +#define LPDDR4__SC_PHY_ADR_MANUAL_CLEAR_0__FLD LPDDR4__DENALI_PHY_1024__SC_PHY_ADR_MANUAL_CLEAR_0 + +#define LPDDR4__DENALI_PHY_1025_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1025_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1025__PHY_ADR_LPBK_RESULT_OBS_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1025__PHY_ADR_LPBK_RESULT_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1025__PHY_ADR_LPBK_RESULT_OBS_0_WIDTH 32U +#define LPDDR4__PHY_ADR_LPBK_RESULT_OBS_0__REG DENALI_PHY_1025 +#define LPDDR4__PHY_ADR_LPBK_RESULT_OBS_0__FLD LPDDR4__DENALI_PHY_1025__PHY_ADR_LPBK_RESULT_OBS_0 + +#define LPDDR4__DENALI_PHY_1026_READ_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_1026_WRITE_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_1026__PHY_ADR_LPBK_ERROR_COUNT_OBS_0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_1026__PHY_ADR_LPBK_ERROR_COUNT_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1026__PHY_ADR_LPBK_ERROR_COUNT_OBS_0_WIDTH 16U +#define LPDDR4__PHY_ADR_LPBK_ERROR_COUNT_OBS_0__REG DENALI_PHY_1026 +#define LPDDR4__PHY_ADR_LPBK_ERROR_COUNT_OBS_0__FLD LPDDR4__DENALI_PHY_1026__PHY_ADR_LPBK_ERROR_COUNT_OBS_0 + +#define LPDDR4__DENALI_PHY_1026__PHY_ADR_MEAS_DLY_STEP_VALUE_0_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_1026__PHY_ADR_MEAS_DLY_STEP_VALUE_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1026__PHY_ADR_MEAS_DLY_STEP_VALUE_0_WIDTH 8U +#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_VALUE_0__REG DENALI_PHY_1026 +#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_VALUE_0__FLD LPDDR4__DENALI_PHY_1026__PHY_ADR_MEAS_DLY_STEP_VALUE_0 + +#define LPDDR4__DENALI_PHY_1026__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0_MASK 0x0F000000U +#define LPDDR4__DENALI_PHY_1026__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_1026__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0_WIDTH 4U +#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0__REG DENALI_PHY_1026 +#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_1026__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0 + +#define LPDDR4__DENALI_PHY_1027_READ_MASK 0xFF7F07FFU +#define LPDDR4__DENALI_PHY_1027_WRITE_MASK 0xFF7F07FFU +#define LPDDR4__DENALI_PHY_1027__PHY_ADR_MASTER_DLY_LOCK_OBS_0_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1027__PHY_ADR_MASTER_DLY_LOCK_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1027__PHY_ADR_MASTER_DLY_LOCK_OBS_0_WIDTH 11U +#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_0__REG DENALI_PHY_1027 +#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_0__FLD LPDDR4__DENALI_PHY_1027__PHY_ADR_MASTER_DLY_LOCK_OBS_0 + +#define LPDDR4__DENALI_PHY_1027__PHY_ADR_BASE_SLV_DLY_ENC_OBS_0_MASK 0x007F0000U +#define LPDDR4__DENALI_PHY_1027__PHY_ADR_BASE_SLV_DLY_ENC_OBS_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1027__PHY_ADR_BASE_SLV_DLY_ENC_OBS_0_WIDTH 7U +#define LPDDR4__PHY_ADR_BASE_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_1027 +#define LPDDR4__PHY_ADR_BASE_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_1027__PHY_ADR_BASE_SLV_DLY_ENC_OBS_0 + +#define LPDDR4__DENALI_PHY_1027__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_1027__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_1027__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0_WIDTH 8U +#define LPDDR4__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_1027 +#define LPDDR4__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_1027__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0 + +#define LPDDR4__DENALI_PHY_1028_READ_MASK 0x01000707U +#define LPDDR4__DENALI_PHY_1028_WRITE_MASK 0x01000707U +#define LPDDR4__DENALI_PHY_1028__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0_MASK 0x00000007U +#define LPDDR4__DENALI_PHY_1028__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1028__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0_WIDTH 3U +#define LPDDR4__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0__REG DENALI_PHY_1028 +#define LPDDR4__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0__FLD LPDDR4__DENALI_PHY_1028__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0 + +#define LPDDR4__DENALI_PHY_1028__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_0_MASK 0x00000700U +#define LPDDR4__DENALI_PHY_1028__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_1028__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_0_WIDTH 3U +#define LPDDR4__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_0__REG DENALI_PHY_1028 +#define LPDDR4__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_1028__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_0 + +#define LPDDR4__DENALI_PHY_1028__SC_PHY_ADR_SNAP_OBS_REGS_0_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_1028__SC_PHY_ADR_SNAP_OBS_REGS_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1028__SC_PHY_ADR_SNAP_OBS_REGS_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_1028__SC_PHY_ADR_SNAP_OBS_REGS_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_1028__SC_PHY_ADR_SNAP_OBS_REGS_0_WOSET 0U +#define LPDDR4__SC_PHY_ADR_SNAP_OBS_REGS_0__REG DENALI_PHY_1028 +#define LPDDR4__SC_PHY_ADR_SNAP_OBS_REGS_0__FLD LPDDR4__DENALI_PHY_1028__SC_PHY_ADR_SNAP_OBS_REGS_0 + +#define LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_0_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_0_WOSET 0U +#define LPDDR4__PHY_ADR_TSEL_ENABLE_0__REG DENALI_PHY_1028 +#define LPDDR4__PHY_ADR_TSEL_ENABLE_0__FLD LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_0 + +#define LPDDR4__DENALI_PHY_1029_READ_MASK 0x011F7F7FU +#define LPDDR4__DENALI_PHY_1029_WRITE_MASK 0x011F7F7FU +#define LPDDR4__DENALI_PHY_1029__PHY_ADR_LPBK_CONTROL_0_MASK 0x0000007FU +#define LPDDR4__DENALI_PHY_1029__PHY_ADR_LPBK_CONTROL_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1029__PHY_ADR_LPBK_CONTROL_0_WIDTH 7U +#define LPDDR4__PHY_ADR_LPBK_CONTROL_0__REG DENALI_PHY_1029 +#define LPDDR4__PHY_ADR_LPBK_CONTROL_0__FLD LPDDR4__DENALI_PHY_1029__PHY_ADR_LPBK_CONTROL_0 + +#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_START_0_MASK 0x00007F00U +#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_START_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_START_0_WIDTH 7U +#define LPDDR4__PHY_ADR_PRBS_PATTERN_START_0__REG DENALI_PHY_1029 +#define LPDDR4__PHY_ADR_PRBS_PATTERN_START_0__FLD LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_START_0 + +#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_MASK_0_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_MASK_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_MASK_0_WIDTH 5U +#define LPDDR4__PHY_ADR_PRBS_PATTERN_MASK_0__REG DENALI_PHY_1029 +#define LPDDR4__PHY_ADR_PRBS_PATTERN_MASK_0__FLD LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_MASK_0 + +#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PWR_RDC_DISABLE_0_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PWR_RDC_DISABLE_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PWR_RDC_DISABLE_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PWR_RDC_DISABLE_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PWR_RDC_DISABLE_0_WOSET 0U +#define LPDDR4__PHY_ADR_PWR_RDC_DISABLE_0__REG DENALI_PHY_1029 +#define LPDDR4__PHY_ADR_PWR_RDC_DISABLE_0__FLD LPDDR4__DENALI_PHY_1029__PHY_ADR_PWR_RDC_DISABLE_0 + +#define LPDDR4__DENALI_PHY_1030_READ_MASK 0x01070301U +#define LPDDR4__DENALI_PHY_1030_WRITE_MASK 0x01070301U +#define LPDDR4__DENALI_PHY_1030__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_1030__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1030__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_1030__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_1030__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0_WOSET 0U +#define LPDDR4__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0__REG DENALI_PHY_1030 +#define LPDDR4__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0__FLD LPDDR4__DENALI_PHY_1030__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0 + +#define LPDDR4__DENALI_PHY_1030__PHY_ADR_TYPE_0_MASK 0x00000300U +#define LPDDR4__DENALI_PHY_1030__PHY_ADR_TYPE_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_1030__PHY_ADR_TYPE_0_WIDTH 2U +#define LPDDR4__PHY_ADR_TYPE_0__REG DENALI_PHY_1030 +#define LPDDR4__PHY_ADR_TYPE_0__FLD LPDDR4__DENALI_PHY_1030__PHY_ADR_TYPE_0 + +#define LPDDR4__DENALI_PHY_1030__PHY_ADR_WRADDR_SHIFT_OBS_0_MASK 0x00070000U +#define LPDDR4__DENALI_PHY_1030__PHY_ADR_WRADDR_SHIFT_OBS_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1030__PHY_ADR_WRADDR_SHIFT_OBS_0_WIDTH 3U +#define LPDDR4__PHY_ADR_WRADDR_SHIFT_OBS_0__REG DENALI_PHY_1030 +#define LPDDR4__PHY_ADR_WRADDR_SHIFT_OBS_0__FLD LPDDR4__DENALI_PHY_1030__PHY_ADR_WRADDR_SHIFT_OBS_0 + +#define LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_0_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_0_WOSET 0U +#define LPDDR4__PHY_ADR_IE_MODE_0__REG DENALI_PHY_1030 +#define LPDDR4__PHY_ADR_IE_MODE_0__FLD LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_0 + +#define LPDDR4__DENALI_PHY_1031_READ_MASK 0x07FFFFFFU +#define LPDDR4__DENALI_PHY_1031_WRITE_MASK 0x07FFFFFFU +#define LPDDR4__DENALI_PHY_1031__PHY_ADR_DDL_MODE_0_MASK 0x07FFFFFFU +#define LPDDR4__DENALI_PHY_1031__PHY_ADR_DDL_MODE_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1031__PHY_ADR_DDL_MODE_0_WIDTH 27U +#define LPDDR4__PHY_ADR_DDL_MODE_0__REG DENALI_PHY_1031 +#define LPDDR4__PHY_ADR_DDL_MODE_0__FLD LPDDR4__DENALI_PHY_1031__PHY_ADR_DDL_MODE_0 + +#define LPDDR4__DENALI_PHY_1032_READ_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_1032_WRITE_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_1032__PHY_ADR_DDL_MASK_0_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_1032__PHY_ADR_DDL_MASK_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1032__PHY_ADR_DDL_MASK_0_WIDTH 6U +#define LPDDR4__PHY_ADR_DDL_MASK_0__REG DENALI_PHY_1032 +#define LPDDR4__PHY_ADR_DDL_MASK_0__FLD LPDDR4__DENALI_PHY_1032__PHY_ADR_DDL_MASK_0 + +#define LPDDR4__DENALI_PHY_1033_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1033_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1033__PHY_ADR_DDL_TEST_OBS_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1033__PHY_ADR_DDL_TEST_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1033__PHY_ADR_DDL_TEST_OBS_0_WIDTH 32U +#define LPDDR4__PHY_ADR_DDL_TEST_OBS_0__REG DENALI_PHY_1033 +#define LPDDR4__PHY_ADR_DDL_TEST_OBS_0__FLD LPDDR4__DENALI_PHY_1033__PHY_ADR_DDL_TEST_OBS_0 + +#define LPDDR4__DENALI_PHY_1034_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1034_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1034__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1034__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1034__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0_WIDTH 32U +#define LPDDR4__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0__REG DENALI_PHY_1034 +#define LPDDR4__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0__FLD LPDDR4__DENALI_PHY_1034__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0 + +#define LPDDR4__DENALI_PHY_1035_READ_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_1035_WRITE_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_START_0_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_START_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_START_0_WIDTH 11U +#define LPDDR4__PHY_ADR_CALVL_START_0__REG DENALI_PHY_1035 +#define LPDDR4__PHY_ADR_CALVL_START_0__FLD LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_START_0 + +#define LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_COARSE_DLY_0_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_COARSE_DLY_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_COARSE_DLY_0_WIDTH 11U +#define LPDDR4__PHY_ADR_CALVL_COARSE_DLY_0__REG DENALI_PHY_1035 +#define LPDDR4__PHY_ADR_CALVL_COARSE_DLY_0__FLD LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_COARSE_DLY_0 + +#define LPDDR4__DENALI_PHY_1036_READ_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1036_WRITE_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1036__PHY_ADR_CALVL_QTR_0_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1036__PHY_ADR_CALVL_QTR_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1036__PHY_ADR_CALVL_QTR_0_WIDTH 11U +#define LPDDR4__PHY_ADR_CALVL_QTR_0__REG DENALI_PHY_1036 +#define LPDDR4__PHY_ADR_CALVL_QTR_0__FLD LPDDR4__DENALI_PHY_1036__PHY_ADR_CALVL_QTR_0 + +#define LPDDR4__DENALI_PHY_1037_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PHY_1037_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PHY_1037__PHY_ADR_CALVL_SWIZZLE0_0_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PHY_1037__PHY_ADR_CALVL_SWIZZLE0_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1037__PHY_ADR_CALVL_SWIZZLE0_0_WIDTH 24U +#define LPDDR4__PHY_ADR_CALVL_SWIZZLE0_0__REG DENALI_PHY_1037 +#define LPDDR4__PHY_ADR_CALVL_SWIZZLE0_0__FLD LPDDR4__DENALI_PHY_1037__PHY_ADR_CALVL_SWIZZLE0_0 + +#define LPDDR4__DENALI_PHY_1038_READ_MASK 0x03FFFFFFU +#define LPDDR4__DENALI_PHY_1038_WRITE_MASK 0x03FFFFFFU +#define LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_SWIZZLE1_0_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_SWIZZLE1_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_SWIZZLE1_0_WIDTH 24U +#define LPDDR4__PHY_ADR_CALVL_SWIZZLE1_0__REG DENALI_PHY_1038 +#define LPDDR4__PHY_ADR_CALVL_SWIZZLE1_0__FLD LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_SWIZZLE1_0 + +#define LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_RANK_CTRL_0_MASK 0x03000000U +#define LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_RANK_CTRL_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_RANK_CTRL_0_WIDTH 2U +#define LPDDR4__PHY_ADR_CALVL_RANK_CTRL_0__REG DENALI_PHY_1038 +#define LPDDR4__PHY_ADR_CALVL_RANK_CTRL_0__FLD LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_RANK_CTRL_0 + +#define LPDDR4__DENALI_PHY_1039_READ_MASK 0x01FF0F03U +#define LPDDR4__DENALI_PHY_1039_WRITE_MASK 0x01FF0F03U +#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_NUM_PATTERNS_0_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_NUM_PATTERNS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_NUM_PATTERNS_0_WIDTH 2U +#define LPDDR4__PHY_ADR_CALVL_NUM_PATTERNS_0__REG DENALI_PHY_1039 +#define LPDDR4__PHY_ADR_CALVL_NUM_PATTERNS_0__FLD LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_NUM_PATTERNS_0 + +#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_RESP_WAIT_CNT_0_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_RESP_WAIT_CNT_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_RESP_WAIT_CNT_0_WIDTH 4U +#define LPDDR4__PHY_ADR_CALVL_RESP_WAIT_CNT_0__REG DENALI_PHY_1039 +#define LPDDR4__PHY_ADR_CALVL_RESP_WAIT_CNT_0__FLD LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_RESP_WAIT_CNT_0 + +#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_PERIODIC_START_OFFSET_0_MASK 0x01FF0000U +#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_PERIODIC_START_OFFSET_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_PERIODIC_START_OFFSET_0_WIDTH 9U +#define LPDDR4__PHY_ADR_CALVL_PERIODIC_START_OFFSET_0__REG DENALI_PHY_1039 +#define LPDDR4__PHY_ADR_CALVL_PERIODIC_START_OFFSET_0__FLD LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_PERIODIC_START_OFFSET_0 + +#define LPDDR4__DENALI_PHY_1040_READ_MASK 0x07000001U +#define LPDDR4__DENALI_PHY_1040_WRITE_MASK 0x07000001U +#define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_DEBUG_MODE_0_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_DEBUG_MODE_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_DEBUG_MODE_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_DEBUG_MODE_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_DEBUG_MODE_0_WOSET 0U +#define LPDDR4__PHY_ADR_CALVL_DEBUG_MODE_0__REG DENALI_PHY_1040 +#define LPDDR4__PHY_ADR_CALVL_DEBUG_MODE_0__FLD LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_DEBUG_MODE_0 + +#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_DEBUG_CONT_0_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_DEBUG_CONT_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_DEBUG_CONT_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_DEBUG_CONT_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_DEBUG_CONT_0_WOSET 0U +#define LPDDR4__SC_PHY_ADR_CALVL_DEBUG_CONT_0__REG DENALI_PHY_1040 +#define LPDDR4__SC_PHY_ADR_CALVL_DEBUG_CONT_0__FLD LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_DEBUG_CONT_0 + +#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_ERROR_CLR_0_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_ERROR_CLR_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_ERROR_CLR_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_ERROR_CLR_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_ERROR_CLR_0_WOSET 0U +#define LPDDR4__SC_PHY_ADR_CALVL_ERROR_CLR_0__REG DENALI_PHY_1040 +#define LPDDR4__SC_PHY_ADR_CALVL_ERROR_CLR_0__FLD LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_ERROR_CLR_0 + +#define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_OBS_SELECT_0_MASK 0x07000000U +#define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_OBS_SELECT_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_OBS_SELECT_0_WIDTH 3U +#define LPDDR4__PHY_ADR_CALVL_OBS_SELECT_0__REG DENALI_PHY_1040 +#define LPDDR4__PHY_ADR_CALVL_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_OBS_SELECT_0 + +#define LPDDR4__DENALI_PHY_1041_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1041_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1041__PHY_ADR_CALVL_CH0_OBS0_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1041__PHY_ADR_CALVL_CH0_OBS0_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1041__PHY_ADR_CALVL_CH0_OBS0_0_WIDTH 32U +#define LPDDR4__PHY_ADR_CALVL_CH0_OBS0_0__REG DENALI_PHY_1041 +#define LPDDR4__PHY_ADR_CALVL_CH0_OBS0_0__FLD LPDDR4__DENALI_PHY_1041__PHY_ADR_CALVL_CH0_OBS0_0 + +#define LPDDR4__DENALI_PHY_1042_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1042_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1042__PHY_ADR_CALVL_CH1_OBS0_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1042__PHY_ADR_CALVL_CH1_OBS0_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1042__PHY_ADR_CALVL_CH1_OBS0_0_WIDTH 32U +#define LPDDR4__PHY_ADR_CALVL_CH1_OBS0_0__REG DENALI_PHY_1042 +#define LPDDR4__PHY_ADR_CALVL_CH1_OBS0_0__FLD LPDDR4__DENALI_PHY_1042__PHY_ADR_CALVL_CH1_OBS0_0 + +#define LPDDR4__DENALI_PHY_1043_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1043_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1043__PHY_ADR_CALVL_OBS1_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1043__PHY_ADR_CALVL_OBS1_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1043__PHY_ADR_CALVL_OBS1_0_WIDTH 32U +#define LPDDR4__PHY_ADR_CALVL_OBS1_0__REG DENALI_PHY_1043 +#define LPDDR4__PHY_ADR_CALVL_OBS1_0__FLD LPDDR4__DENALI_PHY_1043__PHY_ADR_CALVL_OBS1_0 + +#define LPDDR4__DENALI_PHY_1044_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1044_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1044__PHY_ADR_CALVL_OBS2_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1044__PHY_ADR_CALVL_OBS2_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1044__PHY_ADR_CALVL_OBS2_0_WIDTH 32U +#define LPDDR4__PHY_ADR_CALVL_OBS2_0__REG DENALI_PHY_1044 +#define LPDDR4__PHY_ADR_CALVL_OBS2_0__FLD LPDDR4__DENALI_PHY_1044__PHY_ADR_CALVL_OBS2_0 + +#define LPDDR4__DENALI_PHY_1045_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1045_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1045__PHY_ADR_CALVL_FG_0_0_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1045__PHY_ADR_CALVL_FG_0_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1045__PHY_ADR_CALVL_FG_0_0_WIDTH 20U +#define LPDDR4__PHY_ADR_CALVL_FG_0_0__REG DENALI_PHY_1045 +#define LPDDR4__PHY_ADR_CALVL_FG_0_0__FLD LPDDR4__DENALI_PHY_1045__PHY_ADR_CALVL_FG_0_0 + +#define LPDDR4__DENALI_PHY_1046_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1046_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1046__PHY_ADR_CALVL_BG_0_0_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1046__PHY_ADR_CALVL_BG_0_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1046__PHY_ADR_CALVL_BG_0_0_WIDTH 20U +#define LPDDR4__PHY_ADR_CALVL_BG_0_0__REG DENALI_PHY_1046 +#define LPDDR4__PHY_ADR_CALVL_BG_0_0__FLD LPDDR4__DENALI_PHY_1046__PHY_ADR_CALVL_BG_0_0 + +#define LPDDR4__DENALI_PHY_1047_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1047_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1047__PHY_ADR_CALVL_FG_1_0_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1047__PHY_ADR_CALVL_FG_1_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1047__PHY_ADR_CALVL_FG_1_0_WIDTH 20U +#define LPDDR4__PHY_ADR_CALVL_FG_1_0__REG DENALI_PHY_1047 +#define LPDDR4__PHY_ADR_CALVL_FG_1_0__FLD LPDDR4__DENALI_PHY_1047__PHY_ADR_CALVL_FG_1_0 + +#define LPDDR4__DENALI_PHY_1048_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1048_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1048__PHY_ADR_CALVL_BG_1_0_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1048__PHY_ADR_CALVL_BG_1_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1048__PHY_ADR_CALVL_BG_1_0_WIDTH 20U +#define LPDDR4__PHY_ADR_CALVL_BG_1_0__REG DENALI_PHY_1048 +#define LPDDR4__PHY_ADR_CALVL_BG_1_0__FLD LPDDR4__DENALI_PHY_1048__PHY_ADR_CALVL_BG_1_0 + +#define LPDDR4__DENALI_PHY_1049_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1049_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1049__PHY_ADR_CALVL_FG_2_0_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1049__PHY_ADR_CALVL_FG_2_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1049__PHY_ADR_CALVL_FG_2_0_WIDTH 20U +#define LPDDR4__PHY_ADR_CALVL_FG_2_0__REG DENALI_PHY_1049 +#define LPDDR4__PHY_ADR_CALVL_FG_2_0__FLD LPDDR4__DENALI_PHY_1049__PHY_ADR_CALVL_FG_2_0 + +#define LPDDR4__DENALI_PHY_1050_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1050_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1050__PHY_ADR_CALVL_BG_2_0_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1050__PHY_ADR_CALVL_BG_2_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1050__PHY_ADR_CALVL_BG_2_0_WIDTH 20U +#define LPDDR4__PHY_ADR_CALVL_BG_2_0__REG DENALI_PHY_1050 +#define LPDDR4__PHY_ADR_CALVL_BG_2_0__FLD LPDDR4__DENALI_PHY_1050__PHY_ADR_CALVL_BG_2_0 + +#define LPDDR4__DENALI_PHY_1051_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1051_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1051__PHY_ADR_CALVL_FG_3_0_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1051__PHY_ADR_CALVL_FG_3_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1051__PHY_ADR_CALVL_FG_3_0_WIDTH 20U +#define LPDDR4__PHY_ADR_CALVL_FG_3_0__REG DENALI_PHY_1051 +#define LPDDR4__PHY_ADR_CALVL_FG_3_0__FLD LPDDR4__DENALI_PHY_1051__PHY_ADR_CALVL_FG_3_0 + +#define LPDDR4__DENALI_PHY_1052_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1052_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1052__PHY_ADR_CALVL_BG_3_0_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1052__PHY_ADR_CALVL_BG_3_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1052__PHY_ADR_CALVL_BG_3_0_WIDTH 20U +#define LPDDR4__PHY_ADR_CALVL_BG_3_0__REG DENALI_PHY_1052 +#define LPDDR4__PHY_ADR_CALVL_BG_3_0__FLD LPDDR4__DENALI_PHY_1052__PHY_ADR_CALVL_BG_3_0 + +#define LPDDR4__DENALI_PHY_1053_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PHY_1053_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PHY_1053__PHY_ADR_ADDR_SEL_0_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PHY_1053__PHY_ADR_ADDR_SEL_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1053__PHY_ADR_ADDR_SEL_0_WIDTH 24U +#define LPDDR4__PHY_ADR_ADDR_SEL_0__REG DENALI_PHY_1053 +#define LPDDR4__PHY_ADR_ADDR_SEL_0__FLD LPDDR4__DENALI_PHY_1053__PHY_ADR_ADDR_SEL_0 + +#define LPDDR4__DENALI_PHY_1054_READ_MASK 0x3F3F03FFU +#define LPDDR4__DENALI_PHY_1054_WRITE_MASK 0x3F3F03FFU +#define LPDDR4__DENALI_PHY_1054__PHY_ADR_LP4_BOOT_SLV_DELAY_0_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_1054__PHY_ADR_LP4_BOOT_SLV_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1054__PHY_ADR_LP4_BOOT_SLV_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_ADR_LP4_BOOT_SLV_DELAY_0__REG DENALI_PHY_1054 +#define LPDDR4__PHY_ADR_LP4_BOOT_SLV_DELAY_0__FLD LPDDR4__DENALI_PHY_1054__PHY_ADR_LP4_BOOT_SLV_DELAY_0 + +#define LPDDR4__DENALI_PHY_1054__PHY_ADR_BIT_MASK_0_MASK 0x003F0000U +#define LPDDR4__DENALI_PHY_1054__PHY_ADR_BIT_MASK_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1054__PHY_ADR_BIT_MASK_0_WIDTH 6U +#define LPDDR4__PHY_ADR_BIT_MASK_0__REG DENALI_PHY_1054 +#define LPDDR4__PHY_ADR_BIT_MASK_0__FLD LPDDR4__DENALI_PHY_1054__PHY_ADR_BIT_MASK_0 + +#define LPDDR4__DENALI_PHY_1054__PHY_ADR_SEG_MASK_0_MASK 0x3F000000U +#define LPDDR4__DENALI_PHY_1054__PHY_ADR_SEG_MASK_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_1054__PHY_ADR_SEG_MASK_0_WIDTH 6U +#define LPDDR4__PHY_ADR_SEG_MASK_0__REG DENALI_PHY_1054 +#define LPDDR4__PHY_ADR_SEG_MASK_0__FLD LPDDR4__DENALI_PHY_1054__PHY_ADR_SEG_MASK_0 + +#define LPDDR4__DENALI_PHY_1055_READ_MASK 0x3F0F3F3FU +#define LPDDR4__DENALI_PHY_1055_WRITE_MASK 0x3F0F3F3FU +#define LPDDR4__DENALI_PHY_1055__PHY_ADR_CALVL_TRAIN_MASK_0_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_1055__PHY_ADR_CALVL_TRAIN_MASK_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1055__PHY_ADR_CALVL_TRAIN_MASK_0_WIDTH 6U +#define LPDDR4__PHY_ADR_CALVL_TRAIN_MASK_0__REG DENALI_PHY_1055 +#define LPDDR4__PHY_ADR_CALVL_TRAIN_MASK_0__FLD LPDDR4__DENALI_PHY_1055__PHY_ADR_CALVL_TRAIN_MASK_0 + +#define LPDDR4__DENALI_PHY_1055__PHY_ADR_CSLVL_TRAIN_MASK_0_MASK 0x00003F00U +#define LPDDR4__DENALI_PHY_1055__PHY_ADR_CSLVL_TRAIN_MASK_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_1055__PHY_ADR_CSLVL_TRAIN_MASK_0_WIDTH 6U +#define LPDDR4__PHY_ADR_CSLVL_TRAIN_MASK_0__REG DENALI_PHY_1055 +#define LPDDR4__PHY_ADR_CSLVL_TRAIN_MASK_0__FLD LPDDR4__DENALI_PHY_1055__PHY_ADR_CSLVL_TRAIN_MASK_0 + +#define LPDDR4__DENALI_PHY_1055__PHY_ADR_STATIC_TOG_DISABLE_0_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_1055__PHY_ADR_STATIC_TOG_DISABLE_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1055__PHY_ADR_STATIC_TOG_DISABLE_0_WIDTH 4U +#define LPDDR4__PHY_ADR_STATIC_TOG_DISABLE_0__REG DENALI_PHY_1055 +#define LPDDR4__PHY_ADR_STATIC_TOG_DISABLE_0__FLD LPDDR4__DENALI_PHY_1055__PHY_ADR_STATIC_TOG_DISABLE_0 + +#define LPDDR4__DENALI_PHY_1055__PHY_ADR_SW_TXIO_CTRL_0_MASK 0x3F000000U +#define LPDDR4__DENALI_PHY_1055__PHY_ADR_SW_TXIO_CTRL_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_1055__PHY_ADR_SW_TXIO_CTRL_0_WIDTH 6U +#define LPDDR4__PHY_ADR_SW_TXIO_CTRL_0__REG DENALI_PHY_1055 +#define LPDDR4__PHY_ADR_SW_TXIO_CTRL_0__FLD LPDDR4__DENALI_PHY_1055__PHY_ADR_SW_TXIO_CTRL_0 + +#define LPDDR4__DENALI_PHY_1056_READ_MASK 0xFFFFFF03U +#define LPDDR4__DENALI_PHY_1056_WRITE_MASK 0xFFFFFF03U +#define LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_INIT_DISABLE_0_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_INIT_DISABLE_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_INIT_DISABLE_0_WIDTH 2U +#define LPDDR4__PHY_ADR_DC_INIT_DISABLE_0__REG DENALI_PHY_1056 +#define LPDDR4__PHY_ADR_DC_INIT_DISABLE_0__FLD LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_INIT_DISABLE_0 + +#define LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_ADR0_CLK_ADJUST_0_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_ADR0_CLK_ADJUST_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_ADR0_CLK_ADJUST_0_WIDTH 8U +#define LPDDR4__PHY_ADR_DC_ADR0_CLK_ADJUST_0__REG DENALI_PHY_1056 +#define LPDDR4__PHY_ADR_DC_ADR0_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_ADR0_CLK_ADJUST_0 + +#define LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_ADR1_CLK_ADJUST_0_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_ADR1_CLK_ADJUST_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_ADR1_CLK_ADJUST_0_WIDTH 8U +#define LPDDR4__PHY_ADR_DC_ADR1_CLK_ADJUST_0__REG DENALI_PHY_1056 +#define LPDDR4__PHY_ADR_DC_ADR1_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_ADR1_CLK_ADJUST_0 + +#define LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_ADR2_CLK_ADJUST_0_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_ADR2_CLK_ADJUST_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_ADR2_CLK_ADJUST_0_WIDTH 8U +#define LPDDR4__PHY_ADR_DC_ADR2_CLK_ADJUST_0__REG DENALI_PHY_1056 +#define LPDDR4__PHY_ADR_DC_ADR2_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_ADR2_CLK_ADJUST_0 + +#define LPDDR4__DENALI_PHY_1057_READ_MASK 0x01FFFFFFU +#define LPDDR4__DENALI_PHY_1057_WRITE_MASK 0x01FFFFFFU +#define LPDDR4__DENALI_PHY_1057__PHY_ADR_DC_ADR3_CLK_ADJUST_0_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_1057__PHY_ADR_DC_ADR3_CLK_ADJUST_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1057__PHY_ADR_DC_ADR3_CLK_ADJUST_0_WIDTH 8U +#define LPDDR4__PHY_ADR_DC_ADR3_CLK_ADJUST_0__REG DENALI_PHY_1057 +#define LPDDR4__PHY_ADR_DC_ADR3_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_1057__PHY_ADR_DC_ADR3_CLK_ADJUST_0 + +#define LPDDR4__DENALI_PHY_1057__PHY_ADR_DC_ADR4_CLK_ADJUST_0_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_1057__PHY_ADR_DC_ADR4_CLK_ADJUST_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_1057__PHY_ADR_DC_ADR4_CLK_ADJUST_0_WIDTH 8U +#define LPDDR4__PHY_ADR_DC_ADR4_CLK_ADJUST_0__REG DENALI_PHY_1057 +#define LPDDR4__PHY_ADR_DC_ADR4_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_1057__PHY_ADR_DC_ADR4_CLK_ADJUST_0 + +#define LPDDR4__DENALI_PHY_1057__PHY_ADR_DC_ADR5_CLK_ADJUST_0_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_1057__PHY_ADR_DC_ADR5_CLK_ADJUST_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1057__PHY_ADR_DC_ADR5_CLK_ADJUST_0_WIDTH 8U +#define LPDDR4__PHY_ADR_DC_ADR5_CLK_ADJUST_0__REG DENALI_PHY_1057 +#define LPDDR4__PHY_ADR_DC_ADR5_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_1057__PHY_ADR_DC_ADR5_CLK_ADJUST_0 + +#define LPDDR4__DENALI_PHY_1057__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_0_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_1057__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_1057__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_1057__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_1057__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_0_WOSET 0U +#define LPDDR4__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_0__REG DENALI_PHY_1057 +#define LPDDR4__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_0__FLD LPDDR4__DENALI_PHY_1057__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_0 + +#define LPDDR4__DENALI_PHY_1058_READ_MASK 0x3F03FFFFU +#define LPDDR4__DENALI_PHY_1058_WRITE_MASK 0x3F03FFFFU +#define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_CAL_SAMPLE_WAIT_0_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_CAL_SAMPLE_WAIT_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_CAL_SAMPLE_WAIT_0_WIDTH 8U +#define LPDDR4__PHY_ADR_DC_CAL_SAMPLE_WAIT_0__REG DENALI_PHY_1058 +#define LPDDR4__PHY_ADR_DC_CAL_SAMPLE_WAIT_0__FLD LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_CAL_SAMPLE_WAIT_0 + +#define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_CAL_TIMEOUT_0_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_CAL_TIMEOUT_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_CAL_TIMEOUT_0_WIDTH 8U +#define LPDDR4__PHY_ADR_DC_CAL_TIMEOUT_0__REG DENALI_PHY_1058 +#define LPDDR4__PHY_ADR_DC_CAL_TIMEOUT_0__FLD LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_CAL_TIMEOUT_0 + +#define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_WEIGHT_0_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_WEIGHT_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_WEIGHT_0_WIDTH 2U +#define LPDDR4__PHY_ADR_DC_WEIGHT_0__REG DENALI_PHY_1058 +#define LPDDR4__PHY_ADR_DC_WEIGHT_0__FLD LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_WEIGHT_0 + +#define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_ADJUST_START_0_MASK 0x3F000000U +#define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_ADJUST_START_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_ADJUST_START_0_WIDTH 6U +#define LPDDR4__PHY_ADR_DC_ADJUST_START_0__REG DENALI_PHY_1058 +#define LPDDR4__PHY_ADR_DC_ADJUST_START_0__FLD LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_ADJUST_START_0 + +#define LPDDR4__DENALI_PHY_1059_READ_MASK 0x0101FFFFU +#define LPDDR4__DENALI_PHY_1059_WRITE_MASK 0x0101FFFFU +#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_SAMPLE_CNT_0_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_SAMPLE_CNT_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_SAMPLE_CNT_0_WIDTH 8U +#define LPDDR4__PHY_ADR_DC_ADJUST_SAMPLE_CNT_0__REG DENALI_PHY_1059 +#define LPDDR4__PHY_ADR_DC_ADJUST_SAMPLE_CNT_0__FLD LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_SAMPLE_CNT_0 + +#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_THRSHLD_0_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_THRSHLD_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_THRSHLD_0_WIDTH 8U +#define LPDDR4__PHY_ADR_DC_ADJUST_THRSHLD_0__REG DENALI_PHY_1059 +#define LPDDR4__PHY_ADR_DC_ADJUST_THRSHLD_0__FLD LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_THRSHLD_0 + +#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_DIRECT_0_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_DIRECT_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_DIRECT_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_DIRECT_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_DIRECT_0_WOSET 0U +#define LPDDR4__PHY_ADR_DC_ADJUST_DIRECT_0__REG DENALI_PHY_1059 +#define LPDDR4__PHY_ADR_DC_ADJUST_DIRECT_0__FLD LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_DIRECT_0 + +#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_CAL_POLARITY_0_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_CAL_POLARITY_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_CAL_POLARITY_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_CAL_POLARITY_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_CAL_POLARITY_0_WOSET 0U +#define LPDDR4__PHY_ADR_DC_CAL_POLARITY_0__REG DENALI_PHY_1059 +#define LPDDR4__PHY_ADR_DC_CAL_POLARITY_0__FLD LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_CAL_POLARITY_0 + +#define LPDDR4__DENALI_PHY_1060_READ_MASK 0x07FF3F01U +#define LPDDR4__DENALI_PHY_1060_WRITE_MASK 0x07FF3F01U +#define LPDDR4__DENALI_PHY_1060__PHY_ADR_DC_CAL_START_0_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_1060__PHY_ADR_DC_CAL_START_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1060__PHY_ADR_DC_CAL_START_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_1060__PHY_ADR_DC_CAL_START_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_1060__PHY_ADR_DC_CAL_START_0_WOSET 0U +#define LPDDR4__PHY_ADR_DC_CAL_START_0__REG DENALI_PHY_1060 +#define LPDDR4__PHY_ADR_DC_CAL_START_0__FLD LPDDR4__DENALI_PHY_1060__PHY_ADR_DC_CAL_START_0 + +#define LPDDR4__DENALI_PHY_1060__PHY_ADR_SW_TXPWR_CTRL_0_MASK 0x00003F00U +#define LPDDR4__DENALI_PHY_1060__PHY_ADR_SW_TXPWR_CTRL_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_1060__PHY_ADR_SW_TXPWR_CTRL_0_WIDTH 6U +#define LPDDR4__PHY_ADR_SW_TXPWR_CTRL_0__REG DENALI_PHY_1060 +#define LPDDR4__PHY_ADR_SW_TXPWR_CTRL_0__FLD LPDDR4__DENALI_PHY_1060__PHY_ADR_SW_TXPWR_CTRL_0 + +#define LPDDR4__DENALI_PHY_1060__PHY_PARITY_ERROR_REGIF_ADR_0_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_1060__PHY_PARITY_ERROR_REGIF_ADR_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1060__PHY_PARITY_ERROR_REGIF_ADR_0_WIDTH 11U +#define LPDDR4__PHY_PARITY_ERROR_REGIF_ADR_0__REG DENALI_PHY_1060 +#define LPDDR4__PHY_PARITY_ERROR_REGIF_ADR_0__FLD LPDDR4__DENALI_PHY_1060__PHY_PARITY_ERROR_REGIF_ADR_0 + +#define LPDDR4__DENALI_PHY_1061_READ_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_1061_WRITE_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_1061__PHY_AS_FSM_ERROR_INFO_0_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_1061__PHY_AS_FSM_ERROR_INFO_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1061__PHY_AS_FSM_ERROR_INFO_0_WIDTH 9U +#define LPDDR4__PHY_AS_FSM_ERROR_INFO_0__REG DENALI_PHY_1061 +#define LPDDR4__PHY_AS_FSM_ERROR_INFO_0__FLD LPDDR4__DENALI_PHY_1061__PHY_AS_FSM_ERROR_INFO_0 + +#define LPDDR4__DENALI_PHY_1061__PHY_AS_FSM_ERROR_INFO_MASK_0_MASK 0x01FF0000U +#define LPDDR4__DENALI_PHY_1061__PHY_AS_FSM_ERROR_INFO_MASK_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1061__PHY_AS_FSM_ERROR_INFO_MASK_0_WIDTH 9U +#define LPDDR4__PHY_AS_FSM_ERROR_INFO_MASK_0__REG DENALI_PHY_1061 +#define LPDDR4__PHY_AS_FSM_ERROR_INFO_MASK_0__FLD LPDDR4__DENALI_PHY_1061__PHY_AS_FSM_ERROR_INFO_MASK_0 + +#define LPDDR4__DENALI_PHY_1062_READ_MASK 0x01010000U +#define LPDDR4__DENALI_PHY_1062_WRITE_MASK 0x01010000U +#define LPDDR4__DENALI_PHY_1062__SC_PHY_AS_FSM_ERROR_INFO_WOCLR_0_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_1062__SC_PHY_AS_FSM_ERROR_INFO_WOCLR_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1062__SC_PHY_AS_FSM_ERROR_INFO_WOCLR_0_WIDTH 9U +#define LPDDR4__SC_PHY_AS_FSM_ERROR_INFO_WOCLR_0__REG DENALI_PHY_1062 +#define LPDDR4__SC_PHY_AS_FSM_ERROR_INFO_WOCLR_0__FLD LPDDR4__DENALI_PHY_1062__SC_PHY_AS_FSM_ERROR_INFO_WOCLR_0 + +#define LPDDR4__DENALI_PHY_1062__PHY_AS_TRAIN_CALIB_ERROR_INFO_0_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_1062__PHY_AS_TRAIN_CALIB_ERROR_INFO_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1062__PHY_AS_TRAIN_CALIB_ERROR_INFO_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_1062__PHY_AS_TRAIN_CALIB_ERROR_INFO_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_1062__PHY_AS_TRAIN_CALIB_ERROR_INFO_0_WOSET 0U +#define LPDDR4__PHY_AS_TRAIN_CALIB_ERROR_INFO_0__REG DENALI_PHY_1062 +#define LPDDR4__PHY_AS_TRAIN_CALIB_ERROR_INFO_0__FLD LPDDR4__DENALI_PHY_1062__PHY_AS_TRAIN_CALIB_ERROR_INFO_0 + +#define LPDDR4__DENALI_PHY_1062__PHY_AS_TRAIN_CALIB_ERROR_INFO_MASK_0_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_1062__PHY_AS_TRAIN_CALIB_ERROR_INFO_MASK_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_1062__PHY_AS_TRAIN_CALIB_ERROR_INFO_MASK_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_1062__PHY_AS_TRAIN_CALIB_ERROR_INFO_MASK_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_1062__PHY_AS_TRAIN_CALIB_ERROR_INFO_MASK_0_WOSET 0U +#define LPDDR4__PHY_AS_TRAIN_CALIB_ERROR_INFO_MASK_0__REG DENALI_PHY_1062 +#define LPDDR4__PHY_AS_TRAIN_CALIB_ERROR_INFO_MASK_0__FLD LPDDR4__DENALI_PHY_1062__PHY_AS_TRAIN_CALIB_ERROR_INFO_MASK_0 + +#define LPDDR4__DENALI_PHY_1063__SC_PHY_AS_TRAIN_CALIB_ERROR_INFO_WOCLR_0_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_1063__SC_PHY_AS_TRAIN_CALIB_ERROR_INFO_WOCLR_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1063__SC_PHY_AS_TRAIN_CALIB_ERROR_INFO_WOCLR_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_1063__SC_PHY_AS_TRAIN_CALIB_ERROR_INFO_WOCLR_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_1063__SC_PHY_AS_TRAIN_CALIB_ERROR_INFO_WOCLR_0_WOSET 0U +#define LPDDR4__SC_PHY_AS_TRAIN_CALIB_ERROR_INFO_WOCLR_0__REG DENALI_PHY_1063 +#define LPDDR4__SC_PHY_AS_TRAIN_CALIB_ERROR_INFO_WOCLR_0__FLD LPDDR4__DENALI_PHY_1063__SC_PHY_AS_TRAIN_CALIB_ERROR_INFO_WOCLR_0 + +#define LPDDR4__DENALI_PHY_1064_READ_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_1064_WRITE_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_1064__PHY_ADR_TSEL_SELECT_0_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_1064__PHY_ADR_TSEL_SELECT_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1064__PHY_ADR_TSEL_SELECT_0_WIDTH 8U +#define LPDDR4__PHY_ADR_TSEL_SELECT_0__REG DENALI_PHY_1064 +#define LPDDR4__PHY_ADR_TSEL_SELECT_0__FLD LPDDR4__DENALI_PHY_1064__PHY_ADR_TSEL_SELECT_0 + +#define LPDDR4__DENALI_PHY_1064__PHY_ADR_DC_CAL_CLK_SEL_0_MASK 0x00000700U +#define LPDDR4__DENALI_PHY_1064__PHY_ADR_DC_CAL_CLK_SEL_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_1064__PHY_ADR_DC_CAL_CLK_SEL_0_WIDTH 3U +#define LPDDR4__PHY_ADR_DC_CAL_CLK_SEL_0__REG DENALI_PHY_1064 +#define LPDDR4__PHY_ADR_DC_CAL_CLK_SEL_0__FLD LPDDR4__DENALI_PHY_1064__PHY_ADR_DC_CAL_CLK_SEL_0 + +#define LPDDR4__DENALI_PHY_1064__PHY_PAD_ADR_IO_CFG_0_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_1064__PHY_PAD_ADR_IO_CFG_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1064__PHY_PAD_ADR_IO_CFG_0_WIDTH 11U +#define LPDDR4__PHY_PAD_ADR_IO_CFG_0__REG DENALI_PHY_1064 +#define LPDDR4__PHY_PAD_ADR_IO_CFG_0__FLD LPDDR4__DENALI_PHY_1064__PHY_PAD_ADR_IO_CFG_0 + +#define LPDDR4__DENALI_PHY_1065_READ_MASK 0x1F07FF1FU +#define LPDDR4__DENALI_PHY_1065_WRITE_MASK 0x1F07FF1FU +#define LPDDR4__DENALI_PHY_1065__PHY_ADR0_SW_WRADDR_SHIFT_0_MASK 0x0000001FU +#define LPDDR4__DENALI_PHY_1065__PHY_ADR0_SW_WRADDR_SHIFT_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1065__PHY_ADR0_SW_WRADDR_SHIFT_0_WIDTH 5U +#define LPDDR4__PHY_ADR0_SW_WRADDR_SHIFT_0__REG DENALI_PHY_1065 +#define LPDDR4__PHY_ADR0_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_1065__PHY_ADR0_SW_WRADDR_SHIFT_0 + +#define LPDDR4__DENALI_PHY_1065__PHY_ADR0_CLK_WR_SLAVE_DELAY_0_MASK 0x0007FF00U +#define LPDDR4__DENALI_PHY_1065__PHY_ADR0_CLK_WR_SLAVE_DELAY_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_1065__PHY_ADR0_CLK_WR_SLAVE_DELAY_0_WIDTH 11U +#define LPDDR4__PHY_ADR0_CLK_WR_SLAVE_DELAY_0__REG DENALI_PHY_1065 +#define LPDDR4__PHY_ADR0_CLK_WR_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1065__PHY_ADR0_CLK_WR_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_1065__PHY_ADR1_SW_WRADDR_SHIFT_0_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_1065__PHY_ADR1_SW_WRADDR_SHIFT_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_1065__PHY_ADR1_SW_WRADDR_SHIFT_0_WIDTH 5U +#define LPDDR4__PHY_ADR1_SW_WRADDR_SHIFT_0__REG DENALI_PHY_1065 +#define LPDDR4__PHY_ADR1_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_1065__PHY_ADR1_SW_WRADDR_SHIFT_0 + +#define LPDDR4__DENALI_PHY_1066_READ_MASK 0x001F07FFU +#define LPDDR4__DENALI_PHY_1066_WRITE_MASK 0x001F07FFU +#define LPDDR4__DENALI_PHY_1066__PHY_ADR1_CLK_WR_SLAVE_DELAY_0_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1066__PHY_ADR1_CLK_WR_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1066__PHY_ADR1_CLK_WR_SLAVE_DELAY_0_WIDTH 11U +#define LPDDR4__PHY_ADR1_CLK_WR_SLAVE_DELAY_0__REG DENALI_PHY_1066 +#define LPDDR4__PHY_ADR1_CLK_WR_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1066__PHY_ADR1_CLK_WR_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_1066__PHY_ADR2_SW_WRADDR_SHIFT_0_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_1066__PHY_ADR2_SW_WRADDR_SHIFT_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1066__PHY_ADR2_SW_WRADDR_SHIFT_0_WIDTH 5U +#define LPDDR4__PHY_ADR2_SW_WRADDR_SHIFT_0__REG DENALI_PHY_1066 +#define LPDDR4__PHY_ADR2_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_1066__PHY_ADR2_SW_WRADDR_SHIFT_0 + +#define LPDDR4__DENALI_PHY_1067_READ_MASK 0x001F07FFU +#define LPDDR4__DENALI_PHY_1067_WRITE_MASK 0x001F07FFU +#define LPDDR4__DENALI_PHY_1067__PHY_ADR2_CLK_WR_SLAVE_DELAY_0_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1067__PHY_ADR2_CLK_WR_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1067__PHY_ADR2_CLK_WR_SLAVE_DELAY_0_WIDTH 11U +#define LPDDR4__PHY_ADR2_CLK_WR_SLAVE_DELAY_0__REG DENALI_PHY_1067 +#define LPDDR4__PHY_ADR2_CLK_WR_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1067__PHY_ADR2_CLK_WR_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_1067__PHY_ADR3_SW_WRADDR_SHIFT_0_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_1067__PHY_ADR3_SW_WRADDR_SHIFT_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1067__PHY_ADR3_SW_WRADDR_SHIFT_0_WIDTH 5U +#define LPDDR4__PHY_ADR3_SW_WRADDR_SHIFT_0__REG DENALI_PHY_1067 +#define LPDDR4__PHY_ADR3_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_1067__PHY_ADR3_SW_WRADDR_SHIFT_0 + +#define LPDDR4__DENALI_PHY_1068_READ_MASK 0x001F07FFU +#define LPDDR4__DENALI_PHY_1068_WRITE_MASK 0x001F07FFU +#define LPDDR4__DENALI_PHY_1068__PHY_ADR3_CLK_WR_SLAVE_DELAY_0_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1068__PHY_ADR3_CLK_WR_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1068__PHY_ADR3_CLK_WR_SLAVE_DELAY_0_WIDTH 11U +#define LPDDR4__PHY_ADR3_CLK_WR_SLAVE_DELAY_0__REG DENALI_PHY_1068 +#define LPDDR4__PHY_ADR3_CLK_WR_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1068__PHY_ADR3_CLK_WR_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_1068__PHY_ADR4_SW_WRADDR_SHIFT_0_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_1068__PHY_ADR4_SW_WRADDR_SHIFT_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1068__PHY_ADR4_SW_WRADDR_SHIFT_0_WIDTH 5U +#define LPDDR4__PHY_ADR4_SW_WRADDR_SHIFT_0__REG DENALI_PHY_1068 +#define LPDDR4__PHY_ADR4_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_1068__PHY_ADR4_SW_WRADDR_SHIFT_0 + +#define LPDDR4__DENALI_PHY_1069_READ_MASK 0x001F07FFU +#define LPDDR4__DENALI_PHY_1069_WRITE_MASK 0x001F07FFU +#define LPDDR4__DENALI_PHY_1069__PHY_ADR4_CLK_WR_SLAVE_DELAY_0_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1069__PHY_ADR4_CLK_WR_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1069__PHY_ADR4_CLK_WR_SLAVE_DELAY_0_WIDTH 11U +#define LPDDR4__PHY_ADR4_CLK_WR_SLAVE_DELAY_0__REG DENALI_PHY_1069 +#define LPDDR4__PHY_ADR4_CLK_WR_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1069__PHY_ADR4_CLK_WR_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_1069__PHY_ADR5_SW_WRADDR_SHIFT_0_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_1069__PHY_ADR5_SW_WRADDR_SHIFT_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1069__PHY_ADR5_SW_WRADDR_SHIFT_0_WIDTH 5U +#define LPDDR4__PHY_ADR5_SW_WRADDR_SHIFT_0__REG DENALI_PHY_1069 +#define LPDDR4__PHY_ADR5_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_1069__PHY_ADR5_SW_WRADDR_SHIFT_0 + +#define LPDDR4__DENALI_PHY_1070_READ_MASK 0x000F07FFU +#define LPDDR4__DENALI_PHY_1070_WRITE_MASK 0x000F07FFU +#define LPDDR4__DENALI_PHY_1070__PHY_ADR5_CLK_WR_SLAVE_DELAY_0_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1070__PHY_ADR5_CLK_WR_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1070__PHY_ADR5_CLK_WR_SLAVE_DELAY_0_WIDTH 11U +#define LPDDR4__PHY_ADR5_CLK_WR_SLAVE_DELAY_0__REG DENALI_PHY_1070 +#define LPDDR4__PHY_ADR5_CLK_WR_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1070__PHY_ADR5_CLK_WR_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_1070__PHY_ADR_SW_MASTER_MODE_0_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_1070__PHY_ADR_SW_MASTER_MODE_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1070__PHY_ADR_SW_MASTER_MODE_0_WIDTH 4U +#define LPDDR4__PHY_ADR_SW_MASTER_MODE_0__REG DENALI_PHY_1070 +#define LPDDR4__PHY_ADR_SW_MASTER_MODE_0__FLD LPDDR4__DENALI_PHY_1070__PHY_ADR_SW_MASTER_MODE_0 + +#define LPDDR4__DENALI_PHY_1071_READ_MASK 0xFF3F07FFU +#define LPDDR4__DENALI_PHY_1071_WRITE_MASK 0xFF3F07FFU +#define LPDDR4__DENALI_PHY_1071__PHY_ADR_MASTER_DELAY_START_0_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1071__PHY_ADR_MASTER_DELAY_START_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1071__PHY_ADR_MASTER_DELAY_START_0_WIDTH 11U +#define LPDDR4__PHY_ADR_MASTER_DELAY_START_0__REG DENALI_PHY_1071 +#define LPDDR4__PHY_ADR_MASTER_DELAY_START_0__FLD LPDDR4__DENALI_PHY_1071__PHY_ADR_MASTER_DELAY_START_0 + +#define LPDDR4__DENALI_PHY_1071__PHY_ADR_MASTER_DELAY_STEP_0_MASK 0x003F0000U +#define LPDDR4__DENALI_PHY_1071__PHY_ADR_MASTER_DELAY_STEP_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1071__PHY_ADR_MASTER_DELAY_STEP_0_WIDTH 6U +#define LPDDR4__PHY_ADR_MASTER_DELAY_STEP_0__REG DENALI_PHY_1071 +#define LPDDR4__PHY_ADR_MASTER_DELAY_STEP_0__FLD LPDDR4__DENALI_PHY_1071__PHY_ADR_MASTER_DELAY_STEP_0 + +#define LPDDR4__DENALI_PHY_1071__PHY_ADR_MASTER_DELAY_WAIT_0_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_1071__PHY_ADR_MASTER_DELAY_WAIT_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_1071__PHY_ADR_MASTER_DELAY_WAIT_0_WIDTH 8U +#define LPDDR4__PHY_ADR_MASTER_DELAY_WAIT_0__REG DENALI_PHY_1071 +#define LPDDR4__PHY_ADR_MASTER_DELAY_WAIT_0__FLD LPDDR4__DENALI_PHY_1071__PHY_ADR_MASTER_DELAY_WAIT_0 + +#define LPDDR4__DENALI_PHY_1072_READ_MASK 0x0103FFFFU +#define LPDDR4__DENALI_PHY_1072_WRITE_MASK 0x0103FFFFU +#define LPDDR4__DENALI_PHY_1072__PHY_ADR_MASTER_DELAY_HALF_MEASURE_0_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_1072__PHY_ADR_MASTER_DELAY_HALF_MEASURE_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1072__PHY_ADR_MASTER_DELAY_HALF_MEASURE_0_WIDTH 8U +#define LPDDR4__PHY_ADR_MASTER_DELAY_HALF_MEASURE_0__REG DENALI_PHY_1072 +#define LPDDR4__PHY_ADR_MASTER_DELAY_HALF_MEASURE_0__FLD LPDDR4__DENALI_PHY_1072__PHY_ADR_MASTER_DELAY_HALF_MEASURE_0 + +#define LPDDR4__DENALI_PHY_1072__PHY_ADR_SW_CALVL_DVW_MIN_0_MASK 0x0003FF00U +#define LPDDR4__DENALI_PHY_1072__PHY_ADR_SW_CALVL_DVW_MIN_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_1072__PHY_ADR_SW_CALVL_DVW_MIN_0_WIDTH 10U +#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_0__REG DENALI_PHY_1072 +#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_0__FLD LPDDR4__DENALI_PHY_1072__PHY_ADR_SW_CALVL_DVW_MIN_0 + +#define LPDDR4__DENALI_PHY_1072__PHY_ADR_SW_CALVL_DVW_MIN_EN_0_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_1072__PHY_ADR_SW_CALVL_DVW_MIN_EN_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_1072__PHY_ADR_SW_CALVL_DVW_MIN_EN_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_1072__PHY_ADR_SW_CALVL_DVW_MIN_EN_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_1072__PHY_ADR_SW_CALVL_DVW_MIN_EN_0_WOSET 0U +#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_EN_0__REG DENALI_PHY_1072 +#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_EN_0__FLD LPDDR4__DENALI_PHY_1072__PHY_ADR_SW_CALVL_DVW_MIN_EN_0 + +#define LPDDR4__DENALI_PHY_1073_READ_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_1073_WRITE_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_1073__PHY_ADR_CALVL_DLY_STEP_0_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_1073__PHY_ADR_CALVL_DLY_STEP_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1073__PHY_ADR_CALVL_DLY_STEP_0_WIDTH 4U +#define LPDDR4__PHY_ADR_CALVL_DLY_STEP_0__REG DENALI_PHY_1073 +#define LPDDR4__PHY_ADR_CALVL_DLY_STEP_0__FLD LPDDR4__DENALI_PHY_1073__PHY_ADR_CALVL_DLY_STEP_0 + +#define LPDDR4__DENALI_PHY_1074_READ_MASK 0x03FF010FU +#define LPDDR4__DENALI_PHY_1074_WRITE_MASK 0x03FF010FU +#define LPDDR4__DENALI_PHY_1074__PHY_ADR_CALVL_CAPTURE_CNT_0_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_1074__PHY_ADR_CALVL_CAPTURE_CNT_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1074__PHY_ADR_CALVL_CAPTURE_CNT_0_WIDTH 4U +#define LPDDR4__PHY_ADR_CALVL_CAPTURE_CNT_0__REG DENALI_PHY_1074 +#define LPDDR4__PHY_ADR_CALVL_CAPTURE_CNT_0__FLD LPDDR4__DENALI_PHY_1074__PHY_ADR_CALVL_CAPTURE_CNT_0 + +#define LPDDR4__DENALI_PHY_1074__PHY_ADR_MEAS_DLY_STEP_ENABLE_0_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_1074__PHY_ADR_MEAS_DLY_STEP_ENABLE_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_1074__PHY_ADR_MEAS_DLY_STEP_ENABLE_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_1074__PHY_ADR_MEAS_DLY_STEP_ENABLE_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_1074__PHY_ADR_MEAS_DLY_STEP_ENABLE_0_WOSET 0U +#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_ENABLE_0__REG DENALI_PHY_1074 +#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_ENABLE_0__FLD LPDDR4__DENALI_PHY_1074__PHY_ADR_MEAS_DLY_STEP_ENABLE_0 + +#define LPDDR4__DENALI_PHY_1074__PHY_ADR_DC_INIT_SLV_DELAY_0_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_1074__PHY_ADR_DC_INIT_SLV_DELAY_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1074__PHY_ADR_DC_INIT_SLV_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_ADR_DC_INIT_SLV_DELAY_0__REG DENALI_PHY_1074 +#define LPDDR4__PHY_ADR_DC_INIT_SLV_DELAY_0__FLD LPDDR4__DENALI_PHY_1074__PHY_ADR_DC_INIT_SLV_DELAY_0 + +#define LPDDR4__DENALI_PHY_1075_READ_MASK 0x0000FF01U +#define LPDDR4__DENALI_PHY_1075_WRITE_MASK 0x0000FF01U +#define LPDDR4__DENALI_PHY_1075__PHY_ADR_DC_CALVL_ENABLE_0_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_1075__PHY_ADR_DC_CALVL_ENABLE_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1075__PHY_ADR_DC_CALVL_ENABLE_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_1075__PHY_ADR_DC_CALVL_ENABLE_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_1075__PHY_ADR_DC_CALVL_ENABLE_0_WOSET 0U +#define LPDDR4__PHY_ADR_DC_CALVL_ENABLE_0__REG DENALI_PHY_1075 +#define LPDDR4__PHY_ADR_DC_CALVL_ENABLE_0__FLD LPDDR4__DENALI_PHY_1075__PHY_ADR_DC_CALVL_ENABLE_0 + +#define LPDDR4__DENALI_PHY_1075__PHY_ADR_DC_DM_CLK_THRSHLD_0_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_1075__PHY_ADR_DC_DM_CLK_THRSHLD_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_1075__PHY_ADR_DC_DM_CLK_THRSHLD_0_WIDTH 8U +#define LPDDR4__PHY_ADR_DC_DM_CLK_THRSHLD_0__REG DENALI_PHY_1075 +#define LPDDR4__PHY_ADR_DC_DM_CLK_THRSHLD_0__FLD LPDDR4__DENALI_PHY_1075__PHY_ADR_DC_DM_CLK_THRSHLD_0 + +#endif /* REG_LPDDR4_ADDRESS_SLICE_0_MACROS_H_ */ diff --git a/drivers/ram/k3-j721e/lpddr4_ctl_regs.h b/drivers/ram/k3-j721e/lpddr4_ctl_regs.h new file mode 100644 index 0000000..213e569 --- /dev/null +++ b/drivers/ram/k3-j721e/lpddr4_ctl_regs.h @@ -0,0 +1,1546 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/********************************************************************** + * Copyright (C) 2012-2019 Cadence Design Systems, Inc. + * + * THIS FILE IS AUTOMATICALLY GENERATED, DO NOT EDIT + * + ********************************************************************** + */ + +#ifndef REG_LPDDR4_CTL_REGS_H_ +#define REG_LPDDR4_CTL_REGS_H_ + +#include "lpddr4_ddr_controller_macros.h" +#include "lpddr4_pi_macros.h" +#include "lpddr4_data_slice_0_macros.h" +#include "lpddr4_data_slice_1_macros.h" +#include "lpddr4_data_slice_2_macros.h" +#include "lpddr4_data_slice_3_macros.h" +#include "lpddr4_address_slice_0_macros.h" +#include "lpddr4_phy_core_macros.h" + +typedef struct __attribute__((packed)) lpddr4_ctlregs_s { + volatile uint32_t DENALI_CTL_0; + volatile uint32_t DENALI_CTL_1; + volatile uint32_t DENALI_CTL_2; + volatile uint32_t DENALI_CTL_3; + volatile uint32_t DENALI_CTL_4; + volatile uint32_t DENALI_CTL_5; + volatile uint32_t DENALI_CTL_6; + volatile uint32_t DENALI_CTL_7; + volatile uint32_t DENALI_CTL_8; + volatile uint32_t DENALI_CTL_9; + volatile uint32_t DENALI_CTL_10; + volatile uint32_t DENALI_CTL_11; + volatile uint32_t DENALI_CTL_12; + volatile uint32_t DENALI_CTL_13; + volatile uint32_t DENALI_CTL_14; + volatile uint32_t DENALI_CTL_15; + volatile uint32_t DENALI_CTL_16; + volatile uint32_t DENALI_CTL_17; + volatile uint32_t DENALI_CTL_18; + volatile uint32_t DENALI_CTL_19; + volatile uint32_t DENALI_CTL_20; + volatile uint32_t DENALI_CTL_21; + volatile uint32_t DENALI_CTL_22; + volatile uint32_t DENALI_CTL_23; + volatile uint32_t DENALI_CTL_24; + volatile uint32_t DENALI_CTL_25; + volatile uint32_t DENALI_CTL_26; + volatile uint32_t DENALI_CTL_27; + volatile uint32_t DENALI_CTL_28; + volatile uint32_t DENALI_CTL_29; + volatile uint32_t DENALI_CTL_30; + volatile uint32_t DENALI_CTL_31; + volatile uint32_t DENALI_CTL_32; + volatile uint32_t DENALI_CTL_33; + volatile uint32_t DENALI_CTL_34; + volatile uint32_t DENALI_CTL_35; + volatile uint32_t DENALI_CTL_36; + volatile uint32_t DENALI_CTL_37; + volatile uint32_t DENALI_CTL_38; + volatile uint32_t DENALI_CTL_39; + volatile uint32_t DENALI_CTL_40; + volatile uint32_t DENALI_CTL_41; + volatile uint32_t DENALI_CTL_42; + volatile uint32_t DENALI_CTL_43; + volatile uint32_t DENALI_CTL_44; + volatile uint32_t DENALI_CTL_45; + volatile uint32_t DENALI_CTL_46; + volatile uint32_t DENALI_CTL_47; + volatile uint32_t DENALI_CTL_48; + volatile uint32_t DENALI_CTL_49; + volatile uint32_t DENALI_CTL_50; + volatile uint32_t DENALI_CTL_51; + volatile uint32_t DENALI_CTL_52; + volatile uint32_t DENALI_CTL_53; + volatile uint32_t DENALI_CTL_54; + volatile uint32_t DENALI_CTL_55; + volatile uint32_t DENALI_CTL_56; + volatile uint32_t DENALI_CTL_57; + volatile uint32_t DENALI_CTL_58; + volatile uint32_t DENALI_CTL_59; + volatile uint32_t DENALI_CTL_60; + volatile uint32_t DENALI_CTL_61; + volatile uint32_t DENALI_CTL_62; + volatile uint32_t DENALI_CTL_63; + volatile uint32_t DENALI_CTL_64; + volatile uint32_t DENALI_CTL_65; + volatile uint32_t DENALI_CTL_66; + volatile uint32_t DENALI_CTL_67; + volatile uint32_t DENALI_CTL_68; + volatile uint32_t DENALI_CTL_69; + volatile uint32_t DENALI_CTL_70; + volatile uint32_t DENALI_CTL_71; + volatile uint32_t DENALI_CTL_72; + volatile uint32_t DENALI_CTL_73; + volatile uint32_t DENALI_CTL_74; + volatile uint32_t DENALI_CTL_75; + volatile uint32_t DENALI_CTL_76; + volatile uint32_t DENALI_CTL_77; + volatile uint32_t DENALI_CTL_78; + volatile uint32_t DENALI_CTL_79; + volatile uint32_t DENALI_CTL_80; + volatile uint32_t DENALI_CTL_81; + volatile uint32_t DENALI_CTL_82; + volatile uint32_t DENALI_CTL_83; + volatile uint32_t DENALI_CTL_84; + volatile uint32_t DENALI_CTL_85; + volatile uint32_t DENALI_CTL_86; + volatile uint32_t DENALI_CTL_87; + volatile uint32_t DENALI_CTL_88; + volatile uint32_t DENALI_CTL_89; + volatile uint32_t DENALI_CTL_90; + volatile uint32_t DENALI_CTL_91; + volatile uint32_t DENALI_CTL_92; + volatile uint32_t DENALI_CTL_93; + volatile uint32_t DENALI_CTL_94; + volatile uint32_t DENALI_CTL_95; + volatile uint32_t DENALI_CTL_96; + volatile uint32_t DENALI_CTL_97; + volatile uint32_t DENALI_CTL_98; + volatile uint32_t DENALI_CTL_99; + volatile uint32_t DENALI_CTL_100; + volatile uint32_t DENALI_CTL_101; + volatile uint32_t DENALI_CTL_102; + volatile uint32_t DENALI_CTL_103; + volatile uint32_t DENALI_CTL_104; + volatile uint32_t DENALI_CTL_105; + volatile uint32_t DENALI_CTL_106; + volatile uint32_t DENALI_CTL_107; + volatile uint32_t DENALI_CTL_108; + volatile uint32_t DENALI_CTL_109; + volatile uint32_t DENALI_CTL_110; + volatile uint32_t DENALI_CTL_111; + volatile uint32_t DENALI_CTL_112; + volatile uint32_t DENALI_CTL_113; + volatile uint32_t DENALI_CTL_114; + volatile uint32_t DENALI_CTL_115; + volatile uint32_t DENALI_CTL_116; + volatile uint32_t DENALI_CTL_117; + volatile uint32_t DENALI_CTL_118; + volatile uint32_t DENALI_CTL_119; + volatile uint32_t DENALI_CTL_120; + volatile uint32_t DENALI_CTL_121; + volatile uint32_t DENALI_CTL_122; + volatile uint32_t DENALI_CTL_123; + volatile uint32_t DENALI_CTL_124; + volatile uint32_t DENALI_CTL_125; + volatile uint32_t DENALI_CTL_126; + volatile uint32_t DENALI_CTL_127; + volatile uint32_t DENALI_CTL_128; + volatile uint32_t DENALI_CTL_129; + volatile uint32_t DENALI_CTL_130; + volatile uint32_t DENALI_CTL_131; + volatile uint32_t DENALI_CTL_132; + volatile uint32_t DENALI_CTL_133; + volatile uint32_t DENALI_CTL_134; + volatile uint32_t DENALI_CTL_135; + volatile uint32_t DENALI_CTL_136; + volatile uint32_t DENALI_CTL_137; + volatile uint32_t DENALI_CTL_138; + volatile uint32_t DENALI_CTL_139; + volatile uint32_t DENALI_CTL_140; + volatile uint32_t DENALI_CTL_141; + volatile uint32_t DENALI_CTL_142; + volatile uint32_t DENALI_CTL_143; + volatile uint32_t DENALI_CTL_144; + volatile uint32_t DENALI_CTL_145; + volatile uint32_t DENALI_CTL_146; + volatile uint32_t DENALI_CTL_147; + volatile uint32_t DENALI_CTL_148; + volatile uint32_t DENALI_CTL_149; + volatile uint32_t DENALI_CTL_150; + volatile uint32_t DENALI_CTL_151; + volatile uint32_t DENALI_CTL_152; + volatile uint32_t DENALI_CTL_153; + volatile uint32_t DENALI_CTL_154; + volatile uint32_t DENALI_CTL_155; + volatile uint32_t DENALI_CTL_156; + volatile uint32_t DENALI_CTL_157; + volatile uint32_t DENALI_CTL_158; + volatile uint32_t DENALI_CTL_159; + volatile uint32_t DENALI_CTL_160; + volatile uint32_t DENALI_CTL_161; + volatile uint32_t DENALI_CTL_162; + volatile uint32_t DENALI_CTL_163; + volatile uint32_t DENALI_CTL_164; + volatile uint32_t DENALI_CTL_165; + volatile uint32_t DENALI_CTL_166; + volatile uint32_t DENALI_CTL_167; + volatile uint32_t DENALI_CTL_168; + volatile uint32_t DENALI_CTL_169; + volatile uint32_t DENALI_CTL_170; + volatile uint32_t DENALI_CTL_171; + volatile uint32_t DENALI_CTL_172; + volatile uint32_t DENALI_CTL_173; + volatile uint32_t DENALI_CTL_174; + volatile uint32_t DENALI_CTL_175; + volatile uint32_t DENALI_CTL_176; + volatile uint32_t DENALI_CTL_177; + volatile uint32_t DENALI_CTL_178; + volatile uint32_t DENALI_CTL_179; + volatile uint32_t DENALI_CTL_180; + volatile uint32_t DENALI_CTL_181; + volatile uint32_t DENALI_CTL_182; + volatile uint32_t DENALI_CTL_183; + volatile uint32_t DENALI_CTL_184; + volatile uint32_t DENALI_CTL_185; + volatile uint32_t DENALI_CTL_186; + volatile uint32_t DENALI_CTL_187; + volatile uint32_t DENALI_CTL_188; + volatile uint32_t DENALI_CTL_189; + volatile uint32_t DENALI_CTL_190; + volatile uint32_t DENALI_CTL_191; + volatile uint32_t DENALI_CTL_192; + volatile uint32_t DENALI_CTL_193; + volatile uint32_t DENALI_CTL_194; + volatile uint32_t DENALI_CTL_195; + volatile uint32_t DENALI_CTL_196; + volatile uint32_t DENALI_CTL_197; + volatile uint32_t DENALI_CTL_198; + volatile uint32_t DENALI_CTL_199; + volatile uint32_t DENALI_CTL_200; + volatile uint32_t DENALI_CTL_201; + volatile uint32_t DENALI_CTL_202; + volatile uint32_t DENALI_CTL_203; + volatile uint32_t DENALI_CTL_204; + volatile uint32_t DENALI_CTL_205; + volatile uint32_t DENALI_CTL_206; + volatile uint32_t DENALI_CTL_207; + volatile uint32_t DENALI_CTL_208; + volatile uint32_t DENALI_CTL_209; + volatile uint32_t DENALI_CTL_210; + volatile uint32_t DENALI_CTL_211; + volatile uint32_t DENALI_CTL_212; + volatile uint32_t DENALI_CTL_213; + volatile uint32_t DENALI_CTL_214; + volatile uint32_t DENALI_CTL_215; + volatile uint32_t DENALI_CTL_216; + volatile uint32_t DENALI_CTL_217; + volatile uint32_t DENALI_CTL_218; + volatile uint32_t DENALI_CTL_219; + volatile uint32_t DENALI_CTL_220; + volatile uint32_t DENALI_CTL_221; + volatile uint32_t DENALI_CTL_222; + volatile uint32_t DENALI_CTL_223; + volatile uint32_t DENALI_CTL_224; + volatile uint32_t DENALI_CTL_225; + volatile uint32_t DENALI_CTL_226; + volatile uint32_t DENALI_CTL_227; + volatile uint32_t DENALI_CTL_228; + volatile uint32_t DENALI_CTL_229; + volatile uint32_t DENALI_CTL_230; + volatile uint32_t DENALI_CTL_231; + volatile uint32_t DENALI_CTL_232; + volatile uint32_t DENALI_CTL_233; + volatile uint32_t DENALI_CTL_234; + volatile uint32_t DENALI_CTL_235; + volatile uint32_t DENALI_CTL_236; + volatile uint32_t DENALI_CTL_237; + volatile uint32_t DENALI_CTL_238; + volatile uint32_t DENALI_CTL_239; + volatile uint32_t DENALI_CTL_240; + volatile uint32_t DENALI_CTL_241; + volatile uint32_t DENALI_CTL_242; + volatile uint32_t DENALI_CTL_243; + volatile uint32_t DENALI_CTL_244; + volatile uint32_t DENALI_CTL_245; + volatile uint32_t DENALI_CTL_246; + volatile uint32_t DENALI_CTL_247; + volatile uint32_t DENALI_CTL_248; + volatile uint32_t DENALI_CTL_249; + volatile uint32_t DENALI_CTL_250; + volatile uint32_t DENALI_CTL_251; + volatile uint32_t DENALI_CTL_252; + volatile uint32_t DENALI_CTL_253; + volatile uint32_t DENALI_CTL_254; + volatile uint32_t DENALI_CTL_255; + volatile uint32_t DENALI_CTL_256; + volatile uint32_t DENALI_CTL_257; + volatile uint32_t DENALI_CTL_258; + volatile uint32_t DENALI_CTL_259; + volatile uint32_t DENALI_CTL_260; + volatile uint32_t DENALI_CTL_261; + volatile uint32_t DENALI_CTL_262; + volatile uint32_t DENALI_CTL_263; + volatile uint32_t DENALI_CTL_264; + volatile uint32_t DENALI_CTL_265; + volatile uint32_t DENALI_CTL_266; + volatile uint32_t DENALI_CTL_267; + volatile uint32_t DENALI_CTL_268; + volatile uint32_t DENALI_CTL_269; + volatile uint32_t DENALI_CTL_270; + volatile uint32_t DENALI_CTL_271; + volatile uint32_t DENALI_CTL_272; + volatile uint32_t DENALI_CTL_273; + volatile uint32_t DENALI_CTL_274; + volatile uint32_t DENALI_CTL_275; + volatile uint32_t DENALI_CTL_276; + volatile uint32_t DENALI_CTL_277; + volatile uint32_t DENALI_CTL_278; + volatile uint32_t DENALI_CTL_279; + volatile uint32_t DENALI_CTL_280; + volatile uint32_t DENALI_CTL_281; + volatile uint32_t DENALI_CTL_282; + volatile uint32_t DENALI_CTL_283; + volatile uint32_t DENALI_CTL_284; + volatile uint32_t DENALI_CTL_285; + volatile uint32_t DENALI_CTL_286; + volatile uint32_t DENALI_CTL_287; + volatile uint32_t DENALI_CTL_288; + volatile uint32_t DENALI_CTL_289; + volatile uint32_t DENALI_CTL_290; + volatile uint32_t DENALI_CTL_291; + volatile uint32_t DENALI_CTL_292; + volatile uint32_t DENALI_CTL_293; + volatile uint32_t DENALI_CTL_294; + volatile uint32_t DENALI_CTL_295; + volatile uint32_t DENALI_CTL_296; + volatile uint32_t DENALI_CTL_297; + volatile uint32_t DENALI_CTL_298; + volatile uint32_t DENALI_CTL_299; + volatile uint32_t DENALI_CTL_300; + volatile uint32_t DENALI_CTL_301; + volatile uint32_t DENALI_CTL_302; + volatile uint32_t DENALI_CTL_303; + volatile uint32_t DENALI_CTL_304; + volatile uint32_t DENALI_CTL_305; + volatile uint32_t DENALI_CTL_306; + volatile uint32_t DENALI_CTL_307; + volatile uint32_t DENALI_CTL_308; + volatile uint32_t DENALI_CTL_309; + volatile uint32_t DENALI_CTL_310; + volatile uint32_t DENALI_CTL_311; + volatile uint32_t DENALI_CTL_312; + volatile uint32_t DENALI_CTL_313; + volatile uint32_t DENALI_CTL_314; + volatile uint32_t DENALI_CTL_315; + volatile uint32_t DENALI_CTL_316; + volatile uint32_t DENALI_CTL_317; + volatile uint32_t DENALI_CTL_318; + volatile uint32_t DENALI_CTL_319; + volatile uint32_t DENALI_CTL_320; + volatile uint32_t DENALI_CTL_321; + volatile uint32_t DENALI_CTL_322; + volatile uint32_t DENALI_CTL_323; + volatile uint32_t DENALI_CTL_324; + volatile uint32_t DENALI_CTL_325; + volatile uint32_t DENALI_CTL_326; + volatile uint32_t DENALI_CTL_327; + volatile uint32_t DENALI_CTL_328; + volatile uint32_t DENALI_CTL_329; + volatile uint32_t DENALI_CTL_330; + volatile uint32_t DENALI_CTL_331; + volatile uint32_t DENALI_CTL_332; + volatile uint32_t DENALI_CTL_333; + volatile uint32_t DENALI_CTL_334; + volatile uint32_t DENALI_CTL_335; + volatile uint32_t DENALI_CTL_336; + volatile uint32_t DENALI_CTL_337; + volatile uint32_t DENALI_CTL_338; + volatile uint32_t DENALI_CTL_339; + volatile uint32_t DENALI_CTL_340; + volatile uint32_t DENALI_CTL_341; + volatile uint32_t DENALI_CTL_342; + volatile uint32_t DENALI_CTL_343; + volatile uint32_t DENALI_CTL_344; + volatile uint32_t DENALI_CTL_345; + volatile uint32_t DENALI_CTL_346; + volatile uint32_t DENALI_CTL_347; + volatile uint32_t DENALI_CTL_348; + volatile uint32_t DENALI_CTL_349; + volatile uint32_t DENALI_CTL_350; + volatile uint32_t DENALI_CTL_351; + volatile uint32_t DENALI_CTL_352; + volatile uint32_t DENALI_CTL_353; + volatile uint32_t DENALI_CTL_354; + volatile uint32_t DENALI_CTL_355; + volatile uint32_t DENALI_CTL_356; + volatile uint32_t DENALI_CTL_357; + volatile uint32_t DENALI_CTL_358; + volatile uint32_t DENALI_CTL_359; + volatile uint32_t DENALI_CTL_360; + volatile uint32_t DENALI_CTL_361; + volatile uint32_t DENALI_CTL_362; + volatile uint32_t DENALI_CTL_363; + volatile uint32_t DENALI_CTL_364; + volatile uint32_t DENALI_CTL_365; + volatile uint32_t DENALI_CTL_366; + volatile uint32_t DENALI_CTL_367; + volatile uint32_t DENALI_CTL_368; + volatile uint32_t DENALI_CTL_369; + volatile uint32_t DENALI_CTL_370; + volatile uint32_t DENALI_CTL_371; + volatile uint32_t DENALI_CTL_372; + volatile uint32_t DENALI_CTL_373; + volatile uint32_t DENALI_CTL_374; + volatile uint32_t DENALI_CTL_375; + volatile uint32_t DENALI_CTL_376; + volatile uint32_t DENALI_CTL_377; + volatile uint32_t DENALI_CTL_378; + volatile uint32_t DENALI_CTL_379; + volatile uint32_t DENALI_CTL_380; + volatile uint32_t DENALI_CTL_381; + volatile uint32_t DENALI_CTL_382; + volatile uint32_t DENALI_CTL_383; + volatile uint32_t DENALI_CTL_384; + volatile uint32_t DENALI_CTL_385; + volatile uint32_t DENALI_CTL_386; + volatile uint32_t DENALI_CTL_387; + volatile uint32_t DENALI_CTL_388; + volatile uint32_t DENALI_CTL_389; + volatile uint32_t DENALI_CTL_390; + volatile uint32_t DENALI_CTL_391; + volatile uint32_t DENALI_CTL_392; + volatile uint32_t DENALI_CTL_393; + volatile uint32_t DENALI_CTL_394; + volatile uint32_t DENALI_CTL_395; + volatile uint32_t DENALI_CTL_396; + volatile uint32_t DENALI_CTL_397; + volatile uint32_t DENALI_CTL_398; + volatile uint32_t DENALI_CTL_399; + volatile uint32_t DENALI_CTL_400; + volatile uint32_t DENALI_CTL_401; + volatile uint32_t DENALI_CTL_402; + volatile uint32_t DENALI_CTL_403; + volatile uint32_t DENALI_CTL_404; + volatile uint32_t DENALI_CTL_405; + volatile uint32_t DENALI_CTL_406; + volatile uint32_t DENALI_CTL_407; + volatile uint32_t DENALI_CTL_408; + volatile uint32_t DENALI_CTL_409; + volatile uint32_t DENALI_CTL_410; + volatile uint32_t DENALI_CTL_411; + volatile uint32_t DENALI_CTL_412; + volatile uint32_t DENALI_CTL_413; + volatile uint32_t DENALI_CTL_414; + volatile uint32_t DENALI_CTL_415; + volatile uint32_t DENALI_CTL_416; + volatile uint32_t DENALI_CTL_417; + volatile uint32_t DENALI_CTL_418; + volatile uint32_t DENALI_CTL_419; + volatile uint32_t DENALI_CTL_420; + volatile uint32_t DENALI_CTL_421; + volatile uint32_t DENALI_CTL_422; + volatile uint32_t DENALI_CTL_423; + volatile uint32_t DENALI_CTL_424; + volatile uint32_t DENALI_CTL_425; + volatile uint32_t DENALI_CTL_426; + volatile uint32_t DENALI_CTL_427; + volatile uint32_t DENALI_CTL_428; + volatile uint32_t DENALI_CTL_429; + volatile uint32_t DENALI_CTL_430; + volatile uint32_t DENALI_CTL_431; + volatile uint32_t DENALI_CTL_432; + volatile uint32_t DENALI_CTL_433; + volatile uint32_t DENALI_CTL_434; + volatile uint32_t DENALI_CTL_435; + volatile uint32_t DENALI_CTL_436; + volatile uint32_t DENALI_CTL_437; + volatile uint32_t DENALI_CTL_438; + volatile uint32_t DENALI_CTL_439; + volatile uint32_t DENALI_CTL_440; + volatile uint32_t DENALI_CTL_441; + volatile uint32_t DENALI_CTL_442; + volatile uint32_t DENALI_CTL_443; + volatile uint32_t DENALI_CTL_444; + volatile uint32_t DENALI_CTL_445; + volatile uint32_t DENALI_CTL_446; + volatile uint32_t DENALI_CTL_447; + volatile uint32_t DENALI_CTL_448; + volatile uint32_t DENALI_CTL_449; + volatile uint32_t DENALI_CTL_450; + volatile uint32_t DENALI_CTL_451; + volatile uint32_t DENALI_CTL_452; + volatile uint32_t DENALI_CTL_453; + volatile uint32_t DENALI_CTL_454; + volatile uint32_t DENALI_CTL_455; + volatile uint32_t DENALI_CTL_456; + volatile uint32_t DENALI_CTL_457; + volatile uint32_t DENALI_CTL_458; + volatile char pad__0[0x18D4U]; + volatile uint32_t DENALI_PI_0; + volatile uint32_t DENALI_PI_1; + volatile uint32_t DENALI_PI_2; + volatile uint32_t DENALI_PI_3; + volatile uint32_t DENALI_PI_4; + volatile uint32_t DENALI_PI_5; + volatile uint32_t DENALI_PI_6; + volatile uint32_t DENALI_PI_7; + volatile uint32_t DENALI_PI_8; + volatile uint32_t DENALI_PI_9; + volatile uint32_t DENALI_PI_10; + volatile uint32_t DENALI_PI_11; + volatile uint32_t DENALI_PI_12; + volatile uint32_t DENALI_PI_13; + volatile uint32_t DENALI_PI_14; + volatile uint32_t DENALI_PI_15; + volatile uint32_t DENALI_PI_16; + volatile uint32_t DENALI_PI_17; + volatile uint32_t DENALI_PI_18; + volatile uint32_t DENALI_PI_19; + volatile uint32_t DENALI_PI_20; + volatile uint32_t DENALI_PI_21; + volatile uint32_t DENALI_PI_22; + volatile uint32_t DENALI_PI_23; + volatile uint32_t DENALI_PI_24; + volatile uint32_t DENALI_PI_25; + volatile uint32_t DENALI_PI_26; + volatile uint32_t DENALI_PI_27; + volatile uint32_t DENALI_PI_28; + volatile uint32_t DENALI_PI_29; + volatile uint32_t DENALI_PI_30; + volatile uint32_t DENALI_PI_31; + volatile uint32_t DENALI_PI_32; + volatile uint32_t DENALI_PI_33; + volatile uint32_t DENALI_PI_34; + volatile uint32_t DENALI_PI_35; + volatile uint32_t DENALI_PI_36; + volatile uint32_t DENALI_PI_37; + volatile uint32_t DENALI_PI_38; + volatile uint32_t DENALI_PI_39; + volatile uint32_t DENALI_PI_40; + volatile uint32_t DENALI_PI_41; + volatile uint32_t DENALI_PI_42; + volatile uint32_t DENALI_PI_43; + volatile uint32_t DENALI_PI_44; + volatile uint32_t DENALI_PI_45; + volatile uint32_t DENALI_PI_46; + volatile uint32_t DENALI_PI_47; + volatile uint32_t DENALI_PI_48; + volatile uint32_t DENALI_PI_49; + volatile uint32_t DENALI_PI_50; + volatile uint32_t DENALI_PI_51; + volatile uint32_t DENALI_PI_52; + volatile uint32_t DENALI_PI_53; + volatile uint32_t DENALI_PI_54; + volatile uint32_t DENALI_PI_55; + volatile uint32_t DENALI_PI_56; + volatile uint32_t DENALI_PI_57; + volatile uint32_t DENALI_PI_58; + volatile uint32_t DENALI_PI_59; + volatile uint32_t DENALI_PI_60; + volatile uint32_t DENALI_PI_61; + volatile uint32_t DENALI_PI_62; + volatile uint32_t DENALI_PI_63; + volatile uint32_t DENALI_PI_64; + volatile uint32_t DENALI_PI_65; + volatile uint32_t DENALI_PI_66; + volatile uint32_t DENALI_PI_67; + volatile uint32_t DENALI_PI_68; + volatile uint32_t DENALI_PI_69; + volatile uint32_t DENALI_PI_70; + volatile uint32_t DENALI_PI_71; + volatile uint32_t DENALI_PI_72; + volatile uint32_t DENALI_PI_73; + volatile uint32_t DENALI_PI_74; + volatile uint32_t DENALI_PI_75; + volatile uint32_t DENALI_PI_76; + volatile uint32_t DENALI_PI_77; + volatile uint32_t DENALI_PI_78; + volatile uint32_t DENALI_PI_79; + volatile uint32_t DENALI_PI_80; + volatile uint32_t DENALI_PI_81; + volatile uint32_t DENALI_PI_82; + volatile uint32_t DENALI_PI_83; + volatile uint32_t DENALI_PI_84; + volatile uint32_t DENALI_PI_85; + volatile uint32_t DENALI_PI_86; + volatile uint32_t DENALI_PI_87; + volatile uint32_t DENALI_PI_88; + volatile uint32_t DENALI_PI_89; + volatile uint32_t DENALI_PI_90; + volatile uint32_t DENALI_PI_91; + volatile uint32_t DENALI_PI_92; + volatile uint32_t DENALI_PI_93; + volatile uint32_t DENALI_PI_94; + volatile uint32_t DENALI_PI_95; + volatile uint32_t DENALI_PI_96; + volatile uint32_t DENALI_PI_97; + volatile uint32_t DENALI_PI_98; + volatile uint32_t DENALI_PI_99; + volatile uint32_t DENALI_PI_100; + volatile uint32_t DENALI_PI_101; + volatile uint32_t DENALI_PI_102; + volatile uint32_t DENALI_PI_103; + volatile uint32_t DENALI_PI_104; + volatile uint32_t DENALI_PI_105; + volatile uint32_t DENALI_PI_106; + volatile uint32_t DENALI_PI_107; + volatile uint32_t DENALI_PI_108; + volatile uint32_t DENALI_PI_109; + volatile uint32_t DENALI_PI_110; + volatile uint32_t DENALI_PI_111; + volatile uint32_t DENALI_PI_112; + volatile uint32_t DENALI_PI_113; + volatile uint32_t DENALI_PI_114; + volatile uint32_t DENALI_PI_115; + volatile uint32_t DENALI_PI_116; + volatile uint32_t DENALI_PI_117; + volatile uint32_t DENALI_PI_118; + volatile uint32_t DENALI_PI_119; + volatile uint32_t DENALI_PI_120; + volatile uint32_t DENALI_PI_121; + volatile uint32_t DENALI_PI_122; + volatile uint32_t DENALI_PI_123; + volatile uint32_t DENALI_PI_124; + volatile uint32_t DENALI_PI_125; + volatile uint32_t DENALI_PI_126; + volatile uint32_t DENALI_PI_127; + volatile uint32_t DENALI_PI_128; + volatile uint32_t DENALI_PI_129; + volatile uint32_t DENALI_PI_130; + volatile uint32_t DENALI_PI_131; + volatile uint32_t DENALI_PI_132; + volatile uint32_t DENALI_PI_133; + volatile uint32_t DENALI_PI_134; + volatile uint32_t DENALI_PI_135; + volatile uint32_t DENALI_PI_136; + volatile uint32_t DENALI_PI_137; + volatile uint32_t DENALI_PI_138; + volatile uint32_t DENALI_PI_139; + volatile uint32_t DENALI_PI_140; + volatile uint32_t DENALI_PI_141; + volatile uint32_t DENALI_PI_142; + volatile uint32_t DENALI_PI_143; + volatile uint32_t DENALI_PI_144; + volatile uint32_t DENALI_PI_145; + volatile uint32_t DENALI_PI_146; + volatile uint32_t DENALI_PI_147; + volatile uint32_t DENALI_PI_148; + volatile uint32_t DENALI_PI_149; + volatile uint32_t DENALI_PI_150; + volatile uint32_t DENALI_PI_151; + volatile uint32_t DENALI_PI_152; + volatile uint32_t DENALI_PI_153; + volatile uint32_t DENALI_PI_154; + volatile uint32_t DENALI_PI_155; + volatile uint32_t DENALI_PI_156; + volatile uint32_t DENALI_PI_157; + volatile uint32_t DENALI_PI_158; + volatile uint32_t DENALI_PI_159; + volatile uint32_t DENALI_PI_160; + volatile uint32_t DENALI_PI_161; + volatile uint32_t DENALI_PI_162; + volatile uint32_t DENALI_PI_163; + volatile uint32_t DENALI_PI_164; + volatile uint32_t DENALI_PI_165; + volatile uint32_t DENALI_PI_166; + volatile uint32_t DENALI_PI_167; + volatile uint32_t DENALI_PI_168; + volatile uint32_t DENALI_PI_169; + volatile uint32_t DENALI_PI_170; + volatile uint32_t DENALI_PI_171; + volatile uint32_t DENALI_PI_172; + volatile uint32_t DENALI_PI_173; + volatile uint32_t DENALI_PI_174; + volatile uint32_t DENALI_PI_175; + volatile uint32_t DENALI_PI_176; + volatile uint32_t DENALI_PI_177; + volatile uint32_t DENALI_PI_178; + volatile uint32_t DENALI_PI_179; + volatile uint32_t DENALI_PI_180; + volatile uint32_t DENALI_PI_181; + volatile uint32_t DENALI_PI_182; + volatile uint32_t DENALI_PI_183; + volatile uint32_t DENALI_PI_184; + volatile uint32_t DENALI_PI_185; + volatile uint32_t DENALI_PI_186; + volatile uint32_t DENALI_PI_187; + volatile uint32_t DENALI_PI_188; + volatile uint32_t DENALI_PI_189; + volatile uint32_t DENALI_PI_190; + volatile uint32_t DENALI_PI_191; + volatile uint32_t DENALI_PI_192; + volatile uint32_t DENALI_PI_193; + volatile uint32_t DENALI_PI_194; + volatile uint32_t DENALI_PI_195; + volatile uint32_t DENALI_PI_196; + volatile uint32_t DENALI_PI_197; + volatile uint32_t DENALI_PI_198; + volatile uint32_t DENALI_PI_199; + volatile uint32_t DENALI_PI_200; + volatile uint32_t DENALI_PI_201; + volatile uint32_t DENALI_PI_202; + volatile uint32_t DENALI_PI_203; + volatile uint32_t DENALI_PI_204; + volatile uint32_t DENALI_PI_205; + volatile uint32_t DENALI_PI_206; + volatile uint32_t DENALI_PI_207; + volatile uint32_t DENALI_PI_208; + volatile uint32_t DENALI_PI_209; + volatile uint32_t DENALI_PI_210; + volatile uint32_t DENALI_PI_211; + volatile uint32_t DENALI_PI_212; + volatile uint32_t DENALI_PI_213; + volatile uint32_t DENALI_PI_214; + volatile uint32_t DENALI_PI_215; + volatile uint32_t DENALI_PI_216; + volatile uint32_t DENALI_PI_217; + volatile uint32_t DENALI_PI_218; + volatile uint32_t DENALI_PI_219; + volatile uint32_t DENALI_PI_220; + volatile uint32_t DENALI_PI_221; + volatile uint32_t DENALI_PI_222; + volatile uint32_t DENALI_PI_223; + volatile uint32_t DENALI_PI_224; + volatile uint32_t DENALI_PI_225; + volatile uint32_t DENALI_PI_226; + volatile uint32_t DENALI_PI_227; + volatile uint32_t DENALI_PI_228; + volatile uint32_t DENALI_PI_229; + volatile uint32_t DENALI_PI_230; + volatile uint32_t DENALI_PI_231; + volatile uint32_t DENALI_PI_232; + volatile uint32_t DENALI_PI_233; + volatile uint32_t DENALI_PI_234; + volatile uint32_t DENALI_PI_235; + volatile uint32_t DENALI_PI_236; + volatile uint32_t DENALI_PI_237; + volatile uint32_t DENALI_PI_238; + volatile uint32_t DENALI_PI_239; + volatile uint32_t DENALI_PI_240; + volatile uint32_t DENALI_PI_241; + volatile uint32_t DENALI_PI_242; + volatile uint32_t DENALI_PI_243; + volatile uint32_t DENALI_PI_244; + volatile uint32_t DENALI_PI_245; + volatile uint32_t DENALI_PI_246; + volatile uint32_t DENALI_PI_247; + volatile uint32_t DENALI_PI_248; + volatile uint32_t DENALI_PI_249; + volatile uint32_t DENALI_PI_250; + volatile uint32_t DENALI_PI_251; + volatile uint32_t DENALI_PI_252; + volatile uint32_t DENALI_PI_253; + volatile uint32_t DENALI_PI_254; + volatile uint32_t DENALI_PI_255; + volatile uint32_t DENALI_PI_256; + volatile uint32_t DENALI_PI_257; + volatile uint32_t DENALI_PI_258; + volatile uint32_t DENALI_PI_259; + volatile uint32_t DENALI_PI_260; + volatile uint32_t DENALI_PI_261; + volatile uint32_t DENALI_PI_262; + volatile uint32_t DENALI_PI_263; + volatile uint32_t DENALI_PI_264; + volatile uint32_t DENALI_PI_265; + volatile uint32_t DENALI_PI_266; + volatile uint32_t DENALI_PI_267; + volatile uint32_t DENALI_PI_268; + volatile uint32_t DENALI_PI_269; + volatile uint32_t DENALI_PI_270; + volatile uint32_t DENALI_PI_271; + volatile uint32_t DENALI_PI_272; + volatile uint32_t DENALI_PI_273; + volatile uint32_t DENALI_PI_274; + volatile uint32_t DENALI_PI_275; + volatile uint32_t DENALI_PI_276; + volatile uint32_t DENALI_PI_277; + volatile uint32_t DENALI_PI_278; + volatile uint32_t DENALI_PI_279; + volatile uint32_t DENALI_PI_280; + volatile uint32_t DENALI_PI_281; + volatile uint32_t DENALI_PI_282; + volatile uint32_t DENALI_PI_283; + volatile uint32_t DENALI_PI_284; + volatile uint32_t DENALI_PI_285; + volatile uint32_t DENALI_PI_286; + volatile uint32_t DENALI_PI_287; + volatile uint32_t DENALI_PI_288; + volatile uint32_t DENALI_PI_289; + volatile uint32_t DENALI_PI_290; + volatile uint32_t DENALI_PI_291; + volatile uint32_t DENALI_PI_292; + volatile uint32_t DENALI_PI_293; + volatile uint32_t DENALI_PI_294; + volatile uint32_t DENALI_PI_295; + volatile uint32_t DENALI_PI_296; + volatile uint32_t DENALI_PI_297; + volatile uint32_t DENALI_PI_298; + volatile uint32_t DENALI_PI_299; + volatile char pad__1[0x1B50U]; + volatile uint32_t DENALI_PHY_0; + volatile uint32_t DENALI_PHY_1; + volatile uint32_t DENALI_PHY_2; + volatile uint32_t DENALI_PHY_3; + volatile uint32_t DENALI_PHY_4; + volatile uint32_t DENALI_PHY_5; + volatile uint32_t DENALI_PHY_6; + volatile uint32_t DENALI_PHY_7; + volatile uint32_t DENALI_PHY_8; + volatile uint32_t DENALI_PHY_9; + volatile uint32_t DENALI_PHY_10; + volatile uint32_t DENALI_PHY_11; + volatile uint32_t DENALI_PHY_12; + volatile uint32_t DENALI_PHY_13; + volatile uint32_t DENALI_PHY_14; + volatile uint32_t DENALI_PHY_15; + volatile uint32_t DENALI_PHY_16; + volatile uint32_t DENALI_PHY_17; + volatile uint32_t DENALI_PHY_18; + volatile uint32_t DENALI_PHY_19; + volatile uint32_t DENALI_PHY_20; + volatile uint32_t DENALI_PHY_21; + volatile uint32_t DENALI_PHY_22; + volatile uint32_t DENALI_PHY_23; + volatile uint32_t DENALI_PHY_24; + volatile uint32_t DENALI_PHY_25; + volatile uint32_t DENALI_PHY_26; + volatile uint32_t DENALI_PHY_27; + volatile uint32_t DENALI_PHY_28; + volatile uint32_t DENALI_PHY_29; + volatile uint32_t DENALI_PHY_30; + volatile uint32_t DENALI_PHY_31; + volatile uint32_t DENALI_PHY_32; + volatile uint32_t DENALI_PHY_33; + volatile uint32_t DENALI_PHY_34; + volatile uint32_t DENALI_PHY_35; + volatile uint32_t DENALI_PHY_36; + volatile uint32_t DENALI_PHY_37; + volatile uint32_t DENALI_PHY_38; + volatile uint32_t DENALI_PHY_39; + volatile uint32_t DENALI_PHY_40; + volatile uint32_t DENALI_PHY_41; + volatile uint32_t DENALI_PHY_42; + volatile uint32_t DENALI_PHY_43; + volatile uint32_t DENALI_PHY_44; + volatile uint32_t DENALI_PHY_45; + volatile uint32_t DENALI_PHY_46; + volatile uint32_t DENALI_PHY_47; + volatile uint32_t DENALI_PHY_48; + volatile uint32_t DENALI_PHY_49; + volatile uint32_t DENALI_PHY_50; + volatile uint32_t DENALI_PHY_51; + volatile uint32_t DENALI_PHY_52; + volatile uint32_t DENALI_PHY_53; + volatile uint32_t DENALI_PHY_54; + volatile uint32_t DENALI_PHY_55; + volatile uint32_t DENALI_PHY_56; + volatile uint32_t DENALI_PHY_57; + volatile uint32_t DENALI_PHY_58; + volatile uint32_t DENALI_PHY_59; + volatile uint32_t DENALI_PHY_60; + volatile uint32_t DENALI_PHY_61; + volatile uint32_t DENALI_PHY_62; + volatile uint32_t DENALI_PHY_63; + volatile uint32_t DENALI_PHY_64; + volatile uint32_t DENALI_PHY_65; + volatile uint32_t DENALI_PHY_66; + volatile uint32_t DENALI_PHY_67; + volatile uint32_t DENALI_PHY_68; + volatile uint32_t DENALI_PHY_69; + volatile uint32_t DENALI_PHY_70; + volatile uint32_t DENALI_PHY_71; + volatile uint32_t DENALI_PHY_72; + volatile uint32_t DENALI_PHY_73; + volatile uint32_t DENALI_PHY_74; + volatile uint32_t DENALI_PHY_75; + volatile uint32_t DENALI_PHY_76; + volatile uint32_t DENALI_PHY_77; + volatile uint32_t DENALI_PHY_78; + volatile uint32_t DENALI_PHY_79; + volatile uint32_t DENALI_PHY_80; + volatile uint32_t DENALI_PHY_81; + volatile uint32_t DENALI_PHY_82; + volatile uint32_t DENALI_PHY_83; + volatile uint32_t DENALI_PHY_84; + volatile uint32_t DENALI_PHY_85; + volatile uint32_t DENALI_PHY_86; + volatile uint32_t DENALI_PHY_87; + volatile uint32_t DENALI_PHY_88; + volatile uint32_t DENALI_PHY_89; + volatile uint32_t DENALI_PHY_90; + volatile uint32_t DENALI_PHY_91; + volatile uint32_t DENALI_PHY_92; + volatile uint32_t DENALI_PHY_93; + volatile uint32_t DENALI_PHY_94; + volatile uint32_t DENALI_PHY_95; + volatile uint32_t DENALI_PHY_96; + volatile uint32_t DENALI_PHY_97; + volatile uint32_t DENALI_PHY_98; + volatile uint32_t DENALI_PHY_99; + volatile uint32_t DENALI_PHY_100; + volatile uint32_t DENALI_PHY_101; + volatile uint32_t DENALI_PHY_102; + volatile uint32_t DENALI_PHY_103; + volatile uint32_t DENALI_PHY_104; + volatile uint32_t DENALI_PHY_105; + volatile uint32_t DENALI_PHY_106; + volatile uint32_t DENALI_PHY_107; + volatile uint32_t DENALI_PHY_108; + volatile uint32_t DENALI_PHY_109; + volatile uint32_t DENALI_PHY_110; + volatile uint32_t DENALI_PHY_111; + volatile uint32_t DENALI_PHY_112; + volatile uint32_t DENALI_PHY_113; + volatile uint32_t DENALI_PHY_114; + volatile uint32_t DENALI_PHY_115; + volatile uint32_t DENALI_PHY_116; + volatile uint32_t DENALI_PHY_117; + volatile uint32_t DENALI_PHY_118; + volatile uint32_t DENALI_PHY_119; + volatile uint32_t DENALI_PHY_120; + volatile uint32_t DENALI_PHY_121; + volatile uint32_t DENALI_PHY_122; + volatile uint32_t DENALI_PHY_123; + volatile uint32_t DENALI_PHY_124; + volatile uint32_t DENALI_PHY_125; + volatile uint32_t DENALI_PHY_126; + volatile uint32_t DENALI_PHY_127; + volatile uint32_t DENALI_PHY_128; + volatile uint32_t DENALI_PHY_129; + volatile uint32_t DENALI_PHY_130; + volatile uint32_t DENALI_PHY_131; + volatile uint32_t DENALI_PHY_132; + volatile uint32_t DENALI_PHY_133; + volatile uint32_t DENALI_PHY_134; + volatile uint32_t DENALI_PHY_135; + volatile uint32_t DENALI_PHY_136; + volatile uint32_t DENALI_PHY_137; + volatile uint32_t DENALI_PHY_138; + volatile uint32_t DENALI_PHY_139; + volatile char pad__2[0x1D0U]; + volatile uint32_t DENALI_PHY_256; + volatile uint32_t DENALI_PHY_257; + volatile uint32_t DENALI_PHY_258; + volatile uint32_t DENALI_PHY_259; + volatile uint32_t DENALI_PHY_260; + volatile uint32_t DENALI_PHY_261; + volatile uint32_t DENALI_PHY_262; + volatile uint32_t DENALI_PHY_263; + volatile uint32_t DENALI_PHY_264; + volatile uint32_t DENALI_PHY_265; + volatile uint32_t DENALI_PHY_266; + volatile uint32_t DENALI_PHY_267; + volatile uint32_t DENALI_PHY_268; + volatile uint32_t DENALI_PHY_269; + volatile uint32_t DENALI_PHY_270; + volatile uint32_t DENALI_PHY_271; + volatile uint32_t DENALI_PHY_272; + volatile uint32_t DENALI_PHY_273; + volatile uint32_t DENALI_PHY_274; + volatile uint32_t DENALI_PHY_275; + volatile uint32_t DENALI_PHY_276; + volatile uint32_t DENALI_PHY_277; + volatile uint32_t DENALI_PHY_278; + volatile uint32_t DENALI_PHY_279; + volatile uint32_t DENALI_PHY_280; + volatile uint32_t DENALI_PHY_281; + volatile uint32_t DENALI_PHY_282; + volatile uint32_t DENALI_PHY_283; + volatile uint32_t DENALI_PHY_284; + volatile uint32_t DENALI_PHY_285; + volatile uint32_t DENALI_PHY_286; + volatile uint32_t DENALI_PHY_287; + volatile uint32_t DENALI_PHY_288; + volatile uint32_t DENALI_PHY_289; + volatile uint32_t DENALI_PHY_290; + volatile uint32_t DENALI_PHY_291; + volatile uint32_t DENALI_PHY_292; + volatile uint32_t DENALI_PHY_293; + volatile uint32_t DENALI_PHY_294; + volatile uint32_t DENALI_PHY_295; + volatile uint32_t DENALI_PHY_296; + volatile uint32_t DENALI_PHY_297; + volatile uint32_t DENALI_PHY_298; + volatile uint32_t DENALI_PHY_299; + volatile uint32_t DENALI_PHY_300; + volatile uint32_t DENALI_PHY_301; + volatile uint32_t DENALI_PHY_302; + volatile uint32_t DENALI_PHY_303; + volatile uint32_t DENALI_PHY_304; + volatile uint32_t DENALI_PHY_305; + volatile uint32_t DENALI_PHY_306; + volatile uint32_t DENALI_PHY_307; + volatile uint32_t DENALI_PHY_308; + volatile uint32_t DENALI_PHY_309; + volatile uint32_t DENALI_PHY_310; + volatile uint32_t DENALI_PHY_311; + volatile uint32_t DENALI_PHY_312; + volatile uint32_t DENALI_PHY_313; + volatile uint32_t DENALI_PHY_314; + volatile uint32_t DENALI_PHY_315; + volatile uint32_t DENALI_PHY_316; + volatile uint32_t DENALI_PHY_317; + volatile uint32_t DENALI_PHY_318; + volatile uint32_t DENALI_PHY_319; + volatile uint32_t DENALI_PHY_320; + volatile uint32_t DENALI_PHY_321; + volatile uint32_t DENALI_PHY_322; + volatile uint32_t DENALI_PHY_323; + volatile uint32_t DENALI_PHY_324; + volatile uint32_t DENALI_PHY_325; + volatile uint32_t DENALI_PHY_326; + volatile uint32_t DENALI_PHY_327; + volatile uint32_t DENALI_PHY_328; + volatile uint32_t DENALI_PHY_329; + volatile uint32_t DENALI_PHY_330; + volatile uint32_t DENALI_PHY_331; + volatile uint32_t DENALI_PHY_332; + volatile uint32_t DENALI_PHY_333; + volatile uint32_t DENALI_PHY_334; + volatile uint32_t DENALI_PHY_335; + volatile uint32_t DENALI_PHY_336; + volatile uint32_t DENALI_PHY_337; + volatile uint32_t DENALI_PHY_338; + volatile uint32_t DENALI_PHY_339; + volatile uint32_t DENALI_PHY_340; + volatile uint32_t DENALI_PHY_341; + volatile uint32_t DENALI_PHY_342; + volatile uint32_t DENALI_PHY_343; + volatile uint32_t DENALI_PHY_344; + volatile uint32_t DENALI_PHY_345; + volatile uint32_t DENALI_PHY_346; + volatile uint32_t DENALI_PHY_347; + volatile uint32_t DENALI_PHY_348; + volatile uint32_t DENALI_PHY_349; + volatile uint32_t DENALI_PHY_350; + volatile uint32_t DENALI_PHY_351; + volatile uint32_t DENALI_PHY_352; + volatile uint32_t DENALI_PHY_353; + volatile uint32_t DENALI_PHY_354; + volatile uint32_t DENALI_PHY_355; + volatile uint32_t DENALI_PHY_356; + volatile uint32_t DENALI_PHY_357; + volatile uint32_t DENALI_PHY_358; + volatile uint32_t DENALI_PHY_359; + volatile uint32_t DENALI_PHY_360; + volatile uint32_t DENALI_PHY_361; + volatile uint32_t DENALI_PHY_362; + volatile uint32_t DENALI_PHY_363; + volatile uint32_t DENALI_PHY_364; + volatile uint32_t DENALI_PHY_365; + volatile uint32_t DENALI_PHY_366; + volatile uint32_t DENALI_PHY_367; + volatile uint32_t DENALI_PHY_368; + volatile uint32_t DENALI_PHY_369; + volatile uint32_t DENALI_PHY_370; + volatile uint32_t DENALI_PHY_371; + volatile uint32_t DENALI_PHY_372; + volatile uint32_t DENALI_PHY_373; + volatile uint32_t DENALI_PHY_374; + volatile uint32_t DENALI_PHY_375; + volatile uint32_t DENALI_PHY_376; + volatile uint32_t DENALI_PHY_377; + volatile uint32_t DENALI_PHY_378; + volatile uint32_t DENALI_PHY_379; + volatile uint32_t DENALI_PHY_380; + volatile uint32_t DENALI_PHY_381; + volatile uint32_t DENALI_PHY_382; + volatile uint32_t DENALI_PHY_383; + volatile uint32_t DENALI_PHY_384; + volatile uint32_t DENALI_PHY_385; + volatile uint32_t DENALI_PHY_386; + volatile uint32_t DENALI_PHY_387; + volatile uint32_t DENALI_PHY_388; + volatile uint32_t DENALI_PHY_389; + volatile uint32_t DENALI_PHY_390; + volatile uint32_t DENALI_PHY_391; + volatile uint32_t DENALI_PHY_392; + volatile uint32_t DENALI_PHY_393; + volatile uint32_t DENALI_PHY_394; + volatile uint32_t DENALI_PHY_395; + volatile char pad__3[0x1D0U]; + volatile uint32_t DENALI_PHY_512; + volatile uint32_t DENALI_PHY_513; + volatile uint32_t DENALI_PHY_514; + volatile uint32_t DENALI_PHY_515; + volatile uint32_t DENALI_PHY_516; + volatile uint32_t DENALI_PHY_517; + volatile uint32_t DENALI_PHY_518; + volatile uint32_t DENALI_PHY_519; + volatile uint32_t DENALI_PHY_520; + volatile uint32_t DENALI_PHY_521; + volatile uint32_t DENALI_PHY_522; + volatile uint32_t DENALI_PHY_523; + volatile uint32_t DENALI_PHY_524; + volatile uint32_t DENALI_PHY_525; + volatile uint32_t DENALI_PHY_526; + volatile uint32_t DENALI_PHY_527; + volatile uint32_t DENALI_PHY_528; + volatile uint32_t DENALI_PHY_529; + volatile uint32_t DENALI_PHY_530; + volatile uint32_t DENALI_PHY_531; + volatile uint32_t DENALI_PHY_532; + volatile uint32_t DENALI_PHY_533; + volatile uint32_t DENALI_PHY_534; + volatile uint32_t DENALI_PHY_535; + volatile uint32_t DENALI_PHY_536; + volatile uint32_t DENALI_PHY_537; + volatile uint32_t DENALI_PHY_538; + volatile uint32_t DENALI_PHY_539; + volatile uint32_t DENALI_PHY_540; + volatile uint32_t DENALI_PHY_541; + volatile uint32_t DENALI_PHY_542; + volatile uint32_t DENALI_PHY_543; + volatile uint32_t DENALI_PHY_544; + volatile uint32_t DENALI_PHY_545; + volatile uint32_t DENALI_PHY_546; + volatile uint32_t DENALI_PHY_547; + volatile uint32_t DENALI_PHY_548; + volatile uint32_t DENALI_PHY_549; + volatile uint32_t DENALI_PHY_550; + volatile uint32_t DENALI_PHY_551; + volatile uint32_t DENALI_PHY_552; + volatile uint32_t DENALI_PHY_553; + volatile uint32_t DENALI_PHY_554; + volatile uint32_t DENALI_PHY_555; + volatile uint32_t DENALI_PHY_556; + volatile uint32_t DENALI_PHY_557; + volatile uint32_t DENALI_PHY_558; + volatile uint32_t DENALI_PHY_559; + volatile uint32_t DENALI_PHY_560; + volatile uint32_t DENALI_PHY_561; + volatile uint32_t DENALI_PHY_562; + volatile uint32_t DENALI_PHY_563; + volatile uint32_t DENALI_PHY_564; + volatile uint32_t DENALI_PHY_565; + volatile uint32_t DENALI_PHY_566; + volatile uint32_t DENALI_PHY_567; + volatile uint32_t DENALI_PHY_568; + volatile uint32_t DENALI_PHY_569; + volatile uint32_t DENALI_PHY_570; + volatile uint32_t DENALI_PHY_571; + volatile uint32_t DENALI_PHY_572; + volatile uint32_t DENALI_PHY_573; + volatile uint32_t DENALI_PHY_574; + volatile uint32_t DENALI_PHY_575; + volatile uint32_t DENALI_PHY_576; + volatile uint32_t DENALI_PHY_577; + volatile uint32_t DENALI_PHY_578; + volatile uint32_t DENALI_PHY_579; + volatile uint32_t DENALI_PHY_580; + volatile uint32_t DENALI_PHY_581; + volatile uint32_t DENALI_PHY_582; + volatile uint32_t DENALI_PHY_583; + volatile uint32_t DENALI_PHY_584; + volatile uint32_t DENALI_PHY_585; + volatile uint32_t DENALI_PHY_586; + volatile uint32_t DENALI_PHY_587; + volatile uint32_t DENALI_PHY_588; + volatile uint32_t DENALI_PHY_589; + volatile uint32_t DENALI_PHY_590; + volatile uint32_t DENALI_PHY_591; + volatile uint32_t DENALI_PHY_592; + volatile uint32_t DENALI_PHY_593; + volatile uint32_t DENALI_PHY_594; + volatile uint32_t DENALI_PHY_595; + volatile uint32_t DENALI_PHY_596; + volatile uint32_t DENALI_PHY_597; + volatile uint32_t DENALI_PHY_598; + volatile uint32_t DENALI_PHY_599; + volatile uint32_t DENALI_PHY_600; + volatile uint32_t DENALI_PHY_601; + volatile uint32_t DENALI_PHY_602; + volatile uint32_t DENALI_PHY_603; + volatile uint32_t DENALI_PHY_604; + volatile uint32_t DENALI_PHY_605; + volatile uint32_t DENALI_PHY_606; + volatile uint32_t DENALI_PHY_607; + volatile uint32_t DENALI_PHY_608; + volatile uint32_t DENALI_PHY_609; + volatile uint32_t DENALI_PHY_610; + volatile uint32_t DENALI_PHY_611; + volatile uint32_t DENALI_PHY_612; + volatile uint32_t DENALI_PHY_613; + volatile uint32_t DENALI_PHY_614; + volatile uint32_t DENALI_PHY_615; + volatile uint32_t DENALI_PHY_616; + volatile uint32_t DENALI_PHY_617; + volatile uint32_t DENALI_PHY_618; + volatile uint32_t DENALI_PHY_619; + volatile uint32_t DENALI_PHY_620; + volatile uint32_t DENALI_PHY_621; + volatile uint32_t DENALI_PHY_622; + volatile uint32_t DENALI_PHY_623; + volatile uint32_t DENALI_PHY_624; + volatile uint32_t DENALI_PHY_625; + volatile uint32_t DENALI_PHY_626; + volatile uint32_t DENALI_PHY_627; + volatile uint32_t DENALI_PHY_628; + volatile uint32_t DENALI_PHY_629; + volatile uint32_t DENALI_PHY_630; + volatile uint32_t DENALI_PHY_631; + volatile uint32_t DENALI_PHY_632; + volatile uint32_t DENALI_PHY_633; + volatile uint32_t DENALI_PHY_634; + volatile uint32_t DENALI_PHY_635; + volatile uint32_t DENALI_PHY_636; + volatile uint32_t DENALI_PHY_637; + volatile uint32_t DENALI_PHY_638; + volatile uint32_t DENALI_PHY_639; + volatile uint32_t DENALI_PHY_640; + volatile uint32_t DENALI_PHY_641; + volatile uint32_t DENALI_PHY_642; + volatile uint32_t DENALI_PHY_643; + volatile uint32_t DENALI_PHY_644; + volatile uint32_t DENALI_PHY_645; + volatile uint32_t DENALI_PHY_646; + volatile uint32_t DENALI_PHY_647; + volatile uint32_t DENALI_PHY_648; + volatile uint32_t DENALI_PHY_649; + volatile uint32_t DENALI_PHY_650; + volatile uint32_t DENALI_PHY_651; + volatile char pad__4[0x1D0U]; + volatile uint32_t DENALI_PHY_768; + volatile uint32_t DENALI_PHY_769; + volatile uint32_t DENALI_PHY_770; + volatile uint32_t DENALI_PHY_771; + volatile uint32_t DENALI_PHY_772; + volatile uint32_t DENALI_PHY_773; + volatile uint32_t DENALI_PHY_774; + volatile uint32_t DENALI_PHY_775; + volatile uint32_t DENALI_PHY_776; + volatile uint32_t DENALI_PHY_777; + volatile uint32_t DENALI_PHY_778; + volatile uint32_t DENALI_PHY_779; + volatile uint32_t DENALI_PHY_780; + volatile uint32_t DENALI_PHY_781; + volatile uint32_t DENALI_PHY_782; + volatile uint32_t DENALI_PHY_783; + volatile uint32_t DENALI_PHY_784; + volatile uint32_t DENALI_PHY_785; + volatile uint32_t DENALI_PHY_786; + volatile uint32_t DENALI_PHY_787; + volatile uint32_t DENALI_PHY_788; + volatile uint32_t DENALI_PHY_789; + volatile uint32_t DENALI_PHY_790; + volatile uint32_t DENALI_PHY_791; + volatile uint32_t DENALI_PHY_792; + volatile uint32_t DENALI_PHY_793; + volatile uint32_t DENALI_PHY_794; + volatile uint32_t DENALI_PHY_795; + volatile uint32_t DENALI_PHY_796; + volatile uint32_t DENALI_PHY_797; + volatile uint32_t DENALI_PHY_798; + volatile uint32_t DENALI_PHY_799; + volatile uint32_t DENALI_PHY_800; + volatile uint32_t DENALI_PHY_801; + volatile uint32_t DENALI_PHY_802; + volatile uint32_t DENALI_PHY_803; + volatile uint32_t DENALI_PHY_804; + volatile uint32_t DENALI_PHY_805; + volatile uint32_t DENALI_PHY_806; + volatile uint32_t DENALI_PHY_807; + volatile uint32_t DENALI_PHY_808; + volatile uint32_t DENALI_PHY_809; + volatile uint32_t DENALI_PHY_810; + volatile uint32_t DENALI_PHY_811; + volatile uint32_t DENALI_PHY_812; + volatile uint32_t DENALI_PHY_813; + volatile uint32_t DENALI_PHY_814; + volatile uint32_t DENALI_PHY_815; + volatile uint32_t DENALI_PHY_816; + volatile uint32_t DENALI_PHY_817; + volatile uint32_t DENALI_PHY_818; + volatile uint32_t DENALI_PHY_819; + volatile uint32_t DENALI_PHY_820; + volatile uint32_t DENALI_PHY_821; + volatile uint32_t DENALI_PHY_822; + volatile uint32_t DENALI_PHY_823; + volatile uint32_t DENALI_PHY_824; + volatile uint32_t DENALI_PHY_825; + volatile uint32_t DENALI_PHY_826; + volatile uint32_t DENALI_PHY_827; + volatile uint32_t DENALI_PHY_828; + volatile uint32_t DENALI_PHY_829; + volatile uint32_t DENALI_PHY_830; + volatile uint32_t DENALI_PHY_831; + volatile uint32_t DENALI_PHY_832; + volatile uint32_t DENALI_PHY_833; + volatile uint32_t DENALI_PHY_834; + volatile uint32_t DENALI_PHY_835; + volatile uint32_t DENALI_PHY_836; + volatile uint32_t DENALI_PHY_837; + volatile uint32_t DENALI_PHY_838; + volatile uint32_t DENALI_PHY_839; + volatile uint32_t DENALI_PHY_840; + volatile uint32_t DENALI_PHY_841; + volatile uint32_t DENALI_PHY_842; + volatile uint32_t DENALI_PHY_843; + volatile uint32_t DENALI_PHY_844; + volatile uint32_t DENALI_PHY_845; + volatile uint32_t DENALI_PHY_846; + volatile uint32_t DENALI_PHY_847; + volatile uint32_t DENALI_PHY_848; + volatile uint32_t DENALI_PHY_849; + volatile uint32_t DENALI_PHY_850; + volatile uint32_t DENALI_PHY_851; + volatile uint32_t DENALI_PHY_852; + volatile uint32_t DENALI_PHY_853; + volatile uint32_t DENALI_PHY_854; + volatile uint32_t DENALI_PHY_855; + volatile uint32_t DENALI_PHY_856; + volatile uint32_t DENALI_PHY_857; + volatile uint32_t DENALI_PHY_858; + volatile uint32_t DENALI_PHY_859; + volatile uint32_t DENALI_PHY_860; + volatile uint32_t DENALI_PHY_861; + volatile uint32_t DENALI_PHY_862; + volatile uint32_t DENALI_PHY_863; + volatile uint32_t DENALI_PHY_864; + volatile uint32_t DENALI_PHY_865; + volatile uint32_t DENALI_PHY_866; + volatile uint32_t DENALI_PHY_867; + volatile uint32_t DENALI_PHY_868; + volatile uint32_t DENALI_PHY_869; + volatile uint32_t DENALI_PHY_870; + volatile uint32_t DENALI_PHY_871; + volatile uint32_t DENALI_PHY_872; + volatile uint32_t DENALI_PHY_873; + volatile uint32_t DENALI_PHY_874; + volatile uint32_t DENALI_PHY_875; + volatile uint32_t DENALI_PHY_876; + volatile uint32_t DENALI_PHY_877; + volatile uint32_t DENALI_PHY_878; + volatile uint32_t DENALI_PHY_879; + volatile uint32_t DENALI_PHY_880; + volatile uint32_t DENALI_PHY_881; + volatile uint32_t DENALI_PHY_882; + volatile uint32_t DENALI_PHY_883; + volatile uint32_t DENALI_PHY_884; + volatile uint32_t DENALI_PHY_885; + volatile uint32_t DENALI_PHY_886; + volatile uint32_t DENALI_PHY_887; + volatile uint32_t DENALI_PHY_888; + volatile uint32_t DENALI_PHY_889; + volatile uint32_t DENALI_PHY_890; + volatile uint32_t DENALI_PHY_891; + volatile uint32_t DENALI_PHY_892; + volatile uint32_t DENALI_PHY_893; + volatile uint32_t DENALI_PHY_894; + volatile uint32_t DENALI_PHY_895; + volatile uint32_t DENALI_PHY_896; + volatile uint32_t DENALI_PHY_897; + volatile uint32_t DENALI_PHY_898; + volatile uint32_t DENALI_PHY_899; + volatile uint32_t DENALI_PHY_900; + volatile uint32_t DENALI_PHY_901; + volatile uint32_t DENALI_PHY_902; + volatile uint32_t DENALI_PHY_903; + volatile uint32_t DENALI_PHY_904; + volatile uint32_t DENALI_PHY_905; + volatile uint32_t DENALI_PHY_906; + volatile uint32_t DENALI_PHY_907; + volatile char pad__5[0x1D0U]; + volatile uint32_t DENALI_PHY_1024; + volatile uint32_t DENALI_PHY_1025; + volatile uint32_t DENALI_PHY_1026; + volatile uint32_t DENALI_PHY_1027; + volatile uint32_t DENALI_PHY_1028; + volatile uint32_t DENALI_PHY_1029; + volatile uint32_t DENALI_PHY_1030; + volatile uint32_t DENALI_PHY_1031; + volatile uint32_t DENALI_PHY_1032; + volatile uint32_t DENALI_PHY_1033; + volatile uint32_t DENALI_PHY_1034; + volatile uint32_t DENALI_PHY_1035; + volatile uint32_t DENALI_PHY_1036; + volatile uint32_t DENALI_PHY_1037; + volatile uint32_t DENALI_PHY_1038; + volatile uint32_t DENALI_PHY_1039; + volatile uint32_t DENALI_PHY_1040; + volatile uint32_t DENALI_PHY_1041; + volatile uint32_t DENALI_PHY_1042; + volatile uint32_t DENALI_PHY_1043; + volatile uint32_t DENALI_PHY_1044; + volatile uint32_t DENALI_PHY_1045; + volatile uint32_t DENALI_PHY_1046; + volatile uint32_t DENALI_PHY_1047; + volatile uint32_t DENALI_PHY_1048; + volatile uint32_t DENALI_PHY_1049; + volatile uint32_t DENALI_PHY_1050; + volatile uint32_t DENALI_PHY_1051; + volatile uint32_t DENALI_PHY_1052; + volatile uint32_t DENALI_PHY_1053; + volatile uint32_t DENALI_PHY_1054; + volatile uint32_t DENALI_PHY_1055; + volatile uint32_t DENALI_PHY_1056; + volatile uint32_t DENALI_PHY_1057; + volatile uint32_t DENALI_PHY_1058; + volatile uint32_t DENALI_PHY_1059; + volatile uint32_t DENALI_PHY_1060; + volatile uint32_t DENALI_PHY_1061; + volatile uint32_t DENALI_PHY_1062; + volatile uint32_t DENALI_PHY_1063; + volatile uint32_t DENALI_PHY_1064; + volatile uint32_t DENALI_PHY_1065; + volatile uint32_t DENALI_PHY_1066; + volatile uint32_t DENALI_PHY_1067; + volatile uint32_t DENALI_PHY_1068; + volatile uint32_t DENALI_PHY_1069; + volatile uint32_t DENALI_PHY_1070; + volatile uint32_t DENALI_PHY_1071; + volatile uint32_t DENALI_PHY_1072; + volatile uint32_t DENALI_PHY_1073; + volatile uint32_t DENALI_PHY_1074; + volatile uint32_t DENALI_PHY_1075; + volatile char pad__6[0x330U]; + volatile uint32_t DENALI_PHY_1280; + volatile uint32_t DENALI_PHY_1281; + volatile uint32_t DENALI_PHY_1282; + volatile uint32_t DENALI_PHY_1283; + volatile uint32_t DENALI_PHY_1284; + volatile uint32_t DENALI_PHY_1285; + volatile uint32_t DENALI_PHY_1286; + volatile uint32_t DENALI_PHY_1287; + volatile uint32_t DENALI_PHY_1288; + volatile uint32_t DENALI_PHY_1289; + volatile uint32_t DENALI_PHY_1290; + volatile uint32_t DENALI_PHY_1291; + volatile uint32_t DENALI_PHY_1292; + volatile uint32_t DENALI_PHY_1293; + volatile uint32_t DENALI_PHY_1294; + volatile uint32_t DENALI_PHY_1295; + volatile uint32_t DENALI_PHY_1296; + volatile uint32_t DENALI_PHY_1297; + volatile uint32_t DENALI_PHY_1298; + volatile uint32_t DENALI_PHY_1299; + volatile uint32_t DENALI_PHY_1300; + volatile uint32_t DENALI_PHY_1301; + volatile uint32_t DENALI_PHY_1302; + volatile uint32_t DENALI_PHY_1303; + volatile uint32_t DENALI_PHY_1304; + volatile uint32_t DENALI_PHY_1305; + volatile uint32_t DENALI_PHY_1306; + volatile uint32_t DENALI_PHY_1307; + volatile uint32_t DENALI_PHY_1308; + volatile uint32_t DENALI_PHY_1309; + volatile uint32_t DENALI_PHY_1310; + volatile uint32_t DENALI_PHY_1311; + volatile uint32_t DENALI_PHY_1312; + volatile uint32_t DENALI_PHY_1313; + volatile uint32_t DENALI_PHY_1314; + volatile uint32_t DENALI_PHY_1315; + volatile uint32_t DENALI_PHY_1316; + volatile uint32_t DENALI_PHY_1317; + volatile uint32_t DENALI_PHY_1318; + volatile uint32_t DENALI_PHY_1319; + volatile uint32_t DENALI_PHY_1320; + volatile uint32_t DENALI_PHY_1321; + volatile uint32_t DENALI_PHY_1322; + volatile uint32_t DENALI_PHY_1323; + volatile uint32_t DENALI_PHY_1324; + volatile uint32_t DENALI_PHY_1325; + volatile uint32_t DENALI_PHY_1326; + volatile uint32_t DENALI_PHY_1327; + volatile uint32_t DENALI_PHY_1328; + volatile uint32_t DENALI_PHY_1329; + volatile uint32_t DENALI_PHY_1330; + volatile uint32_t DENALI_PHY_1331; + volatile uint32_t DENALI_PHY_1332; + volatile uint32_t DENALI_PHY_1333; + volatile uint32_t DENALI_PHY_1334; + volatile uint32_t DENALI_PHY_1335; + volatile uint32_t DENALI_PHY_1336; + volatile uint32_t DENALI_PHY_1337; + volatile uint32_t DENALI_PHY_1338; + volatile uint32_t DENALI_PHY_1339; + volatile uint32_t DENALI_PHY_1340; + volatile uint32_t DENALI_PHY_1341; + volatile uint32_t DENALI_PHY_1342; + volatile uint32_t DENALI_PHY_1343; + volatile uint32_t DENALI_PHY_1344; + volatile uint32_t DENALI_PHY_1345; + volatile uint32_t DENALI_PHY_1346; + volatile uint32_t DENALI_PHY_1347; + volatile uint32_t DENALI_PHY_1348; + volatile uint32_t DENALI_PHY_1349; + volatile uint32_t DENALI_PHY_1350; + volatile uint32_t DENALI_PHY_1351; + volatile uint32_t DENALI_PHY_1352; + volatile uint32_t DENALI_PHY_1353; + volatile uint32_t DENALI_PHY_1354; + volatile uint32_t DENALI_PHY_1355; + volatile uint32_t DENALI_PHY_1356; + volatile uint32_t DENALI_PHY_1357; + volatile uint32_t DENALI_PHY_1358; + volatile uint32_t DENALI_PHY_1359; + volatile uint32_t DENALI_PHY_1360; + volatile uint32_t DENALI_PHY_1361; + volatile uint32_t DENALI_PHY_1362; + volatile uint32_t DENALI_PHY_1363; + volatile uint32_t DENALI_PHY_1364; + volatile uint32_t DENALI_PHY_1365; + volatile uint32_t DENALI_PHY_1366; + volatile uint32_t DENALI_PHY_1367; + volatile uint32_t DENALI_PHY_1368; + volatile uint32_t DENALI_PHY_1369; + volatile uint32_t DENALI_PHY_1370; + volatile uint32_t DENALI_PHY_1371; + volatile uint32_t DENALI_PHY_1372; + volatile uint32_t DENALI_PHY_1373; + volatile uint32_t DENALI_PHY_1374; + volatile uint32_t DENALI_PHY_1375; + volatile uint32_t DENALI_PHY_1376; + volatile uint32_t DENALI_PHY_1377; + volatile uint32_t DENALI_PHY_1378; + volatile uint32_t DENALI_PHY_1379; + volatile uint32_t DENALI_PHY_1380; + volatile uint32_t DENALI_PHY_1381; + volatile uint32_t DENALI_PHY_1382; + volatile uint32_t DENALI_PHY_1383; + volatile uint32_t DENALI_PHY_1384; + volatile uint32_t DENALI_PHY_1385; + volatile uint32_t DENALI_PHY_1386; + volatile uint32_t DENALI_PHY_1387; + volatile uint32_t DENALI_PHY_1388; + volatile uint32_t DENALI_PHY_1389; + volatile uint32_t DENALI_PHY_1390; + volatile uint32_t DENALI_PHY_1391; + volatile uint32_t DENALI_PHY_1392; + volatile uint32_t DENALI_PHY_1393; + volatile uint32_t DENALI_PHY_1394; + volatile uint32_t DENALI_PHY_1395; + volatile uint32_t DENALI_PHY_1396; + volatile uint32_t DENALI_PHY_1397; + volatile uint32_t DENALI_PHY_1398; + volatile uint32_t DENALI_PHY_1399; + volatile uint32_t DENALI_PHY_1400; + volatile uint32_t DENALI_PHY_1401; + volatile uint32_t DENALI_PHY_1402; + volatile uint32_t DENALI_PHY_1403; + volatile uint32_t DENALI_PHY_1404; + volatile uint32_t DENALI_PHY_1405; + volatile uint32_t DENALI_PHY_1406; + volatile uint32_t DENALI_PHY_1407; + volatile uint32_t DENALI_PHY_1408; + volatile uint32_t DENALI_PHY_1409; + volatile uint32_t DENALI_PHY_1410; + volatile uint32_t DENALI_PHY_1411; + volatile uint32_t DENALI_PHY_1412; + volatile uint32_t DENALI_PHY_1413; + volatile uint32_t DENALI_PHY_1414; + volatile uint32_t DENALI_PHY_1415; + volatile uint32_t DENALI_PHY_1416; + volatile uint32_t DENALI_PHY_1417; + volatile uint32_t DENALI_PHY_1418; + volatile uint32_t DENALI_PHY_1419; + volatile uint32_t DENALI_PHY_1420; + volatile uint32_t DENALI_PHY_1421; + volatile uint32_t DENALI_PHY_1422; +} lpddr4_ctlregs; + +#endif /* REG_LPDDR4_CTL_REGS_H_ */ diff --git a/drivers/ram/k3-j721e/lpddr4_data_slice_0_macros.h b/drivers/ram/k3-j721e/lpddr4_data_slice_0_macros.h new file mode 100644 index 0000000..3208b1c --- /dev/null +++ b/drivers/ram/k3-j721e/lpddr4_data_slice_0_macros.h @@ -0,0 +1,2373 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/********************************************************************** + * Copyright (C) 2012-2019 Cadence Design Systems, Inc. + * + * THIS FILE IS AUTOMATICALLY GENERATED, DO NOT EDIT + * + ********************************************************************** + */ + +#ifndef REG_LPDDR4_DATA_SLICE_0_MACROS_H_ +#define REG_LPDDR4_DATA_SLICE_0_MACROS_H_ + +#define LPDDR4__DENALI_PHY_0_READ_MASK 0x000F07FFU +#define LPDDR4__DENALI_PHY_0_WRITE_MASK 0x000F07FFU +#define LPDDR4__DENALI_PHY_0__PHY_CLK_WR_BYPASS_SLAVE_DELAY_0_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_0__PHY_CLK_WR_BYPASS_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_0__PHY_CLK_WR_BYPASS_SLAVE_DELAY_0_WIDTH 11U +#define LPDDR4__PHY_CLK_WR_BYPASS_SLAVE_DELAY_0__REG DENALI_PHY_0 +#define LPDDR4__PHY_CLK_WR_BYPASS_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_0__PHY_CLK_WR_BYPASS_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_0__PHY_IO_PAD_DELAY_TIMING_BYPASS_0_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_0__PHY_IO_PAD_DELAY_TIMING_BYPASS_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_0__PHY_IO_PAD_DELAY_TIMING_BYPASS_0_WIDTH 4U +#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_BYPASS_0__REG DENALI_PHY_0 +#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_BYPASS_0__FLD LPDDR4__DENALI_PHY_0__PHY_IO_PAD_DELAY_TIMING_BYPASS_0 + +#define LPDDR4__DENALI_PHY_1_READ_MASK 0x000703FFU +#define LPDDR4__DENALI_PHY_1_WRITE_MASK 0x000703FFU +#define LPDDR4__DENALI_PHY_1__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_0_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_1__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_0_WIDTH 10U +#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_0__REG DENALI_PHY_1 +#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_0__FLD LPDDR4__DENALI_PHY_1__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_0 + +#define LPDDR4__DENALI_PHY_1__PHY_WRITE_PATH_LAT_ADD_BYPASS_0_MASK 0x00070000U +#define LPDDR4__DENALI_PHY_1__PHY_WRITE_PATH_LAT_ADD_BYPASS_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1__PHY_WRITE_PATH_LAT_ADD_BYPASS_0_WIDTH 3U +#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_BYPASS_0__REG DENALI_PHY_1 +#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_BYPASS_0__FLD LPDDR4__DENALI_PHY_1__PHY_WRITE_PATH_LAT_ADD_BYPASS_0 + +#define LPDDR4__DENALI_PHY_2_READ_MASK 0x010303FFU +#define LPDDR4__DENALI_PHY_2_WRITE_MASK 0x010303FFU +#define LPDDR4__DENALI_PHY_2__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_0_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_2__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_2__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_0__REG DENALI_PHY_2 +#define LPDDR4__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_2__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_2__PHY_BYPASS_TWO_CYC_PREAMBLE_0_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_2__PHY_BYPASS_TWO_CYC_PREAMBLE_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_2__PHY_BYPASS_TWO_CYC_PREAMBLE_0_WIDTH 2U +#define LPDDR4__PHY_BYPASS_TWO_CYC_PREAMBLE_0__REG DENALI_PHY_2 +#define LPDDR4__PHY_BYPASS_TWO_CYC_PREAMBLE_0__FLD LPDDR4__DENALI_PHY_2__PHY_BYPASS_TWO_CYC_PREAMBLE_0 + +#define LPDDR4__DENALI_PHY_2__PHY_CLK_BYPASS_OVERRIDE_0_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_2__PHY_CLK_BYPASS_OVERRIDE_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_2__PHY_CLK_BYPASS_OVERRIDE_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_2__PHY_CLK_BYPASS_OVERRIDE_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_2__PHY_CLK_BYPASS_OVERRIDE_0_WOSET 0U +#define LPDDR4__PHY_CLK_BYPASS_OVERRIDE_0__REG DENALI_PHY_2 +#define LPDDR4__PHY_CLK_BYPASS_OVERRIDE_0__FLD LPDDR4__DENALI_PHY_2__PHY_CLK_BYPASS_OVERRIDE_0 + +#define LPDDR4__DENALI_PHY_3_READ_MASK 0x3F3F3F3FU +#define LPDDR4__DENALI_PHY_3_WRITE_MASK 0x3F3F3F3FU +#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ0_SHIFT_0_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ0_SHIFT_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ0_SHIFT_0_WIDTH 6U +#define LPDDR4__PHY_SW_WRDQ0_SHIFT_0__REG DENALI_PHY_3 +#define LPDDR4__PHY_SW_WRDQ0_SHIFT_0__FLD LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ0_SHIFT_0 + +#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ1_SHIFT_0_MASK 0x00003F00U +#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ1_SHIFT_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ1_SHIFT_0_WIDTH 6U +#define LPDDR4__PHY_SW_WRDQ1_SHIFT_0__REG DENALI_PHY_3 +#define LPDDR4__PHY_SW_WRDQ1_SHIFT_0__FLD LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ1_SHIFT_0 + +#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ2_SHIFT_0_MASK 0x003F0000U +#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ2_SHIFT_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ2_SHIFT_0_WIDTH 6U +#define LPDDR4__PHY_SW_WRDQ2_SHIFT_0__REG DENALI_PHY_3 +#define LPDDR4__PHY_SW_WRDQ2_SHIFT_0__FLD LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ2_SHIFT_0 + +#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ3_SHIFT_0_MASK 0x3F000000U +#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ3_SHIFT_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ3_SHIFT_0_WIDTH 6U +#define LPDDR4__PHY_SW_WRDQ3_SHIFT_0__REG DENALI_PHY_3 +#define LPDDR4__PHY_SW_WRDQ3_SHIFT_0__FLD LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ3_SHIFT_0 + +#define LPDDR4__DENALI_PHY_4_READ_MASK 0x3F3F3F3FU +#define LPDDR4__DENALI_PHY_4_WRITE_MASK 0x3F3F3F3FU +#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ4_SHIFT_0_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ4_SHIFT_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ4_SHIFT_0_WIDTH 6U +#define LPDDR4__PHY_SW_WRDQ4_SHIFT_0__REG DENALI_PHY_4 +#define LPDDR4__PHY_SW_WRDQ4_SHIFT_0__FLD LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ4_SHIFT_0 + +#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ5_SHIFT_0_MASK 0x00003F00U +#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ5_SHIFT_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ5_SHIFT_0_WIDTH 6U +#define LPDDR4__PHY_SW_WRDQ5_SHIFT_0__REG DENALI_PHY_4 +#define LPDDR4__PHY_SW_WRDQ5_SHIFT_0__FLD LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ5_SHIFT_0 + +#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ6_SHIFT_0_MASK 0x003F0000U +#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ6_SHIFT_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ6_SHIFT_0_WIDTH 6U +#define LPDDR4__PHY_SW_WRDQ6_SHIFT_0__REG DENALI_PHY_4 +#define LPDDR4__PHY_SW_WRDQ6_SHIFT_0__FLD LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ6_SHIFT_0 + +#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ7_SHIFT_0_MASK 0x3F000000U +#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ7_SHIFT_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ7_SHIFT_0_WIDTH 6U +#define LPDDR4__PHY_SW_WRDQ7_SHIFT_0__REG DENALI_PHY_4 +#define LPDDR4__PHY_SW_WRDQ7_SHIFT_0__FLD LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ7_SHIFT_0 + +#define LPDDR4__DENALI_PHY_5_READ_MASK 0x01030F3FU +#define LPDDR4__DENALI_PHY_5_WRITE_MASK 0x01030F3FU +#define LPDDR4__DENALI_PHY_5__PHY_SW_WRDM_SHIFT_0_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_5__PHY_SW_WRDM_SHIFT_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_5__PHY_SW_WRDM_SHIFT_0_WIDTH 6U +#define LPDDR4__PHY_SW_WRDM_SHIFT_0__REG DENALI_PHY_5 +#define LPDDR4__PHY_SW_WRDM_SHIFT_0__FLD LPDDR4__DENALI_PHY_5__PHY_SW_WRDM_SHIFT_0 + +#define LPDDR4__DENALI_PHY_5__PHY_SW_WRDQS_SHIFT_0_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_5__PHY_SW_WRDQS_SHIFT_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_5__PHY_SW_WRDQS_SHIFT_0_WIDTH 4U +#define LPDDR4__PHY_SW_WRDQS_SHIFT_0__REG DENALI_PHY_5 +#define LPDDR4__PHY_SW_WRDQS_SHIFT_0__FLD LPDDR4__DENALI_PHY_5__PHY_SW_WRDQS_SHIFT_0 + +#define LPDDR4__DENALI_PHY_5__PHY_PER_RANK_CS_MAP_0_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_5__PHY_PER_RANK_CS_MAP_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_5__PHY_PER_RANK_CS_MAP_0_WIDTH 2U +#define LPDDR4__PHY_PER_RANK_CS_MAP_0__REG DENALI_PHY_5 +#define LPDDR4__PHY_PER_RANK_CS_MAP_0__FLD LPDDR4__DENALI_PHY_5__PHY_PER_RANK_CS_MAP_0 + +#define LPDDR4__DENALI_PHY_5__PHY_PER_CS_TRAINING_MULTICAST_EN_0_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_5__PHY_PER_CS_TRAINING_MULTICAST_EN_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_5__PHY_PER_CS_TRAINING_MULTICAST_EN_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_5__PHY_PER_CS_TRAINING_MULTICAST_EN_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_5__PHY_PER_CS_TRAINING_MULTICAST_EN_0_WOSET 0U +#define LPDDR4__PHY_PER_CS_TRAINING_MULTICAST_EN_0__REG DENALI_PHY_5 +#define LPDDR4__PHY_PER_CS_TRAINING_MULTICAST_EN_0__FLD LPDDR4__DENALI_PHY_5__PHY_PER_CS_TRAINING_MULTICAST_EN_0 + +#define LPDDR4__DENALI_PHY_6_READ_MASK 0x1F1F0301U +#define LPDDR4__DENALI_PHY_6_WRITE_MASK 0x1F1F0301U +#define LPDDR4__DENALI_PHY_6__PHY_PER_CS_TRAINING_INDEX_0_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_6__PHY_PER_CS_TRAINING_INDEX_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_6__PHY_PER_CS_TRAINING_INDEX_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_6__PHY_PER_CS_TRAINING_INDEX_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_6__PHY_PER_CS_TRAINING_INDEX_0_WOSET 0U +#define LPDDR4__PHY_PER_CS_TRAINING_INDEX_0__REG DENALI_PHY_6 +#define LPDDR4__PHY_PER_CS_TRAINING_INDEX_0__FLD LPDDR4__DENALI_PHY_6__PHY_PER_CS_TRAINING_INDEX_0 + +#define LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_0_MASK 0x00000300U +#define LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_0_WIDTH 2U +#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_0__REG DENALI_PHY_6 +#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_0__FLD LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_0 + +#define LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RDDATA_EN_DLY_0_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RDDATA_EN_DLY_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RDDATA_EN_DLY_0_WIDTH 5U +#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_DLY_0__REG DENALI_PHY_6 +#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_DLY_0__FLD LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RDDATA_EN_DLY_0 + +#define LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_0_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_0_WIDTH 5U +#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_0__REG DENALI_PHY_6 +#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_0__FLD LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_0 + +#define LPDDR4__DENALI_PHY_7_READ_MASK 0x1F030F0FU +#define LPDDR4__DENALI_PHY_7_WRITE_MASK 0x1F030F0FU +#define LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_RPTR_UPDATE_0_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_RPTR_UPDATE_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_RPTR_UPDATE_0_WIDTH 4U +#define LPDDR4__PHY_LP4_BOOT_RPTR_UPDATE_0__REG DENALI_PHY_7 +#define LPDDR4__PHY_LP4_BOOT_RPTR_UPDATE_0__FLD LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_RPTR_UPDATE_0 + +#define LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_0_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_0_WIDTH 4U +#define LPDDR4__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_0__REG DENALI_PHY_7 +#define LPDDR4__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_0__FLD LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_0 + +#define LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_0_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_0_WIDTH 2U +#define LPDDR4__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_0__REG DENALI_PHY_7 +#define LPDDR4__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_0__FLD LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_0 + +#define LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_0_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_0_WIDTH 5U +#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_0__REG DENALI_PHY_7 +#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_0__FLD LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_0 + +#define LPDDR4__DENALI_PHY_8_READ_MASK 0x0101FF03U +#define LPDDR4__DENALI_PHY_8_WRITE_MASK 0x0101FF03U +#define LPDDR4__DENALI_PHY_8__PHY_CTRL_LPBK_EN_0_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_8__PHY_CTRL_LPBK_EN_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_8__PHY_CTRL_LPBK_EN_0_WIDTH 2U +#define LPDDR4__PHY_CTRL_LPBK_EN_0__REG DENALI_PHY_8 +#define LPDDR4__PHY_CTRL_LPBK_EN_0__FLD LPDDR4__DENALI_PHY_8__PHY_CTRL_LPBK_EN_0 + +#define LPDDR4__DENALI_PHY_8__PHY_LPBK_CONTROL_0_MASK 0x0001FF00U +#define LPDDR4__DENALI_PHY_8__PHY_LPBK_CONTROL_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_8__PHY_LPBK_CONTROL_0_WIDTH 9U +#define LPDDR4__PHY_LPBK_CONTROL_0__REG DENALI_PHY_8 +#define LPDDR4__PHY_LPBK_CONTROL_0__FLD LPDDR4__DENALI_PHY_8__PHY_LPBK_CONTROL_0 + +#define LPDDR4__DENALI_PHY_8__PHY_LPBK_DFX_TIMEOUT_EN_0_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_8__PHY_LPBK_DFX_TIMEOUT_EN_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_8__PHY_LPBK_DFX_TIMEOUT_EN_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_8__PHY_LPBK_DFX_TIMEOUT_EN_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_8__PHY_LPBK_DFX_TIMEOUT_EN_0_WOSET 0U +#define LPDDR4__PHY_LPBK_DFX_TIMEOUT_EN_0__REG DENALI_PHY_8 +#define LPDDR4__PHY_LPBK_DFX_TIMEOUT_EN_0__FLD LPDDR4__DENALI_PHY_8__PHY_LPBK_DFX_TIMEOUT_EN_0 + +#define LPDDR4__DENALI_PHY_9_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_9_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_9__PHY_AUTO_TIMING_MARGIN_CONTROL_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_9__PHY_AUTO_TIMING_MARGIN_CONTROL_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_9__PHY_AUTO_TIMING_MARGIN_CONTROL_0_WIDTH 32U +#define LPDDR4__PHY_AUTO_TIMING_MARGIN_CONTROL_0__REG DENALI_PHY_9 +#define LPDDR4__PHY_AUTO_TIMING_MARGIN_CONTROL_0__FLD LPDDR4__DENALI_PHY_9__PHY_AUTO_TIMING_MARGIN_CONTROL_0 + +#define LPDDR4__DENALI_PHY_10_READ_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_10_WRITE_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_10__PHY_AUTO_TIMING_MARGIN_OBS_0_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_10__PHY_AUTO_TIMING_MARGIN_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_10__PHY_AUTO_TIMING_MARGIN_OBS_0_WIDTH 28U +#define LPDDR4__PHY_AUTO_TIMING_MARGIN_OBS_0__REG DENALI_PHY_10 +#define LPDDR4__PHY_AUTO_TIMING_MARGIN_OBS_0__FLD LPDDR4__DENALI_PHY_10__PHY_AUTO_TIMING_MARGIN_OBS_0 + +#define LPDDR4__DENALI_PHY_11_READ_MASK 0x0101FF7FU +#define LPDDR4__DENALI_PHY_11_WRITE_MASK 0x0101FF7FU +#define LPDDR4__DENALI_PHY_11__PHY_PRBS_PATTERN_START_0_MASK 0x0000007FU +#define LPDDR4__DENALI_PHY_11__PHY_PRBS_PATTERN_START_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_11__PHY_PRBS_PATTERN_START_0_WIDTH 7U +#define LPDDR4__PHY_PRBS_PATTERN_START_0__REG DENALI_PHY_11 +#define LPDDR4__PHY_PRBS_PATTERN_START_0__FLD LPDDR4__DENALI_PHY_11__PHY_PRBS_PATTERN_START_0 + +#define LPDDR4__DENALI_PHY_11__PHY_PRBS_PATTERN_MASK_0_MASK 0x0001FF00U +#define LPDDR4__DENALI_PHY_11__PHY_PRBS_PATTERN_MASK_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_11__PHY_PRBS_PATTERN_MASK_0_WIDTH 9U +#define LPDDR4__PHY_PRBS_PATTERN_MASK_0__REG DENALI_PHY_11 +#define LPDDR4__PHY_PRBS_PATTERN_MASK_0__FLD LPDDR4__DENALI_PHY_11__PHY_PRBS_PATTERN_MASK_0 + +#define LPDDR4__DENALI_PHY_11__PHY_RDLVL_MULTI_PATT_ENABLE_0_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_11__PHY_RDLVL_MULTI_PATT_ENABLE_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_11__PHY_RDLVL_MULTI_PATT_ENABLE_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_11__PHY_RDLVL_MULTI_PATT_ENABLE_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_11__PHY_RDLVL_MULTI_PATT_ENABLE_0_WOSET 0U +#define LPDDR4__PHY_RDLVL_MULTI_PATT_ENABLE_0__REG DENALI_PHY_11 +#define LPDDR4__PHY_RDLVL_MULTI_PATT_ENABLE_0__FLD LPDDR4__DENALI_PHY_11__PHY_RDLVL_MULTI_PATT_ENABLE_0 + +#define LPDDR4__DENALI_PHY_12_READ_MASK 0x007F3F01U +#define LPDDR4__DENALI_PHY_12_WRITE_MASK 0x007F3F01U +#define LPDDR4__DENALI_PHY_12__PHY_RDLVL_MULTI_PATT_RST_DISABLE_0_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_12__PHY_RDLVL_MULTI_PATT_RST_DISABLE_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_12__PHY_RDLVL_MULTI_PATT_RST_DISABLE_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_12__PHY_RDLVL_MULTI_PATT_RST_DISABLE_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_12__PHY_RDLVL_MULTI_PATT_RST_DISABLE_0_WOSET 0U +#define LPDDR4__PHY_RDLVL_MULTI_PATT_RST_DISABLE_0__REG DENALI_PHY_12 +#define LPDDR4__PHY_RDLVL_MULTI_PATT_RST_DISABLE_0__FLD LPDDR4__DENALI_PHY_12__PHY_RDLVL_MULTI_PATT_RST_DISABLE_0 + +#define LPDDR4__DENALI_PHY_12__PHY_VREF_INITIAL_STEPSIZE_0_MASK 0x00003F00U +#define LPDDR4__DENALI_PHY_12__PHY_VREF_INITIAL_STEPSIZE_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_12__PHY_VREF_INITIAL_STEPSIZE_0_WIDTH 6U +#define LPDDR4__PHY_VREF_INITIAL_STEPSIZE_0__REG DENALI_PHY_12 +#define LPDDR4__PHY_VREF_INITIAL_STEPSIZE_0__FLD LPDDR4__DENALI_PHY_12__PHY_VREF_INITIAL_STEPSIZE_0 + +#define LPDDR4__DENALI_PHY_12__PHY_VREF_TRAIN_OBS_0_MASK 0x007F0000U +#define LPDDR4__DENALI_PHY_12__PHY_VREF_TRAIN_OBS_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_12__PHY_VREF_TRAIN_OBS_0_WIDTH 7U +#define LPDDR4__PHY_VREF_TRAIN_OBS_0__REG DENALI_PHY_12 +#define LPDDR4__PHY_VREF_TRAIN_OBS_0__FLD LPDDR4__DENALI_PHY_12__PHY_VREF_TRAIN_OBS_0 + +#define LPDDR4__DENALI_PHY_13_READ_MASK 0x000F03FFU +#define LPDDR4__DENALI_PHY_13_WRITE_MASK 0x000F03FFU +#define LPDDR4__DENALI_PHY_13__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_0_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_13__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_13__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_0__REG DENALI_PHY_13 +#define LPDDR4__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_13__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_13__PHY_GATE_ERROR_DELAY_SELECT_0_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_13__PHY_GATE_ERROR_DELAY_SELECT_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_13__PHY_GATE_ERROR_DELAY_SELECT_0_WIDTH 4U +#define LPDDR4__PHY_GATE_ERROR_DELAY_SELECT_0__REG DENALI_PHY_13 +#define LPDDR4__PHY_GATE_ERROR_DELAY_SELECT_0__FLD LPDDR4__DENALI_PHY_13__PHY_GATE_ERROR_DELAY_SELECT_0 + +#define LPDDR4__DENALI_PHY_13__SC_PHY_SNAP_OBS_REGS_0_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_13__SC_PHY_SNAP_OBS_REGS_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_13__SC_PHY_SNAP_OBS_REGS_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_13__SC_PHY_SNAP_OBS_REGS_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_13__SC_PHY_SNAP_OBS_REGS_0_WOSET 0U +#define LPDDR4__SC_PHY_SNAP_OBS_REGS_0__REG DENALI_PHY_13 +#define LPDDR4__SC_PHY_SNAP_OBS_REGS_0__FLD LPDDR4__DENALI_PHY_13__SC_PHY_SNAP_OBS_REGS_0 + +#define LPDDR4__DENALI_PHY_14_READ_MASK 0x070101FFU +#define LPDDR4__DENALI_PHY_14_WRITE_MASK 0x070101FFU +#define LPDDR4__DENALI_PHY_14__PHY_GATE_SMPL1_SLAVE_DELAY_0_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_14__PHY_GATE_SMPL1_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_14__PHY_GATE_SMPL1_SLAVE_DELAY_0_WIDTH 9U +#define LPDDR4__PHY_GATE_SMPL1_SLAVE_DELAY_0__REG DENALI_PHY_14 +#define LPDDR4__PHY_GATE_SMPL1_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_14__PHY_GATE_SMPL1_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_14__PHY_LPDDR_0_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_14__PHY_LPDDR_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_14__PHY_LPDDR_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_14__PHY_LPDDR_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_14__PHY_LPDDR_0_WOSET 0U +#define LPDDR4__PHY_LPDDR_0__REG DENALI_PHY_14 +#define LPDDR4__PHY_LPDDR_0__FLD LPDDR4__DENALI_PHY_14__PHY_LPDDR_0 + +#define LPDDR4__DENALI_PHY_14__PHY_MEM_CLASS_0_MASK 0x07000000U +#define LPDDR4__DENALI_PHY_14__PHY_MEM_CLASS_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_14__PHY_MEM_CLASS_0_WIDTH 3U +#define LPDDR4__PHY_MEM_CLASS_0__REG DENALI_PHY_14 +#define LPDDR4__PHY_MEM_CLASS_0__FLD LPDDR4__DENALI_PHY_14__PHY_MEM_CLASS_0 + +#define LPDDR4__DENALI_PHY_15_READ_MASK 0x000301FFU +#define LPDDR4__DENALI_PHY_15_WRITE_MASK 0x000301FFU +#define LPDDR4__DENALI_PHY_15__PHY_GATE_SMPL2_SLAVE_DELAY_0_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_15__PHY_GATE_SMPL2_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_15__PHY_GATE_SMPL2_SLAVE_DELAY_0_WIDTH 9U +#define LPDDR4__PHY_GATE_SMPL2_SLAVE_DELAY_0__REG DENALI_PHY_15 +#define LPDDR4__PHY_GATE_SMPL2_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_15__PHY_GATE_SMPL2_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_15__ON_FLY_GATE_ADJUST_EN_0_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_15__ON_FLY_GATE_ADJUST_EN_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_15__ON_FLY_GATE_ADJUST_EN_0_WIDTH 2U +#define LPDDR4__ON_FLY_GATE_ADJUST_EN_0__REG DENALI_PHY_15 +#define LPDDR4__ON_FLY_GATE_ADJUST_EN_0__FLD LPDDR4__DENALI_PHY_15__ON_FLY_GATE_ADJUST_EN_0 + +#define LPDDR4__DENALI_PHY_16_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_16_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_16__PHY_GATE_TRACKING_OBS_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_16__PHY_GATE_TRACKING_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_16__PHY_GATE_TRACKING_OBS_0_WIDTH 32U +#define LPDDR4__PHY_GATE_TRACKING_OBS_0__REG DENALI_PHY_16 +#define LPDDR4__PHY_GATE_TRACKING_OBS_0__FLD LPDDR4__DENALI_PHY_16__PHY_GATE_TRACKING_OBS_0 + +#define LPDDR4__DENALI_PHY_17_READ_MASK 0x00000301U +#define LPDDR4__DENALI_PHY_17_WRITE_MASK 0x00000301U +#define LPDDR4__DENALI_PHY_17__PHY_DFI40_POLARITY_0_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_17__PHY_DFI40_POLARITY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_17__PHY_DFI40_POLARITY_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_17__PHY_DFI40_POLARITY_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_17__PHY_DFI40_POLARITY_0_WOSET 0U +#define LPDDR4__PHY_DFI40_POLARITY_0__REG DENALI_PHY_17 +#define LPDDR4__PHY_DFI40_POLARITY_0__FLD LPDDR4__DENALI_PHY_17__PHY_DFI40_POLARITY_0 + +#define LPDDR4__DENALI_PHY_17__PHY_LP4_PST_AMBLE_0_MASK 0x00000300U +#define LPDDR4__DENALI_PHY_17__PHY_LP4_PST_AMBLE_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_17__PHY_LP4_PST_AMBLE_0_WIDTH 2U +#define LPDDR4__PHY_LP4_PST_AMBLE_0__REG DENALI_PHY_17 +#define LPDDR4__PHY_LP4_PST_AMBLE_0__FLD LPDDR4__DENALI_PHY_17__PHY_LP4_PST_AMBLE_0 + +#define LPDDR4__DENALI_PHY_18_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_18_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_18__PHY_RDLVL_PATT8_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_18__PHY_RDLVL_PATT8_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_18__PHY_RDLVL_PATT8_0_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PATT8_0__REG DENALI_PHY_18 +#define LPDDR4__PHY_RDLVL_PATT8_0__FLD LPDDR4__DENALI_PHY_18__PHY_RDLVL_PATT8_0 + +#define LPDDR4__DENALI_PHY_19_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_19_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_19__PHY_RDLVL_PATT9_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_19__PHY_RDLVL_PATT9_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_19__PHY_RDLVL_PATT9_0_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PATT9_0__REG DENALI_PHY_19 +#define LPDDR4__PHY_RDLVL_PATT9_0__FLD LPDDR4__DENALI_PHY_19__PHY_RDLVL_PATT9_0 + +#define LPDDR4__DENALI_PHY_20_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_20_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_20__PHY_RDLVL_PATT10_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_20__PHY_RDLVL_PATT10_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_20__PHY_RDLVL_PATT10_0_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PATT10_0__REG DENALI_PHY_20 +#define LPDDR4__PHY_RDLVL_PATT10_0__FLD LPDDR4__DENALI_PHY_20__PHY_RDLVL_PATT10_0 + +#define LPDDR4__DENALI_PHY_21_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_21_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_21__PHY_RDLVL_PATT11_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_21__PHY_RDLVL_PATT11_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_21__PHY_RDLVL_PATT11_0_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PATT11_0__REG DENALI_PHY_21 +#define LPDDR4__PHY_RDLVL_PATT11_0__FLD LPDDR4__DENALI_PHY_21__PHY_RDLVL_PATT11_0 + +#define LPDDR4__DENALI_PHY_22_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_22_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_22__PHY_RDLVL_PATT12_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_22__PHY_RDLVL_PATT12_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_22__PHY_RDLVL_PATT12_0_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PATT12_0__REG DENALI_PHY_22 +#define LPDDR4__PHY_RDLVL_PATT12_0__FLD LPDDR4__DENALI_PHY_22__PHY_RDLVL_PATT12_0 + +#define LPDDR4__DENALI_PHY_23_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_23_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_23__PHY_RDLVL_PATT13_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_23__PHY_RDLVL_PATT13_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_23__PHY_RDLVL_PATT13_0_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PATT13_0__REG DENALI_PHY_23 +#define LPDDR4__PHY_RDLVL_PATT13_0__FLD LPDDR4__DENALI_PHY_23__PHY_RDLVL_PATT13_0 + +#define LPDDR4__DENALI_PHY_24_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_24_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_24__PHY_RDLVL_PATT14_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_24__PHY_RDLVL_PATT14_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_24__PHY_RDLVL_PATT14_0_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PATT14_0__REG DENALI_PHY_24 +#define LPDDR4__PHY_RDLVL_PATT14_0__FLD LPDDR4__DENALI_PHY_24__PHY_RDLVL_PATT14_0 + +#define LPDDR4__DENALI_PHY_25_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_25_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_25__PHY_RDLVL_PATT15_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_25__PHY_RDLVL_PATT15_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_25__PHY_RDLVL_PATT15_0_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PATT15_0__REG DENALI_PHY_25 +#define LPDDR4__PHY_RDLVL_PATT15_0__FLD LPDDR4__DENALI_PHY_25__PHY_RDLVL_PATT15_0 + +#define LPDDR4__DENALI_PHY_26_READ_MASK 0x070F0107U +#define LPDDR4__DENALI_PHY_26_WRITE_MASK 0x070F0107U +#define LPDDR4__DENALI_PHY_26__PHY_SLAVE_LOOP_CNT_UPDATE_0_MASK 0x00000007U +#define LPDDR4__DENALI_PHY_26__PHY_SLAVE_LOOP_CNT_UPDATE_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_26__PHY_SLAVE_LOOP_CNT_UPDATE_0_WIDTH 3U +#define LPDDR4__PHY_SLAVE_LOOP_CNT_UPDATE_0__REG DENALI_PHY_26 +#define LPDDR4__PHY_SLAVE_LOOP_CNT_UPDATE_0__FLD LPDDR4__DENALI_PHY_26__PHY_SLAVE_LOOP_CNT_UPDATE_0 + +#define LPDDR4__DENALI_PHY_26__PHY_SW_FIFO_PTR_RST_DISABLE_0_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_26__PHY_SW_FIFO_PTR_RST_DISABLE_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_26__PHY_SW_FIFO_PTR_RST_DISABLE_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_26__PHY_SW_FIFO_PTR_RST_DISABLE_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_26__PHY_SW_FIFO_PTR_RST_DISABLE_0_WOSET 0U +#define LPDDR4__PHY_SW_FIFO_PTR_RST_DISABLE_0__REG DENALI_PHY_26 +#define LPDDR4__PHY_SW_FIFO_PTR_RST_DISABLE_0__FLD LPDDR4__DENALI_PHY_26__PHY_SW_FIFO_PTR_RST_DISABLE_0 + +#define LPDDR4__DENALI_PHY_26__PHY_MASTER_DLY_LOCK_OBS_SELECT_0_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_26__PHY_MASTER_DLY_LOCK_OBS_SELECT_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_26__PHY_MASTER_DLY_LOCK_OBS_SELECT_0_WIDTH 4U +#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_SELECT_0__REG DENALI_PHY_26 +#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_26__PHY_MASTER_DLY_LOCK_OBS_SELECT_0 + +#define LPDDR4__DENALI_PHY_26__PHY_RDDQ_ENC_OBS_SELECT_0_MASK 0x07000000U +#define LPDDR4__DENALI_PHY_26__PHY_RDDQ_ENC_OBS_SELECT_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_26__PHY_RDDQ_ENC_OBS_SELECT_0_WIDTH 3U +#define LPDDR4__PHY_RDDQ_ENC_OBS_SELECT_0__REG DENALI_PHY_26 +#define LPDDR4__PHY_RDDQ_ENC_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_26__PHY_RDDQ_ENC_OBS_SELECT_0 + +#define LPDDR4__DENALI_PHY_27_READ_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_PHY_27_WRITE_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_PHY_27__PHY_RDDQS_DQ_ENC_OBS_SELECT_0_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_27__PHY_RDDQS_DQ_ENC_OBS_SELECT_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_27__PHY_RDDQS_DQ_ENC_OBS_SELECT_0_WIDTH 4U +#define LPDDR4__PHY_RDDQS_DQ_ENC_OBS_SELECT_0__REG DENALI_PHY_27 +#define LPDDR4__PHY_RDDQS_DQ_ENC_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_27__PHY_RDDQS_DQ_ENC_OBS_SELECT_0 + +#define LPDDR4__DENALI_PHY_27__PHY_WR_ENC_OBS_SELECT_0_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_27__PHY_WR_ENC_OBS_SELECT_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_27__PHY_WR_ENC_OBS_SELECT_0_WIDTH 4U +#define LPDDR4__PHY_WR_ENC_OBS_SELECT_0__REG DENALI_PHY_27 +#define LPDDR4__PHY_WR_ENC_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_27__PHY_WR_ENC_OBS_SELECT_0 + +#define LPDDR4__DENALI_PHY_27__PHY_WR_SHIFT_OBS_SELECT_0_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_27__PHY_WR_SHIFT_OBS_SELECT_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_27__PHY_WR_SHIFT_OBS_SELECT_0_WIDTH 4U +#define LPDDR4__PHY_WR_SHIFT_OBS_SELECT_0__REG DENALI_PHY_27 +#define LPDDR4__PHY_WR_SHIFT_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_27__PHY_WR_SHIFT_OBS_SELECT_0 + +#define LPDDR4__DENALI_PHY_27__PHY_FIFO_PTR_OBS_SELECT_0_MASK 0x0F000000U +#define LPDDR4__DENALI_PHY_27__PHY_FIFO_PTR_OBS_SELECT_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_27__PHY_FIFO_PTR_OBS_SELECT_0_WIDTH 4U +#define LPDDR4__PHY_FIFO_PTR_OBS_SELECT_0__REG DENALI_PHY_27 +#define LPDDR4__PHY_FIFO_PTR_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_27__PHY_FIFO_PTR_OBS_SELECT_0 + +#define LPDDR4__DENALI_PHY_28_READ_MASK 0xFF030001U +#define LPDDR4__DENALI_PHY_28_WRITE_MASK 0xFF030001U +#define LPDDR4__DENALI_PHY_28__PHY_LVL_DEBUG_MODE_0_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_28__PHY_LVL_DEBUG_MODE_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_28__PHY_LVL_DEBUG_MODE_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_28__PHY_LVL_DEBUG_MODE_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_28__PHY_LVL_DEBUG_MODE_0_WOSET 0U +#define LPDDR4__PHY_LVL_DEBUG_MODE_0__REG DENALI_PHY_28 +#define LPDDR4__PHY_LVL_DEBUG_MODE_0__FLD LPDDR4__DENALI_PHY_28__PHY_LVL_DEBUG_MODE_0 + +#define LPDDR4__DENALI_PHY_28__SC_PHY_LVL_DEBUG_CONT_0_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_28__SC_PHY_LVL_DEBUG_CONT_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_28__SC_PHY_LVL_DEBUG_CONT_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_28__SC_PHY_LVL_DEBUG_CONT_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_28__SC_PHY_LVL_DEBUG_CONT_0_WOSET 0U +#define LPDDR4__SC_PHY_LVL_DEBUG_CONT_0__REG DENALI_PHY_28 +#define LPDDR4__SC_PHY_LVL_DEBUG_CONT_0__FLD LPDDR4__DENALI_PHY_28__SC_PHY_LVL_DEBUG_CONT_0 + +#define LPDDR4__DENALI_PHY_28__PHY_WRLVL_ALGO_0_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_28__PHY_WRLVL_ALGO_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_28__PHY_WRLVL_ALGO_0_WIDTH 2U +#define LPDDR4__PHY_WRLVL_ALGO_0__REG DENALI_PHY_28 +#define LPDDR4__PHY_WRLVL_ALGO_0__FLD LPDDR4__DENALI_PHY_28__PHY_WRLVL_ALGO_0 + +#define LPDDR4__DENALI_PHY_28__PHY_WRLVL_PER_START_0_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_28__PHY_WRLVL_PER_START_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_28__PHY_WRLVL_PER_START_0_WIDTH 8U +#define LPDDR4__PHY_WRLVL_PER_START_0__REG DENALI_PHY_28 +#define LPDDR4__PHY_WRLVL_PER_START_0__FLD LPDDR4__DENALI_PHY_28__PHY_WRLVL_PER_START_0 + +#define LPDDR4__DENALI_PHY_29_READ_MASK 0x00FF0F3FU +#define LPDDR4__DENALI_PHY_29_WRITE_MASK 0x00FF0F3FU +#define LPDDR4__DENALI_PHY_29__PHY_WRLVL_CAPTURE_CNT_0_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_29__PHY_WRLVL_CAPTURE_CNT_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_29__PHY_WRLVL_CAPTURE_CNT_0_WIDTH 6U +#define LPDDR4__PHY_WRLVL_CAPTURE_CNT_0__REG DENALI_PHY_29 +#define LPDDR4__PHY_WRLVL_CAPTURE_CNT_0__FLD LPDDR4__DENALI_PHY_29__PHY_WRLVL_CAPTURE_CNT_0 + +#define LPDDR4__DENALI_PHY_29__PHY_WRLVL_UPDT_WAIT_CNT_0_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_29__PHY_WRLVL_UPDT_WAIT_CNT_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_29__PHY_WRLVL_UPDT_WAIT_CNT_0_WIDTH 4U +#define LPDDR4__PHY_WRLVL_UPDT_WAIT_CNT_0__REG DENALI_PHY_29 +#define LPDDR4__PHY_WRLVL_UPDT_WAIT_CNT_0__FLD LPDDR4__DENALI_PHY_29__PHY_WRLVL_UPDT_WAIT_CNT_0 + +#define LPDDR4__DENALI_PHY_29__PHY_DQ_MASK_0_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_29__PHY_DQ_MASK_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_29__PHY_DQ_MASK_0_WIDTH 8U +#define LPDDR4__PHY_DQ_MASK_0__REG DENALI_PHY_29 +#define LPDDR4__PHY_DQ_MASK_0__FLD LPDDR4__DENALI_PHY_29__PHY_DQ_MASK_0 + +#define LPDDR4__DENALI_PHY_30_READ_MASK 0x0F3F03FFU +#define LPDDR4__DENALI_PHY_30_WRITE_MASK 0x0F3F03FFU +#define LPDDR4__DENALI_PHY_30__PHY_GTLVL_PER_START_0_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_30__PHY_GTLVL_PER_START_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_30__PHY_GTLVL_PER_START_0_WIDTH 10U +#define LPDDR4__PHY_GTLVL_PER_START_0__REG DENALI_PHY_30 +#define LPDDR4__PHY_GTLVL_PER_START_0__FLD LPDDR4__DENALI_PHY_30__PHY_GTLVL_PER_START_0 + +#define LPDDR4__DENALI_PHY_30__PHY_GTLVL_CAPTURE_CNT_0_MASK 0x003F0000U +#define LPDDR4__DENALI_PHY_30__PHY_GTLVL_CAPTURE_CNT_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_30__PHY_GTLVL_CAPTURE_CNT_0_WIDTH 6U +#define LPDDR4__PHY_GTLVL_CAPTURE_CNT_0__REG DENALI_PHY_30 +#define LPDDR4__PHY_GTLVL_CAPTURE_CNT_0__FLD LPDDR4__DENALI_PHY_30__PHY_GTLVL_CAPTURE_CNT_0 + +#define LPDDR4__DENALI_PHY_30__PHY_GTLVL_UPDT_WAIT_CNT_0_MASK 0x0F000000U +#define LPDDR4__DENALI_PHY_30__PHY_GTLVL_UPDT_WAIT_CNT_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_30__PHY_GTLVL_UPDT_WAIT_CNT_0_WIDTH 4U +#define LPDDR4__PHY_GTLVL_UPDT_WAIT_CNT_0__REG DENALI_PHY_30 +#define LPDDR4__PHY_GTLVL_UPDT_WAIT_CNT_0__FLD LPDDR4__DENALI_PHY_30__PHY_GTLVL_UPDT_WAIT_CNT_0 + +#define LPDDR4__DENALI_PHY_31_READ_MASK 0x1F030F3FU +#define LPDDR4__DENALI_PHY_31_WRITE_MASK 0x1F030F3FU +#define LPDDR4__DENALI_PHY_31__PHY_RDLVL_CAPTURE_CNT_0_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_31__PHY_RDLVL_CAPTURE_CNT_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_31__PHY_RDLVL_CAPTURE_CNT_0_WIDTH 6U +#define LPDDR4__PHY_RDLVL_CAPTURE_CNT_0__REG DENALI_PHY_31 +#define LPDDR4__PHY_RDLVL_CAPTURE_CNT_0__FLD LPDDR4__DENALI_PHY_31__PHY_RDLVL_CAPTURE_CNT_0 + +#define LPDDR4__DENALI_PHY_31__PHY_RDLVL_UPDT_WAIT_CNT_0_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_31__PHY_RDLVL_UPDT_WAIT_CNT_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_31__PHY_RDLVL_UPDT_WAIT_CNT_0_WIDTH 4U +#define LPDDR4__PHY_RDLVL_UPDT_WAIT_CNT_0__REG DENALI_PHY_31 +#define LPDDR4__PHY_RDLVL_UPDT_WAIT_CNT_0__FLD LPDDR4__DENALI_PHY_31__PHY_RDLVL_UPDT_WAIT_CNT_0 + +#define LPDDR4__DENALI_PHY_31__PHY_RDLVL_OP_MODE_0_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_31__PHY_RDLVL_OP_MODE_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_31__PHY_RDLVL_OP_MODE_0_WIDTH 2U +#define LPDDR4__PHY_RDLVL_OP_MODE_0__REG DENALI_PHY_31 +#define LPDDR4__PHY_RDLVL_OP_MODE_0__FLD LPDDR4__DENALI_PHY_31__PHY_RDLVL_OP_MODE_0 + +#define LPDDR4__DENALI_PHY_31__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_0_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_31__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_31__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_0_WIDTH 5U +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_0__REG DENALI_PHY_31 +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_31__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_0 + +#define LPDDR4__DENALI_PHY_32_READ_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_32_WRITE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_32__PHY_RDLVL_PERIODIC_OBS_SELECT_0_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_32__PHY_RDLVL_PERIODIC_OBS_SELECT_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_32__PHY_RDLVL_PERIODIC_OBS_SELECT_0_WIDTH 8U +#define LPDDR4__PHY_RDLVL_PERIODIC_OBS_SELECT_0__REG DENALI_PHY_32 +#define LPDDR4__PHY_RDLVL_PERIODIC_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_32__PHY_RDLVL_PERIODIC_OBS_SELECT_0 + +#define LPDDR4__DENALI_PHY_32__PHY_RDLVL_DATA_MASK_0_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_32__PHY_RDLVL_DATA_MASK_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_32__PHY_RDLVL_DATA_MASK_0_WIDTH 8U +#define LPDDR4__PHY_RDLVL_DATA_MASK_0__REG DENALI_PHY_32 +#define LPDDR4__PHY_RDLVL_DATA_MASK_0__FLD LPDDR4__DENALI_PHY_32__PHY_RDLVL_DATA_MASK_0 + +#define LPDDR4__DENALI_PHY_32__PHY_WDQLVL_CLK_JITTER_TOLERANCE_0_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_32__PHY_WDQLVL_CLK_JITTER_TOLERANCE_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_32__PHY_WDQLVL_CLK_JITTER_TOLERANCE_0_WIDTH 8U +#define LPDDR4__PHY_WDQLVL_CLK_JITTER_TOLERANCE_0__REG DENALI_PHY_32 +#define LPDDR4__PHY_WDQLVL_CLK_JITTER_TOLERANCE_0__FLD LPDDR4__DENALI_PHY_32__PHY_WDQLVL_CLK_JITTER_TOLERANCE_0 + +#define LPDDR4__DENALI_PHY_32__PHY_WDQLVL_BURST_CNT_0_MASK 0x3F000000U +#define LPDDR4__DENALI_PHY_32__PHY_WDQLVL_BURST_CNT_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_32__PHY_WDQLVL_BURST_CNT_0_WIDTH 6U +#define LPDDR4__PHY_WDQLVL_BURST_CNT_0__REG DENALI_PHY_32 +#define LPDDR4__PHY_WDQLVL_BURST_CNT_0__FLD LPDDR4__DENALI_PHY_32__PHY_WDQLVL_BURST_CNT_0 + +#define LPDDR4__DENALI_PHY_33_READ_MASK 0x0F07FF07U +#define LPDDR4__DENALI_PHY_33_WRITE_MASK 0x0F07FF07U +#define LPDDR4__DENALI_PHY_33__PHY_WDQLVL_PATT_0_MASK 0x00000007U +#define LPDDR4__DENALI_PHY_33__PHY_WDQLVL_PATT_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_33__PHY_WDQLVL_PATT_0_WIDTH 3U +#define LPDDR4__PHY_WDQLVL_PATT_0__REG DENALI_PHY_33 +#define LPDDR4__PHY_WDQLVL_PATT_0__FLD LPDDR4__DENALI_PHY_33__PHY_WDQLVL_PATT_0 + +#define LPDDR4__DENALI_PHY_33__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_0_MASK 0x0007FF00U +#define LPDDR4__DENALI_PHY_33__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_33__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_0_WIDTH 11U +#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_0__REG DENALI_PHY_33 +#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_0__FLD LPDDR4__DENALI_PHY_33__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_0 + +#define LPDDR4__DENALI_PHY_33__PHY_WDQLVL_UPDT_WAIT_CNT_0_MASK 0x0F000000U +#define LPDDR4__DENALI_PHY_33__PHY_WDQLVL_UPDT_WAIT_CNT_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_33__PHY_WDQLVL_UPDT_WAIT_CNT_0_WIDTH 4U +#define LPDDR4__PHY_WDQLVL_UPDT_WAIT_CNT_0__REG DENALI_PHY_33 +#define LPDDR4__PHY_WDQLVL_UPDT_WAIT_CNT_0__FLD LPDDR4__DENALI_PHY_33__PHY_WDQLVL_UPDT_WAIT_CNT_0 + +#define LPDDR4__DENALI_PHY_34_READ_MASK 0x0000FF0FU +#define LPDDR4__DENALI_PHY_34_WRITE_MASK 0x0000FF0FU +#define LPDDR4__DENALI_PHY_34__PHY_WDQLVL_DQDM_OBS_SELECT_0_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_34__PHY_WDQLVL_DQDM_OBS_SELECT_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_34__PHY_WDQLVL_DQDM_OBS_SELECT_0_WIDTH 4U +#define LPDDR4__PHY_WDQLVL_DQDM_OBS_SELECT_0__REG DENALI_PHY_34 +#define LPDDR4__PHY_WDQLVL_DQDM_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_34__PHY_WDQLVL_DQDM_OBS_SELECT_0 + +#define LPDDR4__DENALI_PHY_34__PHY_WDQLVL_PERIODIC_OBS_SELECT_0_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_34__PHY_WDQLVL_PERIODIC_OBS_SELECT_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_34__PHY_WDQLVL_PERIODIC_OBS_SELECT_0_WIDTH 8U +#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_SELECT_0__REG DENALI_PHY_34 +#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_34__PHY_WDQLVL_PERIODIC_OBS_SELECT_0 + +#define LPDDR4__DENALI_PHY_34__SC_PHY_WDQLVL_CLR_PREV_RESULTS_0_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_34__SC_PHY_WDQLVL_CLR_PREV_RESULTS_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_34__SC_PHY_WDQLVL_CLR_PREV_RESULTS_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_34__SC_PHY_WDQLVL_CLR_PREV_RESULTS_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_34__SC_PHY_WDQLVL_CLR_PREV_RESULTS_0_WOSET 0U +#define LPDDR4__SC_PHY_WDQLVL_CLR_PREV_RESULTS_0__REG DENALI_PHY_34 +#define LPDDR4__SC_PHY_WDQLVL_CLR_PREV_RESULTS_0__FLD LPDDR4__DENALI_PHY_34__SC_PHY_WDQLVL_CLR_PREV_RESULTS_0 + +#define LPDDR4__DENALI_PHY_35_READ_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_35_WRITE_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_35__PHY_WDQLVL_DATADM_MASK_0_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_35__PHY_WDQLVL_DATADM_MASK_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_35__PHY_WDQLVL_DATADM_MASK_0_WIDTH 9U +#define LPDDR4__PHY_WDQLVL_DATADM_MASK_0__REG DENALI_PHY_35 +#define LPDDR4__PHY_WDQLVL_DATADM_MASK_0__FLD LPDDR4__DENALI_PHY_35__PHY_WDQLVL_DATADM_MASK_0 + +#define LPDDR4__DENALI_PHY_36_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_36_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_36__PHY_USER_PATT0_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_36__PHY_USER_PATT0_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_36__PHY_USER_PATT0_0_WIDTH 32U +#define LPDDR4__PHY_USER_PATT0_0__REG DENALI_PHY_36 +#define LPDDR4__PHY_USER_PATT0_0__FLD LPDDR4__DENALI_PHY_36__PHY_USER_PATT0_0 + +#define LPDDR4__DENALI_PHY_37_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_37_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_37__PHY_USER_PATT1_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_37__PHY_USER_PATT1_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_37__PHY_USER_PATT1_0_WIDTH 32U +#define LPDDR4__PHY_USER_PATT1_0__REG DENALI_PHY_37 +#define LPDDR4__PHY_USER_PATT1_0__FLD LPDDR4__DENALI_PHY_37__PHY_USER_PATT1_0 + +#define LPDDR4__DENALI_PHY_38_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_38_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_38__PHY_USER_PATT2_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_38__PHY_USER_PATT2_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_38__PHY_USER_PATT2_0_WIDTH 32U +#define LPDDR4__PHY_USER_PATT2_0__REG DENALI_PHY_38 +#define LPDDR4__PHY_USER_PATT2_0__FLD LPDDR4__DENALI_PHY_38__PHY_USER_PATT2_0 + +#define LPDDR4__DENALI_PHY_39_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_39_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_39__PHY_USER_PATT3_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_39__PHY_USER_PATT3_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_39__PHY_USER_PATT3_0_WIDTH 32U +#define LPDDR4__PHY_USER_PATT3_0__REG DENALI_PHY_39 +#define LPDDR4__PHY_USER_PATT3_0__FLD LPDDR4__DENALI_PHY_39__PHY_USER_PATT3_0 + +#define LPDDR4__DENALI_PHY_40_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PHY_40_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PHY_40__PHY_USER_PATT4_0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_40__PHY_USER_PATT4_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_40__PHY_USER_PATT4_0_WIDTH 16U +#define LPDDR4__PHY_USER_PATT4_0__REG DENALI_PHY_40 +#define LPDDR4__PHY_USER_PATT4_0__FLD LPDDR4__DENALI_PHY_40__PHY_USER_PATT4_0 + +#define LPDDR4__DENALI_PHY_40__PHY_NTP_MULT_TRAIN_0_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_40__PHY_NTP_MULT_TRAIN_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_40__PHY_NTP_MULT_TRAIN_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_40__PHY_NTP_MULT_TRAIN_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_40__PHY_NTP_MULT_TRAIN_0_WOSET 0U +#define LPDDR4__PHY_NTP_MULT_TRAIN_0__REG DENALI_PHY_40 +#define LPDDR4__PHY_NTP_MULT_TRAIN_0__FLD LPDDR4__DENALI_PHY_40__PHY_NTP_MULT_TRAIN_0 + +#define LPDDR4__DENALI_PHY_41_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_41_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_41__PHY_NTP_EARLY_THRESHOLD_0_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_41__PHY_NTP_EARLY_THRESHOLD_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_41__PHY_NTP_EARLY_THRESHOLD_0_WIDTH 10U +#define LPDDR4__PHY_NTP_EARLY_THRESHOLD_0__REG DENALI_PHY_41 +#define LPDDR4__PHY_NTP_EARLY_THRESHOLD_0__FLD LPDDR4__DENALI_PHY_41__PHY_NTP_EARLY_THRESHOLD_0 + +#define LPDDR4__DENALI_PHY_41__PHY_NTP_PERIOD_THRESHOLD_0_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_41__PHY_NTP_PERIOD_THRESHOLD_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_41__PHY_NTP_PERIOD_THRESHOLD_0_WIDTH 10U +#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_0__REG DENALI_PHY_41 +#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_0__FLD LPDDR4__DENALI_PHY_41__PHY_NTP_PERIOD_THRESHOLD_0 + +#define LPDDR4__DENALI_PHY_42_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_42_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_42__PHY_NTP_PERIOD_THRESHOLD_MIN_0_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_42__PHY_NTP_PERIOD_THRESHOLD_MIN_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_42__PHY_NTP_PERIOD_THRESHOLD_MIN_0_WIDTH 10U +#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MIN_0__REG DENALI_PHY_42 +#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MIN_0__FLD LPDDR4__DENALI_PHY_42__PHY_NTP_PERIOD_THRESHOLD_MIN_0 + +#define LPDDR4__DENALI_PHY_42__PHY_NTP_PERIOD_THRESHOLD_MAX_0_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_42__PHY_NTP_PERIOD_THRESHOLD_MAX_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_42__PHY_NTP_PERIOD_THRESHOLD_MAX_0_WIDTH 10U +#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MAX_0__REG DENALI_PHY_42 +#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MAX_0__FLD LPDDR4__DENALI_PHY_42__PHY_NTP_PERIOD_THRESHOLD_MAX_0 + +#define LPDDR4__DENALI_PHY_43_READ_MASK 0x00FF0001U +#define LPDDR4__DENALI_PHY_43_WRITE_MASK 0x00FF0001U +#define LPDDR4__DENALI_PHY_43__PHY_CALVL_VREF_DRIVING_SLICE_0_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_43__PHY_CALVL_VREF_DRIVING_SLICE_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_43__PHY_CALVL_VREF_DRIVING_SLICE_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_43__PHY_CALVL_VREF_DRIVING_SLICE_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_43__PHY_CALVL_VREF_DRIVING_SLICE_0_WOSET 0U +#define LPDDR4__PHY_CALVL_VREF_DRIVING_SLICE_0__REG DENALI_PHY_43 +#define LPDDR4__PHY_CALVL_VREF_DRIVING_SLICE_0__FLD LPDDR4__DENALI_PHY_43__PHY_CALVL_VREF_DRIVING_SLICE_0 + +#define LPDDR4__DENALI_PHY_43__SC_PHY_MANUAL_CLEAR_0_MASK 0x00003F00U +#define LPDDR4__DENALI_PHY_43__SC_PHY_MANUAL_CLEAR_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_43__SC_PHY_MANUAL_CLEAR_0_WIDTH 6U +#define LPDDR4__SC_PHY_MANUAL_CLEAR_0__REG DENALI_PHY_43 +#define LPDDR4__SC_PHY_MANUAL_CLEAR_0__FLD LPDDR4__DENALI_PHY_43__SC_PHY_MANUAL_CLEAR_0 + +#define LPDDR4__DENALI_PHY_43__PHY_FIFO_PTR_OBS_0_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_43__PHY_FIFO_PTR_OBS_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_43__PHY_FIFO_PTR_OBS_0_WIDTH 8U +#define LPDDR4__PHY_FIFO_PTR_OBS_0__REG DENALI_PHY_43 +#define LPDDR4__PHY_FIFO_PTR_OBS_0__FLD LPDDR4__DENALI_PHY_43__PHY_FIFO_PTR_OBS_0 + +#define LPDDR4__DENALI_PHY_44_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_44_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_44__PHY_LPBK_RESULT_OBS_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_44__PHY_LPBK_RESULT_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_44__PHY_LPBK_RESULT_OBS_0_WIDTH 32U +#define LPDDR4__PHY_LPBK_RESULT_OBS_0__REG DENALI_PHY_44 +#define LPDDR4__PHY_LPBK_RESULT_OBS_0__FLD LPDDR4__DENALI_PHY_44__PHY_LPBK_RESULT_OBS_0 + +#define LPDDR4__DENALI_PHY_45_READ_MASK 0x07FFFFFFU +#define LPDDR4__DENALI_PHY_45_WRITE_MASK 0x07FFFFFFU +#define LPDDR4__DENALI_PHY_45__PHY_LPBK_ERROR_COUNT_OBS_0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_45__PHY_LPBK_ERROR_COUNT_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_45__PHY_LPBK_ERROR_COUNT_OBS_0_WIDTH 16U +#define LPDDR4__PHY_LPBK_ERROR_COUNT_OBS_0__REG DENALI_PHY_45 +#define LPDDR4__PHY_LPBK_ERROR_COUNT_OBS_0__FLD LPDDR4__DENALI_PHY_45__PHY_LPBK_ERROR_COUNT_OBS_0 + +#define LPDDR4__DENALI_PHY_45__PHY_MASTER_DLY_LOCK_OBS_0_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_45__PHY_MASTER_DLY_LOCK_OBS_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_45__PHY_MASTER_DLY_LOCK_OBS_0_WIDTH 11U +#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_0__REG DENALI_PHY_45 +#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_0__FLD LPDDR4__DENALI_PHY_45__PHY_MASTER_DLY_LOCK_OBS_0 + +#define LPDDR4__DENALI_PHY_46_READ_MASK 0xFFFF7F7FU +#define LPDDR4__DENALI_PHY_46_WRITE_MASK 0xFFFF7F7FU +#define LPDDR4__DENALI_PHY_46__PHY_RDDQ_SLV_DLY_ENC_OBS_0_MASK 0x0000007FU +#define LPDDR4__DENALI_PHY_46__PHY_RDDQ_SLV_DLY_ENC_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_46__PHY_RDDQ_SLV_DLY_ENC_OBS_0_WIDTH 7U +#define LPDDR4__PHY_RDDQ_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_46 +#define LPDDR4__PHY_RDDQ_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_46__PHY_RDDQ_SLV_DLY_ENC_OBS_0 + +#define LPDDR4__DENALI_PHY_46__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_0_MASK 0x00007F00U +#define LPDDR4__DENALI_PHY_46__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_46__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_0_WIDTH 7U +#define LPDDR4__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_46 +#define LPDDR4__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_46__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_0 + +#define LPDDR4__DENALI_PHY_46__PHY_MEAS_DLY_STEP_VALUE_0_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_46__PHY_MEAS_DLY_STEP_VALUE_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_46__PHY_MEAS_DLY_STEP_VALUE_0_WIDTH 8U +#define LPDDR4__PHY_MEAS_DLY_STEP_VALUE_0__REG DENALI_PHY_46 +#define LPDDR4__PHY_MEAS_DLY_STEP_VALUE_0__FLD LPDDR4__DENALI_PHY_46__PHY_MEAS_DLY_STEP_VALUE_0 + +#define LPDDR4__DENALI_PHY_46__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_0_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_46__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_46__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_0_WIDTH 8U +#define LPDDR4__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_46 +#define LPDDR4__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_46__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_0 + +#define LPDDR4__DENALI_PHY_47_READ_MASK 0x7F07FFFFU +#define LPDDR4__DENALI_PHY_47_WRITE_MASK 0x7F07FFFFU +#define LPDDR4__DENALI_PHY_47__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_0_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_47__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_47__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_0_WIDTH 8U +#define LPDDR4__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_47 +#define LPDDR4__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_47__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_0 + +#define LPDDR4__DENALI_PHY_47__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_0_MASK 0x0007FF00U +#define LPDDR4__DENALI_PHY_47__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_47__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_0_WIDTH 11U +#define LPDDR4__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_47 +#define LPDDR4__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_47__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_0 + +#define LPDDR4__DENALI_PHY_47__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_0_MASK 0x7F000000U +#define LPDDR4__DENALI_PHY_47__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_47__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_0_WIDTH 7U +#define LPDDR4__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_47 +#define LPDDR4__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_47__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_0 + +#define LPDDR4__DENALI_PHY_48_READ_MASK 0x0007FFFFU +#define LPDDR4__DENALI_PHY_48_WRITE_MASK 0x0007FFFFU +#define LPDDR4__DENALI_PHY_48__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_0_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_48__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_48__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_0_WIDTH 8U +#define LPDDR4__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_48 +#define LPDDR4__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_48__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_0 + +#define LPDDR4__DENALI_PHY_48__PHY_WR_ADDER_SLV_DLY_ENC_OBS_0_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_48__PHY_WR_ADDER_SLV_DLY_ENC_OBS_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_48__PHY_WR_ADDER_SLV_DLY_ENC_OBS_0_WIDTH 8U +#define LPDDR4__PHY_WR_ADDER_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_48 +#define LPDDR4__PHY_WR_ADDER_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_48__PHY_WR_ADDER_SLV_DLY_ENC_OBS_0 + +#define LPDDR4__DENALI_PHY_48__PHY_WR_SHIFT_OBS_0_MASK 0x00070000U +#define LPDDR4__DENALI_PHY_48__PHY_WR_SHIFT_OBS_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_48__PHY_WR_SHIFT_OBS_0_WIDTH 3U +#define LPDDR4__PHY_WR_SHIFT_OBS_0__REG DENALI_PHY_48 +#define LPDDR4__PHY_WR_SHIFT_OBS_0__FLD LPDDR4__DENALI_PHY_48__PHY_WR_SHIFT_OBS_0 + +#define LPDDR4__DENALI_PHY_49_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_49_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_49__PHY_WRLVL_HARD0_DELAY_OBS_0_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_49__PHY_WRLVL_HARD0_DELAY_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_49__PHY_WRLVL_HARD0_DELAY_OBS_0_WIDTH 10U +#define LPDDR4__PHY_WRLVL_HARD0_DELAY_OBS_0__REG DENALI_PHY_49 +#define LPDDR4__PHY_WRLVL_HARD0_DELAY_OBS_0__FLD LPDDR4__DENALI_PHY_49__PHY_WRLVL_HARD0_DELAY_OBS_0 + +#define LPDDR4__DENALI_PHY_49__PHY_WRLVL_HARD1_DELAY_OBS_0_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_49__PHY_WRLVL_HARD1_DELAY_OBS_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_49__PHY_WRLVL_HARD1_DELAY_OBS_0_WIDTH 10U +#define LPDDR4__PHY_WRLVL_HARD1_DELAY_OBS_0__REG DENALI_PHY_49 +#define LPDDR4__PHY_WRLVL_HARD1_DELAY_OBS_0__FLD LPDDR4__DENALI_PHY_49__PHY_WRLVL_HARD1_DELAY_OBS_0 + +#define LPDDR4__DENALI_PHY_50_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PHY_50_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PHY_50__PHY_WRLVL_STATUS_OBS_0_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PHY_50__PHY_WRLVL_STATUS_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_50__PHY_WRLVL_STATUS_OBS_0_WIDTH 17U +#define LPDDR4__PHY_WRLVL_STATUS_OBS_0__REG DENALI_PHY_50 +#define LPDDR4__PHY_WRLVL_STATUS_OBS_0__FLD LPDDR4__DENALI_PHY_50__PHY_WRLVL_STATUS_OBS_0 + +#define LPDDR4__DENALI_PHY_51_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_51_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_51__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_0_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_51__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_51__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_0_WIDTH 10U +#define LPDDR4__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_51 +#define LPDDR4__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_51__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_0 + +#define LPDDR4__DENALI_PHY_51__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_0_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_51__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_51__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_0_WIDTH 10U +#define LPDDR4__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_51 +#define LPDDR4__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_51__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_0 + +#define LPDDR4__DENALI_PHY_52_READ_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_52_WRITE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_52__PHY_WRLVL_ERROR_OBS_0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_52__PHY_WRLVL_ERROR_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_52__PHY_WRLVL_ERROR_OBS_0_WIDTH 16U +#define LPDDR4__PHY_WRLVL_ERROR_OBS_0__REG DENALI_PHY_52 +#define LPDDR4__PHY_WRLVL_ERROR_OBS_0__FLD LPDDR4__DENALI_PHY_52__PHY_WRLVL_ERROR_OBS_0 + +#define LPDDR4__DENALI_PHY_52__PHY_GTLVL_HARD0_DELAY_OBS_0_MASK 0x3FFF0000U +#define LPDDR4__DENALI_PHY_52__PHY_GTLVL_HARD0_DELAY_OBS_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_52__PHY_GTLVL_HARD0_DELAY_OBS_0_WIDTH 14U +#define LPDDR4__PHY_GTLVL_HARD0_DELAY_OBS_0__REG DENALI_PHY_52 +#define LPDDR4__PHY_GTLVL_HARD0_DELAY_OBS_0__FLD LPDDR4__DENALI_PHY_52__PHY_GTLVL_HARD0_DELAY_OBS_0 + +#define LPDDR4__DENALI_PHY_53_READ_MASK 0x00003FFFU +#define LPDDR4__DENALI_PHY_53_WRITE_MASK 0x00003FFFU +#define LPDDR4__DENALI_PHY_53__PHY_GTLVL_HARD1_DELAY_OBS_0_MASK 0x00003FFFU +#define LPDDR4__DENALI_PHY_53__PHY_GTLVL_HARD1_DELAY_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_53__PHY_GTLVL_HARD1_DELAY_OBS_0_WIDTH 14U +#define LPDDR4__PHY_GTLVL_HARD1_DELAY_OBS_0__REG DENALI_PHY_53 +#define LPDDR4__PHY_GTLVL_HARD1_DELAY_OBS_0__FLD LPDDR4__DENALI_PHY_53__PHY_GTLVL_HARD1_DELAY_OBS_0 + +#define LPDDR4__DENALI_PHY_54_READ_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_54_WRITE_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_54__PHY_GTLVL_STATUS_OBS_0_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_54__PHY_GTLVL_STATUS_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_54__PHY_GTLVL_STATUS_OBS_0_WIDTH 18U +#define LPDDR4__PHY_GTLVL_STATUS_OBS_0__REG DENALI_PHY_54 +#define LPDDR4__PHY_GTLVL_STATUS_OBS_0__FLD LPDDR4__DENALI_PHY_54__PHY_GTLVL_STATUS_OBS_0 + +#define LPDDR4__DENALI_PHY_55_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_55_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_55__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_0_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_55__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_55__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_0_WIDTH 10U +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_0__REG DENALI_PHY_55 +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_0__FLD LPDDR4__DENALI_PHY_55__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_0 + +#define LPDDR4__DENALI_PHY_55__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_0_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_55__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_55__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_0_WIDTH 10U +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_0__REG DENALI_PHY_55 +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_0__FLD LPDDR4__DENALI_PHY_55__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_0 + +#define LPDDR4__DENALI_PHY_56_READ_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_56_WRITE_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_56__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_0_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_56__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_56__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_0_WIDTH 2U +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_0__REG DENALI_PHY_56 +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_0__FLD LPDDR4__DENALI_PHY_56__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_0 + +#define LPDDR4__DENALI_PHY_57_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_57_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_57__PHY_RDLVL_STATUS_OBS_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_57__PHY_RDLVL_STATUS_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_57__PHY_RDLVL_STATUS_OBS_0_WIDTH 32U +#define LPDDR4__PHY_RDLVL_STATUS_OBS_0__REG DENALI_PHY_57 +#define LPDDR4__PHY_RDLVL_STATUS_OBS_0__FLD LPDDR4__DENALI_PHY_57__PHY_RDLVL_STATUS_OBS_0 + +#define LPDDR4__DENALI_PHY_58_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_58_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_58__PHY_RDLVL_PERIODIC_OBS_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_58__PHY_RDLVL_PERIODIC_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_58__PHY_RDLVL_PERIODIC_OBS_0_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PERIODIC_OBS_0__REG DENALI_PHY_58 +#define LPDDR4__PHY_RDLVL_PERIODIC_OBS_0__FLD LPDDR4__DENALI_PHY_58__PHY_RDLVL_PERIODIC_OBS_0 + +#define LPDDR4__DENALI_PHY_59_READ_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_59_WRITE_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_59__PHY_WDQLVL_DQDM_LE_DLY_OBS_0_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_59__PHY_WDQLVL_DQDM_LE_DLY_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_59__PHY_WDQLVL_DQDM_LE_DLY_OBS_0_WIDTH 11U +#define LPDDR4__PHY_WDQLVL_DQDM_LE_DLY_OBS_0__REG DENALI_PHY_59 +#define LPDDR4__PHY_WDQLVL_DQDM_LE_DLY_OBS_0__FLD LPDDR4__DENALI_PHY_59__PHY_WDQLVL_DQDM_LE_DLY_OBS_0 + +#define LPDDR4__DENALI_PHY_59__PHY_WDQLVL_DQDM_TE_DLY_OBS_0_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_59__PHY_WDQLVL_DQDM_TE_DLY_OBS_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_59__PHY_WDQLVL_DQDM_TE_DLY_OBS_0_WIDTH 11U +#define LPDDR4__PHY_WDQLVL_DQDM_TE_DLY_OBS_0__REG DENALI_PHY_59 +#define LPDDR4__PHY_WDQLVL_DQDM_TE_DLY_OBS_0__FLD LPDDR4__DENALI_PHY_59__PHY_WDQLVL_DQDM_TE_DLY_OBS_0 + +#define LPDDR4__DENALI_PHY_60_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_60_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_60__PHY_WDQLVL_STATUS_OBS_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_60__PHY_WDQLVL_STATUS_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_60__PHY_WDQLVL_STATUS_OBS_0_WIDTH 32U +#define LPDDR4__PHY_WDQLVL_STATUS_OBS_0__REG DENALI_PHY_60 +#define LPDDR4__PHY_WDQLVL_STATUS_OBS_0__FLD LPDDR4__DENALI_PHY_60__PHY_WDQLVL_STATUS_OBS_0 + +#define LPDDR4__DENALI_PHY_61_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_61_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_61__PHY_WDQLVL_PERIODIC_OBS_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_61__PHY_WDQLVL_PERIODIC_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_61__PHY_WDQLVL_PERIODIC_OBS_0_WIDTH 32U +#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_0__REG DENALI_PHY_61 +#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_0__FLD LPDDR4__DENALI_PHY_61__PHY_WDQLVL_PERIODIC_OBS_0 + +#define LPDDR4__DENALI_PHY_62_READ_MASK 0x7FFFFFFFU +#define LPDDR4__DENALI_PHY_62_WRITE_MASK 0x7FFFFFFFU +#define LPDDR4__DENALI_PHY_62__PHY_DDL_MODE_0_MASK 0x7FFFFFFFU +#define LPDDR4__DENALI_PHY_62__PHY_DDL_MODE_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_62__PHY_DDL_MODE_0_WIDTH 31U +#define LPDDR4__PHY_DDL_MODE_0__REG DENALI_PHY_62 +#define LPDDR4__PHY_DDL_MODE_0__FLD LPDDR4__DENALI_PHY_62__PHY_DDL_MODE_0 + +#define LPDDR4__DENALI_PHY_63_READ_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_63_WRITE_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_63__PHY_DDL_MASK_0_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_63__PHY_DDL_MASK_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_63__PHY_DDL_MASK_0_WIDTH 6U +#define LPDDR4__PHY_DDL_MASK_0__REG DENALI_PHY_63 +#define LPDDR4__PHY_DDL_MASK_0__FLD LPDDR4__DENALI_PHY_63__PHY_DDL_MASK_0 + +#define LPDDR4__DENALI_PHY_64_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_64_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_64__PHY_DDL_TEST_OBS_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_64__PHY_DDL_TEST_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_64__PHY_DDL_TEST_OBS_0_WIDTH 32U +#define LPDDR4__PHY_DDL_TEST_OBS_0__REG DENALI_PHY_64 +#define LPDDR4__PHY_DDL_TEST_OBS_0__FLD LPDDR4__DENALI_PHY_64__PHY_DDL_TEST_OBS_0 + +#define LPDDR4__DENALI_PHY_65_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_65_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_65__PHY_DDL_TEST_MSTR_DLY_OBS_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_65__PHY_DDL_TEST_MSTR_DLY_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_65__PHY_DDL_TEST_MSTR_DLY_OBS_0_WIDTH 32U +#define LPDDR4__PHY_DDL_TEST_MSTR_DLY_OBS_0__REG DENALI_PHY_65 +#define LPDDR4__PHY_DDL_TEST_MSTR_DLY_OBS_0__FLD LPDDR4__DENALI_PHY_65__PHY_DDL_TEST_MSTR_DLY_OBS_0 + +#define LPDDR4__DENALI_PHY_66_READ_MASK 0x010001FFU +#define LPDDR4__DENALI_PHY_66_WRITE_MASK 0x010001FFU +#define LPDDR4__DENALI_PHY_66__PHY_DDL_TRACK_UPD_THRESHOLD_0_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_66__PHY_DDL_TRACK_UPD_THRESHOLD_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_66__PHY_DDL_TRACK_UPD_THRESHOLD_0_WIDTH 8U +#define LPDDR4__PHY_DDL_TRACK_UPD_THRESHOLD_0__REG DENALI_PHY_66 +#define LPDDR4__PHY_DDL_TRACK_UPD_THRESHOLD_0__FLD LPDDR4__DENALI_PHY_66__PHY_DDL_TRACK_UPD_THRESHOLD_0 + +#define LPDDR4__DENALI_PHY_66__PHY_LP4_WDQS_OE_EXTEND_0_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_66__PHY_LP4_WDQS_OE_EXTEND_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_66__PHY_LP4_WDQS_OE_EXTEND_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_66__PHY_LP4_WDQS_OE_EXTEND_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_66__PHY_LP4_WDQS_OE_EXTEND_0_WOSET 0U +#define LPDDR4__PHY_LP4_WDQS_OE_EXTEND_0__REG DENALI_PHY_66 +#define LPDDR4__PHY_LP4_WDQS_OE_EXTEND_0__FLD LPDDR4__DENALI_PHY_66__PHY_LP4_WDQS_OE_EXTEND_0 + +#define LPDDR4__DENALI_PHY_66__SC_PHY_RX_CAL_START_0_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_66__SC_PHY_RX_CAL_START_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_66__SC_PHY_RX_CAL_START_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_66__SC_PHY_RX_CAL_START_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_66__SC_PHY_RX_CAL_START_0_WOSET 0U +#define LPDDR4__SC_PHY_RX_CAL_START_0__REG DENALI_PHY_66 +#define LPDDR4__SC_PHY_RX_CAL_START_0__FLD LPDDR4__DENALI_PHY_66__SC_PHY_RX_CAL_START_0 + +#define LPDDR4__DENALI_PHY_66__PHY_RX_CAL_OVERRIDE_0_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_66__PHY_RX_CAL_OVERRIDE_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_66__PHY_RX_CAL_OVERRIDE_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_66__PHY_RX_CAL_OVERRIDE_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_66__PHY_RX_CAL_OVERRIDE_0_WOSET 0U +#define LPDDR4__PHY_RX_CAL_OVERRIDE_0__REG DENALI_PHY_66 +#define LPDDR4__PHY_RX_CAL_OVERRIDE_0__FLD LPDDR4__DENALI_PHY_66__PHY_RX_CAL_OVERRIDE_0 + +#define LPDDR4__DENALI_PHY_67_READ_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_67_WRITE_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_67__PHY_RX_CAL_SAMPLE_WAIT_0_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_67__PHY_RX_CAL_SAMPLE_WAIT_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_67__PHY_RX_CAL_SAMPLE_WAIT_0_WIDTH 8U +#define LPDDR4__PHY_RX_CAL_SAMPLE_WAIT_0__REG DENALI_PHY_67 +#define LPDDR4__PHY_RX_CAL_SAMPLE_WAIT_0__FLD LPDDR4__DENALI_PHY_67__PHY_RX_CAL_SAMPLE_WAIT_0 + +#define LPDDR4__DENALI_PHY_67__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_0_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_67__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_67__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_67__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_67__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_0_WOSET 0U +#define LPDDR4__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_0__REG DENALI_PHY_67 +#define LPDDR4__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_0__FLD LPDDR4__DENALI_PHY_67__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_0 + +#define LPDDR4__DENALI_PHY_67__PHY_RX_CAL_DQ0_0_MASK 0x01FF0000U +#define LPDDR4__DENALI_PHY_67__PHY_RX_CAL_DQ0_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_67__PHY_RX_CAL_DQ0_0_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQ0_0__REG DENALI_PHY_67 +#define LPDDR4__PHY_RX_CAL_DQ0_0__FLD LPDDR4__DENALI_PHY_67__PHY_RX_CAL_DQ0_0 + +#define LPDDR4__DENALI_PHY_68_READ_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_68_WRITE_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_68__PHY_RX_CAL_DQ1_0_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_68__PHY_RX_CAL_DQ1_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_68__PHY_RX_CAL_DQ1_0_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQ1_0__REG DENALI_PHY_68 +#define LPDDR4__PHY_RX_CAL_DQ1_0__FLD LPDDR4__DENALI_PHY_68__PHY_RX_CAL_DQ1_0 + +#define LPDDR4__DENALI_PHY_68__PHY_RX_CAL_DQ2_0_MASK 0x01FF0000U +#define LPDDR4__DENALI_PHY_68__PHY_RX_CAL_DQ2_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_68__PHY_RX_CAL_DQ2_0_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQ2_0__REG DENALI_PHY_68 +#define LPDDR4__PHY_RX_CAL_DQ2_0__FLD LPDDR4__DENALI_PHY_68__PHY_RX_CAL_DQ2_0 + +#define LPDDR4__DENALI_PHY_69_READ_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_69_WRITE_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_69__PHY_RX_CAL_DQ3_0_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_69__PHY_RX_CAL_DQ3_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_69__PHY_RX_CAL_DQ3_0_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQ3_0__REG DENALI_PHY_69 +#define LPDDR4__PHY_RX_CAL_DQ3_0__FLD LPDDR4__DENALI_PHY_69__PHY_RX_CAL_DQ3_0 + +#define LPDDR4__DENALI_PHY_69__PHY_RX_CAL_DQ4_0_MASK 0x01FF0000U +#define LPDDR4__DENALI_PHY_69__PHY_RX_CAL_DQ4_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_69__PHY_RX_CAL_DQ4_0_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQ4_0__REG DENALI_PHY_69 +#define LPDDR4__PHY_RX_CAL_DQ4_0__FLD LPDDR4__DENALI_PHY_69__PHY_RX_CAL_DQ4_0 + +#define LPDDR4__DENALI_PHY_70_READ_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_70_WRITE_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_70__PHY_RX_CAL_DQ5_0_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_70__PHY_RX_CAL_DQ5_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_70__PHY_RX_CAL_DQ5_0_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQ5_0__REG DENALI_PHY_70 +#define LPDDR4__PHY_RX_CAL_DQ5_0__FLD LPDDR4__DENALI_PHY_70__PHY_RX_CAL_DQ5_0 + +#define LPDDR4__DENALI_PHY_70__PHY_RX_CAL_DQ6_0_MASK 0x01FF0000U +#define LPDDR4__DENALI_PHY_70__PHY_RX_CAL_DQ6_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_70__PHY_RX_CAL_DQ6_0_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQ6_0__REG DENALI_PHY_70 +#define LPDDR4__PHY_RX_CAL_DQ6_0__FLD LPDDR4__DENALI_PHY_70__PHY_RX_CAL_DQ6_0 + +#define LPDDR4__DENALI_PHY_71_READ_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_71_WRITE_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_71__PHY_RX_CAL_DQ7_0_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_71__PHY_RX_CAL_DQ7_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_71__PHY_RX_CAL_DQ7_0_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQ7_0__REG DENALI_PHY_71 +#define LPDDR4__PHY_RX_CAL_DQ7_0__FLD LPDDR4__DENALI_PHY_71__PHY_RX_CAL_DQ7_0 + +#define LPDDR4__DENALI_PHY_72_READ_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_72_WRITE_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_72__PHY_RX_CAL_DM_0_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_72__PHY_RX_CAL_DM_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_72__PHY_RX_CAL_DM_0_WIDTH 18U +#define LPDDR4__PHY_RX_CAL_DM_0__REG DENALI_PHY_72 +#define LPDDR4__PHY_RX_CAL_DM_0__FLD LPDDR4__DENALI_PHY_72__PHY_RX_CAL_DM_0 + +#define LPDDR4__DENALI_PHY_73_READ_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_73_WRITE_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_73__PHY_RX_CAL_DQS_0_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_73__PHY_RX_CAL_DQS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_73__PHY_RX_CAL_DQS_0_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQS_0__REG DENALI_PHY_73 +#define LPDDR4__PHY_RX_CAL_DQS_0__FLD LPDDR4__DENALI_PHY_73__PHY_RX_CAL_DQS_0 + +#define LPDDR4__DENALI_PHY_73__PHY_RX_CAL_FDBK_0_MASK 0x01FF0000U +#define LPDDR4__DENALI_PHY_73__PHY_RX_CAL_FDBK_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_73__PHY_RX_CAL_FDBK_0_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_FDBK_0__REG DENALI_PHY_73 +#define LPDDR4__PHY_RX_CAL_FDBK_0__FLD LPDDR4__DENALI_PHY_73__PHY_RX_CAL_FDBK_0 + +#define LPDDR4__DENALI_PHY_74_READ_MASK 0x01FF07FFU +#define LPDDR4__DENALI_PHY_74_WRITE_MASK 0x01FF07FFU +#define LPDDR4__DENALI_PHY_74__PHY_RX_CAL_OBS_0_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_74__PHY_RX_CAL_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_74__PHY_RX_CAL_OBS_0_WIDTH 11U +#define LPDDR4__PHY_RX_CAL_OBS_0__REG DENALI_PHY_74 +#define LPDDR4__PHY_RX_CAL_OBS_0__FLD LPDDR4__DENALI_PHY_74__PHY_RX_CAL_OBS_0 + +#define LPDDR4__DENALI_PHY_74__PHY_RX_CAL_LOCK_OBS_0_MASK 0x01FF0000U +#define LPDDR4__DENALI_PHY_74__PHY_RX_CAL_LOCK_OBS_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_74__PHY_RX_CAL_LOCK_OBS_0_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_LOCK_OBS_0__REG DENALI_PHY_74 +#define LPDDR4__PHY_RX_CAL_LOCK_OBS_0__FLD LPDDR4__DENALI_PHY_74__PHY_RX_CAL_LOCK_OBS_0 + +#define LPDDR4__DENALI_PHY_75_READ_MASK 0x017F7F01U +#define LPDDR4__DENALI_PHY_75_WRITE_MASK 0x017F7F01U +#define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_DISABLE_0_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_DISABLE_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_DISABLE_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_DISABLE_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_DISABLE_0_WOSET 0U +#define LPDDR4__PHY_RX_CAL_DISABLE_0__REG DENALI_PHY_75 +#define LPDDR4__PHY_RX_CAL_DISABLE_0__FLD LPDDR4__DENALI_PHY_75__PHY_RX_CAL_DISABLE_0 + +#define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_SE_ADJUST_0_MASK 0x00007F00U +#define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_SE_ADJUST_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_SE_ADJUST_0_WIDTH 7U +#define LPDDR4__PHY_RX_CAL_SE_ADJUST_0__REG DENALI_PHY_75 +#define LPDDR4__PHY_RX_CAL_SE_ADJUST_0__FLD LPDDR4__DENALI_PHY_75__PHY_RX_CAL_SE_ADJUST_0 + +#define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_DIFF_ADJUST_0_MASK 0x007F0000U +#define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_DIFF_ADJUST_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_DIFF_ADJUST_0_WIDTH 7U +#define LPDDR4__PHY_RX_CAL_DIFF_ADJUST_0__REG DENALI_PHY_75 +#define LPDDR4__PHY_RX_CAL_DIFF_ADJUST_0__FLD LPDDR4__DENALI_PHY_75__PHY_RX_CAL_DIFF_ADJUST_0 + +#define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_COMP_VAL_0_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_COMP_VAL_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_COMP_VAL_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_COMP_VAL_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_COMP_VAL_0_WOSET 0U +#define LPDDR4__PHY_RX_CAL_COMP_VAL_0__REG DENALI_PHY_75 +#define LPDDR4__PHY_RX_CAL_COMP_VAL_0__FLD LPDDR4__DENALI_PHY_75__PHY_RX_CAL_COMP_VAL_0 + +#define LPDDR4__DENALI_PHY_76_READ_MASK 0x07FF0FFFU +#define LPDDR4__DENALI_PHY_76_WRITE_MASK 0x07FF0FFFU +#define LPDDR4__DENALI_PHY_76__PHY_RX_CAL_INDEX_MASK_0_MASK 0x00000FFFU +#define LPDDR4__DENALI_PHY_76__PHY_RX_CAL_INDEX_MASK_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_76__PHY_RX_CAL_INDEX_MASK_0_WIDTH 12U +#define LPDDR4__PHY_RX_CAL_INDEX_MASK_0__REG DENALI_PHY_76 +#define LPDDR4__PHY_RX_CAL_INDEX_MASK_0__FLD LPDDR4__DENALI_PHY_76__PHY_RX_CAL_INDEX_MASK_0 + +#define LPDDR4__DENALI_PHY_76__PHY_PAD_RX_BIAS_EN_0_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_76__PHY_PAD_RX_BIAS_EN_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_76__PHY_PAD_RX_BIAS_EN_0_WIDTH 11U +#define LPDDR4__PHY_PAD_RX_BIAS_EN_0__REG DENALI_PHY_76 +#define LPDDR4__PHY_PAD_RX_BIAS_EN_0__FLD LPDDR4__DENALI_PHY_76__PHY_PAD_RX_BIAS_EN_0 + +#define LPDDR4__DENALI_PHY_77_READ_MASK 0x03FFFF1FU +#define LPDDR4__DENALI_PHY_77_WRITE_MASK 0x03FFFF1FU +#define LPDDR4__DENALI_PHY_77__PHY_STATIC_TOG_DISABLE_0_MASK 0x0000001FU +#define LPDDR4__DENALI_PHY_77__PHY_STATIC_TOG_DISABLE_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_77__PHY_STATIC_TOG_DISABLE_0_WIDTH 5U +#define LPDDR4__PHY_STATIC_TOG_DISABLE_0__REG DENALI_PHY_77 +#define LPDDR4__PHY_STATIC_TOG_DISABLE_0__FLD LPDDR4__DENALI_PHY_77__PHY_STATIC_TOG_DISABLE_0 + +#define LPDDR4__DENALI_PHY_77__PHY_DATA_DC_CAL_SAMPLE_WAIT_0_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_77__PHY_DATA_DC_CAL_SAMPLE_WAIT_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_77__PHY_DATA_DC_CAL_SAMPLE_WAIT_0_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_CAL_SAMPLE_WAIT_0__REG DENALI_PHY_77 +#define LPDDR4__PHY_DATA_DC_CAL_SAMPLE_WAIT_0__FLD LPDDR4__DENALI_PHY_77__PHY_DATA_DC_CAL_SAMPLE_WAIT_0 + +#define LPDDR4__DENALI_PHY_77__PHY_DATA_DC_CAL_TIMEOUT_0_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_77__PHY_DATA_DC_CAL_TIMEOUT_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_77__PHY_DATA_DC_CAL_TIMEOUT_0_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_CAL_TIMEOUT_0__REG DENALI_PHY_77 +#define LPDDR4__PHY_DATA_DC_CAL_TIMEOUT_0__FLD LPDDR4__DENALI_PHY_77__PHY_DATA_DC_CAL_TIMEOUT_0 + +#define LPDDR4__DENALI_PHY_77__PHY_DATA_DC_WEIGHT_0_MASK 0x03000000U +#define LPDDR4__DENALI_PHY_77__PHY_DATA_DC_WEIGHT_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_77__PHY_DATA_DC_WEIGHT_0_WIDTH 2U +#define LPDDR4__PHY_DATA_DC_WEIGHT_0__REG DENALI_PHY_77 +#define LPDDR4__PHY_DATA_DC_WEIGHT_0__FLD LPDDR4__DENALI_PHY_77__PHY_DATA_DC_WEIGHT_0 + +#define LPDDR4__DENALI_PHY_78_READ_MASK 0x01FFFF3FU +#define LPDDR4__DENALI_PHY_78_WRITE_MASK 0x01FFFF3FU +#define LPDDR4__DENALI_PHY_78__PHY_DATA_DC_ADJUST_START_0_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_78__PHY_DATA_DC_ADJUST_START_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_78__PHY_DATA_DC_ADJUST_START_0_WIDTH 6U +#define LPDDR4__PHY_DATA_DC_ADJUST_START_0__REG DENALI_PHY_78 +#define LPDDR4__PHY_DATA_DC_ADJUST_START_0__FLD LPDDR4__DENALI_PHY_78__PHY_DATA_DC_ADJUST_START_0 + +#define LPDDR4__DENALI_PHY_78__PHY_DATA_DC_ADJUST_SAMPLE_CNT_0_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_78__PHY_DATA_DC_ADJUST_SAMPLE_CNT_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_78__PHY_DATA_DC_ADJUST_SAMPLE_CNT_0_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_ADJUST_SAMPLE_CNT_0__REG DENALI_PHY_78 +#define LPDDR4__PHY_DATA_DC_ADJUST_SAMPLE_CNT_0__FLD LPDDR4__DENALI_PHY_78__PHY_DATA_DC_ADJUST_SAMPLE_CNT_0 + +#define LPDDR4__DENALI_PHY_78__PHY_DATA_DC_ADJUST_THRSHLD_0_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_78__PHY_DATA_DC_ADJUST_THRSHLD_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_78__PHY_DATA_DC_ADJUST_THRSHLD_0_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_ADJUST_THRSHLD_0__REG DENALI_PHY_78 +#define LPDDR4__PHY_DATA_DC_ADJUST_THRSHLD_0__FLD LPDDR4__DENALI_PHY_78__PHY_DATA_DC_ADJUST_THRSHLD_0 + +#define LPDDR4__DENALI_PHY_78__PHY_DATA_DC_ADJUST_DIRECT_0_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_78__PHY_DATA_DC_ADJUST_DIRECT_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_78__PHY_DATA_DC_ADJUST_DIRECT_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_78__PHY_DATA_DC_ADJUST_DIRECT_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_78__PHY_DATA_DC_ADJUST_DIRECT_0_WOSET 0U +#define LPDDR4__PHY_DATA_DC_ADJUST_DIRECT_0__REG DENALI_PHY_78 +#define LPDDR4__PHY_DATA_DC_ADJUST_DIRECT_0__FLD LPDDR4__DENALI_PHY_78__PHY_DATA_DC_ADJUST_DIRECT_0 + +#define LPDDR4__DENALI_PHY_79_READ_MASK 0x07030101U +#define LPDDR4__DENALI_PHY_79_WRITE_MASK 0x07030101U +#define LPDDR4__DENALI_PHY_79__PHY_DATA_DC_CAL_POLARITY_0_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_79__PHY_DATA_DC_CAL_POLARITY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_79__PHY_DATA_DC_CAL_POLARITY_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_79__PHY_DATA_DC_CAL_POLARITY_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_79__PHY_DATA_DC_CAL_POLARITY_0_WOSET 0U +#define LPDDR4__PHY_DATA_DC_CAL_POLARITY_0__REG DENALI_PHY_79 +#define LPDDR4__PHY_DATA_DC_CAL_POLARITY_0__FLD LPDDR4__DENALI_PHY_79__PHY_DATA_DC_CAL_POLARITY_0 + +#define LPDDR4__DENALI_PHY_79__PHY_DATA_DC_CAL_START_0_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_79__PHY_DATA_DC_CAL_START_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_79__PHY_DATA_DC_CAL_START_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_79__PHY_DATA_DC_CAL_START_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_79__PHY_DATA_DC_CAL_START_0_WOSET 0U +#define LPDDR4__PHY_DATA_DC_CAL_START_0__REG DENALI_PHY_79 +#define LPDDR4__PHY_DATA_DC_CAL_START_0__FLD LPDDR4__DENALI_PHY_79__PHY_DATA_DC_CAL_START_0 + +#define LPDDR4__DENALI_PHY_79__PHY_DATA_DC_SW_RANK_0_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_79__PHY_DATA_DC_SW_RANK_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_79__PHY_DATA_DC_SW_RANK_0_WIDTH 2U +#define LPDDR4__PHY_DATA_DC_SW_RANK_0__REG DENALI_PHY_79 +#define LPDDR4__PHY_DATA_DC_SW_RANK_0__FLD LPDDR4__DENALI_PHY_79__PHY_DATA_DC_SW_RANK_0 + +#define LPDDR4__DENALI_PHY_79__PHY_FDBK_PWR_CTRL_0_MASK 0x07000000U +#define LPDDR4__DENALI_PHY_79__PHY_FDBK_PWR_CTRL_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_79__PHY_FDBK_PWR_CTRL_0_WIDTH 3U +#define LPDDR4__PHY_FDBK_PWR_CTRL_0__REG DENALI_PHY_79 +#define LPDDR4__PHY_FDBK_PWR_CTRL_0__FLD LPDDR4__DENALI_PHY_79__PHY_FDBK_PWR_CTRL_0 + +#define LPDDR4__DENALI_PHY_80_READ_MASK 0x01010101U +#define LPDDR4__DENALI_PHY_80_WRITE_MASK 0x01010101U +#define LPDDR4__DENALI_PHY_80__PHY_SLV_DLY_CTRL_GATE_DISABLE_0_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_80__PHY_SLV_DLY_CTRL_GATE_DISABLE_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_80__PHY_SLV_DLY_CTRL_GATE_DISABLE_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_80__PHY_SLV_DLY_CTRL_GATE_DISABLE_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_80__PHY_SLV_DLY_CTRL_GATE_DISABLE_0_WOSET 0U +#define LPDDR4__PHY_SLV_DLY_CTRL_GATE_DISABLE_0__REG DENALI_PHY_80 +#define LPDDR4__PHY_SLV_DLY_CTRL_GATE_DISABLE_0__FLD LPDDR4__DENALI_PHY_80__PHY_SLV_DLY_CTRL_GATE_DISABLE_0 + +#define LPDDR4__DENALI_PHY_80__PHY_RDPATH_GATE_DISABLE_0_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_80__PHY_RDPATH_GATE_DISABLE_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_80__PHY_RDPATH_GATE_DISABLE_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_80__PHY_RDPATH_GATE_DISABLE_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_80__PHY_RDPATH_GATE_DISABLE_0_WOSET 0U +#define LPDDR4__PHY_RDPATH_GATE_DISABLE_0__REG DENALI_PHY_80 +#define LPDDR4__PHY_RDPATH_GATE_DISABLE_0__FLD LPDDR4__DENALI_PHY_80__PHY_RDPATH_GATE_DISABLE_0 + +#define LPDDR4__DENALI_PHY_80__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_0_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_80__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_80__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_80__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_80__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_0_WOSET 0U +#define LPDDR4__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_0__REG DENALI_PHY_80 +#define LPDDR4__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_0__FLD LPDDR4__DENALI_PHY_80__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_0 + +#define LPDDR4__DENALI_PHY_80__PHY_SLICE_PWR_RDC_DISABLE_0_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_80__PHY_SLICE_PWR_RDC_DISABLE_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_80__PHY_SLICE_PWR_RDC_DISABLE_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_80__PHY_SLICE_PWR_RDC_DISABLE_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_80__PHY_SLICE_PWR_RDC_DISABLE_0_WOSET 0U +#define LPDDR4__PHY_SLICE_PWR_RDC_DISABLE_0__REG DENALI_PHY_80 +#define LPDDR4__PHY_SLICE_PWR_RDC_DISABLE_0__FLD LPDDR4__DENALI_PHY_80__PHY_SLICE_PWR_RDC_DISABLE_0 + +#define LPDDR4__DENALI_PHY_81_READ_MASK 0x3FFF07FFU +#define LPDDR4__DENALI_PHY_81_WRITE_MASK 0x3FFF07FFU +#define LPDDR4__DENALI_PHY_81__PHY_PARITY_ERROR_REGIF_0_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_81__PHY_PARITY_ERROR_REGIF_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_81__PHY_PARITY_ERROR_REGIF_0_WIDTH 11U +#define LPDDR4__PHY_PARITY_ERROR_REGIF_0__REG DENALI_PHY_81 +#define LPDDR4__PHY_PARITY_ERROR_REGIF_0__FLD LPDDR4__DENALI_PHY_81__PHY_PARITY_ERROR_REGIF_0 + +#define LPDDR4__DENALI_PHY_81__PHY_DS_FSM_ERROR_INFO_0_MASK 0x3FFF0000U +#define LPDDR4__DENALI_PHY_81__PHY_DS_FSM_ERROR_INFO_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_81__PHY_DS_FSM_ERROR_INFO_0_WIDTH 14U +#define LPDDR4__PHY_DS_FSM_ERROR_INFO_0__REG DENALI_PHY_81 +#define LPDDR4__PHY_DS_FSM_ERROR_INFO_0__FLD LPDDR4__DENALI_PHY_81__PHY_DS_FSM_ERROR_INFO_0 + +#define LPDDR4__DENALI_PHY_82_READ_MASK 0x00003FFFU +#define LPDDR4__DENALI_PHY_82_WRITE_MASK 0x00003FFFU +#define LPDDR4__DENALI_PHY_82__PHY_DS_FSM_ERROR_INFO_MASK_0_MASK 0x00003FFFU +#define LPDDR4__DENALI_PHY_82__PHY_DS_FSM_ERROR_INFO_MASK_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_82__PHY_DS_FSM_ERROR_INFO_MASK_0_WIDTH 14U +#define LPDDR4__PHY_DS_FSM_ERROR_INFO_MASK_0__REG DENALI_PHY_82 +#define LPDDR4__PHY_DS_FSM_ERROR_INFO_MASK_0__FLD LPDDR4__DENALI_PHY_82__PHY_DS_FSM_ERROR_INFO_MASK_0 + +#define LPDDR4__DENALI_PHY_82__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_0_MASK 0x3FFF0000U +#define LPDDR4__DENALI_PHY_82__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_82__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_0_WIDTH 14U +#define LPDDR4__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_0__REG DENALI_PHY_82 +#define LPDDR4__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_0__FLD LPDDR4__DENALI_PHY_82__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_0 + +#define LPDDR4__DENALI_PHY_83_READ_MASK 0x00001F1FU +#define LPDDR4__DENALI_PHY_83_WRITE_MASK 0x00001F1FU +#define LPDDR4__DENALI_PHY_83__PHY_DS_TRAIN_CALIB_ERROR_INFO_0_MASK 0x0000001FU +#define LPDDR4__DENALI_PHY_83__PHY_DS_TRAIN_CALIB_ERROR_INFO_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_83__PHY_DS_TRAIN_CALIB_ERROR_INFO_0_WIDTH 5U +#define LPDDR4__PHY_DS_TRAIN_CALIB_ERROR_INFO_0__REG DENALI_PHY_83 +#define LPDDR4__PHY_DS_TRAIN_CALIB_ERROR_INFO_0__FLD LPDDR4__DENALI_PHY_83__PHY_DS_TRAIN_CALIB_ERROR_INFO_0 + +#define LPDDR4__DENALI_PHY_83__PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_0_MASK 0x00001F00U +#define LPDDR4__DENALI_PHY_83__PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_83__PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_0_WIDTH 5U +#define LPDDR4__PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_0__REG DENALI_PHY_83 +#define LPDDR4__PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_0__FLD LPDDR4__DENALI_PHY_83__PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_0 + +#define LPDDR4__DENALI_PHY_83__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_0_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_83__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_83__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_0_WIDTH 5U +#define LPDDR4__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_0__REG DENALI_PHY_83 +#define LPDDR4__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_0__FLD LPDDR4__DENALI_PHY_83__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_0 + +#define LPDDR4__DENALI_PHY_84_READ_MASK 0x07FFFF07U +#define LPDDR4__DENALI_PHY_84_WRITE_MASK 0x07FFFF07U +#define LPDDR4__DENALI_PHY_84__PHY_DQ_TSEL_ENABLE_0_MASK 0x00000007U +#define LPDDR4__DENALI_PHY_84__PHY_DQ_TSEL_ENABLE_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_84__PHY_DQ_TSEL_ENABLE_0_WIDTH 3U +#define LPDDR4__PHY_DQ_TSEL_ENABLE_0__REG DENALI_PHY_84 +#define LPDDR4__PHY_DQ_TSEL_ENABLE_0__FLD LPDDR4__DENALI_PHY_84__PHY_DQ_TSEL_ENABLE_0 + +#define LPDDR4__DENALI_PHY_84__PHY_DQ_TSEL_SELECT_0_MASK 0x00FFFF00U +#define LPDDR4__DENALI_PHY_84__PHY_DQ_TSEL_SELECT_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_84__PHY_DQ_TSEL_SELECT_0_WIDTH 16U +#define LPDDR4__PHY_DQ_TSEL_SELECT_0__REG DENALI_PHY_84 +#define LPDDR4__PHY_DQ_TSEL_SELECT_0__FLD LPDDR4__DENALI_PHY_84__PHY_DQ_TSEL_SELECT_0 + +#define LPDDR4__DENALI_PHY_84__PHY_DQS_TSEL_ENABLE_0_MASK 0x07000000U +#define LPDDR4__DENALI_PHY_84__PHY_DQS_TSEL_ENABLE_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_84__PHY_DQS_TSEL_ENABLE_0_WIDTH 3U +#define LPDDR4__PHY_DQS_TSEL_ENABLE_0__REG DENALI_PHY_84 +#define LPDDR4__PHY_DQS_TSEL_ENABLE_0__FLD LPDDR4__DENALI_PHY_84__PHY_DQS_TSEL_ENABLE_0 + +#define LPDDR4__DENALI_PHY_85_READ_MASK 0x7F03FFFFU +#define LPDDR4__DENALI_PHY_85_WRITE_MASK 0x7F03FFFFU +#define LPDDR4__DENALI_PHY_85__PHY_DQS_TSEL_SELECT_0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_85__PHY_DQS_TSEL_SELECT_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_85__PHY_DQS_TSEL_SELECT_0_WIDTH 16U +#define LPDDR4__PHY_DQS_TSEL_SELECT_0__REG DENALI_PHY_85 +#define LPDDR4__PHY_DQS_TSEL_SELECT_0__FLD LPDDR4__DENALI_PHY_85__PHY_DQS_TSEL_SELECT_0 + +#define LPDDR4__DENALI_PHY_85__PHY_TWO_CYC_PREAMBLE_0_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_85__PHY_TWO_CYC_PREAMBLE_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_85__PHY_TWO_CYC_PREAMBLE_0_WIDTH 2U +#define LPDDR4__PHY_TWO_CYC_PREAMBLE_0__REG DENALI_PHY_85 +#define LPDDR4__PHY_TWO_CYC_PREAMBLE_0__FLD LPDDR4__DENALI_PHY_85__PHY_TWO_CYC_PREAMBLE_0 + +#define LPDDR4__DENALI_PHY_85__PHY_VREF_INITIAL_START_POINT_0_MASK 0x7F000000U +#define LPDDR4__DENALI_PHY_85__PHY_VREF_INITIAL_START_POINT_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_85__PHY_VREF_INITIAL_START_POINT_0_WIDTH 7U +#define LPDDR4__PHY_VREF_INITIAL_START_POINT_0__REG DENALI_PHY_85 +#define LPDDR4__PHY_VREF_INITIAL_START_POINT_0__FLD LPDDR4__DENALI_PHY_85__PHY_VREF_INITIAL_START_POINT_0 + +#define LPDDR4__DENALI_PHY_86_READ_MASK 0xFF01037FU +#define LPDDR4__DENALI_PHY_86_WRITE_MASK 0xFF01037FU +#define LPDDR4__DENALI_PHY_86__PHY_VREF_INITIAL_STOP_POINT_0_MASK 0x0000007FU +#define LPDDR4__DENALI_PHY_86__PHY_VREF_INITIAL_STOP_POINT_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_86__PHY_VREF_INITIAL_STOP_POINT_0_WIDTH 7U +#define LPDDR4__PHY_VREF_INITIAL_STOP_POINT_0__REG DENALI_PHY_86 +#define LPDDR4__PHY_VREF_INITIAL_STOP_POINT_0__FLD LPDDR4__DENALI_PHY_86__PHY_VREF_INITIAL_STOP_POINT_0 + +#define LPDDR4__DENALI_PHY_86__PHY_VREF_TRAINING_CTRL_0_MASK 0x00000300U +#define LPDDR4__DENALI_PHY_86__PHY_VREF_TRAINING_CTRL_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_86__PHY_VREF_TRAINING_CTRL_0_WIDTH 2U +#define LPDDR4__PHY_VREF_TRAINING_CTRL_0__REG DENALI_PHY_86 +#define LPDDR4__PHY_VREF_TRAINING_CTRL_0__FLD LPDDR4__DENALI_PHY_86__PHY_VREF_TRAINING_CTRL_0 + +#define LPDDR4__DENALI_PHY_86__PHY_NTP_TRAIN_EN_0_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_86__PHY_NTP_TRAIN_EN_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_86__PHY_NTP_TRAIN_EN_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_86__PHY_NTP_TRAIN_EN_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_86__PHY_NTP_TRAIN_EN_0_WOSET 0U +#define LPDDR4__PHY_NTP_TRAIN_EN_0__REG DENALI_PHY_86 +#define LPDDR4__PHY_NTP_TRAIN_EN_0__FLD LPDDR4__DENALI_PHY_86__PHY_NTP_TRAIN_EN_0 + +#define LPDDR4__DENALI_PHY_86__PHY_NTP_WDQ_STEP_SIZE_0_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_86__PHY_NTP_WDQ_STEP_SIZE_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_86__PHY_NTP_WDQ_STEP_SIZE_0_WIDTH 8U +#define LPDDR4__PHY_NTP_WDQ_STEP_SIZE_0__REG DENALI_PHY_86 +#define LPDDR4__PHY_NTP_WDQ_STEP_SIZE_0__FLD LPDDR4__DENALI_PHY_86__PHY_NTP_WDQ_STEP_SIZE_0 + +#define LPDDR4__DENALI_PHY_87_READ_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_87_WRITE_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_87__PHY_NTP_WDQ_START_0_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_87__PHY_NTP_WDQ_START_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_87__PHY_NTP_WDQ_START_0_WIDTH 11U +#define LPDDR4__PHY_NTP_WDQ_START_0__REG DENALI_PHY_87 +#define LPDDR4__PHY_NTP_WDQ_START_0__FLD LPDDR4__DENALI_PHY_87__PHY_NTP_WDQ_START_0 + +#define LPDDR4__DENALI_PHY_87__PHY_NTP_WDQ_STOP_0_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_87__PHY_NTP_WDQ_STOP_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_87__PHY_NTP_WDQ_STOP_0_WIDTH 11U +#define LPDDR4__PHY_NTP_WDQ_STOP_0__REG DENALI_PHY_87 +#define LPDDR4__PHY_NTP_WDQ_STOP_0__FLD LPDDR4__DENALI_PHY_87__PHY_NTP_WDQ_STOP_0 + +#define LPDDR4__DENALI_PHY_88_READ_MASK 0x0103FFFFU +#define LPDDR4__DENALI_PHY_88_WRITE_MASK 0x0103FFFFU +#define LPDDR4__DENALI_PHY_88__PHY_NTP_WDQ_BIT_EN_0_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_88__PHY_NTP_WDQ_BIT_EN_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_88__PHY_NTP_WDQ_BIT_EN_0_WIDTH 8U +#define LPDDR4__PHY_NTP_WDQ_BIT_EN_0__REG DENALI_PHY_88 +#define LPDDR4__PHY_NTP_WDQ_BIT_EN_0__FLD LPDDR4__DENALI_PHY_88__PHY_NTP_WDQ_BIT_EN_0 + +#define LPDDR4__DENALI_PHY_88__PHY_WDQLVL_DVW_MIN_0_MASK 0x0003FF00U +#define LPDDR4__DENALI_PHY_88__PHY_WDQLVL_DVW_MIN_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_88__PHY_WDQLVL_DVW_MIN_0_WIDTH 10U +#define LPDDR4__PHY_WDQLVL_DVW_MIN_0__REG DENALI_PHY_88 +#define LPDDR4__PHY_WDQLVL_DVW_MIN_0__FLD LPDDR4__DENALI_PHY_88__PHY_WDQLVL_DVW_MIN_0 + +#define LPDDR4__DENALI_PHY_88__PHY_SW_WDQLVL_DVW_MIN_EN_0_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_88__PHY_SW_WDQLVL_DVW_MIN_EN_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_88__PHY_SW_WDQLVL_DVW_MIN_EN_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_88__PHY_SW_WDQLVL_DVW_MIN_EN_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_88__PHY_SW_WDQLVL_DVW_MIN_EN_0_WOSET 0U +#define LPDDR4__PHY_SW_WDQLVL_DVW_MIN_EN_0__REG DENALI_PHY_88 +#define LPDDR4__PHY_SW_WDQLVL_DVW_MIN_EN_0__FLD LPDDR4__DENALI_PHY_88__PHY_SW_WDQLVL_DVW_MIN_EN_0 + +#define LPDDR4__DENALI_PHY_89_READ_MASK 0x1F1F0F3FU +#define LPDDR4__DENALI_PHY_89_WRITE_MASK 0x1F1F0F3FU +#define LPDDR4__DENALI_PHY_89__PHY_WDQLVL_PER_START_OFFSET_0_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_89__PHY_WDQLVL_PER_START_OFFSET_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_89__PHY_WDQLVL_PER_START_OFFSET_0_WIDTH 6U +#define LPDDR4__PHY_WDQLVL_PER_START_OFFSET_0__REG DENALI_PHY_89 +#define LPDDR4__PHY_WDQLVL_PER_START_OFFSET_0__FLD LPDDR4__DENALI_PHY_89__PHY_WDQLVL_PER_START_OFFSET_0 + +#define LPDDR4__DENALI_PHY_89__PHY_FAST_LVL_EN_0_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_89__PHY_FAST_LVL_EN_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_89__PHY_FAST_LVL_EN_0_WIDTH 4U +#define LPDDR4__PHY_FAST_LVL_EN_0__REG DENALI_PHY_89 +#define LPDDR4__PHY_FAST_LVL_EN_0__FLD LPDDR4__DENALI_PHY_89__PHY_FAST_LVL_EN_0 + +#define LPDDR4__DENALI_PHY_89__PHY_PAD_TX_DCD_0_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_89__PHY_PAD_TX_DCD_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_89__PHY_PAD_TX_DCD_0_WIDTH 5U +#define LPDDR4__PHY_PAD_TX_DCD_0__REG DENALI_PHY_89 +#define LPDDR4__PHY_PAD_TX_DCD_0__FLD LPDDR4__DENALI_PHY_89__PHY_PAD_TX_DCD_0 + +#define LPDDR4__DENALI_PHY_89__PHY_PAD_RX_DCD_0_0_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_89__PHY_PAD_RX_DCD_0_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_89__PHY_PAD_RX_DCD_0_0_WIDTH 5U +#define LPDDR4__PHY_PAD_RX_DCD_0_0__REG DENALI_PHY_89 +#define LPDDR4__PHY_PAD_RX_DCD_0_0__FLD LPDDR4__DENALI_PHY_89__PHY_PAD_RX_DCD_0_0 + +#define LPDDR4__DENALI_PHY_90_READ_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_PHY_90_WRITE_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_PHY_90__PHY_PAD_RX_DCD_1_0_MASK 0x0000001FU +#define LPDDR4__DENALI_PHY_90__PHY_PAD_RX_DCD_1_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_90__PHY_PAD_RX_DCD_1_0_WIDTH 5U +#define LPDDR4__PHY_PAD_RX_DCD_1_0__REG DENALI_PHY_90 +#define LPDDR4__PHY_PAD_RX_DCD_1_0__FLD LPDDR4__DENALI_PHY_90__PHY_PAD_RX_DCD_1_0 + +#define LPDDR4__DENALI_PHY_90__PHY_PAD_RX_DCD_2_0_MASK 0x00001F00U +#define LPDDR4__DENALI_PHY_90__PHY_PAD_RX_DCD_2_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_90__PHY_PAD_RX_DCD_2_0_WIDTH 5U +#define LPDDR4__PHY_PAD_RX_DCD_2_0__REG DENALI_PHY_90 +#define LPDDR4__PHY_PAD_RX_DCD_2_0__FLD LPDDR4__DENALI_PHY_90__PHY_PAD_RX_DCD_2_0 + +#define LPDDR4__DENALI_PHY_90__PHY_PAD_RX_DCD_3_0_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_90__PHY_PAD_RX_DCD_3_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_90__PHY_PAD_RX_DCD_3_0_WIDTH 5U +#define LPDDR4__PHY_PAD_RX_DCD_3_0__REG DENALI_PHY_90 +#define LPDDR4__PHY_PAD_RX_DCD_3_0__FLD LPDDR4__DENALI_PHY_90__PHY_PAD_RX_DCD_3_0 + +#define LPDDR4__DENALI_PHY_90__PHY_PAD_RX_DCD_4_0_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_90__PHY_PAD_RX_DCD_4_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_90__PHY_PAD_RX_DCD_4_0_WIDTH 5U +#define LPDDR4__PHY_PAD_RX_DCD_4_0__REG DENALI_PHY_90 +#define LPDDR4__PHY_PAD_RX_DCD_4_0__FLD LPDDR4__DENALI_PHY_90__PHY_PAD_RX_DCD_4_0 + +#define LPDDR4__DENALI_PHY_91_READ_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_PHY_91_WRITE_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_PHY_91__PHY_PAD_RX_DCD_5_0_MASK 0x0000001FU +#define LPDDR4__DENALI_PHY_91__PHY_PAD_RX_DCD_5_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_91__PHY_PAD_RX_DCD_5_0_WIDTH 5U +#define LPDDR4__PHY_PAD_RX_DCD_5_0__REG DENALI_PHY_91 +#define LPDDR4__PHY_PAD_RX_DCD_5_0__FLD LPDDR4__DENALI_PHY_91__PHY_PAD_RX_DCD_5_0 + +#define LPDDR4__DENALI_PHY_91__PHY_PAD_RX_DCD_6_0_MASK 0x00001F00U +#define LPDDR4__DENALI_PHY_91__PHY_PAD_RX_DCD_6_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_91__PHY_PAD_RX_DCD_6_0_WIDTH 5U +#define LPDDR4__PHY_PAD_RX_DCD_6_0__REG DENALI_PHY_91 +#define LPDDR4__PHY_PAD_RX_DCD_6_0__FLD LPDDR4__DENALI_PHY_91__PHY_PAD_RX_DCD_6_0 + +#define LPDDR4__DENALI_PHY_91__PHY_PAD_RX_DCD_7_0_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_91__PHY_PAD_RX_DCD_7_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_91__PHY_PAD_RX_DCD_7_0_WIDTH 5U +#define LPDDR4__PHY_PAD_RX_DCD_7_0__REG DENALI_PHY_91 +#define LPDDR4__PHY_PAD_RX_DCD_7_0__FLD LPDDR4__DENALI_PHY_91__PHY_PAD_RX_DCD_7_0 + +#define LPDDR4__DENALI_PHY_91__PHY_PAD_DM_RX_DCD_0_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_91__PHY_PAD_DM_RX_DCD_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_91__PHY_PAD_DM_RX_DCD_0_WIDTH 5U +#define LPDDR4__PHY_PAD_DM_RX_DCD_0__REG DENALI_PHY_91 +#define LPDDR4__PHY_PAD_DM_RX_DCD_0__FLD LPDDR4__DENALI_PHY_91__PHY_PAD_DM_RX_DCD_0 + +#define LPDDR4__DENALI_PHY_92_READ_MASK 0x003F1F1FU +#define LPDDR4__DENALI_PHY_92_WRITE_MASK 0x003F1F1FU +#define LPDDR4__DENALI_PHY_92__PHY_PAD_DQS_RX_DCD_0_MASK 0x0000001FU +#define LPDDR4__DENALI_PHY_92__PHY_PAD_DQS_RX_DCD_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_92__PHY_PAD_DQS_RX_DCD_0_WIDTH 5U +#define LPDDR4__PHY_PAD_DQS_RX_DCD_0__REG DENALI_PHY_92 +#define LPDDR4__PHY_PAD_DQS_RX_DCD_0__FLD LPDDR4__DENALI_PHY_92__PHY_PAD_DQS_RX_DCD_0 + +#define LPDDR4__DENALI_PHY_92__PHY_PAD_FDBK_RX_DCD_0_MASK 0x00001F00U +#define LPDDR4__DENALI_PHY_92__PHY_PAD_FDBK_RX_DCD_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_92__PHY_PAD_FDBK_RX_DCD_0_WIDTH 5U +#define LPDDR4__PHY_PAD_FDBK_RX_DCD_0__REG DENALI_PHY_92 +#define LPDDR4__PHY_PAD_FDBK_RX_DCD_0__FLD LPDDR4__DENALI_PHY_92__PHY_PAD_FDBK_RX_DCD_0 + +#define LPDDR4__DENALI_PHY_92__PHY_PAD_DSLICE_IO_CFG_0_MASK 0x003F0000U +#define LPDDR4__DENALI_PHY_92__PHY_PAD_DSLICE_IO_CFG_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_92__PHY_PAD_DSLICE_IO_CFG_0_WIDTH 6U +#define LPDDR4__PHY_PAD_DSLICE_IO_CFG_0__REG DENALI_PHY_92 +#define LPDDR4__PHY_PAD_DSLICE_IO_CFG_0__FLD LPDDR4__DENALI_PHY_92__PHY_PAD_DSLICE_IO_CFG_0 + +#define LPDDR4__DENALI_PHY_93_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_93_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_93__PHY_RDDQ0_SLAVE_DELAY_0_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_93__PHY_RDDQ0_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_93__PHY_RDDQ0_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDQ0_SLAVE_DELAY_0__REG DENALI_PHY_93 +#define LPDDR4__PHY_RDDQ0_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_93__PHY_RDDQ0_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_93__PHY_RDDQ1_SLAVE_DELAY_0_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_93__PHY_RDDQ1_SLAVE_DELAY_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_93__PHY_RDDQ1_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDQ1_SLAVE_DELAY_0__REG DENALI_PHY_93 +#define LPDDR4__PHY_RDDQ1_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_93__PHY_RDDQ1_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_94_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_94_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_94__PHY_RDDQ2_SLAVE_DELAY_0_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_94__PHY_RDDQ2_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_94__PHY_RDDQ2_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDQ2_SLAVE_DELAY_0__REG DENALI_PHY_94 +#define LPDDR4__PHY_RDDQ2_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_94__PHY_RDDQ2_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_94__PHY_RDDQ3_SLAVE_DELAY_0_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_94__PHY_RDDQ3_SLAVE_DELAY_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_94__PHY_RDDQ3_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDQ3_SLAVE_DELAY_0__REG DENALI_PHY_94 +#define LPDDR4__PHY_RDDQ3_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_94__PHY_RDDQ3_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_95_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_95_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_95__PHY_RDDQ4_SLAVE_DELAY_0_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_95__PHY_RDDQ4_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_95__PHY_RDDQ4_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDQ4_SLAVE_DELAY_0__REG DENALI_PHY_95 +#define LPDDR4__PHY_RDDQ4_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_95__PHY_RDDQ4_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_95__PHY_RDDQ5_SLAVE_DELAY_0_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_95__PHY_RDDQ5_SLAVE_DELAY_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_95__PHY_RDDQ5_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDQ5_SLAVE_DELAY_0__REG DENALI_PHY_95 +#define LPDDR4__PHY_RDDQ5_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_95__PHY_RDDQ5_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_96_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_96_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_96__PHY_RDDQ6_SLAVE_DELAY_0_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_96__PHY_RDDQ6_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_96__PHY_RDDQ6_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDQ6_SLAVE_DELAY_0__REG DENALI_PHY_96 +#define LPDDR4__PHY_RDDQ6_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_96__PHY_RDDQ6_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_96__PHY_RDDQ7_SLAVE_DELAY_0_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_96__PHY_RDDQ7_SLAVE_DELAY_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_96__PHY_RDDQ7_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDQ7_SLAVE_DELAY_0__REG DENALI_PHY_96 +#define LPDDR4__PHY_RDDQ7_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_96__PHY_RDDQ7_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_97_READ_MASK 0x000703FFU +#define LPDDR4__DENALI_PHY_97_WRITE_MASK 0x000703FFU +#define LPDDR4__DENALI_PHY_97__PHY_RDDM_SLAVE_DELAY_0_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_97__PHY_RDDM_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_97__PHY_RDDM_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDM_SLAVE_DELAY_0__REG DENALI_PHY_97 +#define LPDDR4__PHY_RDDM_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_97__PHY_RDDM_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_97__PHY_DATA_DC_CAL_CLK_SEL_0_MASK 0x00070000U +#define LPDDR4__DENALI_PHY_97__PHY_DATA_DC_CAL_CLK_SEL_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_97__PHY_DATA_DC_CAL_CLK_SEL_0_WIDTH 3U +#define LPDDR4__PHY_DATA_DC_CAL_CLK_SEL_0__REG DENALI_PHY_97 +#define LPDDR4__PHY_DATA_DC_CAL_CLK_SEL_0__FLD LPDDR4__DENALI_PHY_97__PHY_DATA_DC_CAL_CLK_SEL_0 + +#define LPDDR4__DENALI_PHY_98_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_98_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_98__PHY_DQ_OE_TIMING_0_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_98__PHY_DQ_OE_TIMING_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_98__PHY_DQ_OE_TIMING_0_WIDTH 8U +#define LPDDR4__PHY_DQ_OE_TIMING_0__REG DENALI_PHY_98 +#define LPDDR4__PHY_DQ_OE_TIMING_0__FLD LPDDR4__DENALI_PHY_98__PHY_DQ_OE_TIMING_0 + +#define LPDDR4__DENALI_PHY_98__PHY_DQ_TSEL_RD_TIMING_0_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_98__PHY_DQ_TSEL_RD_TIMING_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_98__PHY_DQ_TSEL_RD_TIMING_0_WIDTH 8U +#define LPDDR4__PHY_DQ_TSEL_RD_TIMING_0__REG DENALI_PHY_98 +#define LPDDR4__PHY_DQ_TSEL_RD_TIMING_0__FLD LPDDR4__DENALI_PHY_98__PHY_DQ_TSEL_RD_TIMING_0 + +#define LPDDR4__DENALI_PHY_98__PHY_DQ_TSEL_WR_TIMING_0_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_98__PHY_DQ_TSEL_WR_TIMING_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_98__PHY_DQ_TSEL_WR_TIMING_0_WIDTH 8U +#define LPDDR4__PHY_DQ_TSEL_WR_TIMING_0__REG DENALI_PHY_98 +#define LPDDR4__PHY_DQ_TSEL_WR_TIMING_0__FLD LPDDR4__DENALI_PHY_98__PHY_DQ_TSEL_WR_TIMING_0 + +#define LPDDR4__DENALI_PHY_98__PHY_DQS_OE_TIMING_0_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_98__PHY_DQS_OE_TIMING_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_98__PHY_DQS_OE_TIMING_0_WIDTH 8U +#define LPDDR4__PHY_DQS_OE_TIMING_0__REG DENALI_PHY_98 +#define LPDDR4__PHY_DQS_OE_TIMING_0__FLD LPDDR4__DENALI_PHY_98__PHY_DQS_OE_TIMING_0 + +#define LPDDR4__DENALI_PHY_99_READ_MASK 0xFFFFFF0FU +#define LPDDR4__DENALI_PHY_99_WRITE_MASK 0xFFFFFF0FU +#define LPDDR4__DENALI_PHY_99__PHY_IO_PAD_DELAY_TIMING_0_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_99__PHY_IO_PAD_DELAY_TIMING_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_99__PHY_IO_PAD_DELAY_TIMING_0_WIDTH 4U +#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_0__REG DENALI_PHY_99 +#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_0__FLD LPDDR4__DENALI_PHY_99__PHY_IO_PAD_DELAY_TIMING_0 + +#define LPDDR4__DENALI_PHY_99__PHY_DQS_TSEL_RD_TIMING_0_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_99__PHY_DQS_TSEL_RD_TIMING_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_99__PHY_DQS_TSEL_RD_TIMING_0_WIDTH 8U +#define LPDDR4__PHY_DQS_TSEL_RD_TIMING_0__REG DENALI_PHY_99 +#define LPDDR4__PHY_DQS_TSEL_RD_TIMING_0__FLD LPDDR4__DENALI_PHY_99__PHY_DQS_TSEL_RD_TIMING_0 + +#define LPDDR4__DENALI_PHY_99__PHY_DQS_OE_RD_TIMING_0_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_99__PHY_DQS_OE_RD_TIMING_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_99__PHY_DQS_OE_RD_TIMING_0_WIDTH 8U +#define LPDDR4__PHY_DQS_OE_RD_TIMING_0__REG DENALI_PHY_99 +#define LPDDR4__PHY_DQS_OE_RD_TIMING_0__FLD LPDDR4__DENALI_PHY_99__PHY_DQS_OE_RD_TIMING_0 + +#define LPDDR4__DENALI_PHY_99__PHY_DQS_TSEL_WR_TIMING_0_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_99__PHY_DQS_TSEL_WR_TIMING_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_99__PHY_DQS_TSEL_WR_TIMING_0_WIDTH 8U +#define LPDDR4__PHY_DQS_TSEL_WR_TIMING_0__REG DENALI_PHY_99 +#define LPDDR4__PHY_DQS_TSEL_WR_TIMING_0__FLD LPDDR4__DENALI_PHY_99__PHY_DQS_TSEL_WR_TIMING_0 + +#define LPDDR4__DENALI_PHY_100_READ_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_100_WRITE_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_100__PHY_VREF_SETTING_TIME_0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_100__PHY_VREF_SETTING_TIME_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_100__PHY_VREF_SETTING_TIME_0_WIDTH 16U +#define LPDDR4__PHY_VREF_SETTING_TIME_0__REG DENALI_PHY_100 +#define LPDDR4__PHY_VREF_SETTING_TIME_0__FLD LPDDR4__DENALI_PHY_100__PHY_VREF_SETTING_TIME_0 + +#define LPDDR4__DENALI_PHY_100__PHY_PAD_VREF_CTRL_DQ_0_MASK 0x0FFF0000U +#define LPDDR4__DENALI_PHY_100__PHY_PAD_VREF_CTRL_DQ_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_100__PHY_PAD_VREF_CTRL_DQ_0_WIDTH 12U +#define LPDDR4__PHY_PAD_VREF_CTRL_DQ_0__REG DENALI_PHY_100 +#define LPDDR4__PHY_PAD_VREF_CTRL_DQ_0__FLD LPDDR4__DENALI_PHY_100__PHY_PAD_VREF_CTRL_DQ_0 + +#define LPDDR4__DENALI_PHY_101_READ_MASK 0x03FFFF01U +#define LPDDR4__DENALI_PHY_101_WRITE_MASK 0x03FFFF01U +#define LPDDR4__DENALI_PHY_101__PHY_PER_CS_TRAINING_EN_0_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_101__PHY_PER_CS_TRAINING_EN_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_101__PHY_PER_CS_TRAINING_EN_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_101__PHY_PER_CS_TRAINING_EN_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_101__PHY_PER_CS_TRAINING_EN_0_WOSET 0U +#define LPDDR4__PHY_PER_CS_TRAINING_EN_0__REG DENALI_PHY_101 +#define LPDDR4__PHY_PER_CS_TRAINING_EN_0__FLD LPDDR4__DENALI_PHY_101__PHY_PER_CS_TRAINING_EN_0 + +#define LPDDR4__DENALI_PHY_101__PHY_DQ_IE_TIMING_0_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_101__PHY_DQ_IE_TIMING_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_101__PHY_DQ_IE_TIMING_0_WIDTH 8U +#define LPDDR4__PHY_DQ_IE_TIMING_0__REG DENALI_PHY_101 +#define LPDDR4__PHY_DQ_IE_TIMING_0__FLD LPDDR4__DENALI_PHY_101__PHY_DQ_IE_TIMING_0 + +#define LPDDR4__DENALI_PHY_101__PHY_DQS_IE_TIMING_0_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_101__PHY_DQS_IE_TIMING_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_101__PHY_DQS_IE_TIMING_0_WIDTH 8U +#define LPDDR4__PHY_DQS_IE_TIMING_0__REG DENALI_PHY_101 +#define LPDDR4__PHY_DQS_IE_TIMING_0__FLD LPDDR4__DENALI_PHY_101__PHY_DQS_IE_TIMING_0 + +#define LPDDR4__DENALI_PHY_101__PHY_RDDATA_EN_IE_DLY_0_MASK 0x03000000U +#define LPDDR4__DENALI_PHY_101__PHY_RDDATA_EN_IE_DLY_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_101__PHY_RDDATA_EN_IE_DLY_0_WIDTH 2U +#define LPDDR4__PHY_RDDATA_EN_IE_DLY_0__REG DENALI_PHY_101 +#define LPDDR4__PHY_RDDATA_EN_IE_DLY_0__FLD LPDDR4__DENALI_PHY_101__PHY_RDDATA_EN_IE_DLY_0 + +#define LPDDR4__DENALI_PHY_102_READ_MASK 0x1F1F0103U +#define LPDDR4__DENALI_PHY_102_WRITE_MASK 0x1F1F0103U +#define LPDDR4__DENALI_PHY_102__PHY_IE_MODE_0_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_102__PHY_IE_MODE_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_102__PHY_IE_MODE_0_WIDTH 2U +#define LPDDR4__PHY_IE_MODE_0__REG DENALI_PHY_102 +#define LPDDR4__PHY_IE_MODE_0__FLD LPDDR4__DENALI_PHY_102__PHY_IE_MODE_0 + +#define LPDDR4__DENALI_PHY_102__PHY_DBI_MODE_0_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_102__PHY_DBI_MODE_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_102__PHY_DBI_MODE_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_102__PHY_DBI_MODE_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_102__PHY_DBI_MODE_0_WOSET 0U +#define LPDDR4__PHY_DBI_MODE_0__REG DENALI_PHY_102 +#define LPDDR4__PHY_DBI_MODE_0__FLD LPDDR4__DENALI_PHY_102__PHY_DBI_MODE_0 + +#define LPDDR4__DENALI_PHY_102__PHY_RDDATA_EN_TSEL_DLY_0_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_102__PHY_RDDATA_EN_TSEL_DLY_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_102__PHY_RDDATA_EN_TSEL_DLY_0_WIDTH 5U +#define LPDDR4__PHY_RDDATA_EN_TSEL_DLY_0__REG DENALI_PHY_102 +#define LPDDR4__PHY_RDDATA_EN_TSEL_DLY_0__FLD LPDDR4__DENALI_PHY_102__PHY_RDDATA_EN_TSEL_DLY_0 + +#define LPDDR4__DENALI_PHY_102__PHY_RDDATA_EN_OE_DLY_0_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_102__PHY_RDDATA_EN_OE_DLY_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_102__PHY_RDDATA_EN_OE_DLY_0_WIDTH 5U +#define LPDDR4__PHY_RDDATA_EN_OE_DLY_0__REG DENALI_PHY_102 +#define LPDDR4__PHY_RDDATA_EN_OE_DLY_0__FLD LPDDR4__DENALI_PHY_102__PHY_RDDATA_EN_OE_DLY_0 + +#define LPDDR4__DENALI_PHY_103_READ_MASK 0x3F07FF0FU +#define LPDDR4__DENALI_PHY_103_WRITE_MASK 0x3F07FF0FU +#define LPDDR4__DENALI_PHY_103__PHY_SW_MASTER_MODE_0_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_103__PHY_SW_MASTER_MODE_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_103__PHY_SW_MASTER_MODE_0_WIDTH 4U +#define LPDDR4__PHY_SW_MASTER_MODE_0__REG DENALI_PHY_103 +#define LPDDR4__PHY_SW_MASTER_MODE_0__FLD LPDDR4__DENALI_PHY_103__PHY_SW_MASTER_MODE_0 + +#define LPDDR4__DENALI_PHY_103__PHY_MASTER_DELAY_START_0_MASK 0x0007FF00U +#define LPDDR4__DENALI_PHY_103__PHY_MASTER_DELAY_START_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_103__PHY_MASTER_DELAY_START_0_WIDTH 11U +#define LPDDR4__PHY_MASTER_DELAY_START_0__REG DENALI_PHY_103 +#define LPDDR4__PHY_MASTER_DELAY_START_0__FLD LPDDR4__DENALI_PHY_103__PHY_MASTER_DELAY_START_0 + +#define LPDDR4__DENALI_PHY_103__PHY_MASTER_DELAY_STEP_0_MASK 0x3F000000U +#define LPDDR4__DENALI_PHY_103__PHY_MASTER_DELAY_STEP_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_103__PHY_MASTER_DELAY_STEP_0_WIDTH 6U +#define LPDDR4__PHY_MASTER_DELAY_STEP_0__REG DENALI_PHY_103 +#define LPDDR4__PHY_MASTER_DELAY_STEP_0__FLD LPDDR4__DENALI_PHY_103__PHY_MASTER_DELAY_STEP_0 + +#define LPDDR4__DENALI_PHY_104_READ_MASK 0xFF0FFFFFU +#define LPDDR4__DENALI_PHY_104_WRITE_MASK 0xFF0FFFFFU +#define LPDDR4__DENALI_PHY_104__PHY_MASTER_DELAY_WAIT_0_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_104__PHY_MASTER_DELAY_WAIT_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_104__PHY_MASTER_DELAY_WAIT_0_WIDTH 8U +#define LPDDR4__PHY_MASTER_DELAY_WAIT_0__REG DENALI_PHY_104 +#define LPDDR4__PHY_MASTER_DELAY_WAIT_0__FLD LPDDR4__DENALI_PHY_104__PHY_MASTER_DELAY_WAIT_0 + +#define LPDDR4__DENALI_PHY_104__PHY_MASTER_DELAY_HALF_MEASURE_0_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_104__PHY_MASTER_DELAY_HALF_MEASURE_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_104__PHY_MASTER_DELAY_HALF_MEASURE_0_WIDTH 8U +#define LPDDR4__PHY_MASTER_DELAY_HALF_MEASURE_0__REG DENALI_PHY_104 +#define LPDDR4__PHY_MASTER_DELAY_HALF_MEASURE_0__FLD LPDDR4__DENALI_PHY_104__PHY_MASTER_DELAY_HALF_MEASURE_0 + +#define LPDDR4__DENALI_PHY_104__PHY_RPTR_UPDATE_0_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_104__PHY_RPTR_UPDATE_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_104__PHY_RPTR_UPDATE_0_WIDTH 4U +#define LPDDR4__PHY_RPTR_UPDATE_0__REG DENALI_PHY_104 +#define LPDDR4__PHY_RPTR_UPDATE_0__FLD LPDDR4__DENALI_PHY_104__PHY_RPTR_UPDATE_0 + +#define LPDDR4__DENALI_PHY_104__PHY_WRLVL_DLY_STEP_0_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_104__PHY_WRLVL_DLY_STEP_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_104__PHY_WRLVL_DLY_STEP_0_WIDTH 8U +#define LPDDR4__PHY_WRLVL_DLY_STEP_0__REG DENALI_PHY_104 +#define LPDDR4__PHY_WRLVL_DLY_STEP_0__FLD LPDDR4__DENALI_PHY_104__PHY_WRLVL_DLY_STEP_0 + +#define LPDDR4__DENALI_PHY_105_READ_MASK 0x1F0F3F0FU +#define LPDDR4__DENALI_PHY_105_WRITE_MASK 0x1F0F3F0FU +#define LPDDR4__DENALI_PHY_105__PHY_WRLVL_DLY_FINE_STEP_0_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_105__PHY_WRLVL_DLY_FINE_STEP_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_105__PHY_WRLVL_DLY_FINE_STEP_0_WIDTH 4U +#define LPDDR4__PHY_WRLVL_DLY_FINE_STEP_0__REG DENALI_PHY_105 +#define LPDDR4__PHY_WRLVL_DLY_FINE_STEP_0__FLD LPDDR4__DENALI_PHY_105__PHY_WRLVL_DLY_FINE_STEP_0 + +#define LPDDR4__DENALI_PHY_105__PHY_WRLVL_RESP_WAIT_CNT_0_MASK 0x00003F00U +#define LPDDR4__DENALI_PHY_105__PHY_WRLVL_RESP_WAIT_CNT_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_105__PHY_WRLVL_RESP_WAIT_CNT_0_WIDTH 6U +#define LPDDR4__PHY_WRLVL_RESP_WAIT_CNT_0__REG DENALI_PHY_105 +#define LPDDR4__PHY_WRLVL_RESP_WAIT_CNT_0__FLD LPDDR4__DENALI_PHY_105__PHY_WRLVL_RESP_WAIT_CNT_0 + +#define LPDDR4__DENALI_PHY_105__PHY_GTLVL_DLY_STEP_0_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_105__PHY_GTLVL_DLY_STEP_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_105__PHY_GTLVL_DLY_STEP_0_WIDTH 4U +#define LPDDR4__PHY_GTLVL_DLY_STEP_0__REG DENALI_PHY_105 +#define LPDDR4__PHY_GTLVL_DLY_STEP_0__FLD LPDDR4__DENALI_PHY_105__PHY_GTLVL_DLY_STEP_0 + +#define LPDDR4__DENALI_PHY_105__PHY_GTLVL_RESP_WAIT_CNT_0_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_105__PHY_GTLVL_RESP_WAIT_CNT_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_105__PHY_GTLVL_RESP_WAIT_CNT_0_WIDTH 5U +#define LPDDR4__PHY_GTLVL_RESP_WAIT_CNT_0__REG DENALI_PHY_105 +#define LPDDR4__PHY_GTLVL_RESP_WAIT_CNT_0__FLD LPDDR4__DENALI_PHY_105__PHY_GTLVL_RESP_WAIT_CNT_0 + +#define LPDDR4__DENALI_PHY_106_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_106_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_106__PHY_GTLVL_BACK_STEP_0_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_106__PHY_GTLVL_BACK_STEP_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_106__PHY_GTLVL_BACK_STEP_0_WIDTH 10U +#define LPDDR4__PHY_GTLVL_BACK_STEP_0__REG DENALI_PHY_106 +#define LPDDR4__PHY_GTLVL_BACK_STEP_0__FLD LPDDR4__DENALI_PHY_106__PHY_GTLVL_BACK_STEP_0 + +#define LPDDR4__DENALI_PHY_106__PHY_GTLVL_FINAL_STEP_0_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_106__PHY_GTLVL_FINAL_STEP_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_106__PHY_GTLVL_FINAL_STEP_0_WIDTH 10U +#define LPDDR4__PHY_GTLVL_FINAL_STEP_0__REG DENALI_PHY_106 +#define LPDDR4__PHY_GTLVL_FINAL_STEP_0__FLD LPDDR4__DENALI_PHY_106__PHY_GTLVL_FINAL_STEP_0 + +#define LPDDR4__DENALI_PHY_107_READ_MASK 0x0F010FFFU +#define LPDDR4__DENALI_PHY_107_WRITE_MASK 0x0F010FFFU +#define LPDDR4__DENALI_PHY_107__PHY_WDQLVL_DLY_STEP_0_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_107__PHY_WDQLVL_DLY_STEP_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_107__PHY_WDQLVL_DLY_STEP_0_WIDTH 8U +#define LPDDR4__PHY_WDQLVL_DLY_STEP_0__REG DENALI_PHY_107 +#define LPDDR4__PHY_WDQLVL_DLY_STEP_0__FLD LPDDR4__DENALI_PHY_107__PHY_WDQLVL_DLY_STEP_0 + +#define LPDDR4__DENALI_PHY_107__PHY_WDQLVL_QTR_DLY_STEP_0_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_107__PHY_WDQLVL_QTR_DLY_STEP_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_107__PHY_WDQLVL_QTR_DLY_STEP_0_WIDTH 4U +#define LPDDR4__PHY_WDQLVL_QTR_DLY_STEP_0__REG DENALI_PHY_107 +#define LPDDR4__PHY_WDQLVL_QTR_DLY_STEP_0__FLD LPDDR4__DENALI_PHY_107__PHY_WDQLVL_QTR_DLY_STEP_0 + +#define LPDDR4__DENALI_PHY_107__PHY_TOGGLE_PRE_SUPPORT_0_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_107__PHY_TOGGLE_PRE_SUPPORT_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_107__PHY_TOGGLE_PRE_SUPPORT_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_107__PHY_TOGGLE_PRE_SUPPORT_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_107__PHY_TOGGLE_PRE_SUPPORT_0_WOSET 0U +#define LPDDR4__PHY_TOGGLE_PRE_SUPPORT_0__REG DENALI_PHY_107 +#define LPDDR4__PHY_TOGGLE_PRE_SUPPORT_0__FLD LPDDR4__DENALI_PHY_107__PHY_TOGGLE_PRE_SUPPORT_0 + +#define LPDDR4__DENALI_PHY_107__PHY_RDLVL_DLY_STEP_0_MASK 0x0F000000U +#define LPDDR4__DENALI_PHY_107__PHY_RDLVL_DLY_STEP_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_107__PHY_RDLVL_DLY_STEP_0_WIDTH 4U +#define LPDDR4__PHY_RDLVL_DLY_STEP_0__REG DENALI_PHY_107 +#define LPDDR4__PHY_RDLVL_DLY_STEP_0__FLD LPDDR4__DENALI_PHY_107__PHY_RDLVL_DLY_STEP_0 + +#define LPDDR4__DENALI_PHY_108_READ_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_108_WRITE_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_108__PHY_RDLVL_MAX_EDGE_0_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_108__PHY_RDLVL_MAX_EDGE_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_108__PHY_RDLVL_MAX_EDGE_0_WIDTH 10U +#define LPDDR4__PHY_RDLVL_MAX_EDGE_0__REG DENALI_PHY_108 +#define LPDDR4__PHY_RDLVL_MAX_EDGE_0__FLD LPDDR4__DENALI_PHY_108__PHY_RDLVL_MAX_EDGE_0 + +#define LPDDR4__DENALI_PHY_109_READ_MASK 0x3F0103FFU +#define LPDDR4__DENALI_PHY_109_WRITE_MASK 0x3F0103FFU +#define LPDDR4__DENALI_PHY_109__PHY_RDLVL_DVW_MIN_0_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_109__PHY_RDLVL_DVW_MIN_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_109__PHY_RDLVL_DVW_MIN_0_WIDTH 10U +#define LPDDR4__PHY_RDLVL_DVW_MIN_0__REG DENALI_PHY_109 +#define LPDDR4__PHY_RDLVL_DVW_MIN_0__FLD LPDDR4__DENALI_PHY_109__PHY_RDLVL_DVW_MIN_0 + +#define LPDDR4__DENALI_PHY_109__PHY_SW_RDLVL_DVW_MIN_EN_0_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_109__PHY_SW_RDLVL_DVW_MIN_EN_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_109__PHY_SW_RDLVL_DVW_MIN_EN_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_109__PHY_SW_RDLVL_DVW_MIN_EN_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_109__PHY_SW_RDLVL_DVW_MIN_EN_0_WOSET 0U +#define LPDDR4__PHY_SW_RDLVL_DVW_MIN_EN_0__REG DENALI_PHY_109 +#define LPDDR4__PHY_SW_RDLVL_DVW_MIN_EN_0__FLD LPDDR4__DENALI_PHY_109__PHY_SW_RDLVL_DVW_MIN_EN_0 + +#define LPDDR4__DENALI_PHY_109__PHY_RDLVL_PER_START_OFFSET_0_MASK 0x3F000000U +#define LPDDR4__DENALI_PHY_109__PHY_RDLVL_PER_START_OFFSET_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_109__PHY_RDLVL_PER_START_OFFSET_0_WIDTH 6U +#define LPDDR4__PHY_RDLVL_PER_START_OFFSET_0__REG DENALI_PHY_109 +#define LPDDR4__PHY_RDLVL_PER_START_OFFSET_0__FLD LPDDR4__DENALI_PHY_109__PHY_RDLVL_PER_START_OFFSET_0 + +#define LPDDR4__DENALI_PHY_110_READ_MASK 0x00030703U +#define LPDDR4__DENALI_PHY_110_WRITE_MASK 0x00030703U +#define LPDDR4__DENALI_PHY_110__PHY_WRPATH_GATE_DISABLE_0_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_110__PHY_WRPATH_GATE_DISABLE_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_110__PHY_WRPATH_GATE_DISABLE_0_WIDTH 2U +#define LPDDR4__PHY_WRPATH_GATE_DISABLE_0__REG DENALI_PHY_110 +#define LPDDR4__PHY_WRPATH_GATE_DISABLE_0__FLD LPDDR4__DENALI_PHY_110__PHY_WRPATH_GATE_DISABLE_0 + +#define LPDDR4__DENALI_PHY_110__PHY_WRPATH_GATE_TIMING_0_MASK 0x00000700U +#define LPDDR4__DENALI_PHY_110__PHY_WRPATH_GATE_TIMING_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_110__PHY_WRPATH_GATE_TIMING_0_WIDTH 3U +#define LPDDR4__PHY_WRPATH_GATE_TIMING_0__REG DENALI_PHY_110 +#define LPDDR4__PHY_WRPATH_GATE_TIMING_0__FLD LPDDR4__DENALI_PHY_110__PHY_WRPATH_GATE_TIMING_0 + +#define LPDDR4__DENALI_PHY_110__PHY_DATA_DC_INIT_DISABLE_0_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_110__PHY_DATA_DC_INIT_DISABLE_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_110__PHY_DATA_DC_INIT_DISABLE_0_WIDTH 2U +#define LPDDR4__PHY_DATA_DC_INIT_DISABLE_0__REG DENALI_PHY_110 +#define LPDDR4__PHY_DATA_DC_INIT_DISABLE_0__FLD LPDDR4__DENALI_PHY_110__PHY_DATA_DC_INIT_DISABLE_0 + +#define LPDDR4__DENALI_PHY_111_READ_MASK 0x07FF03FFU +#define LPDDR4__DENALI_PHY_111_WRITE_MASK 0x07FF03FFU +#define LPDDR4__DENALI_PHY_111__PHY_DATA_DC_DQS_INIT_SLV_DELAY_0_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_111__PHY_DATA_DC_DQS_INIT_SLV_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_111__PHY_DATA_DC_DQS_INIT_SLV_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_DATA_DC_DQS_INIT_SLV_DELAY_0__REG DENALI_PHY_111 +#define LPDDR4__PHY_DATA_DC_DQS_INIT_SLV_DELAY_0__FLD LPDDR4__DENALI_PHY_111__PHY_DATA_DC_DQS_INIT_SLV_DELAY_0 + +#define LPDDR4__DENALI_PHY_111__PHY_DATA_DC_DQ_INIT_SLV_DELAY_0_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_111__PHY_DATA_DC_DQ_INIT_SLV_DELAY_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_111__PHY_DATA_DC_DQ_INIT_SLV_DELAY_0_WIDTH 11U +#define LPDDR4__PHY_DATA_DC_DQ_INIT_SLV_DELAY_0__REG DENALI_PHY_111 +#define LPDDR4__PHY_DATA_DC_DQ_INIT_SLV_DELAY_0__FLD LPDDR4__DENALI_PHY_111__PHY_DATA_DC_DQ_INIT_SLV_DELAY_0 + +#define LPDDR4__DENALI_PHY_112_READ_MASK 0xFFFF0101U +#define LPDDR4__DENALI_PHY_112_WRITE_MASK 0xFFFF0101U +#define LPDDR4__DENALI_PHY_112__PHY_DATA_DC_WRLVL_ENABLE_0_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_112__PHY_DATA_DC_WRLVL_ENABLE_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_112__PHY_DATA_DC_WRLVL_ENABLE_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_112__PHY_DATA_DC_WRLVL_ENABLE_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_112__PHY_DATA_DC_WRLVL_ENABLE_0_WOSET 0U +#define LPDDR4__PHY_DATA_DC_WRLVL_ENABLE_0__REG DENALI_PHY_112 +#define LPDDR4__PHY_DATA_DC_WRLVL_ENABLE_0__FLD LPDDR4__DENALI_PHY_112__PHY_DATA_DC_WRLVL_ENABLE_0 + +#define LPDDR4__DENALI_PHY_112__PHY_DATA_DC_WDQLVL_ENABLE_0_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_112__PHY_DATA_DC_WDQLVL_ENABLE_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_112__PHY_DATA_DC_WDQLVL_ENABLE_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_112__PHY_DATA_DC_WDQLVL_ENABLE_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_112__PHY_DATA_DC_WDQLVL_ENABLE_0_WOSET 0U +#define LPDDR4__PHY_DATA_DC_WDQLVL_ENABLE_0__REG DENALI_PHY_112 +#define LPDDR4__PHY_DATA_DC_WDQLVL_ENABLE_0__FLD LPDDR4__DENALI_PHY_112__PHY_DATA_DC_WDQLVL_ENABLE_0 + +#define LPDDR4__DENALI_PHY_112__PHY_DATA_DC_DM_CLK_SE_THRSHLD_0_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_112__PHY_DATA_DC_DM_CLK_SE_THRSHLD_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_112__PHY_DATA_DC_DM_CLK_SE_THRSHLD_0_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DM_CLK_SE_THRSHLD_0__REG DENALI_PHY_112 +#define LPDDR4__PHY_DATA_DC_DM_CLK_SE_THRSHLD_0__FLD LPDDR4__DENALI_PHY_112__PHY_DATA_DC_DM_CLK_SE_THRSHLD_0 + +#define LPDDR4__DENALI_PHY_112__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_0_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_112__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_112__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_0_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_0__REG DENALI_PHY_112 +#define LPDDR4__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_0__FLD LPDDR4__DENALI_PHY_112__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_0 + +#define LPDDR4__DENALI_PHY_113_READ_MASK 0x001F3F7FU +#define LPDDR4__DENALI_PHY_113_WRITE_MASK 0x001F3F7FU +#define LPDDR4__DENALI_PHY_113__PHY_WDQ_OSC_DELTA_0_MASK 0x0000007FU +#define LPDDR4__DENALI_PHY_113__PHY_WDQ_OSC_DELTA_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_113__PHY_WDQ_OSC_DELTA_0_WIDTH 7U +#define LPDDR4__PHY_WDQ_OSC_DELTA_0__REG DENALI_PHY_113 +#define LPDDR4__PHY_WDQ_OSC_DELTA_0__FLD LPDDR4__DENALI_PHY_113__PHY_WDQ_OSC_DELTA_0 + +#define LPDDR4__DENALI_PHY_113__PHY_MEAS_DLY_STEP_ENABLE_0_MASK 0x00003F00U +#define LPDDR4__DENALI_PHY_113__PHY_MEAS_DLY_STEP_ENABLE_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_113__PHY_MEAS_DLY_STEP_ENABLE_0_WIDTH 6U +#define LPDDR4__PHY_MEAS_DLY_STEP_ENABLE_0__REG DENALI_PHY_113 +#define LPDDR4__PHY_MEAS_DLY_STEP_ENABLE_0__FLD LPDDR4__DENALI_PHY_113__PHY_MEAS_DLY_STEP_ENABLE_0 + +#define LPDDR4__DENALI_PHY_113__PHY_RDDATA_EN_DLY_0_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_113__PHY_RDDATA_EN_DLY_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_113__PHY_RDDATA_EN_DLY_0_WIDTH 5U +#define LPDDR4__PHY_RDDATA_EN_DLY_0__REG DENALI_PHY_113 +#define LPDDR4__PHY_RDDATA_EN_DLY_0__FLD LPDDR4__DENALI_PHY_113__PHY_RDDATA_EN_DLY_0 + +#define LPDDR4__DENALI_PHY_114_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_114_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_114__PHY_DQ_DM_SWIZZLE0_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_114__PHY_DQ_DM_SWIZZLE0_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_114__PHY_DQ_DM_SWIZZLE0_0_WIDTH 32U +#define LPDDR4__PHY_DQ_DM_SWIZZLE0_0__REG DENALI_PHY_114 +#define LPDDR4__PHY_DQ_DM_SWIZZLE0_0__FLD LPDDR4__DENALI_PHY_114__PHY_DQ_DM_SWIZZLE0_0 + +#define LPDDR4__DENALI_PHY_115_READ_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_115_WRITE_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_115__PHY_DQ_DM_SWIZZLE1_0_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_115__PHY_DQ_DM_SWIZZLE1_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_115__PHY_DQ_DM_SWIZZLE1_0_WIDTH 4U +#define LPDDR4__PHY_DQ_DM_SWIZZLE1_0__REG DENALI_PHY_115 +#define LPDDR4__PHY_DQ_DM_SWIZZLE1_0__FLD LPDDR4__DENALI_PHY_115__PHY_DQ_DM_SWIZZLE1_0 + +#define LPDDR4__DENALI_PHY_116_READ_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_116_WRITE_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_116__PHY_CLK_WRDQ0_SLAVE_DELAY_0_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_116__PHY_CLK_WRDQ0_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_116__PHY_CLK_WRDQ0_SLAVE_DELAY_0_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDQ0_SLAVE_DELAY_0__REG DENALI_PHY_116 +#define LPDDR4__PHY_CLK_WRDQ0_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_116__PHY_CLK_WRDQ0_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_116__PHY_CLK_WRDQ1_SLAVE_DELAY_0_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_116__PHY_CLK_WRDQ1_SLAVE_DELAY_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_116__PHY_CLK_WRDQ1_SLAVE_DELAY_0_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDQ1_SLAVE_DELAY_0__REG DENALI_PHY_116 +#define LPDDR4__PHY_CLK_WRDQ1_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_116__PHY_CLK_WRDQ1_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_117_READ_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_117_WRITE_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_117__PHY_CLK_WRDQ2_SLAVE_DELAY_0_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_117__PHY_CLK_WRDQ2_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_117__PHY_CLK_WRDQ2_SLAVE_DELAY_0_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDQ2_SLAVE_DELAY_0__REG DENALI_PHY_117 +#define LPDDR4__PHY_CLK_WRDQ2_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_117__PHY_CLK_WRDQ2_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_117__PHY_CLK_WRDQ3_SLAVE_DELAY_0_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_117__PHY_CLK_WRDQ3_SLAVE_DELAY_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_117__PHY_CLK_WRDQ3_SLAVE_DELAY_0_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDQ3_SLAVE_DELAY_0__REG DENALI_PHY_117 +#define LPDDR4__PHY_CLK_WRDQ3_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_117__PHY_CLK_WRDQ3_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_118_READ_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_118_WRITE_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_118__PHY_CLK_WRDQ4_SLAVE_DELAY_0_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_118__PHY_CLK_WRDQ4_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_118__PHY_CLK_WRDQ4_SLAVE_DELAY_0_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDQ4_SLAVE_DELAY_0__REG DENALI_PHY_118 +#define LPDDR4__PHY_CLK_WRDQ4_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_118__PHY_CLK_WRDQ4_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_118__PHY_CLK_WRDQ5_SLAVE_DELAY_0_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_118__PHY_CLK_WRDQ5_SLAVE_DELAY_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_118__PHY_CLK_WRDQ5_SLAVE_DELAY_0_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDQ5_SLAVE_DELAY_0__REG DENALI_PHY_118 +#define LPDDR4__PHY_CLK_WRDQ5_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_118__PHY_CLK_WRDQ5_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_119_READ_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_119_WRITE_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_119__PHY_CLK_WRDQ6_SLAVE_DELAY_0_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_119__PHY_CLK_WRDQ6_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_119__PHY_CLK_WRDQ6_SLAVE_DELAY_0_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDQ6_SLAVE_DELAY_0__REG DENALI_PHY_119 +#define LPDDR4__PHY_CLK_WRDQ6_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_119__PHY_CLK_WRDQ6_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_119__PHY_CLK_WRDQ7_SLAVE_DELAY_0_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_119__PHY_CLK_WRDQ7_SLAVE_DELAY_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_119__PHY_CLK_WRDQ7_SLAVE_DELAY_0_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDQ7_SLAVE_DELAY_0__REG DENALI_PHY_119 +#define LPDDR4__PHY_CLK_WRDQ7_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_119__PHY_CLK_WRDQ7_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_120_READ_MASK 0x03FF07FFU +#define LPDDR4__DENALI_PHY_120_WRITE_MASK 0x03FF07FFU +#define LPDDR4__DENALI_PHY_120__PHY_CLK_WRDM_SLAVE_DELAY_0_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_120__PHY_CLK_WRDM_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_120__PHY_CLK_WRDM_SLAVE_DELAY_0_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDM_SLAVE_DELAY_0__REG DENALI_PHY_120 +#define LPDDR4__PHY_CLK_WRDM_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_120__PHY_CLK_WRDM_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_120__PHY_CLK_WRDQS_SLAVE_DELAY_0_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_120__PHY_CLK_WRDQS_SLAVE_DELAY_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_120__PHY_CLK_WRDQS_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_0__REG DENALI_PHY_120 +#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_120__PHY_CLK_WRDQS_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_121_READ_MASK 0x0003FF03U +#define LPDDR4__DENALI_PHY_121_WRITE_MASK 0x0003FF03U +#define LPDDR4__DENALI_PHY_121__PHY_WRLVL_THRESHOLD_ADJUST_0_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_121__PHY_WRLVL_THRESHOLD_ADJUST_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_121__PHY_WRLVL_THRESHOLD_ADJUST_0_WIDTH 2U +#define LPDDR4__PHY_WRLVL_THRESHOLD_ADJUST_0__REG DENALI_PHY_121 +#define LPDDR4__PHY_WRLVL_THRESHOLD_ADJUST_0__FLD LPDDR4__DENALI_PHY_121__PHY_WRLVL_THRESHOLD_ADJUST_0 + +#define LPDDR4__DENALI_PHY_121__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_0_MASK 0x0003FF00U +#define LPDDR4__DENALI_PHY_121__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_121__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_0__REG DENALI_PHY_121 +#define LPDDR4__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_121__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_122_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_122_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_122__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_0_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_122__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_122__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_0__REG DENALI_PHY_122 +#define LPDDR4__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_122__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_122__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_0_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_122__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_122__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_0__REG DENALI_PHY_122 +#define LPDDR4__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_122__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_123_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_123_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_123__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_0_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_123__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_123__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_0__REG DENALI_PHY_123 +#define LPDDR4__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_123__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_123__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_0_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_123__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_123__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_0__REG DENALI_PHY_123 +#define LPDDR4__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_123__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_124_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_124_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_124__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_0_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_124__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_124__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_0__REG DENALI_PHY_124 +#define LPDDR4__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_124__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_124__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_0_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_124__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_124__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_0__REG DENALI_PHY_124 +#define LPDDR4__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_124__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_125_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_125_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_125__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_0_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_125__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_125__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_0__REG DENALI_PHY_125 +#define LPDDR4__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_125__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_125__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_0_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_125__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_125__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_0__REG DENALI_PHY_125 +#define LPDDR4__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_125__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_126_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_126_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_126__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_0_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_126__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_126__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_0__REG DENALI_PHY_126 +#define LPDDR4__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_126__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_126__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_0_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_126__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_126__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_0__REG DENALI_PHY_126 +#define LPDDR4__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_126__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_127_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_127_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_127__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_0_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_127__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_127__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_0__REG DENALI_PHY_127 +#define LPDDR4__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_127__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_127__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_0_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_127__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_127__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_0__REG DENALI_PHY_127 +#define LPDDR4__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_127__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_128_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_128_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_128__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_0_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_128__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_128__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_0__REG DENALI_PHY_128 +#define LPDDR4__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_128__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_128__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_0_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_128__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_128__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_0__REG DENALI_PHY_128 +#define LPDDR4__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_128__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_129_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_129_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_129__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_0_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_129__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_129__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_0__REG DENALI_PHY_129 +#define LPDDR4__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_129__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_129__PHY_RDDQS_DM_RISE_SLAVE_DELAY_0_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_129__PHY_RDDQS_DM_RISE_SLAVE_DELAY_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_129__PHY_RDDQS_DM_RISE_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DM_RISE_SLAVE_DELAY_0__REG DENALI_PHY_129 +#define LPDDR4__PHY_RDDQS_DM_RISE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_129__PHY_RDDQS_DM_RISE_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_130_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_130_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_130__PHY_RDDQS_DM_FALL_SLAVE_DELAY_0_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_130__PHY_RDDQS_DM_FALL_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_130__PHY_RDDQS_DM_FALL_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DM_FALL_SLAVE_DELAY_0__REG DENALI_PHY_130 +#define LPDDR4__PHY_RDDQS_DM_FALL_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_130__PHY_RDDQS_DM_FALL_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_130__PHY_RDDQS_GATE_SLAVE_DELAY_0_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_130__PHY_RDDQS_GATE_SLAVE_DELAY_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_130__PHY_RDDQS_GATE_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDQS_GATE_SLAVE_DELAY_0__REG DENALI_PHY_130 +#define LPDDR4__PHY_RDDQS_GATE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_130__PHY_RDDQS_GATE_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_131_READ_MASK 0x03FF070FU +#define LPDDR4__DENALI_PHY_131_WRITE_MASK 0x03FF070FU +#define LPDDR4__DENALI_PHY_131__PHY_RDDQS_LATENCY_ADJUST_0_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_131__PHY_RDDQS_LATENCY_ADJUST_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_131__PHY_RDDQS_LATENCY_ADJUST_0_WIDTH 4U +#define LPDDR4__PHY_RDDQS_LATENCY_ADJUST_0__REG DENALI_PHY_131 +#define LPDDR4__PHY_RDDQS_LATENCY_ADJUST_0__FLD LPDDR4__DENALI_PHY_131__PHY_RDDQS_LATENCY_ADJUST_0 + +#define LPDDR4__DENALI_PHY_131__PHY_WRITE_PATH_LAT_ADD_0_MASK 0x00000700U +#define LPDDR4__DENALI_PHY_131__PHY_WRITE_PATH_LAT_ADD_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_131__PHY_WRITE_PATH_LAT_ADD_0_WIDTH 3U +#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_0__REG DENALI_PHY_131 +#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_0__FLD LPDDR4__DENALI_PHY_131__PHY_WRITE_PATH_LAT_ADD_0 + +#define LPDDR4__DENALI_PHY_131__PHY_WRLVL_DELAY_EARLY_THRESHOLD_0_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_131__PHY_WRLVL_DELAY_EARLY_THRESHOLD_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_131__PHY_WRLVL_DELAY_EARLY_THRESHOLD_0_WIDTH 10U +#define LPDDR4__PHY_WRLVL_DELAY_EARLY_THRESHOLD_0__REG DENALI_PHY_131 +#define LPDDR4__PHY_WRLVL_DELAY_EARLY_THRESHOLD_0__FLD LPDDR4__DENALI_PHY_131__PHY_WRLVL_DELAY_EARLY_THRESHOLD_0 + +#define LPDDR4__DENALI_PHY_132_READ_MASK 0x000103FFU +#define LPDDR4__DENALI_PHY_132_WRITE_MASK 0x000103FFU +#define LPDDR4__DENALI_PHY_132__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_0_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_132__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_132__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_0_WIDTH 10U +#define LPDDR4__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_0__REG DENALI_PHY_132 +#define LPDDR4__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_0__FLD LPDDR4__DENALI_PHY_132__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_0 + +#define LPDDR4__DENALI_PHY_132__PHY_WRLVL_EARLY_FORCE_ZERO_0_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_132__PHY_WRLVL_EARLY_FORCE_ZERO_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_132__PHY_WRLVL_EARLY_FORCE_ZERO_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_132__PHY_WRLVL_EARLY_FORCE_ZERO_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_132__PHY_WRLVL_EARLY_FORCE_ZERO_0_WOSET 0U +#define LPDDR4__PHY_WRLVL_EARLY_FORCE_ZERO_0__REG DENALI_PHY_132 +#define LPDDR4__PHY_WRLVL_EARLY_FORCE_ZERO_0__FLD LPDDR4__DENALI_PHY_132__PHY_WRLVL_EARLY_FORCE_ZERO_0 + +#define LPDDR4__DENALI_PHY_133_READ_MASK 0x000F03FFU +#define LPDDR4__DENALI_PHY_133_WRITE_MASK 0x000F03FFU +#define LPDDR4__DENALI_PHY_133__PHY_GTLVL_RDDQS_SLV_DLY_START_0_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_133__PHY_GTLVL_RDDQS_SLV_DLY_START_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_133__PHY_GTLVL_RDDQS_SLV_DLY_START_0_WIDTH 10U +#define LPDDR4__PHY_GTLVL_RDDQS_SLV_DLY_START_0__REG DENALI_PHY_133 +#define LPDDR4__PHY_GTLVL_RDDQS_SLV_DLY_START_0__FLD LPDDR4__DENALI_PHY_133__PHY_GTLVL_RDDQS_SLV_DLY_START_0 + +#define LPDDR4__DENALI_PHY_133__PHY_GTLVL_LAT_ADJ_START_0_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_133__PHY_GTLVL_LAT_ADJ_START_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_133__PHY_GTLVL_LAT_ADJ_START_0_WIDTH 4U +#define LPDDR4__PHY_GTLVL_LAT_ADJ_START_0__REG DENALI_PHY_133 +#define LPDDR4__PHY_GTLVL_LAT_ADJ_START_0__FLD LPDDR4__DENALI_PHY_133__PHY_GTLVL_LAT_ADJ_START_0 + +#define LPDDR4__DENALI_PHY_134_READ_MASK 0x010F07FFU +#define LPDDR4__DENALI_PHY_134_WRITE_MASK 0x010F07FFU +#define LPDDR4__DENALI_PHY_134__PHY_WDQLVL_DQDM_SLV_DLY_START_0_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_134__PHY_WDQLVL_DQDM_SLV_DLY_START_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_134__PHY_WDQLVL_DQDM_SLV_DLY_START_0_WIDTH 11U +#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_START_0__REG DENALI_PHY_134 +#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_START_0__FLD LPDDR4__DENALI_PHY_134__PHY_WDQLVL_DQDM_SLV_DLY_START_0 + +#define LPDDR4__DENALI_PHY_134__PHY_NTP_WRLAT_START_0_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_134__PHY_NTP_WRLAT_START_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_134__PHY_NTP_WRLAT_START_0_WIDTH 4U +#define LPDDR4__PHY_NTP_WRLAT_START_0__REG DENALI_PHY_134 +#define LPDDR4__PHY_NTP_WRLAT_START_0__FLD LPDDR4__DENALI_PHY_134__PHY_NTP_WRLAT_START_0 + +#define LPDDR4__DENALI_PHY_134__PHY_NTP_PASS_0_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_134__PHY_NTP_PASS_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_134__PHY_NTP_PASS_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_134__PHY_NTP_PASS_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_134__PHY_NTP_PASS_0_WOSET 0U +#define LPDDR4__PHY_NTP_PASS_0__REG DENALI_PHY_134 +#define LPDDR4__PHY_NTP_PASS_0__FLD LPDDR4__DENALI_PHY_134__PHY_NTP_PASS_0 + +#define LPDDR4__DENALI_PHY_135_READ_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_135_WRITE_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_135__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_0_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_135__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_135__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_0_WIDTH 10U +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_0__REG DENALI_PHY_135 +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_0__FLD LPDDR4__DENALI_PHY_135__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_0 + +#define LPDDR4__DENALI_PHY_136_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_136_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_136__PHY_DATA_DC_DQS_CLK_ADJUST_0_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_136__PHY_DATA_DC_DQS_CLK_ADJUST_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_136__PHY_DATA_DC_DQS_CLK_ADJUST_0_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DQS_CLK_ADJUST_0__REG DENALI_PHY_136 +#define LPDDR4__PHY_DATA_DC_DQS_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_136__PHY_DATA_DC_DQS_CLK_ADJUST_0 + +#define LPDDR4__DENALI_PHY_136__PHY_DATA_DC_DQ0_CLK_ADJUST_0_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_136__PHY_DATA_DC_DQ0_CLK_ADJUST_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_136__PHY_DATA_DC_DQ0_CLK_ADJUST_0_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DQ0_CLK_ADJUST_0__REG DENALI_PHY_136 +#define LPDDR4__PHY_DATA_DC_DQ0_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_136__PHY_DATA_DC_DQ0_CLK_ADJUST_0 + +#define LPDDR4__DENALI_PHY_136__PHY_DATA_DC_DQ1_CLK_ADJUST_0_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_136__PHY_DATA_DC_DQ1_CLK_ADJUST_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_136__PHY_DATA_DC_DQ1_CLK_ADJUST_0_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DQ1_CLK_ADJUST_0__REG DENALI_PHY_136 +#define LPDDR4__PHY_DATA_DC_DQ1_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_136__PHY_DATA_DC_DQ1_CLK_ADJUST_0 + +#define LPDDR4__DENALI_PHY_136__PHY_DATA_DC_DQ2_CLK_ADJUST_0_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_136__PHY_DATA_DC_DQ2_CLK_ADJUST_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_136__PHY_DATA_DC_DQ2_CLK_ADJUST_0_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DQ2_CLK_ADJUST_0__REG DENALI_PHY_136 +#define LPDDR4__PHY_DATA_DC_DQ2_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_136__PHY_DATA_DC_DQ2_CLK_ADJUST_0 + +#define LPDDR4__DENALI_PHY_137_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_137_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_137__PHY_DATA_DC_DQ3_CLK_ADJUST_0_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_137__PHY_DATA_DC_DQ3_CLK_ADJUST_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_137__PHY_DATA_DC_DQ3_CLK_ADJUST_0_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DQ3_CLK_ADJUST_0__REG DENALI_PHY_137 +#define LPDDR4__PHY_DATA_DC_DQ3_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_137__PHY_DATA_DC_DQ3_CLK_ADJUST_0 + +#define LPDDR4__DENALI_PHY_137__PHY_DATA_DC_DQ4_CLK_ADJUST_0_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_137__PHY_DATA_DC_DQ4_CLK_ADJUST_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_137__PHY_DATA_DC_DQ4_CLK_ADJUST_0_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DQ4_CLK_ADJUST_0__REG DENALI_PHY_137 +#define LPDDR4__PHY_DATA_DC_DQ4_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_137__PHY_DATA_DC_DQ4_CLK_ADJUST_0 + +#define LPDDR4__DENALI_PHY_137__PHY_DATA_DC_DQ5_CLK_ADJUST_0_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_137__PHY_DATA_DC_DQ5_CLK_ADJUST_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_137__PHY_DATA_DC_DQ5_CLK_ADJUST_0_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DQ5_CLK_ADJUST_0__REG DENALI_PHY_137 +#define LPDDR4__PHY_DATA_DC_DQ5_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_137__PHY_DATA_DC_DQ5_CLK_ADJUST_0 + +#define LPDDR4__DENALI_PHY_137__PHY_DATA_DC_DQ6_CLK_ADJUST_0_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_137__PHY_DATA_DC_DQ6_CLK_ADJUST_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_137__PHY_DATA_DC_DQ6_CLK_ADJUST_0_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DQ6_CLK_ADJUST_0__REG DENALI_PHY_137 +#define LPDDR4__PHY_DATA_DC_DQ6_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_137__PHY_DATA_DC_DQ6_CLK_ADJUST_0 + +#define LPDDR4__DENALI_PHY_138_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_138_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_138__PHY_DATA_DC_DQ7_CLK_ADJUST_0_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_138__PHY_DATA_DC_DQ7_CLK_ADJUST_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_138__PHY_DATA_DC_DQ7_CLK_ADJUST_0_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DQ7_CLK_ADJUST_0__REG DENALI_PHY_138 +#define LPDDR4__PHY_DATA_DC_DQ7_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_138__PHY_DATA_DC_DQ7_CLK_ADJUST_0 + +#define LPDDR4__DENALI_PHY_138__PHY_DATA_DC_DM_CLK_ADJUST_0_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_138__PHY_DATA_DC_DM_CLK_ADJUST_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_138__PHY_DATA_DC_DM_CLK_ADJUST_0_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DM_CLK_ADJUST_0__REG DENALI_PHY_138 +#define LPDDR4__PHY_DATA_DC_DM_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_138__PHY_DATA_DC_DM_CLK_ADJUST_0 + +#define LPDDR4__DENALI_PHY_138__PHY_DSLICE_PAD_BOOSTPN_SETTING_0_MASK 0xFFFF0000U +#define LPDDR4__DENALI_PHY_138__PHY_DSLICE_PAD_BOOSTPN_SETTING_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_138__PHY_DSLICE_PAD_BOOSTPN_SETTING_0_WIDTH 16U +#define LPDDR4__PHY_DSLICE_PAD_BOOSTPN_SETTING_0__REG DENALI_PHY_138 +#define LPDDR4__PHY_DSLICE_PAD_BOOSTPN_SETTING_0__FLD LPDDR4__DENALI_PHY_138__PHY_DSLICE_PAD_BOOSTPN_SETTING_0 + +#define LPDDR4__DENALI_PHY_139_READ_MASK 0x0003033FU +#define LPDDR4__DENALI_PHY_139_WRITE_MASK 0x0003033FU +#define LPDDR4__DENALI_PHY_139__PHY_DSLICE_PAD_RX_CTLE_SETTING_0_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_139__PHY_DSLICE_PAD_RX_CTLE_SETTING_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_139__PHY_DSLICE_PAD_RX_CTLE_SETTING_0_WIDTH 6U +#define LPDDR4__PHY_DSLICE_PAD_RX_CTLE_SETTING_0__REG DENALI_PHY_139 +#define LPDDR4__PHY_DSLICE_PAD_RX_CTLE_SETTING_0__FLD LPDDR4__DENALI_PHY_139__PHY_DSLICE_PAD_RX_CTLE_SETTING_0 + +#define LPDDR4__DENALI_PHY_139__PHY_DQ_FFE_0_MASK 0x00000300U +#define LPDDR4__DENALI_PHY_139__PHY_DQ_FFE_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_139__PHY_DQ_FFE_0_WIDTH 2U +#define LPDDR4__PHY_DQ_FFE_0__REG DENALI_PHY_139 +#define LPDDR4__PHY_DQ_FFE_0__FLD LPDDR4__DENALI_PHY_139__PHY_DQ_FFE_0 + +#define LPDDR4__DENALI_PHY_139__PHY_DQS_FFE_0_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_139__PHY_DQS_FFE_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_139__PHY_DQS_FFE_0_WIDTH 2U +#define LPDDR4__PHY_DQS_FFE_0__REG DENALI_PHY_139 +#define LPDDR4__PHY_DQS_FFE_0__FLD LPDDR4__DENALI_PHY_139__PHY_DQS_FFE_0 + +#endif /* REG_LPDDR4_DATA_SLICE_0_MACROS_H_ */ diff --git a/drivers/ram/k3-j721e/lpddr4_data_slice_1_macros.h b/drivers/ram/k3-j721e/lpddr4_data_slice_1_macros.h new file mode 100644 index 0000000..124f58f --- /dev/null +++ b/drivers/ram/k3-j721e/lpddr4_data_slice_1_macros.h @@ -0,0 +1,2373 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/********************************************************************** + * Copyright (C) 2012-2019 Cadence Design Systems, Inc. + * + * THIS FILE IS AUTOMATICALLY GENERATED, DO NOT EDIT + * + ********************************************************************** + */ + +#ifndef REG_LPDDR4_DATA_SLICE_1_MACROS_H_ +#define REG_LPDDR4_DATA_SLICE_1_MACROS_H_ + +#define LPDDR4__DENALI_PHY_256_READ_MASK 0x000F07FFU +#define LPDDR4__DENALI_PHY_256_WRITE_MASK 0x000F07FFU +#define LPDDR4__DENALI_PHY_256__PHY_CLK_WR_BYPASS_SLAVE_DELAY_1_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_256__PHY_CLK_WR_BYPASS_SLAVE_DELAY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_256__PHY_CLK_WR_BYPASS_SLAVE_DELAY_1_WIDTH 11U +#define LPDDR4__PHY_CLK_WR_BYPASS_SLAVE_DELAY_1__REG DENALI_PHY_256 +#define LPDDR4__PHY_CLK_WR_BYPASS_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_256__PHY_CLK_WR_BYPASS_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_256__PHY_IO_PAD_DELAY_TIMING_BYPASS_1_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_256__PHY_IO_PAD_DELAY_TIMING_BYPASS_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_256__PHY_IO_PAD_DELAY_TIMING_BYPASS_1_WIDTH 4U +#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_BYPASS_1__REG DENALI_PHY_256 +#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_BYPASS_1__FLD LPDDR4__DENALI_PHY_256__PHY_IO_PAD_DELAY_TIMING_BYPASS_1 + +#define LPDDR4__DENALI_PHY_257_READ_MASK 0x000703FFU +#define LPDDR4__DENALI_PHY_257_WRITE_MASK 0x000703FFU +#define LPDDR4__DENALI_PHY_257__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_1_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_257__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_257__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_1_WIDTH 10U +#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_1__REG DENALI_PHY_257 +#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_1__FLD LPDDR4__DENALI_PHY_257__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_1 + +#define LPDDR4__DENALI_PHY_257__PHY_WRITE_PATH_LAT_ADD_BYPASS_1_MASK 0x00070000U +#define LPDDR4__DENALI_PHY_257__PHY_WRITE_PATH_LAT_ADD_BYPASS_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_257__PHY_WRITE_PATH_LAT_ADD_BYPASS_1_WIDTH 3U +#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_BYPASS_1__REG DENALI_PHY_257 +#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_BYPASS_1__FLD LPDDR4__DENALI_PHY_257__PHY_WRITE_PATH_LAT_ADD_BYPASS_1 + +#define LPDDR4__DENALI_PHY_258_READ_MASK 0x010303FFU +#define LPDDR4__DENALI_PHY_258_WRITE_MASK 0x010303FFU +#define LPDDR4__DENALI_PHY_258__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_1_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_258__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_258__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_1__REG DENALI_PHY_258 +#define LPDDR4__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_258__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_258__PHY_BYPASS_TWO_CYC_PREAMBLE_1_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_258__PHY_BYPASS_TWO_CYC_PREAMBLE_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_258__PHY_BYPASS_TWO_CYC_PREAMBLE_1_WIDTH 2U +#define LPDDR4__PHY_BYPASS_TWO_CYC_PREAMBLE_1__REG DENALI_PHY_258 +#define LPDDR4__PHY_BYPASS_TWO_CYC_PREAMBLE_1__FLD LPDDR4__DENALI_PHY_258__PHY_BYPASS_TWO_CYC_PREAMBLE_1 + +#define LPDDR4__DENALI_PHY_258__PHY_CLK_BYPASS_OVERRIDE_1_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_258__PHY_CLK_BYPASS_OVERRIDE_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_258__PHY_CLK_BYPASS_OVERRIDE_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_258__PHY_CLK_BYPASS_OVERRIDE_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_258__PHY_CLK_BYPASS_OVERRIDE_1_WOSET 0U +#define LPDDR4__PHY_CLK_BYPASS_OVERRIDE_1__REG DENALI_PHY_258 +#define LPDDR4__PHY_CLK_BYPASS_OVERRIDE_1__FLD LPDDR4__DENALI_PHY_258__PHY_CLK_BYPASS_OVERRIDE_1 + +#define LPDDR4__DENALI_PHY_259_READ_MASK 0x3F3F3F3FU +#define LPDDR4__DENALI_PHY_259_WRITE_MASK 0x3F3F3F3FU +#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ0_SHIFT_1_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ0_SHIFT_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ0_SHIFT_1_WIDTH 6U +#define LPDDR4__PHY_SW_WRDQ0_SHIFT_1__REG DENALI_PHY_259 +#define LPDDR4__PHY_SW_WRDQ0_SHIFT_1__FLD LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ0_SHIFT_1 + +#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ1_SHIFT_1_MASK 0x00003F00U +#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ1_SHIFT_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ1_SHIFT_1_WIDTH 6U +#define LPDDR4__PHY_SW_WRDQ1_SHIFT_1__REG DENALI_PHY_259 +#define LPDDR4__PHY_SW_WRDQ1_SHIFT_1__FLD LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ1_SHIFT_1 + +#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ2_SHIFT_1_MASK 0x003F0000U +#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ2_SHIFT_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ2_SHIFT_1_WIDTH 6U +#define LPDDR4__PHY_SW_WRDQ2_SHIFT_1__REG DENALI_PHY_259 +#define LPDDR4__PHY_SW_WRDQ2_SHIFT_1__FLD LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ2_SHIFT_1 + +#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ3_SHIFT_1_MASK 0x3F000000U +#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ3_SHIFT_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ3_SHIFT_1_WIDTH 6U +#define LPDDR4__PHY_SW_WRDQ3_SHIFT_1__REG DENALI_PHY_259 +#define LPDDR4__PHY_SW_WRDQ3_SHIFT_1__FLD LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ3_SHIFT_1 + +#define LPDDR4__DENALI_PHY_260_READ_MASK 0x3F3F3F3FU +#define LPDDR4__DENALI_PHY_260_WRITE_MASK 0x3F3F3F3FU +#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ4_SHIFT_1_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ4_SHIFT_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ4_SHIFT_1_WIDTH 6U +#define LPDDR4__PHY_SW_WRDQ4_SHIFT_1__REG DENALI_PHY_260 +#define LPDDR4__PHY_SW_WRDQ4_SHIFT_1__FLD LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ4_SHIFT_1 + +#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ5_SHIFT_1_MASK 0x00003F00U +#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ5_SHIFT_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ5_SHIFT_1_WIDTH 6U +#define LPDDR4__PHY_SW_WRDQ5_SHIFT_1__REG DENALI_PHY_260 +#define LPDDR4__PHY_SW_WRDQ5_SHIFT_1__FLD LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ5_SHIFT_1 + +#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ6_SHIFT_1_MASK 0x003F0000U +#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ6_SHIFT_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ6_SHIFT_1_WIDTH 6U +#define LPDDR4__PHY_SW_WRDQ6_SHIFT_1__REG DENALI_PHY_260 +#define LPDDR4__PHY_SW_WRDQ6_SHIFT_1__FLD LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ6_SHIFT_1 + +#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ7_SHIFT_1_MASK 0x3F000000U +#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ7_SHIFT_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ7_SHIFT_1_WIDTH 6U +#define LPDDR4__PHY_SW_WRDQ7_SHIFT_1__REG DENALI_PHY_260 +#define LPDDR4__PHY_SW_WRDQ7_SHIFT_1__FLD LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ7_SHIFT_1 + +#define LPDDR4__DENALI_PHY_261_READ_MASK 0x01030F3FU +#define LPDDR4__DENALI_PHY_261_WRITE_MASK 0x01030F3FU +#define LPDDR4__DENALI_PHY_261__PHY_SW_WRDM_SHIFT_1_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_261__PHY_SW_WRDM_SHIFT_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_261__PHY_SW_WRDM_SHIFT_1_WIDTH 6U +#define LPDDR4__PHY_SW_WRDM_SHIFT_1__REG DENALI_PHY_261 +#define LPDDR4__PHY_SW_WRDM_SHIFT_1__FLD LPDDR4__DENALI_PHY_261__PHY_SW_WRDM_SHIFT_1 + +#define LPDDR4__DENALI_PHY_261__PHY_SW_WRDQS_SHIFT_1_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_261__PHY_SW_WRDQS_SHIFT_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_261__PHY_SW_WRDQS_SHIFT_1_WIDTH 4U +#define LPDDR4__PHY_SW_WRDQS_SHIFT_1__REG DENALI_PHY_261 +#define LPDDR4__PHY_SW_WRDQS_SHIFT_1__FLD LPDDR4__DENALI_PHY_261__PHY_SW_WRDQS_SHIFT_1 + +#define LPDDR4__DENALI_PHY_261__PHY_PER_RANK_CS_MAP_1_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_261__PHY_PER_RANK_CS_MAP_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_261__PHY_PER_RANK_CS_MAP_1_WIDTH 2U +#define LPDDR4__PHY_PER_RANK_CS_MAP_1__REG DENALI_PHY_261 +#define LPDDR4__PHY_PER_RANK_CS_MAP_1__FLD LPDDR4__DENALI_PHY_261__PHY_PER_RANK_CS_MAP_1 + +#define LPDDR4__DENALI_PHY_261__PHY_PER_CS_TRAINING_MULTICAST_EN_1_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_261__PHY_PER_CS_TRAINING_MULTICAST_EN_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_261__PHY_PER_CS_TRAINING_MULTICAST_EN_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_261__PHY_PER_CS_TRAINING_MULTICAST_EN_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_261__PHY_PER_CS_TRAINING_MULTICAST_EN_1_WOSET 0U +#define LPDDR4__PHY_PER_CS_TRAINING_MULTICAST_EN_1__REG DENALI_PHY_261 +#define LPDDR4__PHY_PER_CS_TRAINING_MULTICAST_EN_1__FLD LPDDR4__DENALI_PHY_261__PHY_PER_CS_TRAINING_MULTICAST_EN_1 + +#define LPDDR4__DENALI_PHY_262_READ_MASK 0x1F1F0301U +#define LPDDR4__DENALI_PHY_262_WRITE_MASK 0x1F1F0301U +#define LPDDR4__DENALI_PHY_262__PHY_PER_CS_TRAINING_INDEX_1_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_262__PHY_PER_CS_TRAINING_INDEX_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_262__PHY_PER_CS_TRAINING_INDEX_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_262__PHY_PER_CS_TRAINING_INDEX_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_262__PHY_PER_CS_TRAINING_INDEX_1_WOSET 0U +#define LPDDR4__PHY_PER_CS_TRAINING_INDEX_1__REG DENALI_PHY_262 +#define LPDDR4__PHY_PER_CS_TRAINING_INDEX_1__FLD LPDDR4__DENALI_PHY_262__PHY_PER_CS_TRAINING_INDEX_1 + +#define LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_1_MASK 0x00000300U +#define LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_1_WIDTH 2U +#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_1__REG DENALI_PHY_262 +#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_1__FLD LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_1 + +#define LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RDDATA_EN_DLY_1_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RDDATA_EN_DLY_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RDDATA_EN_DLY_1_WIDTH 5U +#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_DLY_1__REG DENALI_PHY_262 +#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_DLY_1__FLD LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RDDATA_EN_DLY_1 + +#define LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_1_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_1_WIDTH 5U +#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_1__REG DENALI_PHY_262 +#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_1__FLD LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_1 + +#define LPDDR4__DENALI_PHY_263_READ_MASK 0x1F030F0FU +#define LPDDR4__DENALI_PHY_263_WRITE_MASK 0x1F030F0FU +#define LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_RPTR_UPDATE_1_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_RPTR_UPDATE_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_RPTR_UPDATE_1_WIDTH 4U +#define LPDDR4__PHY_LP4_BOOT_RPTR_UPDATE_1__REG DENALI_PHY_263 +#define LPDDR4__PHY_LP4_BOOT_RPTR_UPDATE_1__FLD LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_RPTR_UPDATE_1 + +#define LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_1_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_1_WIDTH 4U +#define LPDDR4__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_1__REG DENALI_PHY_263 +#define LPDDR4__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_1__FLD LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_1 + +#define LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_1_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_1_WIDTH 2U +#define LPDDR4__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_1__REG DENALI_PHY_263 +#define LPDDR4__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_1__FLD LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_1 + +#define LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_1_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_1_WIDTH 5U +#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_1__REG DENALI_PHY_263 +#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_1__FLD LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_1 + +#define LPDDR4__DENALI_PHY_264_READ_MASK 0x0101FF03U +#define LPDDR4__DENALI_PHY_264_WRITE_MASK 0x0101FF03U +#define LPDDR4__DENALI_PHY_264__PHY_CTRL_LPBK_EN_1_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_264__PHY_CTRL_LPBK_EN_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_264__PHY_CTRL_LPBK_EN_1_WIDTH 2U +#define LPDDR4__PHY_CTRL_LPBK_EN_1__REG DENALI_PHY_264 +#define LPDDR4__PHY_CTRL_LPBK_EN_1__FLD LPDDR4__DENALI_PHY_264__PHY_CTRL_LPBK_EN_1 + +#define LPDDR4__DENALI_PHY_264__PHY_LPBK_CONTROL_1_MASK 0x0001FF00U +#define LPDDR4__DENALI_PHY_264__PHY_LPBK_CONTROL_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_264__PHY_LPBK_CONTROL_1_WIDTH 9U +#define LPDDR4__PHY_LPBK_CONTROL_1__REG DENALI_PHY_264 +#define LPDDR4__PHY_LPBK_CONTROL_1__FLD LPDDR4__DENALI_PHY_264__PHY_LPBK_CONTROL_1 + +#define LPDDR4__DENALI_PHY_264__PHY_LPBK_DFX_TIMEOUT_EN_1_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_264__PHY_LPBK_DFX_TIMEOUT_EN_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_264__PHY_LPBK_DFX_TIMEOUT_EN_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_264__PHY_LPBK_DFX_TIMEOUT_EN_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_264__PHY_LPBK_DFX_TIMEOUT_EN_1_WOSET 0U +#define LPDDR4__PHY_LPBK_DFX_TIMEOUT_EN_1__REG DENALI_PHY_264 +#define LPDDR4__PHY_LPBK_DFX_TIMEOUT_EN_1__FLD LPDDR4__DENALI_PHY_264__PHY_LPBK_DFX_TIMEOUT_EN_1 + +#define LPDDR4__DENALI_PHY_265_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_265_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_265__PHY_AUTO_TIMING_MARGIN_CONTROL_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_265__PHY_AUTO_TIMING_MARGIN_CONTROL_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_265__PHY_AUTO_TIMING_MARGIN_CONTROL_1_WIDTH 32U +#define LPDDR4__PHY_AUTO_TIMING_MARGIN_CONTROL_1__REG DENALI_PHY_265 +#define LPDDR4__PHY_AUTO_TIMING_MARGIN_CONTROL_1__FLD LPDDR4__DENALI_PHY_265__PHY_AUTO_TIMING_MARGIN_CONTROL_1 + +#define LPDDR4__DENALI_PHY_266_READ_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_266_WRITE_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_266__PHY_AUTO_TIMING_MARGIN_OBS_1_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_266__PHY_AUTO_TIMING_MARGIN_OBS_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_266__PHY_AUTO_TIMING_MARGIN_OBS_1_WIDTH 28U +#define LPDDR4__PHY_AUTO_TIMING_MARGIN_OBS_1__REG DENALI_PHY_266 +#define LPDDR4__PHY_AUTO_TIMING_MARGIN_OBS_1__FLD LPDDR4__DENALI_PHY_266__PHY_AUTO_TIMING_MARGIN_OBS_1 + +#define LPDDR4__DENALI_PHY_267_READ_MASK 0x0101FF7FU +#define LPDDR4__DENALI_PHY_267_WRITE_MASK 0x0101FF7FU +#define LPDDR4__DENALI_PHY_267__PHY_PRBS_PATTERN_START_1_MASK 0x0000007FU +#define LPDDR4__DENALI_PHY_267__PHY_PRBS_PATTERN_START_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_267__PHY_PRBS_PATTERN_START_1_WIDTH 7U +#define LPDDR4__PHY_PRBS_PATTERN_START_1__REG DENALI_PHY_267 +#define LPDDR4__PHY_PRBS_PATTERN_START_1__FLD LPDDR4__DENALI_PHY_267__PHY_PRBS_PATTERN_START_1 + +#define LPDDR4__DENALI_PHY_267__PHY_PRBS_PATTERN_MASK_1_MASK 0x0001FF00U +#define LPDDR4__DENALI_PHY_267__PHY_PRBS_PATTERN_MASK_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_267__PHY_PRBS_PATTERN_MASK_1_WIDTH 9U +#define LPDDR4__PHY_PRBS_PATTERN_MASK_1__REG DENALI_PHY_267 +#define LPDDR4__PHY_PRBS_PATTERN_MASK_1__FLD LPDDR4__DENALI_PHY_267__PHY_PRBS_PATTERN_MASK_1 + +#define LPDDR4__DENALI_PHY_267__PHY_RDLVL_MULTI_PATT_ENABLE_1_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_267__PHY_RDLVL_MULTI_PATT_ENABLE_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_267__PHY_RDLVL_MULTI_PATT_ENABLE_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_267__PHY_RDLVL_MULTI_PATT_ENABLE_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_267__PHY_RDLVL_MULTI_PATT_ENABLE_1_WOSET 0U +#define LPDDR4__PHY_RDLVL_MULTI_PATT_ENABLE_1__REG DENALI_PHY_267 +#define LPDDR4__PHY_RDLVL_MULTI_PATT_ENABLE_1__FLD LPDDR4__DENALI_PHY_267__PHY_RDLVL_MULTI_PATT_ENABLE_1 + +#define LPDDR4__DENALI_PHY_268_READ_MASK 0x007F3F01U +#define LPDDR4__DENALI_PHY_268_WRITE_MASK 0x007F3F01U +#define LPDDR4__DENALI_PHY_268__PHY_RDLVL_MULTI_PATT_RST_DISABLE_1_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_268__PHY_RDLVL_MULTI_PATT_RST_DISABLE_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_268__PHY_RDLVL_MULTI_PATT_RST_DISABLE_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_268__PHY_RDLVL_MULTI_PATT_RST_DISABLE_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_268__PHY_RDLVL_MULTI_PATT_RST_DISABLE_1_WOSET 0U +#define LPDDR4__PHY_RDLVL_MULTI_PATT_RST_DISABLE_1__REG DENALI_PHY_268 +#define LPDDR4__PHY_RDLVL_MULTI_PATT_RST_DISABLE_1__FLD LPDDR4__DENALI_PHY_268__PHY_RDLVL_MULTI_PATT_RST_DISABLE_1 + +#define LPDDR4__DENALI_PHY_268__PHY_VREF_INITIAL_STEPSIZE_1_MASK 0x00003F00U +#define LPDDR4__DENALI_PHY_268__PHY_VREF_INITIAL_STEPSIZE_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_268__PHY_VREF_INITIAL_STEPSIZE_1_WIDTH 6U +#define LPDDR4__PHY_VREF_INITIAL_STEPSIZE_1__REG DENALI_PHY_268 +#define LPDDR4__PHY_VREF_INITIAL_STEPSIZE_1__FLD LPDDR4__DENALI_PHY_268__PHY_VREF_INITIAL_STEPSIZE_1 + +#define LPDDR4__DENALI_PHY_268__PHY_VREF_TRAIN_OBS_1_MASK 0x007F0000U +#define LPDDR4__DENALI_PHY_268__PHY_VREF_TRAIN_OBS_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_268__PHY_VREF_TRAIN_OBS_1_WIDTH 7U +#define LPDDR4__PHY_VREF_TRAIN_OBS_1__REG DENALI_PHY_268 +#define LPDDR4__PHY_VREF_TRAIN_OBS_1__FLD LPDDR4__DENALI_PHY_268__PHY_VREF_TRAIN_OBS_1 + +#define LPDDR4__DENALI_PHY_269_READ_MASK 0x000F03FFU +#define LPDDR4__DENALI_PHY_269_WRITE_MASK 0x000F03FFU +#define LPDDR4__DENALI_PHY_269__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_1_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_269__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_269__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_1__REG DENALI_PHY_269 +#define LPDDR4__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_269__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_269__PHY_GATE_ERROR_DELAY_SELECT_1_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_269__PHY_GATE_ERROR_DELAY_SELECT_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_269__PHY_GATE_ERROR_DELAY_SELECT_1_WIDTH 4U +#define LPDDR4__PHY_GATE_ERROR_DELAY_SELECT_1__REG DENALI_PHY_269 +#define LPDDR4__PHY_GATE_ERROR_DELAY_SELECT_1__FLD LPDDR4__DENALI_PHY_269__PHY_GATE_ERROR_DELAY_SELECT_1 + +#define LPDDR4__DENALI_PHY_269__SC_PHY_SNAP_OBS_REGS_1_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_269__SC_PHY_SNAP_OBS_REGS_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_269__SC_PHY_SNAP_OBS_REGS_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_269__SC_PHY_SNAP_OBS_REGS_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_269__SC_PHY_SNAP_OBS_REGS_1_WOSET 0U +#define LPDDR4__SC_PHY_SNAP_OBS_REGS_1__REG DENALI_PHY_269 +#define LPDDR4__SC_PHY_SNAP_OBS_REGS_1__FLD LPDDR4__DENALI_PHY_269__SC_PHY_SNAP_OBS_REGS_1 + +#define LPDDR4__DENALI_PHY_270_READ_MASK 0x070101FFU +#define LPDDR4__DENALI_PHY_270_WRITE_MASK 0x070101FFU +#define LPDDR4__DENALI_PHY_270__PHY_GATE_SMPL1_SLAVE_DELAY_1_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_270__PHY_GATE_SMPL1_SLAVE_DELAY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_270__PHY_GATE_SMPL1_SLAVE_DELAY_1_WIDTH 9U +#define LPDDR4__PHY_GATE_SMPL1_SLAVE_DELAY_1__REG DENALI_PHY_270 +#define LPDDR4__PHY_GATE_SMPL1_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_270__PHY_GATE_SMPL1_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_270__PHY_LPDDR_1_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_270__PHY_LPDDR_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_270__PHY_LPDDR_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_270__PHY_LPDDR_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_270__PHY_LPDDR_1_WOSET 0U +#define LPDDR4__PHY_LPDDR_1__REG DENALI_PHY_270 +#define LPDDR4__PHY_LPDDR_1__FLD LPDDR4__DENALI_PHY_270__PHY_LPDDR_1 + +#define LPDDR4__DENALI_PHY_270__PHY_MEM_CLASS_1_MASK 0x07000000U +#define LPDDR4__DENALI_PHY_270__PHY_MEM_CLASS_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_270__PHY_MEM_CLASS_1_WIDTH 3U +#define LPDDR4__PHY_MEM_CLASS_1__REG DENALI_PHY_270 +#define LPDDR4__PHY_MEM_CLASS_1__FLD LPDDR4__DENALI_PHY_270__PHY_MEM_CLASS_1 + +#define LPDDR4__DENALI_PHY_271_READ_MASK 0x000301FFU +#define LPDDR4__DENALI_PHY_271_WRITE_MASK 0x000301FFU +#define LPDDR4__DENALI_PHY_271__PHY_GATE_SMPL2_SLAVE_DELAY_1_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_271__PHY_GATE_SMPL2_SLAVE_DELAY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_271__PHY_GATE_SMPL2_SLAVE_DELAY_1_WIDTH 9U +#define LPDDR4__PHY_GATE_SMPL2_SLAVE_DELAY_1__REG DENALI_PHY_271 +#define LPDDR4__PHY_GATE_SMPL2_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_271__PHY_GATE_SMPL2_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_271__ON_FLY_GATE_ADJUST_EN_1_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_271__ON_FLY_GATE_ADJUST_EN_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_271__ON_FLY_GATE_ADJUST_EN_1_WIDTH 2U +#define LPDDR4__ON_FLY_GATE_ADJUST_EN_1__REG DENALI_PHY_271 +#define LPDDR4__ON_FLY_GATE_ADJUST_EN_1__FLD LPDDR4__DENALI_PHY_271__ON_FLY_GATE_ADJUST_EN_1 + +#define LPDDR4__DENALI_PHY_272_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_272_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_272__PHY_GATE_TRACKING_OBS_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_272__PHY_GATE_TRACKING_OBS_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_272__PHY_GATE_TRACKING_OBS_1_WIDTH 32U +#define LPDDR4__PHY_GATE_TRACKING_OBS_1__REG DENALI_PHY_272 +#define LPDDR4__PHY_GATE_TRACKING_OBS_1__FLD LPDDR4__DENALI_PHY_272__PHY_GATE_TRACKING_OBS_1 + +#define LPDDR4__DENALI_PHY_273_READ_MASK 0x00000301U +#define LPDDR4__DENALI_PHY_273_WRITE_MASK 0x00000301U +#define LPDDR4__DENALI_PHY_273__PHY_DFI40_POLARITY_1_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_273__PHY_DFI40_POLARITY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_273__PHY_DFI40_POLARITY_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_273__PHY_DFI40_POLARITY_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_273__PHY_DFI40_POLARITY_1_WOSET 0U +#define LPDDR4__PHY_DFI40_POLARITY_1__REG DENALI_PHY_273 +#define LPDDR4__PHY_DFI40_POLARITY_1__FLD LPDDR4__DENALI_PHY_273__PHY_DFI40_POLARITY_1 + +#define LPDDR4__DENALI_PHY_273__PHY_LP4_PST_AMBLE_1_MASK 0x00000300U +#define LPDDR4__DENALI_PHY_273__PHY_LP4_PST_AMBLE_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_273__PHY_LP4_PST_AMBLE_1_WIDTH 2U +#define LPDDR4__PHY_LP4_PST_AMBLE_1__REG DENALI_PHY_273 +#define LPDDR4__PHY_LP4_PST_AMBLE_1__FLD LPDDR4__DENALI_PHY_273__PHY_LP4_PST_AMBLE_1 + +#define LPDDR4__DENALI_PHY_274_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_274_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_274__PHY_RDLVL_PATT8_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_274__PHY_RDLVL_PATT8_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_274__PHY_RDLVL_PATT8_1_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PATT8_1__REG DENALI_PHY_274 +#define LPDDR4__PHY_RDLVL_PATT8_1__FLD LPDDR4__DENALI_PHY_274__PHY_RDLVL_PATT8_1 + +#define LPDDR4__DENALI_PHY_275_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_275_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_275__PHY_RDLVL_PATT9_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_275__PHY_RDLVL_PATT9_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_275__PHY_RDLVL_PATT9_1_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PATT9_1__REG DENALI_PHY_275 +#define LPDDR4__PHY_RDLVL_PATT9_1__FLD LPDDR4__DENALI_PHY_275__PHY_RDLVL_PATT9_1 + +#define LPDDR4__DENALI_PHY_276_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_276_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_276__PHY_RDLVL_PATT10_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_276__PHY_RDLVL_PATT10_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_276__PHY_RDLVL_PATT10_1_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PATT10_1__REG DENALI_PHY_276 +#define LPDDR4__PHY_RDLVL_PATT10_1__FLD LPDDR4__DENALI_PHY_276__PHY_RDLVL_PATT10_1 + +#define LPDDR4__DENALI_PHY_277_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_277_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_277__PHY_RDLVL_PATT11_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_277__PHY_RDLVL_PATT11_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_277__PHY_RDLVL_PATT11_1_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PATT11_1__REG DENALI_PHY_277 +#define LPDDR4__PHY_RDLVL_PATT11_1__FLD LPDDR4__DENALI_PHY_277__PHY_RDLVL_PATT11_1 + +#define LPDDR4__DENALI_PHY_278_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_278_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_278__PHY_RDLVL_PATT12_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_278__PHY_RDLVL_PATT12_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_278__PHY_RDLVL_PATT12_1_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PATT12_1__REG DENALI_PHY_278 +#define LPDDR4__PHY_RDLVL_PATT12_1__FLD LPDDR4__DENALI_PHY_278__PHY_RDLVL_PATT12_1 + +#define LPDDR4__DENALI_PHY_279_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_279_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_279__PHY_RDLVL_PATT13_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_279__PHY_RDLVL_PATT13_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_279__PHY_RDLVL_PATT13_1_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PATT13_1__REG DENALI_PHY_279 +#define LPDDR4__PHY_RDLVL_PATT13_1__FLD LPDDR4__DENALI_PHY_279__PHY_RDLVL_PATT13_1 + +#define LPDDR4__DENALI_PHY_280_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_280_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_280__PHY_RDLVL_PATT14_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_280__PHY_RDLVL_PATT14_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_280__PHY_RDLVL_PATT14_1_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PATT14_1__REG DENALI_PHY_280 +#define LPDDR4__PHY_RDLVL_PATT14_1__FLD LPDDR4__DENALI_PHY_280__PHY_RDLVL_PATT14_1 + +#define LPDDR4__DENALI_PHY_281_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_281_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_281__PHY_RDLVL_PATT15_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_281__PHY_RDLVL_PATT15_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_281__PHY_RDLVL_PATT15_1_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PATT15_1__REG DENALI_PHY_281 +#define LPDDR4__PHY_RDLVL_PATT15_1__FLD LPDDR4__DENALI_PHY_281__PHY_RDLVL_PATT15_1 + +#define LPDDR4__DENALI_PHY_282_READ_MASK 0x070F0107U +#define LPDDR4__DENALI_PHY_282_WRITE_MASK 0x070F0107U +#define LPDDR4__DENALI_PHY_282__PHY_SLAVE_LOOP_CNT_UPDATE_1_MASK 0x00000007U +#define LPDDR4__DENALI_PHY_282__PHY_SLAVE_LOOP_CNT_UPDATE_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_282__PHY_SLAVE_LOOP_CNT_UPDATE_1_WIDTH 3U +#define LPDDR4__PHY_SLAVE_LOOP_CNT_UPDATE_1__REG DENALI_PHY_282 +#define LPDDR4__PHY_SLAVE_LOOP_CNT_UPDATE_1__FLD LPDDR4__DENALI_PHY_282__PHY_SLAVE_LOOP_CNT_UPDATE_1 + +#define LPDDR4__DENALI_PHY_282__PHY_SW_FIFO_PTR_RST_DISABLE_1_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_282__PHY_SW_FIFO_PTR_RST_DISABLE_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_282__PHY_SW_FIFO_PTR_RST_DISABLE_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_282__PHY_SW_FIFO_PTR_RST_DISABLE_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_282__PHY_SW_FIFO_PTR_RST_DISABLE_1_WOSET 0U +#define LPDDR4__PHY_SW_FIFO_PTR_RST_DISABLE_1__REG DENALI_PHY_282 +#define LPDDR4__PHY_SW_FIFO_PTR_RST_DISABLE_1__FLD LPDDR4__DENALI_PHY_282__PHY_SW_FIFO_PTR_RST_DISABLE_1 + +#define LPDDR4__DENALI_PHY_282__PHY_MASTER_DLY_LOCK_OBS_SELECT_1_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_282__PHY_MASTER_DLY_LOCK_OBS_SELECT_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_282__PHY_MASTER_DLY_LOCK_OBS_SELECT_1_WIDTH 4U +#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_SELECT_1__REG DENALI_PHY_282 +#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_282__PHY_MASTER_DLY_LOCK_OBS_SELECT_1 + +#define LPDDR4__DENALI_PHY_282__PHY_RDDQ_ENC_OBS_SELECT_1_MASK 0x07000000U +#define LPDDR4__DENALI_PHY_282__PHY_RDDQ_ENC_OBS_SELECT_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_282__PHY_RDDQ_ENC_OBS_SELECT_1_WIDTH 3U +#define LPDDR4__PHY_RDDQ_ENC_OBS_SELECT_1__REG DENALI_PHY_282 +#define LPDDR4__PHY_RDDQ_ENC_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_282__PHY_RDDQ_ENC_OBS_SELECT_1 + +#define LPDDR4__DENALI_PHY_283_READ_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_PHY_283_WRITE_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_PHY_283__PHY_RDDQS_DQ_ENC_OBS_SELECT_1_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_283__PHY_RDDQS_DQ_ENC_OBS_SELECT_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_283__PHY_RDDQS_DQ_ENC_OBS_SELECT_1_WIDTH 4U +#define LPDDR4__PHY_RDDQS_DQ_ENC_OBS_SELECT_1__REG DENALI_PHY_283 +#define LPDDR4__PHY_RDDQS_DQ_ENC_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_283__PHY_RDDQS_DQ_ENC_OBS_SELECT_1 + +#define LPDDR4__DENALI_PHY_283__PHY_WR_ENC_OBS_SELECT_1_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_283__PHY_WR_ENC_OBS_SELECT_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_283__PHY_WR_ENC_OBS_SELECT_1_WIDTH 4U +#define LPDDR4__PHY_WR_ENC_OBS_SELECT_1__REG DENALI_PHY_283 +#define LPDDR4__PHY_WR_ENC_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_283__PHY_WR_ENC_OBS_SELECT_1 + +#define LPDDR4__DENALI_PHY_283__PHY_WR_SHIFT_OBS_SELECT_1_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_283__PHY_WR_SHIFT_OBS_SELECT_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_283__PHY_WR_SHIFT_OBS_SELECT_1_WIDTH 4U +#define LPDDR4__PHY_WR_SHIFT_OBS_SELECT_1__REG DENALI_PHY_283 +#define LPDDR4__PHY_WR_SHIFT_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_283__PHY_WR_SHIFT_OBS_SELECT_1 + +#define LPDDR4__DENALI_PHY_283__PHY_FIFO_PTR_OBS_SELECT_1_MASK 0x0F000000U +#define LPDDR4__DENALI_PHY_283__PHY_FIFO_PTR_OBS_SELECT_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_283__PHY_FIFO_PTR_OBS_SELECT_1_WIDTH 4U +#define LPDDR4__PHY_FIFO_PTR_OBS_SELECT_1__REG DENALI_PHY_283 +#define LPDDR4__PHY_FIFO_PTR_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_283__PHY_FIFO_PTR_OBS_SELECT_1 + +#define LPDDR4__DENALI_PHY_284_READ_MASK 0xFF030001U +#define LPDDR4__DENALI_PHY_284_WRITE_MASK 0xFF030001U +#define LPDDR4__DENALI_PHY_284__PHY_LVL_DEBUG_MODE_1_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_284__PHY_LVL_DEBUG_MODE_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_284__PHY_LVL_DEBUG_MODE_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_284__PHY_LVL_DEBUG_MODE_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_284__PHY_LVL_DEBUG_MODE_1_WOSET 0U +#define LPDDR4__PHY_LVL_DEBUG_MODE_1__REG DENALI_PHY_284 +#define LPDDR4__PHY_LVL_DEBUG_MODE_1__FLD LPDDR4__DENALI_PHY_284__PHY_LVL_DEBUG_MODE_1 + +#define LPDDR4__DENALI_PHY_284__SC_PHY_LVL_DEBUG_CONT_1_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_284__SC_PHY_LVL_DEBUG_CONT_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_284__SC_PHY_LVL_DEBUG_CONT_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_284__SC_PHY_LVL_DEBUG_CONT_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_284__SC_PHY_LVL_DEBUG_CONT_1_WOSET 0U +#define LPDDR4__SC_PHY_LVL_DEBUG_CONT_1__REG DENALI_PHY_284 +#define LPDDR4__SC_PHY_LVL_DEBUG_CONT_1__FLD LPDDR4__DENALI_PHY_284__SC_PHY_LVL_DEBUG_CONT_1 + +#define LPDDR4__DENALI_PHY_284__PHY_WRLVL_ALGO_1_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_284__PHY_WRLVL_ALGO_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_284__PHY_WRLVL_ALGO_1_WIDTH 2U +#define LPDDR4__PHY_WRLVL_ALGO_1__REG DENALI_PHY_284 +#define LPDDR4__PHY_WRLVL_ALGO_1__FLD LPDDR4__DENALI_PHY_284__PHY_WRLVL_ALGO_1 + +#define LPDDR4__DENALI_PHY_284__PHY_WRLVL_PER_START_1_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_284__PHY_WRLVL_PER_START_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_284__PHY_WRLVL_PER_START_1_WIDTH 8U +#define LPDDR4__PHY_WRLVL_PER_START_1__REG DENALI_PHY_284 +#define LPDDR4__PHY_WRLVL_PER_START_1__FLD LPDDR4__DENALI_PHY_284__PHY_WRLVL_PER_START_1 + +#define LPDDR4__DENALI_PHY_285_READ_MASK 0x00FF0F3FU +#define LPDDR4__DENALI_PHY_285_WRITE_MASK 0x00FF0F3FU +#define LPDDR4__DENALI_PHY_285__PHY_WRLVL_CAPTURE_CNT_1_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_285__PHY_WRLVL_CAPTURE_CNT_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_285__PHY_WRLVL_CAPTURE_CNT_1_WIDTH 6U +#define LPDDR4__PHY_WRLVL_CAPTURE_CNT_1__REG DENALI_PHY_285 +#define LPDDR4__PHY_WRLVL_CAPTURE_CNT_1__FLD LPDDR4__DENALI_PHY_285__PHY_WRLVL_CAPTURE_CNT_1 + +#define LPDDR4__DENALI_PHY_285__PHY_WRLVL_UPDT_WAIT_CNT_1_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_285__PHY_WRLVL_UPDT_WAIT_CNT_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_285__PHY_WRLVL_UPDT_WAIT_CNT_1_WIDTH 4U +#define LPDDR4__PHY_WRLVL_UPDT_WAIT_CNT_1__REG DENALI_PHY_285 +#define LPDDR4__PHY_WRLVL_UPDT_WAIT_CNT_1__FLD LPDDR4__DENALI_PHY_285__PHY_WRLVL_UPDT_WAIT_CNT_1 + +#define LPDDR4__DENALI_PHY_285__PHY_DQ_MASK_1_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_285__PHY_DQ_MASK_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_285__PHY_DQ_MASK_1_WIDTH 8U +#define LPDDR4__PHY_DQ_MASK_1__REG DENALI_PHY_285 +#define LPDDR4__PHY_DQ_MASK_1__FLD LPDDR4__DENALI_PHY_285__PHY_DQ_MASK_1 + +#define LPDDR4__DENALI_PHY_286_READ_MASK 0x0F3F03FFU +#define LPDDR4__DENALI_PHY_286_WRITE_MASK 0x0F3F03FFU +#define LPDDR4__DENALI_PHY_286__PHY_GTLVL_PER_START_1_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_286__PHY_GTLVL_PER_START_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_286__PHY_GTLVL_PER_START_1_WIDTH 10U +#define LPDDR4__PHY_GTLVL_PER_START_1__REG DENALI_PHY_286 +#define LPDDR4__PHY_GTLVL_PER_START_1__FLD LPDDR4__DENALI_PHY_286__PHY_GTLVL_PER_START_1 + +#define LPDDR4__DENALI_PHY_286__PHY_GTLVL_CAPTURE_CNT_1_MASK 0x003F0000U +#define LPDDR4__DENALI_PHY_286__PHY_GTLVL_CAPTURE_CNT_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_286__PHY_GTLVL_CAPTURE_CNT_1_WIDTH 6U +#define LPDDR4__PHY_GTLVL_CAPTURE_CNT_1__REG DENALI_PHY_286 +#define LPDDR4__PHY_GTLVL_CAPTURE_CNT_1__FLD LPDDR4__DENALI_PHY_286__PHY_GTLVL_CAPTURE_CNT_1 + +#define LPDDR4__DENALI_PHY_286__PHY_GTLVL_UPDT_WAIT_CNT_1_MASK 0x0F000000U +#define LPDDR4__DENALI_PHY_286__PHY_GTLVL_UPDT_WAIT_CNT_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_286__PHY_GTLVL_UPDT_WAIT_CNT_1_WIDTH 4U +#define LPDDR4__PHY_GTLVL_UPDT_WAIT_CNT_1__REG DENALI_PHY_286 +#define LPDDR4__PHY_GTLVL_UPDT_WAIT_CNT_1__FLD LPDDR4__DENALI_PHY_286__PHY_GTLVL_UPDT_WAIT_CNT_1 + +#define LPDDR4__DENALI_PHY_287_READ_MASK 0x1F030F3FU +#define LPDDR4__DENALI_PHY_287_WRITE_MASK 0x1F030F3FU +#define LPDDR4__DENALI_PHY_287__PHY_RDLVL_CAPTURE_CNT_1_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_287__PHY_RDLVL_CAPTURE_CNT_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_287__PHY_RDLVL_CAPTURE_CNT_1_WIDTH 6U +#define LPDDR4__PHY_RDLVL_CAPTURE_CNT_1__REG DENALI_PHY_287 +#define LPDDR4__PHY_RDLVL_CAPTURE_CNT_1__FLD LPDDR4__DENALI_PHY_287__PHY_RDLVL_CAPTURE_CNT_1 + +#define LPDDR4__DENALI_PHY_287__PHY_RDLVL_UPDT_WAIT_CNT_1_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_287__PHY_RDLVL_UPDT_WAIT_CNT_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_287__PHY_RDLVL_UPDT_WAIT_CNT_1_WIDTH 4U +#define LPDDR4__PHY_RDLVL_UPDT_WAIT_CNT_1__REG DENALI_PHY_287 +#define LPDDR4__PHY_RDLVL_UPDT_WAIT_CNT_1__FLD LPDDR4__DENALI_PHY_287__PHY_RDLVL_UPDT_WAIT_CNT_1 + +#define LPDDR4__DENALI_PHY_287__PHY_RDLVL_OP_MODE_1_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_287__PHY_RDLVL_OP_MODE_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_287__PHY_RDLVL_OP_MODE_1_WIDTH 2U +#define LPDDR4__PHY_RDLVL_OP_MODE_1__REG DENALI_PHY_287 +#define LPDDR4__PHY_RDLVL_OP_MODE_1__FLD LPDDR4__DENALI_PHY_287__PHY_RDLVL_OP_MODE_1 + +#define LPDDR4__DENALI_PHY_287__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_1_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_287__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_287__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_1_WIDTH 5U +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_1__REG DENALI_PHY_287 +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_287__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_1 + +#define LPDDR4__DENALI_PHY_288_READ_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_288_WRITE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_288__PHY_RDLVL_PERIODIC_OBS_SELECT_1_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_288__PHY_RDLVL_PERIODIC_OBS_SELECT_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_288__PHY_RDLVL_PERIODIC_OBS_SELECT_1_WIDTH 8U +#define LPDDR4__PHY_RDLVL_PERIODIC_OBS_SELECT_1__REG DENALI_PHY_288 +#define LPDDR4__PHY_RDLVL_PERIODIC_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_288__PHY_RDLVL_PERIODIC_OBS_SELECT_1 + +#define LPDDR4__DENALI_PHY_288__PHY_RDLVL_DATA_MASK_1_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_288__PHY_RDLVL_DATA_MASK_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_288__PHY_RDLVL_DATA_MASK_1_WIDTH 8U +#define LPDDR4__PHY_RDLVL_DATA_MASK_1__REG DENALI_PHY_288 +#define LPDDR4__PHY_RDLVL_DATA_MASK_1__FLD LPDDR4__DENALI_PHY_288__PHY_RDLVL_DATA_MASK_1 + +#define LPDDR4__DENALI_PHY_288__PHY_WDQLVL_CLK_JITTER_TOLERANCE_1_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_288__PHY_WDQLVL_CLK_JITTER_TOLERANCE_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_288__PHY_WDQLVL_CLK_JITTER_TOLERANCE_1_WIDTH 8U +#define LPDDR4__PHY_WDQLVL_CLK_JITTER_TOLERANCE_1__REG DENALI_PHY_288 +#define LPDDR4__PHY_WDQLVL_CLK_JITTER_TOLERANCE_1__FLD LPDDR4__DENALI_PHY_288__PHY_WDQLVL_CLK_JITTER_TOLERANCE_1 + +#define LPDDR4__DENALI_PHY_288__PHY_WDQLVL_BURST_CNT_1_MASK 0x3F000000U +#define LPDDR4__DENALI_PHY_288__PHY_WDQLVL_BURST_CNT_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_288__PHY_WDQLVL_BURST_CNT_1_WIDTH 6U +#define LPDDR4__PHY_WDQLVL_BURST_CNT_1__REG DENALI_PHY_288 +#define LPDDR4__PHY_WDQLVL_BURST_CNT_1__FLD LPDDR4__DENALI_PHY_288__PHY_WDQLVL_BURST_CNT_1 + +#define LPDDR4__DENALI_PHY_289_READ_MASK 0x0F07FF07U +#define LPDDR4__DENALI_PHY_289_WRITE_MASK 0x0F07FF07U +#define LPDDR4__DENALI_PHY_289__PHY_WDQLVL_PATT_1_MASK 0x00000007U +#define LPDDR4__DENALI_PHY_289__PHY_WDQLVL_PATT_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_289__PHY_WDQLVL_PATT_1_WIDTH 3U +#define LPDDR4__PHY_WDQLVL_PATT_1__REG DENALI_PHY_289 +#define LPDDR4__PHY_WDQLVL_PATT_1__FLD LPDDR4__DENALI_PHY_289__PHY_WDQLVL_PATT_1 + +#define LPDDR4__DENALI_PHY_289__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_1_MASK 0x0007FF00U +#define LPDDR4__DENALI_PHY_289__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_289__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_1_WIDTH 11U +#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_1__REG DENALI_PHY_289 +#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_1__FLD LPDDR4__DENALI_PHY_289__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_1 + +#define LPDDR4__DENALI_PHY_289__PHY_WDQLVL_UPDT_WAIT_CNT_1_MASK 0x0F000000U +#define LPDDR4__DENALI_PHY_289__PHY_WDQLVL_UPDT_WAIT_CNT_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_289__PHY_WDQLVL_UPDT_WAIT_CNT_1_WIDTH 4U +#define LPDDR4__PHY_WDQLVL_UPDT_WAIT_CNT_1__REG DENALI_PHY_289 +#define LPDDR4__PHY_WDQLVL_UPDT_WAIT_CNT_1__FLD LPDDR4__DENALI_PHY_289__PHY_WDQLVL_UPDT_WAIT_CNT_1 + +#define LPDDR4__DENALI_PHY_290_READ_MASK 0x0000FF0FU +#define LPDDR4__DENALI_PHY_290_WRITE_MASK 0x0000FF0FU +#define LPDDR4__DENALI_PHY_290__PHY_WDQLVL_DQDM_OBS_SELECT_1_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_290__PHY_WDQLVL_DQDM_OBS_SELECT_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_290__PHY_WDQLVL_DQDM_OBS_SELECT_1_WIDTH 4U +#define LPDDR4__PHY_WDQLVL_DQDM_OBS_SELECT_1__REG DENALI_PHY_290 +#define LPDDR4__PHY_WDQLVL_DQDM_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_290__PHY_WDQLVL_DQDM_OBS_SELECT_1 + +#define LPDDR4__DENALI_PHY_290__PHY_WDQLVL_PERIODIC_OBS_SELECT_1_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_290__PHY_WDQLVL_PERIODIC_OBS_SELECT_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_290__PHY_WDQLVL_PERIODIC_OBS_SELECT_1_WIDTH 8U +#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_SELECT_1__REG DENALI_PHY_290 +#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_290__PHY_WDQLVL_PERIODIC_OBS_SELECT_1 + +#define LPDDR4__DENALI_PHY_290__SC_PHY_WDQLVL_CLR_PREV_RESULTS_1_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_290__SC_PHY_WDQLVL_CLR_PREV_RESULTS_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_290__SC_PHY_WDQLVL_CLR_PREV_RESULTS_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_290__SC_PHY_WDQLVL_CLR_PREV_RESULTS_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_290__SC_PHY_WDQLVL_CLR_PREV_RESULTS_1_WOSET 0U +#define LPDDR4__SC_PHY_WDQLVL_CLR_PREV_RESULTS_1__REG DENALI_PHY_290 +#define LPDDR4__SC_PHY_WDQLVL_CLR_PREV_RESULTS_1__FLD LPDDR4__DENALI_PHY_290__SC_PHY_WDQLVL_CLR_PREV_RESULTS_1 + +#define LPDDR4__DENALI_PHY_291_READ_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_291_WRITE_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_291__PHY_WDQLVL_DATADM_MASK_1_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_291__PHY_WDQLVL_DATADM_MASK_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_291__PHY_WDQLVL_DATADM_MASK_1_WIDTH 9U +#define LPDDR4__PHY_WDQLVL_DATADM_MASK_1__REG DENALI_PHY_291 +#define LPDDR4__PHY_WDQLVL_DATADM_MASK_1__FLD LPDDR4__DENALI_PHY_291__PHY_WDQLVL_DATADM_MASK_1 + +#define LPDDR4__DENALI_PHY_292_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_292_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_292__PHY_USER_PATT0_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_292__PHY_USER_PATT0_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_292__PHY_USER_PATT0_1_WIDTH 32U +#define LPDDR4__PHY_USER_PATT0_1__REG DENALI_PHY_292 +#define LPDDR4__PHY_USER_PATT0_1__FLD LPDDR4__DENALI_PHY_292__PHY_USER_PATT0_1 + +#define LPDDR4__DENALI_PHY_293_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_293_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_293__PHY_USER_PATT1_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_293__PHY_USER_PATT1_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_293__PHY_USER_PATT1_1_WIDTH 32U +#define LPDDR4__PHY_USER_PATT1_1__REG DENALI_PHY_293 +#define LPDDR4__PHY_USER_PATT1_1__FLD LPDDR4__DENALI_PHY_293__PHY_USER_PATT1_1 + +#define LPDDR4__DENALI_PHY_294_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_294_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_294__PHY_USER_PATT2_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_294__PHY_USER_PATT2_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_294__PHY_USER_PATT2_1_WIDTH 32U +#define LPDDR4__PHY_USER_PATT2_1__REG DENALI_PHY_294 +#define LPDDR4__PHY_USER_PATT2_1__FLD LPDDR4__DENALI_PHY_294__PHY_USER_PATT2_1 + +#define LPDDR4__DENALI_PHY_295_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_295_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_295__PHY_USER_PATT3_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_295__PHY_USER_PATT3_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_295__PHY_USER_PATT3_1_WIDTH 32U +#define LPDDR4__PHY_USER_PATT3_1__REG DENALI_PHY_295 +#define LPDDR4__PHY_USER_PATT3_1__FLD LPDDR4__DENALI_PHY_295__PHY_USER_PATT3_1 + +#define LPDDR4__DENALI_PHY_296_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PHY_296_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PHY_296__PHY_USER_PATT4_1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_296__PHY_USER_PATT4_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_296__PHY_USER_PATT4_1_WIDTH 16U +#define LPDDR4__PHY_USER_PATT4_1__REG DENALI_PHY_296 +#define LPDDR4__PHY_USER_PATT4_1__FLD LPDDR4__DENALI_PHY_296__PHY_USER_PATT4_1 + +#define LPDDR4__DENALI_PHY_296__PHY_NTP_MULT_TRAIN_1_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_296__PHY_NTP_MULT_TRAIN_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_296__PHY_NTP_MULT_TRAIN_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_296__PHY_NTP_MULT_TRAIN_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_296__PHY_NTP_MULT_TRAIN_1_WOSET 0U +#define LPDDR4__PHY_NTP_MULT_TRAIN_1__REG DENALI_PHY_296 +#define LPDDR4__PHY_NTP_MULT_TRAIN_1__FLD LPDDR4__DENALI_PHY_296__PHY_NTP_MULT_TRAIN_1 + +#define LPDDR4__DENALI_PHY_297_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_297_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_297__PHY_NTP_EARLY_THRESHOLD_1_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_297__PHY_NTP_EARLY_THRESHOLD_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_297__PHY_NTP_EARLY_THRESHOLD_1_WIDTH 10U +#define LPDDR4__PHY_NTP_EARLY_THRESHOLD_1__REG DENALI_PHY_297 +#define LPDDR4__PHY_NTP_EARLY_THRESHOLD_1__FLD LPDDR4__DENALI_PHY_297__PHY_NTP_EARLY_THRESHOLD_1 + +#define LPDDR4__DENALI_PHY_297__PHY_NTP_PERIOD_THRESHOLD_1_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_297__PHY_NTP_PERIOD_THRESHOLD_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_297__PHY_NTP_PERIOD_THRESHOLD_1_WIDTH 10U +#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_1__REG DENALI_PHY_297 +#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_1__FLD LPDDR4__DENALI_PHY_297__PHY_NTP_PERIOD_THRESHOLD_1 + +#define LPDDR4__DENALI_PHY_298_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_298_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_298__PHY_NTP_PERIOD_THRESHOLD_MIN_1_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_298__PHY_NTP_PERIOD_THRESHOLD_MIN_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_298__PHY_NTP_PERIOD_THRESHOLD_MIN_1_WIDTH 10U +#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MIN_1__REG DENALI_PHY_298 +#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MIN_1__FLD LPDDR4__DENALI_PHY_298__PHY_NTP_PERIOD_THRESHOLD_MIN_1 + +#define LPDDR4__DENALI_PHY_298__PHY_NTP_PERIOD_THRESHOLD_MAX_1_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_298__PHY_NTP_PERIOD_THRESHOLD_MAX_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_298__PHY_NTP_PERIOD_THRESHOLD_MAX_1_WIDTH 10U +#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MAX_1__REG DENALI_PHY_298 +#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MAX_1__FLD LPDDR4__DENALI_PHY_298__PHY_NTP_PERIOD_THRESHOLD_MAX_1 + +#define LPDDR4__DENALI_PHY_299_READ_MASK 0x00FF0001U +#define LPDDR4__DENALI_PHY_299_WRITE_MASK 0x00FF0001U +#define LPDDR4__DENALI_PHY_299__PHY_CALVL_VREF_DRIVING_SLICE_1_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_299__PHY_CALVL_VREF_DRIVING_SLICE_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_299__PHY_CALVL_VREF_DRIVING_SLICE_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_299__PHY_CALVL_VREF_DRIVING_SLICE_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_299__PHY_CALVL_VREF_DRIVING_SLICE_1_WOSET 0U +#define LPDDR4__PHY_CALVL_VREF_DRIVING_SLICE_1__REG DENALI_PHY_299 +#define LPDDR4__PHY_CALVL_VREF_DRIVING_SLICE_1__FLD LPDDR4__DENALI_PHY_299__PHY_CALVL_VREF_DRIVING_SLICE_1 + +#define LPDDR4__DENALI_PHY_299__SC_PHY_MANUAL_CLEAR_1_MASK 0x00003F00U +#define LPDDR4__DENALI_PHY_299__SC_PHY_MANUAL_CLEAR_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_299__SC_PHY_MANUAL_CLEAR_1_WIDTH 6U +#define LPDDR4__SC_PHY_MANUAL_CLEAR_1__REG DENALI_PHY_299 +#define LPDDR4__SC_PHY_MANUAL_CLEAR_1__FLD LPDDR4__DENALI_PHY_299__SC_PHY_MANUAL_CLEAR_1 + +#define LPDDR4__DENALI_PHY_299__PHY_FIFO_PTR_OBS_1_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_299__PHY_FIFO_PTR_OBS_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_299__PHY_FIFO_PTR_OBS_1_WIDTH 8U +#define LPDDR4__PHY_FIFO_PTR_OBS_1__REG DENALI_PHY_299 +#define LPDDR4__PHY_FIFO_PTR_OBS_1__FLD LPDDR4__DENALI_PHY_299__PHY_FIFO_PTR_OBS_1 + +#define LPDDR4__DENALI_PHY_300_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_300_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_300__PHY_LPBK_RESULT_OBS_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_300__PHY_LPBK_RESULT_OBS_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_300__PHY_LPBK_RESULT_OBS_1_WIDTH 32U +#define LPDDR4__PHY_LPBK_RESULT_OBS_1__REG DENALI_PHY_300 +#define LPDDR4__PHY_LPBK_RESULT_OBS_1__FLD LPDDR4__DENALI_PHY_300__PHY_LPBK_RESULT_OBS_1 + +#define LPDDR4__DENALI_PHY_301_READ_MASK 0x07FFFFFFU +#define LPDDR4__DENALI_PHY_301_WRITE_MASK 0x07FFFFFFU +#define LPDDR4__DENALI_PHY_301__PHY_LPBK_ERROR_COUNT_OBS_1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_301__PHY_LPBK_ERROR_COUNT_OBS_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_301__PHY_LPBK_ERROR_COUNT_OBS_1_WIDTH 16U +#define LPDDR4__PHY_LPBK_ERROR_COUNT_OBS_1__REG DENALI_PHY_301 +#define LPDDR4__PHY_LPBK_ERROR_COUNT_OBS_1__FLD LPDDR4__DENALI_PHY_301__PHY_LPBK_ERROR_COUNT_OBS_1 + +#define LPDDR4__DENALI_PHY_301__PHY_MASTER_DLY_LOCK_OBS_1_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_301__PHY_MASTER_DLY_LOCK_OBS_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_301__PHY_MASTER_DLY_LOCK_OBS_1_WIDTH 11U +#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_1__REG DENALI_PHY_301 +#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_1__FLD LPDDR4__DENALI_PHY_301__PHY_MASTER_DLY_LOCK_OBS_1 + +#define LPDDR4__DENALI_PHY_302_READ_MASK 0xFFFF7F7FU +#define LPDDR4__DENALI_PHY_302_WRITE_MASK 0xFFFF7F7FU +#define LPDDR4__DENALI_PHY_302__PHY_RDDQ_SLV_DLY_ENC_OBS_1_MASK 0x0000007FU +#define LPDDR4__DENALI_PHY_302__PHY_RDDQ_SLV_DLY_ENC_OBS_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_302__PHY_RDDQ_SLV_DLY_ENC_OBS_1_WIDTH 7U +#define LPDDR4__PHY_RDDQ_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_302 +#define LPDDR4__PHY_RDDQ_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_302__PHY_RDDQ_SLV_DLY_ENC_OBS_1 + +#define LPDDR4__DENALI_PHY_302__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_1_MASK 0x00007F00U +#define LPDDR4__DENALI_PHY_302__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_302__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_1_WIDTH 7U +#define LPDDR4__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_302 +#define LPDDR4__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_302__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_1 + +#define LPDDR4__DENALI_PHY_302__PHY_MEAS_DLY_STEP_VALUE_1_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_302__PHY_MEAS_DLY_STEP_VALUE_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_302__PHY_MEAS_DLY_STEP_VALUE_1_WIDTH 8U +#define LPDDR4__PHY_MEAS_DLY_STEP_VALUE_1__REG DENALI_PHY_302 +#define LPDDR4__PHY_MEAS_DLY_STEP_VALUE_1__FLD LPDDR4__DENALI_PHY_302__PHY_MEAS_DLY_STEP_VALUE_1 + +#define LPDDR4__DENALI_PHY_302__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_1_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_302__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_302__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_1_WIDTH 8U +#define LPDDR4__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_302 +#define LPDDR4__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_302__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_1 + +#define LPDDR4__DENALI_PHY_303_READ_MASK 0x7F07FFFFU +#define LPDDR4__DENALI_PHY_303_WRITE_MASK 0x7F07FFFFU +#define LPDDR4__DENALI_PHY_303__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_1_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_303__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_303__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_1_WIDTH 8U +#define LPDDR4__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_303 +#define LPDDR4__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_303__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_1 + +#define LPDDR4__DENALI_PHY_303__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_1_MASK 0x0007FF00U +#define LPDDR4__DENALI_PHY_303__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_303__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_1_WIDTH 11U +#define LPDDR4__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_303 +#define LPDDR4__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_303__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_1 + +#define LPDDR4__DENALI_PHY_303__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_1_MASK 0x7F000000U +#define LPDDR4__DENALI_PHY_303__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_303__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_1_WIDTH 7U +#define LPDDR4__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_303 +#define LPDDR4__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_303__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_1 + +#define LPDDR4__DENALI_PHY_304_READ_MASK 0x0007FFFFU +#define LPDDR4__DENALI_PHY_304_WRITE_MASK 0x0007FFFFU +#define LPDDR4__DENALI_PHY_304__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_1_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_304__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_304__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_1_WIDTH 8U +#define LPDDR4__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_304 +#define LPDDR4__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_304__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_1 + +#define LPDDR4__DENALI_PHY_304__PHY_WR_ADDER_SLV_DLY_ENC_OBS_1_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_304__PHY_WR_ADDER_SLV_DLY_ENC_OBS_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_304__PHY_WR_ADDER_SLV_DLY_ENC_OBS_1_WIDTH 8U +#define LPDDR4__PHY_WR_ADDER_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_304 +#define LPDDR4__PHY_WR_ADDER_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_304__PHY_WR_ADDER_SLV_DLY_ENC_OBS_1 + +#define LPDDR4__DENALI_PHY_304__PHY_WR_SHIFT_OBS_1_MASK 0x00070000U +#define LPDDR4__DENALI_PHY_304__PHY_WR_SHIFT_OBS_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_304__PHY_WR_SHIFT_OBS_1_WIDTH 3U +#define LPDDR4__PHY_WR_SHIFT_OBS_1__REG DENALI_PHY_304 +#define LPDDR4__PHY_WR_SHIFT_OBS_1__FLD LPDDR4__DENALI_PHY_304__PHY_WR_SHIFT_OBS_1 + +#define LPDDR4__DENALI_PHY_305_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_305_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_305__PHY_WRLVL_HARD0_DELAY_OBS_1_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_305__PHY_WRLVL_HARD0_DELAY_OBS_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_305__PHY_WRLVL_HARD0_DELAY_OBS_1_WIDTH 10U +#define LPDDR4__PHY_WRLVL_HARD0_DELAY_OBS_1__REG DENALI_PHY_305 +#define LPDDR4__PHY_WRLVL_HARD0_DELAY_OBS_1__FLD LPDDR4__DENALI_PHY_305__PHY_WRLVL_HARD0_DELAY_OBS_1 + +#define LPDDR4__DENALI_PHY_305__PHY_WRLVL_HARD1_DELAY_OBS_1_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_305__PHY_WRLVL_HARD1_DELAY_OBS_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_305__PHY_WRLVL_HARD1_DELAY_OBS_1_WIDTH 10U +#define LPDDR4__PHY_WRLVL_HARD1_DELAY_OBS_1__REG DENALI_PHY_305 +#define LPDDR4__PHY_WRLVL_HARD1_DELAY_OBS_1__FLD LPDDR4__DENALI_PHY_305__PHY_WRLVL_HARD1_DELAY_OBS_1 + +#define LPDDR4__DENALI_PHY_306_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PHY_306_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PHY_306__PHY_WRLVL_STATUS_OBS_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PHY_306__PHY_WRLVL_STATUS_OBS_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_306__PHY_WRLVL_STATUS_OBS_1_WIDTH 17U +#define LPDDR4__PHY_WRLVL_STATUS_OBS_1__REG DENALI_PHY_306 +#define LPDDR4__PHY_WRLVL_STATUS_OBS_1__FLD LPDDR4__DENALI_PHY_306__PHY_WRLVL_STATUS_OBS_1 + +#define LPDDR4__DENALI_PHY_307_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_307_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_307__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_1_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_307__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_307__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_1_WIDTH 10U +#define LPDDR4__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_307 +#define LPDDR4__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_307__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_1 + +#define LPDDR4__DENALI_PHY_307__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_1_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_307__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_307__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_1_WIDTH 10U +#define LPDDR4__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_307 +#define LPDDR4__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_307__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_1 + +#define LPDDR4__DENALI_PHY_308_READ_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_308_WRITE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_308__PHY_WRLVL_ERROR_OBS_1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_308__PHY_WRLVL_ERROR_OBS_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_308__PHY_WRLVL_ERROR_OBS_1_WIDTH 16U +#define LPDDR4__PHY_WRLVL_ERROR_OBS_1__REG DENALI_PHY_308 +#define LPDDR4__PHY_WRLVL_ERROR_OBS_1__FLD LPDDR4__DENALI_PHY_308__PHY_WRLVL_ERROR_OBS_1 + +#define LPDDR4__DENALI_PHY_308__PHY_GTLVL_HARD0_DELAY_OBS_1_MASK 0x3FFF0000U +#define LPDDR4__DENALI_PHY_308__PHY_GTLVL_HARD0_DELAY_OBS_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_308__PHY_GTLVL_HARD0_DELAY_OBS_1_WIDTH 14U +#define LPDDR4__PHY_GTLVL_HARD0_DELAY_OBS_1__REG DENALI_PHY_308 +#define LPDDR4__PHY_GTLVL_HARD0_DELAY_OBS_1__FLD LPDDR4__DENALI_PHY_308__PHY_GTLVL_HARD0_DELAY_OBS_1 + +#define LPDDR4__DENALI_PHY_309_READ_MASK 0x00003FFFU +#define LPDDR4__DENALI_PHY_309_WRITE_MASK 0x00003FFFU +#define LPDDR4__DENALI_PHY_309__PHY_GTLVL_HARD1_DELAY_OBS_1_MASK 0x00003FFFU +#define LPDDR4__DENALI_PHY_309__PHY_GTLVL_HARD1_DELAY_OBS_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_309__PHY_GTLVL_HARD1_DELAY_OBS_1_WIDTH 14U +#define LPDDR4__PHY_GTLVL_HARD1_DELAY_OBS_1__REG DENALI_PHY_309 +#define LPDDR4__PHY_GTLVL_HARD1_DELAY_OBS_1__FLD LPDDR4__DENALI_PHY_309__PHY_GTLVL_HARD1_DELAY_OBS_1 + +#define LPDDR4__DENALI_PHY_310_READ_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_310_WRITE_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_310__PHY_GTLVL_STATUS_OBS_1_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_310__PHY_GTLVL_STATUS_OBS_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_310__PHY_GTLVL_STATUS_OBS_1_WIDTH 18U +#define LPDDR4__PHY_GTLVL_STATUS_OBS_1__REG DENALI_PHY_310 +#define LPDDR4__PHY_GTLVL_STATUS_OBS_1__FLD LPDDR4__DENALI_PHY_310__PHY_GTLVL_STATUS_OBS_1 + +#define LPDDR4__DENALI_PHY_311_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_311_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_311__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_1_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_311__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_311__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_1_WIDTH 10U +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_1__REG DENALI_PHY_311 +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_1__FLD LPDDR4__DENALI_PHY_311__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_1 + +#define LPDDR4__DENALI_PHY_311__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_1_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_311__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_311__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_1_WIDTH 10U +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_1__REG DENALI_PHY_311 +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_1__FLD LPDDR4__DENALI_PHY_311__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_1 + +#define LPDDR4__DENALI_PHY_312_READ_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_312_WRITE_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_312__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_1_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_312__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_312__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_1_WIDTH 2U +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_1__REG DENALI_PHY_312 +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_1__FLD LPDDR4__DENALI_PHY_312__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_1 + +#define LPDDR4__DENALI_PHY_313_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_313_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_313__PHY_RDLVL_STATUS_OBS_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_313__PHY_RDLVL_STATUS_OBS_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_313__PHY_RDLVL_STATUS_OBS_1_WIDTH 32U +#define LPDDR4__PHY_RDLVL_STATUS_OBS_1__REG DENALI_PHY_313 +#define LPDDR4__PHY_RDLVL_STATUS_OBS_1__FLD LPDDR4__DENALI_PHY_313__PHY_RDLVL_STATUS_OBS_1 + +#define LPDDR4__DENALI_PHY_314_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_314_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_314__PHY_RDLVL_PERIODIC_OBS_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_314__PHY_RDLVL_PERIODIC_OBS_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_314__PHY_RDLVL_PERIODIC_OBS_1_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PERIODIC_OBS_1__REG DENALI_PHY_314 +#define LPDDR4__PHY_RDLVL_PERIODIC_OBS_1__FLD LPDDR4__DENALI_PHY_314__PHY_RDLVL_PERIODIC_OBS_1 + +#define LPDDR4__DENALI_PHY_315_READ_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_315_WRITE_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_315__PHY_WDQLVL_DQDM_LE_DLY_OBS_1_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_315__PHY_WDQLVL_DQDM_LE_DLY_OBS_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_315__PHY_WDQLVL_DQDM_LE_DLY_OBS_1_WIDTH 11U +#define LPDDR4__PHY_WDQLVL_DQDM_LE_DLY_OBS_1__REG DENALI_PHY_315 +#define LPDDR4__PHY_WDQLVL_DQDM_LE_DLY_OBS_1__FLD LPDDR4__DENALI_PHY_315__PHY_WDQLVL_DQDM_LE_DLY_OBS_1 + +#define LPDDR4__DENALI_PHY_315__PHY_WDQLVL_DQDM_TE_DLY_OBS_1_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_315__PHY_WDQLVL_DQDM_TE_DLY_OBS_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_315__PHY_WDQLVL_DQDM_TE_DLY_OBS_1_WIDTH 11U +#define LPDDR4__PHY_WDQLVL_DQDM_TE_DLY_OBS_1__REG DENALI_PHY_315 +#define LPDDR4__PHY_WDQLVL_DQDM_TE_DLY_OBS_1__FLD LPDDR4__DENALI_PHY_315__PHY_WDQLVL_DQDM_TE_DLY_OBS_1 + +#define LPDDR4__DENALI_PHY_316_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_316_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_316__PHY_WDQLVL_STATUS_OBS_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_316__PHY_WDQLVL_STATUS_OBS_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_316__PHY_WDQLVL_STATUS_OBS_1_WIDTH 32U +#define LPDDR4__PHY_WDQLVL_STATUS_OBS_1__REG DENALI_PHY_316 +#define LPDDR4__PHY_WDQLVL_STATUS_OBS_1__FLD LPDDR4__DENALI_PHY_316__PHY_WDQLVL_STATUS_OBS_1 + +#define LPDDR4__DENALI_PHY_317_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_317_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_317__PHY_WDQLVL_PERIODIC_OBS_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_317__PHY_WDQLVL_PERIODIC_OBS_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_317__PHY_WDQLVL_PERIODIC_OBS_1_WIDTH 32U +#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_1__REG DENALI_PHY_317 +#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_1__FLD LPDDR4__DENALI_PHY_317__PHY_WDQLVL_PERIODIC_OBS_1 + +#define LPDDR4__DENALI_PHY_318_READ_MASK 0x7FFFFFFFU +#define LPDDR4__DENALI_PHY_318_WRITE_MASK 0x7FFFFFFFU +#define LPDDR4__DENALI_PHY_318__PHY_DDL_MODE_1_MASK 0x7FFFFFFFU +#define LPDDR4__DENALI_PHY_318__PHY_DDL_MODE_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_318__PHY_DDL_MODE_1_WIDTH 31U +#define LPDDR4__PHY_DDL_MODE_1__REG DENALI_PHY_318 +#define LPDDR4__PHY_DDL_MODE_1__FLD LPDDR4__DENALI_PHY_318__PHY_DDL_MODE_1 + +#define LPDDR4__DENALI_PHY_319_READ_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_319_WRITE_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_319__PHY_DDL_MASK_1_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_319__PHY_DDL_MASK_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_319__PHY_DDL_MASK_1_WIDTH 6U +#define LPDDR4__PHY_DDL_MASK_1__REG DENALI_PHY_319 +#define LPDDR4__PHY_DDL_MASK_1__FLD LPDDR4__DENALI_PHY_319__PHY_DDL_MASK_1 + +#define LPDDR4__DENALI_PHY_320_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_320_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_320__PHY_DDL_TEST_OBS_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_320__PHY_DDL_TEST_OBS_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_320__PHY_DDL_TEST_OBS_1_WIDTH 32U +#define LPDDR4__PHY_DDL_TEST_OBS_1__REG DENALI_PHY_320 +#define LPDDR4__PHY_DDL_TEST_OBS_1__FLD LPDDR4__DENALI_PHY_320__PHY_DDL_TEST_OBS_1 + +#define LPDDR4__DENALI_PHY_321_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_321_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_321__PHY_DDL_TEST_MSTR_DLY_OBS_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_321__PHY_DDL_TEST_MSTR_DLY_OBS_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_321__PHY_DDL_TEST_MSTR_DLY_OBS_1_WIDTH 32U +#define LPDDR4__PHY_DDL_TEST_MSTR_DLY_OBS_1__REG DENALI_PHY_321 +#define LPDDR4__PHY_DDL_TEST_MSTR_DLY_OBS_1__FLD LPDDR4__DENALI_PHY_321__PHY_DDL_TEST_MSTR_DLY_OBS_1 + +#define LPDDR4__DENALI_PHY_322_READ_MASK 0x010001FFU +#define LPDDR4__DENALI_PHY_322_WRITE_MASK 0x010001FFU +#define LPDDR4__DENALI_PHY_322__PHY_DDL_TRACK_UPD_THRESHOLD_1_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_322__PHY_DDL_TRACK_UPD_THRESHOLD_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_322__PHY_DDL_TRACK_UPD_THRESHOLD_1_WIDTH 8U +#define LPDDR4__PHY_DDL_TRACK_UPD_THRESHOLD_1__REG DENALI_PHY_322 +#define LPDDR4__PHY_DDL_TRACK_UPD_THRESHOLD_1__FLD LPDDR4__DENALI_PHY_322__PHY_DDL_TRACK_UPD_THRESHOLD_1 + +#define LPDDR4__DENALI_PHY_322__PHY_LP4_WDQS_OE_EXTEND_1_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_322__PHY_LP4_WDQS_OE_EXTEND_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_322__PHY_LP4_WDQS_OE_EXTEND_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_322__PHY_LP4_WDQS_OE_EXTEND_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_322__PHY_LP4_WDQS_OE_EXTEND_1_WOSET 0U +#define LPDDR4__PHY_LP4_WDQS_OE_EXTEND_1__REG DENALI_PHY_322 +#define LPDDR4__PHY_LP4_WDQS_OE_EXTEND_1__FLD LPDDR4__DENALI_PHY_322__PHY_LP4_WDQS_OE_EXTEND_1 + +#define LPDDR4__DENALI_PHY_322__SC_PHY_RX_CAL_START_1_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_322__SC_PHY_RX_CAL_START_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_322__SC_PHY_RX_CAL_START_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_322__SC_PHY_RX_CAL_START_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_322__SC_PHY_RX_CAL_START_1_WOSET 0U +#define LPDDR4__SC_PHY_RX_CAL_START_1__REG DENALI_PHY_322 +#define LPDDR4__SC_PHY_RX_CAL_START_1__FLD LPDDR4__DENALI_PHY_322__SC_PHY_RX_CAL_START_1 + +#define LPDDR4__DENALI_PHY_322__PHY_RX_CAL_OVERRIDE_1_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_322__PHY_RX_CAL_OVERRIDE_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_322__PHY_RX_CAL_OVERRIDE_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_322__PHY_RX_CAL_OVERRIDE_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_322__PHY_RX_CAL_OVERRIDE_1_WOSET 0U +#define LPDDR4__PHY_RX_CAL_OVERRIDE_1__REG DENALI_PHY_322 +#define LPDDR4__PHY_RX_CAL_OVERRIDE_1__FLD LPDDR4__DENALI_PHY_322__PHY_RX_CAL_OVERRIDE_1 + +#define LPDDR4__DENALI_PHY_323_READ_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_323_WRITE_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_323__PHY_RX_CAL_SAMPLE_WAIT_1_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_323__PHY_RX_CAL_SAMPLE_WAIT_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_323__PHY_RX_CAL_SAMPLE_WAIT_1_WIDTH 8U +#define LPDDR4__PHY_RX_CAL_SAMPLE_WAIT_1__REG DENALI_PHY_323 +#define LPDDR4__PHY_RX_CAL_SAMPLE_WAIT_1__FLD LPDDR4__DENALI_PHY_323__PHY_RX_CAL_SAMPLE_WAIT_1 + +#define LPDDR4__DENALI_PHY_323__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_1_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_323__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_323__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_323__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_323__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_1_WOSET 0U +#define LPDDR4__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_1__REG DENALI_PHY_323 +#define LPDDR4__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_1__FLD LPDDR4__DENALI_PHY_323__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_1 + +#define LPDDR4__DENALI_PHY_323__PHY_RX_CAL_DQ0_1_MASK 0x01FF0000U +#define LPDDR4__DENALI_PHY_323__PHY_RX_CAL_DQ0_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_323__PHY_RX_CAL_DQ0_1_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQ0_1__REG DENALI_PHY_323 +#define LPDDR4__PHY_RX_CAL_DQ0_1__FLD LPDDR4__DENALI_PHY_323__PHY_RX_CAL_DQ0_1 + +#define LPDDR4__DENALI_PHY_324_READ_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_324_WRITE_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_324__PHY_RX_CAL_DQ1_1_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_324__PHY_RX_CAL_DQ1_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_324__PHY_RX_CAL_DQ1_1_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQ1_1__REG DENALI_PHY_324 +#define LPDDR4__PHY_RX_CAL_DQ1_1__FLD LPDDR4__DENALI_PHY_324__PHY_RX_CAL_DQ1_1 + +#define LPDDR4__DENALI_PHY_324__PHY_RX_CAL_DQ2_1_MASK 0x01FF0000U +#define LPDDR4__DENALI_PHY_324__PHY_RX_CAL_DQ2_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_324__PHY_RX_CAL_DQ2_1_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQ2_1__REG DENALI_PHY_324 +#define LPDDR4__PHY_RX_CAL_DQ2_1__FLD LPDDR4__DENALI_PHY_324__PHY_RX_CAL_DQ2_1 + +#define LPDDR4__DENALI_PHY_325_READ_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_325_WRITE_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_325__PHY_RX_CAL_DQ3_1_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_325__PHY_RX_CAL_DQ3_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_325__PHY_RX_CAL_DQ3_1_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQ3_1__REG DENALI_PHY_325 +#define LPDDR4__PHY_RX_CAL_DQ3_1__FLD LPDDR4__DENALI_PHY_325__PHY_RX_CAL_DQ3_1 + +#define LPDDR4__DENALI_PHY_325__PHY_RX_CAL_DQ4_1_MASK 0x01FF0000U +#define LPDDR4__DENALI_PHY_325__PHY_RX_CAL_DQ4_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_325__PHY_RX_CAL_DQ4_1_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQ4_1__REG DENALI_PHY_325 +#define LPDDR4__PHY_RX_CAL_DQ4_1__FLD LPDDR4__DENALI_PHY_325__PHY_RX_CAL_DQ4_1 + +#define LPDDR4__DENALI_PHY_326_READ_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_326_WRITE_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_326__PHY_RX_CAL_DQ5_1_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_326__PHY_RX_CAL_DQ5_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_326__PHY_RX_CAL_DQ5_1_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQ5_1__REG DENALI_PHY_326 +#define LPDDR4__PHY_RX_CAL_DQ5_1__FLD LPDDR4__DENALI_PHY_326__PHY_RX_CAL_DQ5_1 + +#define LPDDR4__DENALI_PHY_326__PHY_RX_CAL_DQ6_1_MASK 0x01FF0000U +#define LPDDR4__DENALI_PHY_326__PHY_RX_CAL_DQ6_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_326__PHY_RX_CAL_DQ6_1_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQ6_1__REG DENALI_PHY_326 +#define LPDDR4__PHY_RX_CAL_DQ6_1__FLD LPDDR4__DENALI_PHY_326__PHY_RX_CAL_DQ6_1 + +#define LPDDR4__DENALI_PHY_327_READ_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_327_WRITE_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_327__PHY_RX_CAL_DQ7_1_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_327__PHY_RX_CAL_DQ7_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_327__PHY_RX_CAL_DQ7_1_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQ7_1__REG DENALI_PHY_327 +#define LPDDR4__PHY_RX_CAL_DQ7_1__FLD LPDDR4__DENALI_PHY_327__PHY_RX_CAL_DQ7_1 + +#define LPDDR4__DENALI_PHY_328_READ_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_328_WRITE_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_328__PHY_RX_CAL_DM_1_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_328__PHY_RX_CAL_DM_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_328__PHY_RX_CAL_DM_1_WIDTH 18U +#define LPDDR4__PHY_RX_CAL_DM_1__REG DENALI_PHY_328 +#define LPDDR4__PHY_RX_CAL_DM_1__FLD LPDDR4__DENALI_PHY_328__PHY_RX_CAL_DM_1 + +#define LPDDR4__DENALI_PHY_329_READ_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_329_WRITE_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_329__PHY_RX_CAL_DQS_1_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_329__PHY_RX_CAL_DQS_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_329__PHY_RX_CAL_DQS_1_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQS_1__REG DENALI_PHY_329 +#define LPDDR4__PHY_RX_CAL_DQS_1__FLD LPDDR4__DENALI_PHY_329__PHY_RX_CAL_DQS_1 + +#define LPDDR4__DENALI_PHY_329__PHY_RX_CAL_FDBK_1_MASK 0x01FF0000U +#define LPDDR4__DENALI_PHY_329__PHY_RX_CAL_FDBK_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_329__PHY_RX_CAL_FDBK_1_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_FDBK_1__REG DENALI_PHY_329 +#define LPDDR4__PHY_RX_CAL_FDBK_1__FLD LPDDR4__DENALI_PHY_329__PHY_RX_CAL_FDBK_1 + +#define LPDDR4__DENALI_PHY_330_READ_MASK 0x01FF07FFU +#define LPDDR4__DENALI_PHY_330_WRITE_MASK 0x01FF07FFU +#define LPDDR4__DENALI_PHY_330__PHY_RX_CAL_OBS_1_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_330__PHY_RX_CAL_OBS_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_330__PHY_RX_CAL_OBS_1_WIDTH 11U +#define LPDDR4__PHY_RX_CAL_OBS_1__REG DENALI_PHY_330 +#define LPDDR4__PHY_RX_CAL_OBS_1__FLD LPDDR4__DENALI_PHY_330__PHY_RX_CAL_OBS_1 + +#define LPDDR4__DENALI_PHY_330__PHY_RX_CAL_LOCK_OBS_1_MASK 0x01FF0000U +#define LPDDR4__DENALI_PHY_330__PHY_RX_CAL_LOCK_OBS_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_330__PHY_RX_CAL_LOCK_OBS_1_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_LOCK_OBS_1__REG DENALI_PHY_330 +#define LPDDR4__PHY_RX_CAL_LOCK_OBS_1__FLD LPDDR4__DENALI_PHY_330__PHY_RX_CAL_LOCK_OBS_1 + +#define LPDDR4__DENALI_PHY_331_READ_MASK 0x017F7F01U +#define LPDDR4__DENALI_PHY_331_WRITE_MASK 0x017F7F01U +#define LPDDR4__DENALI_PHY_331__PHY_RX_CAL_DISABLE_1_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_331__PHY_RX_CAL_DISABLE_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_331__PHY_RX_CAL_DISABLE_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_331__PHY_RX_CAL_DISABLE_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_331__PHY_RX_CAL_DISABLE_1_WOSET 0U +#define LPDDR4__PHY_RX_CAL_DISABLE_1__REG DENALI_PHY_331 +#define LPDDR4__PHY_RX_CAL_DISABLE_1__FLD LPDDR4__DENALI_PHY_331__PHY_RX_CAL_DISABLE_1 + +#define LPDDR4__DENALI_PHY_331__PHY_RX_CAL_SE_ADJUST_1_MASK 0x00007F00U +#define LPDDR4__DENALI_PHY_331__PHY_RX_CAL_SE_ADJUST_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_331__PHY_RX_CAL_SE_ADJUST_1_WIDTH 7U +#define LPDDR4__PHY_RX_CAL_SE_ADJUST_1__REG DENALI_PHY_331 +#define LPDDR4__PHY_RX_CAL_SE_ADJUST_1__FLD LPDDR4__DENALI_PHY_331__PHY_RX_CAL_SE_ADJUST_1 + +#define LPDDR4__DENALI_PHY_331__PHY_RX_CAL_DIFF_ADJUST_1_MASK 0x007F0000U +#define LPDDR4__DENALI_PHY_331__PHY_RX_CAL_DIFF_ADJUST_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_331__PHY_RX_CAL_DIFF_ADJUST_1_WIDTH 7U +#define LPDDR4__PHY_RX_CAL_DIFF_ADJUST_1__REG DENALI_PHY_331 +#define LPDDR4__PHY_RX_CAL_DIFF_ADJUST_1__FLD LPDDR4__DENALI_PHY_331__PHY_RX_CAL_DIFF_ADJUST_1 + +#define LPDDR4__DENALI_PHY_331__PHY_RX_CAL_COMP_VAL_1_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_331__PHY_RX_CAL_COMP_VAL_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_331__PHY_RX_CAL_COMP_VAL_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_331__PHY_RX_CAL_COMP_VAL_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_331__PHY_RX_CAL_COMP_VAL_1_WOSET 0U +#define LPDDR4__PHY_RX_CAL_COMP_VAL_1__REG DENALI_PHY_331 +#define LPDDR4__PHY_RX_CAL_COMP_VAL_1__FLD LPDDR4__DENALI_PHY_331__PHY_RX_CAL_COMP_VAL_1 + +#define LPDDR4__DENALI_PHY_332_READ_MASK 0x07FF0FFFU +#define LPDDR4__DENALI_PHY_332_WRITE_MASK 0x07FF0FFFU +#define LPDDR4__DENALI_PHY_332__PHY_RX_CAL_INDEX_MASK_1_MASK 0x00000FFFU +#define LPDDR4__DENALI_PHY_332__PHY_RX_CAL_INDEX_MASK_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_332__PHY_RX_CAL_INDEX_MASK_1_WIDTH 12U +#define LPDDR4__PHY_RX_CAL_INDEX_MASK_1__REG DENALI_PHY_332 +#define LPDDR4__PHY_RX_CAL_INDEX_MASK_1__FLD LPDDR4__DENALI_PHY_332__PHY_RX_CAL_INDEX_MASK_1 + +#define LPDDR4__DENALI_PHY_332__PHY_PAD_RX_BIAS_EN_1_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_332__PHY_PAD_RX_BIAS_EN_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_332__PHY_PAD_RX_BIAS_EN_1_WIDTH 11U +#define LPDDR4__PHY_PAD_RX_BIAS_EN_1__REG DENALI_PHY_332 +#define LPDDR4__PHY_PAD_RX_BIAS_EN_1__FLD LPDDR4__DENALI_PHY_332__PHY_PAD_RX_BIAS_EN_1 + +#define LPDDR4__DENALI_PHY_333_READ_MASK 0x03FFFF1FU +#define LPDDR4__DENALI_PHY_333_WRITE_MASK 0x03FFFF1FU +#define LPDDR4__DENALI_PHY_333__PHY_STATIC_TOG_DISABLE_1_MASK 0x0000001FU +#define LPDDR4__DENALI_PHY_333__PHY_STATIC_TOG_DISABLE_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_333__PHY_STATIC_TOG_DISABLE_1_WIDTH 5U +#define LPDDR4__PHY_STATIC_TOG_DISABLE_1__REG DENALI_PHY_333 +#define LPDDR4__PHY_STATIC_TOG_DISABLE_1__FLD LPDDR4__DENALI_PHY_333__PHY_STATIC_TOG_DISABLE_1 + +#define LPDDR4__DENALI_PHY_333__PHY_DATA_DC_CAL_SAMPLE_WAIT_1_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_333__PHY_DATA_DC_CAL_SAMPLE_WAIT_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_333__PHY_DATA_DC_CAL_SAMPLE_WAIT_1_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_CAL_SAMPLE_WAIT_1__REG DENALI_PHY_333 +#define LPDDR4__PHY_DATA_DC_CAL_SAMPLE_WAIT_1__FLD LPDDR4__DENALI_PHY_333__PHY_DATA_DC_CAL_SAMPLE_WAIT_1 + +#define LPDDR4__DENALI_PHY_333__PHY_DATA_DC_CAL_TIMEOUT_1_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_333__PHY_DATA_DC_CAL_TIMEOUT_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_333__PHY_DATA_DC_CAL_TIMEOUT_1_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_CAL_TIMEOUT_1__REG DENALI_PHY_333 +#define LPDDR4__PHY_DATA_DC_CAL_TIMEOUT_1__FLD LPDDR4__DENALI_PHY_333__PHY_DATA_DC_CAL_TIMEOUT_1 + +#define LPDDR4__DENALI_PHY_333__PHY_DATA_DC_WEIGHT_1_MASK 0x03000000U +#define LPDDR4__DENALI_PHY_333__PHY_DATA_DC_WEIGHT_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_333__PHY_DATA_DC_WEIGHT_1_WIDTH 2U +#define LPDDR4__PHY_DATA_DC_WEIGHT_1__REG DENALI_PHY_333 +#define LPDDR4__PHY_DATA_DC_WEIGHT_1__FLD LPDDR4__DENALI_PHY_333__PHY_DATA_DC_WEIGHT_1 + +#define LPDDR4__DENALI_PHY_334_READ_MASK 0x01FFFF3FU +#define LPDDR4__DENALI_PHY_334_WRITE_MASK 0x01FFFF3FU +#define LPDDR4__DENALI_PHY_334__PHY_DATA_DC_ADJUST_START_1_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_334__PHY_DATA_DC_ADJUST_START_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_334__PHY_DATA_DC_ADJUST_START_1_WIDTH 6U +#define LPDDR4__PHY_DATA_DC_ADJUST_START_1__REG DENALI_PHY_334 +#define LPDDR4__PHY_DATA_DC_ADJUST_START_1__FLD LPDDR4__DENALI_PHY_334__PHY_DATA_DC_ADJUST_START_1 + +#define LPDDR4__DENALI_PHY_334__PHY_DATA_DC_ADJUST_SAMPLE_CNT_1_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_334__PHY_DATA_DC_ADJUST_SAMPLE_CNT_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_334__PHY_DATA_DC_ADJUST_SAMPLE_CNT_1_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_ADJUST_SAMPLE_CNT_1__REG DENALI_PHY_334 +#define LPDDR4__PHY_DATA_DC_ADJUST_SAMPLE_CNT_1__FLD LPDDR4__DENALI_PHY_334__PHY_DATA_DC_ADJUST_SAMPLE_CNT_1 + +#define LPDDR4__DENALI_PHY_334__PHY_DATA_DC_ADJUST_THRSHLD_1_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_334__PHY_DATA_DC_ADJUST_THRSHLD_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_334__PHY_DATA_DC_ADJUST_THRSHLD_1_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_ADJUST_THRSHLD_1__REG DENALI_PHY_334 +#define LPDDR4__PHY_DATA_DC_ADJUST_THRSHLD_1__FLD LPDDR4__DENALI_PHY_334__PHY_DATA_DC_ADJUST_THRSHLD_1 + +#define LPDDR4__DENALI_PHY_334__PHY_DATA_DC_ADJUST_DIRECT_1_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_334__PHY_DATA_DC_ADJUST_DIRECT_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_334__PHY_DATA_DC_ADJUST_DIRECT_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_334__PHY_DATA_DC_ADJUST_DIRECT_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_334__PHY_DATA_DC_ADJUST_DIRECT_1_WOSET 0U +#define LPDDR4__PHY_DATA_DC_ADJUST_DIRECT_1__REG DENALI_PHY_334 +#define LPDDR4__PHY_DATA_DC_ADJUST_DIRECT_1__FLD LPDDR4__DENALI_PHY_334__PHY_DATA_DC_ADJUST_DIRECT_1 + +#define LPDDR4__DENALI_PHY_335_READ_MASK 0x07030101U +#define LPDDR4__DENALI_PHY_335_WRITE_MASK 0x07030101U +#define LPDDR4__DENALI_PHY_335__PHY_DATA_DC_CAL_POLARITY_1_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_335__PHY_DATA_DC_CAL_POLARITY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_335__PHY_DATA_DC_CAL_POLARITY_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_335__PHY_DATA_DC_CAL_POLARITY_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_335__PHY_DATA_DC_CAL_POLARITY_1_WOSET 0U +#define LPDDR4__PHY_DATA_DC_CAL_POLARITY_1__REG DENALI_PHY_335 +#define LPDDR4__PHY_DATA_DC_CAL_POLARITY_1__FLD LPDDR4__DENALI_PHY_335__PHY_DATA_DC_CAL_POLARITY_1 + +#define LPDDR4__DENALI_PHY_335__PHY_DATA_DC_CAL_START_1_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_335__PHY_DATA_DC_CAL_START_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_335__PHY_DATA_DC_CAL_START_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_335__PHY_DATA_DC_CAL_START_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_335__PHY_DATA_DC_CAL_START_1_WOSET 0U +#define LPDDR4__PHY_DATA_DC_CAL_START_1__REG DENALI_PHY_335 +#define LPDDR4__PHY_DATA_DC_CAL_START_1__FLD LPDDR4__DENALI_PHY_335__PHY_DATA_DC_CAL_START_1 + +#define LPDDR4__DENALI_PHY_335__PHY_DATA_DC_SW_RANK_1_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_335__PHY_DATA_DC_SW_RANK_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_335__PHY_DATA_DC_SW_RANK_1_WIDTH 2U +#define LPDDR4__PHY_DATA_DC_SW_RANK_1__REG DENALI_PHY_335 +#define LPDDR4__PHY_DATA_DC_SW_RANK_1__FLD LPDDR4__DENALI_PHY_335__PHY_DATA_DC_SW_RANK_1 + +#define LPDDR4__DENALI_PHY_335__PHY_FDBK_PWR_CTRL_1_MASK 0x07000000U +#define LPDDR4__DENALI_PHY_335__PHY_FDBK_PWR_CTRL_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_335__PHY_FDBK_PWR_CTRL_1_WIDTH 3U +#define LPDDR4__PHY_FDBK_PWR_CTRL_1__REG DENALI_PHY_335 +#define LPDDR4__PHY_FDBK_PWR_CTRL_1__FLD LPDDR4__DENALI_PHY_335__PHY_FDBK_PWR_CTRL_1 + +#define LPDDR4__DENALI_PHY_336_READ_MASK 0x01010101U +#define LPDDR4__DENALI_PHY_336_WRITE_MASK 0x01010101U +#define LPDDR4__DENALI_PHY_336__PHY_SLV_DLY_CTRL_GATE_DISABLE_1_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_336__PHY_SLV_DLY_CTRL_GATE_DISABLE_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_336__PHY_SLV_DLY_CTRL_GATE_DISABLE_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_336__PHY_SLV_DLY_CTRL_GATE_DISABLE_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_336__PHY_SLV_DLY_CTRL_GATE_DISABLE_1_WOSET 0U +#define LPDDR4__PHY_SLV_DLY_CTRL_GATE_DISABLE_1__REG DENALI_PHY_336 +#define LPDDR4__PHY_SLV_DLY_CTRL_GATE_DISABLE_1__FLD LPDDR4__DENALI_PHY_336__PHY_SLV_DLY_CTRL_GATE_DISABLE_1 + +#define LPDDR4__DENALI_PHY_336__PHY_RDPATH_GATE_DISABLE_1_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_336__PHY_RDPATH_GATE_DISABLE_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_336__PHY_RDPATH_GATE_DISABLE_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_336__PHY_RDPATH_GATE_DISABLE_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_336__PHY_RDPATH_GATE_DISABLE_1_WOSET 0U +#define LPDDR4__PHY_RDPATH_GATE_DISABLE_1__REG DENALI_PHY_336 +#define LPDDR4__PHY_RDPATH_GATE_DISABLE_1__FLD LPDDR4__DENALI_PHY_336__PHY_RDPATH_GATE_DISABLE_1 + +#define LPDDR4__DENALI_PHY_336__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_1_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_336__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_336__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_336__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_336__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_1_WOSET 0U +#define LPDDR4__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_1__REG DENALI_PHY_336 +#define LPDDR4__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_1__FLD LPDDR4__DENALI_PHY_336__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_1 + +#define LPDDR4__DENALI_PHY_336__PHY_SLICE_PWR_RDC_DISABLE_1_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_336__PHY_SLICE_PWR_RDC_DISABLE_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_336__PHY_SLICE_PWR_RDC_DISABLE_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_336__PHY_SLICE_PWR_RDC_DISABLE_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_336__PHY_SLICE_PWR_RDC_DISABLE_1_WOSET 0U +#define LPDDR4__PHY_SLICE_PWR_RDC_DISABLE_1__REG DENALI_PHY_336 +#define LPDDR4__PHY_SLICE_PWR_RDC_DISABLE_1__FLD LPDDR4__DENALI_PHY_336__PHY_SLICE_PWR_RDC_DISABLE_1 + +#define LPDDR4__DENALI_PHY_337_READ_MASK 0x3FFF07FFU +#define LPDDR4__DENALI_PHY_337_WRITE_MASK 0x3FFF07FFU +#define LPDDR4__DENALI_PHY_337__PHY_PARITY_ERROR_REGIF_1_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_337__PHY_PARITY_ERROR_REGIF_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_337__PHY_PARITY_ERROR_REGIF_1_WIDTH 11U +#define LPDDR4__PHY_PARITY_ERROR_REGIF_1__REG DENALI_PHY_337 +#define LPDDR4__PHY_PARITY_ERROR_REGIF_1__FLD LPDDR4__DENALI_PHY_337__PHY_PARITY_ERROR_REGIF_1 + +#define LPDDR4__DENALI_PHY_337__PHY_DS_FSM_ERROR_INFO_1_MASK 0x3FFF0000U +#define LPDDR4__DENALI_PHY_337__PHY_DS_FSM_ERROR_INFO_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_337__PHY_DS_FSM_ERROR_INFO_1_WIDTH 14U +#define LPDDR4__PHY_DS_FSM_ERROR_INFO_1__REG DENALI_PHY_337 +#define LPDDR4__PHY_DS_FSM_ERROR_INFO_1__FLD LPDDR4__DENALI_PHY_337__PHY_DS_FSM_ERROR_INFO_1 + +#define LPDDR4__DENALI_PHY_338_READ_MASK 0x00003FFFU +#define LPDDR4__DENALI_PHY_338_WRITE_MASK 0x00003FFFU +#define LPDDR4__DENALI_PHY_338__PHY_DS_FSM_ERROR_INFO_MASK_1_MASK 0x00003FFFU +#define LPDDR4__DENALI_PHY_338__PHY_DS_FSM_ERROR_INFO_MASK_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_338__PHY_DS_FSM_ERROR_INFO_MASK_1_WIDTH 14U +#define LPDDR4__PHY_DS_FSM_ERROR_INFO_MASK_1__REG DENALI_PHY_338 +#define LPDDR4__PHY_DS_FSM_ERROR_INFO_MASK_1__FLD LPDDR4__DENALI_PHY_338__PHY_DS_FSM_ERROR_INFO_MASK_1 + +#define LPDDR4__DENALI_PHY_338__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_1_MASK 0x3FFF0000U +#define LPDDR4__DENALI_PHY_338__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_338__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_1_WIDTH 14U +#define LPDDR4__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_1__REG DENALI_PHY_338 +#define LPDDR4__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_1__FLD LPDDR4__DENALI_PHY_338__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_1 + +#define LPDDR4__DENALI_PHY_339_READ_MASK 0x00001F1FU +#define LPDDR4__DENALI_PHY_339_WRITE_MASK 0x00001F1FU +#define LPDDR4__DENALI_PHY_339__PHY_DS_TRAIN_CALIB_ERROR_INFO_1_MASK 0x0000001FU +#define LPDDR4__DENALI_PHY_339__PHY_DS_TRAIN_CALIB_ERROR_INFO_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_339__PHY_DS_TRAIN_CALIB_ERROR_INFO_1_WIDTH 5U +#define LPDDR4__PHY_DS_TRAIN_CALIB_ERROR_INFO_1__REG DENALI_PHY_339 +#define LPDDR4__PHY_DS_TRAIN_CALIB_ERROR_INFO_1__FLD LPDDR4__DENALI_PHY_339__PHY_DS_TRAIN_CALIB_ERROR_INFO_1 + +#define LPDDR4__DENALI_PHY_339__PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_1_MASK 0x00001F00U +#define LPDDR4__DENALI_PHY_339__PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_339__PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_1_WIDTH 5U +#define LPDDR4__PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_1__REG DENALI_PHY_339 +#define LPDDR4__PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_1__FLD LPDDR4__DENALI_PHY_339__PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_1 + +#define LPDDR4__DENALI_PHY_339__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_1_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_339__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_339__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_1_WIDTH 5U +#define LPDDR4__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_1__REG DENALI_PHY_339 +#define LPDDR4__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_1__FLD LPDDR4__DENALI_PHY_339__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_1 + +#define LPDDR4__DENALI_PHY_340_READ_MASK 0x07FFFF07U +#define LPDDR4__DENALI_PHY_340_WRITE_MASK 0x07FFFF07U +#define LPDDR4__DENALI_PHY_340__PHY_DQ_TSEL_ENABLE_1_MASK 0x00000007U +#define LPDDR4__DENALI_PHY_340__PHY_DQ_TSEL_ENABLE_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_340__PHY_DQ_TSEL_ENABLE_1_WIDTH 3U +#define LPDDR4__PHY_DQ_TSEL_ENABLE_1__REG DENALI_PHY_340 +#define LPDDR4__PHY_DQ_TSEL_ENABLE_1__FLD LPDDR4__DENALI_PHY_340__PHY_DQ_TSEL_ENABLE_1 + +#define LPDDR4__DENALI_PHY_340__PHY_DQ_TSEL_SELECT_1_MASK 0x00FFFF00U +#define LPDDR4__DENALI_PHY_340__PHY_DQ_TSEL_SELECT_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_340__PHY_DQ_TSEL_SELECT_1_WIDTH 16U +#define LPDDR4__PHY_DQ_TSEL_SELECT_1__REG DENALI_PHY_340 +#define LPDDR4__PHY_DQ_TSEL_SELECT_1__FLD LPDDR4__DENALI_PHY_340__PHY_DQ_TSEL_SELECT_1 + +#define LPDDR4__DENALI_PHY_340__PHY_DQS_TSEL_ENABLE_1_MASK 0x07000000U +#define LPDDR4__DENALI_PHY_340__PHY_DQS_TSEL_ENABLE_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_340__PHY_DQS_TSEL_ENABLE_1_WIDTH 3U +#define LPDDR4__PHY_DQS_TSEL_ENABLE_1__REG DENALI_PHY_340 +#define LPDDR4__PHY_DQS_TSEL_ENABLE_1__FLD LPDDR4__DENALI_PHY_340__PHY_DQS_TSEL_ENABLE_1 + +#define LPDDR4__DENALI_PHY_341_READ_MASK 0x7F03FFFFU +#define LPDDR4__DENALI_PHY_341_WRITE_MASK 0x7F03FFFFU +#define LPDDR4__DENALI_PHY_341__PHY_DQS_TSEL_SELECT_1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_341__PHY_DQS_TSEL_SELECT_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_341__PHY_DQS_TSEL_SELECT_1_WIDTH 16U +#define LPDDR4__PHY_DQS_TSEL_SELECT_1__REG DENALI_PHY_341 +#define LPDDR4__PHY_DQS_TSEL_SELECT_1__FLD LPDDR4__DENALI_PHY_341__PHY_DQS_TSEL_SELECT_1 + +#define LPDDR4__DENALI_PHY_341__PHY_TWO_CYC_PREAMBLE_1_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_341__PHY_TWO_CYC_PREAMBLE_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_341__PHY_TWO_CYC_PREAMBLE_1_WIDTH 2U +#define LPDDR4__PHY_TWO_CYC_PREAMBLE_1__REG DENALI_PHY_341 +#define LPDDR4__PHY_TWO_CYC_PREAMBLE_1__FLD LPDDR4__DENALI_PHY_341__PHY_TWO_CYC_PREAMBLE_1 + +#define LPDDR4__DENALI_PHY_341__PHY_VREF_INITIAL_START_POINT_1_MASK 0x7F000000U +#define LPDDR4__DENALI_PHY_341__PHY_VREF_INITIAL_START_POINT_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_341__PHY_VREF_INITIAL_START_POINT_1_WIDTH 7U +#define LPDDR4__PHY_VREF_INITIAL_START_POINT_1__REG DENALI_PHY_341 +#define LPDDR4__PHY_VREF_INITIAL_START_POINT_1__FLD LPDDR4__DENALI_PHY_341__PHY_VREF_INITIAL_START_POINT_1 + +#define LPDDR4__DENALI_PHY_342_READ_MASK 0xFF01037FU +#define LPDDR4__DENALI_PHY_342_WRITE_MASK 0xFF01037FU +#define LPDDR4__DENALI_PHY_342__PHY_VREF_INITIAL_STOP_POINT_1_MASK 0x0000007FU +#define LPDDR4__DENALI_PHY_342__PHY_VREF_INITIAL_STOP_POINT_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_342__PHY_VREF_INITIAL_STOP_POINT_1_WIDTH 7U +#define LPDDR4__PHY_VREF_INITIAL_STOP_POINT_1__REG DENALI_PHY_342 +#define LPDDR4__PHY_VREF_INITIAL_STOP_POINT_1__FLD LPDDR4__DENALI_PHY_342__PHY_VREF_INITIAL_STOP_POINT_1 + +#define LPDDR4__DENALI_PHY_342__PHY_VREF_TRAINING_CTRL_1_MASK 0x00000300U +#define LPDDR4__DENALI_PHY_342__PHY_VREF_TRAINING_CTRL_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_342__PHY_VREF_TRAINING_CTRL_1_WIDTH 2U +#define LPDDR4__PHY_VREF_TRAINING_CTRL_1__REG DENALI_PHY_342 +#define LPDDR4__PHY_VREF_TRAINING_CTRL_1__FLD LPDDR4__DENALI_PHY_342__PHY_VREF_TRAINING_CTRL_1 + +#define LPDDR4__DENALI_PHY_342__PHY_NTP_TRAIN_EN_1_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_342__PHY_NTP_TRAIN_EN_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_342__PHY_NTP_TRAIN_EN_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_342__PHY_NTP_TRAIN_EN_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_342__PHY_NTP_TRAIN_EN_1_WOSET 0U +#define LPDDR4__PHY_NTP_TRAIN_EN_1__REG DENALI_PHY_342 +#define LPDDR4__PHY_NTP_TRAIN_EN_1__FLD LPDDR4__DENALI_PHY_342__PHY_NTP_TRAIN_EN_1 + +#define LPDDR4__DENALI_PHY_342__PHY_NTP_WDQ_STEP_SIZE_1_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_342__PHY_NTP_WDQ_STEP_SIZE_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_342__PHY_NTP_WDQ_STEP_SIZE_1_WIDTH 8U +#define LPDDR4__PHY_NTP_WDQ_STEP_SIZE_1__REG DENALI_PHY_342 +#define LPDDR4__PHY_NTP_WDQ_STEP_SIZE_1__FLD LPDDR4__DENALI_PHY_342__PHY_NTP_WDQ_STEP_SIZE_1 + +#define LPDDR4__DENALI_PHY_343_READ_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_343_WRITE_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_343__PHY_NTP_WDQ_START_1_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_343__PHY_NTP_WDQ_START_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_343__PHY_NTP_WDQ_START_1_WIDTH 11U +#define LPDDR4__PHY_NTP_WDQ_START_1__REG DENALI_PHY_343 +#define LPDDR4__PHY_NTP_WDQ_START_1__FLD LPDDR4__DENALI_PHY_343__PHY_NTP_WDQ_START_1 + +#define LPDDR4__DENALI_PHY_343__PHY_NTP_WDQ_STOP_1_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_343__PHY_NTP_WDQ_STOP_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_343__PHY_NTP_WDQ_STOP_1_WIDTH 11U +#define LPDDR4__PHY_NTP_WDQ_STOP_1__REG DENALI_PHY_343 +#define LPDDR4__PHY_NTP_WDQ_STOP_1__FLD LPDDR4__DENALI_PHY_343__PHY_NTP_WDQ_STOP_1 + +#define LPDDR4__DENALI_PHY_344_READ_MASK 0x0103FFFFU +#define LPDDR4__DENALI_PHY_344_WRITE_MASK 0x0103FFFFU +#define LPDDR4__DENALI_PHY_344__PHY_NTP_WDQ_BIT_EN_1_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_344__PHY_NTP_WDQ_BIT_EN_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_344__PHY_NTP_WDQ_BIT_EN_1_WIDTH 8U +#define LPDDR4__PHY_NTP_WDQ_BIT_EN_1__REG DENALI_PHY_344 +#define LPDDR4__PHY_NTP_WDQ_BIT_EN_1__FLD LPDDR4__DENALI_PHY_344__PHY_NTP_WDQ_BIT_EN_1 + +#define LPDDR4__DENALI_PHY_344__PHY_WDQLVL_DVW_MIN_1_MASK 0x0003FF00U +#define LPDDR4__DENALI_PHY_344__PHY_WDQLVL_DVW_MIN_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_344__PHY_WDQLVL_DVW_MIN_1_WIDTH 10U +#define LPDDR4__PHY_WDQLVL_DVW_MIN_1__REG DENALI_PHY_344 +#define LPDDR4__PHY_WDQLVL_DVW_MIN_1__FLD LPDDR4__DENALI_PHY_344__PHY_WDQLVL_DVW_MIN_1 + +#define LPDDR4__DENALI_PHY_344__PHY_SW_WDQLVL_DVW_MIN_EN_1_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_344__PHY_SW_WDQLVL_DVW_MIN_EN_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_344__PHY_SW_WDQLVL_DVW_MIN_EN_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_344__PHY_SW_WDQLVL_DVW_MIN_EN_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_344__PHY_SW_WDQLVL_DVW_MIN_EN_1_WOSET 0U +#define LPDDR4__PHY_SW_WDQLVL_DVW_MIN_EN_1__REG DENALI_PHY_344 +#define LPDDR4__PHY_SW_WDQLVL_DVW_MIN_EN_1__FLD LPDDR4__DENALI_PHY_344__PHY_SW_WDQLVL_DVW_MIN_EN_1 + +#define LPDDR4__DENALI_PHY_345_READ_MASK 0x1F1F0F3FU +#define LPDDR4__DENALI_PHY_345_WRITE_MASK 0x1F1F0F3FU +#define LPDDR4__DENALI_PHY_345__PHY_WDQLVL_PER_START_OFFSET_1_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_345__PHY_WDQLVL_PER_START_OFFSET_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_345__PHY_WDQLVL_PER_START_OFFSET_1_WIDTH 6U +#define LPDDR4__PHY_WDQLVL_PER_START_OFFSET_1__REG DENALI_PHY_345 +#define LPDDR4__PHY_WDQLVL_PER_START_OFFSET_1__FLD LPDDR4__DENALI_PHY_345__PHY_WDQLVL_PER_START_OFFSET_1 + +#define LPDDR4__DENALI_PHY_345__PHY_FAST_LVL_EN_1_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_345__PHY_FAST_LVL_EN_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_345__PHY_FAST_LVL_EN_1_WIDTH 4U +#define LPDDR4__PHY_FAST_LVL_EN_1__REG DENALI_PHY_345 +#define LPDDR4__PHY_FAST_LVL_EN_1__FLD LPDDR4__DENALI_PHY_345__PHY_FAST_LVL_EN_1 + +#define LPDDR4__DENALI_PHY_345__PHY_PAD_TX_DCD_1_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_345__PHY_PAD_TX_DCD_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_345__PHY_PAD_TX_DCD_1_WIDTH 5U +#define LPDDR4__PHY_PAD_TX_DCD_1__REG DENALI_PHY_345 +#define LPDDR4__PHY_PAD_TX_DCD_1__FLD LPDDR4__DENALI_PHY_345__PHY_PAD_TX_DCD_1 + +#define LPDDR4__DENALI_PHY_345__PHY_PAD_RX_DCD_0_1_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_345__PHY_PAD_RX_DCD_0_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_345__PHY_PAD_RX_DCD_0_1_WIDTH 5U +#define LPDDR4__PHY_PAD_RX_DCD_0_1__REG DENALI_PHY_345 +#define LPDDR4__PHY_PAD_RX_DCD_0_1__FLD LPDDR4__DENALI_PHY_345__PHY_PAD_RX_DCD_0_1 + +#define LPDDR4__DENALI_PHY_346_READ_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_PHY_346_WRITE_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_PHY_346__PHY_PAD_RX_DCD_1_1_MASK 0x0000001FU +#define LPDDR4__DENALI_PHY_346__PHY_PAD_RX_DCD_1_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_346__PHY_PAD_RX_DCD_1_1_WIDTH 5U +#define LPDDR4__PHY_PAD_RX_DCD_1_1__REG DENALI_PHY_346 +#define LPDDR4__PHY_PAD_RX_DCD_1_1__FLD LPDDR4__DENALI_PHY_346__PHY_PAD_RX_DCD_1_1 + +#define LPDDR4__DENALI_PHY_346__PHY_PAD_RX_DCD_2_1_MASK 0x00001F00U +#define LPDDR4__DENALI_PHY_346__PHY_PAD_RX_DCD_2_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_346__PHY_PAD_RX_DCD_2_1_WIDTH 5U +#define LPDDR4__PHY_PAD_RX_DCD_2_1__REG DENALI_PHY_346 +#define LPDDR4__PHY_PAD_RX_DCD_2_1__FLD LPDDR4__DENALI_PHY_346__PHY_PAD_RX_DCD_2_1 + +#define LPDDR4__DENALI_PHY_346__PHY_PAD_RX_DCD_3_1_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_346__PHY_PAD_RX_DCD_3_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_346__PHY_PAD_RX_DCD_3_1_WIDTH 5U +#define LPDDR4__PHY_PAD_RX_DCD_3_1__REG DENALI_PHY_346 +#define LPDDR4__PHY_PAD_RX_DCD_3_1__FLD LPDDR4__DENALI_PHY_346__PHY_PAD_RX_DCD_3_1 + +#define LPDDR4__DENALI_PHY_346__PHY_PAD_RX_DCD_4_1_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_346__PHY_PAD_RX_DCD_4_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_346__PHY_PAD_RX_DCD_4_1_WIDTH 5U +#define LPDDR4__PHY_PAD_RX_DCD_4_1__REG DENALI_PHY_346 +#define LPDDR4__PHY_PAD_RX_DCD_4_1__FLD LPDDR4__DENALI_PHY_346__PHY_PAD_RX_DCD_4_1 + +#define LPDDR4__DENALI_PHY_347_READ_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_PHY_347_WRITE_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_PHY_347__PHY_PAD_RX_DCD_5_1_MASK 0x0000001FU +#define LPDDR4__DENALI_PHY_347__PHY_PAD_RX_DCD_5_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_347__PHY_PAD_RX_DCD_5_1_WIDTH 5U +#define LPDDR4__PHY_PAD_RX_DCD_5_1__REG DENALI_PHY_347 +#define LPDDR4__PHY_PAD_RX_DCD_5_1__FLD LPDDR4__DENALI_PHY_347__PHY_PAD_RX_DCD_5_1 + +#define LPDDR4__DENALI_PHY_347__PHY_PAD_RX_DCD_6_1_MASK 0x00001F00U +#define LPDDR4__DENALI_PHY_347__PHY_PAD_RX_DCD_6_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_347__PHY_PAD_RX_DCD_6_1_WIDTH 5U +#define LPDDR4__PHY_PAD_RX_DCD_6_1__REG DENALI_PHY_347 +#define LPDDR4__PHY_PAD_RX_DCD_6_1__FLD LPDDR4__DENALI_PHY_347__PHY_PAD_RX_DCD_6_1 + +#define LPDDR4__DENALI_PHY_347__PHY_PAD_RX_DCD_7_1_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_347__PHY_PAD_RX_DCD_7_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_347__PHY_PAD_RX_DCD_7_1_WIDTH 5U +#define LPDDR4__PHY_PAD_RX_DCD_7_1__REG DENALI_PHY_347 +#define LPDDR4__PHY_PAD_RX_DCD_7_1__FLD LPDDR4__DENALI_PHY_347__PHY_PAD_RX_DCD_7_1 + +#define LPDDR4__DENALI_PHY_347__PHY_PAD_DM_RX_DCD_1_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_347__PHY_PAD_DM_RX_DCD_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_347__PHY_PAD_DM_RX_DCD_1_WIDTH 5U +#define LPDDR4__PHY_PAD_DM_RX_DCD_1__REG DENALI_PHY_347 +#define LPDDR4__PHY_PAD_DM_RX_DCD_1__FLD LPDDR4__DENALI_PHY_347__PHY_PAD_DM_RX_DCD_1 + +#define LPDDR4__DENALI_PHY_348_READ_MASK 0x003F1F1FU +#define LPDDR4__DENALI_PHY_348_WRITE_MASK 0x003F1F1FU +#define LPDDR4__DENALI_PHY_348__PHY_PAD_DQS_RX_DCD_1_MASK 0x0000001FU +#define LPDDR4__DENALI_PHY_348__PHY_PAD_DQS_RX_DCD_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_348__PHY_PAD_DQS_RX_DCD_1_WIDTH 5U +#define LPDDR4__PHY_PAD_DQS_RX_DCD_1__REG DENALI_PHY_348 +#define LPDDR4__PHY_PAD_DQS_RX_DCD_1__FLD LPDDR4__DENALI_PHY_348__PHY_PAD_DQS_RX_DCD_1 + +#define LPDDR4__DENALI_PHY_348__PHY_PAD_FDBK_RX_DCD_1_MASK 0x00001F00U +#define LPDDR4__DENALI_PHY_348__PHY_PAD_FDBK_RX_DCD_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_348__PHY_PAD_FDBK_RX_DCD_1_WIDTH 5U +#define LPDDR4__PHY_PAD_FDBK_RX_DCD_1__REG DENALI_PHY_348 +#define LPDDR4__PHY_PAD_FDBK_RX_DCD_1__FLD LPDDR4__DENALI_PHY_348__PHY_PAD_FDBK_RX_DCD_1 + +#define LPDDR4__DENALI_PHY_348__PHY_PAD_DSLICE_IO_CFG_1_MASK 0x003F0000U +#define LPDDR4__DENALI_PHY_348__PHY_PAD_DSLICE_IO_CFG_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_348__PHY_PAD_DSLICE_IO_CFG_1_WIDTH 6U +#define LPDDR4__PHY_PAD_DSLICE_IO_CFG_1__REG DENALI_PHY_348 +#define LPDDR4__PHY_PAD_DSLICE_IO_CFG_1__FLD LPDDR4__DENALI_PHY_348__PHY_PAD_DSLICE_IO_CFG_1 + +#define LPDDR4__DENALI_PHY_349_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_349_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_349__PHY_RDDQ0_SLAVE_DELAY_1_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_349__PHY_RDDQ0_SLAVE_DELAY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_349__PHY_RDDQ0_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDQ0_SLAVE_DELAY_1__REG DENALI_PHY_349 +#define LPDDR4__PHY_RDDQ0_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_349__PHY_RDDQ0_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_349__PHY_RDDQ1_SLAVE_DELAY_1_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_349__PHY_RDDQ1_SLAVE_DELAY_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_349__PHY_RDDQ1_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDQ1_SLAVE_DELAY_1__REG DENALI_PHY_349 +#define LPDDR4__PHY_RDDQ1_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_349__PHY_RDDQ1_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_350_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_350_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_350__PHY_RDDQ2_SLAVE_DELAY_1_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_350__PHY_RDDQ2_SLAVE_DELAY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_350__PHY_RDDQ2_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDQ2_SLAVE_DELAY_1__REG DENALI_PHY_350 +#define LPDDR4__PHY_RDDQ2_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_350__PHY_RDDQ2_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_350__PHY_RDDQ3_SLAVE_DELAY_1_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_350__PHY_RDDQ3_SLAVE_DELAY_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_350__PHY_RDDQ3_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDQ3_SLAVE_DELAY_1__REG DENALI_PHY_350 +#define LPDDR4__PHY_RDDQ3_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_350__PHY_RDDQ3_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_351_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_351_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_351__PHY_RDDQ4_SLAVE_DELAY_1_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_351__PHY_RDDQ4_SLAVE_DELAY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_351__PHY_RDDQ4_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDQ4_SLAVE_DELAY_1__REG DENALI_PHY_351 +#define LPDDR4__PHY_RDDQ4_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_351__PHY_RDDQ4_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_351__PHY_RDDQ5_SLAVE_DELAY_1_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_351__PHY_RDDQ5_SLAVE_DELAY_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_351__PHY_RDDQ5_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDQ5_SLAVE_DELAY_1__REG DENALI_PHY_351 +#define LPDDR4__PHY_RDDQ5_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_351__PHY_RDDQ5_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_352_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_352_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_352__PHY_RDDQ6_SLAVE_DELAY_1_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_352__PHY_RDDQ6_SLAVE_DELAY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_352__PHY_RDDQ6_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDQ6_SLAVE_DELAY_1__REG DENALI_PHY_352 +#define LPDDR4__PHY_RDDQ6_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_352__PHY_RDDQ6_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_352__PHY_RDDQ7_SLAVE_DELAY_1_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_352__PHY_RDDQ7_SLAVE_DELAY_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_352__PHY_RDDQ7_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDQ7_SLAVE_DELAY_1__REG DENALI_PHY_352 +#define LPDDR4__PHY_RDDQ7_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_352__PHY_RDDQ7_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_353_READ_MASK 0x000703FFU +#define LPDDR4__DENALI_PHY_353_WRITE_MASK 0x000703FFU +#define LPDDR4__DENALI_PHY_353__PHY_RDDM_SLAVE_DELAY_1_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_353__PHY_RDDM_SLAVE_DELAY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_353__PHY_RDDM_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDM_SLAVE_DELAY_1__REG DENALI_PHY_353 +#define LPDDR4__PHY_RDDM_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_353__PHY_RDDM_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_353__PHY_DATA_DC_CAL_CLK_SEL_1_MASK 0x00070000U +#define LPDDR4__DENALI_PHY_353__PHY_DATA_DC_CAL_CLK_SEL_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_353__PHY_DATA_DC_CAL_CLK_SEL_1_WIDTH 3U +#define LPDDR4__PHY_DATA_DC_CAL_CLK_SEL_1__REG DENALI_PHY_353 +#define LPDDR4__PHY_DATA_DC_CAL_CLK_SEL_1__FLD LPDDR4__DENALI_PHY_353__PHY_DATA_DC_CAL_CLK_SEL_1 + +#define LPDDR4__DENALI_PHY_354_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_354_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_354__PHY_DQ_OE_TIMING_1_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_354__PHY_DQ_OE_TIMING_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_354__PHY_DQ_OE_TIMING_1_WIDTH 8U +#define LPDDR4__PHY_DQ_OE_TIMING_1__REG DENALI_PHY_354 +#define LPDDR4__PHY_DQ_OE_TIMING_1__FLD LPDDR4__DENALI_PHY_354__PHY_DQ_OE_TIMING_1 + +#define LPDDR4__DENALI_PHY_354__PHY_DQ_TSEL_RD_TIMING_1_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_354__PHY_DQ_TSEL_RD_TIMING_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_354__PHY_DQ_TSEL_RD_TIMING_1_WIDTH 8U +#define LPDDR4__PHY_DQ_TSEL_RD_TIMING_1__REG DENALI_PHY_354 +#define LPDDR4__PHY_DQ_TSEL_RD_TIMING_1__FLD LPDDR4__DENALI_PHY_354__PHY_DQ_TSEL_RD_TIMING_1 + +#define LPDDR4__DENALI_PHY_354__PHY_DQ_TSEL_WR_TIMING_1_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_354__PHY_DQ_TSEL_WR_TIMING_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_354__PHY_DQ_TSEL_WR_TIMING_1_WIDTH 8U +#define LPDDR4__PHY_DQ_TSEL_WR_TIMING_1__REG DENALI_PHY_354 +#define LPDDR4__PHY_DQ_TSEL_WR_TIMING_1__FLD LPDDR4__DENALI_PHY_354__PHY_DQ_TSEL_WR_TIMING_1 + +#define LPDDR4__DENALI_PHY_354__PHY_DQS_OE_TIMING_1_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_354__PHY_DQS_OE_TIMING_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_354__PHY_DQS_OE_TIMING_1_WIDTH 8U +#define LPDDR4__PHY_DQS_OE_TIMING_1__REG DENALI_PHY_354 +#define LPDDR4__PHY_DQS_OE_TIMING_1__FLD LPDDR4__DENALI_PHY_354__PHY_DQS_OE_TIMING_1 + +#define LPDDR4__DENALI_PHY_355_READ_MASK 0xFFFFFF0FU +#define LPDDR4__DENALI_PHY_355_WRITE_MASK 0xFFFFFF0FU +#define LPDDR4__DENALI_PHY_355__PHY_IO_PAD_DELAY_TIMING_1_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_355__PHY_IO_PAD_DELAY_TIMING_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_355__PHY_IO_PAD_DELAY_TIMING_1_WIDTH 4U +#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_1__REG DENALI_PHY_355 +#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_1__FLD LPDDR4__DENALI_PHY_355__PHY_IO_PAD_DELAY_TIMING_1 + +#define LPDDR4__DENALI_PHY_355__PHY_DQS_TSEL_RD_TIMING_1_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_355__PHY_DQS_TSEL_RD_TIMING_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_355__PHY_DQS_TSEL_RD_TIMING_1_WIDTH 8U +#define LPDDR4__PHY_DQS_TSEL_RD_TIMING_1__REG DENALI_PHY_355 +#define LPDDR4__PHY_DQS_TSEL_RD_TIMING_1__FLD LPDDR4__DENALI_PHY_355__PHY_DQS_TSEL_RD_TIMING_1 + +#define LPDDR4__DENALI_PHY_355__PHY_DQS_OE_RD_TIMING_1_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_355__PHY_DQS_OE_RD_TIMING_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_355__PHY_DQS_OE_RD_TIMING_1_WIDTH 8U +#define LPDDR4__PHY_DQS_OE_RD_TIMING_1__REG DENALI_PHY_355 +#define LPDDR4__PHY_DQS_OE_RD_TIMING_1__FLD LPDDR4__DENALI_PHY_355__PHY_DQS_OE_RD_TIMING_1 + +#define LPDDR4__DENALI_PHY_355__PHY_DQS_TSEL_WR_TIMING_1_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_355__PHY_DQS_TSEL_WR_TIMING_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_355__PHY_DQS_TSEL_WR_TIMING_1_WIDTH 8U +#define LPDDR4__PHY_DQS_TSEL_WR_TIMING_1__REG DENALI_PHY_355 +#define LPDDR4__PHY_DQS_TSEL_WR_TIMING_1__FLD LPDDR4__DENALI_PHY_355__PHY_DQS_TSEL_WR_TIMING_1 + +#define LPDDR4__DENALI_PHY_356_READ_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_356_WRITE_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_356__PHY_VREF_SETTING_TIME_1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_356__PHY_VREF_SETTING_TIME_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_356__PHY_VREF_SETTING_TIME_1_WIDTH 16U +#define LPDDR4__PHY_VREF_SETTING_TIME_1__REG DENALI_PHY_356 +#define LPDDR4__PHY_VREF_SETTING_TIME_1__FLD LPDDR4__DENALI_PHY_356__PHY_VREF_SETTING_TIME_1 + +#define LPDDR4__DENALI_PHY_356__PHY_PAD_VREF_CTRL_DQ_1_MASK 0x0FFF0000U +#define LPDDR4__DENALI_PHY_356__PHY_PAD_VREF_CTRL_DQ_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_356__PHY_PAD_VREF_CTRL_DQ_1_WIDTH 12U +#define LPDDR4__PHY_PAD_VREF_CTRL_DQ_1__REG DENALI_PHY_356 +#define LPDDR4__PHY_PAD_VREF_CTRL_DQ_1__FLD LPDDR4__DENALI_PHY_356__PHY_PAD_VREF_CTRL_DQ_1 + +#define LPDDR4__DENALI_PHY_357_READ_MASK 0x03FFFF01U +#define LPDDR4__DENALI_PHY_357_WRITE_MASK 0x03FFFF01U +#define LPDDR4__DENALI_PHY_357__PHY_PER_CS_TRAINING_EN_1_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_357__PHY_PER_CS_TRAINING_EN_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_357__PHY_PER_CS_TRAINING_EN_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_357__PHY_PER_CS_TRAINING_EN_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_357__PHY_PER_CS_TRAINING_EN_1_WOSET 0U +#define LPDDR4__PHY_PER_CS_TRAINING_EN_1__REG DENALI_PHY_357 +#define LPDDR4__PHY_PER_CS_TRAINING_EN_1__FLD LPDDR4__DENALI_PHY_357__PHY_PER_CS_TRAINING_EN_1 + +#define LPDDR4__DENALI_PHY_357__PHY_DQ_IE_TIMING_1_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_357__PHY_DQ_IE_TIMING_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_357__PHY_DQ_IE_TIMING_1_WIDTH 8U +#define LPDDR4__PHY_DQ_IE_TIMING_1__REG DENALI_PHY_357 +#define LPDDR4__PHY_DQ_IE_TIMING_1__FLD LPDDR4__DENALI_PHY_357__PHY_DQ_IE_TIMING_1 + +#define LPDDR4__DENALI_PHY_357__PHY_DQS_IE_TIMING_1_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_357__PHY_DQS_IE_TIMING_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_357__PHY_DQS_IE_TIMING_1_WIDTH 8U +#define LPDDR4__PHY_DQS_IE_TIMING_1__REG DENALI_PHY_357 +#define LPDDR4__PHY_DQS_IE_TIMING_1__FLD LPDDR4__DENALI_PHY_357__PHY_DQS_IE_TIMING_1 + +#define LPDDR4__DENALI_PHY_357__PHY_RDDATA_EN_IE_DLY_1_MASK 0x03000000U +#define LPDDR4__DENALI_PHY_357__PHY_RDDATA_EN_IE_DLY_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_357__PHY_RDDATA_EN_IE_DLY_1_WIDTH 2U +#define LPDDR4__PHY_RDDATA_EN_IE_DLY_1__REG DENALI_PHY_357 +#define LPDDR4__PHY_RDDATA_EN_IE_DLY_1__FLD LPDDR4__DENALI_PHY_357__PHY_RDDATA_EN_IE_DLY_1 + +#define LPDDR4__DENALI_PHY_358_READ_MASK 0x1F1F0103U +#define LPDDR4__DENALI_PHY_358_WRITE_MASK 0x1F1F0103U +#define LPDDR4__DENALI_PHY_358__PHY_IE_MODE_1_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_358__PHY_IE_MODE_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_358__PHY_IE_MODE_1_WIDTH 2U +#define LPDDR4__PHY_IE_MODE_1__REG DENALI_PHY_358 +#define LPDDR4__PHY_IE_MODE_1__FLD LPDDR4__DENALI_PHY_358__PHY_IE_MODE_1 + +#define LPDDR4__DENALI_PHY_358__PHY_DBI_MODE_1_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_358__PHY_DBI_MODE_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_358__PHY_DBI_MODE_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_358__PHY_DBI_MODE_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_358__PHY_DBI_MODE_1_WOSET 0U +#define LPDDR4__PHY_DBI_MODE_1__REG DENALI_PHY_358 +#define LPDDR4__PHY_DBI_MODE_1__FLD LPDDR4__DENALI_PHY_358__PHY_DBI_MODE_1 + +#define LPDDR4__DENALI_PHY_358__PHY_RDDATA_EN_TSEL_DLY_1_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_358__PHY_RDDATA_EN_TSEL_DLY_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_358__PHY_RDDATA_EN_TSEL_DLY_1_WIDTH 5U +#define LPDDR4__PHY_RDDATA_EN_TSEL_DLY_1__REG DENALI_PHY_358 +#define LPDDR4__PHY_RDDATA_EN_TSEL_DLY_1__FLD LPDDR4__DENALI_PHY_358__PHY_RDDATA_EN_TSEL_DLY_1 + +#define LPDDR4__DENALI_PHY_358__PHY_RDDATA_EN_OE_DLY_1_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_358__PHY_RDDATA_EN_OE_DLY_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_358__PHY_RDDATA_EN_OE_DLY_1_WIDTH 5U +#define LPDDR4__PHY_RDDATA_EN_OE_DLY_1__REG DENALI_PHY_358 +#define LPDDR4__PHY_RDDATA_EN_OE_DLY_1__FLD LPDDR4__DENALI_PHY_358__PHY_RDDATA_EN_OE_DLY_1 + +#define LPDDR4__DENALI_PHY_359_READ_MASK 0x3F07FF0FU +#define LPDDR4__DENALI_PHY_359_WRITE_MASK 0x3F07FF0FU +#define LPDDR4__DENALI_PHY_359__PHY_SW_MASTER_MODE_1_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_359__PHY_SW_MASTER_MODE_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_359__PHY_SW_MASTER_MODE_1_WIDTH 4U +#define LPDDR4__PHY_SW_MASTER_MODE_1__REG DENALI_PHY_359 +#define LPDDR4__PHY_SW_MASTER_MODE_1__FLD LPDDR4__DENALI_PHY_359__PHY_SW_MASTER_MODE_1 + +#define LPDDR4__DENALI_PHY_359__PHY_MASTER_DELAY_START_1_MASK 0x0007FF00U +#define LPDDR4__DENALI_PHY_359__PHY_MASTER_DELAY_START_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_359__PHY_MASTER_DELAY_START_1_WIDTH 11U +#define LPDDR4__PHY_MASTER_DELAY_START_1__REG DENALI_PHY_359 +#define LPDDR4__PHY_MASTER_DELAY_START_1__FLD LPDDR4__DENALI_PHY_359__PHY_MASTER_DELAY_START_1 + +#define LPDDR4__DENALI_PHY_359__PHY_MASTER_DELAY_STEP_1_MASK 0x3F000000U +#define LPDDR4__DENALI_PHY_359__PHY_MASTER_DELAY_STEP_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_359__PHY_MASTER_DELAY_STEP_1_WIDTH 6U +#define LPDDR4__PHY_MASTER_DELAY_STEP_1__REG DENALI_PHY_359 +#define LPDDR4__PHY_MASTER_DELAY_STEP_1__FLD LPDDR4__DENALI_PHY_359__PHY_MASTER_DELAY_STEP_1 + +#define LPDDR4__DENALI_PHY_360_READ_MASK 0xFF0FFFFFU +#define LPDDR4__DENALI_PHY_360_WRITE_MASK 0xFF0FFFFFU +#define LPDDR4__DENALI_PHY_360__PHY_MASTER_DELAY_WAIT_1_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_360__PHY_MASTER_DELAY_WAIT_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_360__PHY_MASTER_DELAY_WAIT_1_WIDTH 8U +#define LPDDR4__PHY_MASTER_DELAY_WAIT_1__REG DENALI_PHY_360 +#define LPDDR4__PHY_MASTER_DELAY_WAIT_1__FLD LPDDR4__DENALI_PHY_360__PHY_MASTER_DELAY_WAIT_1 + +#define LPDDR4__DENALI_PHY_360__PHY_MASTER_DELAY_HALF_MEASURE_1_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_360__PHY_MASTER_DELAY_HALF_MEASURE_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_360__PHY_MASTER_DELAY_HALF_MEASURE_1_WIDTH 8U +#define LPDDR4__PHY_MASTER_DELAY_HALF_MEASURE_1__REG DENALI_PHY_360 +#define LPDDR4__PHY_MASTER_DELAY_HALF_MEASURE_1__FLD LPDDR4__DENALI_PHY_360__PHY_MASTER_DELAY_HALF_MEASURE_1 + +#define LPDDR4__DENALI_PHY_360__PHY_RPTR_UPDATE_1_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_360__PHY_RPTR_UPDATE_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_360__PHY_RPTR_UPDATE_1_WIDTH 4U +#define LPDDR4__PHY_RPTR_UPDATE_1__REG DENALI_PHY_360 +#define LPDDR4__PHY_RPTR_UPDATE_1__FLD LPDDR4__DENALI_PHY_360__PHY_RPTR_UPDATE_1 + +#define LPDDR4__DENALI_PHY_360__PHY_WRLVL_DLY_STEP_1_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_360__PHY_WRLVL_DLY_STEP_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_360__PHY_WRLVL_DLY_STEP_1_WIDTH 8U +#define LPDDR4__PHY_WRLVL_DLY_STEP_1__REG DENALI_PHY_360 +#define LPDDR4__PHY_WRLVL_DLY_STEP_1__FLD LPDDR4__DENALI_PHY_360__PHY_WRLVL_DLY_STEP_1 + +#define LPDDR4__DENALI_PHY_361_READ_MASK 0x1F0F3F0FU +#define LPDDR4__DENALI_PHY_361_WRITE_MASK 0x1F0F3F0FU +#define LPDDR4__DENALI_PHY_361__PHY_WRLVL_DLY_FINE_STEP_1_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_361__PHY_WRLVL_DLY_FINE_STEP_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_361__PHY_WRLVL_DLY_FINE_STEP_1_WIDTH 4U +#define LPDDR4__PHY_WRLVL_DLY_FINE_STEP_1__REG DENALI_PHY_361 +#define LPDDR4__PHY_WRLVL_DLY_FINE_STEP_1__FLD LPDDR4__DENALI_PHY_361__PHY_WRLVL_DLY_FINE_STEP_1 + +#define LPDDR4__DENALI_PHY_361__PHY_WRLVL_RESP_WAIT_CNT_1_MASK 0x00003F00U +#define LPDDR4__DENALI_PHY_361__PHY_WRLVL_RESP_WAIT_CNT_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_361__PHY_WRLVL_RESP_WAIT_CNT_1_WIDTH 6U +#define LPDDR4__PHY_WRLVL_RESP_WAIT_CNT_1__REG DENALI_PHY_361 +#define LPDDR4__PHY_WRLVL_RESP_WAIT_CNT_1__FLD LPDDR4__DENALI_PHY_361__PHY_WRLVL_RESP_WAIT_CNT_1 + +#define LPDDR4__DENALI_PHY_361__PHY_GTLVL_DLY_STEP_1_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_361__PHY_GTLVL_DLY_STEP_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_361__PHY_GTLVL_DLY_STEP_1_WIDTH 4U +#define LPDDR4__PHY_GTLVL_DLY_STEP_1__REG DENALI_PHY_361 +#define LPDDR4__PHY_GTLVL_DLY_STEP_1__FLD LPDDR4__DENALI_PHY_361__PHY_GTLVL_DLY_STEP_1 + +#define LPDDR4__DENALI_PHY_361__PHY_GTLVL_RESP_WAIT_CNT_1_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_361__PHY_GTLVL_RESP_WAIT_CNT_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_361__PHY_GTLVL_RESP_WAIT_CNT_1_WIDTH 5U +#define LPDDR4__PHY_GTLVL_RESP_WAIT_CNT_1__REG DENALI_PHY_361 +#define LPDDR4__PHY_GTLVL_RESP_WAIT_CNT_1__FLD LPDDR4__DENALI_PHY_361__PHY_GTLVL_RESP_WAIT_CNT_1 + +#define LPDDR4__DENALI_PHY_362_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_362_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_362__PHY_GTLVL_BACK_STEP_1_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_362__PHY_GTLVL_BACK_STEP_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_362__PHY_GTLVL_BACK_STEP_1_WIDTH 10U +#define LPDDR4__PHY_GTLVL_BACK_STEP_1__REG DENALI_PHY_362 +#define LPDDR4__PHY_GTLVL_BACK_STEP_1__FLD LPDDR4__DENALI_PHY_362__PHY_GTLVL_BACK_STEP_1 + +#define LPDDR4__DENALI_PHY_362__PHY_GTLVL_FINAL_STEP_1_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_362__PHY_GTLVL_FINAL_STEP_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_362__PHY_GTLVL_FINAL_STEP_1_WIDTH 10U +#define LPDDR4__PHY_GTLVL_FINAL_STEP_1__REG DENALI_PHY_362 +#define LPDDR4__PHY_GTLVL_FINAL_STEP_1__FLD LPDDR4__DENALI_PHY_362__PHY_GTLVL_FINAL_STEP_1 + +#define LPDDR4__DENALI_PHY_363_READ_MASK 0x0F010FFFU +#define LPDDR4__DENALI_PHY_363_WRITE_MASK 0x0F010FFFU +#define LPDDR4__DENALI_PHY_363__PHY_WDQLVL_DLY_STEP_1_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_363__PHY_WDQLVL_DLY_STEP_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_363__PHY_WDQLVL_DLY_STEP_1_WIDTH 8U +#define LPDDR4__PHY_WDQLVL_DLY_STEP_1__REG DENALI_PHY_363 +#define LPDDR4__PHY_WDQLVL_DLY_STEP_1__FLD LPDDR4__DENALI_PHY_363__PHY_WDQLVL_DLY_STEP_1 + +#define LPDDR4__DENALI_PHY_363__PHY_WDQLVL_QTR_DLY_STEP_1_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_363__PHY_WDQLVL_QTR_DLY_STEP_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_363__PHY_WDQLVL_QTR_DLY_STEP_1_WIDTH 4U +#define LPDDR4__PHY_WDQLVL_QTR_DLY_STEP_1__REG DENALI_PHY_363 +#define LPDDR4__PHY_WDQLVL_QTR_DLY_STEP_1__FLD LPDDR4__DENALI_PHY_363__PHY_WDQLVL_QTR_DLY_STEP_1 + +#define LPDDR4__DENALI_PHY_363__PHY_TOGGLE_PRE_SUPPORT_1_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_363__PHY_TOGGLE_PRE_SUPPORT_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_363__PHY_TOGGLE_PRE_SUPPORT_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_363__PHY_TOGGLE_PRE_SUPPORT_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_363__PHY_TOGGLE_PRE_SUPPORT_1_WOSET 0U +#define LPDDR4__PHY_TOGGLE_PRE_SUPPORT_1__REG DENALI_PHY_363 +#define LPDDR4__PHY_TOGGLE_PRE_SUPPORT_1__FLD LPDDR4__DENALI_PHY_363__PHY_TOGGLE_PRE_SUPPORT_1 + +#define LPDDR4__DENALI_PHY_363__PHY_RDLVL_DLY_STEP_1_MASK 0x0F000000U +#define LPDDR4__DENALI_PHY_363__PHY_RDLVL_DLY_STEP_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_363__PHY_RDLVL_DLY_STEP_1_WIDTH 4U +#define LPDDR4__PHY_RDLVL_DLY_STEP_1__REG DENALI_PHY_363 +#define LPDDR4__PHY_RDLVL_DLY_STEP_1__FLD LPDDR4__DENALI_PHY_363__PHY_RDLVL_DLY_STEP_1 + +#define LPDDR4__DENALI_PHY_364_READ_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_364_WRITE_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_364__PHY_RDLVL_MAX_EDGE_1_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_364__PHY_RDLVL_MAX_EDGE_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_364__PHY_RDLVL_MAX_EDGE_1_WIDTH 10U +#define LPDDR4__PHY_RDLVL_MAX_EDGE_1__REG DENALI_PHY_364 +#define LPDDR4__PHY_RDLVL_MAX_EDGE_1__FLD LPDDR4__DENALI_PHY_364__PHY_RDLVL_MAX_EDGE_1 + +#define LPDDR4__DENALI_PHY_365_READ_MASK 0x3F0103FFU +#define LPDDR4__DENALI_PHY_365_WRITE_MASK 0x3F0103FFU +#define LPDDR4__DENALI_PHY_365__PHY_RDLVL_DVW_MIN_1_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_365__PHY_RDLVL_DVW_MIN_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_365__PHY_RDLVL_DVW_MIN_1_WIDTH 10U +#define LPDDR4__PHY_RDLVL_DVW_MIN_1__REG DENALI_PHY_365 +#define LPDDR4__PHY_RDLVL_DVW_MIN_1__FLD LPDDR4__DENALI_PHY_365__PHY_RDLVL_DVW_MIN_1 + +#define LPDDR4__DENALI_PHY_365__PHY_SW_RDLVL_DVW_MIN_EN_1_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_365__PHY_SW_RDLVL_DVW_MIN_EN_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_365__PHY_SW_RDLVL_DVW_MIN_EN_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_365__PHY_SW_RDLVL_DVW_MIN_EN_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_365__PHY_SW_RDLVL_DVW_MIN_EN_1_WOSET 0U +#define LPDDR4__PHY_SW_RDLVL_DVW_MIN_EN_1__REG DENALI_PHY_365 +#define LPDDR4__PHY_SW_RDLVL_DVW_MIN_EN_1__FLD LPDDR4__DENALI_PHY_365__PHY_SW_RDLVL_DVW_MIN_EN_1 + +#define LPDDR4__DENALI_PHY_365__PHY_RDLVL_PER_START_OFFSET_1_MASK 0x3F000000U +#define LPDDR4__DENALI_PHY_365__PHY_RDLVL_PER_START_OFFSET_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_365__PHY_RDLVL_PER_START_OFFSET_1_WIDTH 6U +#define LPDDR4__PHY_RDLVL_PER_START_OFFSET_1__REG DENALI_PHY_365 +#define LPDDR4__PHY_RDLVL_PER_START_OFFSET_1__FLD LPDDR4__DENALI_PHY_365__PHY_RDLVL_PER_START_OFFSET_1 + +#define LPDDR4__DENALI_PHY_366_READ_MASK 0x00030703U +#define LPDDR4__DENALI_PHY_366_WRITE_MASK 0x00030703U +#define LPDDR4__DENALI_PHY_366__PHY_WRPATH_GATE_DISABLE_1_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_366__PHY_WRPATH_GATE_DISABLE_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_366__PHY_WRPATH_GATE_DISABLE_1_WIDTH 2U +#define LPDDR4__PHY_WRPATH_GATE_DISABLE_1__REG DENALI_PHY_366 +#define LPDDR4__PHY_WRPATH_GATE_DISABLE_1__FLD LPDDR4__DENALI_PHY_366__PHY_WRPATH_GATE_DISABLE_1 + +#define LPDDR4__DENALI_PHY_366__PHY_WRPATH_GATE_TIMING_1_MASK 0x00000700U +#define LPDDR4__DENALI_PHY_366__PHY_WRPATH_GATE_TIMING_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_366__PHY_WRPATH_GATE_TIMING_1_WIDTH 3U +#define LPDDR4__PHY_WRPATH_GATE_TIMING_1__REG DENALI_PHY_366 +#define LPDDR4__PHY_WRPATH_GATE_TIMING_1__FLD LPDDR4__DENALI_PHY_366__PHY_WRPATH_GATE_TIMING_1 + +#define LPDDR4__DENALI_PHY_366__PHY_DATA_DC_INIT_DISABLE_1_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_366__PHY_DATA_DC_INIT_DISABLE_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_366__PHY_DATA_DC_INIT_DISABLE_1_WIDTH 2U +#define LPDDR4__PHY_DATA_DC_INIT_DISABLE_1__REG DENALI_PHY_366 +#define LPDDR4__PHY_DATA_DC_INIT_DISABLE_1__FLD LPDDR4__DENALI_PHY_366__PHY_DATA_DC_INIT_DISABLE_1 + +#define LPDDR4__DENALI_PHY_367_READ_MASK 0x07FF03FFU +#define LPDDR4__DENALI_PHY_367_WRITE_MASK 0x07FF03FFU +#define LPDDR4__DENALI_PHY_367__PHY_DATA_DC_DQS_INIT_SLV_DELAY_1_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_367__PHY_DATA_DC_DQS_INIT_SLV_DELAY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_367__PHY_DATA_DC_DQS_INIT_SLV_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_DATA_DC_DQS_INIT_SLV_DELAY_1__REG DENALI_PHY_367 +#define LPDDR4__PHY_DATA_DC_DQS_INIT_SLV_DELAY_1__FLD LPDDR4__DENALI_PHY_367__PHY_DATA_DC_DQS_INIT_SLV_DELAY_1 + +#define LPDDR4__DENALI_PHY_367__PHY_DATA_DC_DQ_INIT_SLV_DELAY_1_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_367__PHY_DATA_DC_DQ_INIT_SLV_DELAY_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_367__PHY_DATA_DC_DQ_INIT_SLV_DELAY_1_WIDTH 11U +#define LPDDR4__PHY_DATA_DC_DQ_INIT_SLV_DELAY_1__REG DENALI_PHY_367 +#define LPDDR4__PHY_DATA_DC_DQ_INIT_SLV_DELAY_1__FLD LPDDR4__DENALI_PHY_367__PHY_DATA_DC_DQ_INIT_SLV_DELAY_1 + +#define LPDDR4__DENALI_PHY_368_READ_MASK 0xFFFF0101U +#define LPDDR4__DENALI_PHY_368_WRITE_MASK 0xFFFF0101U +#define LPDDR4__DENALI_PHY_368__PHY_DATA_DC_WRLVL_ENABLE_1_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_368__PHY_DATA_DC_WRLVL_ENABLE_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_368__PHY_DATA_DC_WRLVL_ENABLE_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_368__PHY_DATA_DC_WRLVL_ENABLE_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_368__PHY_DATA_DC_WRLVL_ENABLE_1_WOSET 0U +#define LPDDR4__PHY_DATA_DC_WRLVL_ENABLE_1__REG DENALI_PHY_368 +#define LPDDR4__PHY_DATA_DC_WRLVL_ENABLE_1__FLD LPDDR4__DENALI_PHY_368__PHY_DATA_DC_WRLVL_ENABLE_1 + +#define LPDDR4__DENALI_PHY_368__PHY_DATA_DC_WDQLVL_ENABLE_1_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_368__PHY_DATA_DC_WDQLVL_ENABLE_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_368__PHY_DATA_DC_WDQLVL_ENABLE_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_368__PHY_DATA_DC_WDQLVL_ENABLE_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_368__PHY_DATA_DC_WDQLVL_ENABLE_1_WOSET 0U +#define LPDDR4__PHY_DATA_DC_WDQLVL_ENABLE_1__REG DENALI_PHY_368 +#define LPDDR4__PHY_DATA_DC_WDQLVL_ENABLE_1__FLD LPDDR4__DENALI_PHY_368__PHY_DATA_DC_WDQLVL_ENABLE_1 + +#define LPDDR4__DENALI_PHY_368__PHY_DATA_DC_DM_CLK_SE_THRSHLD_1_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_368__PHY_DATA_DC_DM_CLK_SE_THRSHLD_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_368__PHY_DATA_DC_DM_CLK_SE_THRSHLD_1_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DM_CLK_SE_THRSHLD_1__REG DENALI_PHY_368 +#define LPDDR4__PHY_DATA_DC_DM_CLK_SE_THRSHLD_1__FLD LPDDR4__DENALI_PHY_368__PHY_DATA_DC_DM_CLK_SE_THRSHLD_1 + +#define LPDDR4__DENALI_PHY_368__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_1_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_368__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_368__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_1_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_1__REG DENALI_PHY_368 +#define LPDDR4__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_1__FLD LPDDR4__DENALI_PHY_368__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_1 + +#define LPDDR4__DENALI_PHY_369_READ_MASK 0x001F3F7FU +#define LPDDR4__DENALI_PHY_369_WRITE_MASK 0x001F3F7FU +#define LPDDR4__DENALI_PHY_369__PHY_WDQ_OSC_DELTA_1_MASK 0x0000007FU +#define LPDDR4__DENALI_PHY_369__PHY_WDQ_OSC_DELTA_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_369__PHY_WDQ_OSC_DELTA_1_WIDTH 7U +#define LPDDR4__PHY_WDQ_OSC_DELTA_1__REG DENALI_PHY_369 +#define LPDDR4__PHY_WDQ_OSC_DELTA_1__FLD LPDDR4__DENALI_PHY_369__PHY_WDQ_OSC_DELTA_1 + +#define LPDDR4__DENALI_PHY_369__PHY_MEAS_DLY_STEP_ENABLE_1_MASK 0x00003F00U +#define LPDDR4__DENALI_PHY_369__PHY_MEAS_DLY_STEP_ENABLE_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_369__PHY_MEAS_DLY_STEP_ENABLE_1_WIDTH 6U +#define LPDDR4__PHY_MEAS_DLY_STEP_ENABLE_1__REG DENALI_PHY_369 +#define LPDDR4__PHY_MEAS_DLY_STEP_ENABLE_1__FLD LPDDR4__DENALI_PHY_369__PHY_MEAS_DLY_STEP_ENABLE_1 + +#define LPDDR4__DENALI_PHY_369__PHY_RDDATA_EN_DLY_1_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_369__PHY_RDDATA_EN_DLY_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_369__PHY_RDDATA_EN_DLY_1_WIDTH 5U +#define LPDDR4__PHY_RDDATA_EN_DLY_1__REG DENALI_PHY_369 +#define LPDDR4__PHY_RDDATA_EN_DLY_1__FLD LPDDR4__DENALI_PHY_369__PHY_RDDATA_EN_DLY_1 + +#define LPDDR4__DENALI_PHY_370_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_370_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_370__PHY_DQ_DM_SWIZZLE0_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_370__PHY_DQ_DM_SWIZZLE0_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_370__PHY_DQ_DM_SWIZZLE0_1_WIDTH 32U +#define LPDDR4__PHY_DQ_DM_SWIZZLE0_1__REG DENALI_PHY_370 +#define LPDDR4__PHY_DQ_DM_SWIZZLE0_1__FLD LPDDR4__DENALI_PHY_370__PHY_DQ_DM_SWIZZLE0_1 + +#define LPDDR4__DENALI_PHY_371_READ_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_371_WRITE_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_371__PHY_DQ_DM_SWIZZLE1_1_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_371__PHY_DQ_DM_SWIZZLE1_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_371__PHY_DQ_DM_SWIZZLE1_1_WIDTH 4U +#define LPDDR4__PHY_DQ_DM_SWIZZLE1_1__REG DENALI_PHY_371 +#define LPDDR4__PHY_DQ_DM_SWIZZLE1_1__FLD LPDDR4__DENALI_PHY_371__PHY_DQ_DM_SWIZZLE1_1 + +#define LPDDR4__DENALI_PHY_372_READ_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_372_WRITE_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_372__PHY_CLK_WRDQ0_SLAVE_DELAY_1_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_372__PHY_CLK_WRDQ0_SLAVE_DELAY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_372__PHY_CLK_WRDQ0_SLAVE_DELAY_1_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDQ0_SLAVE_DELAY_1__REG DENALI_PHY_372 +#define LPDDR4__PHY_CLK_WRDQ0_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_372__PHY_CLK_WRDQ0_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_372__PHY_CLK_WRDQ1_SLAVE_DELAY_1_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_372__PHY_CLK_WRDQ1_SLAVE_DELAY_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_372__PHY_CLK_WRDQ1_SLAVE_DELAY_1_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDQ1_SLAVE_DELAY_1__REG DENALI_PHY_372 +#define LPDDR4__PHY_CLK_WRDQ1_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_372__PHY_CLK_WRDQ1_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_373_READ_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_373_WRITE_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_373__PHY_CLK_WRDQ2_SLAVE_DELAY_1_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_373__PHY_CLK_WRDQ2_SLAVE_DELAY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_373__PHY_CLK_WRDQ2_SLAVE_DELAY_1_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDQ2_SLAVE_DELAY_1__REG DENALI_PHY_373 +#define LPDDR4__PHY_CLK_WRDQ2_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_373__PHY_CLK_WRDQ2_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_373__PHY_CLK_WRDQ3_SLAVE_DELAY_1_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_373__PHY_CLK_WRDQ3_SLAVE_DELAY_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_373__PHY_CLK_WRDQ3_SLAVE_DELAY_1_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDQ3_SLAVE_DELAY_1__REG DENALI_PHY_373 +#define LPDDR4__PHY_CLK_WRDQ3_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_373__PHY_CLK_WRDQ3_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_374_READ_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_374_WRITE_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_374__PHY_CLK_WRDQ4_SLAVE_DELAY_1_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_374__PHY_CLK_WRDQ4_SLAVE_DELAY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_374__PHY_CLK_WRDQ4_SLAVE_DELAY_1_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDQ4_SLAVE_DELAY_1__REG DENALI_PHY_374 +#define LPDDR4__PHY_CLK_WRDQ4_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_374__PHY_CLK_WRDQ4_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_374__PHY_CLK_WRDQ5_SLAVE_DELAY_1_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_374__PHY_CLK_WRDQ5_SLAVE_DELAY_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_374__PHY_CLK_WRDQ5_SLAVE_DELAY_1_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDQ5_SLAVE_DELAY_1__REG DENALI_PHY_374 +#define LPDDR4__PHY_CLK_WRDQ5_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_374__PHY_CLK_WRDQ5_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_375_READ_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_375_WRITE_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_375__PHY_CLK_WRDQ6_SLAVE_DELAY_1_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_375__PHY_CLK_WRDQ6_SLAVE_DELAY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_375__PHY_CLK_WRDQ6_SLAVE_DELAY_1_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDQ6_SLAVE_DELAY_1__REG DENALI_PHY_375 +#define LPDDR4__PHY_CLK_WRDQ6_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_375__PHY_CLK_WRDQ6_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_375__PHY_CLK_WRDQ7_SLAVE_DELAY_1_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_375__PHY_CLK_WRDQ7_SLAVE_DELAY_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_375__PHY_CLK_WRDQ7_SLAVE_DELAY_1_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDQ7_SLAVE_DELAY_1__REG DENALI_PHY_375 +#define LPDDR4__PHY_CLK_WRDQ7_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_375__PHY_CLK_WRDQ7_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_376_READ_MASK 0x03FF07FFU +#define LPDDR4__DENALI_PHY_376_WRITE_MASK 0x03FF07FFU +#define LPDDR4__DENALI_PHY_376__PHY_CLK_WRDM_SLAVE_DELAY_1_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_376__PHY_CLK_WRDM_SLAVE_DELAY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_376__PHY_CLK_WRDM_SLAVE_DELAY_1_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDM_SLAVE_DELAY_1__REG DENALI_PHY_376 +#define LPDDR4__PHY_CLK_WRDM_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_376__PHY_CLK_WRDM_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_376__PHY_CLK_WRDQS_SLAVE_DELAY_1_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_376__PHY_CLK_WRDQS_SLAVE_DELAY_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_376__PHY_CLK_WRDQS_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_1__REG DENALI_PHY_376 +#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_376__PHY_CLK_WRDQS_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_377_READ_MASK 0x0003FF03U +#define LPDDR4__DENALI_PHY_377_WRITE_MASK 0x0003FF03U +#define LPDDR4__DENALI_PHY_377__PHY_WRLVL_THRESHOLD_ADJUST_1_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_377__PHY_WRLVL_THRESHOLD_ADJUST_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_377__PHY_WRLVL_THRESHOLD_ADJUST_1_WIDTH 2U +#define LPDDR4__PHY_WRLVL_THRESHOLD_ADJUST_1__REG DENALI_PHY_377 +#define LPDDR4__PHY_WRLVL_THRESHOLD_ADJUST_1__FLD LPDDR4__DENALI_PHY_377__PHY_WRLVL_THRESHOLD_ADJUST_1 + +#define LPDDR4__DENALI_PHY_377__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_1_MASK 0x0003FF00U +#define LPDDR4__DENALI_PHY_377__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_377__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_1__REG DENALI_PHY_377 +#define LPDDR4__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_377__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_378_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_378_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_378__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_1_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_378__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_378__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_1__REG DENALI_PHY_378 +#define LPDDR4__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_378__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_378__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_1_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_378__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_378__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_1__REG DENALI_PHY_378 +#define LPDDR4__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_378__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_379_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_379_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_379__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_1_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_379__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_379__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_1__REG DENALI_PHY_379 +#define LPDDR4__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_379__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_379__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_1_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_379__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_379__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_1__REG DENALI_PHY_379 +#define LPDDR4__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_379__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_380_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_380_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_380__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_1_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_380__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_380__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_1__REG DENALI_PHY_380 +#define LPDDR4__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_380__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_380__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_1_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_380__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_380__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_1__REG DENALI_PHY_380 +#define LPDDR4__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_380__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_381_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_381_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_381__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_1_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_381__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_381__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_1__REG DENALI_PHY_381 +#define LPDDR4__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_381__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_381__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_1_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_381__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_381__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_1__REG DENALI_PHY_381 +#define LPDDR4__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_381__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_382_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_382_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_382__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_1_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_382__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_382__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_1__REG DENALI_PHY_382 +#define LPDDR4__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_382__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_382__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_1_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_382__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_382__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_1__REG DENALI_PHY_382 +#define LPDDR4__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_382__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_383_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_383_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_383__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_1_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_383__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_383__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_1__REG DENALI_PHY_383 +#define LPDDR4__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_383__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_383__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_1_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_383__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_383__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_1__REG DENALI_PHY_383 +#define LPDDR4__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_383__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_384_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_384_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_384__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_1_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_384__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_384__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_1__REG DENALI_PHY_384 +#define LPDDR4__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_384__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_384__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_1_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_384__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_384__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_1__REG DENALI_PHY_384 +#define LPDDR4__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_384__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_385_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_385_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_385__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_1_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_385__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_385__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_1__REG DENALI_PHY_385 +#define LPDDR4__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_385__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_385__PHY_RDDQS_DM_RISE_SLAVE_DELAY_1_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_385__PHY_RDDQS_DM_RISE_SLAVE_DELAY_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_385__PHY_RDDQS_DM_RISE_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DM_RISE_SLAVE_DELAY_1__REG DENALI_PHY_385 +#define LPDDR4__PHY_RDDQS_DM_RISE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_385__PHY_RDDQS_DM_RISE_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_386_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_386_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_386__PHY_RDDQS_DM_FALL_SLAVE_DELAY_1_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_386__PHY_RDDQS_DM_FALL_SLAVE_DELAY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_386__PHY_RDDQS_DM_FALL_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DM_FALL_SLAVE_DELAY_1__REG DENALI_PHY_386 +#define LPDDR4__PHY_RDDQS_DM_FALL_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_386__PHY_RDDQS_DM_FALL_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_386__PHY_RDDQS_GATE_SLAVE_DELAY_1_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_386__PHY_RDDQS_GATE_SLAVE_DELAY_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_386__PHY_RDDQS_GATE_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDQS_GATE_SLAVE_DELAY_1__REG DENALI_PHY_386 +#define LPDDR4__PHY_RDDQS_GATE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_386__PHY_RDDQS_GATE_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_387_READ_MASK 0x03FF070FU +#define LPDDR4__DENALI_PHY_387_WRITE_MASK 0x03FF070FU +#define LPDDR4__DENALI_PHY_387__PHY_RDDQS_LATENCY_ADJUST_1_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_387__PHY_RDDQS_LATENCY_ADJUST_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_387__PHY_RDDQS_LATENCY_ADJUST_1_WIDTH 4U +#define LPDDR4__PHY_RDDQS_LATENCY_ADJUST_1__REG DENALI_PHY_387 +#define LPDDR4__PHY_RDDQS_LATENCY_ADJUST_1__FLD LPDDR4__DENALI_PHY_387__PHY_RDDQS_LATENCY_ADJUST_1 + +#define LPDDR4__DENALI_PHY_387__PHY_WRITE_PATH_LAT_ADD_1_MASK 0x00000700U +#define LPDDR4__DENALI_PHY_387__PHY_WRITE_PATH_LAT_ADD_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_387__PHY_WRITE_PATH_LAT_ADD_1_WIDTH 3U +#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_1__REG DENALI_PHY_387 +#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_1__FLD LPDDR4__DENALI_PHY_387__PHY_WRITE_PATH_LAT_ADD_1 + +#define LPDDR4__DENALI_PHY_387__PHY_WRLVL_DELAY_EARLY_THRESHOLD_1_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_387__PHY_WRLVL_DELAY_EARLY_THRESHOLD_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_387__PHY_WRLVL_DELAY_EARLY_THRESHOLD_1_WIDTH 10U +#define LPDDR4__PHY_WRLVL_DELAY_EARLY_THRESHOLD_1__REG DENALI_PHY_387 +#define LPDDR4__PHY_WRLVL_DELAY_EARLY_THRESHOLD_1__FLD LPDDR4__DENALI_PHY_387__PHY_WRLVL_DELAY_EARLY_THRESHOLD_1 + +#define LPDDR4__DENALI_PHY_388_READ_MASK 0x000103FFU +#define LPDDR4__DENALI_PHY_388_WRITE_MASK 0x000103FFU +#define LPDDR4__DENALI_PHY_388__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_1_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_388__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_388__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_1_WIDTH 10U +#define LPDDR4__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_1__REG DENALI_PHY_388 +#define LPDDR4__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_1__FLD LPDDR4__DENALI_PHY_388__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_1 + +#define LPDDR4__DENALI_PHY_388__PHY_WRLVL_EARLY_FORCE_ZERO_1_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_388__PHY_WRLVL_EARLY_FORCE_ZERO_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_388__PHY_WRLVL_EARLY_FORCE_ZERO_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_388__PHY_WRLVL_EARLY_FORCE_ZERO_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_388__PHY_WRLVL_EARLY_FORCE_ZERO_1_WOSET 0U +#define LPDDR4__PHY_WRLVL_EARLY_FORCE_ZERO_1__REG DENALI_PHY_388 +#define LPDDR4__PHY_WRLVL_EARLY_FORCE_ZERO_1__FLD LPDDR4__DENALI_PHY_388__PHY_WRLVL_EARLY_FORCE_ZERO_1 + +#define LPDDR4__DENALI_PHY_389_READ_MASK 0x000F03FFU +#define LPDDR4__DENALI_PHY_389_WRITE_MASK 0x000F03FFU +#define LPDDR4__DENALI_PHY_389__PHY_GTLVL_RDDQS_SLV_DLY_START_1_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_389__PHY_GTLVL_RDDQS_SLV_DLY_START_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_389__PHY_GTLVL_RDDQS_SLV_DLY_START_1_WIDTH 10U +#define LPDDR4__PHY_GTLVL_RDDQS_SLV_DLY_START_1__REG DENALI_PHY_389 +#define LPDDR4__PHY_GTLVL_RDDQS_SLV_DLY_START_1__FLD LPDDR4__DENALI_PHY_389__PHY_GTLVL_RDDQS_SLV_DLY_START_1 + +#define LPDDR4__DENALI_PHY_389__PHY_GTLVL_LAT_ADJ_START_1_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_389__PHY_GTLVL_LAT_ADJ_START_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_389__PHY_GTLVL_LAT_ADJ_START_1_WIDTH 4U +#define LPDDR4__PHY_GTLVL_LAT_ADJ_START_1__REG DENALI_PHY_389 +#define LPDDR4__PHY_GTLVL_LAT_ADJ_START_1__FLD LPDDR4__DENALI_PHY_389__PHY_GTLVL_LAT_ADJ_START_1 + +#define LPDDR4__DENALI_PHY_390_READ_MASK 0x010F07FFU +#define LPDDR4__DENALI_PHY_390_WRITE_MASK 0x010F07FFU +#define LPDDR4__DENALI_PHY_390__PHY_WDQLVL_DQDM_SLV_DLY_START_1_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_390__PHY_WDQLVL_DQDM_SLV_DLY_START_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_390__PHY_WDQLVL_DQDM_SLV_DLY_START_1_WIDTH 11U +#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_START_1__REG DENALI_PHY_390 +#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_START_1__FLD LPDDR4__DENALI_PHY_390__PHY_WDQLVL_DQDM_SLV_DLY_START_1 + +#define LPDDR4__DENALI_PHY_390__PHY_NTP_WRLAT_START_1_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_390__PHY_NTP_WRLAT_START_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_390__PHY_NTP_WRLAT_START_1_WIDTH 4U +#define LPDDR4__PHY_NTP_WRLAT_START_1__REG DENALI_PHY_390 +#define LPDDR4__PHY_NTP_WRLAT_START_1__FLD LPDDR4__DENALI_PHY_390__PHY_NTP_WRLAT_START_1 + +#define LPDDR4__DENALI_PHY_390__PHY_NTP_PASS_1_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_390__PHY_NTP_PASS_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_390__PHY_NTP_PASS_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_390__PHY_NTP_PASS_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_390__PHY_NTP_PASS_1_WOSET 0U +#define LPDDR4__PHY_NTP_PASS_1__REG DENALI_PHY_390 +#define LPDDR4__PHY_NTP_PASS_1__FLD LPDDR4__DENALI_PHY_390__PHY_NTP_PASS_1 + +#define LPDDR4__DENALI_PHY_391_READ_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_391_WRITE_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_391__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_1_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_391__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_391__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_1_WIDTH 10U +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_1__REG DENALI_PHY_391 +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_1__FLD LPDDR4__DENALI_PHY_391__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_1 + +#define LPDDR4__DENALI_PHY_392_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_392_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_392__PHY_DATA_DC_DQS_CLK_ADJUST_1_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_392__PHY_DATA_DC_DQS_CLK_ADJUST_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_392__PHY_DATA_DC_DQS_CLK_ADJUST_1_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DQS_CLK_ADJUST_1__REG DENALI_PHY_392 +#define LPDDR4__PHY_DATA_DC_DQS_CLK_ADJUST_1__FLD LPDDR4__DENALI_PHY_392__PHY_DATA_DC_DQS_CLK_ADJUST_1 + +#define LPDDR4__DENALI_PHY_392__PHY_DATA_DC_DQ0_CLK_ADJUST_1_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_392__PHY_DATA_DC_DQ0_CLK_ADJUST_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_392__PHY_DATA_DC_DQ0_CLK_ADJUST_1_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DQ0_CLK_ADJUST_1__REG DENALI_PHY_392 +#define LPDDR4__PHY_DATA_DC_DQ0_CLK_ADJUST_1__FLD LPDDR4__DENALI_PHY_392__PHY_DATA_DC_DQ0_CLK_ADJUST_1 + +#define LPDDR4__DENALI_PHY_392__PHY_DATA_DC_DQ1_CLK_ADJUST_1_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_392__PHY_DATA_DC_DQ1_CLK_ADJUST_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_392__PHY_DATA_DC_DQ1_CLK_ADJUST_1_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DQ1_CLK_ADJUST_1__REG DENALI_PHY_392 +#define LPDDR4__PHY_DATA_DC_DQ1_CLK_ADJUST_1__FLD LPDDR4__DENALI_PHY_392__PHY_DATA_DC_DQ1_CLK_ADJUST_1 + +#define LPDDR4__DENALI_PHY_392__PHY_DATA_DC_DQ2_CLK_ADJUST_1_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_392__PHY_DATA_DC_DQ2_CLK_ADJUST_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_392__PHY_DATA_DC_DQ2_CLK_ADJUST_1_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DQ2_CLK_ADJUST_1__REG DENALI_PHY_392 +#define LPDDR4__PHY_DATA_DC_DQ2_CLK_ADJUST_1__FLD LPDDR4__DENALI_PHY_392__PHY_DATA_DC_DQ2_CLK_ADJUST_1 + +#define LPDDR4__DENALI_PHY_393_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_393_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_393__PHY_DATA_DC_DQ3_CLK_ADJUST_1_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_393__PHY_DATA_DC_DQ3_CLK_ADJUST_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_393__PHY_DATA_DC_DQ3_CLK_ADJUST_1_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DQ3_CLK_ADJUST_1__REG DENALI_PHY_393 +#define LPDDR4__PHY_DATA_DC_DQ3_CLK_ADJUST_1__FLD LPDDR4__DENALI_PHY_393__PHY_DATA_DC_DQ3_CLK_ADJUST_1 + +#define LPDDR4__DENALI_PHY_393__PHY_DATA_DC_DQ4_CLK_ADJUST_1_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_393__PHY_DATA_DC_DQ4_CLK_ADJUST_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_393__PHY_DATA_DC_DQ4_CLK_ADJUST_1_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DQ4_CLK_ADJUST_1__REG DENALI_PHY_393 +#define LPDDR4__PHY_DATA_DC_DQ4_CLK_ADJUST_1__FLD LPDDR4__DENALI_PHY_393__PHY_DATA_DC_DQ4_CLK_ADJUST_1 + +#define LPDDR4__DENALI_PHY_393__PHY_DATA_DC_DQ5_CLK_ADJUST_1_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_393__PHY_DATA_DC_DQ5_CLK_ADJUST_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_393__PHY_DATA_DC_DQ5_CLK_ADJUST_1_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DQ5_CLK_ADJUST_1__REG DENALI_PHY_393 +#define LPDDR4__PHY_DATA_DC_DQ5_CLK_ADJUST_1__FLD LPDDR4__DENALI_PHY_393__PHY_DATA_DC_DQ5_CLK_ADJUST_1 + +#define LPDDR4__DENALI_PHY_393__PHY_DATA_DC_DQ6_CLK_ADJUST_1_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_393__PHY_DATA_DC_DQ6_CLK_ADJUST_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_393__PHY_DATA_DC_DQ6_CLK_ADJUST_1_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DQ6_CLK_ADJUST_1__REG DENALI_PHY_393 +#define LPDDR4__PHY_DATA_DC_DQ6_CLK_ADJUST_1__FLD LPDDR4__DENALI_PHY_393__PHY_DATA_DC_DQ6_CLK_ADJUST_1 + +#define LPDDR4__DENALI_PHY_394_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_394_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_394__PHY_DATA_DC_DQ7_CLK_ADJUST_1_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_394__PHY_DATA_DC_DQ7_CLK_ADJUST_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_394__PHY_DATA_DC_DQ7_CLK_ADJUST_1_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DQ7_CLK_ADJUST_1__REG DENALI_PHY_394 +#define LPDDR4__PHY_DATA_DC_DQ7_CLK_ADJUST_1__FLD LPDDR4__DENALI_PHY_394__PHY_DATA_DC_DQ7_CLK_ADJUST_1 + +#define LPDDR4__DENALI_PHY_394__PHY_DATA_DC_DM_CLK_ADJUST_1_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_394__PHY_DATA_DC_DM_CLK_ADJUST_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_394__PHY_DATA_DC_DM_CLK_ADJUST_1_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DM_CLK_ADJUST_1__REG DENALI_PHY_394 +#define LPDDR4__PHY_DATA_DC_DM_CLK_ADJUST_1__FLD LPDDR4__DENALI_PHY_394__PHY_DATA_DC_DM_CLK_ADJUST_1 + +#define LPDDR4__DENALI_PHY_394__PHY_DSLICE_PAD_BOOSTPN_SETTING_1_MASK 0xFFFF0000U +#define LPDDR4__DENALI_PHY_394__PHY_DSLICE_PAD_BOOSTPN_SETTING_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_394__PHY_DSLICE_PAD_BOOSTPN_SETTING_1_WIDTH 16U +#define LPDDR4__PHY_DSLICE_PAD_BOOSTPN_SETTING_1__REG DENALI_PHY_394 +#define LPDDR4__PHY_DSLICE_PAD_BOOSTPN_SETTING_1__FLD LPDDR4__DENALI_PHY_394__PHY_DSLICE_PAD_BOOSTPN_SETTING_1 + +#define LPDDR4__DENALI_PHY_395_READ_MASK 0x0003033FU +#define LPDDR4__DENALI_PHY_395_WRITE_MASK 0x0003033FU +#define LPDDR4__DENALI_PHY_395__PHY_DSLICE_PAD_RX_CTLE_SETTING_1_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_395__PHY_DSLICE_PAD_RX_CTLE_SETTING_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_395__PHY_DSLICE_PAD_RX_CTLE_SETTING_1_WIDTH 6U +#define LPDDR4__PHY_DSLICE_PAD_RX_CTLE_SETTING_1__REG DENALI_PHY_395 +#define LPDDR4__PHY_DSLICE_PAD_RX_CTLE_SETTING_1__FLD LPDDR4__DENALI_PHY_395__PHY_DSLICE_PAD_RX_CTLE_SETTING_1 + +#define LPDDR4__DENALI_PHY_395__PHY_DQ_FFE_1_MASK 0x00000300U +#define LPDDR4__DENALI_PHY_395__PHY_DQ_FFE_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_395__PHY_DQ_FFE_1_WIDTH 2U +#define LPDDR4__PHY_DQ_FFE_1__REG DENALI_PHY_395 +#define LPDDR4__PHY_DQ_FFE_1__FLD LPDDR4__DENALI_PHY_395__PHY_DQ_FFE_1 + +#define LPDDR4__DENALI_PHY_395__PHY_DQS_FFE_1_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_395__PHY_DQS_FFE_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_395__PHY_DQS_FFE_1_WIDTH 2U +#define LPDDR4__PHY_DQS_FFE_1__REG DENALI_PHY_395 +#define LPDDR4__PHY_DQS_FFE_1__FLD LPDDR4__DENALI_PHY_395__PHY_DQS_FFE_1 + +#endif /* REG_LPDDR4_DATA_SLICE_1_MACROS_H_ */ diff --git a/drivers/ram/k3-j721e/lpddr4_data_slice_2_macros.h b/drivers/ram/k3-j721e/lpddr4_data_slice_2_macros.h new file mode 100644 index 0000000..7c3756c --- /dev/null +++ b/drivers/ram/k3-j721e/lpddr4_data_slice_2_macros.h @@ -0,0 +1,2373 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/********************************************************************** + * Copyright (C) 2012-2019 Cadence Design Systems, Inc. + * + * THIS FILE IS AUTOMATICALLY GENERATED, DO NOT EDIT + * + ********************************************************************** + */ + +#ifndef REG_LPDDR4_DATA_SLICE_2_MACROS_H_ +#define REG_LPDDR4_DATA_SLICE_2_MACROS_H_ + +#define LPDDR4__DENALI_PHY_512_READ_MASK 0x000F07FFU +#define LPDDR4__DENALI_PHY_512_WRITE_MASK 0x000F07FFU +#define LPDDR4__DENALI_PHY_512__PHY_CLK_WR_BYPASS_SLAVE_DELAY_2_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_512__PHY_CLK_WR_BYPASS_SLAVE_DELAY_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_512__PHY_CLK_WR_BYPASS_SLAVE_DELAY_2_WIDTH 11U +#define LPDDR4__PHY_CLK_WR_BYPASS_SLAVE_DELAY_2__REG DENALI_PHY_512 +#define LPDDR4__PHY_CLK_WR_BYPASS_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_512__PHY_CLK_WR_BYPASS_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_512__PHY_IO_PAD_DELAY_TIMING_BYPASS_2_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_512__PHY_IO_PAD_DELAY_TIMING_BYPASS_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_512__PHY_IO_PAD_DELAY_TIMING_BYPASS_2_WIDTH 4U +#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_BYPASS_2__REG DENALI_PHY_512 +#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_BYPASS_2__FLD LPDDR4__DENALI_PHY_512__PHY_IO_PAD_DELAY_TIMING_BYPASS_2 + +#define LPDDR4__DENALI_PHY_513_READ_MASK 0x000703FFU +#define LPDDR4__DENALI_PHY_513_WRITE_MASK 0x000703FFU +#define LPDDR4__DENALI_PHY_513__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_2_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_513__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_513__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_2_WIDTH 10U +#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_2__REG DENALI_PHY_513 +#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_2__FLD LPDDR4__DENALI_PHY_513__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_2 + +#define LPDDR4__DENALI_PHY_513__PHY_WRITE_PATH_LAT_ADD_BYPASS_2_MASK 0x00070000U +#define LPDDR4__DENALI_PHY_513__PHY_WRITE_PATH_LAT_ADD_BYPASS_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_513__PHY_WRITE_PATH_LAT_ADD_BYPASS_2_WIDTH 3U +#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_BYPASS_2__REG DENALI_PHY_513 +#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_BYPASS_2__FLD LPDDR4__DENALI_PHY_513__PHY_WRITE_PATH_LAT_ADD_BYPASS_2 + +#define LPDDR4__DENALI_PHY_514_READ_MASK 0x010303FFU +#define LPDDR4__DENALI_PHY_514_WRITE_MASK 0x010303FFU +#define LPDDR4__DENALI_PHY_514__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_2_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_514__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_514__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_2_WIDTH 10U +#define LPDDR4__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_2__REG DENALI_PHY_514 +#define LPDDR4__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_514__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_514__PHY_BYPASS_TWO_CYC_PREAMBLE_2_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_514__PHY_BYPASS_TWO_CYC_PREAMBLE_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_514__PHY_BYPASS_TWO_CYC_PREAMBLE_2_WIDTH 2U +#define LPDDR4__PHY_BYPASS_TWO_CYC_PREAMBLE_2__REG DENALI_PHY_514 +#define LPDDR4__PHY_BYPASS_TWO_CYC_PREAMBLE_2__FLD LPDDR4__DENALI_PHY_514__PHY_BYPASS_TWO_CYC_PREAMBLE_2 + +#define LPDDR4__DENALI_PHY_514__PHY_CLK_BYPASS_OVERRIDE_2_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_514__PHY_CLK_BYPASS_OVERRIDE_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_514__PHY_CLK_BYPASS_OVERRIDE_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_514__PHY_CLK_BYPASS_OVERRIDE_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_514__PHY_CLK_BYPASS_OVERRIDE_2_WOSET 0U +#define LPDDR4__PHY_CLK_BYPASS_OVERRIDE_2__REG DENALI_PHY_514 +#define LPDDR4__PHY_CLK_BYPASS_OVERRIDE_2__FLD LPDDR4__DENALI_PHY_514__PHY_CLK_BYPASS_OVERRIDE_2 + +#define LPDDR4__DENALI_PHY_515_READ_MASK 0x3F3F3F3FU +#define LPDDR4__DENALI_PHY_515_WRITE_MASK 0x3F3F3F3FU +#define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ0_SHIFT_2_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ0_SHIFT_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ0_SHIFT_2_WIDTH 6U +#define LPDDR4__PHY_SW_WRDQ0_SHIFT_2__REG DENALI_PHY_515 +#define LPDDR4__PHY_SW_WRDQ0_SHIFT_2__FLD LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ0_SHIFT_2 + +#define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ1_SHIFT_2_MASK 0x00003F00U +#define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ1_SHIFT_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ1_SHIFT_2_WIDTH 6U +#define LPDDR4__PHY_SW_WRDQ1_SHIFT_2__REG DENALI_PHY_515 +#define LPDDR4__PHY_SW_WRDQ1_SHIFT_2__FLD LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ1_SHIFT_2 + +#define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ2_SHIFT_2_MASK 0x003F0000U +#define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ2_SHIFT_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ2_SHIFT_2_WIDTH 6U +#define LPDDR4__PHY_SW_WRDQ2_SHIFT_2__REG DENALI_PHY_515 +#define LPDDR4__PHY_SW_WRDQ2_SHIFT_2__FLD LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ2_SHIFT_2 + +#define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ3_SHIFT_2_MASK 0x3F000000U +#define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ3_SHIFT_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ3_SHIFT_2_WIDTH 6U +#define LPDDR4__PHY_SW_WRDQ3_SHIFT_2__REG DENALI_PHY_515 +#define LPDDR4__PHY_SW_WRDQ3_SHIFT_2__FLD LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ3_SHIFT_2 + +#define LPDDR4__DENALI_PHY_516_READ_MASK 0x3F3F3F3FU +#define LPDDR4__DENALI_PHY_516_WRITE_MASK 0x3F3F3F3FU +#define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ4_SHIFT_2_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ4_SHIFT_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ4_SHIFT_2_WIDTH 6U +#define LPDDR4__PHY_SW_WRDQ4_SHIFT_2__REG DENALI_PHY_516 +#define LPDDR4__PHY_SW_WRDQ4_SHIFT_2__FLD LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ4_SHIFT_2 + +#define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ5_SHIFT_2_MASK 0x00003F00U +#define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ5_SHIFT_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ5_SHIFT_2_WIDTH 6U +#define LPDDR4__PHY_SW_WRDQ5_SHIFT_2__REG DENALI_PHY_516 +#define LPDDR4__PHY_SW_WRDQ5_SHIFT_2__FLD LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ5_SHIFT_2 + +#define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ6_SHIFT_2_MASK 0x003F0000U +#define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ6_SHIFT_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ6_SHIFT_2_WIDTH 6U +#define LPDDR4__PHY_SW_WRDQ6_SHIFT_2__REG DENALI_PHY_516 +#define LPDDR4__PHY_SW_WRDQ6_SHIFT_2__FLD LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ6_SHIFT_2 + +#define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ7_SHIFT_2_MASK 0x3F000000U +#define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ7_SHIFT_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ7_SHIFT_2_WIDTH 6U +#define LPDDR4__PHY_SW_WRDQ7_SHIFT_2__REG DENALI_PHY_516 +#define LPDDR4__PHY_SW_WRDQ7_SHIFT_2__FLD LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ7_SHIFT_2 + +#define LPDDR4__DENALI_PHY_517_READ_MASK 0x01030F3FU +#define LPDDR4__DENALI_PHY_517_WRITE_MASK 0x01030F3FU +#define LPDDR4__DENALI_PHY_517__PHY_SW_WRDM_SHIFT_2_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_517__PHY_SW_WRDM_SHIFT_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_517__PHY_SW_WRDM_SHIFT_2_WIDTH 6U +#define LPDDR4__PHY_SW_WRDM_SHIFT_2__REG DENALI_PHY_517 +#define LPDDR4__PHY_SW_WRDM_SHIFT_2__FLD LPDDR4__DENALI_PHY_517__PHY_SW_WRDM_SHIFT_2 + +#define LPDDR4__DENALI_PHY_517__PHY_SW_WRDQS_SHIFT_2_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_517__PHY_SW_WRDQS_SHIFT_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_517__PHY_SW_WRDQS_SHIFT_2_WIDTH 4U +#define LPDDR4__PHY_SW_WRDQS_SHIFT_2__REG DENALI_PHY_517 +#define LPDDR4__PHY_SW_WRDQS_SHIFT_2__FLD LPDDR4__DENALI_PHY_517__PHY_SW_WRDQS_SHIFT_2 + +#define LPDDR4__DENALI_PHY_517__PHY_PER_RANK_CS_MAP_2_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_517__PHY_PER_RANK_CS_MAP_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_517__PHY_PER_RANK_CS_MAP_2_WIDTH 2U +#define LPDDR4__PHY_PER_RANK_CS_MAP_2__REG DENALI_PHY_517 +#define LPDDR4__PHY_PER_RANK_CS_MAP_2__FLD LPDDR4__DENALI_PHY_517__PHY_PER_RANK_CS_MAP_2 + +#define LPDDR4__DENALI_PHY_517__PHY_PER_CS_TRAINING_MULTICAST_EN_2_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_517__PHY_PER_CS_TRAINING_MULTICAST_EN_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_517__PHY_PER_CS_TRAINING_MULTICAST_EN_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_517__PHY_PER_CS_TRAINING_MULTICAST_EN_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_517__PHY_PER_CS_TRAINING_MULTICAST_EN_2_WOSET 0U +#define LPDDR4__PHY_PER_CS_TRAINING_MULTICAST_EN_2__REG DENALI_PHY_517 +#define LPDDR4__PHY_PER_CS_TRAINING_MULTICAST_EN_2__FLD LPDDR4__DENALI_PHY_517__PHY_PER_CS_TRAINING_MULTICAST_EN_2 + +#define LPDDR4__DENALI_PHY_518_READ_MASK 0x1F1F0301U +#define LPDDR4__DENALI_PHY_518_WRITE_MASK 0x1F1F0301U +#define LPDDR4__DENALI_PHY_518__PHY_PER_CS_TRAINING_INDEX_2_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_518__PHY_PER_CS_TRAINING_INDEX_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_518__PHY_PER_CS_TRAINING_INDEX_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_518__PHY_PER_CS_TRAINING_INDEX_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_518__PHY_PER_CS_TRAINING_INDEX_2_WOSET 0U +#define LPDDR4__PHY_PER_CS_TRAINING_INDEX_2__REG DENALI_PHY_518 +#define LPDDR4__PHY_PER_CS_TRAINING_INDEX_2__FLD LPDDR4__DENALI_PHY_518__PHY_PER_CS_TRAINING_INDEX_2 + +#define LPDDR4__DENALI_PHY_518__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_2_MASK 0x00000300U +#define LPDDR4__DENALI_PHY_518__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_518__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_2_WIDTH 2U +#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_2__REG DENALI_PHY_518 +#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_2__FLD LPDDR4__DENALI_PHY_518__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_2 + +#define LPDDR4__DENALI_PHY_518__PHY_LP4_BOOT_RDDATA_EN_DLY_2_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_518__PHY_LP4_BOOT_RDDATA_EN_DLY_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_518__PHY_LP4_BOOT_RDDATA_EN_DLY_2_WIDTH 5U +#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_DLY_2__REG DENALI_PHY_518 +#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_DLY_2__FLD LPDDR4__DENALI_PHY_518__PHY_LP4_BOOT_RDDATA_EN_DLY_2 + +#define LPDDR4__DENALI_PHY_518__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_2_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_518__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_518__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_2_WIDTH 5U +#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_2__REG DENALI_PHY_518 +#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_2__FLD LPDDR4__DENALI_PHY_518__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_2 + +#define LPDDR4__DENALI_PHY_519_READ_MASK 0x1F030F0FU +#define LPDDR4__DENALI_PHY_519_WRITE_MASK 0x1F030F0FU +#define LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_RPTR_UPDATE_2_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_RPTR_UPDATE_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_RPTR_UPDATE_2_WIDTH 4U +#define LPDDR4__PHY_LP4_BOOT_RPTR_UPDATE_2__REG DENALI_PHY_519 +#define LPDDR4__PHY_LP4_BOOT_RPTR_UPDATE_2__FLD LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_RPTR_UPDATE_2 + +#define LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_2_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_2_WIDTH 4U +#define LPDDR4__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_2__REG DENALI_PHY_519 +#define LPDDR4__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_2__FLD LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_2 + +#define LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_2_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_2_WIDTH 2U +#define LPDDR4__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_2__REG DENALI_PHY_519 +#define LPDDR4__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_2__FLD LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_2 + +#define LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_2_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_2_WIDTH 5U +#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_2__REG DENALI_PHY_519 +#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_2__FLD LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_2 + +#define LPDDR4__DENALI_PHY_520_READ_MASK 0x0101FF03U +#define LPDDR4__DENALI_PHY_520_WRITE_MASK 0x0101FF03U +#define LPDDR4__DENALI_PHY_520__PHY_CTRL_LPBK_EN_2_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_520__PHY_CTRL_LPBK_EN_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_520__PHY_CTRL_LPBK_EN_2_WIDTH 2U +#define LPDDR4__PHY_CTRL_LPBK_EN_2__REG DENALI_PHY_520 +#define LPDDR4__PHY_CTRL_LPBK_EN_2__FLD LPDDR4__DENALI_PHY_520__PHY_CTRL_LPBK_EN_2 + +#define LPDDR4__DENALI_PHY_520__PHY_LPBK_CONTROL_2_MASK 0x0001FF00U +#define LPDDR4__DENALI_PHY_520__PHY_LPBK_CONTROL_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_520__PHY_LPBK_CONTROL_2_WIDTH 9U +#define LPDDR4__PHY_LPBK_CONTROL_2__REG DENALI_PHY_520 +#define LPDDR4__PHY_LPBK_CONTROL_2__FLD LPDDR4__DENALI_PHY_520__PHY_LPBK_CONTROL_2 + +#define LPDDR4__DENALI_PHY_520__PHY_LPBK_DFX_TIMEOUT_EN_2_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_520__PHY_LPBK_DFX_TIMEOUT_EN_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_520__PHY_LPBK_DFX_TIMEOUT_EN_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_520__PHY_LPBK_DFX_TIMEOUT_EN_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_520__PHY_LPBK_DFX_TIMEOUT_EN_2_WOSET 0U +#define LPDDR4__PHY_LPBK_DFX_TIMEOUT_EN_2__REG DENALI_PHY_520 +#define LPDDR4__PHY_LPBK_DFX_TIMEOUT_EN_2__FLD LPDDR4__DENALI_PHY_520__PHY_LPBK_DFX_TIMEOUT_EN_2 + +#define LPDDR4__DENALI_PHY_521_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_521_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_521__PHY_AUTO_TIMING_MARGIN_CONTROL_2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_521__PHY_AUTO_TIMING_MARGIN_CONTROL_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_521__PHY_AUTO_TIMING_MARGIN_CONTROL_2_WIDTH 32U +#define LPDDR4__PHY_AUTO_TIMING_MARGIN_CONTROL_2__REG DENALI_PHY_521 +#define LPDDR4__PHY_AUTO_TIMING_MARGIN_CONTROL_2__FLD LPDDR4__DENALI_PHY_521__PHY_AUTO_TIMING_MARGIN_CONTROL_2 + +#define LPDDR4__DENALI_PHY_522_READ_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_522_WRITE_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_522__PHY_AUTO_TIMING_MARGIN_OBS_2_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_522__PHY_AUTO_TIMING_MARGIN_OBS_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_522__PHY_AUTO_TIMING_MARGIN_OBS_2_WIDTH 28U +#define LPDDR4__PHY_AUTO_TIMING_MARGIN_OBS_2__REG DENALI_PHY_522 +#define LPDDR4__PHY_AUTO_TIMING_MARGIN_OBS_2__FLD LPDDR4__DENALI_PHY_522__PHY_AUTO_TIMING_MARGIN_OBS_2 + +#define LPDDR4__DENALI_PHY_523_READ_MASK 0x0101FF7FU +#define LPDDR4__DENALI_PHY_523_WRITE_MASK 0x0101FF7FU +#define LPDDR4__DENALI_PHY_523__PHY_PRBS_PATTERN_START_2_MASK 0x0000007FU +#define LPDDR4__DENALI_PHY_523__PHY_PRBS_PATTERN_START_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_523__PHY_PRBS_PATTERN_START_2_WIDTH 7U +#define LPDDR4__PHY_PRBS_PATTERN_START_2__REG DENALI_PHY_523 +#define LPDDR4__PHY_PRBS_PATTERN_START_2__FLD LPDDR4__DENALI_PHY_523__PHY_PRBS_PATTERN_START_2 + +#define LPDDR4__DENALI_PHY_523__PHY_PRBS_PATTERN_MASK_2_MASK 0x0001FF00U +#define LPDDR4__DENALI_PHY_523__PHY_PRBS_PATTERN_MASK_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_523__PHY_PRBS_PATTERN_MASK_2_WIDTH 9U +#define LPDDR4__PHY_PRBS_PATTERN_MASK_2__REG DENALI_PHY_523 +#define LPDDR4__PHY_PRBS_PATTERN_MASK_2__FLD LPDDR4__DENALI_PHY_523__PHY_PRBS_PATTERN_MASK_2 + +#define LPDDR4__DENALI_PHY_523__PHY_RDLVL_MULTI_PATT_ENABLE_2_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_523__PHY_RDLVL_MULTI_PATT_ENABLE_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_523__PHY_RDLVL_MULTI_PATT_ENABLE_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_523__PHY_RDLVL_MULTI_PATT_ENABLE_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_523__PHY_RDLVL_MULTI_PATT_ENABLE_2_WOSET 0U +#define LPDDR4__PHY_RDLVL_MULTI_PATT_ENABLE_2__REG DENALI_PHY_523 +#define LPDDR4__PHY_RDLVL_MULTI_PATT_ENABLE_2__FLD LPDDR4__DENALI_PHY_523__PHY_RDLVL_MULTI_PATT_ENABLE_2 + +#define LPDDR4__DENALI_PHY_524_READ_MASK 0x007F3F01U +#define LPDDR4__DENALI_PHY_524_WRITE_MASK 0x007F3F01U +#define LPDDR4__DENALI_PHY_524__PHY_RDLVL_MULTI_PATT_RST_DISABLE_2_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_524__PHY_RDLVL_MULTI_PATT_RST_DISABLE_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_524__PHY_RDLVL_MULTI_PATT_RST_DISABLE_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_524__PHY_RDLVL_MULTI_PATT_RST_DISABLE_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_524__PHY_RDLVL_MULTI_PATT_RST_DISABLE_2_WOSET 0U +#define LPDDR4__PHY_RDLVL_MULTI_PATT_RST_DISABLE_2__REG DENALI_PHY_524 +#define LPDDR4__PHY_RDLVL_MULTI_PATT_RST_DISABLE_2__FLD LPDDR4__DENALI_PHY_524__PHY_RDLVL_MULTI_PATT_RST_DISABLE_2 + +#define LPDDR4__DENALI_PHY_524__PHY_VREF_INITIAL_STEPSIZE_2_MASK 0x00003F00U +#define LPDDR4__DENALI_PHY_524__PHY_VREF_INITIAL_STEPSIZE_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_524__PHY_VREF_INITIAL_STEPSIZE_2_WIDTH 6U +#define LPDDR4__PHY_VREF_INITIAL_STEPSIZE_2__REG DENALI_PHY_524 +#define LPDDR4__PHY_VREF_INITIAL_STEPSIZE_2__FLD LPDDR4__DENALI_PHY_524__PHY_VREF_INITIAL_STEPSIZE_2 + +#define LPDDR4__DENALI_PHY_524__PHY_VREF_TRAIN_OBS_2_MASK 0x007F0000U +#define LPDDR4__DENALI_PHY_524__PHY_VREF_TRAIN_OBS_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_524__PHY_VREF_TRAIN_OBS_2_WIDTH 7U +#define LPDDR4__PHY_VREF_TRAIN_OBS_2__REG DENALI_PHY_524 +#define LPDDR4__PHY_VREF_TRAIN_OBS_2__FLD LPDDR4__DENALI_PHY_524__PHY_VREF_TRAIN_OBS_2 + +#define LPDDR4__DENALI_PHY_525_READ_MASK 0x000F03FFU +#define LPDDR4__DENALI_PHY_525_WRITE_MASK 0x000F03FFU +#define LPDDR4__DENALI_PHY_525__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_2_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_525__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_525__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_2_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_2__REG DENALI_PHY_525 +#define LPDDR4__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_525__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_525__PHY_GATE_ERROR_DELAY_SELECT_2_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_525__PHY_GATE_ERROR_DELAY_SELECT_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_525__PHY_GATE_ERROR_DELAY_SELECT_2_WIDTH 4U +#define LPDDR4__PHY_GATE_ERROR_DELAY_SELECT_2__REG DENALI_PHY_525 +#define LPDDR4__PHY_GATE_ERROR_DELAY_SELECT_2__FLD LPDDR4__DENALI_PHY_525__PHY_GATE_ERROR_DELAY_SELECT_2 + +#define LPDDR4__DENALI_PHY_525__SC_PHY_SNAP_OBS_REGS_2_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_525__SC_PHY_SNAP_OBS_REGS_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_525__SC_PHY_SNAP_OBS_REGS_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_525__SC_PHY_SNAP_OBS_REGS_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_525__SC_PHY_SNAP_OBS_REGS_2_WOSET 0U +#define LPDDR4__SC_PHY_SNAP_OBS_REGS_2__REG DENALI_PHY_525 +#define LPDDR4__SC_PHY_SNAP_OBS_REGS_2__FLD LPDDR4__DENALI_PHY_525__SC_PHY_SNAP_OBS_REGS_2 + +#define LPDDR4__DENALI_PHY_526_READ_MASK 0x070101FFU +#define LPDDR4__DENALI_PHY_526_WRITE_MASK 0x070101FFU +#define LPDDR4__DENALI_PHY_526__PHY_GATE_SMPL1_SLAVE_DELAY_2_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_526__PHY_GATE_SMPL1_SLAVE_DELAY_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_526__PHY_GATE_SMPL1_SLAVE_DELAY_2_WIDTH 9U +#define LPDDR4__PHY_GATE_SMPL1_SLAVE_DELAY_2__REG DENALI_PHY_526 +#define LPDDR4__PHY_GATE_SMPL1_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_526__PHY_GATE_SMPL1_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_526__PHY_LPDDR_2_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_526__PHY_LPDDR_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_526__PHY_LPDDR_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_526__PHY_LPDDR_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_526__PHY_LPDDR_2_WOSET 0U +#define LPDDR4__PHY_LPDDR_2__REG DENALI_PHY_526 +#define LPDDR4__PHY_LPDDR_2__FLD LPDDR4__DENALI_PHY_526__PHY_LPDDR_2 + +#define LPDDR4__DENALI_PHY_526__PHY_MEM_CLASS_2_MASK 0x07000000U +#define LPDDR4__DENALI_PHY_526__PHY_MEM_CLASS_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_526__PHY_MEM_CLASS_2_WIDTH 3U +#define LPDDR4__PHY_MEM_CLASS_2__REG DENALI_PHY_526 +#define LPDDR4__PHY_MEM_CLASS_2__FLD LPDDR4__DENALI_PHY_526__PHY_MEM_CLASS_2 + +#define LPDDR4__DENALI_PHY_527_READ_MASK 0x000301FFU +#define LPDDR4__DENALI_PHY_527_WRITE_MASK 0x000301FFU +#define LPDDR4__DENALI_PHY_527__PHY_GATE_SMPL2_SLAVE_DELAY_2_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_527__PHY_GATE_SMPL2_SLAVE_DELAY_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_527__PHY_GATE_SMPL2_SLAVE_DELAY_2_WIDTH 9U +#define LPDDR4__PHY_GATE_SMPL2_SLAVE_DELAY_2__REG DENALI_PHY_527 +#define LPDDR4__PHY_GATE_SMPL2_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_527__PHY_GATE_SMPL2_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_527__ON_FLY_GATE_ADJUST_EN_2_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_527__ON_FLY_GATE_ADJUST_EN_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_527__ON_FLY_GATE_ADJUST_EN_2_WIDTH 2U +#define LPDDR4__ON_FLY_GATE_ADJUST_EN_2__REG DENALI_PHY_527 +#define LPDDR4__ON_FLY_GATE_ADJUST_EN_2__FLD LPDDR4__DENALI_PHY_527__ON_FLY_GATE_ADJUST_EN_2 + +#define LPDDR4__DENALI_PHY_528_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_528_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_528__PHY_GATE_TRACKING_OBS_2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_528__PHY_GATE_TRACKING_OBS_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_528__PHY_GATE_TRACKING_OBS_2_WIDTH 32U +#define LPDDR4__PHY_GATE_TRACKING_OBS_2__REG DENALI_PHY_528 +#define LPDDR4__PHY_GATE_TRACKING_OBS_2__FLD LPDDR4__DENALI_PHY_528__PHY_GATE_TRACKING_OBS_2 + +#define LPDDR4__DENALI_PHY_529_READ_MASK 0x00000301U +#define LPDDR4__DENALI_PHY_529_WRITE_MASK 0x00000301U +#define LPDDR4__DENALI_PHY_529__PHY_DFI40_POLARITY_2_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_529__PHY_DFI40_POLARITY_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_529__PHY_DFI40_POLARITY_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_529__PHY_DFI40_POLARITY_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_529__PHY_DFI40_POLARITY_2_WOSET 0U +#define LPDDR4__PHY_DFI40_POLARITY_2__REG DENALI_PHY_529 +#define LPDDR4__PHY_DFI40_POLARITY_2__FLD LPDDR4__DENALI_PHY_529__PHY_DFI40_POLARITY_2 + +#define LPDDR4__DENALI_PHY_529__PHY_LP4_PST_AMBLE_2_MASK 0x00000300U +#define LPDDR4__DENALI_PHY_529__PHY_LP4_PST_AMBLE_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_529__PHY_LP4_PST_AMBLE_2_WIDTH 2U +#define LPDDR4__PHY_LP4_PST_AMBLE_2__REG DENALI_PHY_529 +#define LPDDR4__PHY_LP4_PST_AMBLE_2__FLD LPDDR4__DENALI_PHY_529__PHY_LP4_PST_AMBLE_2 + +#define LPDDR4__DENALI_PHY_530_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_530_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_530__PHY_RDLVL_PATT8_2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_530__PHY_RDLVL_PATT8_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_530__PHY_RDLVL_PATT8_2_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PATT8_2__REG DENALI_PHY_530 +#define LPDDR4__PHY_RDLVL_PATT8_2__FLD LPDDR4__DENALI_PHY_530__PHY_RDLVL_PATT8_2 + +#define LPDDR4__DENALI_PHY_531_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_531_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_531__PHY_RDLVL_PATT9_2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_531__PHY_RDLVL_PATT9_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_531__PHY_RDLVL_PATT9_2_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PATT9_2__REG DENALI_PHY_531 +#define LPDDR4__PHY_RDLVL_PATT9_2__FLD LPDDR4__DENALI_PHY_531__PHY_RDLVL_PATT9_2 + +#define LPDDR4__DENALI_PHY_532_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_532_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_532__PHY_RDLVL_PATT10_2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_532__PHY_RDLVL_PATT10_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_532__PHY_RDLVL_PATT10_2_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PATT10_2__REG DENALI_PHY_532 +#define LPDDR4__PHY_RDLVL_PATT10_2__FLD LPDDR4__DENALI_PHY_532__PHY_RDLVL_PATT10_2 + +#define LPDDR4__DENALI_PHY_533_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_533_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_533__PHY_RDLVL_PATT11_2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_533__PHY_RDLVL_PATT11_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_533__PHY_RDLVL_PATT11_2_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PATT11_2__REG DENALI_PHY_533 +#define LPDDR4__PHY_RDLVL_PATT11_2__FLD LPDDR4__DENALI_PHY_533__PHY_RDLVL_PATT11_2 + +#define LPDDR4__DENALI_PHY_534_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_534_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_534__PHY_RDLVL_PATT12_2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_534__PHY_RDLVL_PATT12_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_534__PHY_RDLVL_PATT12_2_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PATT12_2__REG DENALI_PHY_534 +#define LPDDR4__PHY_RDLVL_PATT12_2__FLD LPDDR4__DENALI_PHY_534__PHY_RDLVL_PATT12_2 + +#define LPDDR4__DENALI_PHY_535_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_535_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_535__PHY_RDLVL_PATT13_2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_535__PHY_RDLVL_PATT13_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_535__PHY_RDLVL_PATT13_2_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PATT13_2__REG DENALI_PHY_535 +#define LPDDR4__PHY_RDLVL_PATT13_2__FLD LPDDR4__DENALI_PHY_535__PHY_RDLVL_PATT13_2 + +#define LPDDR4__DENALI_PHY_536_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_536_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_536__PHY_RDLVL_PATT14_2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_536__PHY_RDLVL_PATT14_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_536__PHY_RDLVL_PATT14_2_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PATT14_2__REG DENALI_PHY_536 +#define LPDDR4__PHY_RDLVL_PATT14_2__FLD LPDDR4__DENALI_PHY_536__PHY_RDLVL_PATT14_2 + +#define LPDDR4__DENALI_PHY_537_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_537_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_537__PHY_RDLVL_PATT15_2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_537__PHY_RDLVL_PATT15_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_537__PHY_RDLVL_PATT15_2_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PATT15_2__REG DENALI_PHY_537 +#define LPDDR4__PHY_RDLVL_PATT15_2__FLD LPDDR4__DENALI_PHY_537__PHY_RDLVL_PATT15_2 + +#define LPDDR4__DENALI_PHY_538_READ_MASK 0x070F0107U +#define LPDDR4__DENALI_PHY_538_WRITE_MASK 0x070F0107U +#define LPDDR4__DENALI_PHY_538__PHY_SLAVE_LOOP_CNT_UPDATE_2_MASK 0x00000007U +#define LPDDR4__DENALI_PHY_538__PHY_SLAVE_LOOP_CNT_UPDATE_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_538__PHY_SLAVE_LOOP_CNT_UPDATE_2_WIDTH 3U +#define LPDDR4__PHY_SLAVE_LOOP_CNT_UPDATE_2__REG DENALI_PHY_538 +#define LPDDR4__PHY_SLAVE_LOOP_CNT_UPDATE_2__FLD LPDDR4__DENALI_PHY_538__PHY_SLAVE_LOOP_CNT_UPDATE_2 + +#define LPDDR4__DENALI_PHY_538__PHY_SW_FIFO_PTR_RST_DISABLE_2_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_538__PHY_SW_FIFO_PTR_RST_DISABLE_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_538__PHY_SW_FIFO_PTR_RST_DISABLE_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_538__PHY_SW_FIFO_PTR_RST_DISABLE_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_538__PHY_SW_FIFO_PTR_RST_DISABLE_2_WOSET 0U +#define LPDDR4__PHY_SW_FIFO_PTR_RST_DISABLE_2__REG DENALI_PHY_538 +#define LPDDR4__PHY_SW_FIFO_PTR_RST_DISABLE_2__FLD LPDDR4__DENALI_PHY_538__PHY_SW_FIFO_PTR_RST_DISABLE_2 + +#define LPDDR4__DENALI_PHY_538__PHY_MASTER_DLY_LOCK_OBS_SELECT_2_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_538__PHY_MASTER_DLY_LOCK_OBS_SELECT_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_538__PHY_MASTER_DLY_LOCK_OBS_SELECT_2_WIDTH 4U +#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_SELECT_2__REG DENALI_PHY_538 +#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_SELECT_2__FLD LPDDR4__DENALI_PHY_538__PHY_MASTER_DLY_LOCK_OBS_SELECT_2 + +#define LPDDR4__DENALI_PHY_538__PHY_RDDQ_ENC_OBS_SELECT_2_MASK 0x07000000U +#define LPDDR4__DENALI_PHY_538__PHY_RDDQ_ENC_OBS_SELECT_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_538__PHY_RDDQ_ENC_OBS_SELECT_2_WIDTH 3U +#define LPDDR4__PHY_RDDQ_ENC_OBS_SELECT_2__REG DENALI_PHY_538 +#define LPDDR4__PHY_RDDQ_ENC_OBS_SELECT_2__FLD LPDDR4__DENALI_PHY_538__PHY_RDDQ_ENC_OBS_SELECT_2 + +#define LPDDR4__DENALI_PHY_539_READ_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_PHY_539_WRITE_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_PHY_539__PHY_RDDQS_DQ_ENC_OBS_SELECT_2_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_539__PHY_RDDQS_DQ_ENC_OBS_SELECT_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_539__PHY_RDDQS_DQ_ENC_OBS_SELECT_2_WIDTH 4U +#define LPDDR4__PHY_RDDQS_DQ_ENC_OBS_SELECT_2__REG DENALI_PHY_539 +#define LPDDR4__PHY_RDDQS_DQ_ENC_OBS_SELECT_2__FLD LPDDR4__DENALI_PHY_539__PHY_RDDQS_DQ_ENC_OBS_SELECT_2 + +#define LPDDR4__DENALI_PHY_539__PHY_WR_ENC_OBS_SELECT_2_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_539__PHY_WR_ENC_OBS_SELECT_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_539__PHY_WR_ENC_OBS_SELECT_2_WIDTH 4U +#define LPDDR4__PHY_WR_ENC_OBS_SELECT_2__REG DENALI_PHY_539 +#define LPDDR4__PHY_WR_ENC_OBS_SELECT_2__FLD LPDDR4__DENALI_PHY_539__PHY_WR_ENC_OBS_SELECT_2 + +#define LPDDR4__DENALI_PHY_539__PHY_WR_SHIFT_OBS_SELECT_2_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_539__PHY_WR_SHIFT_OBS_SELECT_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_539__PHY_WR_SHIFT_OBS_SELECT_2_WIDTH 4U +#define LPDDR4__PHY_WR_SHIFT_OBS_SELECT_2__REG DENALI_PHY_539 +#define LPDDR4__PHY_WR_SHIFT_OBS_SELECT_2__FLD LPDDR4__DENALI_PHY_539__PHY_WR_SHIFT_OBS_SELECT_2 + +#define LPDDR4__DENALI_PHY_539__PHY_FIFO_PTR_OBS_SELECT_2_MASK 0x0F000000U +#define LPDDR4__DENALI_PHY_539__PHY_FIFO_PTR_OBS_SELECT_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_539__PHY_FIFO_PTR_OBS_SELECT_2_WIDTH 4U +#define LPDDR4__PHY_FIFO_PTR_OBS_SELECT_2__REG DENALI_PHY_539 +#define LPDDR4__PHY_FIFO_PTR_OBS_SELECT_2__FLD LPDDR4__DENALI_PHY_539__PHY_FIFO_PTR_OBS_SELECT_2 + +#define LPDDR4__DENALI_PHY_540_READ_MASK 0xFF030001U +#define LPDDR4__DENALI_PHY_540_WRITE_MASK 0xFF030001U +#define LPDDR4__DENALI_PHY_540__PHY_LVL_DEBUG_MODE_2_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_540__PHY_LVL_DEBUG_MODE_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_540__PHY_LVL_DEBUG_MODE_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_540__PHY_LVL_DEBUG_MODE_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_540__PHY_LVL_DEBUG_MODE_2_WOSET 0U +#define LPDDR4__PHY_LVL_DEBUG_MODE_2__REG DENALI_PHY_540 +#define LPDDR4__PHY_LVL_DEBUG_MODE_2__FLD LPDDR4__DENALI_PHY_540__PHY_LVL_DEBUG_MODE_2 + +#define LPDDR4__DENALI_PHY_540__SC_PHY_LVL_DEBUG_CONT_2_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_540__SC_PHY_LVL_DEBUG_CONT_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_540__SC_PHY_LVL_DEBUG_CONT_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_540__SC_PHY_LVL_DEBUG_CONT_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_540__SC_PHY_LVL_DEBUG_CONT_2_WOSET 0U +#define LPDDR4__SC_PHY_LVL_DEBUG_CONT_2__REG DENALI_PHY_540 +#define LPDDR4__SC_PHY_LVL_DEBUG_CONT_2__FLD LPDDR4__DENALI_PHY_540__SC_PHY_LVL_DEBUG_CONT_2 + +#define LPDDR4__DENALI_PHY_540__PHY_WRLVL_ALGO_2_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_540__PHY_WRLVL_ALGO_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_540__PHY_WRLVL_ALGO_2_WIDTH 2U +#define LPDDR4__PHY_WRLVL_ALGO_2__REG DENALI_PHY_540 +#define LPDDR4__PHY_WRLVL_ALGO_2__FLD LPDDR4__DENALI_PHY_540__PHY_WRLVL_ALGO_2 + +#define LPDDR4__DENALI_PHY_540__PHY_WRLVL_PER_START_2_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_540__PHY_WRLVL_PER_START_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_540__PHY_WRLVL_PER_START_2_WIDTH 8U +#define LPDDR4__PHY_WRLVL_PER_START_2__REG DENALI_PHY_540 +#define LPDDR4__PHY_WRLVL_PER_START_2__FLD LPDDR4__DENALI_PHY_540__PHY_WRLVL_PER_START_2 + +#define LPDDR4__DENALI_PHY_541_READ_MASK 0x00FF0F3FU +#define LPDDR4__DENALI_PHY_541_WRITE_MASK 0x00FF0F3FU +#define LPDDR4__DENALI_PHY_541__PHY_WRLVL_CAPTURE_CNT_2_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_541__PHY_WRLVL_CAPTURE_CNT_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_541__PHY_WRLVL_CAPTURE_CNT_2_WIDTH 6U +#define LPDDR4__PHY_WRLVL_CAPTURE_CNT_2__REG DENALI_PHY_541 +#define LPDDR4__PHY_WRLVL_CAPTURE_CNT_2__FLD LPDDR4__DENALI_PHY_541__PHY_WRLVL_CAPTURE_CNT_2 + +#define LPDDR4__DENALI_PHY_541__PHY_WRLVL_UPDT_WAIT_CNT_2_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_541__PHY_WRLVL_UPDT_WAIT_CNT_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_541__PHY_WRLVL_UPDT_WAIT_CNT_2_WIDTH 4U +#define LPDDR4__PHY_WRLVL_UPDT_WAIT_CNT_2__REG DENALI_PHY_541 +#define LPDDR4__PHY_WRLVL_UPDT_WAIT_CNT_2__FLD LPDDR4__DENALI_PHY_541__PHY_WRLVL_UPDT_WAIT_CNT_2 + +#define LPDDR4__DENALI_PHY_541__PHY_DQ_MASK_2_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_541__PHY_DQ_MASK_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_541__PHY_DQ_MASK_2_WIDTH 8U +#define LPDDR4__PHY_DQ_MASK_2__REG DENALI_PHY_541 +#define LPDDR4__PHY_DQ_MASK_2__FLD LPDDR4__DENALI_PHY_541__PHY_DQ_MASK_2 + +#define LPDDR4__DENALI_PHY_542_READ_MASK 0x0F3F03FFU +#define LPDDR4__DENALI_PHY_542_WRITE_MASK 0x0F3F03FFU +#define LPDDR4__DENALI_PHY_542__PHY_GTLVL_PER_START_2_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_542__PHY_GTLVL_PER_START_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_542__PHY_GTLVL_PER_START_2_WIDTH 10U +#define LPDDR4__PHY_GTLVL_PER_START_2__REG DENALI_PHY_542 +#define LPDDR4__PHY_GTLVL_PER_START_2__FLD LPDDR4__DENALI_PHY_542__PHY_GTLVL_PER_START_2 + +#define LPDDR4__DENALI_PHY_542__PHY_GTLVL_CAPTURE_CNT_2_MASK 0x003F0000U +#define LPDDR4__DENALI_PHY_542__PHY_GTLVL_CAPTURE_CNT_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_542__PHY_GTLVL_CAPTURE_CNT_2_WIDTH 6U +#define LPDDR4__PHY_GTLVL_CAPTURE_CNT_2__REG DENALI_PHY_542 +#define LPDDR4__PHY_GTLVL_CAPTURE_CNT_2__FLD LPDDR4__DENALI_PHY_542__PHY_GTLVL_CAPTURE_CNT_2 + +#define LPDDR4__DENALI_PHY_542__PHY_GTLVL_UPDT_WAIT_CNT_2_MASK 0x0F000000U +#define LPDDR4__DENALI_PHY_542__PHY_GTLVL_UPDT_WAIT_CNT_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_542__PHY_GTLVL_UPDT_WAIT_CNT_2_WIDTH 4U +#define LPDDR4__PHY_GTLVL_UPDT_WAIT_CNT_2__REG DENALI_PHY_542 +#define LPDDR4__PHY_GTLVL_UPDT_WAIT_CNT_2__FLD LPDDR4__DENALI_PHY_542__PHY_GTLVL_UPDT_WAIT_CNT_2 + +#define LPDDR4__DENALI_PHY_543_READ_MASK 0x1F030F3FU +#define LPDDR4__DENALI_PHY_543_WRITE_MASK 0x1F030F3FU +#define LPDDR4__DENALI_PHY_543__PHY_RDLVL_CAPTURE_CNT_2_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_543__PHY_RDLVL_CAPTURE_CNT_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_543__PHY_RDLVL_CAPTURE_CNT_2_WIDTH 6U +#define LPDDR4__PHY_RDLVL_CAPTURE_CNT_2__REG DENALI_PHY_543 +#define LPDDR4__PHY_RDLVL_CAPTURE_CNT_2__FLD LPDDR4__DENALI_PHY_543__PHY_RDLVL_CAPTURE_CNT_2 + +#define LPDDR4__DENALI_PHY_543__PHY_RDLVL_UPDT_WAIT_CNT_2_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_543__PHY_RDLVL_UPDT_WAIT_CNT_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_543__PHY_RDLVL_UPDT_WAIT_CNT_2_WIDTH 4U +#define LPDDR4__PHY_RDLVL_UPDT_WAIT_CNT_2__REG DENALI_PHY_543 +#define LPDDR4__PHY_RDLVL_UPDT_WAIT_CNT_2__FLD LPDDR4__DENALI_PHY_543__PHY_RDLVL_UPDT_WAIT_CNT_2 + +#define LPDDR4__DENALI_PHY_543__PHY_RDLVL_OP_MODE_2_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_543__PHY_RDLVL_OP_MODE_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_543__PHY_RDLVL_OP_MODE_2_WIDTH 2U +#define LPDDR4__PHY_RDLVL_OP_MODE_2__REG DENALI_PHY_543 +#define LPDDR4__PHY_RDLVL_OP_MODE_2__FLD LPDDR4__DENALI_PHY_543__PHY_RDLVL_OP_MODE_2 + +#define LPDDR4__DENALI_PHY_543__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_2_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_543__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_543__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_2_WIDTH 5U +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_2__REG DENALI_PHY_543 +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_2__FLD LPDDR4__DENALI_PHY_543__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_2 + +#define LPDDR4__DENALI_PHY_544_READ_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_544_WRITE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_544__PHY_RDLVL_PERIODIC_OBS_SELECT_2_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_544__PHY_RDLVL_PERIODIC_OBS_SELECT_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_544__PHY_RDLVL_PERIODIC_OBS_SELECT_2_WIDTH 8U +#define LPDDR4__PHY_RDLVL_PERIODIC_OBS_SELECT_2__REG DENALI_PHY_544 +#define LPDDR4__PHY_RDLVL_PERIODIC_OBS_SELECT_2__FLD LPDDR4__DENALI_PHY_544__PHY_RDLVL_PERIODIC_OBS_SELECT_2 + +#define LPDDR4__DENALI_PHY_544__PHY_RDLVL_DATA_MASK_2_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_544__PHY_RDLVL_DATA_MASK_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_544__PHY_RDLVL_DATA_MASK_2_WIDTH 8U +#define LPDDR4__PHY_RDLVL_DATA_MASK_2__REG DENALI_PHY_544 +#define LPDDR4__PHY_RDLVL_DATA_MASK_2__FLD LPDDR4__DENALI_PHY_544__PHY_RDLVL_DATA_MASK_2 + +#define LPDDR4__DENALI_PHY_544__PHY_WDQLVL_CLK_JITTER_TOLERANCE_2_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_544__PHY_WDQLVL_CLK_JITTER_TOLERANCE_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_544__PHY_WDQLVL_CLK_JITTER_TOLERANCE_2_WIDTH 8U +#define LPDDR4__PHY_WDQLVL_CLK_JITTER_TOLERANCE_2__REG DENALI_PHY_544 +#define LPDDR4__PHY_WDQLVL_CLK_JITTER_TOLERANCE_2__FLD LPDDR4__DENALI_PHY_544__PHY_WDQLVL_CLK_JITTER_TOLERANCE_2 + +#define LPDDR4__DENALI_PHY_544__PHY_WDQLVL_BURST_CNT_2_MASK 0x3F000000U +#define LPDDR4__DENALI_PHY_544__PHY_WDQLVL_BURST_CNT_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_544__PHY_WDQLVL_BURST_CNT_2_WIDTH 6U +#define LPDDR4__PHY_WDQLVL_BURST_CNT_2__REG DENALI_PHY_544 +#define LPDDR4__PHY_WDQLVL_BURST_CNT_2__FLD LPDDR4__DENALI_PHY_544__PHY_WDQLVL_BURST_CNT_2 + +#define LPDDR4__DENALI_PHY_545_READ_MASK 0x0F07FF07U +#define LPDDR4__DENALI_PHY_545_WRITE_MASK 0x0F07FF07U +#define LPDDR4__DENALI_PHY_545__PHY_WDQLVL_PATT_2_MASK 0x00000007U +#define LPDDR4__DENALI_PHY_545__PHY_WDQLVL_PATT_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_545__PHY_WDQLVL_PATT_2_WIDTH 3U +#define LPDDR4__PHY_WDQLVL_PATT_2__REG DENALI_PHY_545 +#define LPDDR4__PHY_WDQLVL_PATT_2__FLD LPDDR4__DENALI_PHY_545__PHY_WDQLVL_PATT_2 + +#define LPDDR4__DENALI_PHY_545__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_2_MASK 0x0007FF00U +#define LPDDR4__DENALI_PHY_545__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_545__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_2_WIDTH 11U +#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_2__REG DENALI_PHY_545 +#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_2__FLD LPDDR4__DENALI_PHY_545__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_2 + +#define LPDDR4__DENALI_PHY_545__PHY_WDQLVL_UPDT_WAIT_CNT_2_MASK 0x0F000000U +#define LPDDR4__DENALI_PHY_545__PHY_WDQLVL_UPDT_WAIT_CNT_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_545__PHY_WDQLVL_UPDT_WAIT_CNT_2_WIDTH 4U +#define LPDDR4__PHY_WDQLVL_UPDT_WAIT_CNT_2__REG DENALI_PHY_545 +#define LPDDR4__PHY_WDQLVL_UPDT_WAIT_CNT_2__FLD LPDDR4__DENALI_PHY_545__PHY_WDQLVL_UPDT_WAIT_CNT_2 + +#define LPDDR4__DENALI_PHY_546_READ_MASK 0x0000FF0FU +#define LPDDR4__DENALI_PHY_546_WRITE_MASK 0x0000FF0FU +#define LPDDR4__DENALI_PHY_546__PHY_WDQLVL_DQDM_OBS_SELECT_2_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_546__PHY_WDQLVL_DQDM_OBS_SELECT_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_546__PHY_WDQLVL_DQDM_OBS_SELECT_2_WIDTH 4U +#define LPDDR4__PHY_WDQLVL_DQDM_OBS_SELECT_2__REG DENALI_PHY_546 +#define LPDDR4__PHY_WDQLVL_DQDM_OBS_SELECT_2__FLD LPDDR4__DENALI_PHY_546__PHY_WDQLVL_DQDM_OBS_SELECT_2 + +#define LPDDR4__DENALI_PHY_546__PHY_WDQLVL_PERIODIC_OBS_SELECT_2_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_546__PHY_WDQLVL_PERIODIC_OBS_SELECT_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_546__PHY_WDQLVL_PERIODIC_OBS_SELECT_2_WIDTH 8U +#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_SELECT_2__REG DENALI_PHY_546 +#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_SELECT_2__FLD LPDDR4__DENALI_PHY_546__PHY_WDQLVL_PERIODIC_OBS_SELECT_2 + +#define LPDDR4__DENALI_PHY_546__SC_PHY_WDQLVL_CLR_PREV_RESULTS_2_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_546__SC_PHY_WDQLVL_CLR_PREV_RESULTS_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_546__SC_PHY_WDQLVL_CLR_PREV_RESULTS_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_546__SC_PHY_WDQLVL_CLR_PREV_RESULTS_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_546__SC_PHY_WDQLVL_CLR_PREV_RESULTS_2_WOSET 0U +#define LPDDR4__SC_PHY_WDQLVL_CLR_PREV_RESULTS_2__REG DENALI_PHY_546 +#define LPDDR4__SC_PHY_WDQLVL_CLR_PREV_RESULTS_2__FLD LPDDR4__DENALI_PHY_546__SC_PHY_WDQLVL_CLR_PREV_RESULTS_2 + +#define LPDDR4__DENALI_PHY_547_READ_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_547_WRITE_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_547__PHY_WDQLVL_DATADM_MASK_2_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_547__PHY_WDQLVL_DATADM_MASK_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_547__PHY_WDQLVL_DATADM_MASK_2_WIDTH 9U +#define LPDDR4__PHY_WDQLVL_DATADM_MASK_2__REG DENALI_PHY_547 +#define LPDDR4__PHY_WDQLVL_DATADM_MASK_2__FLD LPDDR4__DENALI_PHY_547__PHY_WDQLVL_DATADM_MASK_2 + +#define LPDDR4__DENALI_PHY_548_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_548_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_548__PHY_USER_PATT0_2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_548__PHY_USER_PATT0_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_548__PHY_USER_PATT0_2_WIDTH 32U +#define LPDDR4__PHY_USER_PATT0_2__REG DENALI_PHY_548 +#define LPDDR4__PHY_USER_PATT0_2__FLD LPDDR4__DENALI_PHY_548__PHY_USER_PATT0_2 + +#define LPDDR4__DENALI_PHY_549_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_549_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_549__PHY_USER_PATT1_2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_549__PHY_USER_PATT1_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_549__PHY_USER_PATT1_2_WIDTH 32U +#define LPDDR4__PHY_USER_PATT1_2__REG DENALI_PHY_549 +#define LPDDR4__PHY_USER_PATT1_2__FLD LPDDR4__DENALI_PHY_549__PHY_USER_PATT1_2 + +#define LPDDR4__DENALI_PHY_550_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_550_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_550__PHY_USER_PATT2_2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_550__PHY_USER_PATT2_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_550__PHY_USER_PATT2_2_WIDTH 32U +#define LPDDR4__PHY_USER_PATT2_2__REG DENALI_PHY_550 +#define LPDDR4__PHY_USER_PATT2_2__FLD LPDDR4__DENALI_PHY_550__PHY_USER_PATT2_2 + +#define LPDDR4__DENALI_PHY_551_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_551_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_551__PHY_USER_PATT3_2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_551__PHY_USER_PATT3_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_551__PHY_USER_PATT3_2_WIDTH 32U +#define LPDDR4__PHY_USER_PATT3_2__REG DENALI_PHY_551 +#define LPDDR4__PHY_USER_PATT3_2__FLD LPDDR4__DENALI_PHY_551__PHY_USER_PATT3_2 + +#define LPDDR4__DENALI_PHY_552_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PHY_552_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PHY_552__PHY_USER_PATT4_2_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_552__PHY_USER_PATT4_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_552__PHY_USER_PATT4_2_WIDTH 16U +#define LPDDR4__PHY_USER_PATT4_2__REG DENALI_PHY_552 +#define LPDDR4__PHY_USER_PATT4_2__FLD LPDDR4__DENALI_PHY_552__PHY_USER_PATT4_2 + +#define LPDDR4__DENALI_PHY_552__PHY_NTP_MULT_TRAIN_2_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_552__PHY_NTP_MULT_TRAIN_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_552__PHY_NTP_MULT_TRAIN_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_552__PHY_NTP_MULT_TRAIN_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_552__PHY_NTP_MULT_TRAIN_2_WOSET 0U +#define LPDDR4__PHY_NTP_MULT_TRAIN_2__REG DENALI_PHY_552 +#define LPDDR4__PHY_NTP_MULT_TRAIN_2__FLD LPDDR4__DENALI_PHY_552__PHY_NTP_MULT_TRAIN_2 + +#define LPDDR4__DENALI_PHY_553_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_553_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_553__PHY_NTP_EARLY_THRESHOLD_2_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_553__PHY_NTP_EARLY_THRESHOLD_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_553__PHY_NTP_EARLY_THRESHOLD_2_WIDTH 10U +#define LPDDR4__PHY_NTP_EARLY_THRESHOLD_2__REG DENALI_PHY_553 +#define LPDDR4__PHY_NTP_EARLY_THRESHOLD_2__FLD LPDDR4__DENALI_PHY_553__PHY_NTP_EARLY_THRESHOLD_2 + +#define LPDDR4__DENALI_PHY_553__PHY_NTP_PERIOD_THRESHOLD_2_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_553__PHY_NTP_PERIOD_THRESHOLD_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_553__PHY_NTP_PERIOD_THRESHOLD_2_WIDTH 10U +#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_2__REG DENALI_PHY_553 +#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_2__FLD LPDDR4__DENALI_PHY_553__PHY_NTP_PERIOD_THRESHOLD_2 + +#define LPDDR4__DENALI_PHY_554_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_554_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_554__PHY_NTP_PERIOD_THRESHOLD_MIN_2_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_554__PHY_NTP_PERIOD_THRESHOLD_MIN_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_554__PHY_NTP_PERIOD_THRESHOLD_MIN_2_WIDTH 10U +#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MIN_2__REG DENALI_PHY_554 +#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MIN_2__FLD LPDDR4__DENALI_PHY_554__PHY_NTP_PERIOD_THRESHOLD_MIN_2 + +#define LPDDR4__DENALI_PHY_554__PHY_NTP_PERIOD_THRESHOLD_MAX_2_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_554__PHY_NTP_PERIOD_THRESHOLD_MAX_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_554__PHY_NTP_PERIOD_THRESHOLD_MAX_2_WIDTH 10U +#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MAX_2__REG DENALI_PHY_554 +#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MAX_2__FLD LPDDR4__DENALI_PHY_554__PHY_NTP_PERIOD_THRESHOLD_MAX_2 + +#define LPDDR4__DENALI_PHY_555_READ_MASK 0x00FF0001U +#define LPDDR4__DENALI_PHY_555_WRITE_MASK 0x00FF0001U +#define LPDDR4__DENALI_PHY_555__PHY_CALVL_VREF_DRIVING_SLICE_2_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_555__PHY_CALVL_VREF_DRIVING_SLICE_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_555__PHY_CALVL_VREF_DRIVING_SLICE_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_555__PHY_CALVL_VREF_DRIVING_SLICE_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_555__PHY_CALVL_VREF_DRIVING_SLICE_2_WOSET 0U +#define LPDDR4__PHY_CALVL_VREF_DRIVING_SLICE_2__REG DENALI_PHY_555 +#define LPDDR4__PHY_CALVL_VREF_DRIVING_SLICE_2__FLD LPDDR4__DENALI_PHY_555__PHY_CALVL_VREF_DRIVING_SLICE_2 + +#define LPDDR4__DENALI_PHY_555__SC_PHY_MANUAL_CLEAR_2_MASK 0x00003F00U +#define LPDDR4__DENALI_PHY_555__SC_PHY_MANUAL_CLEAR_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_555__SC_PHY_MANUAL_CLEAR_2_WIDTH 6U +#define LPDDR4__SC_PHY_MANUAL_CLEAR_2__REG DENALI_PHY_555 +#define LPDDR4__SC_PHY_MANUAL_CLEAR_2__FLD LPDDR4__DENALI_PHY_555__SC_PHY_MANUAL_CLEAR_2 + +#define LPDDR4__DENALI_PHY_555__PHY_FIFO_PTR_OBS_2_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_555__PHY_FIFO_PTR_OBS_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_555__PHY_FIFO_PTR_OBS_2_WIDTH 8U +#define LPDDR4__PHY_FIFO_PTR_OBS_2__REG DENALI_PHY_555 +#define LPDDR4__PHY_FIFO_PTR_OBS_2__FLD LPDDR4__DENALI_PHY_555__PHY_FIFO_PTR_OBS_2 + +#define LPDDR4__DENALI_PHY_556_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_556_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_556__PHY_LPBK_RESULT_OBS_2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_556__PHY_LPBK_RESULT_OBS_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_556__PHY_LPBK_RESULT_OBS_2_WIDTH 32U +#define LPDDR4__PHY_LPBK_RESULT_OBS_2__REG DENALI_PHY_556 +#define LPDDR4__PHY_LPBK_RESULT_OBS_2__FLD LPDDR4__DENALI_PHY_556__PHY_LPBK_RESULT_OBS_2 + +#define LPDDR4__DENALI_PHY_557_READ_MASK 0x07FFFFFFU +#define LPDDR4__DENALI_PHY_557_WRITE_MASK 0x07FFFFFFU +#define LPDDR4__DENALI_PHY_557__PHY_LPBK_ERROR_COUNT_OBS_2_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_557__PHY_LPBK_ERROR_COUNT_OBS_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_557__PHY_LPBK_ERROR_COUNT_OBS_2_WIDTH 16U +#define LPDDR4__PHY_LPBK_ERROR_COUNT_OBS_2__REG DENALI_PHY_557 +#define LPDDR4__PHY_LPBK_ERROR_COUNT_OBS_2__FLD LPDDR4__DENALI_PHY_557__PHY_LPBK_ERROR_COUNT_OBS_2 + +#define LPDDR4__DENALI_PHY_557__PHY_MASTER_DLY_LOCK_OBS_2_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_557__PHY_MASTER_DLY_LOCK_OBS_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_557__PHY_MASTER_DLY_LOCK_OBS_2_WIDTH 11U +#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_2__REG DENALI_PHY_557 +#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_2__FLD LPDDR4__DENALI_PHY_557__PHY_MASTER_DLY_LOCK_OBS_2 + +#define LPDDR4__DENALI_PHY_558_READ_MASK 0xFFFF7F7FU +#define LPDDR4__DENALI_PHY_558_WRITE_MASK 0xFFFF7F7FU +#define LPDDR4__DENALI_PHY_558__PHY_RDDQ_SLV_DLY_ENC_OBS_2_MASK 0x0000007FU +#define LPDDR4__DENALI_PHY_558__PHY_RDDQ_SLV_DLY_ENC_OBS_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_558__PHY_RDDQ_SLV_DLY_ENC_OBS_2_WIDTH 7U +#define LPDDR4__PHY_RDDQ_SLV_DLY_ENC_OBS_2__REG DENALI_PHY_558 +#define LPDDR4__PHY_RDDQ_SLV_DLY_ENC_OBS_2__FLD LPDDR4__DENALI_PHY_558__PHY_RDDQ_SLV_DLY_ENC_OBS_2 + +#define LPDDR4__DENALI_PHY_558__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_2_MASK 0x00007F00U +#define LPDDR4__DENALI_PHY_558__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_558__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_2_WIDTH 7U +#define LPDDR4__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_2__REG DENALI_PHY_558 +#define LPDDR4__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_2__FLD LPDDR4__DENALI_PHY_558__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_2 + +#define LPDDR4__DENALI_PHY_558__PHY_MEAS_DLY_STEP_VALUE_2_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_558__PHY_MEAS_DLY_STEP_VALUE_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_558__PHY_MEAS_DLY_STEP_VALUE_2_WIDTH 8U +#define LPDDR4__PHY_MEAS_DLY_STEP_VALUE_2__REG DENALI_PHY_558 +#define LPDDR4__PHY_MEAS_DLY_STEP_VALUE_2__FLD LPDDR4__DENALI_PHY_558__PHY_MEAS_DLY_STEP_VALUE_2 + +#define LPDDR4__DENALI_PHY_558__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_2_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_558__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_558__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_2_WIDTH 8U +#define LPDDR4__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_2__REG DENALI_PHY_558 +#define LPDDR4__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_2__FLD LPDDR4__DENALI_PHY_558__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_2 + +#define LPDDR4__DENALI_PHY_559_READ_MASK 0x7F07FFFFU +#define LPDDR4__DENALI_PHY_559_WRITE_MASK 0x7F07FFFFU +#define LPDDR4__DENALI_PHY_559__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_2_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_559__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_559__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_2_WIDTH 8U +#define LPDDR4__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_2__REG DENALI_PHY_559 +#define LPDDR4__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_2__FLD LPDDR4__DENALI_PHY_559__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_2 + +#define LPDDR4__DENALI_PHY_559__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_2_MASK 0x0007FF00U +#define LPDDR4__DENALI_PHY_559__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_559__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_2_WIDTH 11U +#define LPDDR4__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_2__REG DENALI_PHY_559 +#define LPDDR4__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_2__FLD LPDDR4__DENALI_PHY_559__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_2 + +#define LPDDR4__DENALI_PHY_559__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_2_MASK 0x7F000000U +#define LPDDR4__DENALI_PHY_559__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_559__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_2_WIDTH 7U +#define LPDDR4__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_2__REG DENALI_PHY_559 +#define LPDDR4__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_2__FLD LPDDR4__DENALI_PHY_559__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_2 + +#define LPDDR4__DENALI_PHY_560_READ_MASK 0x0007FFFFU +#define LPDDR4__DENALI_PHY_560_WRITE_MASK 0x0007FFFFU +#define LPDDR4__DENALI_PHY_560__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_2_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_560__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_560__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_2_WIDTH 8U +#define LPDDR4__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_2__REG DENALI_PHY_560 +#define LPDDR4__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_2__FLD LPDDR4__DENALI_PHY_560__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_2 + +#define LPDDR4__DENALI_PHY_560__PHY_WR_ADDER_SLV_DLY_ENC_OBS_2_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_560__PHY_WR_ADDER_SLV_DLY_ENC_OBS_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_560__PHY_WR_ADDER_SLV_DLY_ENC_OBS_2_WIDTH 8U +#define LPDDR4__PHY_WR_ADDER_SLV_DLY_ENC_OBS_2__REG DENALI_PHY_560 +#define LPDDR4__PHY_WR_ADDER_SLV_DLY_ENC_OBS_2__FLD LPDDR4__DENALI_PHY_560__PHY_WR_ADDER_SLV_DLY_ENC_OBS_2 + +#define LPDDR4__DENALI_PHY_560__PHY_WR_SHIFT_OBS_2_MASK 0x00070000U +#define LPDDR4__DENALI_PHY_560__PHY_WR_SHIFT_OBS_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_560__PHY_WR_SHIFT_OBS_2_WIDTH 3U +#define LPDDR4__PHY_WR_SHIFT_OBS_2__REG DENALI_PHY_560 +#define LPDDR4__PHY_WR_SHIFT_OBS_2__FLD LPDDR4__DENALI_PHY_560__PHY_WR_SHIFT_OBS_2 + +#define LPDDR4__DENALI_PHY_561_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_561_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_561__PHY_WRLVL_HARD0_DELAY_OBS_2_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_561__PHY_WRLVL_HARD0_DELAY_OBS_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_561__PHY_WRLVL_HARD0_DELAY_OBS_2_WIDTH 10U +#define LPDDR4__PHY_WRLVL_HARD0_DELAY_OBS_2__REG DENALI_PHY_561 +#define LPDDR4__PHY_WRLVL_HARD0_DELAY_OBS_2__FLD LPDDR4__DENALI_PHY_561__PHY_WRLVL_HARD0_DELAY_OBS_2 + +#define LPDDR4__DENALI_PHY_561__PHY_WRLVL_HARD1_DELAY_OBS_2_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_561__PHY_WRLVL_HARD1_DELAY_OBS_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_561__PHY_WRLVL_HARD1_DELAY_OBS_2_WIDTH 10U +#define LPDDR4__PHY_WRLVL_HARD1_DELAY_OBS_2__REG DENALI_PHY_561 +#define LPDDR4__PHY_WRLVL_HARD1_DELAY_OBS_2__FLD LPDDR4__DENALI_PHY_561__PHY_WRLVL_HARD1_DELAY_OBS_2 + +#define LPDDR4__DENALI_PHY_562_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PHY_562_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PHY_562__PHY_WRLVL_STATUS_OBS_2_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PHY_562__PHY_WRLVL_STATUS_OBS_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_562__PHY_WRLVL_STATUS_OBS_2_WIDTH 17U +#define LPDDR4__PHY_WRLVL_STATUS_OBS_2__REG DENALI_PHY_562 +#define LPDDR4__PHY_WRLVL_STATUS_OBS_2__FLD LPDDR4__DENALI_PHY_562__PHY_WRLVL_STATUS_OBS_2 + +#define LPDDR4__DENALI_PHY_563_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_563_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_563__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_2_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_563__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_563__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_2_WIDTH 10U +#define LPDDR4__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_2__REG DENALI_PHY_563 +#define LPDDR4__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_2__FLD LPDDR4__DENALI_PHY_563__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_2 + +#define LPDDR4__DENALI_PHY_563__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_2_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_563__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_563__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_2_WIDTH 10U +#define LPDDR4__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_2__REG DENALI_PHY_563 +#define LPDDR4__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_2__FLD LPDDR4__DENALI_PHY_563__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_2 + +#define LPDDR4__DENALI_PHY_564_READ_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_564_WRITE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_564__PHY_WRLVL_ERROR_OBS_2_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_564__PHY_WRLVL_ERROR_OBS_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_564__PHY_WRLVL_ERROR_OBS_2_WIDTH 16U +#define LPDDR4__PHY_WRLVL_ERROR_OBS_2__REG DENALI_PHY_564 +#define LPDDR4__PHY_WRLVL_ERROR_OBS_2__FLD LPDDR4__DENALI_PHY_564__PHY_WRLVL_ERROR_OBS_2 + +#define LPDDR4__DENALI_PHY_564__PHY_GTLVL_HARD0_DELAY_OBS_2_MASK 0x3FFF0000U +#define LPDDR4__DENALI_PHY_564__PHY_GTLVL_HARD0_DELAY_OBS_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_564__PHY_GTLVL_HARD0_DELAY_OBS_2_WIDTH 14U +#define LPDDR4__PHY_GTLVL_HARD0_DELAY_OBS_2__REG DENALI_PHY_564 +#define LPDDR4__PHY_GTLVL_HARD0_DELAY_OBS_2__FLD LPDDR4__DENALI_PHY_564__PHY_GTLVL_HARD0_DELAY_OBS_2 + +#define LPDDR4__DENALI_PHY_565_READ_MASK 0x00003FFFU +#define LPDDR4__DENALI_PHY_565_WRITE_MASK 0x00003FFFU +#define LPDDR4__DENALI_PHY_565__PHY_GTLVL_HARD1_DELAY_OBS_2_MASK 0x00003FFFU +#define LPDDR4__DENALI_PHY_565__PHY_GTLVL_HARD1_DELAY_OBS_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_565__PHY_GTLVL_HARD1_DELAY_OBS_2_WIDTH 14U +#define LPDDR4__PHY_GTLVL_HARD1_DELAY_OBS_2__REG DENALI_PHY_565 +#define LPDDR4__PHY_GTLVL_HARD1_DELAY_OBS_2__FLD LPDDR4__DENALI_PHY_565__PHY_GTLVL_HARD1_DELAY_OBS_2 + +#define LPDDR4__DENALI_PHY_566_READ_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_566_WRITE_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_566__PHY_GTLVL_STATUS_OBS_2_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_566__PHY_GTLVL_STATUS_OBS_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_566__PHY_GTLVL_STATUS_OBS_2_WIDTH 18U +#define LPDDR4__PHY_GTLVL_STATUS_OBS_2__REG DENALI_PHY_566 +#define LPDDR4__PHY_GTLVL_STATUS_OBS_2__FLD LPDDR4__DENALI_PHY_566__PHY_GTLVL_STATUS_OBS_2 + +#define LPDDR4__DENALI_PHY_567_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_567_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_567__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_2_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_567__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_567__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_2_WIDTH 10U +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_2__REG DENALI_PHY_567 +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_2__FLD LPDDR4__DENALI_PHY_567__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_2 + +#define LPDDR4__DENALI_PHY_567__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_2_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_567__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_567__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_2_WIDTH 10U +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_2__REG DENALI_PHY_567 +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_2__FLD LPDDR4__DENALI_PHY_567__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_2 + +#define LPDDR4__DENALI_PHY_568_READ_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_568_WRITE_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_568__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_2_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_568__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_568__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_2_WIDTH 2U +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_2__REG DENALI_PHY_568 +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_2__FLD LPDDR4__DENALI_PHY_568__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_2 + +#define LPDDR4__DENALI_PHY_569_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_569_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_569__PHY_RDLVL_STATUS_OBS_2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_569__PHY_RDLVL_STATUS_OBS_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_569__PHY_RDLVL_STATUS_OBS_2_WIDTH 32U +#define LPDDR4__PHY_RDLVL_STATUS_OBS_2__REG DENALI_PHY_569 +#define LPDDR4__PHY_RDLVL_STATUS_OBS_2__FLD LPDDR4__DENALI_PHY_569__PHY_RDLVL_STATUS_OBS_2 + +#define LPDDR4__DENALI_PHY_570_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_570_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_570__PHY_RDLVL_PERIODIC_OBS_2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_570__PHY_RDLVL_PERIODIC_OBS_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_570__PHY_RDLVL_PERIODIC_OBS_2_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PERIODIC_OBS_2__REG DENALI_PHY_570 +#define LPDDR4__PHY_RDLVL_PERIODIC_OBS_2__FLD LPDDR4__DENALI_PHY_570__PHY_RDLVL_PERIODIC_OBS_2 + +#define LPDDR4__DENALI_PHY_571_READ_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_571_WRITE_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_571__PHY_WDQLVL_DQDM_LE_DLY_OBS_2_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_571__PHY_WDQLVL_DQDM_LE_DLY_OBS_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_571__PHY_WDQLVL_DQDM_LE_DLY_OBS_2_WIDTH 11U +#define LPDDR4__PHY_WDQLVL_DQDM_LE_DLY_OBS_2__REG DENALI_PHY_571 +#define LPDDR4__PHY_WDQLVL_DQDM_LE_DLY_OBS_2__FLD LPDDR4__DENALI_PHY_571__PHY_WDQLVL_DQDM_LE_DLY_OBS_2 + +#define LPDDR4__DENALI_PHY_571__PHY_WDQLVL_DQDM_TE_DLY_OBS_2_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_571__PHY_WDQLVL_DQDM_TE_DLY_OBS_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_571__PHY_WDQLVL_DQDM_TE_DLY_OBS_2_WIDTH 11U +#define LPDDR4__PHY_WDQLVL_DQDM_TE_DLY_OBS_2__REG DENALI_PHY_571 +#define LPDDR4__PHY_WDQLVL_DQDM_TE_DLY_OBS_2__FLD LPDDR4__DENALI_PHY_571__PHY_WDQLVL_DQDM_TE_DLY_OBS_2 + +#define LPDDR4__DENALI_PHY_572_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_572_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_572__PHY_WDQLVL_STATUS_OBS_2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_572__PHY_WDQLVL_STATUS_OBS_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_572__PHY_WDQLVL_STATUS_OBS_2_WIDTH 32U +#define LPDDR4__PHY_WDQLVL_STATUS_OBS_2__REG DENALI_PHY_572 +#define LPDDR4__PHY_WDQLVL_STATUS_OBS_2__FLD LPDDR4__DENALI_PHY_572__PHY_WDQLVL_STATUS_OBS_2 + +#define LPDDR4__DENALI_PHY_573_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_573_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_573__PHY_WDQLVL_PERIODIC_OBS_2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_573__PHY_WDQLVL_PERIODIC_OBS_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_573__PHY_WDQLVL_PERIODIC_OBS_2_WIDTH 32U +#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_2__REG DENALI_PHY_573 +#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_2__FLD LPDDR4__DENALI_PHY_573__PHY_WDQLVL_PERIODIC_OBS_2 + +#define LPDDR4__DENALI_PHY_574_READ_MASK 0x7FFFFFFFU +#define LPDDR4__DENALI_PHY_574_WRITE_MASK 0x7FFFFFFFU +#define LPDDR4__DENALI_PHY_574__PHY_DDL_MODE_2_MASK 0x7FFFFFFFU +#define LPDDR4__DENALI_PHY_574__PHY_DDL_MODE_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_574__PHY_DDL_MODE_2_WIDTH 31U +#define LPDDR4__PHY_DDL_MODE_2__REG DENALI_PHY_574 +#define LPDDR4__PHY_DDL_MODE_2__FLD LPDDR4__DENALI_PHY_574__PHY_DDL_MODE_2 + +#define LPDDR4__DENALI_PHY_575_READ_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_575_WRITE_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_575__PHY_DDL_MASK_2_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_575__PHY_DDL_MASK_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_575__PHY_DDL_MASK_2_WIDTH 6U +#define LPDDR4__PHY_DDL_MASK_2__REG DENALI_PHY_575 +#define LPDDR4__PHY_DDL_MASK_2__FLD LPDDR4__DENALI_PHY_575__PHY_DDL_MASK_2 + +#define LPDDR4__DENALI_PHY_576_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_576_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_576__PHY_DDL_TEST_OBS_2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_576__PHY_DDL_TEST_OBS_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_576__PHY_DDL_TEST_OBS_2_WIDTH 32U +#define LPDDR4__PHY_DDL_TEST_OBS_2__REG DENALI_PHY_576 +#define LPDDR4__PHY_DDL_TEST_OBS_2__FLD LPDDR4__DENALI_PHY_576__PHY_DDL_TEST_OBS_2 + +#define LPDDR4__DENALI_PHY_577_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_577_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_577__PHY_DDL_TEST_MSTR_DLY_OBS_2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_577__PHY_DDL_TEST_MSTR_DLY_OBS_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_577__PHY_DDL_TEST_MSTR_DLY_OBS_2_WIDTH 32U +#define LPDDR4__PHY_DDL_TEST_MSTR_DLY_OBS_2__REG DENALI_PHY_577 +#define LPDDR4__PHY_DDL_TEST_MSTR_DLY_OBS_2__FLD LPDDR4__DENALI_PHY_577__PHY_DDL_TEST_MSTR_DLY_OBS_2 + +#define LPDDR4__DENALI_PHY_578_READ_MASK 0x010001FFU +#define LPDDR4__DENALI_PHY_578_WRITE_MASK 0x010001FFU +#define LPDDR4__DENALI_PHY_578__PHY_DDL_TRACK_UPD_THRESHOLD_2_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_578__PHY_DDL_TRACK_UPD_THRESHOLD_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_578__PHY_DDL_TRACK_UPD_THRESHOLD_2_WIDTH 8U +#define LPDDR4__PHY_DDL_TRACK_UPD_THRESHOLD_2__REG DENALI_PHY_578 +#define LPDDR4__PHY_DDL_TRACK_UPD_THRESHOLD_2__FLD LPDDR4__DENALI_PHY_578__PHY_DDL_TRACK_UPD_THRESHOLD_2 + +#define LPDDR4__DENALI_PHY_578__PHY_LP4_WDQS_OE_EXTEND_2_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_578__PHY_LP4_WDQS_OE_EXTEND_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_578__PHY_LP4_WDQS_OE_EXTEND_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_578__PHY_LP4_WDQS_OE_EXTEND_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_578__PHY_LP4_WDQS_OE_EXTEND_2_WOSET 0U +#define LPDDR4__PHY_LP4_WDQS_OE_EXTEND_2__REG DENALI_PHY_578 +#define LPDDR4__PHY_LP4_WDQS_OE_EXTEND_2__FLD LPDDR4__DENALI_PHY_578__PHY_LP4_WDQS_OE_EXTEND_2 + +#define LPDDR4__DENALI_PHY_578__SC_PHY_RX_CAL_START_2_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_578__SC_PHY_RX_CAL_START_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_578__SC_PHY_RX_CAL_START_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_578__SC_PHY_RX_CAL_START_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_578__SC_PHY_RX_CAL_START_2_WOSET 0U +#define LPDDR4__SC_PHY_RX_CAL_START_2__REG DENALI_PHY_578 +#define LPDDR4__SC_PHY_RX_CAL_START_2__FLD LPDDR4__DENALI_PHY_578__SC_PHY_RX_CAL_START_2 + +#define LPDDR4__DENALI_PHY_578__PHY_RX_CAL_OVERRIDE_2_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_578__PHY_RX_CAL_OVERRIDE_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_578__PHY_RX_CAL_OVERRIDE_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_578__PHY_RX_CAL_OVERRIDE_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_578__PHY_RX_CAL_OVERRIDE_2_WOSET 0U +#define LPDDR4__PHY_RX_CAL_OVERRIDE_2__REG DENALI_PHY_578 +#define LPDDR4__PHY_RX_CAL_OVERRIDE_2__FLD LPDDR4__DENALI_PHY_578__PHY_RX_CAL_OVERRIDE_2 + +#define LPDDR4__DENALI_PHY_579_READ_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_579_WRITE_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_579__PHY_RX_CAL_SAMPLE_WAIT_2_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_579__PHY_RX_CAL_SAMPLE_WAIT_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_579__PHY_RX_CAL_SAMPLE_WAIT_2_WIDTH 8U +#define LPDDR4__PHY_RX_CAL_SAMPLE_WAIT_2__REG DENALI_PHY_579 +#define LPDDR4__PHY_RX_CAL_SAMPLE_WAIT_2__FLD LPDDR4__DENALI_PHY_579__PHY_RX_CAL_SAMPLE_WAIT_2 + +#define LPDDR4__DENALI_PHY_579__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_2_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_579__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_579__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_579__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_579__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_2_WOSET 0U +#define LPDDR4__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_2__REG DENALI_PHY_579 +#define LPDDR4__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_2__FLD LPDDR4__DENALI_PHY_579__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_2 + +#define LPDDR4__DENALI_PHY_579__PHY_RX_CAL_DQ0_2_MASK 0x01FF0000U +#define LPDDR4__DENALI_PHY_579__PHY_RX_CAL_DQ0_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_579__PHY_RX_CAL_DQ0_2_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQ0_2__REG DENALI_PHY_579 +#define LPDDR4__PHY_RX_CAL_DQ0_2__FLD LPDDR4__DENALI_PHY_579__PHY_RX_CAL_DQ0_2 + +#define LPDDR4__DENALI_PHY_580_READ_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_580_WRITE_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_580__PHY_RX_CAL_DQ1_2_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_580__PHY_RX_CAL_DQ1_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_580__PHY_RX_CAL_DQ1_2_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQ1_2__REG DENALI_PHY_580 +#define LPDDR4__PHY_RX_CAL_DQ1_2__FLD LPDDR4__DENALI_PHY_580__PHY_RX_CAL_DQ1_2 + +#define LPDDR4__DENALI_PHY_580__PHY_RX_CAL_DQ2_2_MASK 0x01FF0000U +#define LPDDR4__DENALI_PHY_580__PHY_RX_CAL_DQ2_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_580__PHY_RX_CAL_DQ2_2_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQ2_2__REG DENALI_PHY_580 +#define LPDDR4__PHY_RX_CAL_DQ2_2__FLD LPDDR4__DENALI_PHY_580__PHY_RX_CAL_DQ2_2 + +#define LPDDR4__DENALI_PHY_581_READ_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_581_WRITE_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_581__PHY_RX_CAL_DQ3_2_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_581__PHY_RX_CAL_DQ3_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_581__PHY_RX_CAL_DQ3_2_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQ3_2__REG DENALI_PHY_581 +#define LPDDR4__PHY_RX_CAL_DQ3_2__FLD LPDDR4__DENALI_PHY_581__PHY_RX_CAL_DQ3_2 + +#define LPDDR4__DENALI_PHY_581__PHY_RX_CAL_DQ4_2_MASK 0x01FF0000U +#define LPDDR4__DENALI_PHY_581__PHY_RX_CAL_DQ4_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_581__PHY_RX_CAL_DQ4_2_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQ4_2__REG DENALI_PHY_581 +#define LPDDR4__PHY_RX_CAL_DQ4_2__FLD LPDDR4__DENALI_PHY_581__PHY_RX_CAL_DQ4_2 + +#define LPDDR4__DENALI_PHY_582_READ_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_582_WRITE_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_582__PHY_RX_CAL_DQ5_2_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_582__PHY_RX_CAL_DQ5_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_582__PHY_RX_CAL_DQ5_2_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQ5_2__REG DENALI_PHY_582 +#define LPDDR4__PHY_RX_CAL_DQ5_2__FLD LPDDR4__DENALI_PHY_582__PHY_RX_CAL_DQ5_2 + +#define LPDDR4__DENALI_PHY_582__PHY_RX_CAL_DQ6_2_MASK 0x01FF0000U +#define LPDDR4__DENALI_PHY_582__PHY_RX_CAL_DQ6_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_582__PHY_RX_CAL_DQ6_2_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQ6_2__REG DENALI_PHY_582 +#define LPDDR4__PHY_RX_CAL_DQ6_2__FLD LPDDR4__DENALI_PHY_582__PHY_RX_CAL_DQ6_2 + +#define LPDDR4__DENALI_PHY_583_READ_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_583_WRITE_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_583__PHY_RX_CAL_DQ7_2_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_583__PHY_RX_CAL_DQ7_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_583__PHY_RX_CAL_DQ7_2_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQ7_2__REG DENALI_PHY_583 +#define LPDDR4__PHY_RX_CAL_DQ7_2__FLD LPDDR4__DENALI_PHY_583__PHY_RX_CAL_DQ7_2 + +#define LPDDR4__DENALI_PHY_584_READ_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_584_WRITE_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_584__PHY_RX_CAL_DM_2_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_584__PHY_RX_CAL_DM_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_584__PHY_RX_CAL_DM_2_WIDTH 18U +#define LPDDR4__PHY_RX_CAL_DM_2__REG DENALI_PHY_584 +#define LPDDR4__PHY_RX_CAL_DM_2__FLD LPDDR4__DENALI_PHY_584__PHY_RX_CAL_DM_2 + +#define LPDDR4__DENALI_PHY_585_READ_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_585_WRITE_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_585__PHY_RX_CAL_DQS_2_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_585__PHY_RX_CAL_DQS_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_585__PHY_RX_CAL_DQS_2_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQS_2__REG DENALI_PHY_585 +#define LPDDR4__PHY_RX_CAL_DQS_2__FLD LPDDR4__DENALI_PHY_585__PHY_RX_CAL_DQS_2 + +#define LPDDR4__DENALI_PHY_585__PHY_RX_CAL_FDBK_2_MASK 0x01FF0000U +#define LPDDR4__DENALI_PHY_585__PHY_RX_CAL_FDBK_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_585__PHY_RX_CAL_FDBK_2_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_FDBK_2__REG DENALI_PHY_585 +#define LPDDR4__PHY_RX_CAL_FDBK_2__FLD LPDDR4__DENALI_PHY_585__PHY_RX_CAL_FDBK_2 + +#define LPDDR4__DENALI_PHY_586_READ_MASK 0x01FF07FFU +#define LPDDR4__DENALI_PHY_586_WRITE_MASK 0x01FF07FFU +#define LPDDR4__DENALI_PHY_586__PHY_RX_CAL_OBS_2_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_586__PHY_RX_CAL_OBS_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_586__PHY_RX_CAL_OBS_2_WIDTH 11U +#define LPDDR4__PHY_RX_CAL_OBS_2__REG DENALI_PHY_586 +#define LPDDR4__PHY_RX_CAL_OBS_2__FLD LPDDR4__DENALI_PHY_586__PHY_RX_CAL_OBS_2 + +#define LPDDR4__DENALI_PHY_586__PHY_RX_CAL_LOCK_OBS_2_MASK 0x01FF0000U +#define LPDDR4__DENALI_PHY_586__PHY_RX_CAL_LOCK_OBS_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_586__PHY_RX_CAL_LOCK_OBS_2_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_LOCK_OBS_2__REG DENALI_PHY_586 +#define LPDDR4__PHY_RX_CAL_LOCK_OBS_2__FLD LPDDR4__DENALI_PHY_586__PHY_RX_CAL_LOCK_OBS_2 + +#define LPDDR4__DENALI_PHY_587_READ_MASK 0x017F7F01U +#define LPDDR4__DENALI_PHY_587_WRITE_MASK 0x017F7F01U +#define LPDDR4__DENALI_PHY_587__PHY_RX_CAL_DISABLE_2_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_587__PHY_RX_CAL_DISABLE_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_587__PHY_RX_CAL_DISABLE_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_587__PHY_RX_CAL_DISABLE_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_587__PHY_RX_CAL_DISABLE_2_WOSET 0U +#define LPDDR4__PHY_RX_CAL_DISABLE_2__REG DENALI_PHY_587 +#define LPDDR4__PHY_RX_CAL_DISABLE_2__FLD LPDDR4__DENALI_PHY_587__PHY_RX_CAL_DISABLE_2 + +#define LPDDR4__DENALI_PHY_587__PHY_RX_CAL_SE_ADJUST_2_MASK 0x00007F00U +#define LPDDR4__DENALI_PHY_587__PHY_RX_CAL_SE_ADJUST_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_587__PHY_RX_CAL_SE_ADJUST_2_WIDTH 7U +#define LPDDR4__PHY_RX_CAL_SE_ADJUST_2__REG DENALI_PHY_587 +#define LPDDR4__PHY_RX_CAL_SE_ADJUST_2__FLD LPDDR4__DENALI_PHY_587__PHY_RX_CAL_SE_ADJUST_2 + +#define LPDDR4__DENALI_PHY_587__PHY_RX_CAL_DIFF_ADJUST_2_MASK 0x007F0000U +#define LPDDR4__DENALI_PHY_587__PHY_RX_CAL_DIFF_ADJUST_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_587__PHY_RX_CAL_DIFF_ADJUST_2_WIDTH 7U +#define LPDDR4__PHY_RX_CAL_DIFF_ADJUST_2__REG DENALI_PHY_587 +#define LPDDR4__PHY_RX_CAL_DIFF_ADJUST_2__FLD LPDDR4__DENALI_PHY_587__PHY_RX_CAL_DIFF_ADJUST_2 + +#define LPDDR4__DENALI_PHY_587__PHY_RX_CAL_COMP_VAL_2_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_587__PHY_RX_CAL_COMP_VAL_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_587__PHY_RX_CAL_COMP_VAL_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_587__PHY_RX_CAL_COMP_VAL_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_587__PHY_RX_CAL_COMP_VAL_2_WOSET 0U +#define LPDDR4__PHY_RX_CAL_COMP_VAL_2__REG DENALI_PHY_587 +#define LPDDR4__PHY_RX_CAL_COMP_VAL_2__FLD LPDDR4__DENALI_PHY_587__PHY_RX_CAL_COMP_VAL_2 + +#define LPDDR4__DENALI_PHY_588_READ_MASK 0x07FF0FFFU +#define LPDDR4__DENALI_PHY_588_WRITE_MASK 0x07FF0FFFU +#define LPDDR4__DENALI_PHY_588__PHY_RX_CAL_INDEX_MASK_2_MASK 0x00000FFFU +#define LPDDR4__DENALI_PHY_588__PHY_RX_CAL_INDEX_MASK_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_588__PHY_RX_CAL_INDEX_MASK_2_WIDTH 12U +#define LPDDR4__PHY_RX_CAL_INDEX_MASK_2__REG DENALI_PHY_588 +#define LPDDR4__PHY_RX_CAL_INDEX_MASK_2__FLD LPDDR4__DENALI_PHY_588__PHY_RX_CAL_INDEX_MASK_2 + +#define LPDDR4__DENALI_PHY_588__PHY_PAD_RX_BIAS_EN_2_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_588__PHY_PAD_RX_BIAS_EN_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_588__PHY_PAD_RX_BIAS_EN_2_WIDTH 11U +#define LPDDR4__PHY_PAD_RX_BIAS_EN_2__REG DENALI_PHY_588 +#define LPDDR4__PHY_PAD_RX_BIAS_EN_2__FLD LPDDR4__DENALI_PHY_588__PHY_PAD_RX_BIAS_EN_2 + +#define LPDDR4__DENALI_PHY_589_READ_MASK 0x03FFFF1FU +#define LPDDR4__DENALI_PHY_589_WRITE_MASK 0x03FFFF1FU +#define LPDDR4__DENALI_PHY_589__PHY_STATIC_TOG_DISABLE_2_MASK 0x0000001FU +#define LPDDR4__DENALI_PHY_589__PHY_STATIC_TOG_DISABLE_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_589__PHY_STATIC_TOG_DISABLE_2_WIDTH 5U +#define LPDDR4__PHY_STATIC_TOG_DISABLE_2__REG DENALI_PHY_589 +#define LPDDR4__PHY_STATIC_TOG_DISABLE_2__FLD LPDDR4__DENALI_PHY_589__PHY_STATIC_TOG_DISABLE_2 + +#define LPDDR4__DENALI_PHY_589__PHY_DATA_DC_CAL_SAMPLE_WAIT_2_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_589__PHY_DATA_DC_CAL_SAMPLE_WAIT_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_589__PHY_DATA_DC_CAL_SAMPLE_WAIT_2_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_CAL_SAMPLE_WAIT_2__REG DENALI_PHY_589 +#define LPDDR4__PHY_DATA_DC_CAL_SAMPLE_WAIT_2__FLD LPDDR4__DENALI_PHY_589__PHY_DATA_DC_CAL_SAMPLE_WAIT_2 + +#define LPDDR4__DENALI_PHY_589__PHY_DATA_DC_CAL_TIMEOUT_2_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_589__PHY_DATA_DC_CAL_TIMEOUT_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_589__PHY_DATA_DC_CAL_TIMEOUT_2_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_CAL_TIMEOUT_2__REG DENALI_PHY_589 +#define LPDDR4__PHY_DATA_DC_CAL_TIMEOUT_2__FLD LPDDR4__DENALI_PHY_589__PHY_DATA_DC_CAL_TIMEOUT_2 + +#define LPDDR4__DENALI_PHY_589__PHY_DATA_DC_WEIGHT_2_MASK 0x03000000U +#define LPDDR4__DENALI_PHY_589__PHY_DATA_DC_WEIGHT_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_589__PHY_DATA_DC_WEIGHT_2_WIDTH 2U +#define LPDDR4__PHY_DATA_DC_WEIGHT_2__REG DENALI_PHY_589 +#define LPDDR4__PHY_DATA_DC_WEIGHT_2__FLD LPDDR4__DENALI_PHY_589__PHY_DATA_DC_WEIGHT_2 + +#define LPDDR4__DENALI_PHY_590_READ_MASK 0x01FFFF3FU +#define LPDDR4__DENALI_PHY_590_WRITE_MASK 0x01FFFF3FU +#define LPDDR4__DENALI_PHY_590__PHY_DATA_DC_ADJUST_START_2_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_590__PHY_DATA_DC_ADJUST_START_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_590__PHY_DATA_DC_ADJUST_START_2_WIDTH 6U +#define LPDDR4__PHY_DATA_DC_ADJUST_START_2__REG DENALI_PHY_590 +#define LPDDR4__PHY_DATA_DC_ADJUST_START_2__FLD LPDDR4__DENALI_PHY_590__PHY_DATA_DC_ADJUST_START_2 + +#define LPDDR4__DENALI_PHY_590__PHY_DATA_DC_ADJUST_SAMPLE_CNT_2_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_590__PHY_DATA_DC_ADJUST_SAMPLE_CNT_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_590__PHY_DATA_DC_ADJUST_SAMPLE_CNT_2_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_ADJUST_SAMPLE_CNT_2__REG DENALI_PHY_590 +#define LPDDR4__PHY_DATA_DC_ADJUST_SAMPLE_CNT_2__FLD LPDDR4__DENALI_PHY_590__PHY_DATA_DC_ADJUST_SAMPLE_CNT_2 + +#define LPDDR4__DENALI_PHY_590__PHY_DATA_DC_ADJUST_THRSHLD_2_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_590__PHY_DATA_DC_ADJUST_THRSHLD_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_590__PHY_DATA_DC_ADJUST_THRSHLD_2_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_ADJUST_THRSHLD_2__REG DENALI_PHY_590 +#define LPDDR4__PHY_DATA_DC_ADJUST_THRSHLD_2__FLD LPDDR4__DENALI_PHY_590__PHY_DATA_DC_ADJUST_THRSHLD_2 + +#define LPDDR4__DENALI_PHY_590__PHY_DATA_DC_ADJUST_DIRECT_2_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_590__PHY_DATA_DC_ADJUST_DIRECT_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_590__PHY_DATA_DC_ADJUST_DIRECT_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_590__PHY_DATA_DC_ADJUST_DIRECT_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_590__PHY_DATA_DC_ADJUST_DIRECT_2_WOSET 0U +#define LPDDR4__PHY_DATA_DC_ADJUST_DIRECT_2__REG DENALI_PHY_590 +#define LPDDR4__PHY_DATA_DC_ADJUST_DIRECT_2__FLD LPDDR4__DENALI_PHY_590__PHY_DATA_DC_ADJUST_DIRECT_2 + +#define LPDDR4__DENALI_PHY_591_READ_MASK 0x07030101U +#define LPDDR4__DENALI_PHY_591_WRITE_MASK 0x07030101U +#define LPDDR4__DENALI_PHY_591__PHY_DATA_DC_CAL_POLARITY_2_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_591__PHY_DATA_DC_CAL_POLARITY_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_591__PHY_DATA_DC_CAL_POLARITY_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_591__PHY_DATA_DC_CAL_POLARITY_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_591__PHY_DATA_DC_CAL_POLARITY_2_WOSET 0U +#define LPDDR4__PHY_DATA_DC_CAL_POLARITY_2__REG DENALI_PHY_591 +#define LPDDR4__PHY_DATA_DC_CAL_POLARITY_2__FLD LPDDR4__DENALI_PHY_591__PHY_DATA_DC_CAL_POLARITY_2 + +#define LPDDR4__DENALI_PHY_591__PHY_DATA_DC_CAL_START_2_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_591__PHY_DATA_DC_CAL_START_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_591__PHY_DATA_DC_CAL_START_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_591__PHY_DATA_DC_CAL_START_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_591__PHY_DATA_DC_CAL_START_2_WOSET 0U +#define LPDDR4__PHY_DATA_DC_CAL_START_2__REG DENALI_PHY_591 +#define LPDDR4__PHY_DATA_DC_CAL_START_2__FLD LPDDR4__DENALI_PHY_591__PHY_DATA_DC_CAL_START_2 + +#define LPDDR4__DENALI_PHY_591__PHY_DATA_DC_SW_RANK_2_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_591__PHY_DATA_DC_SW_RANK_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_591__PHY_DATA_DC_SW_RANK_2_WIDTH 2U +#define LPDDR4__PHY_DATA_DC_SW_RANK_2__REG DENALI_PHY_591 +#define LPDDR4__PHY_DATA_DC_SW_RANK_2__FLD LPDDR4__DENALI_PHY_591__PHY_DATA_DC_SW_RANK_2 + +#define LPDDR4__DENALI_PHY_591__PHY_FDBK_PWR_CTRL_2_MASK 0x07000000U +#define LPDDR4__DENALI_PHY_591__PHY_FDBK_PWR_CTRL_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_591__PHY_FDBK_PWR_CTRL_2_WIDTH 3U +#define LPDDR4__PHY_FDBK_PWR_CTRL_2__REG DENALI_PHY_591 +#define LPDDR4__PHY_FDBK_PWR_CTRL_2__FLD LPDDR4__DENALI_PHY_591__PHY_FDBK_PWR_CTRL_2 + +#define LPDDR4__DENALI_PHY_592_READ_MASK 0x01010101U +#define LPDDR4__DENALI_PHY_592_WRITE_MASK 0x01010101U +#define LPDDR4__DENALI_PHY_592__PHY_SLV_DLY_CTRL_GATE_DISABLE_2_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_592__PHY_SLV_DLY_CTRL_GATE_DISABLE_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_592__PHY_SLV_DLY_CTRL_GATE_DISABLE_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_592__PHY_SLV_DLY_CTRL_GATE_DISABLE_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_592__PHY_SLV_DLY_CTRL_GATE_DISABLE_2_WOSET 0U +#define LPDDR4__PHY_SLV_DLY_CTRL_GATE_DISABLE_2__REG DENALI_PHY_592 +#define LPDDR4__PHY_SLV_DLY_CTRL_GATE_DISABLE_2__FLD LPDDR4__DENALI_PHY_592__PHY_SLV_DLY_CTRL_GATE_DISABLE_2 + +#define LPDDR4__DENALI_PHY_592__PHY_RDPATH_GATE_DISABLE_2_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_592__PHY_RDPATH_GATE_DISABLE_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_592__PHY_RDPATH_GATE_DISABLE_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_592__PHY_RDPATH_GATE_DISABLE_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_592__PHY_RDPATH_GATE_DISABLE_2_WOSET 0U +#define LPDDR4__PHY_RDPATH_GATE_DISABLE_2__REG DENALI_PHY_592 +#define LPDDR4__PHY_RDPATH_GATE_DISABLE_2__FLD LPDDR4__DENALI_PHY_592__PHY_RDPATH_GATE_DISABLE_2 + +#define LPDDR4__DENALI_PHY_592__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_2_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_592__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_592__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_592__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_592__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_2_WOSET 0U +#define LPDDR4__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_2__REG DENALI_PHY_592 +#define LPDDR4__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_2__FLD LPDDR4__DENALI_PHY_592__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_2 + +#define LPDDR4__DENALI_PHY_592__PHY_SLICE_PWR_RDC_DISABLE_2_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_592__PHY_SLICE_PWR_RDC_DISABLE_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_592__PHY_SLICE_PWR_RDC_DISABLE_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_592__PHY_SLICE_PWR_RDC_DISABLE_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_592__PHY_SLICE_PWR_RDC_DISABLE_2_WOSET 0U +#define LPDDR4__PHY_SLICE_PWR_RDC_DISABLE_2__REG DENALI_PHY_592 +#define LPDDR4__PHY_SLICE_PWR_RDC_DISABLE_2__FLD LPDDR4__DENALI_PHY_592__PHY_SLICE_PWR_RDC_DISABLE_2 + +#define LPDDR4__DENALI_PHY_593_READ_MASK 0x3FFF07FFU +#define LPDDR4__DENALI_PHY_593_WRITE_MASK 0x3FFF07FFU +#define LPDDR4__DENALI_PHY_593__PHY_PARITY_ERROR_REGIF_2_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_593__PHY_PARITY_ERROR_REGIF_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_593__PHY_PARITY_ERROR_REGIF_2_WIDTH 11U +#define LPDDR4__PHY_PARITY_ERROR_REGIF_2__REG DENALI_PHY_593 +#define LPDDR4__PHY_PARITY_ERROR_REGIF_2__FLD LPDDR4__DENALI_PHY_593__PHY_PARITY_ERROR_REGIF_2 + +#define LPDDR4__DENALI_PHY_593__PHY_DS_FSM_ERROR_INFO_2_MASK 0x3FFF0000U +#define LPDDR4__DENALI_PHY_593__PHY_DS_FSM_ERROR_INFO_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_593__PHY_DS_FSM_ERROR_INFO_2_WIDTH 14U +#define LPDDR4__PHY_DS_FSM_ERROR_INFO_2__REG DENALI_PHY_593 +#define LPDDR4__PHY_DS_FSM_ERROR_INFO_2__FLD LPDDR4__DENALI_PHY_593__PHY_DS_FSM_ERROR_INFO_2 + +#define LPDDR4__DENALI_PHY_594_READ_MASK 0x00003FFFU +#define LPDDR4__DENALI_PHY_594_WRITE_MASK 0x00003FFFU +#define LPDDR4__DENALI_PHY_594__PHY_DS_FSM_ERROR_INFO_MASK_2_MASK 0x00003FFFU +#define LPDDR4__DENALI_PHY_594__PHY_DS_FSM_ERROR_INFO_MASK_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_594__PHY_DS_FSM_ERROR_INFO_MASK_2_WIDTH 14U +#define LPDDR4__PHY_DS_FSM_ERROR_INFO_MASK_2__REG DENALI_PHY_594 +#define LPDDR4__PHY_DS_FSM_ERROR_INFO_MASK_2__FLD LPDDR4__DENALI_PHY_594__PHY_DS_FSM_ERROR_INFO_MASK_2 + +#define LPDDR4__DENALI_PHY_594__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_2_MASK 0x3FFF0000U +#define LPDDR4__DENALI_PHY_594__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_594__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_2_WIDTH 14U +#define LPDDR4__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_2__REG DENALI_PHY_594 +#define LPDDR4__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_2__FLD LPDDR4__DENALI_PHY_594__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_2 + +#define LPDDR4__DENALI_PHY_595_READ_MASK 0x00001F1FU +#define LPDDR4__DENALI_PHY_595_WRITE_MASK 0x00001F1FU +#define LPDDR4__DENALI_PHY_595__PHY_DS_TRAIN_CALIB_ERROR_INFO_2_MASK 0x0000001FU +#define LPDDR4__DENALI_PHY_595__PHY_DS_TRAIN_CALIB_ERROR_INFO_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_595__PHY_DS_TRAIN_CALIB_ERROR_INFO_2_WIDTH 5U +#define LPDDR4__PHY_DS_TRAIN_CALIB_ERROR_INFO_2__REG DENALI_PHY_595 +#define LPDDR4__PHY_DS_TRAIN_CALIB_ERROR_INFO_2__FLD LPDDR4__DENALI_PHY_595__PHY_DS_TRAIN_CALIB_ERROR_INFO_2 + +#define LPDDR4__DENALI_PHY_595__PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_2_MASK 0x00001F00U +#define LPDDR4__DENALI_PHY_595__PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_595__PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_2_WIDTH 5U +#define LPDDR4__PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_2__REG DENALI_PHY_595 +#define LPDDR4__PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_2__FLD LPDDR4__DENALI_PHY_595__PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_2 + +#define LPDDR4__DENALI_PHY_595__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_2_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_595__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_595__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_2_WIDTH 5U +#define LPDDR4__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_2__REG DENALI_PHY_595 +#define LPDDR4__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_2__FLD LPDDR4__DENALI_PHY_595__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_2 + +#define LPDDR4__DENALI_PHY_596_READ_MASK 0x07FFFF07U +#define LPDDR4__DENALI_PHY_596_WRITE_MASK 0x07FFFF07U +#define LPDDR4__DENALI_PHY_596__PHY_DQ_TSEL_ENABLE_2_MASK 0x00000007U +#define LPDDR4__DENALI_PHY_596__PHY_DQ_TSEL_ENABLE_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_596__PHY_DQ_TSEL_ENABLE_2_WIDTH 3U +#define LPDDR4__PHY_DQ_TSEL_ENABLE_2__REG DENALI_PHY_596 +#define LPDDR4__PHY_DQ_TSEL_ENABLE_2__FLD LPDDR4__DENALI_PHY_596__PHY_DQ_TSEL_ENABLE_2 + +#define LPDDR4__DENALI_PHY_596__PHY_DQ_TSEL_SELECT_2_MASK 0x00FFFF00U +#define LPDDR4__DENALI_PHY_596__PHY_DQ_TSEL_SELECT_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_596__PHY_DQ_TSEL_SELECT_2_WIDTH 16U +#define LPDDR4__PHY_DQ_TSEL_SELECT_2__REG DENALI_PHY_596 +#define LPDDR4__PHY_DQ_TSEL_SELECT_2__FLD LPDDR4__DENALI_PHY_596__PHY_DQ_TSEL_SELECT_2 + +#define LPDDR4__DENALI_PHY_596__PHY_DQS_TSEL_ENABLE_2_MASK 0x07000000U +#define LPDDR4__DENALI_PHY_596__PHY_DQS_TSEL_ENABLE_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_596__PHY_DQS_TSEL_ENABLE_2_WIDTH 3U +#define LPDDR4__PHY_DQS_TSEL_ENABLE_2__REG DENALI_PHY_596 +#define LPDDR4__PHY_DQS_TSEL_ENABLE_2__FLD LPDDR4__DENALI_PHY_596__PHY_DQS_TSEL_ENABLE_2 + +#define LPDDR4__DENALI_PHY_597_READ_MASK 0x7F03FFFFU +#define LPDDR4__DENALI_PHY_597_WRITE_MASK 0x7F03FFFFU +#define LPDDR4__DENALI_PHY_597__PHY_DQS_TSEL_SELECT_2_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_597__PHY_DQS_TSEL_SELECT_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_597__PHY_DQS_TSEL_SELECT_2_WIDTH 16U +#define LPDDR4__PHY_DQS_TSEL_SELECT_2__REG DENALI_PHY_597 +#define LPDDR4__PHY_DQS_TSEL_SELECT_2__FLD LPDDR4__DENALI_PHY_597__PHY_DQS_TSEL_SELECT_2 + +#define LPDDR4__DENALI_PHY_597__PHY_TWO_CYC_PREAMBLE_2_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_597__PHY_TWO_CYC_PREAMBLE_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_597__PHY_TWO_CYC_PREAMBLE_2_WIDTH 2U +#define LPDDR4__PHY_TWO_CYC_PREAMBLE_2__REG DENALI_PHY_597 +#define LPDDR4__PHY_TWO_CYC_PREAMBLE_2__FLD LPDDR4__DENALI_PHY_597__PHY_TWO_CYC_PREAMBLE_2 + +#define LPDDR4__DENALI_PHY_597__PHY_VREF_INITIAL_START_POINT_2_MASK 0x7F000000U +#define LPDDR4__DENALI_PHY_597__PHY_VREF_INITIAL_START_POINT_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_597__PHY_VREF_INITIAL_START_POINT_2_WIDTH 7U +#define LPDDR4__PHY_VREF_INITIAL_START_POINT_2__REG DENALI_PHY_597 +#define LPDDR4__PHY_VREF_INITIAL_START_POINT_2__FLD LPDDR4__DENALI_PHY_597__PHY_VREF_INITIAL_START_POINT_2 + +#define LPDDR4__DENALI_PHY_598_READ_MASK 0xFF01037FU +#define LPDDR4__DENALI_PHY_598_WRITE_MASK 0xFF01037FU +#define LPDDR4__DENALI_PHY_598__PHY_VREF_INITIAL_STOP_POINT_2_MASK 0x0000007FU +#define LPDDR4__DENALI_PHY_598__PHY_VREF_INITIAL_STOP_POINT_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_598__PHY_VREF_INITIAL_STOP_POINT_2_WIDTH 7U +#define LPDDR4__PHY_VREF_INITIAL_STOP_POINT_2__REG DENALI_PHY_598 +#define LPDDR4__PHY_VREF_INITIAL_STOP_POINT_2__FLD LPDDR4__DENALI_PHY_598__PHY_VREF_INITIAL_STOP_POINT_2 + +#define LPDDR4__DENALI_PHY_598__PHY_VREF_TRAINING_CTRL_2_MASK 0x00000300U +#define LPDDR4__DENALI_PHY_598__PHY_VREF_TRAINING_CTRL_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_598__PHY_VREF_TRAINING_CTRL_2_WIDTH 2U +#define LPDDR4__PHY_VREF_TRAINING_CTRL_2__REG DENALI_PHY_598 +#define LPDDR4__PHY_VREF_TRAINING_CTRL_2__FLD LPDDR4__DENALI_PHY_598__PHY_VREF_TRAINING_CTRL_2 + +#define LPDDR4__DENALI_PHY_598__PHY_NTP_TRAIN_EN_2_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_598__PHY_NTP_TRAIN_EN_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_598__PHY_NTP_TRAIN_EN_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_598__PHY_NTP_TRAIN_EN_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_598__PHY_NTP_TRAIN_EN_2_WOSET 0U +#define LPDDR4__PHY_NTP_TRAIN_EN_2__REG DENALI_PHY_598 +#define LPDDR4__PHY_NTP_TRAIN_EN_2__FLD LPDDR4__DENALI_PHY_598__PHY_NTP_TRAIN_EN_2 + +#define LPDDR4__DENALI_PHY_598__PHY_NTP_WDQ_STEP_SIZE_2_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_598__PHY_NTP_WDQ_STEP_SIZE_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_598__PHY_NTP_WDQ_STEP_SIZE_2_WIDTH 8U +#define LPDDR4__PHY_NTP_WDQ_STEP_SIZE_2__REG DENALI_PHY_598 +#define LPDDR4__PHY_NTP_WDQ_STEP_SIZE_2__FLD LPDDR4__DENALI_PHY_598__PHY_NTP_WDQ_STEP_SIZE_2 + +#define LPDDR4__DENALI_PHY_599_READ_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_599_WRITE_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_599__PHY_NTP_WDQ_START_2_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_599__PHY_NTP_WDQ_START_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_599__PHY_NTP_WDQ_START_2_WIDTH 11U +#define LPDDR4__PHY_NTP_WDQ_START_2__REG DENALI_PHY_599 +#define LPDDR4__PHY_NTP_WDQ_START_2__FLD LPDDR4__DENALI_PHY_599__PHY_NTP_WDQ_START_2 + +#define LPDDR4__DENALI_PHY_599__PHY_NTP_WDQ_STOP_2_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_599__PHY_NTP_WDQ_STOP_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_599__PHY_NTP_WDQ_STOP_2_WIDTH 11U +#define LPDDR4__PHY_NTP_WDQ_STOP_2__REG DENALI_PHY_599 +#define LPDDR4__PHY_NTP_WDQ_STOP_2__FLD LPDDR4__DENALI_PHY_599__PHY_NTP_WDQ_STOP_2 + +#define LPDDR4__DENALI_PHY_600_READ_MASK 0x0103FFFFU +#define LPDDR4__DENALI_PHY_600_WRITE_MASK 0x0103FFFFU +#define LPDDR4__DENALI_PHY_600__PHY_NTP_WDQ_BIT_EN_2_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_600__PHY_NTP_WDQ_BIT_EN_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_600__PHY_NTP_WDQ_BIT_EN_2_WIDTH 8U +#define LPDDR4__PHY_NTP_WDQ_BIT_EN_2__REG DENALI_PHY_600 +#define LPDDR4__PHY_NTP_WDQ_BIT_EN_2__FLD LPDDR4__DENALI_PHY_600__PHY_NTP_WDQ_BIT_EN_2 + +#define LPDDR4__DENALI_PHY_600__PHY_WDQLVL_DVW_MIN_2_MASK 0x0003FF00U +#define LPDDR4__DENALI_PHY_600__PHY_WDQLVL_DVW_MIN_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_600__PHY_WDQLVL_DVW_MIN_2_WIDTH 10U +#define LPDDR4__PHY_WDQLVL_DVW_MIN_2__REG DENALI_PHY_600 +#define LPDDR4__PHY_WDQLVL_DVW_MIN_2__FLD LPDDR4__DENALI_PHY_600__PHY_WDQLVL_DVW_MIN_2 + +#define LPDDR4__DENALI_PHY_600__PHY_SW_WDQLVL_DVW_MIN_EN_2_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_600__PHY_SW_WDQLVL_DVW_MIN_EN_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_600__PHY_SW_WDQLVL_DVW_MIN_EN_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_600__PHY_SW_WDQLVL_DVW_MIN_EN_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_600__PHY_SW_WDQLVL_DVW_MIN_EN_2_WOSET 0U +#define LPDDR4__PHY_SW_WDQLVL_DVW_MIN_EN_2__REG DENALI_PHY_600 +#define LPDDR4__PHY_SW_WDQLVL_DVW_MIN_EN_2__FLD LPDDR4__DENALI_PHY_600__PHY_SW_WDQLVL_DVW_MIN_EN_2 + +#define LPDDR4__DENALI_PHY_601_READ_MASK 0x1F1F0F3FU +#define LPDDR4__DENALI_PHY_601_WRITE_MASK 0x1F1F0F3FU +#define LPDDR4__DENALI_PHY_601__PHY_WDQLVL_PER_START_OFFSET_2_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_601__PHY_WDQLVL_PER_START_OFFSET_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_601__PHY_WDQLVL_PER_START_OFFSET_2_WIDTH 6U +#define LPDDR4__PHY_WDQLVL_PER_START_OFFSET_2__REG DENALI_PHY_601 +#define LPDDR4__PHY_WDQLVL_PER_START_OFFSET_2__FLD LPDDR4__DENALI_PHY_601__PHY_WDQLVL_PER_START_OFFSET_2 + +#define LPDDR4__DENALI_PHY_601__PHY_FAST_LVL_EN_2_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_601__PHY_FAST_LVL_EN_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_601__PHY_FAST_LVL_EN_2_WIDTH 4U +#define LPDDR4__PHY_FAST_LVL_EN_2__REG DENALI_PHY_601 +#define LPDDR4__PHY_FAST_LVL_EN_2__FLD LPDDR4__DENALI_PHY_601__PHY_FAST_LVL_EN_2 + +#define LPDDR4__DENALI_PHY_601__PHY_PAD_TX_DCD_2_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_601__PHY_PAD_TX_DCD_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_601__PHY_PAD_TX_DCD_2_WIDTH 5U +#define LPDDR4__PHY_PAD_TX_DCD_2__REG DENALI_PHY_601 +#define LPDDR4__PHY_PAD_TX_DCD_2__FLD LPDDR4__DENALI_PHY_601__PHY_PAD_TX_DCD_2 + +#define LPDDR4__DENALI_PHY_601__PHY_PAD_RX_DCD_0_2_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_601__PHY_PAD_RX_DCD_0_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_601__PHY_PAD_RX_DCD_0_2_WIDTH 5U +#define LPDDR4__PHY_PAD_RX_DCD_0_2__REG DENALI_PHY_601 +#define LPDDR4__PHY_PAD_RX_DCD_0_2__FLD LPDDR4__DENALI_PHY_601__PHY_PAD_RX_DCD_0_2 + +#define LPDDR4__DENALI_PHY_602_READ_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_PHY_602_WRITE_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_PHY_602__PHY_PAD_RX_DCD_1_2_MASK 0x0000001FU +#define LPDDR4__DENALI_PHY_602__PHY_PAD_RX_DCD_1_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_602__PHY_PAD_RX_DCD_1_2_WIDTH 5U +#define LPDDR4__PHY_PAD_RX_DCD_1_2__REG DENALI_PHY_602 +#define LPDDR4__PHY_PAD_RX_DCD_1_2__FLD LPDDR4__DENALI_PHY_602__PHY_PAD_RX_DCD_1_2 + +#define LPDDR4__DENALI_PHY_602__PHY_PAD_RX_DCD_2_2_MASK 0x00001F00U +#define LPDDR4__DENALI_PHY_602__PHY_PAD_RX_DCD_2_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_602__PHY_PAD_RX_DCD_2_2_WIDTH 5U +#define LPDDR4__PHY_PAD_RX_DCD_2_2__REG DENALI_PHY_602 +#define LPDDR4__PHY_PAD_RX_DCD_2_2__FLD LPDDR4__DENALI_PHY_602__PHY_PAD_RX_DCD_2_2 + +#define LPDDR4__DENALI_PHY_602__PHY_PAD_RX_DCD_3_2_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_602__PHY_PAD_RX_DCD_3_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_602__PHY_PAD_RX_DCD_3_2_WIDTH 5U +#define LPDDR4__PHY_PAD_RX_DCD_3_2__REG DENALI_PHY_602 +#define LPDDR4__PHY_PAD_RX_DCD_3_2__FLD LPDDR4__DENALI_PHY_602__PHY_PAD_RX_DCD_3_2 + +#define LPDDR4__DENALI_PHY_602__PHY_PAD_RX_DCD_4_2_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_602__PHY_PAD_RX_DCD_4_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_602__PHY_PAD_RX_DCD_4_2_WIDTH 5U +#define LPDDR4__PHY_PAD_RX_DCD_4_2__REG DENALI_PHY_602 +#define LPDDR4__PHY_PAD_RX_DCD_4_2__FLD LPDDR4__DENALI_PHY_602__PHY_PAD_RX_DCD_4_2 + +#define LPDDR4__DENALI_PHY_603_READ_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_PHY_603_WRITE_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_PHY_603__PHY_PAD_RX_DCD_5_2_MASK 0x0000001FU +#define LPDDR4__DENALI_PHY_603__PHY_PAD_RX_DCD_5_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_603__PHY_PAD_RX_DCD_5_2_WIDTH 5U +#define LPDDR4__PHY_PAD_RX_DCD_5_2__REG DENALI_PHY_603 +#define LPDDR4__PHY_PAD_RX_DCD_5_2__FLD LPDDR4__DENALI_PHY_603__PHY_PAD_RX_DCD_5_2 + +#define LPDDR4__DENALI_PHY_603__PHY_PAD_RX_DCD_6_2_MASK 0x00001F00U +#define LPDDR4__DENALI_PHY_603__PHY_PAD_RX_DCD_6_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_603__PHY_PAD_RX_DCD_6_2_WIDTH 5U +#define LPDDR4__PHY_PAD_RX_DCD_6_2__REG DENALI_PHY_603 +#define LPDDR4__PHY_PAD_RX_DCD_6_2__FLD LPDDR4__DENALI_PHY_603__PHY_PAD_RX_DCD_6_2 + +#define LPDDR4__DENALI_PHY_603__PHY_PAD_RX_DCD_7_2_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_603__PHY_PAD_RX_DCD_7_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_603__PHY_PAD_RX_DCD_7_2_WIDTH 5U +#define LPDDR4__PHY_PAD_RX_DCD_7_2__REG DENALI_PHY_603 +#define LPDDR4__PHY_PAD_RX_DCD_7_2__FLD LPDDR4__DENALI_PHY_603__PHY_PAD_RX_DCD_7_2 + +#define LPDDR4__DENALI_PHY_603__PHY_PAD_DM_RX_DCD_2_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_603__PHY_PAD_DM_RX_DCD_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_603__PHY_PAD_DM_RX_DCD_2_WIDTH 5U +#define LPDDR4__PHY_PAD_DM_RX_DCD_2__REG DENALI_PHY_603 +#define LPDDR4__PHY_PAD_DM_RX_DCD_2__FLD LPDDR4__DENALI_PHY_603__PHY_PAD_DM_RX_DCD_2 + +#define LPDDR4__DENALI_PHY_604_READ_MASK 0x003F1F1FU +#define LPDDR4__DENALI_PHY_604_WRITE_MASK 0x003F1F1FU +#define LPDDR4__DENALI_PHY_604__PHY_PAD_DQS_RX_DCD_2_MASK 0x0000001FU +#define LPDDR4__DENALI_PHY_604__PHY_PAD_DQS_RX_DCD_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_604__PHY_PAD_DQS_RX_DCD_2_WIDTH 5U +#define LPDDR4__PHY_PAD_DQS_RX_DCD_2__REG DENALI_PHY_604 +#define LPDDR4__PHY_PAD_DQS_RX_DCD_2__FLD LPDDR4__DENALI_PHY_604__PHY_PAD_DQS_RX_DCD_2 + +#define LPDDR4__DENALI_PHY_604__PHY_PAD_FDBK_RX_DCD_2_MASK 0x00001F00U +#define LPDDR4__DENALI_PHY_604__PHY_PAD_FDBK_RX_DCD_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_604__PHY_PAD_FDBK_RX_DCD_2_WIDTH 5U +#define LPDDR4__PHY_PAD_FDBK_RX_DCD_2__REG DENALI_PHY_604 +#define LPDDR4__PHY_PAD_FDBK_RX_DCD_2__FLD LPDDR4__DENALI_PHY_604__PHY_PAD_FDBK_RX_DCD_2 + +#define LPDDR4__DENALI_PHY_604__PHY_PAD_DSLICE_IO_CFG_2_MASK 0x003F0000U +#define LPDDR4__DENALI_PHY_604__PHY_PAD_DSLICE_IO_CFG_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_604__PHY_PAD_DSLICE_IO_CFG_2_WIDTH 6U +#define LPDDR4__PHY_PAD_DSLICE_IO_CFG_2__REG DENALI_PHY_604 +#define LPDDR4__PHY_PAD_DSLICE_IO_CFG_2__FLD LPDDR4__DENALI_PHY_604__PHY_PAD_DSLICE_IO_CFG_2 + +#define LPDDR4__DENALI_PHY_605_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_605_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_605__PHY_RDDQ0_SLAVE_DELAY_2_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_605__PHY_RDDQ0_SLAVE_DELAY_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_605__PHY_RDDQ0_SLAVE_DELAY_2_WIDTH 10U +#define LPDDR4__PHY_RDDQ0_SLAVE_DELAY_2__REG DENALI_PHY_605 +#define LPDDR4__PHY_RDDQ0_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_605__PHY_RDDQ0_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_605__PHY_RDDQ1_SLAVE_DELAY_2_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_605__PHY_RDDQ1_SLAVE_DELAY_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_605__PHY_RDDQ1_SLAVE_DELAY_2_WIDTH 10U +#define LPDDR4__PHY_RDDQ1_SLAVE_DELAY_2__REG DENALI_PHY_605 +#define LPDDR4__PHY_RDDQ1_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_605__PHY_RDDQ1_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_606_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_606_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_606__PHY_RDDQ2_SLAVE_DELAY_2_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_606__PHY_RDDQ2_SLAVE_DELAY_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_606__PHY_RDDQ2_SLAVE_DELAY_2_WIDTH 10U +#define LPDDR4__PHY_RDDQ2_SLAVE_DELAY_2__REG DENALI_PHY_606 +#define LPDDR4__PHY_RDDQ2_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_606__PHY_RDDQ2_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_606__PHY_RDDQ3_SLAVE_DELAY_2_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_606__PHY_RDDQ3_SLAVE_DELAY_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_606__PHY_RDDQ3_SLAVE_DELAY_2_WIDTH 10U +#define LPDDR4__PHY_RDDQ3_SLAVE_DELAY_2__REG DENALI_PHY_606 +#define LPDDR4__PHY_RDDQ3_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_606__PHY_RDDQ3_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_607_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_607_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_607__PHY_RDDQ4_SLAVE_DELAY_2_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_607__PHY_RDDQ4_SLAVE_DELAY_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_607__PHY_RDDQ4_SLAVE_DELAY_2_WIDTH 10U +#define LPDDR4__PHY_RDDQ4_SLAVE_DELAY_2__REG DENALI_PHY_607 +#define LPDDR4__PHY_RDDQ4_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_607__PHY_RDDQ4_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_607__PHY_RDDQ5_SLAVE_DELAY_2_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_607__PHY_RDDQ5_SLAVE_DELAY_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_607__PHY_RDDQ5_SLAVE_DELAY_2_WIDTH 10U +#define LPDDR4__PHY_RDDQ5_SLAVE_DELAY_2__REG DENALI_PHY_607 +#define LPDDR4__PHY_RDDQ5_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_607__PHY_RDDQ5_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_608_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_608_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_608__PHY_RDDQ6_SLAVE_DELAY_2_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_608__PHY_RDDQ6_SLAVE_DELAY_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_608__PHY_RDDQ6_SLAVE_DELAY_2_WIDTH 10U +#define LPDDR4__PHY_RDDQ6_SLAVE_DELAY_2__REG DENALI_PHY_608 +#define LPDDR4__PHY_RDDQ6_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_608__PHY_RDDQ6_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_608__PHY_RDDQ7_SLAVE_DELAY_2_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_608__PHY_RDDQ7_SLAVE_DELAY_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_608__PHY_RDDQ7_SLAVE_DELAY_2_WIDTH 10U +#define LPDDR4__PHY_RDDQ7_SLAVE_DELAY_2__REG DENALI_PHY_608 +#define LPDDR4__PHY_RDDQ7_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_608__PHY_RDDQ7_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_609_READ_MASK 0x000703FFU +#define LPDDR4__DENALI_PHY_609_WRITE_MASK 0x000703FFU +#define LPDDR4__DENALI_PHY_609__PHY_RDDM_SLAVE_DELAY_2_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_609__PHY_RDDM_SLAVE_DELAY_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_609__PHY_RDDM_SLAVE_DELAY_2_WIDTH 10U +#define LPDDR4__PHY_RDDM_SLAVE_DELAY_2__REG DENALI_PHY_609 +#define LPDDR4__PHY_RDDM_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_609__PHY_RDDM_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_609__PHY_DATA_DC_CAL_CLK_SEL_2_MASK 0x00070000U +#define LPDDR4__DENALI_PHY_609__PHY_DATA_DC_CAL_CLK_SEL_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_609__PHY_DATA_DC_CAL_CLK_SEL_2_WIDTH 3U +#define LPDDR4__PHY_DATA_DC_CAL_CLK_SEL_2__REG DENALI_PHY_609 +#define LPDDR4__PHY_DATA_DC_CAL_CLK_SEL_2__FLD LPDDR4__DENALI_PHY_609__PHY_DATA_DC_CAL_CLK_SEL_2 + +#define LPDDR4__DENALI_PHY_610_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_610_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_610__PHY_DQ_OE_TIMING_2_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_610__PHY_DQ_OE_TIMING_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_610__PHY_DQ_OE_TIMING_2_WIDTH 8U +#define LPDDR4__PHY_DQ_OE_TIMING_2__REG DENALI_PHY_610 +#define LPDDR4__PHY_DQ_OE_TIMING_2__FLD LPDDR4__DENALI_PHY_610__PHY_DQ_OE_TIMING_2 + +#define LPDDR4__DENALI_PHY_610__PHY_DQ_TSEL_RD_TIMING_2_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_610__PHY_DQ_TSEL_RD_TIMING_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_610__PHY_DQ_TSEL_RD_TIMING_2_WIDTH 8U +#define LPDDR4__PHY_DQ_TSEL_RD_TIMING_2__REG DENALI_PHY_610 +#define LPDDR4__PHY_DQ_TSEL_RD_TIMING_2__FLD LPDDR4__DENALI_PHY_610__PHY_DQ_TSEL_RD_TIMING_2 + +#define LPDDR4__DENALI_PHY_610__PHY_DQ_TSEL_WR_TIMING_2_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_610__PHY_DQ_TSEL_WR_TIMING_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_610__PHY_DQ_TSEL_WR_TIMING_2_WIDTH 8U +#define LPDDR4__PHY_DQ_TSEL_WR_TIMING_2__REG DENALI_PHY_610 +#define LPDDR4__PHY_DQ_TSEL_WR_TIMING_2__FLD LPDDR4__DENALI_PHY_610__PHY_DQ_TSEL_WR_TIMING_2 + +#define LPDDR4__DENALI_PHY_610__PHY_DQS_OE_TIMING_2_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_610__PHY_DQS_OE_TIMING_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_610__PHY_DQS_OE_TIMING_2_WIDTH 8U +#define LPDDR4__PHY_DQS_OE_TIMING_2__REG DENALI_PHY_610 +#define LPDDR4__PHY_DQS_OE_TIMING_2__FLD LPDDR4__DENALI_PHY_610__PHY_DQS_OE_TIMING_2 + +#define LPDDR4__DENALI_PHY_611_READ_MASK 0xFFFFFF0FU +#define LPDDR4__DENALI_PHY_611_WRITE_MASK 0xFFFFFF0FU +#define LPDDR4__DENALI_PHY_611__PHY_IO_PAD_DELAY_TIMING_2_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_611__PHY_IO_PAD_DELAY_TIMING_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_611__PHY_IO_PAD_DELAY_TIMING_2_WIDTH 4U +#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_2__REG DENALI_PHY_611 +#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_2__FLD LPDDR4__DENALI_PHY_611__PHY_IO_PAD_DELAY_TIMING_2 + +#define LPDDR4__DENALI_PHY_611__PHY_DQS_TSEL_RD_TIMING_2_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_611__PHY_DQS_TSEL_RD_TIMING_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_611__PHY_DQS_TSEL_RD_TIMING_2_WIDTH 8U +#define LPDDR4__PHY_DQS_TSEL_RD_TIMING_2__REG DENALI_PHY_611 +#define LPDDR4__PHY_DQS_TSEL_RD_TIMING_2__FLD LPDDR4__DENALI_PHY_611__PHY_DQS_TSEL_RD_TIMING_2 + +#define LPDDR4__DENALI_PHY_611__PHY_DQS_OE_RD_TIMING_2_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_611__PHY_DQS_OE_RD_TIMING_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_611__PHY_DQS_OE_RD_TIMING_2_WIDTH 8U +#define LPDDR4__PHY_DQS_OE_RD_TIMING_2__REG DENALI_PHY_611 +#define LPDDR4__PHY_DQS_OE_RD_TIMING_2__FLD LPDDR4__DENALI_PHY_611__PHY_DQS_OE_RD_TIMING_2 + +#define LPDDR4__DENALI_PHY_611__PHY_DQS_TSEL_WR_TIMING_2_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_611__PHY_DQS_TSEL_WR_TIMING_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_611__PHY_DQS_TSEL_WR_TIMING_2_WIDTH 8U +#define LPDDR4__PHY_DQS_TSEL_WR_TIMING_2__REG DENALI_PHY_611 +#define LPDDR4__PHY_DQS_TSEL_WR_TIMING_2__FLD LPDDR4__DENALI_PHY_611__PHY_DQS_TSEL_WR_TIMING_2 + +#define LPDDR4__DENALI_PHY_612_READ_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_612_WRITE_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_612__PHY_VREF_SETTING_TIME_2_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_612__PHY_VREF_SETTING_TIME_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_612__PHY_VREF_SETTING_TIME_2_WIDTH 16U +#define LPDDR4__PHY_VREF_SETTING_TIME_2__REG DENALI_PHY_612 +#define LPDDR4__PHY_VREF_SETTING_TIME_2__FLD LPDDR4__DENALI_PHY_612__PHY_VREF_SETTING_TIME_2 + +#define LPDDR4__DENALI_PHY_612__PHY_PAD_VREF_CTRL_DQ_2_MASK 0x0FFF0000U +#define LPDDR4__DENALI_PHY_612__PHY_PAD_VREF_CTRL_DQ_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_612__PHY_PAD_VREF_CTRL_DQ_2_WIDTH 12U +#define LPDDR4__PHY_PAD_VREF_CTRL_DQ_2__REG DENALI_PHY_612 +#define LPDDR4__PHY_PAD_VREF_CTRL_DQ_2__FLD LPDDR4__DENALI_PHY_612__PHY_PAD_VREF_CTRL_DQ_2 + +#define LPDDR4__DENALI_PHY_613_READ_MASK 0x03FFFF01U +#define LPDDR4__DENALI_PHY_613_WRITE_MASK 0x03FFFF01U +#define LPDDR4__DENALI_PHY_613__PHY_PER_CS_TRAINING_EN_2_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_613__PHY_PER_CS_TRAINING_EN_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_613__PHY_PER_CS_TRAINING_EN_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_613__PHY_PER_CS_TRAINING_EN_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_613__PHY_PER_CS_TRAINING_EN_2_WOSET 0U +#define LPDDR4__PHY_PER_CS_TRAINING_EN_2__REG DENALI_PHY_613 +#define LPDDR4__PHY_PER_CS_TRAINING_EN_2__FLD LPDDR4__DENALI_PHY_613__PHY_PER_CS_TRAINING_EN_2 + +#define LPDDR4__DENALI_PHY_613__PHY_DQ_IE_TIMING_2_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_613__PHY_DQ_IE_TIMING_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_613__PHY_DQ_IE_TIMING_2_WIDTH 8U +#define LPDDR4__PHY_DQ_IE_TIMING_2__REG DENALI_PHY_613 +#define LPDDR4__PHY_DQ_IE_TIMING_2__FLD LPDDR4__DENALI_PHY_613__PHY_DQ_IE_TIMING_2 + +#define LPDDR4__DENALI_PHY_613__PHY_DQS_IE_TIMING_2_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_613__PHY_DQS_IE_TIMING_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_613__PHY_DQS_IE_TIMING_2_WIDTH 8U +#define LPDDR4__PHY_DQS_IE_TIMING_2__REG DENALI_PHY_613 +#define LPDDR4__PHY_DQS_IE_TIMING_2__FLD LPDDR4__DENALI_PHY_613__PHY_DQS_IE_TIMING_2 + +#define LPDDR4__DENALI_PHY_613__PHY_RDDATA_EN_IE_DLY_2_MASK 0x03000000U +#define LPDDR4__DENALI_PHY_613__PHY_RDDATA_EN_IE_DLY_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_613__PHY_RDDATA_EN_IE_DLY_2_WIDTH 2U +#define LPDDR4__PHY_RDDATA_EN_IE_DLY_2__REG DENALI_PHY_613 +#define LPDDR4__PHY_RDDATA_EN_IE_DLY_2__FLD LPDDR4__DENALI_PHY_613__PHY_RDDATA_EN_IE_DLY_2 + +#define LPDDR4__DENALI_PHY_614_READ_MASK 0x1F1F0103U +#define LPDDR4__DENALI_PHY_614_WRITE_MASK 0x1F1F0103U +#define LPDDR4__DENALI_PHY_614__PHY_IE_MODE_2_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_614__PHY_IE_MODE_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_614__PHY_IE_MODE_2_WIDTH 2U +#define LPDDR4__PHY_IE_MODE_2__REG DENALI_PHY_614 +#define LPDDR4__PHY_IE_MODE_2__FLD LPDDR4__DENALI_PHY_614__PHY_IE_MODE_2 + +#define LPDDR4__DENALI_PHY_614__PHY_DBI_MODE_2_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_614__PHY_DBI_MODE_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_614__PHY_DBI_MODE_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_614__PHY_DBI_MODE_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_614__PHY_DBI_MODE_2_WOSET 0U +#define LPDDR4__PHY_DBI_MODE_2__REG DENALI_PHY_614 +#define LPDDR4__PHY_DBI_MODE_2__FLD LPDDR4__DENALI_PHY_614__PHY_DBI_MODE_2 + +#define LPDDR4__DENALI_PHY_614__PHY_RDDATA_EN_TSEL_DLY_2_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_614__PHY_RDDATA_EN_TSEL_DLY_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_614__PHY_RDDATA_EN_TSEL_DLY_2_WIDTH 5U +#define LPDDR4__PHY_RDDATA_EN_TSEL_DLY_2__REG DENALI_PHY_614 +#define LPDDR4__PHY_RDDATA_EN_TSEL_DLY_2__FLD LPDDR4__DENALI_PHY_614__PHY_RDDATA_EN_TSEL_DLY_2 + +#define LPDDR4__DENALI_PHY_614__PHY_RDDATA_EN_OE_DLY_2_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_614__PHY_RDDATA_EN_OE_DLY_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_614__PHY_RDDATA_EN_OE_DLY_2_WIDTH 5U +#define LPDDR4__PHY_RDDATA_EN_OE_DLY_2__REG DENALI_PHY_614 +#define LPDDR4__PHY_RDDATA_EN_OE_DLY_2__FLD LPDDR4__DENALI_PHY_614__PHY_RDDATA_EN_OE_DLY_2 + +#define LPDDR4__DENALI_PHY_615_READ_MASK 0x3F07FF0FU +#define LPDDR4__DENALI_PHY_615_WRITE_MASK 0x3F07FF0FU +#define LPDDR4__DENALI_PHY_615__PHY_SW_MASTER_MODE_2_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_615__PHY_SW_MASTER_MODE_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_615__PHY_SW_MASTER_MODE_2_WIDTH 4U +#define LPDDR4__PHY_SW_MASTER_MODE_2__REG DENALI_PHY_615 +#define LPDDR4__PHY_SW_MASTER_MODE_2__FLD LPDDR4__DENALI_PHY_615__PHY_SW_MASTER_MODE_2 + +#define LPDDR4__DENALI_PHY_615__PHY_MASTER_DELAY_START_2_MASK 0x0007FF00U +#define LPDDR4__DENALI_PHY_615__PHY_MASTER_DELAY_START_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_615__PHY_MASTER_DELAY_START_2_WIDTH 11U +#define LPDDR4__PHY_MASTER_DELAY_START_2__REG DENALI_PHY_615 +#define LPDDR4__PHY_MASTER_DELAY_START_2__FLD LPDDR4__DENALI_PHY_615__PHY_MASTER_DELAY_START_2 + +#define LPDDR4__DENALI_PHY_615__PHY_MASTER_DELAY_STEP_2_MASK 0x3F000000U +#define LPDDR4__DENALI_PHY_615__PHY_MASTER_DELAY_STEP_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_615__PHY_MASTER_DELAY_STEP_2_WIDTH 6U +#define LPDDR4__PHY_MASTER_DELAY_STEP_2__REG DENALI_PHY_615 +#define LPDDR4__PHY_MASTER_DELAY_STEP_2__FLD LPDDR4__DENALI_PHY_615__PHY_MASTER_DELAY_STEP_2 + +#define LPDDR4__DENALI_PHY_616_READ_MASK 0xFF0FFFFFU +#define LPDDR4__DENALI_PHY_616_WRITE_MASK 0xFF0FFFFFU +#define LPDDR4__DENALI_PHY_616__PHY_MASTER_DELAY_WAIT_2_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_616__PHY_MASTER_DELAY_WAIT_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_616__PHY_MASTER_DELAY_WAIT_2_WIDTH 8U +#define LPDDR4__PHY_MASTER_DELAY_WAIT_2__REG DENALI_PHY_616 +#define LPDDR4__PHY_MASTER_DELAY_WAIT_2__FLD LPDDR4__DENALI_PHY_616__PHY_MASTER_DELAY_WAIT_2 + +#define LPDDR4__DENALI_PHY_616__PHY_MASTER_DELAY_HALF_MEASURE_2_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_616__PHY_MASTER_DELAY_HALF_MEASURE_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_616__PHY_MASTER_DELAY_HALF_MEASURE_2_WIDTH 8U +#define LPDDR4__PHY_MASTER_DELAY_HALF_MEASURE_2__REG DENALI_PHY_616 +#define LPDDR4__PHY_MASTER_DELAY_HALF_MEASURE_2__FLD LPDDR4__DENALI_PHY_616__PHY_MASTER_DELAY_HALF_MEASURE_2 + +#define LPDDR4__DENALI_PHY_616__PHY_RPTR_UPDATE_2_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_616__PHY_RPTR_UPDATE_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_616__PHY_RPTR_UPDATE_2_WIDTH 4U +#define LPDDR4__PHY_RPTR_UPDATE_2__REG DENALI_PHY_616 +#define LPDDR4__PHY_RPTR_UPDATE_2__FLD LPDDR4__DENALI_PHY_616__PHY_RPTR_UPDATE_2 + +#define LPDDR4__DENALI_PHY_616__PHY_WRLVL_DLY_STEP_2_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_616__PHY_WRLVL_DLY_STEP_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_616__PHY_WRLVL_DLY_STEP_2_WIDTH 8U +#define LPDDR4__PHY_WRLVL_DLY_STEP_2__REG DENALI_PHY_616 +#define LPDDR4__PHY_WRLVL_DLY_STEP_2__FLD LPDDR4__DENALI_PHY_616__PHY_WRLVL_DLY_STEP_2 + +#define LPDDR4__DENALI_PHY_617_READ_MASK 0x1F0F3F0FU +#define LPDDR4__DENALI_PHY_617_WRITE_MASK 0x1F0F3F0FU +#define LPDDR4__DENALI_PHY_617__PHY_WRLVL_DLY_FINE_STEP_2_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_617__PHY_WRLVL_DLY_FINE_STEP_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_617__PHY_WRLVL_DLY_FINE_STEP_2_WIDTH 4U +#define LPDDR4__PHY_WRLVL_DLY_FINE_STEP_2__REG DENALI_PHY_617 +#define LPDDR4__PHY_WRLVL_DLY_FINE_STEP_2__FLD LPDDR4__DENALI_PHY_617__PHY_WRLVL_DLY_FINE_STEP_2 + +#define LPDDR4__DENALI_PHY_617__PHY_WRLVL_RESP_WAIT_CNT_2_MASK 0x00003F00U +#define LPDDR4__DENALI_PHY_617__PHY_WRLVL_RESP_WAIT_CNT_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_617__PHY_WRLVL_RESP_WAIT_CNT_2_WIDTH 6U +#define LPDDR4__PHY_WRLVL_RESP_WAIT_CNT_2__REG DENALI_PHY_617 +#define LPDDR4__PHY_WRLVL_RESP_WAIT_CNT_2__FLD LPDDR4__DENALI_PHY_617__PHY_WRLVL_RESP_WAIT_CNT_2 + +#define LPDDR4__DENALI_PHY_617__PHY_GTLVL_DLY_STEP_2_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_617__PHY_GTLVL_DLY_STEP_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_617__PHY_GTLVL_DLY_STEP_2_WIDTH 4U +#define LPDDR4__PHY_GTLVL_DLY_STEP_2__REG DENALI_PHY_617 +#define LPDDR4__PHY_GTLVL_DLY_STEP_2__FLD LPDDR4__DENALI_PHY_617__PHY_GTLVL_DLY_STEP_2 + +#define LPDDR4__DENALI_PHY_617__PHY_GTLVL_RESP_WAIT_CNT_2_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_617__PHY_GTLVL_RESP_WAIT_CNT_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_617__PHY_GTLVL_RESP_WAIT_CNT_2_WIDTH 5U +#define LPDDR4__PHY_GTLVL_RESP_WAIT_CNT_2__REG DENALI_PHY_617 +#define LPDDR4__PHY_GTLVL_RESP_WAIT_CNT_2__FLD LPDDR4__DENALI_PHY_617__PHY_GTLVL_RESP_WAIT_CNT_2 + +#define LPDDR4__DENALI_PHY_618_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_618_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_618__PHY_GTLVL_BACK_STEP_2_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_618__PHY_GTLVL_BACK_STEP_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_618__PHY_GTLVL_BACK_STEP_2_WIDTH 10U +#define LPDDR4__PHY_GTLVL_BACK_STEP_2__REG DENALI_PHY_618 +#define LPDDR4__PHY_GTLVL_BACK_STEP_2__FLD LPDDR4__DENALI_PHY_618__PHY_GTLVL_BACK_STEP_2 + +#define LPDDR4__DENALI_PHY_618__PHY_GTLVL_FINAL_STEP_2_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_618__PHY_GTLVL_FINAL_STEP_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_618__PHY_GTLVL_FINAL_STEP_2_WIDTH 10U +#define LPDDR4__PHY_GTLVL_FINAL_STEP_2__REG DENALI_PHY_618 +#define LPDDR4__PHY_GTLVL_FINAL_STEP_2__FLD LPDDR4__DENALI_PHY_618__PHY_GTLVL_FINAL_STEP_2 + +#define LPDDR4__DENALI_PHY_619_READ_MASK 0x0F010FFFU +#define LPDDR4__DENALI_PHY_619_WRITE_MASK 0x0F010FFFU +#define LPDDR4__DENALI_PHY_619__PHY_WDQLVL_DLY_STEP_2_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_619__PHY_WDQLVL_DLY_STEP_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_619__PHY_WDQLVL_DLY_STEP_2_WIDTH 8U +#define LPDDR4__PHY_WDQLVL_DLY_STEP_2__REG DENALI_PHY_619 +#define LPDDR4__PHY_WDQLVL_DLY_STEP_2__FLD LPDDR4__DENALI_PHY_619__PHY_WDQLVL_DLY_STEP_2 + +#define LPDDR4__DENALI_PHY_619__PHY_WDQLVL_QTR_DLY_STEP_2_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_619__PHY_WDQLVL_QTR_DLY_STEP_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_619__PHY_WDQLVL_QTR_DLY_STEP_2_WIDTH 4U +#define LPDDR4__PHY_WDQLVL_QTR_DLY_STEP_2__REG DENALI_PHY_619 +#define LPDDR4__PHY_WDQLVL_QTR_DLY_STEP_2__FLD LPDDR4__DENALI_PHY_619__PHY_WDQLVL_QTR_DLY_STEP_2 + +#define LPDDR4__DENALI_PHY_619__PHY_TOGGLE_PRE_SUPPORT_2_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_619__PHY_TOGGLE_PRE_SUPPORT_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_619__PHY_TOGGLE_PRE_SUPPORT_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_619__PHY_TOGGLE_PRE_SUPPORT_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_619__PHY_TOGGLE_PRE_SUPPORT_2_WOSET 0U +#define LPDDR4__PHY_TOGGLE_PRE_SUPPORT_2__REG DENALI_PHY_619 +#define LPDDR4__PHY_TOGGLE_PRE_SUPPORT_2__FLD LPDDR4__DENALI_PHY_619__PHY_TOGGLE_PRE_SUPPORT_2 + +#define LPDDR4__DENALI_PHY_619__PHY_RDLVL_DLY_STEP_2_MASK 0x0F000000U +#define LPDDR4__DENALI_PHY_619__PHY_RDLVL_DLY_STEP_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_619__PHY_RDLVL_DLY_STEP_2_WIDTH 4U +#define LPDDR4__PHY_RDLVL_DLY_STEP_2__REG DENALI_PHY_619 +#define LPDDR4__PHY_RDLVL_DLY_STEP_2__FLD LPDDR4__DENALI_PHY_619__PHY_RDLVL_DLY_STEP_2 + +#define LPDDR4__DENALI_PHY_620_READ_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_620_WRITE_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_620__PHY_RDLVL_MAX_EDGE_2_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_620__PHY_RDLVL_MAX_EDGE_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_620__PHY_RDLVL_MAX_EDGE_2_WIDTH 10U +#define LPDDR4__PHY_RDLVL_MAX_EDGE_2__REG DENALI_PHY_620 +#define LPDDR4__PHY_RDLVL_MAX_EDGE_2__FLD LPDDR4__DENALI_PHY_620__PHY_RDLVL_MAX_EDGE_2 + +#define LPDDR4__DENALI_PHY_621_READ_MASK 0x3F0103FFU +#define LPDDR4__DENALI_PHY_621_WRITE_MASK 0x3F0103FFU +#define LPDDR4__DENALI_PHY_621__PHY_RDLVL_DVW_MIN_2_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_621__PHY_RDLVL_DVW_MIN_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_621__PHY_RDLVL_DVW_MIN_2_WIDTH 10U +#define LPDDR4__PHY_RDLVL_DVW_MIN_2__REG DENALI_PHY_621 +#define LPDDR4__PHY_RDLVL_DVW_MIN_2__FLD LPDDR4__DENALI_PHY_621__PHY_RDLVL_DVW_MIN_2 + +#define LPDDR4__DENALI_PHY_621__PHY_SW_RDLVL_DVW_MIN_EN_2_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_621__PHY_SW_RDLVL_DVW_MIN_EN_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_621__PHY_SW_RDLVL_DVW_MIN_EN_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_621__PHY_SW_RDLVL_DVW_MIN_EN_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_621__PHY_SW_RDLVL_DVW_MIN_EN_2_WOSET 0U +#define LPDDR4__PHY_SW_RDLVL_DVW_MIN_EN_2__REG DENALI_PHY_621 +#define LPDDR4__PHY_SW_RDLVL_DVW_MIN_EN_2__FLD LPDDR4__DENALI_PHY_621__PHY_SW_RDLVL_DVW_MIN_EN_2 + +#define LPDDR4__DENALI_PHY_621__PHY_RDLVL_PER_START_OFFSET_2_MASK 0x3F000000U +#define LPDDR4__DENALI_PHY_621__PHY_RDLVL_PER_START_OFFSET_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_621__PHY_RDLVL_PER_START_OFFSET_2_WIDTH 6U +#define LPDDR4__PHY_RDLVL_PER_START_OFFSET_2__REG DENALI_PHY_621 +#define LPDDR4__PHY_RDLVL_PER_START_OFFSET_2__FLD LPDDR4__DENALI_PHY_621__PHY_RDLVL_PER_START_OFFSET_2 + +#define LPDDR4__DENALI_PHY_622_READ_MASK 0x00030703U +#define LPDDR4__DENALI_PHY_622_WRITE_MASK 0x00030703U +#define LPDDR4__DENALI_PHY_622__PHY_WRPATH_GATE_DISABLE_2_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_622__PHY_WRPATH_GATE_DISABLE_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_622__PHY_WRPATH_GATE_DISABLE_2_WIDTH 2U +#define LPDDR4__PHY_WRPATH_GATE_DISABLE_2__REG DENALI_PHY_622 +#define LPDDR4__PHY_WRPATH_GATE_DISABLE_2__FLD LPDDR4__DENALI_PHY_622__PHY_WRPATH_GATE_DISABLE_2 + +#define LPDDR4__DENALI_PHY_622__PHY_WRPATH_GATE_TIMING_2_MASK 0x00000700U +#define LPDDR4__DENALI_PHY_622__PHY_WRPATH_GATE_TIMING_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_622__PHY_WRPATH_GATE_TIMING_2_WIDTH 3U +#define LPDDR4__PHY_WRPATH_GATE_TIMING_2__REG DENALI_PHY_622 +#define LPDDR4__PHY_WRPATH_GATE_TIMING_2__FLD LPDDR4__DENALI_PHY_622__PHY_WRPATH_GATE_TIMING_2 + +#define LPDDR4__DENALI_PHY_622__PHY_DATA_DC_INIT_DISABLE_2_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_622__PHY_DATA_DC_INIT_DISABLE_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_622__PHY_DATA_DC_INIT_DISABLE_2_WIDTH 2U +#define LPDDR4__PHY_DATA_DC_INIT_DISABLE_2__REG DENALI_PHY_622 +#define LPDDR4__PHY_DATA_DC_INIT_DISABLE_2__FLD LPDDR4__DENALI_PHY_622__PHY_DATA_DC_INIT_DISABLE_2 + +#define LPDDR4__DENALI_PHY_623_READ_MASK 0x07FF03FFU +#define LPDDR4__DENALI_PHY_623_WRITE_MASK 0x07FF03FFU +#define LPDDR4__DENALI_PHY_623__PHY_DATA_DC_DQS_INIT_SLV_DELAY_2_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_623__PHY_DATA_DC_DQS_INIT_SLV_DELAY_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_623__PHY_DATA_DC_DQS_INIT_SLV_DELAY_2_WIDTH 10U +#define LPDDR4__PHY_DATA_DC_DQS_INIT_SLV_DELAY_2__REG DENALI_PHY_623 +#define LPDDR4__PHY_DATA_DC_DQS_INIT_SLV_DELAY_2__FLD LPDDR4__DENALI_PHY_623__PHY_DATA_DC_DQS_INIT_SLV_DELAY_2 + +#define LPDDR4__DENALI_PHY_623__PHY_DATA_DC_DQ_INIT_SLV_DELAY_2_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_623__PHY_DATA_DC_DQ_INIT_SLV_DELAY_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_623__PHY_DATA_DC_DQ_INIT_SLV_DELAY_2_WIDTH 11U +#define LPDDR4__PHY_DATA_DC_DQ_INIT_SLV_DELAY_2__REG DENALI_PHY_623 +#define LPDDR4__PHY_DATA_DC_DQ_INIT_SLV_DELAY_2__FLD LPDDR4__DENALI_PHY_623__PHY_DATA_DC_DQ_INIT_SLV_DELAY_2 + +#define LPDDR4__DENALI_PHY_624_READ_MASK 0xFFFF0101U +#define LPDDR4__DENALI_PHY_624_WRITE_MASK 0xFFFF0101U +#define LPDDR4__DENALI_PHY_624__PHY_DATA_DC_WRLVL_ENABLE_2_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_624__PHY_DATA_DC_WRLVL_ENABLE_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_624__PHY_DATA_DC_WRLVL_ENABLE_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_624__PHY_DATA_DC_WRLVL_ENABLE_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_624__PHY_DATA_DC_WRLVL_ENABLE_2_WOSET 0U +#define LPDDR4__PHY_DATA_DC_WRLVL_ENABLE_2__REG DENALI_PHY_624 +#define LPDDR4__PHY_DATA_DC_WRLVL_ENABLE_2__FLD LPDDR4__DENALI_PHY_624__PHY_DATA_DC_WRLVL_ENABLE_2 + +#define LPDDR4__DENALI_PHY_624__PHY_DATA_DC_WDQLVL_ENABLE_2_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_624__PHY_DATA_DC_WDQLVL_ENABLE_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_624__PHY_DATA_DC_WDQLVL_ENABLE_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_624__PHY_DATA_DC_WDQLVL_ENABLE_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_624__PHY_DATA_DC_WDQLVL_ENABLE_2_WOSET 0U +#define LPDDR4__PHY_DATA_DC_WDQLVL_ENABLE_2__REG DENALI_PHY_624 +#define LPDDR4__PHY_DATA_DC_WDQLVL_ENABLE_2__FLD LPDDR4__DENALI_PHY_624__PHY_DATA_DC_WDQLVL_ENABLE_2 + +#define LPDDR4__DENALI_PHY_624__PHY_DATA_DC_DM_CLK_SE_THRSHLD_2_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_624__PHY_DATA_DC_DM_CLK_SE_THRSHLD_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_624__PHY_DATA_DC_DM_CLK_SE_THRSHLD_2_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DM_CLK_SE_THRSHLD_2__REG DENALI_PHY_624 +#define LPDDR4__PHY_DATA_DC_DM_CLK_SE_THRSHLD_2__FLD LPDDR4__DENALI_PHY_624__PHY_DATA_DC_DM_CLK_SE_THRSHLD_2 + +#define LPDDR4__DENALI_PHY_624__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_2_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_624__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_624__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_2_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_2__REG DENALI_PHY_624 +#define LPDDR4__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_2__FLD LPDDR4__DENALI_PHY_624__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_2 + +#define LPDDR4__DENALI_PHY_625_READ_MASK 0x001F3F7FU +#define LPDDR4__DENALI_PHY_625_WRITE_MASK 0x001F3F7FU +#define LPDDR4__DENALI_PHY_625__PHY_WDQ_OSC_DELTA_2_MASK 0x0000007FU +#define LPDDR4__DENALI_PHY_625__PHY_WDQ_OSC_DELTA_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_625__PHY_WDQ_OSC_DELTA_2_WIDTH 7U +#define LPDDR4__PHY_WDQ_OSC_DELTA_2__REG DENALI_PHY_625 +#define LPDDR4__PHY_WDQ_OSC_DELTA_2__FLD LPDDR4__DENALI_PHY_625__PHY_WDQ_OSC_DELTA_2 + +#define LPDDR4__DENALI_PHY_625__PHY_MEAS_DLY_STEP_ENABLE_2_MASK 0x00003F00U +#define LPDDR4__DENALI_PHY_625__PHY_MEAS_DLY_STEP_ENABLE_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_625__PHY_MEAS_DLY_STEP_ENABLE_2_WIDTH 6U +#define LPDDR4__PHY_MEAS_DLY_STEP_ENABLE_2__REG DENALI_PHY_625 +#define LPDDR4__PHY_MEAS_DLY_STEP_ENABLE_2__FLD LPDDR4__DENALI_PHY_625__PHY_MEAS_DLY_STEP_ENABLE_2 + +#define LPDDR4__DENALI_PHY_625__PHY_RDDATA_EN_DLY_2_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_625__PHY_RDDATA_EN_DLY_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_625__PHY_RDDATA_EN_DLY_2_WIDTH 5U +#define LPDDR4__PHY_RDDATA_EN_DLY_2__REG DENALI_PHY_625 +#define LPDDR4__PHY_RDDATA_EN_DLY_2__FLD LPDDR4__DENALI_PHY_625__PHY_RDDATA_EN_DLY_2 + +#define LPDDR4__DENALI_PHY_626_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_626_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_626__PHY_DQ_DM_SWIZZLE0_2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_626__PHY_DQ_DM_SWIZZLE0_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_626__PHY_DQ_DM_SWIZZLE0_2_WIDTH 32U +#define LPDDR4__PHY_DQ_DM_SWIZZLE0_2__REG DENALI_PHY_626 +#define LPDDR4__PHY_DQ_DM_SWIZZLE0_2__FLD LPDDR4__DENALI_PHY_626__PHY_DQ_DM_SWIZZLE0_2 + +#define LPDDR4__DENALI_PHY_627_READ_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_627_WRITE_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_627__PHY_DQ_DM_SWIZZLE1_2_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_627__PHY_DQ_DM_SWIZZLE1_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_627__PHY_DQ_DM_SWIZZLE1_2_WIDTH 4U +#define LPDDR4__PHY_DQ_DM_SWIZZLE1_2__REG DENALI_PHY_627 +#define LPDDR4__PHY_DQ_DM_SWIZZLE1_2__FLD LPDDR4__DENALI_PHY_627__PHY_DQ_DM_SWIZZLE1_2 + +#define LPDDR4__DENALI_PHY_628_READ_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_628_WRITE_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_628__PHY_CLK_WRDQ0_SLAVE_DELAY_2_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_628__PHY_CLK_WRDQ0_SLAVE_DELAY_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_628__PHY_CLK_WRDQ0_SLAVE_DELAY_2_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDQ0_SLAVE_DELAY_2__REG DENALI_PHY_628 +#define LPDDR4__PHY_CLK_WRDQ0_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_628__PHY_CLK_WRDQ0_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_628__PHY_CLK_WRDQ1_SLAVE_DELAY_2_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_628__PHY_CLK_WRDQ1_SLAVE_DELAY_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_628__PHY_CLK_WRDQ1_SLAVE_DELAY_2_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDQ1_SLAVE_DELAY_2__REG DENALI_PHY_628 +#define LPDDR4__PHY_CLK_WRDQ1_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_628__PHY_CLK_WRDQ1_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_629_READ_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_629_WRITE_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_629__PHY_CLK_WRDQ2_SLAVE_DELAY_2_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_629__PHY_CLK_WRDQ2_SLAVE_DELAY_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_629__PHY_CLK_WRDQ2_SLAVE_DELAY_2_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDQ2_SLAVE_DELAY_2__REG DENALI_PHY_629 +#define LPDDR4__PHY_CLK_WRDQ2_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_629__PHY_CLK_WRDQ2_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_629__PHY_CLK_WRDQ3_SLAVE_DELAY_2_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_629__PHY_CLK_WRDQ3_SLAVE_DELAY_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_629__PHY_CLK_WRDQ3_SLAVE_DELAY_2_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDQ3_SLAVE_DELAY_2__REG DENALI_PHY_629 +#define LPDDR4__PHY_CLK_WRDQ3_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_629__PHY_CLK_WRDQ3_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_630_READ_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_630_WRITE_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_630__PHY_CLK_WRDQ4_SLAVE_DELAY_2_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_630__PHY_CLK_WRDQ4_SLAVE_DELAY_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_630__PHY_CLK_WRDQ4_SLAVE_DELAY_2_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDQ4_SLAVE_DELAY_2__REG DENALI_PHY_630 +#define LPDDR4__PHY_CLK_WRDQ4_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_630__PHY_CLK_WRDQ4_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_630__PHY_CLK_WRDQ5_SLAVE_DELAY_2_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_630__PHY_CLK_WRDQ5_SLAVE_DELAY_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_630__PHY_CLK_WRDQ5_SLAVE_DELAY_2_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDQ5_SLAVE_DELAY_2__REG DENALI_PHY_630 +#define LPDDR4__PHY_CLK_WRDQ5_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_630__PHY_CLK_WRDQ5_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_631_READ_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_631_WRITE_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_631__PHY_CLK_WRDQ6_SLAVE_DELAY_2_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_631__PHY_CLK_WRDQ6_SLAVE_DELAY_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_631__PHY_CLK_WRDQ6_SLAVE_DELAY_2_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDQ6_SLAVE_DELAY_2__REG DENALI_PHY_631 +#define LPDDR4__PHY_CLK_WRDQ6_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_631__PHY_CLK_WRDQ6_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_631__PHY_CLK_WRDQ7_SLAVE_DELAY_2_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_631__PHY_CLK_WRDQ7_SLAVE_DELAY_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_631__PHY_CLK_WRDQ7_SLAVE_DELAY_2_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDQ7_SLAVE_DELAY_2__REG DENALI_PHY_631 +#define LPDDR4__PHY_CLK_WRDQ7_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_631__PHY_CLK_WRDQ7_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_632_READ_MASK 0x03FF07FFU +#define LPDDR4__DENALI_PHY_632_WRITE_MASK 0x03FF07FFU +#define LPDDR4__DENALI_PHY_632__PHY_CLK_WRDM_SLAVE_DELAY_2_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_632__PHY_CLK_WRDM_SLAVE_DELAY_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_632__PHY_CLK_WRDM_SLAVE_DELAY_2_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDM_SLAVE_DELAY_2__REG DENALI_PHY_632 +#define LPDDR4__PHY_CLK_WRDM_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_632__PHY_CLK_WRDM_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_632__PHY_CLK_WRDQS_SLAVE_DELAY_2_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_632__PHY_CLK_WRDQS_SLAVE_DELAY_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_632__PHY_CLK_WRDQS_SLAVE_DELAY_2_WIDTH 10U +#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_2__REG DENALI_PHY_632 +#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_632__PHY_CLK_WRDQS_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_633_READ_MASK 0x0003FF03U +#define LPDDR4__DENALI_PHY_633_WRITE_MASK 0x0003FF03U +#define LPDDR4__DENALI_PHY_633__PHY_WRLVL_THRESHOLD_ADJUST_2_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_633__PHY_WRLVL_THRESHOLD_ADJUST_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_633__PHY_WRLVL_THRESHOLD_ADJUST_2_WIDTH 2U +#define LPDDR4__PHY_WRLVL_THRESHOLD_ADJUST_2__REG DENALI_PHY_633 +#define LPDDR4__PHY_WRLVL_THRESHOLD_ADJUST_2__FLD LPDDR4__DENALI_PHY_633__PHY_WRLVL_THRESHOLD_ADJUST_2 + +#define LPDDR4__DENALI_PHY_633__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_2_MASK 0x0003FF00U +#define LPDDR4__DENALI_PHY_633__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_633__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_2_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_2__REG DENALI_PHY_633 +#define LPDDR4__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_633__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_634_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_634_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_634__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_2_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_634__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_634__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_2_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_2__REG DENALI_PHY_634 +#define LPDDR4__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_634__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_634__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_2_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_634__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_634__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_2_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_2__REG DENALI_PHY_634 +#define LPDDR4__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_634__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_635_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_635_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_635__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_2_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_635__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_635__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_2_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_2__REG DENALI_PHY_635 +#define LPDDR4__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_635__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_635__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_2_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_635__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_635__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_2_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_2__REG DENALI_PHY_635 +#define LPDDR4__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_635__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_636_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_636_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_636__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_2_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_636__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_636__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_2_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_2__REG DENALI_PHY_636 +#define LPDDR4__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_636__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_636__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_2_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_636__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_636__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_2_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_2__REG DENALI_PHY_636 +#define LPDDR4__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_636__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_637_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_637_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_637__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_2_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_637__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_637__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_2_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_2__REG DENALI_PHY_637 +#define LPDDR4__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_637__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_637__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_2_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_637__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_637__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_2_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_2__REG DENALI_PHY_637 +#define LPDDR4__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_637__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_638_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_638_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_638__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_2_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_638__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_638__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_2_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_2__REG DENALI_PHY_638 +#define LPDDR4__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_638__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_638__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_2_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_638__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_638__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_2_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_2__REG DENALI_PHY_638 +#define LPDDR4__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_638__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_639_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_639_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_639__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_2_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_639__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_639__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_2_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_2__REG DENALI_PHY_639 +#define LPDDR4__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_639__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_639__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_2_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_639__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_639__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_2_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_2__REG DENALI_PHY_639 +#define LPDDR4__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_639__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_640_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_640_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_640__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_2_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_640__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_640__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_2_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_2__REG DENALI_PHY_640 +#define LPDDR4__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_640__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_640__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_2_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_640__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_640__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_2_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_2__REG DENALI_PHY_640 +#define LPDDR4__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_640__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_641_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_641_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_641__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_2_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_641__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_641__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_2_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_2__REG DENALI_PHY_641 +#define LPDDR4__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_641__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_641__PHY_RDDQS_DM_RISE_SLAVE_DELAY_2_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_641__PHY_RDDQS_DM_RISE_SLAVE_DELAY_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_641__PHY_RDDQS_DM_RISE_SLAVE_DELAY_2_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DM_RISE_SLAVE_DELAY_2__REG DENALI_PHY_641 +#define LPDDR4__PHY_RDDQS_DM_RISE_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_641__PHY_RDDQS_DM_RISE_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_642_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_642_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_642__PHY_RDDQS_DM_FALL_SLAVE_DELAY_2_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_642__PHY_RDDQS_DM_FALL_SLAVE_DELAY_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_642__PHY_RDDQS_DM_FALL_SLAVE_DELAY_2_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DM_FALL_SLAVE_DELAY_2__REG DENALI_PHY_642 +#define LPDDR4__PHY_RDDQS_DM_FALL_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_642__PHY_RDDQS_DM_FALL_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_642__PHY_RDDQS_GATE_SLAVE_DELAY_2_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_642__PHY_RDDQS_GATE_SLAVE_DELAY_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_642__PHY_RDDQS_GATE_SLAVE_DELAY_2_WIDTH 10U +#define LPDDR4__PHY_RDDQS_GATE_SLAVE_DELAY_2__REG DENALI_PHY_642 +#define LPDDR4__PHY_RDDQS_GATE_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_642__PHY_RDDQS_GATE_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_643_READ_MASK 0x03FF070FU +#define LPDDR4__DENALI_PHY_643_WRITE_MASK 0x03FF070FU +#define LPDDR4__DENALI_PHY_643__PHY_RDDQS_LATENCY_ADJUST_2_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_643__PHY_RDDQS_LATENCY_ADJUST_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_643__PHY_RDDQS_LATENCY_ADJUST_2_WIDTH 4U +#define LPDDR4__PHY_RDDQS_LATENCY_ADJUST_2__REG DENALI_PHY_643 +#define LPDDR4__PHY_RDDQS_LATENCY_ADJUST_2__FLD LPDDR4__DENALI_PHY_643__PHY_RDDQS_LATENCY_ADJUST_2 + +#define LPDDR4__DENALI_PHY_643__PHY_WRITE_PATH_LAT_ADD_2_MASK 0x00000700U +#define LPDDR4__DENALI_PHY_643__PHY_WRITE_PATH_LAT_ADD_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_643__PHY_WRITE_PATH_LAT_ADD_2_WIDTH 3U +#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_2__REG DENALI_PHY_643 +#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_2__FLD LPDDR4__DENALI_PHY_643__PHY_WRITE_PATH_LAT_ADD_2 + +#define LPDDR4__DENALI_PHY_643__PHY_WRLVL_DELAY_EARLY_THRESHOLD_2_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_643__PHY_WRLVL_DELAY_EARLY_THRESHOLD_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_643__PHY_WRLVL_DELAY_EARLY_THRESHOLD_2_WIDTH 10U +#define LPDDR4__PHY_WRLVL_DELAY_EARLY_THRESHOLD_2__REG DENALI_PHY_643 +#define LPDDR4__PHY_WRLVL_DELAY_EARLY_THRESHOLD_2__FLD LPDDR4__DENALI_PHY_643__PHY_WRLVL_DELAY_EARLY_THRESHOLD_2 + +#define LPDDR4__DENALI_PHY_644_READ_MASK 0x000103FFU +#define LPDDR4__DENALI_PHY_644_WRITE_MASK 0x000103FFU +#define LPDDR4__DENALI_PHY_644__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_644__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_644__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2_WIDTH 10U +#define LPDDR4__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2__REG DENALI_PHY_644 +#define LPDDR4__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2__FLD LPDDR4__DENALI_PHY_644__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2 + +#define LPDDR4__DENALI_PHY_644__PHY_WRLVL_EARLY_FORCE_ZERO_2_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_644__PHY_WRLVL_EARLY_FORCE_ZERO_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_644__PHY_WRLVL_EARLY_FORCE_ZERO_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_644__PHY_WRLVL_EARLY_FORCE_ZERO_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_644__PHY_WRLVL_EARLY_FORCE_ZERO_2_WOSET 0U +#define LPDDR4__PHY_WRLVL_EARLY_FORCE_ZERO_2__REG DENALI_PHY_644 +#define LPDDR4__PHY_WRLVL_EARLY_FORCE_ZERO_2__FLD LPDDR4__DENALI_PHY_644__PHY_WRLVL_EARLY_FORCE_ZERO_2 + +#define LPDDR4__DENALI_PHY_645_READ_MASK 0x000F03FFU +#define LPDDR4__DENALI_PHY_645_WRITE_MASK 0x000F03FFU +#define LPDDR4__DENALI_PHY_645__PHY_GTLVL_RDDQS_SLV_DLY_START_2_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_645__PHY_GTLVL_RDDQS_SLV_DLY_START_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_645__PHY_GTLVL_RDDQS_SLV_DLY_START_2_WIDTH 10U +#define LPDDR4__PHY_GTLVL_RDDQS_SLV_DLY_START_2__REG DENALI_PHY_645 +#define LPDDR4__PHY_GTLVL_RDDQS_SLV_DLY_START_2__FLD LPDDR4__DENALI_PHY_645__PHY_GTLVL_RDDQS_SLV_DLY_START_2 + +#define LPDDR4__DENALI_PHY_645__PHY_GTLVL_LAT_ADJ_START_2_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_645__PHY_GTLVL_LAT_ADJ_START_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_645__PHY_GTLVL_LAT_ADJ_START_2_WIDTH 4U +#define LPDDR4__PHY_GTLVL_LAT_ADJ_START_2__REG DENALI_PHY_645 +#define LPDDR4__PHY_GTLVL_LAT_ADJ_START_2__FLD LPDDR4__DENALI_PHY_645__PHY_GTLVL_LAT_ADJ_START_2 + +#define LPDDR4__DENALI_PHY_646_READ_MASK 0x010F07FFU +#define LPDDR4__DENALI_PHY_646_WRITE_MASK 0x010F07FFU +#define LPDDR4__DENALI_PHY_646__PHY_WDQLVL_DQDM_SLV_DLY_START_2_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_646__PHY_WDQLVL_DQDM_SLV_DLY_START_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_646__PHY_WDQLVL_DQDM_SLV_DLY_START_2_WIDTH 11U +#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_START_2__REG DENALI_PHY_646 +#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_START_2__FLD LPDDR4__DENALI_PHY_646__PHY_WDQLVL_DQDM_SLV_DLY_START_2 + +#define LPDDR4__DENALI_PHY_646__PHY_NTP_WRLAT_START_2_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_646__PHY_NTP_WRLAT_START_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_646__PHY_NTP_WRLAT_START_2_WIDTH 4U +#define LPDDR4__PHY_NTP_WRLAT_START_2__REG DENALI_PHY_646 +#define LPDDR4__PHY_NTP_WRLAT_START_2__FLD LPDDR4__DENALI_PHY_646__PHY_NTP_WRLAT_START_2 + +#define LPDDR4__DENALI_PHY_646__PHY_NTP_PASS_2_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_646__PHY_NTP_PASS_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_646__PHY_NTP_PASS_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_646__PHY_NTP_PASS_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_646__PHY_NTP_PASS_2_WOSET 0U +#define LPDDR4__PHY_NTP_PASS_2__REG DENALI_PHY_646 +#define LPDDR4__PHY_NTP_PASS_2__FLD LPDDR4__DENALI_PHY_646__PHY_NTP_PASS_2 + +#define LPDDR4__DENALI_PHY_647_READ_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_647_WRITE_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_647__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_2_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_647__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_647__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_2_WIDTH 10U +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_2__REG DENALI_PHY_647 +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_2__FLD LPDDR4__DENALI_PHY_647__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_2 + +#define LPDDR4__DENALI_PHY_648_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_648_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_648__PHY_DATA_DC_DQS_CLK_ADJUST_2_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_648__PHY_DATA_DC_DQS_CLK_ADJUST_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_648__PHY_DATA_DC_DQS_CLK_ADJUST_2_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DQS_CLK_ADJUST_2__REG DENALI_PHY_648 +#define LPDDR4__PHY_DATA_DC_DQS_CLK_ADJUST_2__FLD LPDDR4__DENALI_PHY_648__PHY_DATA_DC_DQS_CLK_ADJUST_2 + +#define LPDDR4__DENALI_PHY_648__PHY_DATA_DC_DQ0_CLK_ADJUST_2_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_648__PHY_DATA_DC_DQ0_CLK_ADJUST_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_648__PHY_DATA_DC_DQ0_CLK_ADJUST_2_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DQ0_CLK_ADJUST_2__REG DENALI_PHY_648 +#define LPDDR4__PHY_DATA_DC_DQ0_CLK_ADJUST_2__FLD LPDDR4__DENALI_PHY_648__PHY_DATA_DC_DQ0_CLK_ADJUST_2 + +#define LPDDR4__DENALI_PHY_648__PHY_DATA_DC_DQ1_CLK_ADJUST_2_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_648__PHY_DATA_DC_DQ1_CLK_ADJUST_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_648__PHY_DATA_DC_DQ1_CLK_ADJUST_2_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DQ1_CLK_ADJUST_2__REG DENALI_PHY_648 +#define LPDDR4__PHY_DATA_DC_DQ1_CLK_ADJUST_2__FLD LPDDR4__DENALI_PHY_648__PHY_DATA_DC_DQ1_CLK_ADJUST_2 + +#define LPDDR4__DENALI_PHY_648__PHY_DATA_DC_DQ2_CLK_ADJUST_2_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_648__PHY_DATA_DC_DQ2_CLK_ADJUST_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_648__PHY_DATA_DC_DQ2_CLK_ADJUST_2_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DQ2_CLK_ADJUST_2__REG DENALI_PHY_648 +#define LPDDR4__PHY_DATA_DC_DQ2_CLK_ADJUST_2__FLD LPDDR4__DENALI_PHY_648__PHY_DATA_DC_DQ2_CLK_ADJUST_2 + +#define LPDDR4__DENALI_PHY_649_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_649_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_649__PHY_DATA_DC_DQ3_CLK_ADJUST_2_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_649__PHY_DATA_DC_DQ3_CLK_ADJUST_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_649__PHY_DATA_DC_DQ3_CLK_ADJUST_2_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DQ3_CLK_ADJUST_2__REG DENALI_PHY_649 +#define LPDDR4__PHY_DATA_DC_DQ3_CLK_ADJUST_2__FLD LPDDR4__DENALI_PHY_649__PHY_DATA_DC_DQ3_CLK_ADJUST_2 + +#define LPDDR4__DENALI_PHY_649__PHY_DATA_DC_DQ4_CLK_ADJUST_2_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_649__PHY_DATA_DC_DQ4_CLK_ADJUST_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_649__PHY_DATA_DC_DQ4_CLK_ADJUST_2_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DQ4_CLK_ADJUST_2__REG DENALI_PHY_649 +#define LPDDR4__PHY_DATA_DC_DQ4_CLK_ADJUST_2__FLD LPDDR4__DENALI_PHY_649__PHY_DATA_DC_DQ4_CLK_ADJUST_2 + +#define LPDDR4__DENALI_PHY_649__PHY_DATA_DC_DQ5_CLK_ADJUST_2_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_649__PHY_DATA_DC_DQ5_CLK_ADJUST_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_649__PHY_DATA_DC_DQ5_CLK_ADJUST_2_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DQ5_CLK_ADJUST_2__REG DENALI_PHY_649 +#define LPDDR4__PHY_DATA_DC_DQ5_CLK_ADJUST_2__FLD LPDDR4__DENALI_PHY_649__PHY_DATA_DC_DQ5_CLK_ADJUST_2 + +#define LPDDR4__DENALI_PHY_649__PHY_DATA_DC_DQ6_CLK_ADJUST_2_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_649__PHY_DATA_DC_DQ6_CLK_ADJUST_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_649__PHY_DATA_DC_DQ6_CLK_ADJUST_2_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DQ6_CLK_ADJUST_2__REG DENALI_PHY_649 +#define LPDDR4__PHY_DATA_DC_DQ6_CLK_ADJUST_2__FLD LPDDR4__DENALI_PHY_649__PHY_DATA_DC_DQ6_CLK_ADJUST_2 + +#define LPDDR4__DENALI_PHY_650_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_650_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_650__PHY_DATA_DC_DQ7_CLK_ADJUST_2_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_650__PHY_DATA_DC_DQ7_CLK_ADJUST_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_650__PHY_DATA_DC_DQ7_CLK_ADJUST_2_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DQ7_CLK_ADJUST_2__REG DENALI_PHY_650 +#define LPDDR4__PHY_DATA_DC_DQ7_CLK_ADJUST_2__FLD LPDDR4__DENALI_PHY_650__PHY_DATA_DC_DQ7_CLK_ADJUST_2 + +#define LPDDR4__DENALI_PHY_650__PHY_DATA_DC_DM_CLK_ADJUST_2_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_650__PHY_DATA_DC_DM_CLK_ADJUST_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_650__PHY_DATA_DC_DM_CLK_ADJUST_2_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DM_CLK_ADJUST_2__REG DENALI_PHY_650 +#define LPDDR4__PHY_DATA_DC_DM_CLK_ADJUST_2__FLD LPDDR4__DENALI_PHY_650__PHY_DATA_DC_DM_CLK_ADJUST_2 + +#define LPDDR4__DENALI_PHY_650__PHY_DSLICE_PAD_BOOSTPN_SETTING_2_MASK 0xFFFF0000U +#define LPDDR4__DENALI_PHY_650__PHY_DSLICE_PAD_BOOSTPN_SETTING_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_650__PHY_DSLICE_PAD_BOOSTPN_SETTING_2_WIDTH 16U +#define LPDDR4__PHY_DSLICE_PAD_BOOSTPN_SETTING_2__REG DENALI_PHY_650 +#define LPDDR4__PHY_DSLICE_PAD_BOOSTPN_SETTING_2__FLD LPDDR4__DENALI_PHY_650__PHY_DSLICE_PAD_BOOSTPN_SETTING_2 + +#define LPDDR4__DENALI_PHY_651_READ_MASK 0x0003033FU +#define LPDDR4__DENALI_PHY_651_WRITE_MASK 0x0003033FU +#define LPDDR4__DENALI_PHY_651__PHY_DSLICE_PAD_RX_CTLE_SETTING_2_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_651__PHY_DSLICE_PAD_RX_CTLE_SETTING_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_651__PHY_DSLICE_PAD_RX_CTLE_SETTING_2_WIDTH 6U +#define LPDDR4__PHY_DSLICE_PAD_RX_CTLE_SETTING_2__REG DENALI_PHY_651 +#define LPDDR4__PHY_DSLICE_PAD_RX_CTLE_SETTING_2__FLD LPDDR4__DENALI_PHY_651__PHY_DSLICE_PAD_RX_CTLE_SETTING_2 + +#define LPDDR4__DENALI_PHY_651__PHY_DQ_FFE_2_MASK 0x00000300U +#define LPDDR4__DENALI_PHY_651__PHY_DQ_FFE_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_651__PHY_DQ_FFE_2_WIDTH 2U +#define LPDDR4__PHY_DQ_FFE_2__REG DENALI_PHY_651 +#define LPDDR4__PHY_DQ_FFE_2__FLD LPDDR4__DENALI_PHY_651__PHY_DQ_FFE_2 + +#define LPDDR4__DENALI_PHY_651__PHY_DQS_FFE_2_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_651__PHY_DQS_FFE_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_651__PHY_DQS_FFE_2_WIDTH 2U +#define LPDDR4__PHY_DQS_FFE_2__REG DENALI_PHY_651 +#define LPDDR4__PHY_DQS_FFE_2__FLD LPDDR4__DENALI_PHY_651__PHY_DQS_FFE_2 + +#endif /* REG_LPDDR4_DATA_SLICE_2_MACROS_H_ */ diff --git a/drivers/ram/k3-j721e/lpddr4_data_slice_3_macros.h b/drivers/ram/k3-j721e/lpddr4_data_slice_3_macros.h new file mode 100644 index 0000000..bfde51d --- /dev/null +++ b/drivers/ram/k3-j721e/lpddr4_data_slice_3_macros.h @@ -0,0 +1,2373 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/********************************************************************** + * Copyright (C) 2012-2019 Cadence Design Systems, Inc. + * + * THIS FILE IS AUTOMATICALLY GENERATED, DO NOT EDIT + * + ********************************************************************** + */ + +#ifndef REG_LPDDR4_DATA_SLICE_3_MACROS_H_ +#define REG_LPDDR4_DATA_SLICE_3_MACROS_H_ + +#define LPDDR4__DENALI_PHY_768_READ_MASK 0x000F07FFU +#define LPDDR4__DENALI_PHY_768_WRITE_MASK 0x000F07FFU +#define LPDDR4__DENALI_PHY_768__PHY_CLK_WR_BYPASS_SLAVE_DELAY_3_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_768__PHY_CLK_WR_BYPASS_SLAVE_DELAY_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_768__PHY_CLK_WR_BYPASS_SLAVE_DELAY_3_WIDTH 11U +#define LPDDR4__PHY_CLK_WR_BYPASS_SLAVE_DELAY_3__REG DENALI_PHY_768 +#define LPDDR4__PHY_CLK_WR_BYPASS_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_768__PHY_CLK_WR_BYPASS_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_768__PHY_IO_PAD_DELAY_TIMING_BYPASS_3_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_768__PHY_IO_PAD_DELAY_TIMING_BYPASS_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_768__PHY_IO_PAD_DELAY_TIMING_BYPASS_3_WIDTH 4U +#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_BYPASS_3__REG DENALI_PHY_768 +#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_BYPASS_3__FLD LPDDR4__DENALI_PHY_768__PHY_IO_PAD_DELAY_TIMING_BYPASS_3 + +#define LPDDR4__DENALI_PHY_769_READ_MASK 0x000703FFU +#define LPDDR4__DENALI_PHY_769_WRITE_MASK 0x000703FFU +#define LPDDR4__DENALI_PHY_769__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_3_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_769__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_769__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_3_WIDTH 10U +#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_3__REG DENALI_PHY_769 +#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_3__FLD LPDDR4__DENALI_PHY_769__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_3 + +#define LPDDR4__DENALI_PHY_769__PHY_WRITE_PATH_LAT_ADD_BYPASS_3_MASK 0x00070000U +#define LPDDR4__DENALI_PHY_769__PHY_WRITE_PATH_LAT_ADD_BYPASS_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_769__PHY_WRITE_PATH_LAT_ADD_BYPASS_3_WIDTH 3U +#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_BYPASS_3__REG DENALI_PHY_769 +#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_BYPASS_3__FLD LPDDR4__DENALI_PHY_769__PHY_WRITE_PATH_LAT_ADD_BYPASS_3 + +#define LPDDR4__DENALI_PHY_770_READ_MASK 0x010303FFU +#define LPDDR4__DENALI_PHY_770_WRITE_MASK 0x010303FFU +#define LPDDR4__DENALI_PHY_770__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_3_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_770__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_770__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_3_WIDTH 10U +#define LPDDR4__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_3__REG DENALI_PHY_770 +#define LPDDR4__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_770__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_770__PHY_BYPASS_TWO_CYC_PREAMBLE_3_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_770__PHY_BYPASS_TWO_CYC_PREAMBLE_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_770__PHY_BYPASS_TWO_CYC_PREAMBLE_3_WIDTH 2U +#define LPDDR4__PHY_BYPASS_TWO_CYC_PREAMBLE_3__REG DENALI_PHY_770 +#define LPDDR4__PHY_BYPASS_TWO_CYC_PREAMBLE_3__FLD LPDDR4__DENALI_PHY_770__PHY_BYPASS_TWO_CYC_PREAMBLE_3 + +#define LPDDR4__DENALI_PHY_770__PHY_CLK_BYPASS_OVERRIDE_3_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_770__PHY_CLK_BYPASS_OVERRIDE_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_770__PHY_CLK_BYPASS_OVERRIDE_3_WIDTH 1U +#define LPDDR4__DENALI_PHY_770__PHY_CLK_BYPASS_OVERRIDE_3_WOCLR 0U +#define LPDDR4__DENALI_PHY_770__PHY_CLK_BYPASS_OVERRIDE_3_WOSET 0U +#define LPDDR4__PHY_CLK_BYPASS_OVERRIDE_3__REG DENALI_PHY_770 +#define LPDDR4__PHY_CLK_BYPASS_OVERRIDE_3__FLD LPDDR4__DENALI_PHY_770__PHY_CLK_BYPASS_OVERRIDE_3 + +#define LPDDR4__DENALI_PHY_771_READ_MASK 0x3F3F3F3FU +#define LPDDR4__DENALI_PHY_771_WRITE_MASK 0x3F3F3F3FU +#define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ0_SHIFT_3_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ0_SHIFT_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ0_SHIFT_3_WIDTH 6U +#define LPDDR4__PHY_SW_WRDQ0_SHIFT_3__REG DENALI_PHY_771 +#define LPDDR4__PHY_SW_WRDQ0_SHIFT_3__FLD LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ0_SHIFT_3 + +#define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ1_SHIFT_3_MASK 0x00003F00U +#define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ1_SHIFT_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ1_SHIFT_3_WIDTH 6U +#define LPDDR4__PHY_SW_WRDQ1_SHIFT_3__REG DENALI_PHY_771 +#define LPDDR4__PHY_SW_WRDQ1_SHIFT_3__FLD LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ1_SHIFT_3 + +#define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ2_SHIFT_3_MASK 0x003F0000U +#define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ2_SHIFT_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ2_SHIFT_3_WIDTH 6U +#define LPDDR4__PHY_SW_WRDQ2_SHIFT_3__REG DENALI_PHY_771 +#define LPDDR4__PHY_SW_WRDQ2_SHIFT_3__FLD LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ2_SHIFT_3 + +#define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ3_SHIFT_3_MASK 0x3F000000U +#define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ3_SHIFT_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ3_SHIFT_3_WIDTH 6U +#define LPDDR4__PHY_SW_WRDQ3_SHIFT_3__REG DENALI_PHY_771 +#define LPDDR4__PHY_SW_WRDQ3_SHIFT_3__FLD LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ3_SHIFT_3 + +#define LPDDR4__DENALI_PHY_772_READ_MASK 0x3F3F3F3FU +#define LPDDR4__DENALI_PHY_772_WRITE_MASK 0x3F3F3F3FU +#define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ4_SHIFT_3_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ4_SHIFT_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ4_SHIFT_3_WIDTH 6U +#define LPDDR4__PHY_SW_WRDQ4_SHIFT_3__REG DENALI_PHY_772 +#define LPDDR4__PHY_SW_WRDQ4_SHIFT_3__FLD LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ4_SHIFT_3 + +#define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ5_SHIFT_3_MASK 0x00003F00U +#define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ5_SHIFT_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ5_SHIFT_3_WIDTH 6U +#define LPDDR4__PHY_SW_WRDQ5_SHIFT_3__REG DENALI_PHY_772 +#define LPDDR4__PHY_SW_WRDQ5_SHIFT_3__FLD LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ5_SHIFT_3 + +#define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ6_SHIFT_3_MASK 0x003F0000U +#define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ6_SHIFT_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ6_SHIFT_3_WIDTH 6U +#define LPDDR4__PHY_SW_WRDQ6_SHIFT_3__REG DENALI_PHY_772 +#define LPDDR4__PHY_SW_WRDQ6_SHIFT_3__FLD LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ6_SHIFT_3 + +#define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ7_SHIFT_3_MASK 0x3F000000U +#define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ7_SHIFT_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ7_SHIFT_3_WIDTH 6U +#define LPDDR4__PHY_SW_WRDQ7_SHIFT_3__REG DENALI_PHY_772 +#define LPDDR4__PHY_SW_WRDQ7_SHIFT_3__FLD LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ7_SHIFT_3 + +#define LPDDR4__DENALI_PHY_773_READ_MASK 0x01030F3FU +#define LPDDR4__DENALI_PHY_773_WRITE_MASK 0x01030F3FU +#define LPDDR4__DENALI_PHY_773__PHY_SW_WRDM_SHIFT_3_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_773__PHY_SW_WRDM_SHIFT_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_773__PHY_SW_WRDM_SHIFT_3_WIDTH 6U +#define LPDDR4__PHY_SW_WRDM_SHIFT_3__REG DENALI_PHY_773 +#define LPDDR4__PHY_SW_WRDM_SHIFT_3__FLD LPDDR4__DENALI_PHY_773__PHY_SW_WRDM_SHIFT_3 + +#define LPDDR4__DENALI_PHY_773__PHY_SW_WRDQS_SHIFT_3_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_773__PHY_SW_WRDQS_SHIFT_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_773__PHY_SW_WRDQS_SHIFT_3_WIDTH 4U +#define LPDDR4__PHY_SW_WRDQS_SHIFT_3__REG DENALI_PHY_773 +#define LPDDR4__PHY_SW_WRDQS_SHIFT_3__FLD LPDDR4__DENALI_PHY_773__PHY_SW_WRDQS_SHIFT_3 + +#define LPDDR4__DENALI_PHY_773__PHY_PER_RANK_CS_MAP_3_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_773__PHY_PER_RANK_CS_MAP_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_773__PHY_PER_RANK_CS_MAP_3_WIDTH 2U +#define LPDDR4__PHY_PER_RANK_CS_MAP_3__REG DENALI_PHY_773 +#define LPDDR4__PHY_PER_RANK_CS_MAP_3__FLD LPDDR4__DENALI_PHY_773__PHY_PER_RANK_CS_MAP_3 + +#define LPDDR4__DENALI_PHY_773__PHY_PER_CS_TRAINING_MULTICAST_EN_3_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_773__PHY_PER_CS_TRAINING_MULTICAST_EN_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_773__PHY_PER_CS_TRAINING_MULTICAST_EN_3_WIDTH 1U +#define LPDDR4__DENALI_PHY_773__PHY_PER_CS_TRAINING_MULTICAST_EN_3_WOCLR 0U +#define LPDDR4__DENALI_PHY_773__PHY_PER_CS_TRAINING_MULTICAST_EN_3_WOSET 0U +#define LPDDR4__PHY_PER_CS_TRAINING_MULTICAST_EN_3__REG DENALI_PHY_773 +#define LPDDR4__PHY_PER_CS_TRAINING_MULTICAST_EN_3__FLD LPDDR4__DENALI_PHY_773__PHY_PER_CS_TRAINING_MULTICAST_EN_3 + +#define LPDDR4__DENALI_PHY_774_READ_MASK 0x1F1F0301U +#define LPDDR4__DENALI_PHY_774_WRITE_MASK 0x1F1F0301U +#define LPDDR4__DENALI_PHY_774__PHY_PER_CS_TRAINING_INDEX_3_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_774__PHY_PER_CS_TRAINING_INDEX_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_774__PHY_PER_CS_TRAINING_INDEX_3_WIDTH 1U +#define LPDDR4__DENALI_PHY_774__PHY_PER_CS_TRAINING_INDEX_3_WOCLR 0U +#define LPDDR4__DENALI_PHY_774__PHY_PER_CS_TRAINING_INDEX_3_WOSET 0U +#define LPDDR4__PHY_PER_CS_TRAINING_INDEX_3__REG DENALI_PHY_774 +#define LPDDR4__PHY_PER_CS_TRAINING_INDEX_3__FLD LPDDR4__DENALI_PHY_774__PHY_PER_CS_TRAINING_INDEX_3 + +#define LPDDR4__DENALI_PHY_774__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_3_MASK 0x00000300U +#define LPDDR4__DENALI_PHY_774__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_774__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_3_WIDTH 2U +#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_3__REG DENALI_PHY_774 +#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_3__FLD LPDDR4__DENALI_PHY_774__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_3 + +#define LPDDR4__DENALI_PHY_774__PHY_LP4_BOOT_RDDATA_EN_DLY_3_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_774__PHY_LP4_BOOT_RDDATA_EN_DLY_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_774__PHY_LP4_BOOT_RDDATA_EN_DLY_3_WIDTH 5U +#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_DLY_3__REG DENALI_PHY_774 +#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_DLY_3__FLD LPDDR4__DENALI_PHY_774__PHY_LP4_BOOT_RDDATA_EN_DLY_3 + +#define LPDDR4__DENALI_PHY_774__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_3_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_774__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_774__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_3_WIDTH 5U +#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_3__REG DENALI_PHY_774 +#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_3__FLD LPDDR4__DENALI_PHY_774__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_3 + +#define LPDDR4__DENALI_PHY_775_READ_MASK 0x1F030F0FU +#define LPDDR4__DENALI_PHY_775_WRITE_MASK 0x1F030F0FU +#define LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_RPTR_UPDATE_3_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_RPTR_UPDATE_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_RPTR_UPDATE_3_WIDTH 4U +#define LPDDR4__PHY_LP4_BOOT_RPTR_UPDATE_3__REG DENALI_PHY_775 +#define LPDDR4__PHY_LP4_BOOT_RPTR_UPDATE_3__FLD LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_RPTR_UPDATE_3 + +#define LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_3_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_3_WIDTH 4U +#define LPDDR4__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_3__REG DENALI_PHY_775 +#define LPDDR4__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_3__FLD LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_3 + +#define LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_3_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_3_WIDTH 2U +#define LPDDR4__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_3__REG DENALI_PHY_775 +#define LPDDR4__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_3__FLD LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_3 + +#define LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_3_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_3_WIDTH 5U +#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_3__REG DENALI_PHY_775 +#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_3__FLD LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_3 + +#define LPDDR4__DENALI_PHY_776_READ_MASK 0x0101FF03U +#define LPDDR4__DENALI_PHY_776_WRITE_MASK 0x0101FF03U +#define LPDDR4__DENALI_PHY_776__PHY_CTRL_LPBK_EN_3_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_776__PHY_CTRL_LPBK_EN_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_776__PHY_CTRL_LPBK_EN_3_WIDTH 2U +#define LPDDR4__PHY_CTRL_LPBK_EN_3__REG DENALI_PHY_776 +#define LPDDR4__PHY_CTRL_LPBK_EN_3__FLD LPDDR4__DENALI_PHY_776__PHY_CTRL_LPBK_EN_3 + +#define LPDDR4__DENALI_PHY_776__PHY_LPBK_CONTROL_3_MASK 0x0001FF00U +#define LPDDR4__DENALI_PHY_776__PHY_LPBK_CONTROL_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_776__PHY_LPBK_CONTROL_3_WIDTH 9U +#define LPDDR4__PHY_LPBK_CONTROL_3__REG DENALI_PHY_776 +#define LPDDR4__PHY_LPBK_CONTROL_3__FLD LPDDR4__DENALI_PHY_776__PHY_LPBK_CONTROL_3 + +#define LPDDR4__DENALI_PHY_776__PHY_LPBK_DFX_TIMEOUT_EN_3_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_776__PHY_LPBK_DFX_TIMEOUT_EN_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_776__PHY_LPBK_DFX_TIMEOUT_EN_3_WIDTH 1U +#define LPDDR4__DENALI_PHY_776__PHY_LPBK_DFX_TIMEOUT_EN_3_WOCLR 0U +#define LPDDR4__DENALI_PHY_776__PHY_LPBK_DFX_TIMEOUT_EN_3_WOSET 0U +#define LPDDR4__PHY_LPBK_DFX_TIMEOUT_EN_3__REG DENALI_PHY_776 +#define LPDDR4__PHY_LPBK_DFX_TIMEOUT_EN_3__FLD LPDDR4__DENALI_PHY_776__PHY_LPBK_DFX_TIMEOUT_EN_3 + +#define LPDDR4__DENALI_PHY_777_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_777_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_777__PHY_AUTO_TIMING_MARGIN_CONTROL_3_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_777__PHY_AUTO_TIMING_MARGIN_CONTROL_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_777__PHY_AUTO_TIMING_MARGIN_CONTROL_3_WIDTH 32U +#define LPDDR4__PHY_AUTO_TIMING_MARGIN_CONTROL_3__REG DENALI_PHY_777 +#define LPDDR4__PHY_AUTO_TIMING_MARGIN_CONTROL_3__FLD LPDDR4__DENALI_PHY_777__PHY_AUTO_TIMING_MARGIN_CONTROL_3 + +#define LPDDR4__DENALI_PHY_778_READ_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_778_WRITE_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_778__PHY_AUTO_TIMING_MARGIN_OBS_3_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_778__PHY_AUTO_TIMING_MARGIN_OBS_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_778__PHY_AUTO_TIMING_MARGIN_OBS_3_WIDTH 28U +#define LPDDR4__PHY_AUTO_TIMING_MARGIN_OBS_3__REG DENALI_PHY_778 +#define LPDDR4__PHY_AUTO_TIMING_MARGIN_OBS_3__FLD LPDDR4__DENALI_PHY_778__PHY_AUTO_TIMING_MARGIN_OBS_3 + +#define LPDDR4__DENALI_PHY_779_READ_MASK 0x0101FF7FU +#define LPDDR4__DENALI_PHY_779_WRITE_MASK 0x0101FF7FU +#define LPDDR4__DENALI_PHY_779__PHY_PRBS_PATTERN_START_3_MASK 0x0000007FU +#define LPDDR4__DENALI_PHY_779__PHY_PRBS_PATTERN_START_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_779__PHY_PRBS_PATTERN_START_3_WIDTH 7U +#define LPDDR4__PHY_PRBS_PATTERN_START_3__REG DENALI_PHY_779 +#define LPDDR4__PHY_PRBS_PATTERN_START_3__FLD LPDDR4__DENALI_PHY_779__PHY_PRBS_PATTERN_START_3 + +#define LPDDR4__DENALI_PHY_779__PHY_PRBS_PATTERN_MASK_3_MASK 0x0001FF00U +#define LPDDR4__DENALI_PHY_779__PHY_PRBS_PATTERN_MASK_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_779__PHY_PRBS_PATTERN_MASK_3_WIDTH 9U +#define LPDDR4__PHY_PRBS_PATTERN_MASK_3__REG DENALI_PHY_779 +#define LPDDR4__PHY_PRBS_PATTERN_MASK_3__FLD LPDDR4__DENALI_PHY_779__PHY_PRBS_PATTERN_MASK_3 + +#define LPDDR4__DENALI_PHY_779__PHY_RDLVL_MULTI_PATT_ENABLE_3_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_779__PHY_RDLVL_MULTI_PATT_ENABLE_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_779__PHY_RDLVL_MULTI_PATT_ENABLE_3_WIDTH 1U +#define LPDDR4__DENALI_PHY_779__PHY_RDLVL_MULTI_PATT_ENABLE_3_WOCLR 0U +#define LPDDR4__DENALI_PHY_779__PHY_RDLVL_MULTI_PATT_ENABLE_3_WOSET 0U +#define LPDDR4__PHY_RDLVL_MULTI_PATT_ENABLE_3__REG DENALI_PHY_779 +#define LPDDR4__PHY_RDLVL_MULTI_PATT_ENABLE_3__FLD LPDDR4__DENALI_PHY_779__PHY_RDLVL_MULTI_PATT_ENABLE_3 + +#define LPDDR4__DENALI_PHY_780_READ_MASK 0x007F3F01U +#define LPDDR4__DENALI_PHY_780_WRITE_MASK 0x007F3F01U +#define LPDDR4__DENALI_PHY_780__PHY_RDLVL_MULTI_PATT_RST_DISABLE_3_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_780__PHY_RDLVL_MULTI_PATT_RST_DISABLE_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_780__PHY_RDLVL_MULTI_PATT_RST_DISABLE_3_WIDTH 1U +#define LPDDR4__DENALI_PHY_780__PHY_RDLVL_MULTI_PATT_RST_DISABLE_3_WOCLR 0U +#define LPDDR4__DENALI_PHY_780__PHY_RDLVL_MULTI_PATT_RST_DISABLE_3_WOSET 0U +#define LPDDR4__PHY_RDLVL_MULTI_PATT_RST_DISABLE_3__REG DENALI_PHY_780 +#define LPDDR4__PHY_RDLVL_MULTI_PATT_RST_DISABLE_3__FLD LPDDR4__DENALI_PHY_780__PHY_RDLVL_MULTI_PATT_RST_DISABLE_3 + +#define LPDDR4__DENALI_PHY_780__PHY_VREF_INITIAL_STEPSIZE_3_MASK 0x00003F00U +#define LPDDR4__DENALI_PHY_780__PHY_VREF_INITIAL_STEPSIZE_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_780__PHY_VREF_INITIAL_STEPSIZE_3_WIDTH 6U +#define LPDDR4__PHY_VREF_INITIAL_STEPSIZE_3__REG DENALI_PHY_780 +#define LPDDR4__PHY_VREF_INITIAL_STEPSIZE_3__FLD LPDDR4__DENALI_PHY_780__PHY_VREF_INITIAL_STEPSIZE_3 + +#define LPDDR4__DENALI_PHY_780__PHY_VREF_TRAIN_OBS_3_MASK 0x007F0000U +#define LPDDR4__DENALI_PHY_780__PHY_VREF_TRAIN_OBS_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_780__PHY_VREF_TRAIN_OBS_3_WIDTH 7U +#define LPDDR4__PHY_VREF_TRAIN_OBS_3__REG DENALI_PHY_780 +#define LPDDR4__PHY_VREF_TRAIN_OBS_3__FLD LPDDR4__DENALI_PHY_780__PHY_VREF_TRAIN_OBS_3 + +#define LPDDR4__DENALI_PHY_781_READ_MASK 0x000F03FFU +#define LPDDR4__DENALI_PHY_781_WRITE_MASK 0x000F03FFU +#define LPDDR4__DENALI_PHY_781__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_3_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_781__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_781__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_3_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_3__REG DENALI_PHY_781 +#define LPDDR4__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_781__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_781__PHY_GATE_ERROR_DELAY_SELECT_3_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_781__PHY_GATE_ERROR_DELAY_SELECT_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_781__PHY_GATE_ERROR_DELAY_SELECT_3_WIDTH 4U +#define LPDDR4__PHY_GATE_ERROR_DELAY_SELECT_3__REG DENALI_PHY_781 +#define LPDDR4__PHY_GATE_ERROR_DELAY_SELECT_3__FLD LPDDR4__DENALI_PHY_781__PHY_GATE_ERROR_DELAY_SELECT_3 + +#define LPDDR4__DENALI_PHY_781__SC_PHY_SNAP_OBS_REGS_3_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_781__SC_PHY_SNAP_OBS_REGS_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_781__SC_PHY_SNAP_OBS_REGS_3_WIDTH 1U +#define LPDDR4__DENALI_PHY_781__SC_PHY_SNAP_OBS_REGS_3_WOCLR 0U +#define LPDDR4__DENALI_PHY_781__SC_PHY_SNAP_OBS_REGS_3_WOSET 0U +#define LPDDR4__SC_PHY_SNAP_OBS_REGS_3__REG DENALI_PHY_781 +#define LPDDR4__SC_PHY_SNAP_OBS_REGS_3__FLD LPDDR4__DENALI_PHY_781__SC_PHY_SNAP_OBS_REGS_3 + +#define LPDDR4__DENALI_PHY_782_READ_MASK 0x070101FFU +#define LPDDR4__DENALI_PHY_782_WRITE_MASK 0x070101FFU +#define LPDDR4__DENALI_PHY_782__PHY_GATE_SMPL1_SLAVE_DELAY_3_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_782__PHY_GATE_SMPL1_SLAVE_DELAY_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_782__PHY_GATE_SMPL1_SLAVE_DELAY_3_WIDTH 9U +#define LPDDR4__PHY_GATE_SMPL1_SLAVE_DELAY_3__REG DENALI_PHY_782 +#define LPDDR4__PHY_GATE_SMPL1_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_782__PHY_GATE_SMPL1_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_782__PHY_LPDDR_3_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_782__PHY_LPDDR_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_782__PHY_LPDDR_3_WIDTH 1U +#define LPDDR4__DENALI_PHY_782__PHY_LPDDR_3_WOCLR 0U +#define LPDDR4__DENALI_PHY_782__PHY_LPDDR_3_WOSET 0U +#define LPDDR4__PHY_LPDDR_3__REG DENALI_PHY_782 +#define LPDDR4__PHY_LPDDR_3__FLD LPDDR4__DENALI_PHY_782__PHY_LPDDR_3 + +#define LPDDR4__DENALI_PHY_782__PHY_MEM_CLASS_3_MASK 0x07000000U +#define LPDDR4__DENALI_PHY_782__PHY_MEM_CLASS_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_782__PHY_MEM_CLASS_3_WIDTH 3U +#define LPDDR4__PHY_MEM_CLASS_3__REG DENALI_PHY_782 +#define LPDDR4__PHY_MEM_CLASS_3__FLD LPDDR4__DENALI_PHY_782__PHY_MEM_CLASS_3 + +#define LPDDR4__DENALI_PHY_783_READ_MASK 0x000301FFU +#define LPDDR4__DENALI_PHY_783_WRITE_MASK 0x000301FFU +#define LPDDR4__DENALI_PHY_783__PHY_GATE_SMPL2_SLAVE_DELAY_3_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_783__PHY_GATE_SMPL2_SLAVE_DELAY_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_783__PHY_GATE_SMPL2_SLAVE_DELAY_3_WIDTH 9U +#define LPDDR4__PHY_GATE_SMPL2_SLAVE_DELAY_3__REG DENALI_PHY_783 +#define LPDDR4__PHY_GATE_SMPL2_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_783__PHY_GATE_SMPL2_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_783__ON_FLY_GATE_ADJUST_EN_3_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_783__ON_FLY_GATE_ADJUST_EN_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_783__ON_FLY_GATE_ADJUST_EN_3_WIDTH 2U +#define LPDDR4__ON_FLY_GATE_ADJUST_EN_3__REG DENALI_PHY_783 +#define LPDDR4__ON_FLY_GATE_ADJUST_EN_3__FLD LPDDR4__DENALI_PHY_783__ON_FLY_GATE_ADJUST_EN_3 + +#define LPDDR4__DENALI_PHY_784_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_784_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_784__PHY_GATE_TRACKING_OBS_3_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_784__PHY_GATE_TRACKING_OBS_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_784__PHY_GATE_TRACKING_OBS_3_WIDTH 32U +#define LPDDR4__PHY_GATE_TRACKING_OBS_3__REG DENALI_PHY_784 +#define LPDDR4__PHY_GATE_TRACKING_OBS_3__FLD LPDDR4__DENALI_PHY_784__PHY_GATE_TRACKING_OBS_3 + +#define LPDDR4__DENALI_PHY_785_READ_MASK 0x00000301U +#define LPDDR4__DENALI_PHY_785_WRITE_MASK 0x00000301U +#define LPDDR4__DENALI_PHY_785__PHY_DFI40_POLARITY_3_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_785__PHY_DFI40_POLARITY_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_785__PHY_DFI40_POLARITY_3_WIDTH 1U +#define LPDDR4__DENALI_PHY_785__PHY_DFI40_POLARITY_3_WOCLR 0U +#define LPDDR4__DENALI_PHY_785__PHY_DFI40_POLARITY_3_WOSET 0U +#define LPDDR4__PHY_DFI40_POLARITY_3__REG DENALI_PHY_785 +#define LPDDR4__PHY_DFI40_POLARITY_3__FLD LPDDR4__DENALI_PHY_785__PHY_DFI40_POLARITY_3 + +#define LPDDR4__DENALI_PHY_785__PHY_LP4_PST_AMBLE_3_MASK 0x00000300U +#define LPDDR4__DENALI_PHY_785__PHY_LP4_PST_AMBLE_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_785__PHY_LP4_PST_AMBLE_3_WIDTH 2U +#define LPDDR4__PHY_LP4_PST_AMBLE_3__REG DENALI_PHY_785 +#define LPDDR4__PHY_LP4_PST_AMBLE_3__FLD LPDDR4__DENALI_PHY_785__PHY_LP4_PST_AMBLE_3 + +#define LPDDR4__DENALI_PHY_786_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_786_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_786__PHY_RDLVL_PATT8_3_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_786__PHY_RDLVL_PATT8_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_786__PHY_RDLVL_PATT8_3_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PATT8_3__REG DENALI_PHY_786 +#define LPDDR4__PHY_RDLVL_PATT8_3__FLD LPDDR4__DENALI_PHY_786__PHY_RDLVL_PATT8_3 + +#define LPDDR4__DENALI_PHY_787_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_787_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_787__PHY_RDLVL_PATT9_3_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_787__PHY_RDLVL_PATT9_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_787__PHY_RDLVL_PATT9_3_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PATT9_3__REG DENALI_PHY_787 +#define LPDDR4__PHY_RDLVL_PATT9_3__FLD LPDDR4__DENALI_PHY_787__PHY_RDLVL_PATT9_3 + +#define LPDDR4__DENALI_PHY_788_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_788_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_788__PHY_RDLVL_PATT10_3_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_788__PHY_RDLVL_PATT10_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_788__PHY_RDLVL_PATT10_3_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PATT10_3__REG DENALI_PHY_788 +#define LPDDR4__PHY_RDLVL_PATT10_3__FLD LPDDR4__DENALI_PHY_788__PHY_RDLVL_PATT10_3 + +#define LPDDR4__DENALI_PHY_789_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_789_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_789__PHY_RDLVL_PATT11_3_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_789__PHY_RDLVL_PATT11_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_789__PHY_RDLVL_PATT11_3_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PATT11_3__REG DENALI_PHY_789 +#define LPDDR4__PHY_RDLVL_PATT11_3__FLD LPDDR4__DENALI_PHY_789__PHY_RDLVL_PATT11_3 + +#define LPDDR4__DENALI_PHY_790_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_790_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_790__PHY_RDLVL_PATT12_3_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_790__PHY_RDLVL_PATT12_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_790__PHY_RDLVL_PATT12_3_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PATT12_3__REG DENALI_PHY_790 +#define LPDDR4__PHY_RDLVL_PATT12_3__FLD LPDDR4__DENALI_PHY_790__PHY_RDLVL_PATT12_3 + +#define LPDDR4__DENALI_PHY_791_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_791_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_791__PHY_RDLVL_PATT13_3_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_791__PHY_RDLVL_PATT13_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_791__PHY_RDLVL_PATT13_3_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PATT13_3__REG DENALI_PHY_791 +#define LPDDR4__PHY_RDLVL_PATT13_3__FLD LPDDR4__DENALI_PHY_791__PHY_RDLVL_PATT13_3 + +#define LPDDR4__DENALI_PHY_792_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_792_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_792__PHY_RDLVL_PATT14_3_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_792__PHY_RDLVL_PATT14_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_792__PHY_RDLVL_PATT14_3_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PATT14_3__REG DENALI_PHY_792 +#define LPDDR4__PHY_RDLVL_PATT14_3__FLD LPDDR4__DENALI_PHY_792__PHY_RDLVL_PATT14_3 + +#define LPDDR4__DENALI_PHY_793_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_793_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_793__PHY_RDLVL_PATT15_3_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_793__PHY_RDLVL_PATT15_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_793__PHY_RDLVL_PATT15_3_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PATT15_3__REG DENALI_PHY_793 +#define LPDDR4__PHY_RDLVL_PATT15_3__FLD LPDDR4__DENALI_PHY_793__PHY_RDLVL_PATT15_3 + +#define LPDDR4__DENALI_PHY_794_READ_MASK 0x070F0107U +#define LPDDR4__DENALI_PHY_794_WRITE_MASK 0x070F0107U +#define LPDDR4__DENALI_PHY_794__PHY_SLAVE_LOOP_CNT_UPDATE_3_MASK 0x00000007U +#define LPDDR4__DENALI_PHY_794__PHY_SLAVE_LOOP_CNT_UPDATE_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_794__PHY_SLAVE_LOOP_CNT_UPDATE_3_WIDTH 3U +#define LPDDR4__PHY_SLAVE_LOOP_CNT_UPDATE_3__REG DENALI_PHY_794 +#define LPDDR4__PHY_SLAVE_LOOP_CNT_UPDATE_3__FLD LPDDR4__DENALI_PHY_794__PHY_SLAVE_LOOP_CNT_UPDATE_3 + +#define LPDDR4__DENALI_PHY_794__PHY_SW_FIFO_PTR_RST_DISABLE_3_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_794__PHY_SW_FIFO_PTR_RST_DISABLE_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_794__PHY_SW_FIFO_PTR_RST_DISABLE_3_WIDTH 1U +#define LPDDR4__DENALI_PHY_794__PHY_SW_FIFO_PTR_RST_DISABLE_3_WOCLR 0U +#define LPDDR4__DENALI_PHY_794__PHY_SW_FIFO_PTR_RST_DISABLE_3_WOSET 0U +#define LPDDR4__PHY_SW_FIFO_PTR_RST_DISABLE_3__REG DENALI_PHY_794 +#define LPDDR4__PHY_SW_FIFO_PTR_RST_DISABLE_3__FLD LPDDR4__DENALI_PHY_794__PHY_SW_FIFO_PTR_RST_DISABLE_3 + +#define LPDDR4__DENALI_PHY_794__PHY_MASTER_DLY_LOCK_OBS_SELECT_3_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_794__PHY_MASTER_DLY_LOCK_OBS_SELECT_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_794__PHY_MASTER_DLY_LOCK_OBS_SELECT_3_WIDTH 4U +#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_SELECT_3__REG DENALI_PHY_794 +#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_SELECT_3__FLD LPDDR4__DENALI_PHY_794__PHY_MASTER_DLY_LOCK_OBS_SELECT_3 + +#define LPDDR4__DENALI_PHY_794__PHY_RDDQ_ENC_OBS_SELECT_3_MASK 0x07000000U +#define LPDDR4__DENALI_PHY_794__PHY_RDDQ_ENC_OBS_SELECT_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_794__PHY_RDDQ_ENC_OBS_SELECT_3_WIDTH 3U +#define LPDDR4__PHY_RDDQ_ENC_OBS_SELECT_3__REG DENALI_PHY_794 +#define LPDDR4__PHY_RDDQ_ENC_OBS_SELECT_3__FLD LPDDR4__DENALI_PHY_794__PHY_RDDQ_ENC_OBS_SELECT_3 + +#define LPDDR4__DENALI_PHY_795_READ_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_PHY_795_WRITE_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_PHY_795__PHY_RDDQS_DQ_ENC_OBS_SELECT_3_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_795__PHY_RDDQS_DQ_ENC_OBS_SELECT_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_795__PHY_RDDQS_DQ_ENC_OBS_SELECT_3_WIDTH 4U +#define LPDDR4__PHY_RDDQS_DQ_ENC_OBS_SELECT_3__REG DENALI_PHY_795 +#define LPDDR4__PHY_RDDQS_DQ_ENC_OBS_SELECT_3__FLD LPDDR4__DENALI_PHY_795__PHY_RDDQS_DQ_ENC_OBS_SELECT_3 + +#define LPDDR4__DENALI_PHY_795__PHY_WR_ENC_OBS_SELECT_3_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_795__PHY_WR_ENC_OBS_SELECT_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_795__PHY_WR_ENC_OBS_SELECT_3_WIDTH 4U +#define LPDDR4__PHY_WR_ENC_OBS_SELECT_3__REG DENALI_PHY_795 +#define LPDDR4__PHY_WR_ENC_OBS_SELECT_3__FLD LPDDR4__DENALI_PHY_795__PHY_WR_ENC_OBS_SELECT_3 + +#define LPDDR4__DENALI_PHY_795__PHY_WR_SHIFT_OBS_SELECT_3_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_795__PHY_WR_SHIFT_OBS_SELECT_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_795__PHY_WR_SHIFT_OBS_SELECT_3_WIDTH 4U +#define LPDDR4__PHY_WR_SHIFT_OBS_SELECT_3__REG DENALI_PHY_795 +#define LPDDR4__PHY_WR_SHIFT_OBS_SELECT_3__FLD LPDDR4__DENALI_PHY_795__PHY_WR_SHIFT_OBS_SELECT_3 + +#define LPDDR4__DENALI_PHY_795__PHY_FIFO_PTR_OBS_SELECT_3_MASK 0x0F000000U +#define LPDDR4__DENALI_PHY_795__PHY_FIFO_PTR_OBS_SELECT_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_795__PHY_FIFO_PTR_OBS_SELECT_3_WIDTH 4U +#define LPDDR4__PHY_FIFO_PTR_OBS_SELECT_3__REG DENALI_PHY_795 +#define LPDDR4__PHY_FIFO_PTR_OBS_SELECT_3__FLD LPDDR4__DENALI_PHY_795__PHY_FIFO_PTR_OBS_SELECT_3 + +#define LPDDR4__DENALI_PHY_796_READ_MASK 0xFF030001U +#define LPDDR4__DENALI_PHY_796_WRITE_MASK 0xFF030001U +#define LPDDR4__DENALI_PHY_796__PHY_LVL_DEBUG_MODE_3_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_796__PHY_LVL_DEBUG_MODE_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_796__PHY_LVL_DEBUG_MODE_3_WIDTH 1U +#define LPDDR4__DENALI_PHY_796__PHY_LVL_DEBUG_MODE_3_WOCLR 0U +#define LPDDR4__DENALI_PHY_796__PHY_LVL_DEBUG_MODE_3_WOSET 0U +#define LPDDR4__PHY_LVL_DEBUG_MODE_3__REG DENALI_PHY_796 +#define LPDDR4__PHY_LVL_DEBUG_MODE_3__FLD LPDDR4__DENALI_PHY_796__PHY_LVL_DEBUG_MODE_3 + +#define LPDDR4__DENALI_PHY_796__SC_PHY_LVL_DEBUG_CONT_3_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_796__SC_PHY_LVL_DEBUG_CONT_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_796__SC_PHY_LVL_DEBUG_CONT_3_WIDTH 1U +#define LPDDR4__DENALI_PHY_796__SC_PHY_LVL_DEBUG_CONT_3_WOCLR 0U +#define LPDDR4__DENALI_PHY_796__SC_PHY_LVL_DEBUG_CONT_3_WOSET 0U +#define LPDDR4__SC_PHY_LVL_DEBUG_CONT_3__REG DENALI_PHY_796 +#define LPDDR4__SC_PHY_LVL_DEBUG_CONT_3__FLD LPDDR4__DENALI_PHY_796__SC_PHY_LVL_DEBUG_CONT_3 + +#define LPDDR4__DENALI_PHY_796__PHY_WRLVL_ALGO_3_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_796__PHY_WRLVL_ALGO_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_796__PHY_WRLVL_ALGO_3_WIDTH 2U +#define LPDDR4__PHY_WRLVL_ALGO_3__REG DENALI_PHY_796 +#define LPDDR4__PHY_WRLVL_ALGO_3__FLD LPDDR4__DENALI_PHY_796__PHY_WRLVL_ALGO_3 + +#define LPDDR4__DENALI_PHY_796__PHY_WRLVL_PER_START_3_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_796__PHY_WRLVL_PER_START_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_796__PHY_WRLVL_PER_START_3_WIDTH 8U +#define LPDDR4__PHY_WRLVL_PER_START_3__REG DENALI_PHY_796 +#define LPDDR4__PHY_WRLVL_PER_START_3__FLD LPDDR4__DENALI_PHY_796__PHY_WRLVL_PER_START_3 + +#define LPDDR4__DENALI_PHY_797_READ_MASK 0x00FF0F3FU +#define LPDDR4__DENALI_PHY_797_WRITE_MASK 0x00FF0F3FU +#define LPDDR4__DENALI_PHY_797__PHY_WRLVL_CAPTURE_CNT_3_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_797__PHY_WRLVL_CAPTURE_CNT_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_797__PHY_WRLVL_CAPTURE_CNT_3_WIDTH 6U +#define LPDDR4__PHY_WRLVL_CAPTURE_CNT_3__REG DENALI_PHY_797 +#define LPDDR4__PHY_WRLVL_CAPTURE_CNT_3__FLD LPDDR4__DENALI_PHY_797__PHY_WRLVL_CAPTURE_CNT_3 + +#define LPDDR4__DENALI_PHY_797__PHY_WRLVL_UPDT_WAIT_CNT_3_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_797__PHY_WRLVL_UPDT_WAIT_CNT_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_797__PHY_WRLVL_UPDT_WAIT_CNT_3_WIDTH 4U +#define LPDDR4__PHY_WRLVL_UPDT_WAIT_CNT_3__REG DENALI_PHY_797 +#define LPDDR4__PHY_WRLVL_UPDT_WAIT_CNT_3__FLD LPDDR4__DENALI_PHY_797__PHY_WRLVL_UPDT_WAIT_CNT_3 + +#define LPDDR4__DENALI_PHY_797__PHY_DQ_MASK_3_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_797__PHY_DQ_MASK_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_797__PHY_DQ_MASK_3_WIDTH 8U +#define LPDDR4__PHY_DQ_MASK_3__REG DENALI_PHY_797 +#define LPDDR4__PHY_DQ_MASK_3__FLD LPDDR4__DENALI_PHY_797__PHY_DQ_MASK_3 + +#define LPDDR4__DENALI_PHY_798_READ_MASK 0x0F3F03FFU +#define LPDDR4__DENALI_PHY_798_WRITE_MASK 0x0F3F03FFU +#define LPDDR4__DENALI_PHY_798__PHY_GTLVL_PER_START_3_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_798__PHY_GTLVL_PER_START_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_798__PHY_GTLVL_PER_START_3_WIDTH 10U +#define LPDDR4__PHY_GTLVL_PER_START_3__REG DENALI_PHY_798 +#define LPDDR4__PHY_GTLVL_PER_START_3__FLD LPDDR4__DENALI_PHY_798__PHY_GTLVL_PER_START_3 + +#define LPDDR4__DENALI_PHY_798__PHY_GTLVL_CAPTURE_CNT_3_MASK 0x003F0000U +#define LPDDR4__DENALI_PHY_798__PHY_GTLVL_CAPTURE_CNT_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_798__PHY_GTLVL_CAPTURE_CNT_3_WIDTH 6U +#define LPDDR4__PHY_GTLVL_CAPTURE_CNT_3__REG DENALI_PHY_798 +#define LPDDR4__PHY_GTLVL_CAPTURE_CNT_3__FLD LPDDR4__DENALI_PHY_798__PHY_GTLVL_CAPTURE_CNT_3 + +#define LPDDR4__DENALI_PHY_798__PHY_GTLVL_UPDT_WAIT_CNT_3_MASK 0x0F000000U +#define LPDDR4__DENALI_PHY_798__PHY_GTLVL_UPDT_WAIT_CNT_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_798__PHY_GTLVL_UPDT_WAIT_CNT_3_WIDTH 4U +#define LPDDR4__PHY_GTLVL_UPDT_WAIT_CNT_3__REG DENALI_PHY_798 +#define LPDDR4__PHY_GTLVL_UPDT_WAIT_CNT_3__FLD LPDDR4__DENALI_PHY_798__PHY_GTLVL_UPDT_WAIT_CNT_3 + +#define LPDDR4__DENALI_PHY_799_READ_MASK 0x1F030F3FU +#define LPDDR4__DENALI_PHY_799_WRITE_MASK 0x1F030F3FU +#define LPDDR4__DENALI_PHY_799__PHY_RDLVL_CAPTURE_CNT_3_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_799__PHY_RDLVL_CAPTURE_CNT_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_799__PHY_RDLVL_CAPTURE_CNT_3_WIDTH 6U +#define LPDDR4__PHY_RDLVL_CAPTURE_CNT_3__REG DENALI_PHY_799 +#define LPDDR4__PHY_RDLVL_CAPTURE_CNT_3__FLD LPDDR4__DENALI_PHY_799__PHY_RDLVL_CAPTURE_CNT_3 + +#define LPDDR4__DENALI_PHY_799__PHY_RDLVL_UPDT_WAIT_CNT_3_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_799__PHY_RDLVL_UPDT_WAIT_CNT_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_799__PHY_RDLVL_UPDT_WAIT_CNT_3_WIDTH 4U +#define LPDDR4__PHY_RDLVL_UPDT_WAIT_CNT_3__REG DENALI_PHY_799 +#define LPDDR4__PHY_RDLVL_UPDT_WAIT_CNT_3__FLD LPDDR4__DENALI_PHY_799__PHY_RDLVL_UPDT_WAIT_CNT_3 + +#define LPDDR4__DENALI_PHY_799__PHY_RDLVL_OP_MODE_3_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_799__PHY_RDLVL_OP_MODE_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_799__PHY_RDLVL_OP_MODE_3_WIDTH 2U +#define LPDDR4__PHY_RDLVL_OP_MODE_3__REG DENALI_PHY_799 +#define LPDDR4__PHY_RDLVL_OP_MODE_3__FLD LPDDR4__DENALI_PHY_799__PHY_RDLVL_OP_MODE_3 + +#define LPDDR4__DENALI_PHY_799__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_3_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_799__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_799__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_3_WIDTH 5U +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_3__REG DENALI_PHY_799 +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_3__FLD LPDDR4__DENALI_PHY_799__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_3 + +#define LPDDR4__DENALI_PHY_800_READ_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_800_WRITE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_800__PHY_RDLVL_PERIODIC_OBS_SELECT_3_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_800__PHY_RDLVL_PERIODIC_OBS_SELECT_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_800__PHY_RDLVL_PERIODIC_OBS_SELECT_3_WIDTH 8U +#define LPDDR4__PHY_RDLVL_PERIODIC_OBS_SELECT_3__REG DENALI_PHY_800 +#define LPDDR4__PHY_RDLVL_PERIODIC_OBS_SELECT_3__FLD LPDDR4__DENALI_PHY_800__PHY_RDLVL_PERIODIC_OBS_SELECT_3 + +#define LPDDR4__DENALI_PHY_800__PHY_RDLVL_DATA_MASK_3_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_800__PHY_RDLVL_DATA_MASK_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_800__PHY_RDLVL_DATA_MASK_3_WIDTH 8U +#define LPDDR4__PHY_RDLVL_DATA_MASK_3__REG DENALI_PHY_800 +#define LPDDR4__PHY_RDLVL_DATA_MASK_3__FLD LPDDR4__DENALI_PHY_800__PHY_RDLVL_DATA_MASK_3 + +#define LPDDR4__DENALI_PHY_800__PHY_WDQLVL_CLK_JITTER_TOLERANCE_3_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_800__PHY_WDQLVL_CLK_JITTER_TOLERANCE_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_800__PHY_WDQLVL_CLK_JITTER_TOLERANCE_3_WIDTH 8U +#define LPDDR4__PHY_WDQLVL_CLK_JITTER_TOLERANCE_3__REG DENALI_PHY_800 +#define LPDDR4__PHY_WDQLVL_CLK_JITTER_TOLERANCE_3__FLD LPDDR4__DENALI_PHY_800__PHY_WDQLVL_CLK_JITTER_TOLERANCE_3 + +#define LPDDR4__DENALI_PHY_800__PHY_WDQLVL_BURST_CNT_3_MASK 0x3F000000U +#define LPDDR4__DENALI_PHY_800__PHY_WDQLVL_BURST_CNT_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_800__PHY_WDQLVL_BURST_CNT_3_WIDTH 6U +#define LPDDR4__PHY_WDQLVL_BURST_CNT_3__REG DENALI_PHY_800 +#define LPDDR4__PHY_WDQLVL_BURST_CNT_3__FLD LPDDR4__DENALI_PHY_800__PHY_WDQLVL_BURST_CNT_3 + +#define LPDDR4__DENALI_PHY_801_READ_MASK 0x0F07FF07U +#define LPDDR4__DENALI_PHY_801_WRITE_MASK 0x0F07FF07U +#define LPDDR4__DENALI_PHY_801__PHY_WDQLVL_PATT_3_MASK 0x00000007U +#define LPDDR4__DENALI_PHY_801__PHY_WDQLVL_PATT_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_801__PHY_WDQLVL_PATT_3_WIDTH 3U +#define LPDDR4__PHY_WDQLVL_PATT_3__REG DENALI_PHY_801 +#define LPDDR4__PHY_WDQLVL_PATT_3__FLD LPDDR4__DENALI_PHY_801__PHY_WDQLVL_PATT_3 + +#define LPDDR4__DENALI_PHY_801__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_3_MASK 0x0007FF00U +#define LPDDR4__DENALI_PHY_801__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_801__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_3_WIDTH 11U +#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_3__REG DENALI_PHY_801 +#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_3__FLD LPDDR4__DENALI_PHY_801__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_3 + +#define LPDDR4__DENALI_PHY_801__PHY_WDQLVL_UPDT_WAIT_CNT_3_MASK 0x0F000000U +#define LPDDR4__DENALI_PHY_801__PHY_WDQLVL_UPDT_WAIT_CNT_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_801__PHY_WDQLVL_UPDT_WAIT_CNT_3_WIDTH 4U +#define LPDDR4__PHY_WDQLVL_UPDT_WAIT_CNT_3__REG DENALI_PHY_801 +#define LPDDR4__PHY_WDQLVL_UPDT_WAIT_CNT_3__FLD LPDDR4__DENALI_PHY_801__PHY_WDQLVL_UPDT_WAIT_CNT_3 + +#define LPDDR4__DENALI_PHY_802_READ_MASK 0x0000FF0FU +#define LPDDR4__DENALI_PHY_802_WRITE_MASK 0x0000FF0FU +#define LPDDR4__DENALI_PHY_802__PHY_WDQLVL_DQDM_OBS_SELECT_3_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_802__PHY_WDQLVL_DQDM_OBS_SELECT_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_802__PHY_WDQLVL_DQDM_OBS_SELECT_3_WIDTH 4U +#define LPDDR4__PHY_WDQLVL_DQDM_OBS_SELECT_3__REG DENALI_PHY_802 +#define LPDDR4__PHY_WDQLVL_DQDM_OBS_SELECT_3__FLD LPDDR4__DENALI_PHY_802__PHY_WDQLVL_DQDM_OBS_SELECT_3 + +#define LPDDR4__DENALI_PHY_802__PHY_WDQLVL_PERIODIC_OBS_SELECT_3_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_802__PHY_WDQLVL_PERIODIC_OBS_SELECT_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_802__PHY_WDQLVL_PERIODIC_OBS_SELECT_3_WIDTH 8U +#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_SELECT_3__REG DENALI_PHY_802 +#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_SELECT_3__FLD LPDDR4__DENALI_PHY_802__PHY_WDQLVL_PERIODIC_OBS_SELECT_3 + +#define LPDDR4__DENALI_PHY_802__SC_PHY_WDQLVL_CLR_PREV_RESULTS_3_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_802__SC_PHY_WDQLVL_CLR_PREV_RESULTS_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_802__SC_PHY_WDQLVL_CLR_PREV_RESULTS_3_WIDTH 1U +#define LPDDR4__DENALI_PHY_802__SC_PHY_WDQLVL_CLR_PREV_RESULTS_3_WOCLR 0U +#define LPDDR4__DENALI_PHY_802__SC_PHY_WDQLVL_CLR_PREV_RESULTS_3_WOSET 0U +#define LPDDR4__SC_PHY_WDQLVL_CLR_PREV_RESULTS_3__REG DENALI_PHY_802 +#define LPDDR4__SC_PHY_WDQLVL_CLR_PREV_RESULTS_3__FLD LPDDR4__DENALI_PHY_802__SC_PHY_WDQLVL_CLR_PREV_RESULTS_3 + +#define LPDDR4__DENALI_PHY_803_READ_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_803_WRITE_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_803__PHY_WDQLVL_DATADM_MASK_3_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_803__PHY_WDQLVL_DATADM_MASK_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_803__PHY_WDQLVL_DATADM_MASK_3_WIDTH 9U +#define LPDDR4__PHY_WDQLVL_DATADM_MASK_3__REG DENALI_PHY_803 +#define LPDDR4__PHY_WDQLVL_DATADM_MASK_3__FLD LPDDR4__DENALI_PHY_803__PHY_WDQLVL_DATADM_MASK_3 + +#define LPDDR4__DENALI_PHY_804_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_804_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_804__PHY_USER_PATT0_3_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_804__PHY_USER_PATT0_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_804__PHY_USER_PATT0_3_WIDTH 32U +#define LPDDR4__PHY_USER_PATT0_3__REG DENALI_PHY_804 +#define LPDDR4__PHY_USER_PATT0_3__FLD LPDDR4__DENALI_PHY_804__PHY_USER_PATT0_3 + +#define LPDDR4__DENALI_PHY_805_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_805_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_805__PHY_USER_PATT1_3_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_805__PHY_USER_PATT1_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_805__PHY_USER_PATT1_3_WIDTH 32U +#define LPDDR4__PHY_USER_PATT1_3__REG DENALI_PHY_805 +#define LPDDR4__PHY_USER_PATT1_3__FLD LPDDR4__DENALI_PHY_805__PHY_USER_PATT1_3 + +#define LPDDR4__DENALI_PHY_806_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_806_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_806__PHY_USER_PATT2_3_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_806__PHY_USER_PATT2_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_806__PHY_USER_PATT2_3_WIDTH 32U +#define LPDDR4__PHY_USER_PATT2_3__REG DENALI_PHY_806 +#define LPDDR4__PHY_USER_PATT2_3__FLD LPDDR4__DENALI_PHY_806__PHY_USER_PATT2_3 + +#define LPDDR4__DENALI_PHY_807_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_807_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_807__PHY_USER_PATT3_3_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_807__PHY_USER_PATT3_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_807__PHY_USER_PATT3_3_WIDTH 32U +#define LPDDR4__PHY_USER_PATT3_3__REG DENALI_PHY_807 +#define LPDDR4__PHY_USER_PATT3_3__FLD LPDDR4__DENALI_PHY_807__PHY_USER_PATT3_3 + +#define LPDDR4__DENALI_PHY_808_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PHY_808_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PHY_808__PHY_USER_PATT4_3_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_808__PHY_USER_PATT4_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_808__PHY_USER_PATT4_3_WIDTH 16U +#define LPDDR4__PHY_USER_PATT4_3__REG DENALI_PHY_808 +#define LPDDR4__PHY_USER_PATT4_3__FLD LPDDR4__DENALI_PHY_808__PHY_USER_PATT4_3 + +#define LPDDR4__DENALI_PHY_808__PHY_NTP_MULT_TRAIN_3_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_808__PHY_NTP_MULT_TRAIN_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_808__PHY_NTP_MULT_TRAIN_3_WIDTH 1U +#define LPDDR4__DENALI_PHY_808__PHY_NTP_MULT_TRAIN_3_WOCLR 0U +#define LPDDR4__DENALI_PHY_808__PHY_NTP_MULT_TRAIN_3_WOSET 0U +#define LPDDR4__PHY_NTP_MULT_TRAIN_3__REG DENALI_PHY_808 +#define LPDDR4__PHY_NTP_MULT_TRAIN_3__FLD LPDDR4__DENALI_PHY_808__PHY_NTP_MULT_TRAIN_3 + +#define LPDDR4__DENALI_PHY_809_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_809_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_809__PHY_NTP_EARLY_THRESHOLD_3_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_809__PHY_NTP_EARLY_THRESHOLD_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_809__PHY_NTP_EARLY_THRESHOLD_3_WIDTH 10U +#define LPDDR4__PHY_NTP_EARLY_THRESHOLD_3__REG DENALI_PHY_809 +#define LPDDR4__PHY_NTP_EARLY_THRESHOLD_3__FLD LPDDR4__DENALI_PHY_809__PHY_NTP_EARLY_THRESHOLD_3 + +#define LPDDR4__DENALI_PHY_809__PHY_NTP_PERIOD_THRESHOLD_3_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_809__PHY_NTP_PERIOD_THRESHOLD_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_809__PHY_NTP_PERIOD_THRESHOLD_3_WIDTH 10U +#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_3__REG DENALI_PHY_809 +#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_3__FLD LPDDR4__DENALI_PHY_809__PHY_NTP_PERIOD_THRESHOLD_3 + +#define LPDDR4__DENALI_PHY_810_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_810_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_810__PHY_NTP_PERIOD_THRESHOLD_MIN_3_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_810__PHY_NTP_PERIOD_THRESHOLD_MIN_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_810__PHY_NTP_PERIOD_THRESHOLD_MIN_3_WIDTH 10U +#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MIN_3__REG DENALI_PHY_810 +#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MIN_3__FLD LPDDR4__DENALI_PHY_810__PHY_NTP_PERIOD_THRESHOLD_MIN_3 + +#define LPDDR4__DENALI_PHY_810__PHY_NTP_PERIOD_THRESHOLD_MAX_3_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_810__PHY_NTP_PERIOD_THRESHOLD_MAX_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_810__PHY_NTP_PERIOD_THRESHOLD_MAX_3_WIDTH 10U +#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MAX_3__REG DENALI_PHY_810 +#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MAX_3__FLD LPDDR4__DENALI_PHY_810__PHY_NTP_PERIOD_THRESHOLD_MAX_3 + +#define LPDDR4__DENALI_PHY_811_READ_MASK 0x00FF0001U +#define LPDDR4__DENALI_PHY_811_WRITE_MASK 0x00FF0001U +#define LPDDR4__DENALI_PHY_811__PHY_CALVL_VREF_DRIVING_SLICE_3_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_811__PHY_CALVL_VREF_DRIVING_SLICE_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_811__PHY_CALVL_VREF_DRIVING_SLICE_3_WIDTH 1U +#define LPDDR4__DENALI_PHY_811__PHY_CALVL_VREF_DRIVING_SLICE_3_WOCLR 0U +#define LPDDR4__DENALI_PHY_811__PHY_CALVL_VREF_DRIVING_SLICE_3_WOSET 0U +#define LPDDR4__PHY_CALVL_VREF_DRIVING_SLICE_3__REG DENALI_PHY_811 +#define LPDDR4__PHY_CALVL_VREF_DRIVING_SLICE_3__FLD LPDDR4__DENALI_PHY_811__PHY_CALVL_VREF_DRIVING_SLICE_3 + +#define LPDDR4__DENALI_PHY_811__SC_PHY_MANUAL_CLEAR_3_MASK 0x00003F00U +#define LPDDR4__DENALI_PHY_811__SC_PHY_MANUAL_CLEAR_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_811__SC_PHY_MANUAL_CLEAR_3_WIDTH 6U +#define LPDDR4__SC_PHY_MANUAL_CLEAR_3__REG DENALI_PHY_811 +#define LPDDR4__SC_PHY_MANUAL_CLEAR_3__FLD LPDDR4__DENALI_PHY_811__SC_PHY_MANUAL_CLEAR_3 + +#define LPDDR4__DENALI_PHY_811__PHY_FIFO_PTR_OBS_3_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_811__PHY_FIFO_PTR_OBS_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_811__PHY_FIFO_PTR_OBS_3_WIDTH 8U +#define LPDDR4__PHY_FIFO_PTR_OBS_3__REG DENALI_PHY_811 +#define LPDDR4__PHY_FIFO_PTR_OBS_3__FLD LPDDR4__DENALI_PHY_811__PHY_FIFO_PTR_OBS_3 + +#define LPDDR4__DENALI_PHY_812_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_812_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_812__PHY_LPBK_RESULT_OBS_3_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_812__PHY_LPBK_RESULT_OBS_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_812__PHY_LPBK_RESULT_OBS_3_WIDTH 32U +#define LPDDR4__PHY_LPBK_RESULT_OBS_3__REG DENALI_PHY_812 +#define LPDDR4__PHY_LPBK_RESULT_OBS_3__FLD LPDDR4__DENALI_PHY_812__PHY_LPBK_RESULT_OBS_3 + +#define LPDDR4__DENALI_PHY_813_READ_MASK 0x07FFFFFFU +#define LPDDR4__DENALI_PHY_813_WRITE_MASK 0x07FFFFFFU +#define LPDDR4__DENALI_PHY_813__PHY_LPBK_ERROR_COUNT_OBS_3_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_813__PHY_LPBK_ERROR_COUNT_OBS_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_813__PHY_LPBK_ERROR_COUNT_OBS_3_WIDTH 16U +#define LPDDR4__PHY_LPBK_ERROR_COUNT_OBS_3__REG DENALI_PHY_813 +#define LPDDR4__PHY_LPBK_ERROR_COUNT_OBS_3__FLD LPDDR4__DENALI_PHY_813__PHY_LPBK_ERROR_COUNT_OBS_3 + +#define LPDDR4__DENALI_PHY_813__PHY_MASTER_DLY_LOCK_OBS_3_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_813__PHY_MASTER_DLY_LOCK_OBS_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_813__PHY_MASTER_DLY_LOCK_OBS_3_WIDTH 11U +#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_3__REG DENALI_PHY_813 +#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_3__FLD LPDDR4__DENALI_PHY_813__PHY_MASTER_DLY_LOCK_OBS_3 + +#define LPDDR4__DENALI_PHY_814_READ_MASK 0xFFFF7F7FU +#define LPDDR4__DENALI_PHY_814_WRITE_MASK 0xFFFF7F7FU +#define LPDDR4__DENALI_PHY_814__PHY_RDDQ_SLV_DLY_ENC_OBS_3_MASK 0x0000007FU +#define LPDDR4__DENALI_PHY_814__PHY_RDDQ_SLV_DLY_ENC_OBS_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_814__PHY_RDDQ_SLV_DLY_ENC_OBS_3_WIDTH 7U +#define LPDDR4__PHY_RDDQ_SLV_DLY_ENC_OBS_3__REG DENALI_PHY_814 +#define LPDDR4__PHY_RDDQ_SLV_DLY_ENC_OBS_3__FLD LPDDR4__DENALI_PHY_814__PHY_RDDQ_SLV_DLY_ENC_OBS_3 + +#define LPDDR4__DENALI_PHY_814__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_3_MASK 0x00007F00U +#define LPDDR4__DENALI_PHY_814__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_814__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_3_WIDTH 7U +#define LPDDR4__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_3__REG DENALI_PHY_814 +#define LPDDR4__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_3__FLD LPDDR4__DENALI_PHY_814__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_3 + +#define LPDDR4__DENALI_PHY_814__PHY_MEAS_DLY_STEP_VALUE_3_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_814__PHY_MEAS_DLY_STEP_VALUE_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_814__PHY_MEAS_DLY_STEP_VALUE_3_WIDTH 8U +#define LPDDR4__PHY_MEAS_DLY_STEP_VALUE_3__REG DENALI_PHY_814 +#define LPDDR4__PHY_MEAS_DLY_STEP_VALUE_3__FLD LPDDR4__DENALI_PHY_814__PHY_MEAS_DLY_STEP_VALUE_3 + +#define LPDDR4__DENALI_PHY_814__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_3_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_814__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_814__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_3_WIDTH 8U +#define LPDDR4__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_3__REG DENALI_PHY_814 +#define LPDDR4__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_3__FLD LPDDR4__DENALI_PHY_814__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_3 + +#define LPDDR4__DENALI_PHY_815_READ_MASK 0x7F07FFFFU +#define LPDDR4__DENALI_PHY_815_WRITE_MASK 0x7F07FFFFU +#define LPDDR4__DENALI_PHY_815__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_3_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_815__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_815__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_3_WIDTH 8U +#define LPDDR4__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_3__REG DENALI_PHY_815 +#define LPDDR4__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_3__FLD LPDDR4__DENALI_PHY_815__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_3 + +#define LPDDR4__DENALI_PHY_815__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_3_MASK 0x0007FF00U +#define LPDDR4__DENALI_PHY_815__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_815__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_3_WIDTH 11U +#define LPDDR4__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_3__REG DENALI_PHY_815 +#define LPDDR4__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_3__FLD LPDDR4__DENALI_PHY_815__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_3 + +#define LPDDR4__DENALI_PHY_815__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_3_MASK 0x7F000000U +#define LPDDR4__DENALI_PHY_815__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_815__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_3_WIDTH 7U +#define LPDDR4__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_3__REG DENALI_PHY_815 +#define LPDDR4__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_3__FLD LPDDR4__DENALI_PHY_815__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_3 + +#define LPDDR4__DENALI_PHY_816_READ_MASK 0x0007FFFFU +#define LPDDR4__DENALI_PHY_816_WRITE_MASK 0x0007FFFFU +#define LPDDR4__DENALI_PHY_816__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_3_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_816__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_816__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_3_WIDTH 8U +#define LPDDR4__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_3__REG DENALI_PHY_816 +#define LPDDR4__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_3__FLD LPDDR4__DENALI_PHY_816__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_3 + +#define LPDDR4__DENALI_PHY_816__PHY_WR_ADDER_SLV_DLY_ENC_OBS_3_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_816__PHY_WR_ADDER_SLV_DLY_ENC_OBS_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_816__PHY_WR_ADDER_SLV_DLY_ENC_OBS_3_WIDTH 8U +#define LPDDR4__PHY_WR_ADDER_SLV_DLY_ENC_OBS_3__REG DENALI_PHY_816 +#define LPDDR4__PHY_WR_ADDER_SLV_DLY_ENC_OBS_3__FLD LPDDR4__DENALI_PHY_816__PHY_WR_ADDER_SLV_DLY_ENC_OBS_3 + +#define LPDDR4__DENALI_PHY_816__PHY_WR_SHIFT_OBS_3_MASK 0x00070000U +#define LPDDR4__DENALI_PHY_816__PHY_WR_SHIFT_OBS_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_816__PHY_WR_SHIFT_OBS_3_WIDTH 3U +#define LPDDR4__PHY_WR_SHIFT_OBS_3__REG DENALI_PHY_816 +#define LPDDR4__PHY_WR_SHIFT_OBS_3__FLD LPDDR4__DENALI_PHY_816__PHY_WR_SHIFT_OBS_3 + +#define LPDDR4__DENALI_PHY_817_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_817_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_817__PHY_WRLVL_HARD0_DELAY_OBS_3_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_817__PHY_WRLVL_HARD0_DELAY_OBS_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_817__PHY_WRLVL_HARD0_DELAY_OBS_3_WIDTH 10U +#define LPDDR4__PHY_WRLVL_HARD0_DELAY_OBS_3__REG DENALI_PHY_817 +#define LPDDR4__PHY_WRLVL_HARD0_DELAY_OBS_3__FLD LPDDR4__DENALI_PHY_817__PHY_WRLVL_HARD0_DELAY_OBS_3 + +#define LPDDR4__DENALI_PHY_817__PHY_WRLVL_HARD1_DELAY_OBS_3_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_817__PHY_WRLVL_HARD1_DELAY_OBS_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_817__PHY_WRLVL_HARD1_DELAY_OBS_3_WIDTH 10U +#define LPDDR4__PHY_WRLVL_HARD1_DELAY_OBS_3__REG DENALI_PHY_817 +#define LPDDR4__PHY_WRLVL_HARD1_DELAY_OBS_3__FLD LPDDR4__DENALI_PHY_817__PHY_WRLVL_HARD1_DELAY_OBS_3 + +#define LPDDR4__DENALI_PHY_818_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PHY_818_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PHY_818__PHY_WRLVL_STATUS_OBS_3_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PHY_818__PHY_WRLVL_STATUS_OBS_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_818__PHY_WRLVL_STATUS_OBS_3_WIDTH 17U +#define LPDDR4__PHY_WRLVL_STATUS_OBS_3__REG DENALI_PHY_818 +#define LPDDR4__PHY_WRLVL_STATUS_OBS_3__FLD LPDDR4__DENALI_PHY_818__PHY_WRLVL_STATUS_OBS_3 + +#define LPDDR4__DENALI_PHY_819_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_819_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_819__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_3_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_819__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_819__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_3_WIDTH 10U +#define LPDDR4__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_3__REG DENALI_PHY_819 +#define LPDDR4__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_3__FLD LPDDR4__DENALI_PHY_819__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_3 + +#define LPDDR4__DENALI_PHY_819__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_3_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_819__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_819__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_3_WIDTH 10U +#define LPDDR4__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_3__REG DENALI_PHY_819 +#define LPDDR4__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_3__FLD LPDDR4__DENALI_PHY_819__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_3 + +#define LPDDR4__DENALI_PHY_820_READ_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_820_WRITE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_820__PHY_WRLVL_ERROR_OBS_3_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_820__PHY_WRLVL_ERROR_OBS_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_820__PHY_WRLVL_ERROR_OBS_3_WIDTH 16U +#define LPDDR4__PHY_WRLVL_ERROR_OBS_3__REG DENALI_PHY_820 +#define LPDDR4__PHY_WRLVL_ERROR_OBS_3__FLD LPDDR4__DENALI_PHY_820__PHY_WRLVL_ERROR_OBS_3 + +#define LPDDR4__DENALI_PHY_820__PHY_GTLVL_HARD0_DELAY_OBS_3_MASK 0x3FFF0000U +#define LPDDR4__DENALI_PHY_820__PHY_GTLVL_HARD0_DELAY_OBS_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_820__PHY_GTLVL_HARD0_DELAY_OBS_3_WIDTH 14U +#define LPDDR4__PHY_GTLVL_HARD0_DELAY_OBS_3__REG DENALI_PHY_820 +#define LPDDR4__PHY_GTLVL_HARD0_DELAY_OBS_3__FLD LPDDR4__DENALI_PHY_820__PHY_GTLVL_HARD0_DELAY_OBS_3 + +#define LPDDR4__DENALI_PHY_821_READ_MASK 0x00003FFFU +#define LPDDR4__DENALI_PHY_821_WRITE_MASK 0x00003FFFU +#define LPDDR4__DENALI_PHY_821__PHY_GTLVL_HARD1_DELAY_OBS_3_MASK 0x00003FFFU +#define LPDDR4__DENALI_PHY_821__PHY_GTLVL_HARD1_DELAY_OBS_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_821__PHY_GTLVL_HARD1_DELAY_OBS_3_WIDTH 14U +#define LPDDR4__PHY_GTLVL_HARD1_DELAY_OBS_3__REG DENALI_PHY_821 +#define LPDDR4__PHY_GTLVL_HARD1_DELAY_OBS_3__FLD LPDDR4__DENALI_PHY_821__PHY_GTLVL_HARD1_DELAY_OBS_3 + +#define LPDDR4__DENALI_PHY_822_READ_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_822_WRITE_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_822__PHY_GTLVL_STATUS_OBS_3_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_822__PHY_GTLVL_STATUS_OBS_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_822__PHY_GTLVL_STATUS_OBS_3_WIDTH 18U +#define LPDDR4__PHY_GTLVL_STATUS_OBS_3__REG DENALI_PHY_822 +#define LPDDR4__PHY_GTLVL_STATUS_OBS_3__FLD LPDDR4__DENALI_PHY_822__PHY_GTLVL_STATUS_OBS_3 + +#define LPDDR4__DENALI_PHY_823_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_823_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_823__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_3_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_823__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_823__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_3_WIDTH 10U +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_3__REG DENALI_PHY_823 +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_3__FLD LPDDR4__DENALI_PHY_823__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_3 + +#define LPDDR4__DENALI_PHY_823__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_3_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_823__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_823__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_3_WIDTH 10U +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_3__REG DENALI_PHY_823 +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_3__FLD LPDDR4__DENALI_PHY_823__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_3 + +#define LPDDR4__DENALI_PHY_824_READ_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_824_WRITE_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_824__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_3_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_824__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_824__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_3_WIDTH 2U +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_3__REG DENALI_PHY_824 +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_3__FLD LPDDR4__DENALI_PHY_824__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_3 + +#define LPDDR4__DENALI_PHY_825_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_825_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_825__PHY_RDLVL_STATUS_OBS_3_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_825__PHY_RDLVL_STATUS_OBS_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_825__PHY_RDLVL_STATUS_OBS_3_WIDTH 32U +#define LPDDR4__PHY_RDLVL_STATUS_OBS_3__REG DENALI_PHY_825 +#define LPDDR4__PHY_RDLVL_STATUS_OBS_3__FLD LPDDR4__DENALI_PHY_825__PHY_RDLVL_STATUS_OBS_3 + +#define LPDDR4__DENALI_PHY_826_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_826_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_826__PHY_RDLVL_PERIODIC_OBS_3_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_826__PHY_RDLVL_PERIODIC_OBS_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_826__PHY_RDLVL_PERIODIC_OBS_3_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PERIODIC_OBS_3__REG DENALI_PHY_826 +#define LPDDR4__PHY_RDLVL_PERIODIC_OBS_3__FLD LPDDR4__DENALI_PHY_826__PHY_RDLVL_PERIODIC_OBS_3 + +#define LPDDR4__DENALI_PHY_827_READ_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_827_WRITE_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_827__PHY_WDQLVL_DQDM_LE_DLY_OBS_3_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_827__PHY_WDQLVL_DQDM_LE_DLY_OBS_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_827__PHY_WDQLVL_DQDM_LE_DLY_OBS_3_WIDTH 11U +#define LPDDR4__PHY_WDQLVL_DQDM_LE_DLY_OBS_3__REG DENALI_PHY_827 +#define LPDDR4__PHY_WDQLVL_DQDM_LE_DLY_OBS_3__FLD LPDDR4__DENALI_PHY_827__PHY_WDQLVL_DQDM_LE_DLY_OBS_3 + +#define LPDDR4__DENALI_PHY_827__PHY_WDQLVL_DQDM_TE_DLY_OBS_3_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_827__PHY_WDQLVL_DQDM_TE_DLY_OBS_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_827__PHY_WDQLVL_DQDM_TE_DLY_OBS_3_WIDTH 11U +#define LPDDR4__PHY_WDQLVL_DQDM_TE_DLY_OBS_3__REG DENALI_PHY_827 +#define LPDDR4__PHY_WDQLVL_DQDM_TE_DLY_OBS_3__FLD LPDDR4__DENALI_PHY_827__PHY_WDQLVL_DQDM_TE_DLY_OBS_3 + +#define LPDDR4__DENALI_PHY_828_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_828_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_828__PHY_WDQLVL_STATUS_OBS_3_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_828__PHY_WDQLVL_STATUS_OBS_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_828__PHY_WDQLVL_STATUS_OBS_3_WIDTH 32U +#define LPDDR4__PHY_WDQLVL_STATUS_OBS_3__REG DENALI_PHY_828 +#define LPDDR4__PHY_WDQLVL_STATUS_OBS_3__FLD LPDDR4__DENALI_PHY_828__PHY_WDQLVL_STATUS_OBS_3 + +#define LPDDR4__DENALI_PHY_829_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_829_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_829__PHY_WDQLVL_PERIODIC_OBS_3_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_829__PHY_WDQLVL_PERIODIC_OBS_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_829__PHY_WDQLVL_PERIODIC_OBS_3_WIDTH 32U +#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_3__REG DENALI_PHY_829 +#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_3__FLD LPDDR4__DENALI_PHY_829__PHY_WDQLVL_PERIODIC_OBS_3 + +#define LPDDR4__DENALI_PHY_830_READ_MASK 0x7FFFFFFFU +#define LPDDR4__DENALI_PHY_830_WRITE_MASK 0x7FFFFFFFU +#define LPDDR4__DENALI_PHY_830__PHY_DDL_MODE_3_MASK 0x7FFFFFFFU +#define LPDDR4__DENALI_PHY_830__PHY_DDL_MODE_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_830__PHY_DDL_MODE_3_WIDTH 31U +#define LPDDR4__PHY_DDL_MODE_3__REG DENALI_PHY_830 +#define LPDDR4__PHY_DDL_MODE_3__FLD LPDDR4__DENALI_PHY_830__PHY_DDL_MODE_3 + +#define LPDDR4__DENALI_PHY_831_READ_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_831_WRITE_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_831__PHY_DDL_MASK_3_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_831__PHY_DDL_MASK_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_831__PHY_DDL_MASK_3_WIDTH 6U +#define LPDDR4__PHY_DDL_MASK_3__REG DENALI_PHY_831 +#define LPDDR4__PHY_DDL_MASK_3__FLD LPDDR4__DENALI_PHY_831__PHY_DDL_MASK_3 + +#define LPDDR4__DENALI_PHY_832_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_832_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_832__PHY_DDL_TEST_OBS_3_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_832__PHY_DDL_TEST_OBS_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_832__PHY_DDL_TEST_OBS_3_WIDTH 32U +#define LPDDR4__PHY_DDL_TEST_OBS_3__REG DENALI_PHY_832 +#define LPDDR4__PHY_DDL_TEST_OBS_3__FLD LPDDR4__DENALI_PHY_832__PHY_DDL_TEST_OBS_3 + +#define LPDDR4__DENALI_PHY_833_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_833_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_833__PHY_DDL_TEST_MSTR_DLY_OBS_3_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_833__PHY_DDL_TEST_MSTR_DLY_OBS_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_833__PHY_DDL_TEST_MSTR_DLY_OBS_3_WIDTH 32U +#define LPDDR4__PHY_DDL_TEST_MSTR_DLY_OBS_3__REG DENALI_PHY_833 +#define LPDDR4__PHY_DDL_TEST_MSTR_DLY_OBS_3__FLD LPDDR4__DENALI_PHY_833__PHY_DDL_TEST_MSTR_DLY_OBS_3 + +#define LPDDR4__DENALI_PHY_834_READ_MASK 0x010001FFU +#define LPDDR4__DENALI_PHY_834_WRITE_MASK 0x010001FFU +#define LPDDR4__DENALI_PHY_834__PHY_DDL_TRACK_UPD_THRESHOLD_3_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_834__PHY_DDL_TRACK_UPD_THRESHOLD_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_834__PHY_DDL_TRACK_UPD_THRESHOLD_3_WIDTH 8U +#define LPDDR4__PHY_DDL_TRACK_UPD_THRESHOLD_3__REG DENALI_PHY_834 +#define LPDDR4__PHY_DDL_TRACK_UPD_THRESHOLD_3__FLD LPDDR4__DENALI_PHY_834__PHY_DDL_TRACK_UPD_THRESHOLD_3 + +#define LPDDR4__DENALI_PHY_834__PHY_LP4_WDQS_OE_EXTEND_3_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_834__PHY_LP4_WDQS_OE_EXTEND_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_834__PHY_LP4_WDQS_OE_EXTEND_3_WIDTH 1U +#define LPDDR4__DENALI_PHY_834__PHY_LP4_WDQS_OE_EXTEND_3_WOCLR 0U +#define LPDDR4__DENALI_PHY_834__PHY_LP4_WDQS_OE_EXTEND_3_WOSET 0U +#define LPDDR4__PHY_LP4_WDQS_OE_EXTEND_3__REG DENALI_PHY_834 +#define LPDDR4__PHY_LP4_WDQS_OE_EXTEND_3__FLD LPDDR4__DENALI_PHY_834__PHY_LP4_WDQS_OE_EXTEND_3 + +#define LPDDR4__DENALI_PHY_834__SC_PHY_RX_CAL_START_3_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_834__SC_PHY_RX_CAL_START_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_834__SC_PHY_RX_CAL_START_3_WIDTH 1U +#define LPDDR4__DENALI_PHY_834__SC_PHY_RX_CAL_START_3_WOCLR 0U +#define LPDDR4__DENALI_PHY_834__SC_PHY_RX_CAL_START_3_WOSET 0U +#define LPDDR4__SC_PHY_RX_CAL_START_3__REG DENALI_PHY_834 +#define LPDDR4__SC_PHY_RX_CAL_START_3__FLD LPDDR4__DENALI_PHY_834__SC_PHY_RX_CAL_START_3 + +#define LPDDR4__DENALI_PHY_834__PHY_RX_CAL_OVERRIDE_3_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_834__PHY_RX_CAL_OVERRIDE_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_834__PHY_RX_CAL_OVERRIDE_3_WIDTH 1U +#define LPDDR4__DENALI_PHY_834__PHY_RX_CAL_OVERRIDE_3_WOCLR 0U +#define LPDDR4__DENALI_PHY_834__PHY_RX_CAL_OVERRIDE_3_WOSET 0U +#define LPDDR4__PHY_RX_CAL_OVERRIDE_3__REG DENALI_PHY_834 +#define LPDDR4__PHY_RX_CAL_OVERRIDE_3__FLD LPDDR4__DENALI_PHY_834__PHY_RX_CAL_OVERRIDE_3 + +#define LPDDR4__DENALI_PHY_835_READ_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_835_WRITE_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_835__PHY_RX_CAL_SAMPLE_WAIT_3_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_835__PHY_RX_CAL_SAMPLE_WAIT_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_835__PHY_RX_CAL_SAMPLE_WAIT_3_WIDTH 8U +#define LPDDR4__PHY_RX_CAL_SAMPLE_WAIT_3__REG DENALI_PHY_835 +#define LPDDR4__PHY_RX_CAL_SAMPLE_WAIT_3__FLD LPDDR4__DENALI_PHY_835__PHY_RX_CAL_SAMPLE_WAIT_3 + +#define LPDDR4__DENALI_PHY_835__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_3_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_835__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_835__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_3_WIDTH 1U +#define LPDDR4__DENALI_PHY_835__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_3_WOCLR 0U +#define LPDDR4__DENALI_PHY_835__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_3_WOSET 0U +#define LPDDR4__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_3__REG DENALI_PHY_835 +#define LPDDR4__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_3__FLD LPDDR4__DENALI_PHY_835__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_3 + +#define LPDDR4__DENALI_PHY_835__PHY_RX_CAL_DQ0_3_MASK 0x01FF0000U +#define LPDDR4__DENALI_PHY_835__PHY_RX_CAL_DQ0_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_835__PHY_RX_CAL_DQ0_3_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQ0_3__REG DENALI_PHY_835 +#define LPDDR4__PHY_RX_CAL_DQ0_3__FLD LPDDR4__DENALI_PHY_835__PHY_RX_CAL_DQ0_3 + +#define LPDDR4__DENALI_PHY_836_READ_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_836_WRITE_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_836__PHY_RX_CAL_DQ1_3_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_836__PHY_RX_CAL_DQ1_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_836__PHY_RX_CAL_DQ1_3_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQ1_3__REG DENALI_PHY_836 +#define LPDDR4__PHY_RX_CAL_DQ1_3__FLD LPDDR4__DENALI_PHY_836__PHY_RX_CAL_DQ1_3 + +#define LPDDR4__DENALI_PHY_836__PHY_RX_CAL_DQ2_3_MASK 0x01FF0000U +#define LPDDR4__DENALI_PHY_836__PHY_RX_CAL_DQ2_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_836__PHY_RX_CAL_DQ2_3_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQ2_3__REG DENALI_PHY_836 +#define LPDDR4__PHY_RX_CAL_DQ2_3__FLD LPDDR4__DENALI_PHY_836__PHY_RX_CAL_DQ2_3 + +#define LPDDR4__DENALI_PHY_837_READ_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_837_WRITE_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_837__PHY_RX_CAL_DQ3_3_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_837__PHY_RX_CAL_DQ3_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_837__PHY_RX_CAL_DQ3_3_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQ3_3__REG DENALI_PHY_837 +#define LPDDR4__PHY_RX_CAL_DQ3_3__FLD LPDDR4__DENALI_PHY_837__PHY_RX_CAL_DQ3_3 + +#define LPDDR4__DENALI_PHY_837__PHY_RX_CAL_DQ4_3_MASK 0x01FF0000U +#define LPDDR4__DENALI_PHY_837__PHY_RX_CAL_DQ4_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_837__PHY_RX_CAL_DQ4_3_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQ4_3__REG DENALI_PHY_837 +#define LPDDR4__PHY_RX_CAL_DQ4_3__FLD LPDDR4__DENALI_PHY_837__PHY_RX_CAL_DQ4_3 + +#define LPDDR4__DENALI_PHY_838_READ_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_838_WRITE_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_838__PHY_RX_CAL_DQ5_3_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_838__PHY_RX_CAL_DQ5_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_838__PHY_RX_CAL_DQ5_3_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQ5_3__REG DENALI_PHY_838 +#define LPDDR4__PHY_RX_CAL_DQ5_3__FLD LPDDR4__DENALI_PHY_838__PHY_RX_CAL_DQ5_3 + +#define LPDDR4__DENALI_PHY_838__PHY_RX_CAL_DQ6_3_MASK 0x01FF0000U +#define LPDDR4__DENALI_PHY_838__PHY_RX_CAL_DQ6_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_838__PHY_RX_CAL_DQ6_3_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQ6_3__REG DENALI_PHY_838 +#define LPDDR4__PHY_RX_CAL_DQ6_3__FLD LPDDR4__DENALI_PHY_838__PHY_RX_CAL_DQ6_3 + +#define LPDDR4__DENALI_PHY_839_READ_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_839_WRITE_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_839__PHY_RX_CAL_DQ7_3_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_839__PHY_RX_CAL_DQ7_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_839__PHY_RX_CAL_DQ7_3_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQ7_3__REG DENALI_PHY_839 +#define LPDDR4__PHY_RX_CAL_DQ7_3__FLD LPDDR4__DENALI_PHY_839__PHY_RX_CAL_DQ7_3 + +#define LPDDR4__DENALI_PHY_840_READ_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_840_WRITE_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_840__PHY_RX_CAL_DM_3_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_840__PHY_RX_CAL_DM_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_840__PHY_RX_CAL_DM_3_WIDTH 18U +#define LPDDR4__PHY_RX_CAL_DM_3__REG DENALI_PHY_840 +#define LPDDR4__PHY_RX_CAL_DM_3__FLD LPDDR4__DENALI_PHY_840__PHY_RX_CAL_DM_3 + +#define LPDDR4__DENALI_PHY_841_READ_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_841_WRITE_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_841__PHY_RX_CAL_DQS_3_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_841__PHY_RX_CAL_DQS_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_841__PHY_RX_CAL_DQS_3_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQS_3__REG DENALI_PHY_841 +#define LPDDR4__PHY_RX_CAL_DQS_3__FLD LPDDR4__DENALI_PHY_841__PHY_RX_CAL_DQS_3 + +#define LPDDR4__DENALI_PHY_841__PHY_RX_CAL_FDBK_3_MASK 0x01FF0000U +#define LPDDR4__DENALI_PHY_841__PHY_RX_CAL_FDBK_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_841__PHY_RX_CAL_FDBK_3_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_FDBK_3__REG DENALI_PHY_841 +#define LPDDR4__PHY_RX_CAL_FDBK_3__FLD LPDDR4__DENALI_PHY_841__PHY_RX_CAL_FDBK_3 + +#define LPDDR4__DENALI_PHY_842_READ_MASK 0x01FF07FFU +#define LPDDR4__DENALI_PHY_842_WRITE_MASK 0x01FF07FFU +#define LPDDR4__DENALI_PHY_842__PHY_RX_CAL_OBS_3_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_842__PHY_RX_CAL_OBS_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_842__PHY_RX_CAL_OBS_3_WIDTH 11U +#define LPDDR4__PHY_RX_CAL_OBS_3__REG DENALI_PHY_842 +#define LPDDR4__PHY_RX_CAL_OBS_3__FLD LPDDR4__DENALI_PHY_842__PHY_RX_CAL_OBS_3 + +#define LPDDR4__DENALI_PHY_842__PHY_RX_CAL_LOCK_OBS_3_MASK 0x01FF0000U +#define LPDDR4__DENALI_PHY_842__PHY_RX_CAL_LOCK_OBS_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_842__PHY_RX_CAL_LOCK_OBS_3_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_LOCK_OBS_3__REG DENALI_PHY_842 +#define LPDDR4__PHY_RX_CAL_LOCK_OBS_3__FLD LPDDR4__DENALI_PHY_842__PHY_RX_CAL_LOCK_OBS_3 + +#define LPDDR4__DENALI_PHY_843_READ_MASK 0x017F7F01U +#define LPDDR4__DENALI_PHY_843_WRITE_MASK 0x017F7F01U +#define LPDDR4__DENALI_PHY_843__PHY_RX_CAL_DISABLE_3_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_843__PHY_RX_CAL_DISABLE_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_843__PHY_RX_CAL_DISABLE_3_WIDTH 1U +#define LPDDR4__DENALI_PHY_843__PHY_RX_CAL_DISABLE_3_WOCLR 0U +#define LPDDR4__DENALI_PHY_843__PHY_RX_CAL_DISABLE_3_WOSET 0U +#define LPDDR4__PHY_RX_CAL_DISABLE_3__REG DENALI_PHY_843 +#define LPDDR4__PHY_RX_CAL_DISABLE_3__FLD LPDDR4__DENALI_PHY_843__PHY_RX_CAL_DISABLE_3 + +#define LPDDR4__DENALI_PHY_843__PHY_RX_CAL_SE_ADJUST_3_MASK 0x00007F00U +#define LPDDR4__DENALI_PHY_843__PHY_RX_CAL_SE_ADJUST_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_843__PHY_RX_CAL_SE_ADJUST_3_WIDTH 7U +#define LPDDR4__PHY_RX_CAL_SE_ADJUST_3__REG DENALI_PHY_843 +#define LPDDR4__PHY_RX_CAL_SE_ADJUST_3__FLD LPDDR4__DENALI_PHY_843__PHY_RX_CAL_SE_ADJUST_3 + +#define LPDDR4__DENALI_PHY_843__PHY_RX_CAL_DIFF_ADJUST_3_MASK 0x007F0000U +#define LPDDR4__DENALI_PHY_843__PHY_RX_CAL_DIFF_ADJUST_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_843__PHY_RX_CAL_DIFF_ADJUST_3_WIDTH 7U +#define LPDDR4__PHY_RX_CAL_DIFF_ADJUST_3__REG DENALI_PHY_843 +#define LPDDR4__PHY_RX_CAL_DIFF_ADJUST_3__FLD LPDDR4__DENALI_PHY_843__PHY_RX_CAL_DIFF_ADJUST_3 + +#define LPDDR4__DENALI_PHY_843__PHY_RX_CAL_COMP_VAL_3_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_843__PHY_RX_CAL_COMP_VAL_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_843__PHY_RX_CAL_COMP_VAL_3_WIDTH 1U +#define LPDDR4__DENALI_PHY_843__PHY_RX_CAL_COMP_VAL_3_WOCLR 0U +#define LPDDR4__DENALI_PHY_843__PHY_RX_CAL_COMP_VAL_3_WOSET 0U +#define LPDDR4__PHY_RX_CAL_COMP_VAL_3__REG DENALI_PHY_843 +#define LPDDR4__PHY_RX_CAL_COMP_VAL_3__FLD LPDDR4__DENALI_PHY_843__PHY_RX_CAL_COMP_VAL_3 + +#define LPDDR4__DENALI_PHY_844_READ_MASK 0x07FF0FFFU +#define LPDDR4__DENALI_PHY_844_WRITE_MASK 0x07FF0FFFU +#define LPDDR4__DENALI_PHY_844__PHY_RX_CAL_INDEX_MASK_3_MASK 0x00000FFFU +#define LPDDR4__DENALI_PHY_844__PHY_RX_CAL_INDEX_MASK_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_844__PHY_RX_CAL_INDEX_MASK_3_WIDTH 12U +#define LPDDR4__PHY_RX_CAL_INDEX_MASK_3__REG DENALI_PHY_844 +#define LPDDR4__PHY_RX_CAL_INDEX_MASK_3__FLD LPDDR4__DENALI_PHY_844__PHY_RX_CAL_INDEX_MASK_3 + +#define LPDDR4__DENALI_PHY_844__PHY_PAD_RX_BIAS_EN_3_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_844__PHY_PAD_RX_BIAS_EN_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_844__PHY_PAD_RX_BIAS_EN_3_WIDTH 11U +#define LPDDR4__PHY_PAD_RX_BIAS_EN_3__REG DENALI_PHY_844 +#define LPDDR4__PHY_PAD_RX_BIAS_EN_3__FLD LPDDR4__DENALI_PHY_844__PHY_PAD_RX_BIAS_EN_3 + +#define LPDDR4__DENALI_PHY_845_READ_MASK 0x03FFFF1FU +#define LPDDR4__DENALI_PHY_845_WRITE_MASK 0x03FFFF1FU +#define LPDDR4__DENALI_PHY_845__PHY_STATIC_TOG_DISABLE_3_MASK 0x0000001FU +#define LPDDR4__DENALI_PHY_845__PHY_STATIC_TOG_DISABLE_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_845__PHY_STATIC_TOG_DISABLE_3_WIDTH 5U +#define LPDDR4__PHY_STATIC_TOG_DISABLE_3__REG DENALI_PHY_845 +#define LPDDR4__PHY_STATIC_TOG_DISABLE_3__FLD LPDDR4__DENALI_PHY_845__PHY_STATIC_TOG_DISABLE_3 + +#define LPDDR4__DENALI_PHY_845__PHY_DATA_DC_CAL_SAMPLE_WAIT_3_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_845__PHY_DATA_DC_CAL_SAMPLE_WAIT_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_845__PHY_DATA_DC_CAL_SAMPLE_WAIT_3_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_CAL_SAMPLE_WAIT_3__REG DENALI_PHY_845 +#define LPDDR4__PHY_DATA_DC_CAL_SAMPLE_WAIT_3__FLD LPDDR4__DENALI_PHY_845__PHY_DATA_DC_CAL_SAMPLE_WAIT_3 + +#define LPDDR4__DENALI_PHY_845__PHY_DATA_DC_CAL_TIMEOUT_3_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_845__PHY_DATA_DC_CAL_TIMEOUT_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_845__PHY_DATA_DC_CAL_TIMEOUT_3_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_CAL_TIMEOUT_3__REG DENALI_PHY_845 +#define LPDDR4__PHY_DATA_DC_CAL_TIMEOUT_3__FLD LPDDR4__DENALI_PHY_845__PHY_DATA_DC_CAL_TIMEOUT_3 + +#define LPDDR4__DENALI_PHY_845__PHY_DATA_DC_WEIGHT_3_MASK 0x03000000U +#define LPDDR4__DENALI_PHY_845__PHY_DATA_DC_WEIGHT_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_845__PHY_DATA_DC_WEIGHT_3_WIDTH 2U +#define LPDDR4__PHY_DATA_DC_WEIGHT_3__REG DENALI_PHY_845 +#define LPDDR4__PHY_DATA_DC_WEIGHT_3__FLD LPDDR4__DENALI_PHY_845__PHY_DATA_DC_WEIGHT_3 + +#define LPDDR4__DENALI_PHY_846_READ_MASK 0x01FFFF3FU +#define LPDDR4__DENALI_PHY_846_WRITE_MASK 0x01FFFF3FU +#define LPDDR4__DENALI_PHY_846__PHY_DATA_DC_ADJUST_START_3_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_846__PHY_DATA_DC_ADJUST_START_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_846__PHY_DATA_DC_ADJUST_START_3_WIDTH 6U +#define LPDDR4__PHY_DATA_DC_ADJUST_START_3__REG DENALI_PHY_846 +#define LPDDR4__PHY_DATA_DC_ADJUST_START_3__FLD LPDDR4__DENALI_PHY_846__PHY_DATA_DC_ADJUST_START_3 + +#define LPDDR4__DENALI_PHY_846__PHY_DATA_DC_ADJUST_SAMPLE_CNT_3_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_846__PHY_DATA_DC_ADJUST_SAMPLE_CNT_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_846__PHY_DATA_DC_ADJUST_SAMPLE_CNT_3_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_ADJUST_SAMPLE_CNT_3__REG DENALI_PHY_846 +#define LPDDR4__PHY_DATA_DC_ADJUST_SAMPLE_CNT_3__FLD LPDDR4__DENALI_PHY_846__PHY_DATA_DC_ADJUST_SAMPLE_CNT_3 + +#define LPDDR4__DENALI_PHY_846__PHY_DATA_DC_ADJUST_THRSHLD_3_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_846__PHY_DATA_DC_ADJUST_THRSHLD_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_846__PHY_DATA_DC_ADJUST_THRSHLD_3_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_ADJUST_THRSHLD_3__REG DENALI_PHY_846 +#define LPDDR4__PHY_DATA_DC_ADJUST_THRSHLD_3__FLD LPDDR4__DENALI_PHY_846__PHY_DATA_DC_ADJUST_THRSHLD_3 + +#define LPDDR4__DENALI_PHY_846__PHY_DATA_DC_ADJUST_DIRECT_3_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_846__PHY_DATA_DC_ADJUST_DIRECT_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_846__PHY_DATA_DC_ADJUST_DIRECT_3_WIDTH 1U +#define LPDDR4__DENALI_PHY_846__PHY_DATA_DC_ADJUST_DIRECT_3_WOCLR 0U +#define LPDDR4__DENALI_PHY_846__PHY_DATA_DC_ADJUST_DIRECT_3_WOSET 0U +#define LPDDR4__PHY_DATA_DC_ADJUST_DIRECT_3__REG DENALI_PHY_846 +#define LPDDR4__PHY_DATA_DC_ADJUST_DIRECT_3__FLD LPDDR4__DENALI_PHY_846__PHY_DATA_DC_ADJUST_DIRECT_3 + +#define LPDDR4__DENALI_PHY_847_READ_MASK 0x07030101U +#define LPDDR4__DENALI_PHY_847_WRITE_MASK 0x07030101U +#define LPDDR4__DENALI_PHY_847__PHY_DATA_DC_CAL_POLARITY_3_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_847__PHY_DATA_DC_CAL_POLARITY_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_847__PHY_DATA_DC_CAL_POLARITY_3_WIDTH 1U +#define LPDDR4__DENALI_PHY_847__PHY_DATA_DC_CAL_POLARITY_3_WOCLR 0U +#define LPDDR4__DENALI_PHY_847__PHY_DATA_DC_CAL_POLARITY_3_WOSET 0U +#define LPDDR4__PHY_DATA_DC_CAL_POLARITY_3__REG DENALI_PHY_847 +#define LPDDR4__PHY_DATA_DC_CAL_POLARITY_3__FLD LPDDR4__DENALI_PHY_847__PHY_DATA_DC_CAL_POLARITY_3 + +#define LPDDR4__DENALI_PHY_847__PHY_DATA_DC_CAL_START_3_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_847__PHY_DATA_DC_CAL_START_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_847__PHY_DATA_DC_CAL_START_3_WIDTH 1U +#define LPDDR4__DENALI_PHY_847__PHY_DATA_DC_CAL_START_3_WOCLR 0U +#define LPDDR4__DENALI_PHY_847__PHY_DATA_DC_CAL_START_3_WOSET 0U +#define LPDDR4__PHY_DATA_DC_CAL_START_3__REG DENALI_PHY_847 +#define LPDDR4__PHY_DATA_DC_CAL_START_3__FLD LPDDR4__DENALI_PHY_847__PHY_DATA_DC_CAL_START_3 + +#define LPDDR4__DENALI_PHY_847__PHY_DATA_DC_SW_RANK_3_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_847__PHY_DATA_DC_SW_RANK_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_847__PHY_DATA_DC_SW_RANK_3_WIDTH 2U +#define LPDDR4__PHY_DATA_DC_SW_RANK_3__REG DENALI_PHY_847 +#define LPDDR4__PHY_DATA_DC_SW_RANK_3__FLD LPDDR4__DENALI_PHY_847__PHY_DATA_DC_SW_RANK_3 + +#define LPDDR4__DENALI_PHY_847__PHY_FDBK_PWR_CTRL_3_MASK 0x07000000U +#define LPDDR4__DENALI_PHY_847__PHY_FDBK_PWR_CTRL_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_847__PHY_FDBK_PWR_CTRL_3_WIDTH 3U +#define LPDDR4__PHY_FDBK_PWR_CTRL_3__REG DENALI_PHY_847 +#define LPDDR4__PHY_FDBK_PWR_CTRL_3__FLD LPDDR4__DENALI_PHY_847__PHY_FDBK_PWR_CTRL_3 + +#define LPDDR4__DENALI_PHY_848_READ_MASK 0x01010101U +#define LPDDR4__DENALI_PHY_848_WRITE_MASK 0x01010101U +#define LPDDR4__DENALI_PHY_848__PHY_SLV_DLY_CTRL_GATE_DISABLE_3_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_848__PHY_SLV_DLY_CTRL_GATE_DISABLE_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_848__PHY_SLV_DLY_CTRL_GATE_DISABLE_3_WIDTH 1U +#define LPDDR4__DENALI_PHY_848__PHY_SLV_DLY_CTRL_GATE_DISABLE_3_WOCLR 0U +#define LPDDR4__DENALI_PHY_848__PHY_SLV_DLY_CTRL_GATE_DISABLE_3_WOSET 0U +#define LPDDR4__PHY_SLV_DLY_CTRL_GATE_DISABLE_3__REG DENALI_PHY_848 +#define LPDDR4__PHY_SLV_DLY_CTRL_GATE_DISABLE_3__FLD LPDDR4__DENALI_PHY_848__PHY_SLV_DLY_CTRL_GATE_DISABLE_3 + +#define LPDDR4__DENALI_PHY_848__PHY_RDPATH_GATE_DISABLE_3_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_848__PHY_RDPATH_GATE_DISABLE_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_848__PHY_RDPATH_GATE_DISABLE_3_WIDTH 1U +#define LPDDR4__DENALI_PHY_848__PHY_RDPATH_GATE_DISABLE_3_WOCLR 0U +#define LPDDR4__DENALI_PHY_848__PHY_RDPATH_GATE_DISABLE_3_WOSET 0U +#define LPDDR4__PHY_RDPATH_GATE_DISABLE_3__REG DENALI_PHY_848 +#define LPDDR4__PHY_RDPATH_GATE_DISABLE_3__FLD LPDDR4__DENALI_PHY_848__PHY_RDPATH_GATE_DISABLE_3 + +#define LPDDR4__DENALI_PHY_848__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_3_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_848__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_848__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_3_WIDTH 1U +#define LPDDR4__DENALI_PHY_848__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_3_WOCLR 0U +#define LPDDR4__DENALI_PHY_848__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_3_WOSET 0U +#define LPDDR4__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_3__REG DENALI_PHY_848 +#define LPDDR4__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_3__FLD LPDDR4__DENALI_PHY_848__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_3 + +#define LPDDR4__DENALI_PHY_848__PHY_SLICE_PWR_RDC_DISABLE_3_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_848__PHY_SLICE_PWR_RDC_DISABLE_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_848__PHY_SLICE_PWR_RDC_DISABLE_3_WIDTH 1U +#define LPDDR4__DENALI_PHY_848__PHY_SLICE_PWR_RDC_DISABLE_3_WOCLR 0U +#define LPDDR4__DENALI_PHY_848__PHY_SLICE_PWR_RDC_DISABLE_3_WOSET 0U +#define LPDDR4__PHY_SLICE_PWR_RDC_DISABLE_3__REG DENALI_PHY_848 +#define LPDDR4__PHY_SLICE_PWR_RDC_DISABLE_3__FLD LPDDR4__DENALI_PHY_848__PHY_SLICE_PWR_RDC_DISABLE_3 + +#define LPDDR4__DENALI_PHY_849_READ_MASK 0x3FFF07FFU +#define LPDDR4__DENALI_PHY_849_WRITE_MASK 0x3FFF07FFU +#define LPDDR4__DENALI_PHY_849__PHY_PARITY_ERROR_REGIF_3_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_849__PHY_PARITY_ERROR_REGIF_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_849__PHY_PARITY_ERROR_REGIF_3_WIDTH 11U +#define LPDDR4__PHY_PARITY_ERROR_REGIF_3__REG DENALI_PHY_849 +#define LPDDR4__PHY_PARITY_ERROR_REGIF_3__FLD LPDDR4__DENALI_PHY_849__PHY_PARITY_ERROR_REGIF_3 + +#define LPDDR4__DENALI_PHY_849__PHY_DS_FSM_ERROR_INFO_3_MASK 0x3FFF0000U +#define LPDDR4__DENALI_PHY_849__PHY_DS_FSM_ERROR_INFO_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_849__PHY_DS_FSM_ERROR_INFO_3_WIDTH 14U +#define LPDDR4__PHY_DS_FSM_ERROR_INFO_3__REG DENALI_PHY_849 +#define LPDDR4__PHY_DS_FSM_ERROR_INFO_3__FLD LPDDR4__DENALI_PHY_849__PHY_DS_FSM_ERROR_INFO_3 + +#define LPDDR4__DENALI_PHY_850_READ_MASK 0x00003FFFU +#define LPDDR4__DENALI_PHY_850_WRITE_MASK 0x00003FFFU +#define LPDDR4__DENALI_PHY_850__PHY_DS_FSM_ERROR_INFO_MASK_3_MASK 0x00003FFFU +#define LPDDR4__DENALI_PHY_850__PHY_DS_FSM_ERROR_INFO_MASK_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_850__PHY_DS_FSM_ERROR_INFO_MASK_3_WIDTH 14U +#define LPDDR4__PHY_DS_FSM_ERROR_INFO_MASK_3__REG DENALI_PHY_850 +#define LPDDR4__PHY_DS_FSM_ERROR_INFO_MASK_3__FLD LPDDR4__DENALI_PHY_850__PHY_DS_FSM_ERROR_INFO_MASK_3 + +#define LPDDR4__DENALI_PHY_850__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_3_MASK 0x3FFF0000U +#define LPDDR4__DENALI_PHY_850__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_850__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_3_WIDTH 14U +#define LPDDR4__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_3__REG DENALI_PHY_850 +#define LPDDR4__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_3__FLD LPDDR4__DENALI_PHY_850__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_3 + +#define LPDDR4__DENALI_PHY_851_READ_MASK 0x00001F1FU +#define LPDDR4__DENALI_PHY_851_WRITE_MASK 0x00001F1FU +#define LPDDR4__DENALI_PHY_851__PHY_DS_TRAIN_CALIB_ERROR_INFO_3_MASK 0x0000001FU +#define LPDDR4__DENALI_PHY_851__PHY_DS_TRAIN_CALIB_ERROR_INFO_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_851__PHY_DS_TRAIN_CALIB_ERROR_INFO_3_WIDTH 5U +#define LPDDR4__PHY_DS_TRAIN_CALIB_ERROR_INFO_3__REG DENALI_PHY_851 +#define LPDDR4__PHY_DS_TRAIN_CALIB_ERROR_INFO_3__FLD LPDDR4__DENALI_PHY_851__PHY_DS_TRAIN_CALIB_ERROR_INFO_3 + +#define LPDDR4__DENALI_PHY_851__PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_3_MASK 0x00001F00U +#define LPDDR4__DENALI_PHY_851__PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_851__PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_3_WIDTH 5U +#define LPDDR4__PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_3__REG DENALI_PHY_851 +#define LPDDR4__PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_3__FLD LPDDR4__DENALI_PHY_851__PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_3 + +#define LPDDR4__DENALI_PHY_851__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_3_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_851__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_851__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_3_WIDTH 5U +#define LPDDR4__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_3__REG DENALI_PHY_851 +#define LPDDR4__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_3__FLD LPDDR4__DENALI_PHY_851__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_3 + +#define LPDDR4__DENALI_PHY_852_READ_MASK 0x07FFFF07U +#define LPDDR4__DENALI_PHY_852_WRITE_MASK 0x07FFFF07U +#define LPDDR4__DENALI_PHY_852__PHY_DQ_TSEL_ENABLE_3_MASK 0x00000007U +#define LPDDR4__DENALI_PHY_852__PHY_DQ_TSEL_ENABLE_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_852__PHY_DQ_TSEL_ENABLE_3_WIDTH 3U +#define LPDDR4__PHY_DQ_TSEL_ENABLE_3__REG DENALI_PHY_852 +#define LPDDR4__PHY_DQ_TSEL_ENABLE_3__FLD LPDDR4__DENALI_PHY_852__PHY_DQ_TSEL_ENABLE_3 + +#define LPDDR4__DENALI_PHY_852__PHY_DQ_TSEL_SELECT_3_MASK 0x00FFFF00U +#define LPDDR4__DENALI_PHY_852__PHY_DQ_TSEL_SELECT_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_852__PHY_DQ_TSEL_SELECT_3_WIDTH 16U +#define LPDDR4__PHY_DQ_TSEL_SELECT_3__REG DENALI_PHY_852 +#define LPDDR4__PHY_DQ_TSEL_SELECT_3__FLD LPDDR4__DENALI_PHY_852__PHY_DQ_TSEL_SELECT_3 + +#define LPDDR4__DENALI_PHY_852__PHY_DQS_TSEL_ENABLE_3_MASK 0x07000000U +#define LPDDR4__DENALI_PHY_852__PHY_DQS_TSEL_ENABLE_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_852__PHY_DQS_TSEL_ENABLE_3_WIDTH 3U +#define LPDDR4__PHY_DQS_TSEL_ENABLE_3__REG DENALI_PHY_852 +#define LPDDR4__PHY_DQS_TSEL_ENABLE_3__FLD LPDDR4__DENALI_PHY_852__PHY_DQS_TSEL_ENABLE_3 + +#define LPDDR4__DENALI_PHY_853_READ_MASK 0x7F03FFFFU +#define LPDDR4__DENALI_PHY_853_WRITE_MASK 0x7F03FFFFU +#define LPDDR4__DENALI_PHY_853__PHY_DQS_TSEL_SELECT_3_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_853__PHY_DQS_TSEL_SELECT_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_853__PHY_DQS_TSEL_SELECT_3_WIDTH 16U +#define LPDDR4__PHY_DQS_TSEL_SELECT_3__REG DENALI_PHY_853 +#define LPDDR4__PHY_DQS_TSEL_SELECT_3__FLD LPDDR4__DENALI_PHY_853__PHY_DQS_TSEL_SELECT_3 + +#define LPDDR4__DENALI_PHY_853__PHY_TWO_CYC_PREAMBLE_3_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_853__PHY_TWO_CYC_PREAMBLE_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_853__PHY_TWO_CYC_PREAMBLE_3_WIDTH 2U +#define LPDDR4__PHY_TWO_CYC_PREAMBLE_3__REG DENALI_PHY_853 +#define LPDDR4__PHY_TWO_CYC_PREAMBLE_3__FLD LPDDR4__DENALI_PHY_853__PHY_TWO_CYC_PREAMBLE_3 + +#define LPDDR4__DENALI_PHY_853__PHY_VREF_INITIAL_START_POINT_3_MASK 0x7F000000U +#define LPDDR4__DENALI_PHY_853__PHY_VREF_INITIAL_START_POINT_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_853__PHY_VREF_INITIAL_START_POINT_3_WIDTH 7U +#define LPDDR4__PHY_VREF_INITIAL_START_POINT_3__REG DENALI_PHY_853 +#define LPDDR4__PHY_VREF_INITIAL_START_POINT_3__FLD LPDDR4__DENALI_PHY_853__PHY_VREF_INITIAL_START_POINT_3 + +#define LPDDR4__DENALI_PHY_854_READ_MASK 0xFF01037FU +#define LPDDR4__DENALI_PHY_854_WRITE_MASK 0xFF01037FU +#define LPDDR4__DENALI_PHY_854__PHY_VREF_INITIAL_STOP_POINT_3_MASK 0x0000007FU +#define LPDDR4__DENALI_PHY_854__PHY_VREF_INITIAL_STOP_POINT_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_854__PHY_VREF_INITIAL_STOP_POINT_3_WIDTH 7U +#define LPDDR4__PHY_VREF_INITIAL_STOP_POINT_3__REG DENALI_PHY_854 +#define LPDDR4__PHY_VREF_INITIAL_STOP_POINT_3__FLD LPDDR4__DENALI_PHY_854__PHY_VREF_INITIAL_STOP_POINT_3 + +#define LPDDR4__DENALI_PHY_854__PHY_VREF_TRAINING_CTRL_3_MASK 0x00000300U +#define LPDDR4__DENALI_PHY_854__PHY_VREF_TRAINING_CTRL_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_854__PHY_VREF_TRAINING_CTRL_3_WIDTH 2U +#define LPDDR4__PHY_VREF_TRAINING_CTRL_3__REG DENALI_PHY_854 +#define LPDDR4__PHY_VREF_TRAINING_CTRL_3__FLD LPDDR4__DENALI_PHY_854__PHY_VREF_TRAINING_CTRL_3 + +#define LPDDR4__DENALI_PHY_854__PHY_NTP_TRAIN_EN_3_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_854__PHY_NTP_TRAIN_EN_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_854__PHY_NTP_TRAIN_EN_3_WIDTH 1U +#define LPDDR4__DENALI_PHY_854__PHY_NTP_TRAIN_EN_3_WOCLR 0U +#define LPDDR4__DENALI_PHY_854__PHY_NTP_TRAIN_EN_3_WOSET 0U +#define LPDDR4__PHY_NTP_TRAIN_EN_3__REG DENALI_PHY_854 +#define LPDDR4__PHY_NTP_TRAIN_EN_3__FLD LPDDR4__DENALI_PHY_854__PHY_NTP_TRAIN_EN_3 + +#define LPDDR4__DENALI_PHY_854__PHY_NTP_WDQ_STEP_SIZE_3_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_854__PHY_NTP_WDQ_STEP_SIZE_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_854__PHY_NTP_WDQ_STEP_SIZE_3_WIDTH 8U +#define LPDDR4__PHY_NTP_WDQ_STEP_SIZE_3__REG DENALI_PHY_854 +#define LPDDR4__PHY_NTP_WDQ_STEP_SIZE_3__FLD LPDDR4__DENALI_PHY_854__PHY_NTP_WDQ_STEP_SIZE_3 + +#define LPDDR4__DENALI_PHY_855_READ_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_855_WRITE_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_855__PHY_NTP_WDQ_START_3_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_855__PHY_NTP_WDQ_START_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_855__PHY_NTP_WDQ_START_3_WIDTH 11U +#define LPDDR4__PHY_NTP_WDQ_START_3__REG DENALI_PHY_855 +#define LPDDR4__PHY_NTP_WDQ_START_3__FLD LPDDR4__DENALI_PHY_855__PHY_NTP_WDQ_START_3 + +#define LPDDR4__DENALI_PHY_855__PHY_NTP_WDQ_STOP_3_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_855__PHY_NTP_WDQ_STOP_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_855__PHY_NTP_WDQ_STOP_3_WIDTH 11U +#define LPDDR4__PHY_NTP_WDQ_STOP_3__REG DENALI_PHY_855 +#define LPDDR4__PHY_NTP_WDQ_STOP_3__FLD LPDDR4__DENALI_PHY_855__PHY_NTP_WDQ_STOP_3 + +#define LPDDR4__DENALI_PHY_856_READ_MASK 0x0103FFFFU +#define LPDDR4__DENALI_PHY_856_WRITE_MASK 0x0103FFFFU +#define LPDDR4__DENALI_PHY_856__PHY_NTP_WDQ_BIT_EN_3_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_856__PHY_NTP_WDQ_BIT_EN_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_856__PHY_NTP_WDQ_BIT_EN_3_WIDTH 8U +#define LPDDR4__PHY_NTP_WDQ_BIT_EN_3__REG DENALI_PHY_856 +#define LPDDR4__PHY_NTP_WDQ_BIT_EN_3__FLD LPDDR4__DENALI_PHY_856__PHY_NTP_WDQ_BIT_EN_3 + +#define LPDDR4__DENALI_PHY_856__PHY_WDQLVL_DVW_MIN_3_MASK 0x0003FF00U +#define LPDDR4__DENALI_PHY_856__PHY_WDQLVL_DVW_MIN_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_856__PHY_WDQLVL_DVW_MIN_3_WIDTH 10U +#define LPDDR4__PHY_WDQLVL_DVW_MIN_3__REG DENALI_PHY_856 +#define LPDDR4__PHY_WDQLVL_DVW_MIN_3__FLD LPDDR4__DENALI_PHY_856__PHY_WDQLVL_DVW_MIN_3 + +#define LPDDR4__DENALI_PHY_856__PHY_SW_WDQLVL_DVW_MIN_EN_3_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_856__PHY_SW_WDQLVL_DVW_MIN_EN_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_856__PHY_SW_WDQLVL_DVW_MIN_EN_3_WIDTH 1U +#define LPDDR4__DENALI_PHY_856__PHY_SW_WDQLVL_DVW_MIN_EN_3_WOCLR 0U +#define LPDDR4__DENALI_PHY_856__PHY_SW_WDQLVL_DVW_MIN_EN_3_WOSET 0U +#define LPDDR4__PHY_SW_WDQLVL_DVW_MIN_EN_3__REG DENALI_PHY_856 +#define LPDDR4__PHY_SW_WDQLVL_DVW_MIN_EN_3__FLD LPDDR4__DENALI_PHY_856__PHY_SW_WDQLVL_DVW_MIN_EN_3 + +#define LPDDR4__DENALI_PHY_857_READ_MASK 0x1F1F0F3FU +#define LPDDR4__DENALI_PHY_857_WRITE_MASK 0x1F1F0F3FU +#define LPDDR4__DENALI_PHY_857__PHY_WDQLVL_PER_START_OFFSET_3_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_857__PHY_WDQLVL_PER_START_OFFSET_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_857__PHY_WDQLVL_PER_START_OFFSET_3_WIDTH 6U +#define LPDDR4__PHY_WDQLVL_PER_START_OFFSET_3__REG DENALI_PHY_857 +#define LPDDR4__PHY_WDQLVL_PER_START_OFFSET_3__FLD LPDDR4__DENALI_PHY_857__PHY_WDQLVL_PER_START_OFFSET_3 + +#define LPDDR4__DENALI_PHY_857__PHY_FAST_LVL_EN_3_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_857__PHY_FAST_LVL_EN_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_857__PHY_FAST_LVL_EN_3_WIDTH 4U +#define LPDDR4__PHY_FAST_LVL_EN_3__REG DENALI_PHY_857 +#define LPDDR4__PHY_FAST_LVL_EN_3__FLD LPDDR4__DENALI_PHY_857__PHY_FAST_LVL_EN_3 + +#define LPDDR4__DENALI_PHY_857__PHY_PAD_TX_DCD_3_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_857__PHY_PAD_TX_DCD_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_857__PHY_PAD_TX_DCD_3_WIDTH 5U +#define LPDDR4__PHY_PAD_TX_DCD_3__REG DENALI_PHY_857 +#define LPDDR4__PHY_PAD_TX_DCD_3__FLD LPDDR4__DENALI_PHY_857__PHY_PAD_TX_DCD_3 + +#define LPDDR4__DENALI_PHY_857__PHY_PAD_RX_DCD_0_3_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_857__PHY_PAD_RX_DCD_0_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_857__PHY_PAD_RX_DCD_0_3_WIDTH 5U +#define LPDDR4__PHY_PAD_RX_DCD_0_3__REG DENALI_PHY_857 +#define LPDDR4__PHY_PAD_RX_DCD_0_3__FLD LPDDR4__DENALI_PHY_857__PHY_PAD_RX_DCD_0_3 + +#define LPDDR4__DENALI_PHY_858_READ_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_PHY_858_WRITE_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_PHY_858__PHY_PAD_RX_DCD_1_3_MASK 0x0000001FU +#define LPDDR4__DENALI_PHY_858__PHY_PAD_RX_DCD_1_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_858__PHY_PAD_RX_DCD_1_3_WIDTH 5U +#define LPDDR4__PHY_PAD_RX_DCD_1_3__REG DENALI_PHY_858 +#define LPDDR4__PHY_PAD_RX_DCD_1_3__FLD LPDDR4__DENALI_PHY_858__PHY_PAD_RX_DCD_1_3 + +#define LPDDR4__DENALI_PHY_858__PHY_PAD_RX_DCD_2_3_MASK 0x00001F00U +#define LPDDR4__DENALI_PHY_858__PHY_PAD_RX_DCD_2_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_858__PHY_PAD_RX_DCD_2_3_WIDTH 5U +#define LPDDR4__PHY_PAD_RX_DCD_2_3__REG DENALI_PHY_858 +#define LPDDR4__PHY_PAD_RX_DCD_2_3__FLD LPDDR4__DENALI_PHY_858__PHY_PAD_RX_DCD_2_3 + +#define LPDDR4__DENALI_PHY_858__PHY_PAD_RX_DCD_3_3_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_858__PHY_PAD_RX_DCD_3_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_858__PHY_PAD_RX_DCD_3_3_WIDTH 5U +#define LPDDR4__PHY_PAD_RX_DCD_3_3__REG DENALI_PHY_858 +#define LPDDR4__PHY_PAD_RX_DCD_3_3__FLD LPDDR4__DENALI_PHY_858__PHY_PAD_RX_DCD_3_3 + +#define LPDDR4__DENALI_PHY_858__PHY_PAD_RX_DCD_4_3_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_858__PHY_PAD_RX_DCD_4_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_858__PHY_PAD_RX_DCD_4_3_WIDTH 5U +#define LPDDR4__PHY_PAD_RX_DCD_4_3__REG DENALI_PHY_858 +#define LPDDR4__PHY_PAD_RX_DCD_4_3__FLD LPDDR4__DENALI_PHY_858__PHY_PAD_RX_DCD_4_3 + +#define LPDDR4__DENALI_PHY_859_READ_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_PHY_859_WRITE_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_PHY_859__PHY_PAD_RX_DCD_5_3_MASK 0x0000001FU +#define LPDDR4__DENALI_PHY_859__PHY_PAD_RX_DCD_5_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_859__PHY_PAD_RX_DCD_5_3_WIDTH 5U +#define LPDDR4__PHY_PAD_RX_DCD_5_3__REG DENALI_PHY_859 +#define LPDDR4__PHY_PAD_RX_DCD_5_3__FLD LPDDR4__DENALI_PHY_859__PHY_PAD_RX_DCD_5_3 + +#define LPDDR4__DENALI_PHY_859__PHY_PAD_RX_DCD_6_3_MASK 0x00001F00U +#define LPDDR4__DENALI_PHY_859__PHY_PAD_RX_DCD_6_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_859__PHY_PAD_RX_DCD_6_3_WIDTH 5U +#define LPDDR4__PHY_PAD_RX_DCD_6_3__REG DENALI_PHY_859 +#define LPDDR4__PHY_PAD_RX_DCD_6_3__FLD LPDDR4__DENALI_PHY_859__PHY_PAD_RX_DCD_6_3 + +#define LPDDR4__DENALI_PHY_859__PHY_PAD_RX_DCD_7_3_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_859__PHY_PAD_RX_DCD_7_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_859__PHY_PAD_RX_DCD_7_3_WIDTH 5U +#define LPDDR4__PHY_PAD_RX_DCD_7_3__REG DENALI_PHY_859 +#define LPDDR4__PHY_PAD_RX_DCD_7_3__FLD LPDDR4__DENALI_PHY_859__PHY_PAD_RX_DCD_7_3 + +#define LPDDR4__DENALI_PHY_859__PHY_PAD_DM_RX_DCD_3_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_859__PHY_PAD_DM_RX_DCD_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_859__PHY_PAD_DM_RX_DCD_3_WIDTH 5U +#define LPDDR4__PHY_PAD_DM_RX_DCD_3__REG DENALI_PHY_859 +#define LPDDR4__PHY_PAD_DM_RX_DCD_3__FLD LPDDR4__DENALI_PHY_859__PHY_PAD_DM_RX_DCD_3 + +#define LPDDR4__DENALI_PHY_860_READ_MASK 0x003F1F1FU +#define LPDDR4__DENALI_PHY_860_WRITE_MASK 0x003F1F1FU +#define LPDDR4__DENALI_PHY_860__PHY_PAD_DQS_RX_DCD_3_MASK 0x0000001FU +#define LPDDR4__DENALI_PHY_860__PHY_PAD_DQS_RX_DCD_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_860__PHY_PAD_DQS_RX_DCD_3_WIDTH 5U +#define LPDDR4__PHY_PAD_DQS_RX_DCD_3__REG DENALI_PHY_860 +#define LPDDR4__PHY_PAD_DQS_RX_DCD_3__FLD LPDDR4__DENALI_PHY_860__PHY_PAD_DQS_RX_DCD_3 + +#define LPDDR4__DENALI_PHY_860__PHY_PAD_FDBK_RX_DCD_3_MASK 0x00001F00U +#define LPDDR4__DENALI_PHY_860__PHY_PAD_FDBK_RX_DCD_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_860__PHY_PAD_FDBK_RX_DCD_3_WIDTH 5U +#define LPDDR4__PHY_PAD_FDBK_RX_DCD_3__REG DENALI_PHY_860 +#define LPDDR4__PHY_PAD_FDBK_RX_DCD_3__FLD LPDDR4__DENALI_PHY_860__PHY_PAD_FDBK_RX_DCD_3 + +#define LPDDR4__DENALI_PHY_860__PHY_PAD_DSLICE_IO_CFG_3_MASK 0x003F0000U +#define LPDDR4__DENALI_PHY_860__PHY_PAD_DSLICE_IO_CFG_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_860__PHY_PAD_DSLICE_IO_CFG_3_WIDTH 6U +#define LPDDR4__PHY_PAD_DSLICE_IO_CFG_3__REG DENALI_PHY_860 +#define LPDDR4__PHY_PAD_DSLICE_IO_CFG_3__FLD LPDDR4__DENALI_PHY_860__PHY_PAD_DSLICE_IO_CFG_3 + +#define LPDDR4__DENALI_PHY_861_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_861_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_861__PHY_RDDQ0_SLAVE_DELAY_3_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_861__PHY_RDDQ0_SLAVE_DELAY_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_861__PHY_RDDQ0_SLAVE_DELAY_3_WIDTH 10U +#define LPDDR4__PHY_RDDQ0_SLAVE_DELAY_3__REG DENALI_PHY_861 +#define LPDDR4__PHY_RDDQ0_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_861__PHY_RDDQ0_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_861__PHY_RDDQ1_SLAVE_DELAY_3_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_861__PHY_RDDQ1_SLAVE_DELAY_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_861__PHY_RDDQ1_SLAVE_DELAY_3_WIDTH 10U +#define LPDDR4__PHY_RDDQ1_SLAVE_DELAY_3__REG DENALI_PHY_861 +#define LPDDR4__PHY_RDDQ1_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_861__PHY_RDDQ1_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_862_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_862_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_862__PHY_RDDQ2_SLAVE_DELAY_3_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_862__PHY_RDDQ2_SLAVE_DELAY_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_862__PHY_RDDQ2_SLAVE_DELAY_3_WIDTH 10U +#define LPDDR4__PHY_RDDQ2_SLAVE_DELAY_3__REG DENALI_PHY_862 +#define LPDDR4__PHY_RDDQ2_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_862__PHY_RDDQ2_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_862__PHY_RDDQ3_SLAVE_DELAY_3_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_862__PHY_RDDQ3_SLAVE_DELAY_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_862__PHY_RDDQ3_SLAVE_DELAY_3_WIDTH 10U +#define LPDDR4__PHY_RDDQ3_SLAVE_DELAY_3__REG DENALI_PHY_862 +#define LPDDR4__PHY_RDDQ3_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_862__PHY_RDDQ3_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_863_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_863_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_863__PHY_RDDQ4_SLAVE_DELAY_3_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_863__PHY_RDDQ4_SLAVE_DELAY_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_863__PHY_RDDQ4_SLAVE_DELAY_3_WIDTH 10U +#define LPDDR4__PHY_RDDQ4_SLAVE_DELAY_3__REG DENALI_PHY_863 +#define LPDDR4__PHY_RDDQ4_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_863__PHY_RDDQ4_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_863__PHY_RDDQ5_SLAVE_DELAY_3_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_863__PHY_RDDQ5_SLAVE_DELAY_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_863__PHY_RDDQ5_SLAVE_DELAY_3_WIDTH 10U +#define LPDDR4__PHY_RDDQ5_SLAVE_DELAY_3__REG DENALI_PHY_863 +#define LPDDR4__PHY_RDDQ5_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_863__PHY_RDDQ5_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_864_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_864_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_864__PHY_RDDQ6_SLAVE_DELAY_3_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_864__PHY_RDDQ6_SLAVE_DELAY_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_864__PHY_RDDQ6_SLAVE_DELAY_3_WIDTH 10U +#define LPDDR4__PHY_RDDQ6_SLAVE_DELAY_3__REG DENALI_PHY_864 +#define LPDDR4__PHY_RDDQ6_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_864__PHY_RDDQ6_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_864__PHY_RDDQ7_SLAVE_DELAY_3_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_864__PHY_RDDQ7_SLAVE_DELAY_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_864__PHY_RDDQ7_SLAVE_DELAY_3_WIDTH 10U +#define LPDDR4__PHY_RDDQ7_SLAVE_DELAY_3__REG DENALI_PHY_864 +#define LPDDR4__PHY_RDDQ7_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_864__PHY_RDDQ7_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_865_READ_MASK 0x000703FFU +#define LPDDR4__DENALI_PHY_865_WRITE_MASK 0x000703FFU +#define LPDDR4__DENALI_PHY_865__PHY_RDDM_SLAVE_DELAY_3_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_865__PHY_RDDM_SLAVE_DELAY_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_865__PHY_RDDM_SLAVE_DELAY_3_WIDTH 10U +#define LPDDR4__PHY_RDDM_SLAVE_DELAY_3__REG DENALI_PHY_865 +#define LPDDR4__PHY_RDDM_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_865__PHY_RDDM_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_865__PHY_DATA_DC_CAL_CLK_SEL_3_MASK 0x00070000U +#define LPDDR4__DENALI_PHY_865__PHY_DATA_DC_CAL_CLK_SEL_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_865__PHY_DATA_DC_CAL_CLK_SEL_3_WIDTH 3U +#define LPDDR4__PHY_DATA_DC_CAL_CLK_SEL_3__REG DENALI_PHY_865 +#define LPDDR4__PHY_DATA_DC_CAL_CLK_SEL_3__FLD LPDDR4__DENALI_PHY_865__PHY_DATA_DC_CAL_CLK_SEL_3 + +#define LPDDR4__DENALI_PHY_866_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_866_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_866__PHY_DQ_OE_TIMING_3_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_866__PHY_DQ_OE_TIMING_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_866__PHY_DQ_OE_TIMING_3_WIDTH 8U +#define LPDDR4__PHY_DQ_OE_TIMING_3__REG DENALI_PHY_866 +#define LPDDR4__PHY_DQ_OE_TIMING_3__FLD LPDDR4__DENALI_PHY_866__PHY_DQ_OE_TIMING_3 + +#define LPDDR4__DENALI_PHY_866__PHY_DQ_TSEL_RD_TIMING_3_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_866__PHY_DQ_TSEL_RD_TIMING_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_866__PHY_DQ_TSEL_RD_TIMING_3_WIDTH 8U +#define LPDDR4__PHY_DQ_TSEL_RD_TIMING_3__REG DENALI_PHY_866 +#define LPDDR4__PHY_DQ_TSEL_RD_TIMING_3__FLD LPDDR4__DENALI_PHY_866__PHY_DQ_TSEL_RD_TIMING_3 + +#define LPDDR4__DENALI_PHY_866__PHY_DQ_TSEL_WR_TIMING_3_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_866__PHY_DQ_TSEL_WR_TIMING_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_866__PHY_DQ_TSEL_WR_TIMING_3_WIDTH 8U +#define LPDDR4__PHY_DQ_TSEL_WR_TIMING_3__REG DENALI_PHY_866 +#define LPDDR4__PHY_DQ_TSEL_WR_TIMING_3__FLD LPDDR4__DENALI_PHY_866__PHY_DQ_TSEL_WR_TIMING_3 + +#define LPDDR4__DENALI_PHY_866__PHY_DQS_OE_TIMING_3_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_866__PHY_DQS_OE_TIMING_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_866__PHY_DQS_OE_TIMING_3_WIDTH 8U +#define LPDDR4__PHY_DQS_OE_TIMING_3__REG DENALI_PHY_866 +#define LPDDR4__PHY_DQS_OE_TIMING_3__FLD LPDDR4__DENALI_PHY_866__PHY_DQS_OE_TIMING_3 + +#define LPDDR4__DENALI_PHY_867_READ_MASK 0xFFFFFF0FU +#define LPDDR4__DENALI_PHY_867_WRITE_MASK 0xFFFFFF0FU +#define LPDDR4__DENALI_PHY_867__PHY_IO_PAD_DELAY_TIMING_3_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_867__PHY_IO_PAD_DELAY_TIMING_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_867__PHY_IO_PAD_DELAY_TIMING_3_WIDTH 4U +#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_3__REG DENALI_PHY_867 +#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_3__FLD LPDDR4__DENALI_PHY_867__PHY_IO_PAD_DELAY_TIMING_3 + +#define LPDDR4__DENALI_PHY_867__PHY_DQS_TSEL_RD_TIMING_3_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_867__PHY_DQS_TSEL_RD_TIMING_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_867__PHY_DQS_TSEL_RD_TIMING_3_WIDTH 8U +#define LPDDR4__PHY_DQS_TSEL_RD_TIMING_3__REG DENALI_PHY_867 +#define LPDDR4__PHY_DQS_TSEL_RD_TIMING_3__FLD LPDDR4__DENALI_PHY_867__PHY_DQS_TSEL_RD_TIMING_3 + +#define LPDDR4__DENALI_PHY_867__PHY_DQS_OE_RD_TIMING_3_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_867__PHY_DQS_OE_RD_TIMING_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_867__PHY_DQS_OE_RD_TIMING_3_WIDTH 8U +#define LPDDR4__PHY_DQS_OE_RD_TIMING_3__REG DENALI_PHY_867 +#define LPDDR4__PHY_DQS_OE_RD_TIMING_3__FLD LPDDR4__DENALI_PHY_867__PHY_DQS_OE_RD_TIMING_3 + +#define LPDDR4__DENALI_PHY_867__PHY_DQS_TSEL_WR_TIMING_3_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_867__PHY_DQS_TSEL_WR_TIMING_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_867__PHY_DQS_TSEL_WR_TIMING_3_WIDTH 8U +#define LPDDR4__PHY_DQS_TSEL_WR_TIMING_3__REG DENALI_PHY_867 +#define LPDDR4__PHY_DQS_TSEL_WR_TIMING_3__FLD LPDDR4__DENALI_PHY_867__PHY_DQS_TSEL_WR_TIMING_3 + +#define LPDDR4__DENALI_PHY_868_READ_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_868_WRITE_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_868__PHY_VREF_SETTING_TIME_3_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_868__PHY_VREF_SETTING_TIME_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_868__PHY_VREF_SETTING_TIME_3_WIDTH 16U +#define LPDDR4__PHY_VREF_SETTING_TIME_3__REG DENALI_PHY_868 +#define LPDDR4__PHY_VREF_SETTING_TIME_3__FLD LPDDR4__DENALI_PHY_868__PHY_VREF_SETTING_TIME_3 + +#define LPDDR4__DENALI_PHY_868__PHY_PAD_VREF_CTRL_DQ_3_MASK 0x0FFF0000U +#define LPDDR4__DENALI_PHY_868__PHY_PAD_VREF_CTRL_DQ_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_868__PHY_PAD_VREF_CTRL_DQ_3_WIDTH 12U +#define LPDDR4__PHY_PAD_VREF_CTRL_DQ_3__REG DENALI_PHY_868 +#define LPDDR4__PHY_PAD_VREF_CTRL_DQ_3__FLD LPDDR4__DENALI_PHY_868__PHY_PAD_VREF_CTRL_DQ_3 + +#define LPDDR4__DENALI_PHY_869_READ_MASK 0x03FFFF01U +#define LPDDR4__DENALI_PHY_869_WRITE_MASK 0x03FFFF01U +#define LPDDR4__DENALI_PHY_869__PHY_PER_CS_TRAINING_EN_3_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_869__PHY_PER_CS_TRAINING_EN_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_869__PHY_PER_CS_TRAINING_EN_3_WIDTH 1U +#define LPDDR4__DENALI_PHY_869__PHY_PER_CS_TRAINING_EN_3_WOCLR 0U +#define LPDDR4__DENALI_PHY_869__PHY_PER_CS_TRAINING_EN_3_WOSET 0U +#define LPDDR4__PHY_PER_CS_TRAINING_EN_3__REG DENALI_PHY_869 +#define LPDDR4__PHY_PER_CS_TRAINING_EN_3__FLD LPDDR4__DENALI_PHY_869__PHY_PER_CS_TRAINING_EN_3 + +#define LPDDR4__DENALI_PHY_869__PHY_DQ_IE_TIMING_3_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_869__PHY_DQ_IE_TIMING_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_869__PHY_DQ_IE_TIMING_3_WIDTH 8U +#define LPDDR4__PHY_DQ_IE_TIMING_3__REG DENALI_PHY_869 +#define LPDDR4__PHY_DQ_IE_TIMING_3__FLD LPDDR4__DENALI_PHY_869__PHY_DQ_IE_TIMING_3 + +#define LPDDR4__DENALI_PHY_869__PHY_DQS_IE_TIMING_3_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_869__PHY_DQS_IE_TIMING_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_869__PHY_DQS_IE_TIMING_3_WIDTH 8U +#define LPDDR4__PHY_DQS_IE_TIMING_3__REG DENALI_PHY_869 +#define LPDDR4__PHY_DQS_IE_TIMING_3__FLD LPDDR4__DENALI_PHY_869__PHY_DQS_IE_TIMING_3 + +#define LPDDR4__DENALI_PHY_869__PHY_RDDATA_EN_IE_DLY_3_MASK 0x03000000U +#define LPDDR4__DENALI_PHY_869__PHY_RDDATA_EN_IE_DLY_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_869__PHY_RDDATA_EN_IE_DLY_3_WIDTH 2U +#define LPDDR4__PHY_RDDATA_EN_IE_DLY_3__REG DENALI_PHY_869 +#define LPDDR4__PHY_RDDATA_EN_IE_DLY_3__FLD LPDDR4__DENALI_PHY_869__PHY_RDDATA_EN_IE_DLY_3 + +#define LPDDR4__DENALI_PHY_870_READ_MASK 0x1F1F0103U +#define LPDDR4__DENALI_PHY_870_WRITE_MASK 0x1F1F0103U +#define LPDDR4__DENALI_PHY_870__PHY_IE_MODE_3_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_870__PHY_IE_MODE_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_870__PHY_IE_MODE_3_WIDTH 2U +#define LPDDR4__PHY_IE_MODE_3__REG DENALI_PHY_870 +#define LPDDR4__PHY_IE_MODE_3__FLD LPDDR4__DENALI_PHY_870__PHY_IE_MODE_3 + +#define LPDDR4__DENALI_PHY_870__PHY_DBI_MODE_3_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_870__PHY_DBI_MODE_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_870__PHY_DBI_MODE_3_WIDTH 1U +#define LPDDR4__DENALI_PHY_870__PHY_DBI_MODE_3_WOCLR 0U +#define LPDDR4__DENALI_PHY_870__PHY_DBI_MODE_3_WOSET 0U +#define LPDDR4__PHY_DBI_MODE_3__REG DENALI_PHY_870 +#define LPDDR4__PHY_DBI_MODE_3__FLD LPDDR4__DENALI_PHY_870__PHY_DBI_MODE_3 + +#define LPDDR4__DENALI_PHY_870__PHY_RDDATA_EN_TSEL_DLY_3_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_870__PHY_RDDATA_EN_TSEL_DLY_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_870__PHY_RDDATA_EN_TSEL_DLY_3_WIDTH 5U +#define LPDDR4__PHY_RDDATA_EN_TSEL_DLY_3__REG DENALI_PHY_870 +#define LPDDR4__PHY_RDDATA_EN_TSEL_DLY_3__FLD LPDDR4__DENALI_PHY_870__PHY_RDDATA_EN_TSEL_DLY_3 + +#define LPDDR4__DENALI_PHY_870__PHY_RDDATA_EN_OE_DLY_3_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_870__PHY_RDDATA_EN_OE_DLY_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_870__PHY_RDDATA_EN_OE_DLY_3_WIDTH 5U +#define LPDDR4__PHY_RDDATA_EN_OE_DLY_3__REG DENALI_PHY_870 +#define LPDDR4__PHY_RDDATA_EN_OE_DLY_3__FLD LPDDR4__DENALI_PHY_870__PHY_RDDATA_EN_OE_DLY_3 + +#define LPDDR4__DENALI_PHY_871_READ_MASK 0x3F07FF0FU +#define LPDDR4__DENALI_PHY_871_WRITE_MASK 0x3F07FF0FU +#define LPDDR4__DENALI_PHY_871__PHY_SW_MASTER_MODE_3_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_871__PHY_SW_MASTER_MODE_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_871__PHY_SW_MASTER_MODE_3_WIDTH 4U +#define LPDDR4__PHY_SW_MASTER_MODE_3__REG DENALI_PHY_871 +#define LPDDR4__PHY_SW_MASTER_MODE_3__FLD LPDDR4__DENALI_PHY_871__PHY_SW_MASTER_MODE_3 + +#define LPDDR4__DENALI_PHY_871__PHY_MASTER_DELAY_START_3_MASK 0x0007FF00U +#define LPDDR4__DENALI_PHY_871__PHY_MASTER_DELAY_START_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_871__PHY_MASTER_DELAY_START_3_WIDTH 11U +#define LPDDR4__PHY_MASTER_DELAY_START_3__REG DENALI_PHY_871 +#define LPDDR4__PHY_MASTER_DELAY_START_3__FLD LPDDR4__DENALI_PHY_871__PHY_MASTER_DELAY_START_3 + +#define LPDDR4__DENALI_PHY_871__PHY_MASTER_DELAY_STEP_3_MASK 0x3F000000U +#define LPDDR4__DENALI_PHY_871__PHY_MASTER_DELAY_STEP_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_871__PHY_MASTER_DELAY_STEP_3_WIDTH 6U +#define LPDDR4__PHY_MASTER_DELAY_STEP_3__REG DENALI_PHY_871 +#define LPDDR4__PHY_MASTER_DELAY_STEP_3__FLD LPDDR4__DENALI_PHY_871__PHY_MASTER_DELAY_STEP_3 + +#define LPDDR4__DENALI_PHY_872_READ_MASK 0xFF0FFFFFU +#define LPDDR4__DENALI_PHY_872_WRITE_MASK 0xFF0FFFFFU +#define LPDDR4__DENALI_PHY_872__PHY_MASTER_DELAY_WAIT_3_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_872__PHY_MASTER_DELAY_WAIT_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_872__PHY_MASTER_DELAY_WAIT_3_WIDTH 8U +#define LPDDR4__PHY_MASTER_DELAY_WAIT_3__REG DENALI_PHY_872 +#define LPDDR4__PHY_MASTER_DELAY_WAIT_3__FLD LPDDR4__DENALI_PHY_872__PHY_MASTER_DELAY_WAIT_3 + +#define LPDDR4__DENALI_PHY_872__PHY_MASTER_DELAY_HALF_MEASURE_3_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_872__PHY_MASTER_DELAY_HALF_MEASURE_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_872__PHY_MASTER_DELAY_HALF_MEASURE_3_WIDTH 8U +#define LPDDR4__PHY_MASTER_DELAY_HALF_MEASURE_3__REG DENALI_PHY_872 +#define LPDDR4__PHY_MASTER_DELAY_HALF_MEASURE_3__FLD LPDDR4__DENALI_PHY_872__PHY_MASTER_DELAY_HALF_MEASURE_3 + +#define LPDDR4__DENALI_PHY_872__PHY_RPTR_UPDATE_3_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_872__PHY_RPTR_UPDATE_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_872__PHY_RPTR_UPDATE_3_WIDTH 4U +#define LPDDR4__PHY_RPTR_UPDATE_3__REG DENALI_PHY_872 +#define LPDDR4__PHY_RPTR_UPDATE_3__FLD LPDDR4__DENALI_PHY_872__PHY_RPTR_UPDATE_3 + +#define LPDDR4__DENALI_PHY_872__PHY_WRLVL_DLY_STEP_3_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_872__PHY_WRLVL_DLY_STEP_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_872__PHY_WRLVL_DLY_STEP_3_WIDTH 8U +#define LPDDR4__PHY_WRLVL_DLY_STEP_3__REG DENALI_PHY_872 +#define LPDDR4__PHY_WRLVL_DLY_STEP_3__FLD LPDDR4__DENALI_PHY_872__PHY_WRLVL_DLY_STEP_3 + +#define LPDDR4__DENALI_PHY_873_READ_MASK 0x1F0F3F0FU +#define LPDDR4__DENALI_PHY_873_WRITE_MASK 0x1F0F3F0FU +#define LPDDR4__DENALI_PHY_873__PHY_WRLVL_DLY_FINE_STEP_3_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_873__PHY_WRLVL_DLY_FINE_STEP_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_873__PHY_WRLVL_DLY_FINE_STEP_3_WIDTH 4U +#define LPDDR4__PHY_WRLVL_DLY_FINE_STEP_3__REG DENALI_PHY_873 +#define LPDDR4__PHY_WRLVL_DLY_FINE_STEP_3__FLD LPDDR4__DENALI_PHY_873__PHY_WRLVL_DLY_FINE_STEP_3 + +#define LPDDR4__DENALI_PHY_873__PHY_WRLVL_RESP_WAIT_CNT_3_MASK 0x00003F00U +#define LPDDR4__DENALI_PHY_873__PHY_WRLVL_RESP_WAIT_CNT_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_873__PHY_WRLVL_RESP_WAIT_CNT_3_WIDTH 6U +#define LPDDR4__PHY_WRLVL_RESP_WAIT_CNT_3__REG DENALI_PHY_873 +#define LPDDR4__PHY_WRLVL_RESP_WAIT_CNT_3__FLD LPDDR4__DENALI_PHY_873__PHY_WRLVL_RESP_WAIT_CNT_3 + +#define LPDDR4__DENALI_PHY_873__PHY_GTLVL_DLY_STEP_3_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_873__PHY_GTLVL_DLY_STEP_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_873__PHY_GTLVL_DLY_STEP_3_WIDTH 4U +#define LPDDR4__PHY_GTLVL_DLY_STEP_3__REG DENALI_PHY_873 +#define LPDDR4__PHY_GTLVL_DLY_STEP_3__FLD LPDDR4__DENALI_PHY_873__PHY_GTLVL_DLY_STEP_3 + +#define LPDDR4__DENALI_PHY_873__PHY_GTLVL_RESP_WAIT_CNT_3_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_873__PHY_GTLVL_RESP_WAIT_CNT_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_873__PHY_GTLVL_RESP_WAIT_CNT_3_WIDTH 5U +#define LPDDR4__PHY_GTLVL_RESP_WAIT_CNT_3__REG DENALI_PHY_873 +#define LPDDR4__PHY_GTLVL_RESP_WAIT_CNT_3__FLD LPDDR4__DENALI_PHY_873__PHY_GTLVL_RESP_WAIT_CNT_3 + +#define LPDDR4__DENALI_PHY_874_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_874_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_874__PHY_GTLVL_BACK_STEP_3_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_874__PHY_GTLVL_BACK_STEP_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_874__PHY_GTLVL_BACK_STEP_3_WIDTH 10U +#define LPDDR4__PHY_GTLVL_BACK_STEP_3__REG DENALI_PHY_874 +#define LPDDR4__PHY_GTLVL_BACK_STEP_3__FLD LPDDR4__DENALI_PHY_874__PHY_GTLVL_BACK_STEP_3 + +#define LPDDR4__DENALI_PHY_874__PHY_GTLVL_FINAL_STEP_3_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_874__PHY_GTLVL_FINAL_STEP_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_874__PHY_GTLVL_FINAL_STEP_3_WIDTH 10U +#define LPDDR4__PHY_GTLVL_FINAL_STEP_3__REG DENALI_PHY_874 +#define LPDDR4__PHY_GTLVL_FINAL_STEP_3__FLD LPDDR4__DENALI_PHY_874__PHY_GTLVL_FINAL_STEP_3 + +#define LPDDR4__DENALI_PHY_875_READ_MASK 0x0F010FFFU +#define LPDDR4__DENALI_PHY_875_WRITE_MASK 0x0F010FFFU +#define LPDDR4__DENALI_PHY_875__PHY_WDQLVL_DLY_STEP_3_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_875__PHY_WDQLVL_DLY_STEP_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_875__PHY_WDQLVL_DLY_STEP_3_WIDTH 8U +#define LPDDR4__PHY_WDQLVL_DLY_STEP_3__REG DENALI_PHY_875 +#define LPDDR4__PHY_WDQLVL_DLY_STEP_3__FLD LPDDR4__DENALI_PHY_875__PHY_WDQLVL_DLY_STEP_3 + +#define LPDDR4__DENALI_PHY_875__PHY_WDQLVL_QTR_DLY_STEP_3_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_875__PHY_WDQLVL_QTR_DLY_STEP_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_875__PHY_WDQLVL_QTR_DLY_STEP_3_WIDTH 4U +#define LPDDR4__PHY_WDQLVL_QTR_DLY_STEP_3__REG DENALI_PHY_875 +#define LPDDR4__PHY_WDQLVL_QTR_DLY_STEP_3__FLD LPDDR4__DENALI_PHY_875__PHY_WDQLVL_QTR_DLY_STEP_3 + +#define LPDDR4__DENALI_PHY_875__PHY_TOGGLE_PRE_SUPPORT_3_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_875__PHY_TOGGLE_PRE_SUPPORT_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_875__PHY_TOGGLE_PRE_SUPPORT_3_WIDTH 1U +#define LPDDR4__DENALI_PHY_875__PHY_TOGGLE_PRE_SUPPORT_3_WOCLR 0U +#define LPDDR4__DENALI_PHY_875__PHY_TOGGLE_PRE_SUPPORT_3_WOSET 0U +#define LPDDR4__PHY_TOGGLE_PRE_SUPPORT_3__REG DENALI_PHY_875 +#define LPDDR4__PHY_TOGGLE_PRE_SUPPORT_3__FLD LPDDR4__DENALI_PHY_875__PHY_TOGGLE_PRE_SUPPORT_3 + +#define LPDDR4__DENALI_PHY_875__PHY_RDLVL_DLY_STEP_3_MASK 0x0F000000U +#define LPDDR4__DENALI_PHY_875__PHY_RDLVL_DLY_STEP_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_875__PHY_RDLVL_DLY_STEP_3_WIDTH 4U +#define LPDDR4__PHY_RDLVL_DLY_STEP_3__REG DENALI_PHY_875 +#define LPDDR4__PHY_RDLVL_DLY_STEP_3__FLD LPDDR4__DENALI_PHY_875__PHY_RDLVL_DLY_STEP_3 + +#define LPDDR4__DENALI_PHY_876_READ_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_876_WRITE_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_876__PHY_RDLVL_MAX_EDGE_3_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_876__PHY_RDLVL_MAX_EDGE_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_876__PHY_RDLVL_MAX_EDGE_3_WIDTH 10U +#define LPDDR4__PHY_RDLVL_MAX_EDGE_3__REG DENALI_PHY_876 +#define LPDDR4__PHY_RDLVL_MAX_EDGE_3__FLD LPDDR4__DENALI_PHY_876__PHY_RDLVL_MAX_EDGE_3 + +#define LPDDR4__DENALI_PHY_877_READ_MASK 0x3F0103FFU +#define LPDDR4__DENALI_PHY_877_WRITE_MASK 0x3F0103FFU +#define LPDDR4__DENALI_PHY_877__PHY_RDLVL_DVW_MIN_3_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_877__PHY_RDLVL_DVW_MIN_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_877__PHY_RDLVL_DVW_MIN_3_WIDTH 10U +#define LPDDR4__PHY_RDLVL_DVW_MIN_3__REG DENALI_PHY_877 +#define LPDDR4__PHY_RDLVL_DVW_MIN_3__FLD LPDDR4__DENALI_PHY_877__PHY_RDLVL_DVW_MIN_3 + +#define LPDDR4__DENALI_PHY_877__PHY_SW_RDLVL_DVW_MIN_EN_3_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_877__PHY_SW_RDLVL_DVW_MIN_EN_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_877__PHY_SW_RDLVL_DVW_MIN_EN_3_WIDTH 1U +#define LPDDR4__DENALI_PHY_877__PHY_SW_RDLVL_DVW_MIN_EN_3_WOCLR 0U +#define LPDDR4__DENALI_PHY_877__PHY_SW_RDLVL_DVW_MIN_EN_3_WOSET 0U +#define LPDDR4__PHY_SW_RDLVL_DVW_MIN_EN_3__REG DENALI_PHY_877 +#define LPDDR4__PHY_SW_RDLVL_DVW_MIN_EN_3__FLD LPDDR4__DENALI_PHY_877__PHY_SW_RDLVL_DVW_MIN_EN_3 + +#define LPDDR4__DENALI_PHY_877__PHY_RDLVL_PER_START_OFFSET_3_MASK 0x3F000000U +#define LPDDR4__DENALI_PHY_877__PHY_RDLVL_PER_START_OFFSET_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_877__PHY_RDLVL_PER_START_OFFSET_3_WIDTH 6U +#define LPDDR4__PHY_RDLVL_PER_START_OFFSET_3__REG DENALI_PHY_877 +#define LPDDR4__PHY_RDLVL_PER_START_OFFSET_3__FLD LPDDR4__DENALI_PHY_877__PHY_RDLVL_PER_START_OFFSET_3 + +#define LPDDR4__DENALI_PHY_878_READ_MASK 0x00030703U +#define LPDDR4__DENALI_PHY_878_WRITE_MASK 0x00030703U +#define LPDDR4__DENALI_PHY_878__PHY_WRPATH_GATE_DISABLE_3_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_878__PHY_WRPATH_GATE_DISABLE_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_878__PHY_WRPATH_GATE_DISABLE_3_WIDTH 2U +#define LPDDR4__PHY_WRPATH_GATE_DISABLE_3__REG DENALI_PHY_878 +#define LPDDR4__PHY_WRPATH_GATE_DISABLE_3__FLD LPDDR4__DENALI_PHY_878__PHY_WRPATH_GATE_DISABLE_3 + +#define LPDDR4__DENALI_PHY_878__PHY_WRPATH_GATE_TIMING_3_MASK 0x00000700U +#define LPDDR4__DENALI_PHY_878__PHY_WRPATH_GATE_TIMING_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_878__PHY_WRPATH_GATE_TIMING_3_WIDTH 3U +#define LPDDR4__PHY_WRPATH_GATE_TIMING_3__REG DENALI_PHY_878 +#define LPDDR4__PHY_WRPATH_GATE_TIMING_3__FLD LPDDR4__DENALI_PHY_878__PHY_WRPATH_GATE_TIMING_3 + +#define LPDDR4__DENALI_PHY_878__PHY_DATA_DC_INIT_DISABLE_3_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_878__PHY_DATA_DC_INIT_DISABLE_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_878__PHY_DATA_DC_INIT_DISABLE_3_WIDTH 2U +#define LPDDR4__PHY_DATA_DC_INIT_DISABLE_3__REG DENALI_PHY_878 +#define LPDDR4__PHY_DATA_DC_INIT_DISABLE_3__FLD LPDDR4__DENALI_PHY_878__PHY_DATA_DC_INIT_DISABLE_3 + +#define LPDDR4__DENALI_PHY_879_READ_MASK 0x07FF03FFU +#define LPDDR4__DENALI_PHY_879_WRITE_MASK 0x07FF03FFU +#define LPDDR4__DENALI_PHY_879__PHY_DATA_DC_DQS_INIT_SLV_DELAY_3_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_879__PHY_DATA_DC_DQS_INIT_SLV_DELAY_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_879__PHY_DATA_DC_DQS_INIT_SLV_DELAY_3_WIDTH 10U +#define LPDDR4__PHY_DATA_DC_DQS_INIT_SLV_DELAY_3__REG DENALI_PHY_879 +#define LPDDR4__PHY_DATA_DC_DQS_INIT_SLV_DELAY_3__FLD LPDDR4__DENALI_PHY_879__PHY_DATA_DC_DQS_INIT_SLV_DELAY_3 + +#define LPDDR4__DENALI_PHY_879__PHY_DATA_DC_DQ_INIT_SLV_DELAY_3_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_879__PHY_DATA_DC_DQ_INIT_SLV_DELAY_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_879__PHY_DATA_DC_DQ_INIT_SLV_DELAY_3_WIDTH 11U +#define LPDDR4__PHY_DATA_DC_DQ_INIT_SLV_DELAY_3__REG DENALI_PHY_879 +#define LPDDR4__PHY_DATA_DC_DQ_INIT_SLV_DELAY_3__FLD LPDDR4__DENALI_PHY_879__PHY_DATA_DC_DQ_INIT_SLV_DELAY_3 + +#define LPDDR4__DENALI_PHY_880_READ_MASK 0xFFFF0101U +#define LPDDR4__DENALI_PHY_880_WRITE_MASK 0xFFFF0101U +#define LPDDR4__DENALI_PHY_880__PHY_DATA_DC_WRLVL_ENABLE_3_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_880__PHY_DATA_DC_WRLVL_ENABLE_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_880__PHY_DATA_DC_WRLVL_ENABLE_3_WIDTH 1U +#define LPDDR4__DENALI_PHY_880__PHY_DATA_DC_WRLVL_ENABLE_3_WOCLR 0U +#define LPDDR4__DENALI_PHY_880__PHY_DATA_DC_WRLVL_ENABLE_3_WOSET 0U +#define LPDDR4__PHY_DATA_DC_WRLVL_ENABLE_3__REG DENALI_PHY_880 +#define LPDDR4__PHY_DATA_DC_WRLVL_ENABLE_3__FLD LPDDR4__DENALI_PHY_880__PHY_DATA_DC_WRLVL_ENABLE_3 + +#define LPDDR4__DENALI_PHY_880__PHY_DATA_DC_WDQLVL_ENABLE_3_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_880__PHY_DATA_DC_WDQLVL_ENABLE_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_880__PHY_DATA_DC_WDQLVL_ENABLE_3_WIDTH 1U +#define LPDDR4__DENALI_PHY_880__PHY_DATA_DC_WDQLVL_ENABLE_3_WOCLR 0U +#define LPDDR4__DENALI_PHY_880__PHY_DATA_DC_WDQLVL_ENABLE_3_WOSET 0U +#define LPDDR4__PHY_DATA_DC_WDQLVL_ENABLE_3__REG DENALI_PHY_880 +#define LPDDR4__PHY_DATA_DC_WDQLVL_ENABLE_3__FLD LPDDR4__DENALI_PHY_880__PHY_DATA_DC_WDQLVL_ENABLE_3 + +#define LPDDR4__DENALI_PHY_880__PHY_DATA_DC_DM_CLK_SE_THRSHLD_3_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_880__PHY_DATA_DC_DM_CLK_SE_THRSHLD_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_880__PHY_DATA_DC_DM_CLK_SE_THRSHLD_3_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DM_CLK_SE_THRSHLD_3__REG DENALI_PHY_880 +#define LPDDR4__PHY_DATA_DC_DM_CLK_SE_THRSHLD_3__FLD LPDDR4__DENALI_PHY_880__PHY_DATA_DC_DM_CLK_SE_THRSHLD_3 + +#define LPDDR4__DENALI_PHY_880__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_3_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_880__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_880__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_3_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_3__REG DENALI_PHY_880 +#define LPDDR4__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_3__FLD LPDDR4__DENALI_PHY_880__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_3 + +#define LPDDR4__DENALI_PHY_881_READ_MASK 0x001F3F7FU +#define LPDDR4__DENALI_PHY_881_WRITE_MASK 0x001F3F7FU +#define LPDDR4__DENALI_PHY_881__PHY_WDQ_OSC_DELTA_3_MASK 0x0000007FU +#define LPDDR4__DENALI_PHY_881__PHY_WDQ_OSC_DELTA_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_881__PHY_WDQ_OSC_DELTA_3_WIDTH 7U +#define LPDDR4__PHY_WDQ_OSC_DELTA_3__REG DENALI_PHY_881 +#define LPDDR4__PHY_WDQ_OSC_DELTA_3__FLD LPDDR4__DENALI_PHY_881__PHY_WDQ_OSC_DELTA_3 + +#define LPDDR4__DENALI_PHY_881__PHY_MEAS_DLY_STEP_ENABLE_3_MASK 0x00003F00U +#define LPDDR4__DENALI_PHY_881__PHY_MEAS_DLY_STEP_ENABLE_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_881__PHY_MEAS_DLY_STEP_ENABLE_3_WIDTH 6U +#define LPDDR4__PHY_MEAS_DLY_STEP_ENABLE_3__REG DENALI_PHY_881 +#define LPDDR4__PHY_MEAS_DLY_STEP_ENABLE_3__FLD LPDDR4__DENALI_PHY_881__PHY_MEAS_DLY_STEP_ENABLE_3 + +#define LPDDR4__DENALI_PHY_881__PHY_RDDATA_EN_DLY_3_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_881__PHY_RDDATA_EN_DLY_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_881__PHY_RDDATA_EN_DLY_3_WIDTH 5U +#define LPDDR4__PHY_RDDATA_EN_DLY_3__REG DENALI_PHY_881 +#define LPDDR4__PHY_RDDATA_EN_DLY_3__FLD LPDDR4__DENALI_PHY_881__PHY_RDDATA_EN_DLY_3 + +#define LPDDR4__DENALI_PHY_882_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_882_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_882__PHY_DQ_DM_SWIZZLE0_3_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_882__PHY_DQ_DM_SWIZZLE0_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_882__PHY_DQ_DM_SWIZZLE0_3_WIDTH 32U +#define LPDDR4__PHY_DQ_DM_SWIZZLE0_3__REG DENALI_PHY_882 +#define LPDDR4__PHY_DQ_DM_SWIZZLE0_3__FLD LPDDR4__DENALI_PHY_882__PHY_DQ_DM_SWIZZLE0_3 + +#define LPDDR4__DENALI_PHY_883_READ_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_883_WRITE_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_883__PHY_DQ_DM_SWIZZLE1_3_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_883__PHY_DQ_DM_SWIZZLE1_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_883__PHY_DQ_DM_SWIZZLE1_3_WIDTH 4U +#define LPDDR4__PHY_DQ_DM_SWIZZLE1_3__REG DENALI_PHY_883 +#define LPDDR4__PHY_DQ_DM_SWIZZLE1_3__FLD LPDDR4__DENALI_PHY_883__PHY_DQ_DM_SWIZZLE1_3 + +#define LPDDR4__DENALI_PHY_884_READ_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_884_WRITE_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_884__PHY_CLK_WRDQ0_SLAVE_DELAY_3_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_884__PHY_CLK_WRDQ0_SLAVE_DELAY_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_884__PHY_CLK_WRDQ0_SLAVE_DELAY_3_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDQ0_SLAVE_DELAY_3__REG DENALI_PHY_884 +#define LPDDR4__PHY_CLK_WRDQ0_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_884__PHY_CLK_WRDQ0_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_884__PHY_CLK_WRDQ1_SLAVE_DELAY_3_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_884__PHY_CLK_WRDQ1_SLAVE_DELAY_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_884__PHY_CLK_WRDQ1_SLAVE_DELAY_3_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDQ1_SLAVE_DELAY_3__REG DENALI_PHY_884 +#define LPDDR4__PHY_CLK_WRDQ1_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_884__PHY_CLK_WRDQ1_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_885_READ_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_885_WRITE_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_885__PHY_CLK_WRDQ2_SLAVE_DELAY_3_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_885__PHY_CLK_WRDQ2_SLAVE_DELAY_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_885__PHY_CLK_WRDQ2_SLAVE_DELAY_3_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDQ2_SLAVE_DELAY_3__REG DENALI_PHY_885 +#define LPDDR4__PHY_CLK_WRDQ2_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_885__PHY_CLK_WRDQ2_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_885__PHY_CLK_WRDQ3_SLAVE_DELAY_3_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_885__PHY_CLK_WRDQ3_SLAVE_DELAY_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_885__PHY_CLK_WRDQ3_SLAVE_DELAY_3_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDQ3_SLAVE_DELAY_3__REG DENALI_PHY_885 +#define LPDDR4__PHY_CLK_WRDQ3_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_885__PHY_CLK_WRDQ3_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_886_READ_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_886_WRITE_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_886__PHY_CLK_WRDQ4_SLAVE_DELAY_3_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_886__PHY_CLK_WRDQ4_SLAVE_DELAY_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_886__PHY_CLK_WRDQ4_SLAVE_DELAY_3_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDQ4_SLAVE_DELAY_3__REG DENALI_PHY_886 +#define LPDDR4__PHY_CLK_WRDQ4_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_886__PHY_CLK_WRDQ4_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_886__PHY_CLK_WRDQ5_SLAVE_DELAY_3_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_886__PHY_CLK_WRDQ5_SLAVE_DELAY_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_886__PHY_CLK_WRDQ5_SLAVE_DELAY_3_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDQ5_SLAVE_DELAY_3__REG DENALI_PHY_886 +#define LPDDR4__PHY_CLK_WRDQ5_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_886__PHY_CLK_WRDQ5_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_887_READ_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_887_WRITE_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_887__PHY_CLK_WRDQ6_SLAVE_DELAY_3_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_887__PHY_CLK_WRDQ6_SLAVE_DELAY_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_887__PHY_CLK_WRDQ6_SLAVE_DELAY_3_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDQ6_SLAVE_DELAY_3__REG DENALI_PHY_887 +#define LPDDR4__PHY_CLK_WRDQ6_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_887__PHY_CLK_WRDQ6_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_887__PHY_CLK_WRDQ7_SLAVE_DELAY_3_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_887__PHY_CLK_WRDQ7_SLAVE_DELAY_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_887__PHY_CLK_WRDQ7_SLAVE_DELAY_3_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDQ7_SLAVE_DELAY_3__REG DENALI_PHY_887 +#define LPDDR4__PHY_CLK_WRDQ7_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_887__PHY_CLK_WRDQ7_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_888_READ_MASK 0x03FF07FFU +#define LPDDR4__DENALI_PHY_888_WRITE_MASK 0x03FF07FFU +#define LPDDR4__DENALI_PHY_888__PHY_CLK_WRDM_SLAVE_DELAY_3_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_888__PHY_CLK_WRDM_SLAVE_DELAY_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_888__PHY_CLK_WRDM_SLAVE_DELAY_3_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDM_SLAVE_DELAY_3__REG DENALI_PHY_888 +#define LPDDR4__PHY_CLK_WRDM_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_888__PHY_CLK_WRDM_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_888__PHY_CLK_WRDQS_SLAVE_DELAY_3_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_888__PHY_CLK_WRDQS_SLAVE_DELAY_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_888__PHY_CLK_WRDQS_SLAVE_DELAY_3_WIDTH 10U +#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_3__REG DENALI_PHY_888 +#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_888__PHY_CLK_WRDQS_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_889_READ_MASK 0x0003FF03U +#define LPDDR4__DENALI_PHY_889_WRITE_MASK 0x0003FF03U +#define LPDDR4__DENALI_PHY_889__PHY_WRLVL_THRESHOLD_ADJUST_3_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_889__PHY_WRLVL_THRESHOLD_ADJUST_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_889__PHY_WRLVL_THRESHOLD_ADJUST_3_WIDTH 2U +#define LPDDR4__PHY_WRLVL_THRESHOLD_ADJUST_3__REG DENALI_PHY_889 +#define LPDDR4__PHY_WRLVL_THRESHOLD_ADJUST_3__FLD LPDDR4__DENALI_PHY_889__PHY_WRLVL_THRESHOLD_ADJUST_3 + +#define LPDDR4__DENALI_PHY_889__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_3_MASK 0x0003FF00U +#define LPDDR4__DENALI_PHY_889__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_889__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_3_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_3__REG DENALI_PHY_889 +#define LPDDR4__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_889__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_890_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_890_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_890__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_3_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_890__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_890__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_3_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_3__REG DENALI_PHY_890 +#define LPDDR4__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_890__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_890__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_3_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_890__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_890__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_3_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_3__REG DENALI_PHY_890 +#define LPDDR4__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_890__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_891_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_891_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_891__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_3_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_891__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_891__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_3_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_3__REG DENALI_PHY_891 +#define LPDDR4__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_891__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_891__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_3_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_891__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_891__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_3_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_3__REG DENALI_PHY_891 +#define LPDDR4__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_891__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_892_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_892_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_892__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_3_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_892__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_892__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_3_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_3__REG DENALI_PHY_892 +#define LPDDR4__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_892__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_892__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_3_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_892__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_892__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_3_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_3__REG DENALI_PHY_892 +#define LPDDR4__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_892__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_893_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_893_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_893__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_3_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_893__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_893__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_3_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_3__REG DENALI_PHY_893 +#define LPDDR4__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_893__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_893__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_3_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_893__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_893__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_3_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_3__REG DENALI_PHY_893 +#define LPDDR4__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_893__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_894_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_894_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_894__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_3_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_894__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_894__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_3_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_3__REG DENALI_PHY_894 +#define LPDDR4__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_894__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_894__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_3_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_894__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_894__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_3_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_3__REG DENALI_PHY_894 +#define LPDDR4__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_894__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_895_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_895_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_895__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_3_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_895__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_895__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_3_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_3__REG DENALI_PHY_895 +#define LPDDR4__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_895__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_895__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_3_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_895__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_895__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_3_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_3__REG DENALI_PHY_895 +#define LPDDR4__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_895__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_896_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_896_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_896__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_3_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_896__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_896__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_3_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_3__REG DENALI_PHY_896 +#define LPDDR4__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_896__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_896__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_3_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_896__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_896__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_3_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_3__REG DENALI_PHY_896 +#define LPDDR4__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_896__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_897_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_897_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_897__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_3_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_897__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_897__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_3_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_3__REG DENALI_PHY_897 +#define LPDDR4__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_897__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_897__PHY_RDDQS_DM_RISE_SLAVE_DELAY_3_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_897__PHY_RDDQS_DM_RISE_SLAVE_DELAY_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_897__PHY_RDDQS_DM_RISE_SLAVE_DELAY_3_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DM_RISE_SLAVE_DELAY_3__REG DENALI_PHY_897 +#define LPDDR4__PHY_RDDQS_DM_RISE_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_897__PHY_RDDQS_DM_RISE_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_898_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_898_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_898__PHY_RDDQS_DM_FALL_SLAVE_DELAY_3_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_898__PHY_RDDQS_DM_FALL_SLAVE_DELAY_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_898__PHY_RDDQS_DM_FALL_SLAVE_DELAY_3_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DM_FALL_SLAVE_DELAY_3__REG DENALI_PHY_898 +#define LPDDR4__PHY_RDDQS_DM_FALL_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_898__PHY_RDDQS_DM_FALL_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_898__PHY_RDDQS_GATE_SLAVE_DELAY_3_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_898__PHY_RDDQS_GATE_SLAVE_DELAY_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_898__PHY_RDDQS_GATE_SLAVE_DELAY_3_WIDTH 10U +#define LPDDR4__PHY_RDDQS_GATE_SLAVE_DELAY_3__REG DENALI_PHY_898 +#define LPDDR4__PHY_RDDQS_GATE_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_898__PHY_RDDQS_GATE_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_899_READ_MASK 0x03FF070FU +#define LPDDR4__DENALI_PHY_899_WRITE_MASK 0x03FF070FU +#define LPDDR4__DENALI_PHY_899__PHY_RDDQS_LATENCY_ADJUST_3_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_899__PHY_RDDQS_LATENCY_ADJUST_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_899__PHY_RDDQS_LATENCY_ADJUST_3_WIDTH 4U +#define LPDDR4__PHY_RDDQS_LATENCY_ADJUST_3__REG DENALI_PHY_899 +#define LPDDR4__PHY_RDDQS_LATENCY_ADJUST_3__FLD LPDDR4__DENALI_PHY_899__PHY_RDDQS_LATENCY_ADJUST_3 + +#define LPDDR4__DENALI_PHY_899__PHY_WRITE_PATH_LAT_ADD_3_MASK 0x00000700U +#define LPDDR4__DENALI_PHY_899__PHY_WRITE_PATH_LAT_ADD_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_899__PHY_WRITE_PATH_LAT_ADD_3_WIDTH 3U +#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_3__REG DENALI_PHY_899 +#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_3__FLD LPDDR4__DENALI_PHY_899__PHY_WRITE_PATH_LAT_ADD_3 + +#define LPDDR4__DENALI_PHY_899__PHY_WRLVL_DELAY_EARLY_THRESHOLD_3_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_899__PHY_WRLVL_DELAY_EARLY_THRESHOLD_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_899__PHY_WRLVL_DELAY_EARLY_THRESHOLD_3_WIDTH 10U +#define LPDDR4__PHY_WRLVL_DELAY_EARLY_THRESHOLD_3__REG DENALI_PHY_899 +#define LPDDR4__PHY_WRLVL_DELAY_EARLY_THRESHOLD_3__FLD LPDDR4__DENALI_PHY_899__PHY_WRLVL_DELAY_EARLY_THRESHOLD_3 + +#define LPDDR4__DENALI_PHY_900_READ_MASK 0x000103FFU +#define LPDDR4__DENALI_PHY_900_WRITE_MASK 0x000103FFU +#define LPDDR4__DENALI_PHY_900__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_3_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_900__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_900__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_3_WIDTH 10U +#define LPDDR4__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_3__REG DENALI_PHY_900 +#define LPDDR4__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_3__FLD LPDDR4__DENALI_PHY_900__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_3 + +#define LPDDR4__DENALI_PHY_900__PHY_WRLVL_EARLY_FORCE_ZERO_3_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_900__PHY_WRLVL_EARLY_FORCE_ZERO_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_900__PHY_WRLVL_EARLY_FORCE_ZERO_3_WIDTH 1U +#define LPDDR4__DENALI_PHY_900__PHY_WRLVL_EARLY_FORCE_ZERO_3_WOCLR 0U +#define LPDDR4__DENALI_PHY_900__PHY_WRLVL_EARLY_FORCE_ZERO_3_WOSET 0U +#define LPDDR4__PHY_WRLVL_EARLY_FORCE_ZERO_3__REG DENALI_PHY_900 +#define LPDDR4__PHY_WRLVL_EARLY_FORCE_ZERO_3__FLD LPDDR4__DENALI_PHY_900__PHY_WRLVL_EARLY_FORCE_ZERO_3 + +#define LPDDR4__DENALI_PHY_901_READ_MASK 0x000F03FFU +#define LPDDR4__DENALI_PHY_901_WRITE_MASK 0x000F03FFU +#define LPDDR4__DENALI_PHY_901__PHY_GTLVL_RDDQS_SLV_DLY_START_3_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_901__PHY_GTLVL_RDDQS_SLV_DLY_START_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_901__PHY_GTLVL_RDDQS_SLV_DLY_START_3_WIDTH 10U +#define LPDDR4__PHY_GTLVL_RDDQS_SLV_DLY_START_3__REG DENALI_PHY_901 +#define LPDDR4__PHY_GTLVL_RDDQS_SLV_DLY_START_3__FLD LPDDR4__DENALI_PHY_901__PHY_GTLVL_RDDQS_SLV_DLY_START_3 + +#define LPDDR4__DENALI_PHY_901__PHY_GTLVL_LAT_ADJ_START_3_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_901__PHY_GTLVL_LAT_ADJ_START_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_901__PHY_GTLVL_LAT_ADJ_START_3_WIDTH 4U +#define LPDDR4__PHY_GTLVL_LAT_ADJ_START_3__REG DENALI_PHY_901 +#define LPDDR4__PHY_GTLVL_LAT_ADJ_START_3__FLD LPDDR4__DENALI_PHY_901__PHY_GTLVL_LAT_ADJ_START_3 + +#define LPDDR4__DENALI_PHY_902_READ_MASK 0x010F07FFU +#define LPDDR4__DENALI_PHY_902_WRITE_MASK 0x010F07FFU +#define LPDDR4__DENALI_PHY_902__PHY_WDQLVL_DQDM_SLV_DLY_START_3_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_902__PHY_WDQLVL_DQDM_SLV_DLY_START_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_902__PHY_WDQLVL_DQDM_SLV_DLY_START_3_WIDTH 11U +#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_START_3__REG DENALI_PHY_902 +#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_START_3__FLD LPDDR4__DENALI_PHY_902__PHY_WDQLVL_DQDM_SLV_DLY_START_3 + +#define LPDDR4__DENALI_PHY_902__PHY_NTP_WRLAT_START_3_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_902__PHY_NTP_WRLAT_START_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_902__PHY_NTP_WRLAT_START_3_WIDTH 4U +#define LPDDR4__PHY_NTP_WRLAT_START_3__REG DENALI_PHY_902 +#define LPDDR4__PHY_NTP_WRLAT_START_3__FLD LPDDR4__DENALI_PHY_902__PHY_NTP_WRLAT_START_3 + +#define LPDDR4__DENALI_PHY_902__PHY_NTP_PASS_3_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_902__PHY_NTP_PASS_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_902__PHY_NTP_PASS_3_WIDTH 1U +#define LPDDR4__DENALI_PHY_902__PHY_NTP_PASS_3_WOCLR 0U +#define LPDDR4__DENALI_PHY_902__PHY_NTP_PASS_3_WOSET 0U +#define LPDDR4__PHY_NTP_PASS_3__REG DENALI_PHY_902 +#define LPDDR4__PHY_NTP_PASS_3__FLD LPDDR4__DENALI_PHY_902__PHY_NTP_PASS_3 + +#define LPDDR4__DENALI_PHY_903_READ_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_903_WRITE_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_903__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_3_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_903__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_903__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_3_WIDTH 10U +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_3__REG DENALI_PHY_903 +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_3__FLD LPDDR4__DENALI_PHY_903__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_3 + +#define LPDDR4__DENALI_PHY_904_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_904_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_904__PHY_DATA_DC_DQS_CLK_ADJUST_3_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_904__PHY_DATA_DC_DQS_CLK_ADJUST_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_904__PHY_DATA_DC_DQS_CLK_ADJUST_3_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DQS_CLK_ADJUST_3__REG DENALI_PHY_904 +#define LPDDR4__PHY_DATA_DC_DQS_CLK_ADJUST_3__FLD LPDDR4__DENALI_PHY_904__PHY_DATA_DC_DQS_CLK_ADJUST_3 + +#define LPDDR4__DENALI_PHY_904__PHY_DATA_DC_DQ0_CLK_ADJUST_3_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_904__PHY_DATA_DC_DQ0_CLK_ADJUST_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_904__PHY_DATA_DC_DQ0_CLK_ADJUST_3_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DQ0_CLK_ADJUST_3__REG DENALI_PHY_904 +#define LPDDR4__PHY_DATA_DC_DQ0_CLK_ADJUST_3__FLD LPDDR4__DENALI_PHY_904__PHY_DATA_DC_DQ0_CLK_ADJUST_3 + +#define LPDDR4__DENALI_PHY_904__PHY_DATA_DC_DQ1_CLK_ADJUST_3_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_904__PHY_DATA_DC_DQ1_CLK_ADJUST_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_904__PHY_DATA_DC_DQ1_CLK_ADJUST_3_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DQ1_CLK_ADJUST_3__REG DENALI_PHY_904 +#define LPDDR4__PHY_DATA_DC_DQ1_CLK_ADJUST_3__FLD LPDDR4__DENALI_PHY_904__PHY_DATA_DC_DQ1_CLK_ADJUST_3 + +#define LPDDR4__DENALI_PHY_904__PHY_DATA_DC_DQ2_CLK_ADJUST_3_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_904__PHY_DATA_DC_DQ2_CLK_ADJUST_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_904__PHY_DATA_DC_DQ2_CLK_ADJUST_3_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DQ2_CLK_ADJUST_3__REG DENALI_PHY_904 +#define LPDDR4__PHY_DATA_DC_DQ2_CLK_ADJUST_3__FLD LPDDR4__DENALI_PHY_904__PHY_DATA_DC_DQ2_CLK_ADJUST_3 + +#define LPDDR4__DENALI_PHY_905_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_905_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_905__PHY_DATA_DC_DQ3_CLK_ADJUST_3_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_905__PHY_DATA_DC_DQ3_CLK_ADJUST_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_905__PHY_DATA_DC_DQ3_CLK_ADJUST_3_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DQ3_CLK_ADJUST_3__REG DENALI_PHY_905 +#define LPDDR4__PHY_DATA_DC_DQ3_CLK_ADJUST_3__FLD LPDDR4__DENALI_PHY_905__PHY_DATA_DC_DQ3_CLK_ADJUST_3 + +#define LPDDR4__DENALI_PHY_905__PHY_DATA_DC_DQ4_CLK_ADJUST_3_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_905__PHY_DATA_DC_DQ4_CLK_ADJUST_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_905__PHY_DATA_DC_DQ4_CLK_ADJUST_3_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DQ4_CLK_ADJUST_3__REG DENALI_PHY_905 +#define LPDDR4__PHY_DATA_DC_DQ4_CLK_ADJUST_3__FLD LPDDR4__DENALI_PHY_905__PHY_DATA_DC_DQ4_CLK_ADJUST_3 + +#define LPDDR4__DENALI_PHY_905__PHY_DATA_DC_DQ5_CLK_ADJUST_3_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_905__PHY_DATA_DC_DQ5_CLK_ADJUST_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_905__PHY_DATA_DC_DQ5_CLK_ADJUST_3_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DQ5_CLK_ADJUST_3__REG DENALI_PHY_905 +#define LPDDR4__PHY_DATA_DC_DQ5_CLK_ADJUST_3__FLD LPDDR4__DENALI_PHY_905__PHY_DATA_DC_DQ5_CLK_ADJUST_3 + +#define LPDDR4__DENALI_PHY_905__PHY_DATA_DC_DQ6_CLK_ADJUST_3_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_905__PHY_DATA_DC_DQ6_CLK_ADJUST_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_905__PHY_DATA_DC_DQ6_CLK_ADJUST_3_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DQ6_CLK_ADJUST_3__REG DENALI_PHY_905 +#define LPDDR4__PHY_DATA_DC_DQ6_CLK_ADJUST_3__FLD LPDDR4__DENALI_PHY_905__PHY_DATA_DC_DQ6_CLK_ADJUST_3 + +#define LPDDR4__DENALI_PHY_906_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_906_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_906__PHY_DATA_DC_DQ7_CLK_ADJUST_3_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_906__PHY_DATA_DC_DQ7_CLK_ADJUST_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_906__PHY_DATA_DC_DQ7_CLK_ADJUST_3_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DQ7_CLK_ADJUST_3__REG DENALI_PHY_906 +#define LPDDR4__PHY_DATA_DC_DQ7_CLK_ADJUST_3__FLD LPDDR4__DENALI_PHY_906__PHY_DATA_DC_DQ7_CLK_ADJUST_3 + +#define LPDDR4__DENALI_PHY_906__PHY_DATA_DC_DM_CLK_ADJUST_3_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_906__PHY_DATA_DC_DM_CLK_ADJUST_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_906__PHY_DATA_DC_DM_CLK_ADJUST_3_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DM_CLK_ADJUST_3__REG DENALI_PHY_906 +#define LPDDR4__PHY_DATA_DC_DM_CLK_ADJUST_3__FLD LPDDR4__DENALI_PHY_906__PHY_DATA_DC_DM_CLK_ADJUST_3 + +#define LPDDR4__DENALI_PHY_906__PHY_DSLICE_PAD_BOOSTPN_SETTING_3_MASK 0xFFFF0000U +#define LPDDR4__DENALI_PHY_906__PHY_DSLICE_PAD_BOOSTPN_SETTING_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_906__PHY_DSLICE_PAD_BOOSTPN_SETTING_3_WIDTH 16U +#define LPDDR4__PHY_DSLICE_PAD_BOOSTPN_SETTING_3__REG DENALI_PHY_906 +#define LPDDR4__PHY_DSLICE_PAD_BOOSTPN_SETTING_3__FLD LPDDR4__DENALI_PHY_906__PHY_DSLICE_PAD_BOOSTPN_SETTING_3 + +#define LPDDR4__DENALI_PHY_907_READ_MASK 0x0003033FU +#define LPDDR4__DENALI_PHY_907_WRITE_MASK 0x0003033FU +#define LPDDR4__DENALI_PHY_907__PHY_DSLICE_PAD_RX_CTLE_SETTING_3_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_907__PHY_DSLICE_PAD_RX_CTLE_SETTING_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_907__PHY_DSLICE_PAD_RX_CTLE_SETTING_3_WIDTH 6U +#define LPDDR4__PHY_DSLICE_PAD_RX_CTLE_SETTING_3__REG DENALI_PHY_907 +#define LPDDR4__PHY_DSLICE_PAD_RX_CTLE_SETTING_3__FLD LPDDR4__DENALI_PHY_907__PHY_DSLICE_PAD_RX_CTLE_SETTING_3 + +#define LPDDR4__DENALI_PHY_907__PHY_DQ_FFE_3_MASK 0x00000300U +#define LPDDR4__DENALI_PHY_907__PHY_DQ_FFE_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_907__PHY_DQ_FFE_3_WIDTH 2U +#define LPDDR4__PHY_DQ_FFE_3__REG DENALI_PHY_907 +#define LPDDR4__PHY_DQ_FFE_3__FLD LPDDR4__DENALI_PHY_907__PHY_DQ_FFE_3 + +#define LPDDR4__DENALI_PHY_907__PHY_DQS_FFE_3_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_907__PHY_DQS_FFE_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_907__PHY_DQS_FFE_3_WIDTH 2U +#define LPDDR4__PHY_DQS_FFE_3__REG DENALI_PHY_907 +#define LPDDR4__PHY_DQS_FFE_3__FLD LPDDR4__DENALI_PHY_907__PHY_DQS_FFE_3 + +#endif /* REG_LPDDR4_DATA_SLICE_3_MACROS_H_ */ diff --git a/drivers/ram/k3-j721e/lpddr4_ddr_controller_macros.h b/drivers/ram/k3-j721e/lpddr4_ddr_controller_macros.h new file mode 100644 index 0000000..274a976 --- /dev/null +++ b/drivers/ram/k3-j721e/lpddr4_ddr_controller_macros.h @@ -0,0 +1,7793 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/********************************************************************** + * Copyright (C) 2012-2019 Cadence Design Systems, Inc. + * + * THIS FILE IS AUTOMATICALLY GENERATED, DO NOT EDIT + * + ********************************************************************** + */ + +#ifndef REG_LPDDR4_DDR_CONTROLLER_MACROS_H_ +#define REG_LPDDR4_DDR_CONTROLLER_MACROS_H_ + +#define LPDDR4__DENALI_CTL_0_READ_MASK 0xFFFF0F01U +#define LPDDR4__DENALI_CTL_0_WRITE_MASK 0xFFFF0F01U +#define LPDDR4__DENALI_CTL_0__START_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_0__START_SHIFT 0U +#define LPDDR4__DENALI_CTL_0__START_WIDTH 1U +#define LPDDR4__DENALI_CTL_0__START_WOCLR 0U +#define LPDDR4__DENALI_CTL_0__START_WOSET 0U +#define LPDDR4__START__REG DENALI_CTL_0 +#define LPDDR4__START__FLD LPDDR4__DENALI_CTL_0__START + +#define LPDDR4__DENALI_CTL_0__DRAM_CLASS_MASK 0x00000F00U +#define LPDDR4__DENALI_CTL_0__DRAM_CLASS_SHIFT 8U +#define LPDDR4__DENALI_CTL_0__DRAM_CLASS_WIDTH 4U +#define LPDDR4__DRAM_CLASS__REG DENALI_CTL_0 +#define LPDDR4__DRAM_CLASS__FLD LPDDR4__DENALI_CTL_0__DRAM_CLASS + +#define LPDDR4__DENALI_CTL_0__CONTROLLER_ID_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_0__CONTROLLER_ID_SHIFT 16U +#define LPDDR4__DENALI_CTL_0__CONTROLLER_ID_WIDTH 16U +#define LPDDR4__CONTROLLER_ID__REG DENALI_CTL_0 +#define LPDDR4__CONTROLLER_ID__FLD LPDDR4__DENALI_CTL_0__CONTROLLER_ID + +#define LPDDR4__DENALI_CTL_1_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_1_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_1__CONTROLLER_VERSION_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_1__CONTROLLER_VERSION_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_1__CONTROLLER_VERSION_0_WIDTH 32U +#define LPDDR4__CONTROLLER_VERSION_0__REG DENALI_CTL_1 +#define LPDDR4__CONTROLLER_VERSION_0__FLD LPDDR4__DENALI_CTL_1__CONTROLLER_VERSION_0 + +#define LPDDR4__DENALI_CTL_2_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_2_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_2__CONTROLLER_VERSION_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_2__CONTROLLER_VERSION_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_2__CONTROLLER_VERSION_1_WIDTH 32U +#define LPDDR4__CONTROLLER_VERSION_1__REG DENALI_CTL_2 +#define LPDDR4__CONTROLLER_VERSION_1__FLD LPDDR4__DENALI_CTL_2__CONTROLLER_VERSION_1 + +#define LPDDR4__DENALI_CTL_3_READ_MASK 0xFF030F1FU +#define LPDDR4__DENALI_CTL_3_WRITE_MASK 0xFF030F1FU +#define LPDDR4__DENALI_CTL_3__MAX_ROW_REG_MASK 0x0000001FU +#define LPDDR4__DENALI_CTL_3__MAX_ROW_REG_SHIFT 0U +#define LPDDR4__DENALI_CTL_3__MAX_ROW_REG_WIDTH 5U +#define LPDDR4__MAX_ROW_REG__REG DENALI_CTL_3 +#define LPDDR4__MAX_ROW_REG__FLD LPDDR4__DENALI_CTL_3__MAX_ROW_REG + +#define LPDDR4__DENALI_CTL_3__MAX_COL_REG_MASK 0x00000F00U +#define LPDDR4__DENALI_CTL_3__MAX_COL_REG_SHIFT 8U +#define LPDDR4__DENALI_CTL_3__MAX_COL_REG_WIDTH 4U +#define LPDDR4__MAX_COL_REG__REG DENALI_CTL_3 +#define LPDDR4__MAX_COL_REG__FLD LPDDR4__DENALI_CTL_3__MAX_COL_REG + +#define LPDDR4__DENALI_CTL_3__MAX_CS_REG_MASK 0x00030000U +#define LPDDR4__DENALI_CTL_3__MAX_CS_REG_SHIFT 16U +#define LPDDR4__DENALI_CTL_3__MAX_CS_REG_WIDTH 2U +#define LPDDR4__MAX_CS_REG__REG DENALI_CTL_3 +#define LPDDR4__MAX_CS_REG__FLD LPDDR4__DENALI_CTL_3__MAX_CS_REG + +#define LPDDR4__DENALI_CTL_3__READ_DATA_FIFO_DEPTH_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_3__READ_DATA_FIFO_DEPTH_SHIFT 24U +#define LPDDR4__DENALI_CTL_3__READ_DATA_FIFO_DEPTH_WIDTH 8U +#define LPDDR4__READ_DATA_FIFO_DEPTH__REG DENALI_CTL_3 +#define LPDDR4__READ_DATA_FIFO_DEPTH__FLD LPDDR4__DENALI_CTL_3__READ_DATA_FIFO_DEPTH + +#define LPDDR4__DENALI_CTL_4_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_4_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_4__READ_DATA_FIFO_PTR_WIDTH_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_4__READ_DATA_FIFO_PTR_WIDTH_SHIFT 0U +#define LPDDR4__DENALI_CTL_4__READ_DATA_FIFO_PTR_WIDTH_WIDTH 8U +#define LPDDR4__READ_DATA_FIFO_PTR_WIDTH__REG DENALI_CTL_4 +#define LPDDR4__READ_DATA_FIFO_PTR_WIDTH__FLD LPDDR4__DENALI_CTL_4__READ_DATA_FIFO_PTR_WIDTH + +#define LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_DEPTH_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_DEPTH_SHIFT 8U +#define LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_DEPTH_WIDTH 8U +#define LPDDR4__WRITE_DATA_FIFO_DEPTH__REG DENALI_CTL_4 +#define LPDDR4__WRITE_DATA_FIFO_DEPTH__FLD LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_DEPTH + +#define LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_PTR_WIDTH_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_PTR_WIDTH_SHIFT 16U +#define LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_PTR_WIDTH_WIDTH 8U +#define LPDDR4__WRITE_DATA_FIFO_PTR_WIDTH__REG DENALI_CTL_4 +#define LPDDR4__WRITE_DATA_FIFO_PTR_WIDTH__FLD LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_PTR_WIDTH + +#define LPDDR4__DENALI_CTL_5_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_5_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_DEPTH_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_DEPTH_SHIFT 0U +#define LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_DEPTH_WIDTH 16U +#define LPDDR4__MEMCD_RMODW_FIFO_DEPTH__REG DENALI_CTL_5 +#define LPDDR4__MEMCD_RMODW_FIFO_DEPTH__FLD LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_DEPTH + +#define LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_PTR_WIDTH_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_PTR_WIDTH_SHIFT 16U +#define LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_PTR_WIDTH_WIDTH 8U +#define LPDDR4__MEMCD_RMODW_FIFO_PTR_WIDTH__REG DENALI_CTL_5 +#define LPDDR4__MEMCD_RMODW_FIFO_PTR_WIDTH__FLD LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_PTR_WIDTH + +#define LPDDR4__DENALI_CTL_5__ASYNC_CDC_STAGES_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_5__ASYNC_CDC_STAGES_SHIFT 24U +#define LPDDR4__DENALI_CTL_5__ASYNC_CDC_STAGES_WIDTH 8U +#define LPDDR4__ASYNC_CDC_STAGES__REG DENALI_CTL_5 +#define LPDDR4__ASYNC_CDC_STAGES__FLD LPDDR4__DENALI_CTL_5__ASYNC_CDC_STAGES + +#define LPDDR4__DENALI_CTL_6_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_6_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_6__AXI0_CMDFIFO_LOG2_DEPTH_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_6__AXI0_CMDFIFO_LOG2_DEPTH_SHIFT 0U +#define LPDDR4__DENALI_CTL_6__AXI0_CMDFIFO_LOG2_DEPTH_WIDTH 8U +#define LPDDR4__AXI0_CMDFIFO_LOG2_DEPTH__REG DENALI_CTL_6 +#define LPDDR4__AXI0_CMDFIFO_LOG2_DEPTH__FLD LPDDR4__DENALI_CTL_6__AXI0_CMDFIFO_LOG2_DEPTH + +#define LPDDR4__DENALI_CTL_6__AXI0_RDFIFO_LOG2_DEPTH_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_6__AXI0_RDFIFO_LOG2_DEPTH_SHIFT 8U +#define LPDDR4__DENALI_CTL_6__AXI0_RDFIFO_LOG2_DEPTH_WIDTH 8U +#define LPDDR4__AXI0_RDFIFO_LOG2_DEPTH__REG DENALI_CTL_6 +#define LPDDR4__AXI0_RDFIFO_LOG2_DEPTH__FLD LPDDR4__DENALI_CTL_6__AXI0_RDFIFO_LOG2_DEPTH + +#define LPDDR4__DENALI_CTL_6__AXI0_WR_ARRAY_LOG2_DEPTH_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_6__AXI0_WR_ARRAY_LOG2_DEPTH_SHIFT 16U +#define LPDDR4__DENALI_CTL_6__AXI0_WR_ARRAY_LOG2_DEPTH_WIDTH 8U +#define LPDDR4__AXI0_WR_ARRAY_LOG2_DEPTH__REG DENALI_CTL_6 +#define LPDDR4__AXI0_WR_ARRAY_LOG2_DEPTH__FLD LPDDR4__DENALI_CTL_6__AXI0_WR_ARRAY_LOG2_DEPTH + +#define LPDDR4__DENALI_CTL_6__AXI0_WRCMD_PROC_FIFO_LOG2_DEPTH_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_6__AXI0_WRCMD_PROC_FIFO_LOG2_DEPTH_SHIFT 24U +#define LPDDR4__DENALI_CTL_6__AXI0_WRCMD_PROC_FIFO_LOG2_DEPTH_WIDTH 8U +#define LPDDR4__AXI0_WRCMD_PROC_FIFO_LOG2_DEPTH__REG DENALI_CTL_6 +#define LPDDR4__AXI0_WRCMD_PROC_FIFO_LOG2_DEPTH__FLD LPDDR4__DENALI_CTL_6__AXI0_WRCMD_PROC_FIFO_LOG2_DEPTH + +#define LPDDR4__DENALI_CTL_7_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_7_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_7__TINIT_F0_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_7__TINIT_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_7__TINIT_F0_WIDTH 24U +#define LPDDR4__TINIT_F0__REG DENALI_CTL_7 +#define LPDDR4__TINIT_F0__FLD LPDDR4__DENALI_CTL_7__TINIT_F0 + +#define LPDDR4__DENALI_CTL_8_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_8_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_8__TINIT3_F0_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_8__TINIT3_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_8__TINIT3_F0_WIDTH 24U +#define LPDDR4__TINIT3_F0__REG DENALI_CTL_8 +#define LPDDR4__TINIT3_F0__FLD LPDDR4__DENALI_CTL_8__TINIT3_F0 + +#define LPDDR4__DENALI_CTL_9_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_9_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_9__TINIT4_F0_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_9__TINIT4_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_9__TINIT4_F0_WIDTH 24U +#define LPDDR4__TINIT4_F0__REG DENALI_CTL_9 +#define LPDDR4__TINIT4_F0__FLD LPDDR4__DENALI_CTL_9__TINIT4_F0 + +#define LPDDR4__DENALI_CTL_10_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_10_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_10__TINIT5_F0_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_10__TINIT5_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_10__TINIT5_F0_WIDTH 24U +#define LPDDR4__TINIT5_F0__REG DENALI_CTL_10 +#define LPDDR4__TINIT5_F0__FLD LPDDR4__DENALI_CTL_10__TINIT5_F0 + +#define LPDDR4__DENALI_CTL_11_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_11_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_11__TINIT_F1_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_11__TINIT_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_11__TINIT_F1_WIDTH 24U +#define LPDDR4__TINIT_F1__REG DENALI_CTL_11 +#define LPDDR4__TINIT_F1__FLD LPDDR4__DENALI_CTL_11__TINIT_F1 + +#define LPDDR4__DENALI_CTL_12_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_12_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_12__TINIT3_F1_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_12__TINIT3_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_12__TINIT3_F1_WIDTH 24U +#define LPDDR4__TINIT3_F1__REG DENALI_CTL_12 +#define LPDDR4__TINIT3_F1__FLD LPDDR4__DENALI_CTL_12__TINIT3_F1 + +#define LPDDR4__DENALI_CTL_13_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_13_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_13__TINIT4_F1_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_13__TINIT4_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_13__TINIT4_F1_WIDTH 24U +#define LPDDR4__TINIT4_F1__REG DENALI_CTL_13 +#define LPDDR4__TINIT4_F1__FLD LPDDR4__DENALI_CTL_13__TINIT4_F1 + +#define LPDDR4__DENALI_CTL_14_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_14_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_14__TINIT5_F1_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_14__TINIT5_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_14__TINIT5_F1_WIDTH 24U +#define LPDDR4__TINIT5_F1__REG DENALI_CTL_14 +#define LPDDR4__TINIT5_F1__FLD LPDDR4__DENALI_CTL_14__TINIT5_F1 + +#define LPDDR4__DENALI_CTL_15_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_15_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_15__TINIT_F2_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_15__TINIT_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_15__TINIT_F2_WIDTH 24U +#define LPDDR4__TINIT_F2__REG DENALI_CTL_15 +#define LPDDR4__TINIT_F2__FLD LPDDR4__DENALI_CTL_15__TINIT_F2 + +#define LPDDR4__DENALI_CTL_16_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_16_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_16__TINIT3_F2_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_16__TINIT3_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_16__TINIT3_F2_WIDTH 24U +#define LPDDR4__TINIT3_F2__REG DENALI_CTL_16 +#define LPDDR4__TINIT3_F2__FLD LPDDR4__DENALI_CTL_16__TINIT3_F2 + +#define LPDDR4__DENALI_CTL_17_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_17_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_17__TINIT4_F2_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_17__TINIT4_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_17__TINIT4_F2_WIDTH 24U +#define LPDDR4__TINIT4_F2__REG DENALI_CTL_17 +#define LPDDR4__TINIT4_F2__FLD LPDDR4__DENALI_CTL_17__TINIT4_F2 + +#define LPDDR4__DENALI_CTL_18_READ_MASK 0x01FFFFFFU +#define LPDDR4__DENALI_CTL_18_WRITE_MASK 0x01FFFFFFU +#define LPDDR4__DENALI_CTL_18__TINIT5_F2_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_18__TINIT5_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_18__TINIT5_F2_WIDTH 24U +#define LPDDR4__TINIT5_F2__REG DENALI_CTL_18 +#define LPDDR4__TINIT5_F2__FLD LPDDR4__DENALI_CTL_18__TINIT5_F2 + +#define LPDDR4__DENALI_CTL_18__NO_AUTO_MRR_INIT_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_18__NO_AUTO_MRR_INIT_SHIFT 24U +#define LPDDR4__DENALI_CTL_18__NO_AUTO_MRR_INIT_WIDTH 1U +#define LPDDR4__DENALI_CTL_18__NO_AUTO_MRR_INIT_WOCLR 0U +#define LPDDR4__DENALI_CTL_18__NO_AUTO_MRR_INIT_WOSET 0U +#define LPDDR4__NO_AUTO_MRR_INIT__REG DENALI_CTL_18 +#define LPDDR4__NO_AUTO_MRR_INIT__FLD LPDDR4__DENALI_CTL_18__NO_AUTO_MRR_INIT + +#define LPDDR4__DENALI_CTL_19_READ_MASK 0x01010101U +#define LPDDR4__DENALI_CTL_19_WRITE_MASK 0x01010101U +#define LPDDR4__DENALI_CTL_19__MRR_ERROR_STATUS_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_19__MRR_ERROR_STATUS_SHIFT 0U +#define LPDDR4__DENALI_CTL_19__MRR_ERROR_STATUS_WIDTH 1U +#define LPDDR4__DENALI_CTL_19__MRR_ERROR_STATUS_WOCLR 0U +#define LPDDR4__DENALI_CTL_19__MRR_ERROR_STATUS_WOSET 0U +#define LPDDR4__MRR_ERROR_STATUS__REG DENALI_CTL_19 +#define LPDDR4__MRR_ERROR_STATUS__FLD LPDDR4__DENALI_CTL_19__MRR_ERROR_STATUS + +#define LPDDR4__DENALI_CTL_19__DFI_INV_DATA_CS_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_19__DFI_INV_DATA_CS_SHIFT 8U +#define LPDDR4__DENALI_CTL_19__DFI_INV_DATA_CS_WIDTH 1U +#define LPDDR4__DENALI_CTL_19__DFI_INV_DATA_CS_WOCLR 0U +#define LPDDR4__DENALI_CTL_19__DFI_INV_DATA_CS_WOSET 0U +#define LPDDR4__DFI_INV_DATA_CS__REG DENALI_CTL_19 +#define LPDDR4__DFI_INV_DATA_CS__FLD LPDDR4__DENALI_CTL_19__DFI_INV_DATA_CS + +#define LPDDR4__DENALI_CTL_19__NO_MRW_INIT_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_19__NO_MRW_INIT_SHIFT 16U +#define LPDDR4__DENALI_CTL_19__NO_MRW_INIT_WIDTH 1U +#define LPDDR4__DENALI_CTL_19__NO_MRW_INIT_WOCLR 0U +#define LPDDR4__DENALI_CTL_19__NO_MRW_INIT_WOSET 0U +#define LPDDR4__NO_MRW_INIT__REG DENALI_CTL_19 +#define LPDDR4__NO_MRW_INIT__FLD LPDDR4__DENALI_CTL_19__NO_MRW_INIT + +#define LPDDR4__DENALI_CTL_19__ODT_VALUE_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_19__ODT_VALUE_SHIFT 24U +#define LPDDR4__DENALI_CTL_19__ODT_VALUE_WIDTH 1U +#define LPDDR4__DENALI_CTL_19__ODT_VALUE_WOCLR 0U +#define LPDDR4__DENALI_CTL_19__ODT_VALUE_WOSET 0U +#define LPDDR4__ODT_VALUE__REG DENALI_CTL_19 +#define LPDDR4__ODT_VALUE__FLD LPDDR4__DENALI_CTL_19__ODT_VALUE + +#define LPDDR4__DENALI_CTL_20_READ_MASK 0x03013F01U +#define LPDDR4__DENALI_CTL_20_WRITE_MASK 0x03013F01U +#define LPDDR4__DENALI_CTL_20__PHY_INDEP_TRAIN_MODE_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_20__PHY_INDEP_TRAIN_MODE_SHIFT 0U +#define LPDDR4__DENALI_CTL_20__PHY_INDEP_TRAIN_MODE_WIDTH 1U +#define LPDDR4__DENALI_CTL_20__PHY_INDEP_TRAIN_MODE_WOCLR 0U +#define LPDDR4__DENALI_CTL_20__PHY_INDEP_TRAIN_MODE_WOSET 0U +#define LPDDR4__PHY_INDEP_TRAIN_MODE__REG DENALI_CTL_20 +#define LPDDR4__PHY_INDEP_TRAIN_MODE__FLD LPDDR4__DENALI_CTL_20__PHY_INDEP_TRAIN_MODE + +#define LPDDR4__DENALI_CTL_20__TSREF2PHYMSTR_MASK 0x00003F00U +#define LPDDR4__DENALI_CTL_20__TSREF2PHYMSTR_SHIFT 8U +#define LPDDR4__DENALI_CTL_20__TSREF2PHYMSTR_WIDTH 6U +#define LPDDR4__TSREF2PHYMSTR__REG DENALI_CTL_20 +#define LPDDR4__TSREF2PHYMSTR__FLD LPDDR4__DENALI_CTL_20__TSREF2PHYMSTR + +#define LPDDR4__DENALI_CTL_20__PHY_INDEP_INIT_MODE_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_20__PHY_INDEP_INIT_MODE_SHIFT 16U +#define LPDDR4__DENALI_CTL_20__PHY_INDEP_INIT_MODE_WIDTH 1U +#define LPDDR4__DENALI_CTL_20__PHY_INDEP_INIT_MODE_WOCLR 0U +#define LPDDR4__DENALI_CTL_20__PHY_INDEP_INIT_MODE_WOSET 0U +#define LPDDR4__PHY_INDEP_INIT_MODE__REG DENALI_CTL_20 +#define LPDDR4__PHY_INDEP_INIT_MODE__FLD LPDDR4__DENALI_CTL_20__PHY_INDEP_INIT_MODE + +#define LPDDR4__DENALI_CTL_20__DFIBUS_FREQ_INIT_MASK 0x03000000U +#define LPDDR4__DENALI_CTL_20__DFIBUS_FREQ_INIT_SHIFT 24U +#define LPDDR4__DENALI_CTL_20__DFIBUS_FREQ_INIT_WIDTH 2U +#define LPDDR4__DFIBUS_FREQ_INIT__REG DENALI_CTL_20 +#define LPDDR4__DFIBUS_FREQ_INIT__FLD LPDDR4__DENALI_CTL_20__DFIBUS_FREQ_INIT + +#define LPDDR4__DENALI_CTL_21_READ_MASK 0x1F1F1F03U +#define LPDDR4__DENALI_CTL_21_WRITE_MASK 0x1F1F1F03U +#define LPDDR4__DENALI_CTL_21__DFIBUS_BOOT_FREQ_MASK 0x00000003U +#define LPDDR4__DENALI_CTL_21__DFIBUS_BOOT_FREQ_SHIFT 0U +#define LPDDR4__DENALI_CTL_21__DFIBUS_BOOT_FREQ_WIDTH 2U +#define LPDDR4__DFIBUS_BOOT_FREQ__REG DENALI_CTL_21 +#define LPDDR4__DFIBUS_BOOT_FREQ__FLD LPDDR4__DENALI_CTL_21__DFIBUS_BOOT_FREQ + +#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F0_MASK 0x00001F00U +#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F0_SHIFT 8U +#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F0_WIDTH 5U +#define LPDDR4__DFIBUS_FREQ_F0__REG DENALI_CTL_21 +#define LPDDR4__DFIBUS_FREQ_F0__FLD LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F0 + +#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F1_MASK 0x001F0000U +#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F1_WIDTH 5U +#define LPDDR4__DFIBUS_FREQ_F1__REG DENALI_CTL_21 +#define LPDDR4__DFIBUS_FREQ_F1__FLD LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F1 + +#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F2_MASK 0x1F000000U +#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F2_SHIFT 24U +#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F2_WIDTH 5U +#define LPDDR4__DFIBUS_FREQ_F2__REG DENALI_CTL_21 +#define LPDDR4__DFIBUS_FREQ_F2__FLD LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F2 + +#define LPDDR4__DENALI_CTL_22_READ_MASK 0x00030303U +#define LPDDR4__DENALI_CTL_22_WRITE_MASK 0x00030303U +#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F0_MASK 0x00000003U +#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F0_WIDTH 2U +#define LPDDR4__FREQ_CHANGE_TYPE_F0__REG DENALI_CTL_22 +#define LPDDR4__FREQ_CHANGE_TYPE_F0__FLD LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F0 + +#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F1_MASK 0x00000300U +#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F1_SHIFT 8U +#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F1_WIDTH 2U +#define LPDDR4__FREQ_CHANGE_TYPE_F1__REG DENALI_CTL_22 +#define LPDDR4__FREQ_CHANGE_TYPE_F1__FLD LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F1 + +#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F2_MASK 0x00030000U +#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F2_WIDTH 2U +#define LPDDR4__FREQ_CHANGE_TYPE_F2__REG DENALI_CTL_22 +#define LPDDR4__FREQ_CHANGE_TYPE_F2__FLD LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F2 + +#define LPDDR4__DENALI_CTL_23_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_23_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_23__TRST_PWRON_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_23__TRST_PWRON_SHIFT 0U +#define LPDDR4__DENALI_CTL_23__TRST_PWRON_WIDTH 32U +#define LPDDR4__TRST_PWRON__REG DENALI_CTL_23 +#define LPDDR4__TRST_PWRON__FLD LPDDR4__DENALI_CTL_23__TRST_PWRON + +#define LPDDR4__DENALI_CTL_24_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_24_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_24__CKE_INACTIVE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_24__CKE_INACTIVE_SHIFT 0U +#define LPDDR4__DENALI_CTL_24__CKE_INACTIVE_WIDTH 32U +#define LPDDR4__CKE_INACTIVE__REG DENALI_CTL_24 +#define LPDDR4__CKE_INACTIVE__FLD LPDDR4__DENALI_CTL_24__CKE_INACTIVE + +#define LPDDR4__DENALI_CTL_25_READ_MASK 0xFFFFFF01U +#define LPDDR4__DENALI_CTL_25_WRITE_MASK 0xFFFFFF01U +#define LPDDR4__DENALI_CTL_25__MC_RESERVED0_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_25__MC_RESERVED0_SHIFT 0U +#define LPDDR4__DENALI_CTL_25__MC_RESERVED0_WIDTH 1U +#define LPDDR4__DENALI_CTL_25__MC_RESERVED0_WOCLR 0U +#define LPDDR4__DENALI_CTL_25__MC_RESERVED0_WOSET 0U +#define LPDDR4__MC_RESERVED0__REG DENALI_CTL_25 +#define LPDDR4__MC_RESERVED0__FLD LPDDR4__DENALI_CTL_25__MC_RESERVED0 + +#define LPDDR4__DENALI_CTL_25__MC_RESERVED1_MASK 0xFFFFFF00U +#define LPDDR4__DENALI_CTL_25__MC_RESERVED1_SHIFT 8U +#define LPDDR4__DENALI_CTL_25__MC_RESERVED1_WIDTH 24U +#define LPDDR4__MC_RESERVED1__REG DENALI_CTL_25 +#define LPDDR4__MC_RESERVED1__FLD LPDDR4__DENALI_CTL_25__MC_RESERVED1 + +#define LPDDR4__DENALI_CTL_26_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_26_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_26__MC_RESERVED2_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_26__MC_RESERVED2_SHIFT 0U +#define LPDDR4__DENALI_CTL_26__MC_RESERVED2_WIDTH 8U +#define LPDDR4__MC_RESERVED2__REG DENALI_CTL_26 +#define LPDDR4__MC_RESERVED2__FLD LPDDR4__DENALI_CTL_26__MC_RESERVED2 + +#define LPDDR4__DENALI_CTL_26__MC_RESERVED3_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_26__MC_RESERVED3_SHIFT 8U +#define LPDDR4__DENALI_CTL_26__MC_RESERVED3_WIDTH 8U +#define LPDDR4__MC_RESERVED3__REG DENALI_CTL_26 +#define LPDDR4__MC_RESERVED3__FLD LPDDR4__DENALI_CTL_26__MC_RESERVED3 + +#define LPDDR4__DENALI_CTL_26__DQS_OSC_ENABLE_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_26__DQS_OSC_ENABLE_SHIFT 16U +#define LPDDR4__DENALI_CTL_26__DQS_OSC_ENABLE_WIDTH 1U +#define LPDDR4__DENALI_CTL_26__DQS_OSC_ENABLE_WOCLR 0U +#define LPDDR4__DENALI_CTL_26__DQS_OSC_ENABLE_WOSET 0U +#define LPDDR4__DQS_OSC_ENABLE__REG DENALI_CTL_26 +#define LPDDR4__DQS_OSC_ENABLE__FLD LPDDR4__DENALI_CTL_26__DQS_OSC_ENABLE + +#define LPDDR4__DENALI_CTL_27_READ_MASK 0xFF0F7FFFU +#define LPDDR4__DENALI_CTL_27_WRITE_MASK 0xFF0F7FFFU +#define LPDDR4__DENALI_CTL_27__DQS_OSC_PERIOD_MASK 0x00007FFFU +#define LPDDR4__DENALI_CTL_27__DQS_OSC_PERIOD_SHIFT 0U +#define LPDDR4__DENALI_CTL_27__DQS_OSC_PERIOD_WIDTH 15U +#define LPDDR4__DQS_OSC_PERIOD__REG DENALI_CTL_27 +#define LPDDR4__DQS_OSC_PERIOD__FLD LPDDR4__DENALI_CTL_27__DQS_OSC_PERIOD + +#define LPDDR4__DENALI_CTL_27__FUNC_VALID_CYCLES_MASK 0x000F0000U +#define LPDDR4__DENALI_CTL_27__FUNC_VALID_CYCLES_SHIFT 16U +#define LPDDR4__DENALI_CTL_27__FUNC_VALID_CYCLES_WIDTH 4U +#define LPDDR4__FUNC_VALID_CYCLES__REG DENALI_CTL_27 +#define LPDDR4__FUNC_VALID_CYCLES__FLD LPDDR4__DENALI_CTL_27__FUNC_VALID_CYCLES + +#define LPDDR4__DENALI_CTL_27__TOSCO_F0_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_27__TOSCO_F0_SHIFT 24U +#define LPDDR4__DENALI_CTL_27__TOSCO_F0_WIDTH 8U +#define LPDDR4__TOSCO_F0__REG DENALI_CTL_27 +#define LPDDR4__TOSCO_F0__FLD LPDDR4__DENALI_CTL_27__TOSCO_F0 + +#define LPDDR4__DENALI_CTL_28_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_28_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_28__TOSCO_F1_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_28__TOSCO_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_28__TOSCO_F1_WIDTH 8U +#define LPDDR4__TOSCO_F1__REG DENALI_CTL_28 +#define LPDDR4__TOSCO_F1__FLD LPDDR4__DENALI_CTL_28__TOSCO_F1 + +#define LPDDR4__DENALI_CTL_28__TOSCO_F2_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_28__TOSCO_F2_SHIFT 8U +#define LPDDR4__DENALI_CTL_28__TOSCO_F2_WIDTH 8U +#define LPDDR4__TOSCO_F2__REG DENALI_CTL_28 +#define LPDDR4__TOSCO_F2__FLD LPDDR4__DENALI_CTL_28__TOSCO_F2 + +#define LPDDR4__DENALI_CTL_28__DQS_OSC_NORM_THRESHOLD_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_28__DQS_OSC_NORM_THRESHOLD_SHIFT 16U +#define LPDDR4__DENALI_CTL_28__DQS_OSC_NORM_THRESHOLD_WIDTH 8U +#define LPDDR4__DQS_OSC_NORM_THRESHOLD__REG DENALI_CTL_28 +#define LPDDR4__DQS_OSC_NORM_THRESHOLD__FLD LPDDR4__DENALI_CTL_28__DQS_OSC_NORM_THRESHOLD + +#define LPDDR4__DENALI_CTL_28__DQS_OSC_HIGH_THRESHOLD_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_28__DQS_OSC_HIGH_THRESHOLD_SHIFT 24U +#define LPDDR4__DENALI_CTL_28__DQS_OSC_HIGH_THRESHOLD_WIDTH 8U +#define LPDDR4__DQS_OSC_HIGH_THRESHOLD__REG DENALI_CTL_28 +#define LPDDR4__DQS_OSC_HIGH_THRESHOLD__FLD LPDDR4__DENALI_CTL_28__DQS_OSC_HIGH_THRESHOLD + +#define LPDDR4__DENALI_CTL_29_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_29_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_29__DQS_OSC_TIMEOUT_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_29__DQS_OSC_TIMEOUT_SHIFT 0U +#define LPDDR4__DENALI_CTL_29__DQS_OSC_TIMEOUT_WIDTH 8U +#define LPDDR4__DQS_OSC_TIMEOUT__REG DENALI_CTL_29 +#define LPDDR4__DQS_OSC_TIMEOUT__FLD LPDDR4__DENALI_CTL_29__DQS_OSC_TIMEOUT + +#define LPDDR4__DENALI_CTL_29__DQS_OSC_PROMOTE_THRESHOLD_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_29__DQS_OSC_PROMOTE_THRESHOLD_SHIFT 8U +#define LPDDR4__DENALI_CTL_29__DQS_OSC_PROMOTE_THRESHOLD_WIDTH 8U +#define LPDDR4__DQS_OSC_PROMOTE_THRESHOLD__REG DENALI_CTL_29 +#define LPDDR4__DQS_OSC_PROMOTE_THRESHOLD__FLD LPDDR4__DENALI_CTL_29__DQS_OSC_PROMOTE_THRESHOLD + +#define LPDDR4__DENALI_CTL_29__OSC_VARIANCE_LIMIT_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_29__OSC_VARIANCE_LIMIT_SHIFT 16U +#define LPDDR4__DENALI_CTL_29__OSC_VARIANCE_LIMIT_WIDTH 16U +#define LPDDR4__OSC_VARIANCE_LIMIT__REG DENALI_CTL_29 +#define LPDDR4__OSC_VARIANCE_LIMIT__FLD LPDDR4__DENALI_CTL_29__OSC_VARIANCE_LIMIT + +#define LPDDR4__DENALI_CTL_30_READ_MASK 0x00FFFF00U +#define LPDDR4__DENALI_CTL_30_WRITE_MASK 0x00FFFF00U +#define LPDDR4__DENALI_CTL_30__DQS_OSC_REQUEST_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_30__DQS_OSC_REQUEST_SHIFT 0U +#define LPDDR4__DENALI_CTL_30__DQS_OSC_REQUEST_WIDTH 1U +#define LPDDR4__DENALI_CTL_30__DQS_OSC_REQUEST_WOCLR 0U +#define LPDDR4__DENALI_CTL_30__DQS_OSC_REQUEST_WOSET 0U +#define LPDDR4__DQS_OSC_REQUEST__REG DENALI_CTL_30 +#define LPDDR4__DQS_OSC_REQUEST__FLD LPDDR4__DENALI_CTL_30__DQS_OSC_REQUEST + +#define LPDDR4__DENALI_CTL_30__OSC_BASE_VALUE_0_CS0_MASK 0x00FFFF00U +#define LPDDR4__DENALI_CTL_30__OSC_BASE_VALUE_0_CS0_SHIFT 8U +#define LPDDR4__DENALI_CTL_30__OSC_BASE_VALUE_0_CS0_WIDTH 16U +#define LPDDR4__OSC_BASE_VALUE_0_CS0__REG DENALI_CTL_30 +#define LPDDR4__OSC_BASE_VALUE_0_CS0__FLD LPDDR4__DENALI_CTL_30__OSC_BASE_VALUE_0_CS0 + +#define LPDDR4__DENALI_CTL_31_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_31_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_31__OSC_BASE_VALUE_1_CS0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_31__OSC_BASE_VALUE_1_CS0_SHIFT 0U +#define LPDDR4__DENALI_CTL_31__OSC_BASE_VALUE_1_CS0_WIDTH 16U +#define LPDDR4__OSC_BASE_VALUE_1_CS0__REG DENALI_CTL_31 +#define LPDDR4__OSC_BASE_VALUE_1_CS0__FLD LPDDR4__DENALI_CTL_31__OSC_BASE_VALUE_1_CS0 + +#define LPDDR4__DENALI_CTL_31__OSC_BASE_VALUE_2_CS0_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_31__OSC_BASE_VALUE_2_CS0_SHIFT 16U +#define LPDDR4__DENALI_CTL_31__OSC_BASE_VALUE_2_CS0_WIDTH 16U +#define LPDDR4__OSC_BASE_VALUE_2_CS0__REG DENALI_CTL_31 +#define LPDDR4__OSC_BASE_VALUE_2_CS0__FLD LPDDR4__DENALI_CTL_31__OSC_BASE_VALUE_2_CS0 + +#define LPDDR4__DENALI_CTL_32_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_32_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_32__OSC_BASE_VALUE_3_CS0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_32__OSC_BASE_VALUE_3_CS0_SHIFT 0U +#define LPDDR4__DENALI_CTL_32__OSC_BASE_VALUE_3_CS0_WIDTH 16U +#define LPDDR4__OSC_BASE_VALUE_3_CS0__REG DENALI_CTL_32 +#define LPDDR4__OSC_BASE_VALUE_3_CS0__FLD LPDDR4__DENALI_CTL_32__OSC_BASE_VALUE_3_CS0 + +#define LPDDR4__DENALI_CTL_32__OSC_BASE_VALUE_0_CS1_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_32__OSC_BASE_VALUE_0_CS1_SHIFT 16U +#define LPDDR4__DENALI_CTL_32__OSC_BASE_VALUE_0_CS1_WIDTH 16U +#define LPDDR4__OSC_BASE_VALUE_0_CS1__REG DENALI_CTL_32 +#define LPDDR4__OSC_BASE_VALUE_0_CS1__FLD LPDDR4__DENALI_CTL_32__OSC_BASE_VALUE_0_CS1 + +#define LPDDR4__DENALI_CTL_33_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_33_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_33__OSC_BASE_VALUE_1_CS1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_33__OSC_BASE_VALUE_1_CS1_SHIFT 0U +#define LPDDR4__DENALI_CTL_33__OSC_BASE_VALUE_1_CS1_WIDTH 16U +#define LPDDR4__OSC_BASE_VALUE_1_CS1__REG DENALI_CTL_33 +#define LPDDR4__OSC_BASE_VALUE_1_CS1__FLD LPDDR4__DENALI_CTL_33__OSC_BASE_VALUE_1_CS1 + +#define LPDDR4__DENALI_CTL_33__OSC_BASE_VALUE_2_CS1_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_33__OSC_BASE_VALUE_2_CS1_SHIFT 16U +#define LPDDR4__DENALI_CTL_33__OSC_BASE_VALUE_2_CS1_WIDTH 16U +#define LPDDR4__OSC_BASE_VALUE_2_CS1__REG DENALI_CTL_33 +#define LPDDR4__OSC_BASE_VALUE_2_CS1__FLD LPDDR4__DENALI_CTL_33__OSC_BASE_VALUE_2_CS1 + +#define LPDDR4__DENALI_CTL_34_READ_MASK 0x7F7FFFFFU +#define LPDDR4__DENALI_CTL_34_WRITE_MASK 0x7F7FFFFFU +#define LPDDR4__DENALI_CTL_34__OSC_BASE_VALUE_3_CS1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_34__OSC_BASE_VALUE_3_CS1_SHIFT 0U +#define LPDDR4__DENALI_CTL_34__OSC_BASE_VALUE_3_CS1_WIDTH 16U +#define LPDDR4__OSC_BASE_VALUE_3_CS1__REG DENALI_CTL_34 +#define LPDDR4__OSC_BASE_VALUE_3_CS1__FLD LPDDR4__DENALI_CTL_34__OSC_BASE_VALUE_3_CS1 + +#define LPDDR4__DENALI_CTL_34__CASLAT_LIN_F0_MASK 0x007F0000U +#define LPDDR4__DENALI_CTL_34__CASLAT_LIN_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_34__CASLAT_LIN_F0_WIDTH 7U +#define LPDDR4__CASLAT_LIN_F0__REG DENALI_CTL_34 +#define LPDDR4__CASLAT_LIN_F0__FLD LPDDR4__DENALI_CTL_34__CASLAT_LIN_F0 + +#define LPDDR4__DENALI_CTL_34__WRLAT_F0_MASK 0x7F000000U +#define LPDDR4__DENALI_CTL_34__WRLAT_F0_SHIFT 24U +#define LPDDR4__DENALI_CTL_34__WRLAT_F0_WIDTH 7U +#define LPDDR4__WRLAT_F0__REG DENALI_CTL_34 +#define LPDDR4__WRLAT_F0__FLD LPDDR4__DENALI_CTL_34__WRLAT_F0 + +#define LPDDR4__DENALI_CTL_35_READ_MASK 0x7F7F7F7FU +#define LPDDR4__DENALI_CTL_35_WRITE_MASK 0x7F7F7F7FU +#define LPDDR4__DENALI_CTL_35__CASLAT_LIN_F1_MASK 0x0000007FU +#define LPDDR4__DENALI_CTL_35__CASLAT_LIN_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_35__CASLAT_LIN_F1_WIDTH 7U +#define LPDDR4__CASLAT_LIN_F1__REG DENALI_CTL_35 +#define LPDDR4__CASLAT_LIN_F1__FLD LPDDR4__DENALI_CTL_35__CASLAT_LIN_F1 + +#define LPDDR4__DENALI_CTL_35__WRLAT_F1_MASK 0x00007F00U +#define LPDDR4__DENALI_CTL_35__WRLAT_F1_SHIFT 8U +#define LPDDR4__DENALI_CTL_35__WRLAT_F1_WIDTH 7U +#define LPDDR4__WRLAT_F1__REG DENALI_CTL_35 +#define LPDDR4__WRLAT_F1__FLD LPDDR4__DENALI_CTL_35__WRLAT_F1 + +#define LPDDR4__DENALI_CTL_35__CASLAT_LIN_F2_MASK 0x007F0000U +#define LPDDR4__DENALI_CTL_35__CASLAT_LIN_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_35__CASLAT_LIN_F2_WIDTH 7U +#define LPDDR4__CASLAT_LIN_F2__REG DENALI_CTL_35 +#define LPDDR4__CASLAT_LIN_F2__FLD LPDDR4__DENALI_CTL_35__CASLAT_LIN_F2 + +#define LPDDR4__DENALI_CTL_35__WRLAT_F2_MASK 0x7F000000U +#define LPDDR4__DENALI_CTL_35__WRLAT_F2_SHIFT 24U +#define LPDDR4__DENALI_CTL_35__WRLAT_F2_WIDTH 7U +#define LPDDR4__WRLAT_F2__REG DENALI_CTL_35 +#define LPDDR4__WRLAT_F2__FLD LPDDR4__DENALI_CTL_35__WRLAT_F2 + +#define LPDDR4__DENALI_CTL_36_READ_MASK 0x00FF1F07U +#define LPDDR4__DENALI_CTL_36_WRITE_MASK 0x00FF1F07U +#define LPDDR4__DENALI_CTL_36__TBST_INT_INTERVAL_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_36__TBST_INT_INTERVAL_SHIFT 0U +#define LPDDR4__DENALI_CTL_36__TBST_INT_INTERVAL_WIDTH 3U +#define LPDDR4__TBST_INT_INTERVAL__REG DENALI_CTL_36 +#define LPDDR4__TBST_INT_INTERVAL__FLD LPDDR4__DENALI_CTL_36__TBST_INT_INTERVAL + +#define LPDDR4__DENALI_CTL_36__TCCD_MASK 0x00001F00U +#define LPDDR4__DENALI_CTL_36__TCCD_SHIFT 8U +#define LPDDR4__DENALI_CTL_36__TCCD_WIDTH 5U +#define LPDDR4__TCCD__REG DENALI_CTL_36 +#define LPDDR4__TCCD__FLD LPDDR4__DENALI_CTL_36__TCCD + +#define LPDDR4__DENALI_CTL_36__TRRD_F0_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_36__TRRD_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_36__TRRD_F0_WIDTH 8U +#define LPDDR4__TRRD_F0__REG DENALI_CTL_36 +#define LPDDR4__TRRD_F0__FLD LPDDR4__DENALI_CTL_36__TRRD_F0 + +#define LPDDR4__DENALI_CTL_37_READ_MASK 0x3FFF01FFU +#define LPDDR4__DENALI_CTL_37_WRITE_MASK 0x3FFF01FFU +#define LPDDR4__DENALI_CTL_37__TRC_F0_MASK 0x000001FFU +#define LPDDR4__DENALI_CTL_37__TRC_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_37__TRC_F0_WIDTH 9U +#define LPDDR4__TRC_F0__REG DENALI_CTL_37 +#define LPDDR4__TRC_F0__FLD LPDDR4__DENALI_CTL_37__TRC_F0 + +#define LPDDR4__DENALI_CTL_37__TRAS_MIN_F0_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_37__TRAS_MIN_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_37__TRAS_MIN_F0_WIDTH 8U +#define LPDDR4__TRAS_MIN_F0__REG DENALI_CTL_37 +#define LPDDR4__TRAS_MIN_F0__FLD LPDDR4__DENALI_CTL_37__TRAS_MIN_F0 + +#define LPDDR4__DENALI_CTL_37__TWTR_F0_MASK 0x3F000000U +#define LPDDR4__DENALI_CTL_37__TWTR_F0_SHIFT 24U +#define LPDDR4__DENALI_CTL_37__TWTR_F0_WIDTH 6U +#define LPDDR4__TWTR_F0__REG DENALI_CTL_37 +#define LPDDR4__TWTR_F0__FLD LPDDR4__DENALI_CTL_37__TWTR_F0 + +#define LPDDR4__DENALI_CTL_38_READ_MASK 0xFF01FFFFU +#define LPDDR4__DENALI_CTL_38_WRITE_MASK 0xFF01FFFFU +#define LPDDR4__DENALI_CTL_38__TRP_F0_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_38__TRP_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_38__TRP_F0_WIDTH 8U +#define LPDDR4__TRP_F0__REG DENALI_CTL_38 +#define LPDDR4__TRP_F0__FLD LPDDR4__DENALI_CTL_38__TRP_F0 + +#define LPDDR4__DENALI_CTL_38__TFAW_F0_MASK 0x0001FF00U +#define LPDDR4__DENALI_CTL_38__TFAW_F0_SHIFT 8U +#define LPDDR4__DENALI_CTL_38__TFAW_F0_WIDTH 9U +#define LPDDR4__TFAW_F0__REG DENALI_CTL_38 +#define LPDDR4__TFAW_F0__FLD LPDDR4__DENALI_CTL_38__TFAW_F0 + +#define LPDDR4__DENALI_CTL_38__TRRD_F1_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_38__TRRD_F1_SHIFT 24U +#define LPDDR4__DENALI_CTL_38__TRRD_F1_WIDTH 8U +#define LPDDR4__TRRD_F1__REG DENALI_CTL_38 +#define LPDDR4__TRRD_F1__FLD LPDDR4__DENALI_CTL_38__TRRD_F1 + +#define LPDDR4__DENALI_CTL_39_READ_MASK 0x3FFF01FFU +#define LPDDR4__DENALI_CTL_39_WRITE_MASK 0x3FFF01FFU +#define LPDDR4__DENALI_CTL_39__TRC_F1_MASK 0x000001FFU +#define LPDDR4__DENALI_CTL_39__TRC_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_39__TRC_F1_WIDTH 9U +#define LPDDR4__TRC_F1__REG DENALI_CTL_39 +#define LPDDR4__TRC_F1__FLD LPDDR4__DENALI_CTL_39__TRC_F1 + +#define LPDDR4__DENALI_CTL_39__TRAS_MIN_F1_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_39__TRAS_MIN_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_39__TRAS_MIN_F1_WIDTH 8U +#define LPDDR4__TRAS_MIN_F1__REG DENALI_CTL_39 +#define LPDDR4__TRAS_MIN_F1__FLD LPDDR4__DENALI_CTL_39__TRAS_MIN_F1 + +#define LPDDR4__DENALI_CTL_39__TWTR_F1_MASK 0x3F000000U +#define LPDDR4__DENALI_CTL_39__TWTR_F1_SHIFT 24U +#define LPDDR4__DENALI_CTL_39__TWTR_F1_WIDTH 6U +#define LPDDR4__TWTR_F1__REG DENALI_CTL_39 +#define LPDDR4__TWTR_F1__FLD LPDDR4__DENALI_CTL_39__TWTR_F1 + +#define LPDDR4__DENALI_CTL_40_READ_MASK 0xFF01FFFFU +#define LPDDR4__DENALI_CTL_40_WRITE_MASK 0xFF01FFFFU +#define LPDDR4__DENALI_CTL_40__TRP_F1_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_40__TRP_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_40__TRP_F1_WIDTH 8U +#define LPDDR4__TRP_F1__REG DENALI_CTL_40 +#define LPDDR4__TRP_F1__FLD LPDDR4__DENALI_CTL_40__TRP_F1 + +#define LPDDR4__DENALI_CTL_40__TFAW_F1_MASK 0x0001FF00U +#define LPDDR4__DENALI_CTL_40__TFAW_F1_SHIFT 8U +#define LPDDR4__DENALI_CTL_40__TFAW_F1_WIDTH 9U +#define LPDDR4__TFAW_F1__REG DENALI_CTL_40 +#define LPDDR4__TFAW_F1__FLD LPDDR4__DENALI_CTL_40__TFAW_F1 + +#define LPDDR4__DENALI_CTL_40__TRRD_F2_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_40__TRRD_F2_SHIFT 24U +#define LPDDR4__DENALI_CTL_40__TRRD_F2_WIDTH 8U +#define LPDDR4__TRRD_F2__REG DENALI_CTL_40 +#define LPDDR4__TRRD_F2__FLD LPDDR4__DENALI_CTL_40__TRRD_F2 + +#define LPDDR4__DENALI_CTL_41_READ_MASK 0x3FFF01FFU +#define LPDDR4__DENALI_CTL_41_WRITE_MASK 0x3FFF01FFU +#define LPDDR4__DENALI_CTL_41__TRC_F2_MASK 0x000001FFU +#define LPDDR4__DENALI_CTL_41__TRC_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_41__TRC_F2_WIDTH 9U +#define LPDDR4__TRC_F2__REG DENALI_CTL_41 +#define LPDDR4__TRC_F2__FLD LPDDR4__DENALI_CTL_41__TRC_F2 + +#define LPDDR4__DENALI_CTL_41__TRAS_MIN_F2_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_41__TRAS_MIN_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_41__TRAS_MIN_F2_WIDTH 8U +#define LPDDR4__TRAS_MIN_F2__REG DENALI_CTL_41 +#define LPDDR4__TRAS_MIN_F2__FLD LPDDR4__DENALI_CTL_41__TRAS_MIN_F2 + +#define LPDDR4__DENALI_CTL_41__TWTR_F2_MASK 0x3F000000U +#define LPDDR4__DENALI_CTL_41__TWTR_F2_SHIFT 24U +#define LPDDR4__DENALI_CTL_41__TWTR_F2_WIDTH 6U +#define LPDDR4__TWTR_F2__REG DENALI_CTL_41 +#define LPDDR4__TWTR_F2__FLD LPDDR4__DENALI_CTL_41__TWTR_F2 + +#define LPDDR4__DENALI_CTL_42_READ_MASK 0x3F01FFFFU +#define LPDDR4__DENALI_CTL_42_WRITE_MASK 0x3F01FFFFU +#define LPDDR4__DENALI_CTL_42__TRP_F2_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_42__TRP_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_42__TRP_F2_WIDTH 8U +#define LPDDR4__TRP_F2__REG DENALI_CTL_42 +#define LPDDR4__TRP_F2__FLD LPDDR4__DENALI_CTL_42__TRP_F2 + +#define LPDDR4__DENALI_CTL_42__TFAW_F2_MASK 0x0001FF00U +#define LPDDR4__DENALI_CTL_42__TFAW_F2_SHIFT 8U +#define LPDDR4__DENALI_CTL_42__TFAW_F2_WIDTH 9U +#define LPDDR4__TFAW_F2__REG DENALI_CTL_42 +#define LPDDR4__TFAW_F2__FLD LPDDR4__DENALI_CTL_42__TFAW_F2 + +#define LPDDR4__DENALI_CTL_42__TCCDMW_MASK 0x3F000000U +#define LPDDR4__DENALI_CTL_42__TCCDMW_SHIFT 24U +#define LPDDR4__DENALI_CTL_42__TCCDMW_WIDTH 6U +#define LPDDR4__TCCDMW__REG DENALI_CTL_42 +#define LPDDR4__TCCDMW__FLD LPDDR4__DENALI_CTL_42__TCCDMW + +#define LPDDR4__DENALI_CTL_43_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_43_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_43__TRTP_F0_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_43__TRTP_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_43__TRTP_F0_WIDTH 8U +#define LPDDR4__TRTP_F0__REG DENALI_CTL_43 +#define LPDDR4__TRTP_F0__FLD LPDDR4__DENALI_CTL_43__TRTP_F0 + +#define LPDDR4__DENALI_CTL_43__TMRD_F0_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_43__TMRD_F0_SHIFT 8U +#define LPDDR4__DENALI_CTL_43__TMRD_F0_WIDTH 8U +#define LPDDR4__TMRD_F0__REG DENALI_CTL_43 +#define LPDDR4__TMRD_F0__FLD LPDDR4__DENALI_CTL_43__TMRD_F0 + +#define LPDDR4__DENALI_CTL_43__TMOD_F0_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_43__TMOD_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_43__TMOD_F0_WIDTH 8U +#define LPDDR4__TMOD_F0__REG DENALI_CTL_43 +#define LPDDR4__TMOD_F0__FLD LPDDR4__DENALI_CTL_43__TMOD_F0 + +#define LPDDR4__DENALI_CTL_44_READ_MASK 0x1F01FFFFU +#define LPDDR4__DENALI_CTL_44_WRITE_MASK 0x1F01FFFFU +#define LPDDR4__DENALI_CTL_44__TRAS_MAX_F0_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_44__TRAS_MAX_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_44__TRAS_MAX_F0_WIDTH 17U +#define LPDDR4__TRAS_MAX_F0__REG DENALI_CTL_44 +#define LPDDR4__TRAS_MAX_F0__FLD LPDDR4__DENALI_CTL_44__TRAS_MAX_F0 + +#define LPDDR4__DENALI_CTL_44__TCKE_F0_MASK 0x1F000000U +#define LPDDR4__DENALI_CTL_44__TCKE_F0_SHIFT 24U +#define LPDDR4__DENALI_CTL_44__TCKE_F0_WIDTH 5U +#define LPDDR4__TCKE_F0__REG DENALI_CTL_44 +#define LPDDR4__TCKE_F0__FLD LPDDR4__DENALI_CTL_44__TCKE_F0 + +#define LPDDR4__DENALI_CTL_45_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_45_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_45__TCKESR_F0_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_45__TCKESR_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_45__TCKESR_F0_WIDTH 8U +#define LPDDR4__TCKESR_F0__REG DENALI_CTL_45 +#define LPDDR4__TCKESR_F0__FLD LPDDR4__DENALI_CTL_45__TCKESR_F0 + +#define LPDDR4__DENALI_CTL_45__TRTP_F1_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_45__TRTP_F1_SHIFT 8U +#define LPDDR4__DENALI_CTL_45__TRTP_F1_WIDTH 8U +#define LPDDR4__TRTP_F1__REG DENALI_CTL_45 +#define LPDDR4__TRTP_F1__FLD LPDDR4__DENALI_CTL_45__TRTP_F1 + +#define LPDDR4__DENALI_CTL_45__TMRD_F1_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_45__TMRD_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_45__TMRD_F1_WIDTH 8U +#define LPDDR4__TMRD_F1__REG DENALI_CTL_45 +#define LPDDR4__TMRD_F1__FLD LPDDR4__DENALI_CTL_45__TMRD_F1 + +#define LPDDR4__DENALI_CTL_45__TMOD_F1_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_45__TMOD_F1_SHIFT 24U +#define LPDDR4__DENALI_CTL_45__TMOD_F1_WIDTH 8U +#define LPDDR4__TMOD_F1__REG DENALI_CTL_45 +#define LPDDR4__TMOD_F1__FLD LPDDR4__DENALI_CTL_45__TMOD_F1 + +#define LPDDR4__DENALI_CTL_46_READ_MASK 0x1F01FFFFU +#define LPDDR4__DENALI_CTL_46_WRITE_MASK 0x1F01FFFFU +#define LPDDR4__DENALI_CTL_46__TRAS_MAX_F1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_46__TRAS_MAX_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_46__TRAS_MAX_F1_WIDTH 17U +#define LPDDR4__TRAS_MAX_F1__REG DENALI_CTL_46 +#define LPDDR4__TRAS_MAX_F1__FLD LPDDR4__DENALI_CTL_46__TRAS_MAX_F1 + +#define LPDDR4__DENALI_CTL_46__TCKE_F1_MASK 0x1F000000U +#define LPDDR4__DENALI_CTL_46__TCKE_F1_SHIFT 24U +#define LPDDR4__DENALI_CTL_46__TCKE_F1_WIDTH 5U +#define LPDDR4__TCKE_F1__REG DENALI_CTL_46 +#define LPDDR4__TCKE_F1__FLD LPDDR4__DENALI_CTL_46__TCKE_F1 + +#define LPDDR4__DENALI_CTL_47_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_47_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_47__TCKESR_F1_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_47__TCKESR_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_47__TCKESR_F1_WIDTH 8U +#define LPDDR4__TCKESR_F1__REG DENALI_CTL_47 +#define LPDDR4__TCKESR_F1__FLD LPDDR4__DENALI_CTL_47__TCKESR_F1 + +#define LPDDR4__DENALI_CTL_47__TRTP_F2_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_47__TRTP_F2_SHIFT 8U +#define LPDDR4__DENALI_CTL_47__TRTP_F2_WIDTH 8U +#define LPDDR4__TRTP_F2__REG DENALI_CTL_47 +#define LPDDR4__TRTP_F2__FLD LPDDR4__DENALI_CTL_47__TRTP_F2 + +#define LPDDR4__DENALI_CTL_47__TMRD_F2_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_47__TMRD_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_47__TMRD_F2_WIDTH 8U +#define LPDDR4__TMRD_F2__REG DENALI_CTL_47 +#define LPDDR4__TMRD_F2__FLD LPDDR4__DENALI_CTL_47__TMRD_F2 + +#define LPDDR4__DENALI_CTL_47__TMOD_F2_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_47__TMOD_F2_SHIFT 24U +#define LPDDR4__DENALI_CTL_47__TMOD_F2_WIDTH 8U +#define LPDDR4__TMOD_F2__REG DENALI_CTL_47 +#define LPDDR4__TMOD_F2__FLD LPDDR4__DENALI_CTL_47__TMOD_F2 + +#define LPDDR4__DENALI_CTL_48_READ_MASK 0x1F01FFFFU +#define LPDDR4__DENALI_CTL_48_WRITE_MASK 0x1F01FFFFU +#define LPDDR4__DENALI_CTL_48__TRAS_MAX_F2_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_48__TRAS_MAX_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_48__TRAS_MAX_F2_WIDTH 17U +#define LPDDR4__TRAS_MAX_F2__REG DENALI_CTL_48 +#define LPDDR4__TRAS_MAX_F2__FLD LPDDR4__DENALI_CTL_48__TRAS_MAX_F2 + +#define LPDDR4__DENALI_CTL_48__TCKE_F2_MASK 0x1F000000U +#define LPDDR4__DENALI_CTL_48__TCKE_F2_SHIFT 24U +#define LPDDR4__DENALI_CTL_48__TCKE_F2_WIDTH 5U +#define LPDDR4__TCKE_F2__REG DENALI_CTL_48 +#define LPDDR4__TCKE_F2__FLD LPDDR4__DENALI_CTL_48__TCKE_F2 + +#define LPDDR4__DENALI_CTL_49_READ_MASK 0x070707FFU +#define LPDDR4__DENALI_CTL_49_WRITE_MASK 0x070707FFU +#define LPDDR4__DENALI_CTL_49__TCKESR_F2_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_49__TCKESR_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_49__TCKESR_F2_WIDTH 8U +#define LPDDR4__TCKESR_F2__REG DENALI_CTL_49 +#define LPDDR4__TCKESR_F2__FLD LPDDR4__DENALI_CTL_49__TCKESR_F2 + +#define LPDDR4__DENALI_CTL_49__TPPD_MASK 0x00000700U +#define LPDDR4__DENALI_CTL_49__TPPD_SHIFT 8U +#define LPDDR4__DENALI_CTL_49__TPPD_WIDTH 3U +#define LPDDR4__TPPD__REG DENALI_CTL_49 +#define LPDDR4__TPPD__FLD LPDDR4__DENALI_CTL_49__TPPD + +#define LPDDR4__DENALI_CTL_49__MC_RESERVED4_MASK 0x00070000U +#define LPDDR4__DENALI_CTL_49__MC_RESERVED4_SHIFT 16U +#define LPDDR4__DENALI_CTL_49__MC_RESERVED4_WIDTH 3U +#define LPDDR4__MC_RESERVED4__REG DENALI_CTL_49 +#define LPDDR4__MC_RESERVED4__FLD LPDDR4__DENALI_CTL_49__MC_RESERVED4 + +#define LPDDR4__DENALI_CTL_49__MC_RESERVED5_MASK 0x07000000U +#define LPDDR4__DENALI_CTL_49__MC_RESERVED5_SHIFT 24U +#define LPDDR4__DENALI_CTL_49__MC_RESERVED5_WIDTH 3U +#define LPDDR4__MC_RESERVED5__REG DENALI_CTL_49 +#define LPDDR4__MC_RESERVED5__FLD LPDDR4__DENALI_CTL_49__MC_RESERVED5 + +#define LPDDR4__DENALI_CTL_50_READ_MASK 0xFFFFFF01U +#define LPDDR4__DENALI_CTL_50_WRITE_MASK 0xFFFFFF01U +#define LPDDR4__DENALI_CTL_50__WRITEINTERP_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_50__WRITEINTERP_SHIFT 0U +#define LPDDR4__DENALI_CTL_50__WRITEINTERP_WIDTH 1U +#define LPDDR4__DENALI_CTL_50__WRITEINTERP_WOCLR 0U +#define LPDDR4__DENALI_CTL_50__WRITEINTERP_WOSET 0U +#define LPDDR4__WRITEINTERP__REG DENALI_CTL_50 +#define LPDDR4__WRITEINTERP__FLD LPDDR4__DENALI_CTL_50__WRITEINTERP + +#define LPDDR4__DENALI_CTL_50__TRCD_F0_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_50__TRCD_F0_SHIFT 8U +#define LPDDR4__DENALI_CTL_50__TRCD_F0_WIDTH 8U +#define LPDDR4__TRCD_F0__REG DENALI_CTL_50 +#define LPDDR4__TRCD_F0__FLD LPDDR4__DENALI_CTL_50__TRCD_F0 + +#define LPDDR4__DENALI_CTL_50__TWR_F0_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_50__TWR_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_50__TWR_F0_WIDTH 8U +#define LPDDR4__TWR_F0__REG DENALI_CTL_50 +#define LPDDR4__TWR_F0__FLD LPDDR4__DENALI_CTL_50__TWR_F0 + +#define LPDDR4__DENALI_CTL_50__TRCD_F1_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_50__TRCD_F1_SHIFT 24U +#define LPDDR4__DENALI_CTL_50__TRCD_F1_WIDTH 8U +#define LPDDR4__TRCD_F1__REG DENALI_CTL_50 +#define LPDDR4__TRCD_F1__FLD LPDDR4__DENALI_CTL_50__TRCD_F1 + +#define LPDDR4__DENALI_CTL_51_READ_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_CTL_51_WRITE_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_CTL_51__TWR_F1_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_51__TWR_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_51__TWR_F1_WIDTH 8U +#define LPDDR4__TWR_F1__REG DENALI_CTL_51 +#define LPDDR4__TWR_F1__FLD LPDDR4__DENALI_CTL_51__TWR_F1 + +#define LPDDR4__DENALI_CTL_51__TRCD_F2_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_51__TRCD_F2_SHIFT 8U +#define LPDDR4__DENALI_CTL_51__TRCD_F2_WIDTH 8U +#define LPDDR4__TRCD_F2__REG DENALI_CTL_51 +#define LPDDR4__TRCD_F2__FLD LPDDR4__DENALI_CTL_51__TRCD_F2 + +#define LPDDR4__DENALI_CTL_51__TWR_F2_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_51__TWR_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_51__TWR_F2_WIDTH 8U +#define LPDDR4__TWR_F2__REG DENALI_CTL_51 +#define LPDDR4__TWR_F2__FLD LPDDR4__DENALI_CTL_51__TWR_F2 + +#define LPDDR4__DENALI_CTL_51__TMRR_MASK 0x0F000000U +#define LPDDR4__DENALI_CTL_51__TMRR_SHIFT 24U +#define LPDDR4__DENALI_CTL_51__TMRR_WIDTH 4U +#define LPDDR4__TMRR__REG DENALI_CTL_51 +#define LPDDR4__TMRR__FLD LPDDR4__DENALI_CTL_51__TMRR + +#define LPDDR4__DENALI_CTL_52_READ_MASK 0x3F03FF1FU +#define LPDDR4__DENALI_CTL_52_WRITE_MASK 0x3F03FF1FU +#define LPDDR4__DENALI_CTL_52__TCACKEL_MASK 0x0000001FU +#define LPDDR4__DENALI_CTL_52__TCACKEL_SHIFT 0U +#define LPDDR4__DENALI_CTL_52__TCACKEL_WIDTH 5U +#define LPDDR4__TCACKEL__REG DENALI_CTL_52 +#define LPDDR4__TCACKEL__FLD LPDDR4__DENALI_CTL_52__TCACKEL + +#define LPDDR4__DENALI_CTL_52__TCAENT_MASK 0x0003FF00U +#define LPDDR4__DENALI_CTL_52__TCAENT_SHIFT 8U +#define LPDDR4__DENALI_CTL_52__TCAENT_WIDTH 10U +#define LPDDR4__TCAENT__REG DENALI_CTL_52 +#define LPDDR4__TCAENT__FLD LPDDR4__DENALI_CTL_52__TCAENT + +#define LPDDR4__DENALI_CTL_52__TCAMRD_MASK 0x3F000000U +#define LPDDR4__DENALI_CTL_52__TCAMRD_SHIFT 24U +#define LPDDR4__DENALI_CTL_52__TCAMRD_WIDTH 6U +#define LPDDR4__TCAMRD__REG DENALI_CTL_52 +#define LPDDR4__TCAMRD__FLD LPDDR4__DENALI_CTL_52__TCAMRD + +#define LPDDR4__DENALI_CTL_53_READ_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_CTL_53_WRITE_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_CTL_53__TCAEXT_MASK 0x0000001FU +#define LPDDR4__DENALI_CTL_53__TCAEXT_SHIFT 0U +#define LPDDR4__DENALI_CTL_53__TCAEXT_WIDTH 5U +#define LPDDR4__TCAEXT__REG DENALI_CTL_53 +#define LPDDR4__TCAEXT__FLD LPDDR4__DENALI_CTL_53__TCAEXT + +#define LPDDR4__DENALI_CTL_53__TCACKEH_MASK 0x00001F00U +#define LPDDR4__DENALI_CTL_53__TCACKEH_SHIFT 8U +#define LPDDR4__DENALI_CTL_53__TCACKEH_WIDTH 5U +#define LPDDR4__TCACKEH__REG DENALI_CTL_53 +#define LPDDR4__TCACKEH__FLD LPDDR4__DENALI_CTL_53__TCACKEH + +#define LPDDR4__DENALI_CTL_53__TMRZ_F0_MASK 0x001F0000U +#define LPDDR4__DENALI_CTL_53__TMRZ_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_53__TMRZ_F0_WIDTH 5U +#define LPDDR4__TMRZ_F0__REG DENALI_CTL_53 +#define LPDDR4__TMRZ_F0__FLD LPDDR4__DENALI_CTL_53__TMRZ_F0 + +#define LPDDR4__DENALI_CTL_53__TMRZ_F1_MASK 0x1F000000U +#define LPDDR4__DENALI_CTL_53__TMRZ_F1_SHIFT 24U +#define LPDDR4__DENALI_CTL_53__TMRZ_F1_WIDTH 5U +#define LPDDR4__TMRZ_F1__REG DENALI_CTL_53 +#define LPDDR4__TMRZ_F1__FLD LPDDR4__DENALI_CTL_53__TMRZ_F1 + +#define LPDDR4__DENALI_CTL_54_READ_MASK 0x0101011FU +#define LPDDR4__DENALI_CTL_54_WRITE_MASK 0x0101011FU +#define LPDDR4__DENALI_CTL_54__TMRZ_F2_MASK 0x0000001FU +#define LPDDR4__DENALI_CTL_54__TMRZ_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_54__TMRZ_F2_WIDTH 5U +#define LPDDR4__TMRZ_F2__REG DENALI_CTL_54 +#define LPDDR4__TMRZ_F2__FLD LPDDR4__DENALI_CTL_54__TMRZ_F2 + +#define LPDDR4__DENALI_CTL_54__AP_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_54__AP_SHIFT 8U +#define LPDDR4__DENALI_CTL_54__AP_WIDTH 1U +#define LPDDR4__DENALI_CTL_54__AP_WOCLR 0U +#define LPDDR4__DENALI_CTL_54__AP_WOSET 0U +#define LPDDR4__AP__REG DENALI_CTL_54 +#define LPDDR4__AP__FLD LPDDR4__DENALI_CTL_54__AP + +#define LPDDR4__DENALI_CTL_54__CONCURRENTAP_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_54__CONCURRENTAP_SHIFT 16U +#define LPDDR4__DENALI_CTL_54__CONCURRENTAP_WIDTH 1U +#define LPDDR4__DENALI_CTL_54__CONCURRENTAP_WOCLR 0U +#define LPDDR4__DENALI_CTL_54__CONCURRENTAP_WOSET 0U +#define LPDDR4__CONCURRENTAP__REG DENALI_CTL_54 +#define LPDDR4__CONCURRENTAP__FLD LPDDR4__DENALI_CTL_54__CONCURRENTAP + +#define LPDDR4__DENALI_CTL_54__TRAS_LOCKOUT_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_54__TRAS_LOCKOUT_SHIFT 24U +#define LPDDR4__DENALI_CTL_54__TRAS_LOCKOUT_WIDTH 1U +#define LPDDR4__DENALI_CTL_54__TRAS_LOCKOUT_WOCLR 0U +#define LPDDR4__DENALI_CTL_54__TRAS_LOCKOUT_WOSET 0U +#define LPDDR4__TRAS_LOCKOUT__REG DENALI_CTL_54 +#define LPDDR4__TRAS_LOCKOUT__FLD LPDDR4__DENALI_CTL_54__TRAS_LOCKOUT + +#define LPDDR4__DENALI_CTL_55_READ_MASK 0x1FFFFFFFU +#define LPDDR4__DENALI_CTL_55_WRITE_MASK 0x1FFFFFFFU +#define LPDDR4__DENALI_CTL_55__TDAL_F0_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_55__TDAL_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_55__TDAL_F0_WIDTH 8U +#define LPDDR4__TDAL_F0__REG DENALI_CTL_55 +#define LPDDR4__TDAL_F0__FLD LPDDR4__DENALI_CTL_55__TDAL_F0 + +#define LPDDR4__DENALI_CTL_55__TDAL_F1_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_55__TDAL_F1_SHIFT 8U +#define LPDDR4__DENALI_CTL_55__TDAL_F1_WIDTH 8U +#define LPDDR4__TDAL_F1__REG DENALI_CTL_55 +#define LPDDR4__TDAL_F1__FLD LPDDR4__DENALI_CTL_55__TDAL_F1 + +#define LPDDR4__DENALI_CTL_55__TDAL_F2_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_55__TDAL_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_55__TDAL_F2_WIDTH 8U +#define LPDDR4__TDAL_F2__REG DENALI_CTL_55 +#define LPDDR4__TDAL_F2__FLD LPDDR4__DENALI_CTL_55__TDAL_F2 + +#define LPDDR4__DENALI_CTL_55__BSTLEN_MASK 0x1F000000U +#define LPDDR4__DENALI_CTL_55__BSTLEN_SHIFT 24U +#define LPDDR4__DENALI_CTL_55__BSTLEN_WIDTH 5U +#define LPDDR4__BSTLEN__REG DENALI_CTL_55 +#define LPDDR4__BSTLEN__FLD LPDDR4__DENALI_CTL_55__BSTLEN + +#define LPDDR4__DENALI_CTL_56_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_56_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_56__TRP_AB_F0_0_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_56__TRP_AB_F0_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_56__TRP_AB_F0_0_WIDTH 8U +#define LPDDR4__TRP_AB_F0_0__REG DENALI_CTL_56 +#define LPDDR4__TRP_AB_F0_0__FLD LPDDR4__DENALI_CTL_56__TRP_AB_F0_0 + +#define LPDDR4__DENALI_CTL_56__TRP_AB_F1_0_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_56__TRP_AB_F1_0_SHIFT 8U +#define LPDDR4__DENALI_CTL_56__TRP_AB_F1_0_WIDTH 8U +#define LPDDR4__TRP_AB_F1_0__REG DENALI_CTL_56 +#define LPDDR4__TRP_AB_F1_0__FLD LPDDR4__DENALI_CTL_56__TRP_AB_F1_0 + +#define LPDDR4__DENALI_CTL_56__TRP_AB_F2_0_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_56__TRP_AB_F2_0_SHIFT 16U +#define LPDDR4__DENALI_CTL_56__TRP_AB_F2_0_WIDTH 8U +#define LPDDR4__TRP_AB_F2_0__REG DENALI_CTL_56 +#define LPDDR4__TRP_AB_F2_0__FLD LPDDR4__DENALI_CTL_56__TRP_AB_F2_0 + +#define LPDDR4__DENALI_CTL_56__TRP_AB_F0_1_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_56__TRP_AB_F0_1_SHIFT 24U +#define LPDDR4__DENALI_CTL_56__TRP_AB_F0_1_WIDTH 8U +#define LPDDR4__TRP_AB_F0_1__REG DENALI_CTL_56 +#define LPDDR4__TRP_AB_F0_1__FLD LPDDR4__DENALI_CTL_56__TRP_AB_F0_1 + +#define LPDDR4__DENALI_CTL_57_READ_MASK 0x0301FFFFU +#define LPDDR4__DENALI_CTL_57_WRITE_MASK 0x0301FFFFU +#define LPDDR4__DENALI_CTL_57__TRP_AB_F1_1_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_57__TRP_AB_F1_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_57__TRP_AB_F1_1_WIDTH 8U +#define LPDDR4__TRP_AB_F1_1__REG DENALI_CTL_57 +#define LPDDR4__TRP_AB_F1_1__FLD LPDDR4__DENALI_CTL_57__TRP_AB_F1_1 + +#define LPDDR4__DENALI_CTL_57__TRP_AB_F2_1_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_57__TRP_AB_F2_1_SHIFT 8U +#define LPDDR4__DENALI_CTL_57__TRP_AB_F2_1_WIDTH 8U +#define LPDDR4__TRP_AB_F2_1__REG DENALI_CTL_57 +#define LPDDR4__TRP_AB_F2_1__FLD LPDDR4__DENALI_CTL_57__TRP_AB_F2_1 + +#define LPDDR4__DENALI_CTL_57__REG_DIMM_ENABLE_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_57__REG_DIMM_ENABLE_SHIFT 16U +#define LPDDR4__DENALI_CTL_57__REG_DIMM_ENABLE_WIDTH 1U +#define LPDDR4__DENALI_CTL_57__REG_DIMM_ENABLE_WOCLR 0U +#define LPDDR4__DENALI_CTL_57__REG_DIMM_ENABLE_WOSET 0U +#define LPDDR4__REG_DIMM_ENABLE__REG DENALI_CTL_57 +#define LPDDR4__REG_DIMM_ENABLE__FLD LPDDR4__DENALI_CTL_57__REG_DIMM_ENABLE + +#define LPDDR4__DENALI_CTL_57__MC_RESERVED6_MASK 0x03000000U +#define LPDDR4__DENALI_CTL_57__MC_RESERVED6_SHIFT 24U +#define LPDDR4__DENALI_CTL_57__MC_RESERVED6_WIDTH 2U +#define LPDDR4__MC_RESERVED6__REG DENALI_CTL_57 +#define LPDDR4__MC_RESERVED6__FLD LPDDR4__DENALI_CTL_57__MC_RESERVED6 + +#define LPDDR4__DENALI_CTL_58_READ_MASK 0x0101017FU +#define LPDDR4__DENALI_CTL_58_WRITE_MASK 0x0101017FU +#define LPDDR4__DENALI_CTL_58__MC_RESERVED7_MASK 0x0000007FU +#define LPDDR4__DENALI_CTL_58__MC_RESERVED7_SHIFT 0U +#define LPDDR4__DENALI_CTL_58__MC_RESERVED7_WIDTH 7U +#define LPDDR4__MC_RESERVED7__REG DENALI_CTL_58 +#define LPDDR4__MC_RESERVED7__FLD LPDDR4__DENALI_CTL_58__MC_RESERVED7 + +#define LPDDR4__DENALI_CTL_58__OPTIMAL_RMODW_EN_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_58__OPTIMAL_RMODW_EN_SHIFT 8U +#define LPDDR4__DENALI_CTL_58__OPTIMAL_RMODW_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_58__OPTIMAL_RMODW_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_58__OPTIMAL_RMODW_EN_WOSET 0U +#define LPDDR4__OPTIMAL_RMODW_EN__REG DENALI_CTL_58 +#define LPDDR4__OPTIMAL_RMODW_EN__FLD LPDDR4__DENALI_CTL_58__OPTIMAL_RMODW_EN + +#define LPDDR4__DENALI_CTL_58__MC_RESERVED8_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_58__MC_RESERVED8_SHIFT 16U +#define LPDDR4__DENALI_CTL_58__MC_RESERVED8_WIDTH 1U +#define LPDDR4__DENALI_CTL_58__MC_RESERVED8_WOCLR 0U +#define LPDDR4__DENALI_CTL_58__MC_RESERVED8_WOSET 0U +#define LPDDR4__MC_RESERVED8__REG DENALI_CTL_58 +#define LPDDR4__MC_RESERVED8__FLD LPDDR4__DENALI_CTL_58__MC_RESERVED8 + +#define LPDDR4__DENALI_CTL_58__NO_MEMORY_DM_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_58__NO_MEMORY_DM_SHIFT 24U +#define LPDDR4__DENALI_CTL_58__NO_MEMORY_DM_WIDTH 1U +#define LPDDR4__DENALI_CTL_58__NO_MEMORY_DM_WOCLR 0U +#define LPDDR4__DENALI_CTL_58__NO_MEMORY_DM_WOSET 0U +#define LPDDR4__NO_MEMORY_DM__REG DENALI_CTL_58 +#define LPDDR4__NO_MEMORY_DM__FLD LPDDR4__DENALI_CTL_58__NO_MEMORY_DM + +#define LPDDR4__DENALI_CTL_59_READ_MASK 0x07010100U +#define LPDDR4__DENALI_CTL_59_WRITE_MASK 0x07010100U +#define LPDDR4__DENALI_CTL_59__AREFRESH_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_59__AREFRESH_SHIFT 0U +#define LPDDR4__DENALI_CTL_59__AREFRESH_WIDTH 1U +#define LPDDR4__DENALI_CTL_59__AREFRESH_WOCLR 0U +#define LPDDR4__DENALI_CTL_59__AREFRESH_WOSET 0U +#define LPDDR4__AREFRESH__REG DENALI_CTL_59 +#define LPDDR4__AREFRESH__FLD LPDDR4__DENALI_CTL_59__AREFRESH + +#define LPDDR4__DENALI_CTL_59__AREF_STATUS_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_59__AREF_STATUS_SHIFT 8U +#define LPDDR4__DENALI_CTL_59__AREF_STATUS_WIDTH 1U +#define LPDDR4__DENALI_CTL_59__AREF_STATUS_WOCLR 0U +#define LPDDR4__DENALI_CTL_59__AREF_STATUS_WOSET 0U +#define LPDDR4__AREF_STATUS__REG DENALI_CTL_59 +#define LPDDR4__AREF_STATUS__FLD LPDDR4__DENALI_CTL_59__AREF_STATUS + +#define LPDDR4__DENALI_CTL_59__TREF_ENABLE_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_59__TREF_ENABLE_SHIFT 16U +#define LPDDR4__DENALI_CTL_59__TREF_ENABLE_WIDTH 1U +#define LPDDR4__DENALI_CTL_59__TREF_ENABLE_WOCLR 0U +#define LPDDR4__DENALI_CTL_59__TREF_ENABLE_WOSET 0U +#define LPDDR4__TREF_ENABLE__REG DENALI_CTL_59 +#define LPDDR4__TREF_ENABLE__FLD LPDDR4__DENALI_CTL_59__TREF_ENABLE + +#define LPDDR4__DENALI_CTL_59__MC_RESERVED9_MASK 0x07000000U +#define LPDDR4__DENALI_CTL_59__MC_RESERVED9_SHIFT 24U +#define LPDDR4__DENALI_CTL_59__MC_RESERVED9_WIDTH 3U +#define LPDDR4__MC_RESERVED9__REG DENALI_CTL_59 +#define LPDDR4__MC_RESERVED9__FLD LPDDR4__DENALI_CTL_59__MC_RESERVED9 + +#define LPDDR4__DENALI_CTL_60_READ_MASK 0x0003FF3FU +#define LPDDR4__DENALI_CTL_60_WRITE_MASK 0x0003FF3FU +#define LPDDR4__DENALI_CTL_60__CS_COMPARISON_FOR_REFRESH_DEPTH_MASK 0x0000003FU +#define LPDDR4__DENALI_CTL_60__CS_COMPARISON_FOR_REFRESH_DEPTH_SHIFT 0U +#define LPDDR4__DENALI_CTL_60__CS_COMPARISON_FOR_REFRESH_DEPTH_WIDTH 6U +#define LPDDR4__CS_COMPARISON_FOR_REFRESH_DEPTH__REG DENALI_CTL_60 +#define LPDDR4__CS_COMPARISON_FOR_REFRESH_DEPTH__FLD LPDDR4__DENALI_CTL_60__CS_COMPARISON_FOR_REFRESH_DEPTH + +#define LPDDR4__DENALI_CTL_60__TRFC_F0_MASK 0x0003FF00U +#define LPDDR4__DENALI_CTL_60__TRFC_F0_SHIFT 8U +#define LPDDR4__DENALI_CTL_60__TRFC_F0_WIDTH 10U +#define LPDDR4__TRFC_F0__REG DENALI_CTL_60 +#define LPDDR4__TRFC_F0__FLD LPDDR4__DENALI_CTL_60__TRFC_F0 + +#define LPDDR4__DENALI_CTL_61_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_61_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_61__TREF_F0_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_61__TREF_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_61__TREF_F0_WIDTH 20U +#define LPDDR4__TREF_F0__REG DENALI_CTL_61 +#define LPDDR4__TREF_F0__FLD LPDDR4__DENALI_CTL_61__TREF_F0 + +#define LPDDR4__DENALI_CTL_62_READ_MASK 0x000003FFU +#define LPDDR4__DENALI_CTL_62_WRITE_MASK 0x000003FFU +#define LPDDR4__DENALI_CTL_62__TRFC_F1_MASK 0x000003FFU +#define LPDDR4__DENALI_CTL_62__TRFC_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_62__TRFC_F1_WIDTH 10U +#define LPDDR4__TRFC_F1__REG DENALI_CTL_62 +#define LPDDR4__TRFC_F1__FLD LPDDR4__DENALI_CTL_62__TRFC_F1 + +#define LPDDR4__DENALI_CTL_63_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_63_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_63__TREF_F1_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_63__TREF_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_63__TREF_F1_WIDTH 20U +#define LPDDR4__TREF_F1__REG DENALI_CTL_63 +#define LPDDR4__TREF_F1__FLD LPDDR4__DENALI_CTL_63__TREF_F1 + +#define LPDDR4__DENALI_CTL_64_READ_MASK 0x000003FFU +#define LPDDR4__DENALI_CTL_64_WRITE_MASK 0x000003FFU +#define LPDDR4__DENALI_CTL_64__TRFC_F2_MASK 0x000003FFU +#define LPDDR4__DENALI_CTL_64__TRFC_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_64__TRFC_F2_WIDTH 10U +#define LPDDR4__TRFC_F2__REG DENALI_CTL_64 +#define LPDDR4__TRFC_F2__FLD LPDDR4__DENALI_CTL_64__TRFC_F2 + +#define LPDDR4__DENALI_CTL_65_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_65_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_65__TREF_F2_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_65__TREF_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_65__TREF_F2_WIDTH 20U +#define LPDDR4__TREF_F2__REG DENALI_CTL_65 +#define LPDDR4__TREF_F2__FLD LPDDR4__DENALI_CTL_65__TREF_F2 + +#define LPDDR4__DENALI_CTL_66_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_66_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_66__TREF_INTERVAL_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_66__TREF_INTERVAL_SHIFT 0U +#define LPDDR4__DENALI_CTL_66__TREF_INTERVAL_WIDTH 20U +#define LPDDR4__TREF_INTERVAL__REG DENALI_CTL_66 +#define LPDDR4__TREF_INTERVAL__FLD LPDDR4__DENALI_CTL_66__TREF_INTERVAL + +#define LPDDR4__DENALI_CTL_67_READ_MASK 0x03FF0101U +#define LPDDR4__DENALI_CTL_67_WRITE_MASK 0x03FF0101U +#define LPDDR4__DENALI_CTL_67__PBR_EN_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_67__PBR_EN_SHIFT 0U +#define LPDDR4__DENALI_CTL_67__PBR_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_67__PBR_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_67__PBR_EN_WOSET 0U +#define LPDDR4__PBR_EN__REG DENALI_CTL_67 +#define LPDDR4__PBR_EN__FLD LPDDR4__DENALI_CTL_67__PBR_EN + +#define LPDDR4__DENALI_CTL_67__PBR_NUMERIC_ORDER_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_67__PBR_NUMERIC_ORDER_SHIFT 8U +#define LPDDR4__DENALI_CTL_67__PBR_NUMERIC_ORDER_WIDTH 1U +#define LPDDR4__DENALI_CTL_67__PBR_NUMERIC_ORDER_WOCLR 0U +#define LPDDR4__DENALI_CTL_67__PBR_NUMERIC_ORDER_WOSET 0U +#define LPDDR4__PBR_NUMERIC_ORDER__REG DENALI_CTL_67 +#define LPDDR4__PBR_NUMERIC_ORDER__FLD LPDDR4__DENALI_CTL_67__PBR_NUMERIC_ORDER + +#define LPDDR4__DENALI_CTL_67__TRFC_PB_F0_MASK 0x03FF0000U +#define LPDDR4__DENALI_CTL_67__TRFC_PB_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_67__TRFC_PB_F0_WIDTH 10U +#define LPDDR4__TRFC_PB_F0__REG DENALI_CTL_67 +#define LPDDR4__TRFC_PB_F0__FLD LPDDR4__DENALI_CTL_67__TRFC_PB_F0 + +#define LPDDR4__DENALI_CTL_68_READ_MASK 0x03FFFFFFU +#define LPDDR4__DENALI_CTL_68_WRITE_MASK 0x03FFFFFFU +#define LPDDR4__DENALI_CTL_68__TREFI_PB_F0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_68__TREFI_PB_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_68__TREFI_PB_F0_WIDTH 16U +#define LPDDR4__TREFI_PB_F0__REG DENALI_CTL_68 +#define LPDDR4__TREFI_PB_F0__FLD LPDDR4__DENALI_CTL_68__TREFI_PB_F0 + +#define LPDDR4__DENALI_CTL_68__TRFC_PB_F1_MASK 0x03FF0000U +#define LPDDR4__DENALI_CTL_68__TRFC_PB_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_68__TRFC_PB_F1_WIDTH 10U +#define LPDDR4__TRFC_PB_F1__REG DENALI_CTL_68 +#define LPDDR4__TRFC_PB_F1__FLD LPDDR4__DENALI_CTL_68__TRFC_PB_F1 + +#define LPDDR4__DENALI_CTL_69_READ_MASK 0x03FFFFFFU +#define LPDDR4__DENALI_CTL_69_WRITE_MASK 0x03FFFFFFU +#define LPDDR4__DENALI_CTL_69__TREFI_PB_F1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_69__TREFI_PB_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_69__TREFI_PB_F1_WIDTH 16U +#define LPDDR4__TREFI_PB_F1__REG DENALI_CTL_69 +#define LPDDR4__TREFI_PB_F1__FLD LPDDR4__DENALI_CTL_69__TREFI_PB_F1 + +#define LPDDR4__DENALI_CTL_69__TRFC_PB_F2_MASK 0x03FF0000U +#define LPDDR4__DENALI_CTL_69__TRFC_PB_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_69__TRFC_PB_F2_WIDTH 10U +#define LPDDR4__TRFC_PB_F2__REG DENALI_CTL_69 +#define LPDDR4__TRFC_PB_F2__FLD LPDDR4__DENALI_CTL_69__TRFC_PB_F2 + +#define LPDDR4__DENALI_CTL_70_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_70_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_70__TREFI_PB_F2_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_70__TREFI_PB_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_70__TREFI_PB_F2_WIDTH 16U +#define LPDDR4__TREFI_PB_F2__REG DENALI_CTL_70 +#define LPDDR4__TREFI_PB_F2__FLD LPDDR4__DENALI_CTL_70__TREFI_PB_F2 + +#define LPDDR4__DENALI_CTL_70__PBR_MAX_BANK_WAIT_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_70__PBR_MAX_BANK_WAIT_SHIFT 16U +#define LPDDR4__DENALI_CTL_70__PBR_MAX_BANK_WAIT_WIDTH 16U +#define LPDDR4__PBR_MAX_BANK_WAIT__REG DENALI_CTL_70 +#define LPDDR4__PBR_MAX_BANK_WAIT__FLD LPDDR4__DENALI_CTL_70__PBR_MAX_BANK_WAIT + +#define LPDDR4__DENALI_CTL_71_READ_MASK 0x1F1F010FU +#define LPDDR4__DENALI_CTL_71_WRITE_MASK 0x1F1F010FU +#define LPDDR4__DENALI_CTL_71__PBR_BANK_SELECT_DELAY_MASK 0x0000000FU +#define LPDDR4__DENALI_CTL_71__PBR_BANK_SELECT_DELAY_SHIFT 0U +#define LPDDR4__DENALI_CTL_71__PBR_BANK_SELECT_DELAY_WIDTH 4U +#define LPDDR4__PBR_BANK_SELECT_DELAY__REG DENALI_CTL_71 +#define LPDDR4__PBR_BANK_SELECT_DELAY__FLD LPDDR4__DENALI_CTL_71__PBR_BANK_SELECT_DELAY + +#define LPDDR4__DENALI_CTL_71__PBR_CONT_REQ_EN_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_71__PBR_CONT_REQ_EN_SHIFT 8U +#define LPDDR4__DENALI_CTL_71__PBR_CONT_REQ_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_71__PBR_CONT_REQ_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_71__PBR_CONT_REQ_EN_WOSET 0U +#define LPDDR4__PBR_CONT_REQ_EN__REG DENALI_CTL_71 +#define LPDDR4__PBR_CONT_REQ_EN__FLD LPDDR4__DENALI_CTL_71__PBR_CONT_REQ_EN + +#define LPDDR4__DENALI_CTL_71__AREF_PBR_CONT_EN_THRESHOLD_MASK 0x001F0000U +#define LPDDR4__DENALI_CTL_71__AREF_PBR_CONT_EN_THRESHOLD_SHIFT 16U +#define LPDDR4__DENALI_CTL_71__AREF_PBR_CONT_EN_THRESHOLD_WIDTH 5U +#define LPDDR4__AREF_PBR_CONT_EN_THRESHOLD__REG DENALI_CTL_71 +#define LPDDR4__AREF_PBR_CONT_EN_THRESHOLD__FLD LPDDR4__DENALI_CTL_71__AREF_PBR_CONT_EN_THRESHOLD + +#define LPDDR4__DENALI_CTL_71__AREF_PBR_CONT_DIS_THRESHOLD_MASK 0x1F000000U +#define LPDDR4__DENALI_CTL_71__AREF_PBR_CONT_DIS_THRESHOLD_SHIFT 24U +#define LPDDR4__DENALI_CTL_71__AREF_PBR_CONT_DIS_THRESHOLD_WIDTH 5U +#define LPDDR4__AREF_PBR_CONT_DIS_THRESHOLD__REG DENALI_CTL_71 +#define LPDDR4__AREF_PBR_CONT_DIS_THRESHOLD__FLD LPDDR4__DENALI_CTL_71__AREF_PBR_CONT_DIS_THRESHOLD + +#define LPDDR4__DENALI_CTL_72_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_72_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_72__TPDEX_F0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_72__TPDEX_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_72__TPDEX_F0_WIDTH 16U +#define LPDDR4__TPDEX_F0__REG DENALI_CTL_72 +#define LPDDR4__TPDEX_F0__FLD LPDDR4__DENALI_CTL_72__TPDEX_F0 + +#define LPDDR4__DENALI_CTL_72__TPDEX_F1_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_72__TPDEX_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_72__TPDEX_F1_WIDTH 16U +#define LPDDR4__TPDEX_F1__REG DENALI_CTL_72 +#define LPDDR4__TPDEX_F1__FLD LPDDR4__DENALI_CTL_72__TPDEX_F1 + +#define LPDDR4__DENALI_CTL_73_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_73_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_73__TPDEX_F2_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_73__TPDEX_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_73__TPDEX_F2_WIDTH 16U +#define LPDDR4__TPDEX_F2__REG DENALI_CTL_73 +#define LPDDR4__TPDEX_F2__FLD LPDDR4__DENALI_CTL_73__TPDEX_F2 + +#define LPDDR4__DENALI_CTL_73__TMRRI_F0_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_73__TMRRI_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_73__TMRRI_F0_WIDTH 8U +#define LPDDR4__TMRRI_F0__REG DENALI_CTL_73 +#define LPDDR4__TMRRI_F0__FLD LPDDR4__DENALI_CTL_73__TMRRI_F0 + +#define LPDDR4__DENALI_CTL_73__TMRRI_F1_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_73__TMRRI_F1_SHIFT 24U +#define LPDDR4__DENALI_CTL_73__TMRRI_F1_WIDTH 8U +#define LPDDR4__TMRRI_F1__REG DENALI_CTL_73 +#define LPDDR4__TMRRI_F1__FLD LPDDR4__DENALI_CTL_73__TMRRI_F1 + +#define LPDDR4__DENALI_CTL_74_READ_MASK 0x1F1F1FFFU +#define LPDDR4__DENALI_CTL_74_WRITE_MASK 0x1F1F1FFFU +#define LPDDR4__DENALI_CTL_74__TMRRI_F2_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_74__TMRRI_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_74__TMRRI_F2_WIDTH 8U +#define LPDDR4__TMRRI_F2__REG DENALI_CTL_74 +#define LPDDR4__TMRRI_F2__FLD LPDDR4__DENALI_CTL_74__TMRRI_F2 + +#define LPDDR4__DENALI_CTL_74__TCSCKE_F0_MASK 0x00001F00U +#define LPDDR4__DENALI_CTL_74__TCSCKE_F0_SHIFT 8U +#define LPDDR4__DENALI_CTL_74__TCSCKE_F0_WIDTH 5U +#define LPDDR4__TCSCKE_F0__REG DENALI_CTL_74 +#define LPDDR4__TCSCKE_F0__FLD LPDDR4__DENALI_CTL_74__TCSCKE_F0 + +#define LPDDR4__DENALI_CTL_74__TCKELCS_F0_MASK 0x001F0000U +#define LPDDR4__DENALI_CTL_74__TCKELCS_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_74__TCKELCS_F0_WIDTH 5U +#define LPDDR4__TCKELCS_F0__REG DENALI_CTL_74 +#define LPDDR4__TCKELCS_F0__FLD LPDDR4__DENALI_CTL_74__TCKELCS_F0 + +#define LPDDR4__DENALI_CTL_74__TCKEHCS_F0_MASK 0x1F000000U +#define LPDDR4__DENALI_CTL_74__TCKEHCS_F0_SHIFT 24U +#define LPDDR4__DENALI_CTL_74__TCKEHCS_F0_WIDTH 5U +#define LPDDR4__TCKEHCS_F0__REG DENALI_CTL_74 +#define LPDDR4__TCKEHCS_F0__FLD LPDDR4__DENALI_CTL_74__TCKEHCS_F0 + +#define LPDDR4__DENALI_CTL_75_READ_MASK 0x1F010F1FU +#define LPDDR4__DENALI_CTL_75_WRITE_MASK 0x1F010F1FU +#define LPDDR4__DENALI_CTL_75__TMRWCKEL_F0_MASK 0x0000001FU +#define LPDDR4__DENALI_CTL_75__TMRWCKEL_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_75__TMRWCKEL_F0_WIDTH 5U +#define LPDDR4__TMRWCKEL_F0__REG DENALI_CTL_75 +#define LPDDR4__TMRWCKEL_F0__FLD LPDDR4__DENALI_CTL_75__TMRWCKEL_F0 + +#define LPDDR4__DENALI_CTL_75__TZQCKE_F0_MASK 0x00000F00U +#define LPDDR4__DENALI_CTL_75__TZQCKE_F0_SHIFT 8U +#define LPDDR4__DENALI_CTL_75__TZQCKE_F0_WIDTH 4U +#define LPDDR4__TZQCKE_F0__REG DENALI_CTL_75 +#define LPDDR4__TZQCKE_F0__FLD LPDDR4__DENALI_CTL_75__TZQCKE_F0 + +#define LPDDR4__DENALI_CTL_75__CA_DEFAULT_VAL_F0_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_75__CA_DEFAULT_VAL_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_75__CA_DEFAULT_VAL_F0_WIDTH 1U +#define LPDDR4__DENALI_CTL_75__CA_DEFAULT_VAL_F0_WOCLR 0U +#define LPDDR4__DENALI_CTL_75__CA_DEFAULT_VAL_F0_WOSET 0U +#define LPDDR4__CA_DEFAULT_VAL_F0__REG DENALI_CTL_75 +#define LPDDR4__CA_DEFAULT_VAL_F0__FLD LPDDR4__DENALI_CTL_75__CA_DEFAULT_VAL_F0 + +#define LPDDR4__DENALI_CTL_75__TCSCKE_F1_MASK 0x1F000000U +#define LPDDR4__DENALI_CTL_75__TCSCKE_F1_SHIFT 24U +#define LPDDR4__DENALI_CTL_75__TCSCKE_F1_WIDTH 5U +#define LPDDR4__TCSCKE_F1__REG DENALI_CTL_75 +#define LPDDR4__TCSCKE_F1__FLD LPDDR4__DENALI_CTL_75__TCSCKE_F1 + +#define LPDDR4__DENALI_CTL_76_READ_MASK 0x0F1F1F1FU +#define LPDDR4__DENALI_CTL_76_WRITE_MASK 0x0F1F1F1FU +#define LPDDR4__DENALI_CTL_76__TCKELCS_F1_MASK 0x0000001FU +#define LPDDR4__DENALI_CTL_76__TCKELCS_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_76__TCKELCS_F1_WIDTH 5U +#define LPDDR4__TCKELCS_F1__REG DENALI_CTL_76 +#define LPDDR4__TCKELCS_F1__FLD LPDDR4__DENALI_CTL_76__TCKELCS_F1 + +#define LPDDR4__DENALI_CTL_76__TCKEHCS_F1_MASK 0x00001F00U +#define LPDDR4__DENALI_CTL_76__TCKEHCS_F1_SHIFT 8U +#define LPDDR4__DENALI_CTL_76__TCKEHCS_F1_WIDTH 5U +#define LPDDR4__TCKEHCS_F1__REG DENALI_CTL_76 +#define LPDDR4__TCKEHCS_F1__FLD LPDDR4__DENALI_CTL_76__TCKEHCS_F1 + +#define LPDDR4__DENALI_CTL_76__TMRWCKEL_F1_MASK 0x001F0000U +#define LPDDR4__DENALI_CTL_76__TMRWCKEL_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_76__TMRWCKEL_F1_WIDTH 5U +#define LPDDR4__TMRWCKEL_F1__REG DENALI_CTL_76 +#define LPDDR4__TMRWCKEL_F1__FLD LPDDR4__DENALI_CTL_76__TMRWCKEL_F1 + +#define LPDDR4__DENALI_CTL_76__TZQCKE_F1_MASK 0x0F000000U +#define LPDDR4__DENALI_CTL_76__TZQCKE_F1_SHIFT 24U +#define LPDDR4__DENALI_CTL_76__TZQCKE_F1_WIDTH 4U +#define LPDDR4__TZQCKE_F1__REG DENALI_CTL_76 +#define LPDDR4__TZQCKE_F1__FLD LPDDR4__DENALI_CTL_76__TZQCKE_F1 + +#define LPDDR4__DENALI_CTL_77_READ_MASK 0x1F1F1F01U +#define LPDDR4__DENALI_CTL_77_WRITE_MASK 0x1F1F1F01U +#define LPDDR4__DENALI_CTL_77__CA_DEFAULT_VAL_F1_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_77__CA_DEFAULT_VAL_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_77__CA_DEFAULT_VAL_F1_WIDTH 1U +#define LPDDR4__DENALI_CTL_77__CA_DEFAULT_VAL_F1_WOCLR 0U +#define LPDDR4__DENALI_CTL_77__CA_DEFAULT_VAL_F1_WOSET 0U +#define LPDDR4__CA_DEFAULT_VAL_F1__REG DENALI_CTL_77 +#define LPDDR4__CA_DEFAULT_VAL_F1__FLD LPDDR4__DENALI_CTL_77__CA_DEFAULT_VAL_F1 + +#define LPDDR4__DENALI_CTL_77__TCSCKE_F2_MASK 0x00001F00U +#define LPDDR4__DENALI_CTL_77__TCSCKE_F2_SHIFT 8U +#define LPDDR4__DENALI_CTL_77__TCSCKE_F2_WIDTH 5U +#define LPDDR4__TCSCKE_F2__REG DENALI_CTL_77 +#define LPDDR4__TCSCKE_F2__FLD LPDDR4__DENALI_CTL_77__TCSCKE_F2 + +#define LPDDR4__DENALI_CTL_77__TCKELCS_F2_MASK 0x001F0000U +#define LPDDR4__DENALI_CTL_77__TCKELCS_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_77__TCKELCS_F2_WIDTH 5U +#define LPDDR4__TCKELCS_F2__REG DENALI_CTL_77 +#define LPDDR4__TCKELCS_F2__FLD LPDDR4__DENALI_CTL_77__TCKELCS_F2 + +#define LPDDR4__DENALI_CTL_77__TCKEHCS_F2_MASK 0x1F000000U +#define LPDDR4__DENALI_CTL_77__TCKEHCS_F2_SHIFT 24U +#define LPDDR4__DENALI_CTL_77__TCKEHCS_F2_WIDTH 5U +#define LPDDR4__TCKEHCS_F2__REG DENALI_CTL_77 +#define LPDDR4__TCKEHCS_F2__FLD LPDDR4__DENALI_CTL_77__TCKEHCS_F2 + +#define LPDDR4__DENALI_CTL_78_READ_MASK 0x00010F1FU +#define LPDDR4__DENALI_CTL_78_WRITE_MASK 0x00010F1FU +#define LPDDR4__DENALI_CTL_78__TMRWCKEL_F2_MASK 0x0000001FU +#define LPDDR4__DENALI_CTL_78__TMRWCKEL_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_78__TMRWCKEL_F2_WIDTH 5U +#define LPDDR4__TMRWCKEL_F2__REG DENALI_CTL_78 +#define LPDDR4__TMRWCKEL_F2__FLD LPDDR4__DENALI_CTL_78__TMRWCKEL_F2 + +#define LPDDR4__DENALI_CTL_78__TZQCKE_F2_MASK 0x00000F00U +#define LPDDR4__DENALI_CTL_78__TZQCKE_F2_SHIFT 8U +#define LPDDR4__DENALI_CTL_78__TZQCKE_F2_WIDTH 4U +#define LPDDR4__TZQCKE_F2__REG DENALI_CTL_78 +#define LPDDR4__TZQCKE_F2__FLD LPDDR4__DENALI_CTL_78__TZQCKE_F2 + +#define LPDDR4__DENALI_CTL_78__CA_DEFAULT_VAL_F2_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_78__CA_DEFAULT_VAL_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_78__CA_DEFAULT_VAL_F2_WIDTH 1U +#define LPDDR4__DENALI_CTL_78__CA_DEFAULT_VAL_F2_WOCLR 0U +#define LPDDR4__DENALI_CTL_78__CA_DEFAULT_VAL_F2_WOSET 0U +#define LPDDR4__CA_DEFAULT_VAL_F2__REG DENALI_CTL_78 +#define LPDDR4__CA_DEFAULT_VAL_F2__FLD LPDDR4__DENALI_CTL_78__CA_DEFAULT_VAL_F2 + +#define LPDDR4__DENALI_CTL_79_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_79_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_79__TXSR_F0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_79__TXSR_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_79__TXSR_F0_WIDTH 16U +#define LPDDR4__TXSR_F0__REG DENALI_CTL_79 +#define LPDDR4__TXSR_F0__FLD LPDDR4__DENALI_CTL_79__TXSR_F0 + +#define LPDDR4__DENALI_CTL_79__TXSNR_F0_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_79__TXSNR_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_79__TXSNR_F0_WIDTH 16U +#define LPDDR4__TXSNR_F0__REG DENALI_CTL_79 +#define LPDDR4__TXSNR_F0__FLD LPDDR4__DENALI_CTL_79__TXSNR_F0 + +#define LPDDR4__DENALI_CTL_80_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_80_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_80__TXSR_F1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_80__TXSR_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_80__TXSR_F1_WIDTH 16U +#define LPDDR4__TXSR_F1__REG DENALI_CTL_80 +#define LPDDR4__TXSR_F1__FLD LPDDR4__DENALI_CTL_80__TXSR_F1 + +#define LPDDR4__DENALI_CTL_80__TXSNR_F1_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_80__TXSNR_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_80__TXSNR_F1_WIDTH 16U +#define LPDDR4__TXSNR_F1__REG DENALI_CTL_80 +#define LPDDR4__TXSNR_F1__FLD LPDDR4__DENALI_CTL_80__TXSNR_F1 + +#define LPDDR4__DENALI_CTL_81_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_81_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_81__TXSR_F2_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_81__TXSR_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_81__TXSR_F2_WIDTH 16U +#define LPDDR4__TXSR_F2__REG DENALI_CTL_81 +#define LPDDR4__TXSR_F2__FLD LPDDR4__DENALI_CTL_81__TXSR_F2 + +#define LPDDR4__DENALI_CTL_81__TXSNR_F2_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_81__TXSNR_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_81__TXSNR_F2_WIDTH 16U +#define LPDDR4__TXSNR_F2__REG DENALI_CTL_81 +#define LPDDR4__TXSNR_F2__FLD LPDDR4__DENALI_CTL_81__TXSNR_F2 + +#define LPDDR4__DENALI_CTL_82_READ_MASK 0xFF1F1F1FU +#define LPDDR4__DENALI_CTL_82_WRITE_MASK 0xFF1F1F1FU +#define LPDDR4__DENALI_CTL_82__TCKELCMD_F0_MASK 0x0000001FU +#define LPDDR4__DENALI_CTL_82__TCKELCMD_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_82__TCKELCMD_F0_WIDTH 5U +#define LPDDR4__TCKELCMD_F0__REG DENALI_CTL_82 +#define LPDDR4__TCKELCMD_F0__FLD LPDDR4__DENALI_CTL_82__TCKELCMD_F0 + +#define LPDDR4__DENALI_CTL_82__TCKEHCMD_F0_MASK 0x00001F00U +#define LPDDR4__DENALI_CTL_82__TCKEHCMD_F0_SHIFT 8U +#define LPDDR4__DENALI_CTL_82__TCKEHCMD_F0_WIDTH 5U +#define LPDDR4__TCKEHCMD_F0__REG DENALI_CTL_82 +#define LPDDR4__TCKEHCMD_F0__FLD LPDDR4__DENALI_CTL_82__TCKEHCMD_F0 + +#define LPDDR4__DENALI_CTL_82__TCKCKEL_F0_MASK 0x001F0000U +#define LPDDR4__DENALI_CTL_82__TCKCKEL_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_82__TCKCKEL_F0_WIDTH 5U +#define LPDDR4__TCKCKEL_F0__REG DENALI_CTL_82 +#define LPDDR4__TCKCKEL_F0__FLD LPDDR4__DENALI_CTL_82__TCKCKEL_F0 + +#define LPDDR4__DENALI_CTL_82__TSR_F0_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_82__TSR_F0_SHIFT 24U +#define LPDDR4__DENALI_CTL_82__TSR_F0_WIDTH 8U +#define LPDDR4__TSR_F0__REG DENALI_CTL_82 +#define LPDDR4__TSR_F0__FLD LPDDR4__DENALI_CTL_82__TSR_F0 + +#define LPDDR4__DENALI_CTL_83_READ_MASK 0x1F1F1F07U +#define LPDDR4__DENALI_CTL_83_WRITE_MASK 0x1F1F1F07U +#define LPDDR4__DENALI_CTL_83__TESCKE_F0_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_83__TESCKE_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_83__TESCKE_F0_WIDTH 3U +#define LPDDR4__TESCKE_F0__REG DENALI_CTL_83 +#define LPDDR4__TESCKE_F0__FLD LPDDR4__DENALI_CTL_83__TESCKE_F0 + +#define LPDDR4__DENALI_CTL_83__TCKELPD_F0_MASK 0x00001F00U +#define LPDDR4__DENALI_CTL_83__TCKELPD_F0_SHIFT 8U +#define LPDDR4__DENALI_CTL_83__TCKELPD_F0_WIDTH 5U +#define LPDDR4__TCKELPD_F0__REG DENALI_CTL_83 +#define LPDDR4__TCKELPD_F0__FLD LPDDR4__DENALI_CTL_83__TCKELPD_F0 + +#define LPDDR4__DENALI_CTL_83__TCSCKEH_F0_MASK 0x001F0000U +#define LPDDR4__DENALI_CTL_83__TCSCKEH_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_83__TCSCKEH_F0_WIDTH 5U +#define LPDDR4__TCSCKEH_F0__REG DENALI_CTL_83 +#define LPDDR4__TCSCKEH_F0__FLD LPDDR4__DENALI_CTL_83__TCSCKEH_F0 + +#define LPDDR4__DENALI_CTL_83__TCMDCKE_F0_MASK 0x1F000000U +#define LPDDR4__DENALI_CTL_83__TCMDCKE_F0_SHIFT 24U +#define LPDDR4__DENALI_CTL_83__TCMDCKE_F0_WIDTH 5U +#define LPDDR4__TCMDCKE_F0__REG DENALI_CTL_83 +#define LPDDR4__TCMDCKE_F0__FLD LPDDR4__DENALI_CTL_83__TCMDCKE_F0 + +#define LPDDR4__DENALI_CTL_84_READ_MASK 0xFF1F1F1FU +#define LPDDR4__DENALI_CTL_84_WRITE_MASK 0xFF1F1F1FU +#define LPDDR4__DENALI_CTL_84__TCKELCMD_F1_MASK 0x0000001FU +#define LPDDR4__DENALI_CTL_84__TCKELCMD_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_84__TCKELCMD_F1_WIDTH 5U +#define LPDDR4__TCKELCMD_F1__REG DENALI_CTL_84 +#define LPDDR4__TCKELCMD_F1__FLD LPDDR4__DENALI_CTL_84__TCKELCMD_F1 + +#define LPDDR4__DENALI_CTL_84__TCKEHCMD_F1_MASK 0x00001F00U +#define LPDDR4__DENALI_CTL_84__TCKEHCMD_F1_SHIFT 8U +#define LPDDR4__DENALI_CTL_84__TCKEHCMD_F1_WIDTH 5U +#define LPDDR4__TCKEHCMD_F1__REG DENALI_CTL_84 +#define LPDDR4__TCKEHCMD_F1__FLD LPDDR4__DENALI_CTL_84__TCKEHCMD_F1 + +#define LPDDR4__DENALI_CTL_84__TCKCKEL_F1_MASK 0x001F0000U +#define LPDDR4__DENALI_CTL_84__TCKCKEL_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_84__TCKCKEL_F1_WIDTH 5U +#define LPDDR4__TCKCKEL_F1__REG DENALI_CTL_84 +#define LPDDR4__TCKCKEL_F1__FLD LPDDR4__DENALI_CTL_84__TCKCKEL_F1 + +#define LPDDR4__DENALI_CTL_84__TSR_F1_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_84__TSR_F1_SHIFT 24U +#define LPDDR4__DENALI_CTL_84__TSR_F1_WIDTH 8U +#define LPDDR4__TSR_F1__REG DENALI_CTL_84 +#define LPDDR4__TSR_F1__FLD LPDDR4__DENALI_CTL_84__TSR_F1 + +#define LPDDR4__DENALI_CTL_85_READ_MASK 0x1F1F1F07U +#define LPDDR4__DENALI_CTL_85_WRITE_MASK 0x1F1F1F07U +#define LPDDR4__DENALI_CTL_85__TESCKE_F1_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_85__TESCKE_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_85__TESCKE_F1_WIDTH 3U +#define LPDDR4__TESCKE_F1__REG DENALI_CTL_85 +#define LPDDR4__TESCKE_F1__FLD LPDDR4__DENALI_CTL_85__TESCKE_F1 + +#define LPDDR4__DENALI_CTL_85__TCKELPD_F1_MASK 0x00001F00U +#define LPDDR4__DENALI_CTL_85__TCKELPD_F1_SHIFT 8U +#define LPDDR4__DENALI_CTL_85__TCKELPD_F1_WIDTH 5U +#define LPDDR4__TCKELPD_F1__REG DENALI_CTL_85 +#define LPDDR4__TCKELPD_F1__FLD LPDDR4__DENALI_CTL_85__TCKELPD_F1 + +#define LPDDR4__DENALI_CTL_85__TCSCKEH_F1_MASK 0x001F0000U +#define LPDDR4__DENALI_CTL_85__TCSCKEH_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_85__TCSCKEH_F1_WIDTH 5U +#define LPDDR4__TCSCKEH_F1__REG DENALI_CTL_85 +#define LPDDR4__TCSCKEH_F1__FLD LPDDR4__DENALI_CTL_85__TCSCKEH_F1 + +#define LPDDR4__DENALI_CTL_85__TCMDCKE_F1_MASK 0x1F000000U +#define LPDDR4__DENALI_CTL_85__TCMDCKE_F1_SHIFT 24U +#define LPDDR4__DENALI_CTL_85__TCMDCKE_F1_WIDTH 5U +#define LPDDR4__TCMDCKE_F1__REG DENALI_CTL_85 +#define LPDDR4__TCMDCKE_F1__FLD LPDDR4__DENALI_CTL_85__TCMDCKE_F1 + +#define LPDDR4__DENALI_CTL_86_READ_MASK 0xFF1F1F1FU +#define LPDDR4__DENALI_CTL_86_WRITE_MASK 0xFF1F1F1FU +#define LPDDR4__DENALI_CTL_86__TCKELCMD_F2_MASK 0x0000001FU +#define LPDDR4__DENALI_CTL_86__TCKELCMD_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_86__TCKELCMD_F2_WIDTH 5U +#define LPDDR4__TCKELCMD_F2__REG DENALI_CTL_86 +#define LPDDR4__TCKELCMD_F2__FLD LPDDR4__DENALI_CTL_86__TCKELCMD_F2 + +#define LPDDR4__DENALI_CTL_86__TCKEHCMD_F2_MASK 0x00001F00U +#define LPDDR4__DENALI_CTL_86__TCKEHCMD_F2_SHIFT 8U +#define LPDDR4__DENALI_CTL_86__TCKEHCMD_F2_WIDTH 5U +#define LPDDR4__TCKEHCMD_F2__REG DENALI_CTL_86 +#define LPDDR4__TCKEHCMD_F2__FLD LPDDR4__DENALI_CTL_86__TCKEHCMD_F2 + +#define LPDDR4__DENALI_CTL_86__TCKCKEL_F2_MASK 0x001F0000U +#define LPDDR4__DENALI_CTL_86__TCKCKEL_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_86__TCKCKEL_F2_WIDTH 5U +#define LPDDR4__TCKCKEL_F2__REG DENALI_CTL_86 +#define LPDDR4__TCKCKEL_F2__FLD LPDDR4__DENALI_CTL_86__TCKCKEL_F2 + +#define LPDDR4__DENALI_CTL_86__TSR_F2_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_86__TSR_F2_SHIFT 24U +#define LPDDR4__DENALI_CTL_86__TSR_F2_WIDTH 8U +#define LPDDR4__TSR_F2__REG DENALI_CTL_86 +#define LPDDR4__TSR_F2__FLD LPDDR4__DENALI_CTL_86__TSR_F2 + +#define LPDDR4__DENALI_CTL_87_READ_MASK 0x1F1F1F07U +#define LPDDR4__DENALI_CTL_87_WRITE_MASK 0x1F1F1F07U +#define LPDDR4__DENALI_CTL_87__TESCKE_F2_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_87__TESCKE_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_87__TESCKE_F2_WIDTH 3U +#define LPDDR4__TESCKE_F2__REG DENALI_CTL_87 +#define LPDDR4__TESCKE_F2__FLD LPDDR4__DENALI_CTL_87__TESCKE_F2 + +#define LPDDR4__DENALI_CTL_87__TCKELPD_F2_MASK 0x00001F00U +#define LPDDR4__DENALI_CTL_87__TCKELPD_F2_SHIFT 8U +#define LPDDR4__DENALI_CTL_87__TCKELPD_F2_WIDTH 5U +#define LPDDR4__TCKELPD_F2__REG DENALI_CTL_87 +#define LPDDR4__TCKELPD_F2__FLD LPDDR4__DENALI_CTL_87__TCKELPD_F2 + +#define LPDDR4__DENALI_CTL_87__TCSCKEH_F2_MASK 0x001F0000U +#define LPDDR4__DENALI_CTL_87__TCSCKEH_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_87__TCSCKEH_F2_WIDTH 5U +#define LPDDR4__TCSCKEH_F2__REG DENALI_CTL_87 +#define LPDDR4__TCSCKEH_F2__FLD LPDDR4__DENALI_CTL_87__TCSCKEH_F2 + +#define LPDDR4__DENALI_CTL_87__TCMDCKE_F2_MASK 0x1F000000U +#define LPDDR4__DENALI_CTL_87__TCMDCKE_F2_SHIFT 24U +#define LPDDR4__DENALI_CTL_87__TCMDCKE_F2_WIDTH 5U +#define LPDDR4__TCMDCKE_F2__REG DENALI_CTL_87 +#define LPDDR4__TCMDCKE_F2__FLD LPDDR4__DENALI_CTL_87__TCMDCKE_F2 + +#define LPDDR4__DENALI_CTL_88_READ_MASK 0x07010101U +#define LPDDR4__DENALI_CTL_88_WRITE_MASK 0x07010101U +#define LPDDR4__DENALI_CTL_88__PWRUP_SREFRESH_EXIT_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_88__PWRUP_SREFRESH_EXIT_SHIFT 0U +#define LPDDR4__DENALI_CTL_88__PWRUP_SREFRESH_EXIT_WIDTH 1U +#define LPDDR4__DENALI_CTL_88__PWRUP_SREFRESH_EXIT_WOCLR 0U +#define LPDDR4__DENALI_CTL_88__PWRUP_SREFRESH_EXIT_WOSET 0U +#define LPDDR4__PWRUP_SREFRESH_EXIT__REG DENALI_CTL_88 +#define LPDDR4__PWRUP_SREFRESH_EXIT__FLD LPDDR4__DENALI_CTL_88__PWRUP_SREFRESH_EXIT + +#define LPDDR4__DENALI_CTL_88__MC_RESERVED10_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_88__MC_RESERVED10_SHIFT 8U +#define LPDDR4__DENALI_CTL_88__MC_RESERVED10_WIDTH 1U +#define LPDDR4__DENALI_CTL_88__MC_RESERVED10_WOCLR 0U +#define LPDDR4__DENALI_CTL_88__MC_RESERVED10_WOSET 0U +#define LPDDR4__MC_RESERVED10__REG DENALI_CTL_88 +#define LPDDR4__MC_RESERVED10__FLD LPDDR4__DENALI_CTL_88__MC_RESERVED10 + +#define LPDDR4__DENALI_CTL_88__ENABLE_QUICK_SREFRESH_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_88__ENABLE_QUICK_SREFRESH_SHIFT 16U +#define LPDDR4__DENALI_CTL_88__ENABLE_QUICK_SREFRESH_WIDTH 1U +#define LPDDR4__DENALI_CTL_88__ENABLE_QUICK_SREFRESH_WOCLR 0U +#define LPDDR4__DENALI_CTL_88__ENABLE_QUICK_SREFRESH_WOSET 0U +#define LPDDR4__ENABLE_QUICK_SREFRESH__REG DENALI_CTL_88 +#define LPDDR4__ENABLE_QUICK_SREFRESH__FLD LPDDR4__DENALI_CTL_88__ENABLE_QUICK_SREFRESH + +#define LPDDR4__DENALI_CTL_88__CKE_DELAY_MASK 0x07000000U +#define LPDDR4__DENALI_CTL_88__CKE_DELAY_SHIFT 24U +#define LPDDR4__DENALI_CTL_88__CKE_DELAY_WIDTH 3U +#define LPDDR4__CKE_DELAY__REG DENALI_CTL_88 +#define LPDDR4__CKE_DELAY__FLD LPDDR4__DENALI_CTL_88__CKE_DELAY + +#define LPDDR4__DENALI_CTL_89_READ_MASK 0x01010300U +#define LPDDR4__DENALI_CTL_89_WRITE_MASK 0x01010300U +#define LPDDR4__DENALI_CTL_89__MC_RESERVED11_MASK 0x0000001FU +#define LPDDR4__DENALI_CTL_89__MC_RESERVED11_SHIFT 0U +#define LPDDR4__DENALI_CTL_89__MC_RESERVED11_WIDTH 5U +#define LPDDR4__MC_RESERVED11__REG DENALI_CTL_89 +#define LPDDR4__MC_RESERVED11__FLD LPDDR4__DENALI_CTL_89__MC_RESERVED11 + +#define LPDDR4__DENALI_CTL_89__DFS_STATUS_MASK 0x00000300U +#define LPDDR4__DENALI_CTL_89__DFS_STATUS_SHIFT 8U +#define LPDDR4__DENALI_CTL_89__DFS_STATUS_WIDTH 2U +#define LPDDR4__DFS_STATUS__REG DENALI_CTL_89 +#define LPDDR4__DFS_STATUS__FLD LPDDR4__DENALI_CTL_89__DFS_STATUS + +#define LPDDR4__DENALI_CTL_89__DFS_ZQ_EN_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_89__DFS_ZQ_EN_SHIFT 16U +#define LPDDR4__DENALI_CTL_89__DFS_ZQ_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_89__DFS_ZQ_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_89__DFS_ZQ_EN_WOSET 0U +#define LPDDR4__DFS_ZQ_EN__REG DENALI_CTL_89 +#define LPDDR4__DFS_ZQ_EN__FLD LPDDR4__DENALI_CTL_89__DFS_ZQ_EN + +#define LPDDR4__DENALI_CTL_89__DFS_CALVL_EN_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_89__DFS_CALVL_EN_SHIFT 24U +#define LPDDR4__DENALI_CTL_89__DFS_CALVL_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_89__DFS_CALVL_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_89__DFS_CALVL_EN_WOSET 0U +#define LPDDR4__DFS_CALVL_EN__REG DENALI_CTL_89 +#define LPDDR4__DFS_CALVL_EN__FLD LPDDR4__DENALI_CTL_89__DFS_CALVL_EN + +#define LPDDR4__DENALI_CTL_90_READ_MASK 0x00010101U +#define LPDDR4__DENALI_CTL_90_WRITE_MASK 0x00010101U +#define LPDDR4__DENALI_CTL_90__DFS_WRLVL_EN_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_90__DFS_WRLVL_EN_SHIFT 0U +#define LPDDR4__DENALI_CTL_90__DFS_WRLVL_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_90__DFS_WRLVL_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_90__DFS_WRLVL_EN_WOSET 0U +#define LPDDR4__DFS_WRLVL_EN__REG DENALI_CTL_90 +#define LPDDR4__DFS_WRLVL_EN__FLD LPDDR4__DENALI_CTL_90__DFS_WRLVL_EN + +#define LPDDR4__DENALI_CTL_90__DFS_RDLVL_EN_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_90__DFS_RDLVL_EN_SHIFT 8U +#define LPDDR4__DENALI_CTL_90__DFS_RDLVL_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_90__DFS_RDLVL_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_90__DFS_RDLVL_EN_WOSET 0U +#define LPDDR4__DFS_RDLVL_EN__REG DENALI_CTL_90 +#define LPDDR4__DFS_RDLVL_EN__FLD LPDDR4__DENALI_CTL_90__DFS_RDLVL_EN + +#define LPDDR4__DENALI_CTL_90__DFS_RDLVL_GATE_EN_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_90__DFS_RDLVL_GATE_EN_SHIFT 16U +#define LPDDR4__DENALI_CTL_90__DFS_RDLVL_GATE_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_90__DFS_RDLVL_GATE_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_90__DFS_RDLVL_GATE_EN_WOSET 0U +#define LPDDR4__DFS_RDLVL_GATE_EN__REG DENALI_CTL_90 +#define LPDDR4__DFS_RDLVL_GATE_EN__FLD LPDDR4__DENALI_CTL_90__DFS_RDLVL_GATE_EN + +#define LPDDR4__DENALI_CTL_91_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_91_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_91__DFS_PROMOTE_THRESHOLD_F0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_91__DFS_PROMOTE_THRESHOLD_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_91__DFS_PROMOTE_THRESHOLD_F0_WIDTH 16U +#define LPDDR4__DFS_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_91 +#define LPDDR4__DFS_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_91__DFS_PROMOTE_THRESHOLD_F0 + +#define LPDDR4__DENALI_CTL_91__DFS_PROMOTE_THRESHOLD_F1_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_91__DFS_PROMOTE_THRESHOLD_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_91__DFS_PROMOTE_THRESHOLD_F1_WIDTH 16U +#define LPDDR4__DFS_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_91 +#define LPDDR4__DFS_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_91__DFS_PROMOTE_THRESHOLD_F1 + +#define LPDDR4__DENALI_CTL_92_READ_MASK 0x0707FFFFU +#define LPDDR4__DENALI_CTL_92_WRITE_MASK 0x0707FFFFU +#define LPDDR4__DENALI_CTL_92__DFS_PROMOTE_THRESHOLD_F2_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_92__DFS_PROMOTE_THRESHOLD_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_92__DFS_PROMOTE_THRESHOLD_F2_WIDTH 16U +#define LPDDR4__DFS_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_92 +#define LPDDR4__DFS_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_92__DFS_PROMOTE_THRESHOLD_F2 + +#define LPDDR4__DENALI_CTL_92__ZQ_STATUS_LOG_MASK 0x00070000U +#define LPDDR4__DENALI_CTL_92__ZQ_STATUS_LOG_SHIFT 16U +#define LPDDR4__DENALI_CTL_92__ZQ_STATUS_LOG_WIDTH 3U +#define LPDDR4__ZQ_STATUS_LOG__REG DENALI_CTL_92 +#define LPDDR4__ZQ_STATUS_LOG__FLD LPDDR4__DENALI_CTL_92__ZQ_STATUS_LOG + +#define LPDDR4__DENALI_CTL_92__MC_RESERVED12_MASK 0x07000000U +#define LPDDR4__DENALI_CTL_92__MC_RESERVED12_SHIFT 24U +#define LPDDR4__DENALI_CTL_92__MC_RESERVED12_WIDTH 3U +#define LPDDR4__MC_RESERVED12__REG DENALI_CTL_92 +#define LPDDR4__MC_RESERVED12__FLD LPDDR4__DENALI_CTL_92__MC_RESERVED12 + +#define LPDDR4__DENALI_CTL_93_READ_MASK 0xFFFFFF07U +#define LPDDR4__DENALI_CTL_93_WRITE_MASK 0xFFFFFF07U +#define LPDDR4__DENALI_CTL_93__MC_RESERVED13_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_93__MC_RESERVED13_SHIFT 0U +#define LPDDR4__DENALI_CTL_93__MC_RESERVED13_WIDTH 3U +#define LPDDR4__MC_RESERVED13__REG DENALI_CTL_93 +#define LPDDR4__MC_RESERVED13__FLD LPDDR4__DENALI_CTL_93__MC_RESERVED13 + +#define LPDDR4__DENALI_CTL_93__MC_RESERVED14_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_93__MC_RESERVED14_SHIFT 8U +#define LPDDR4__DENALI_CTL_93__MC_RESERVED14_WIDTH 8U +#define LPDDR4__MC_RESERVED14__REG DENALI_CTL_93 +#define LPDDR4__MC_RESERVED14__FLD LPDDR4__DENALI_CTL_93__MC_RESERVED14 + +#define LPDDR4__DENALI_CTL_93__MC_RESERVED15_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_93__MC_RESERVED15_SHIFT 16U +#define LPDDR4__DENALI_CTL_93__MC_RESERVED15_WIDTH 8U +#define LPDDR4__MC_RESERVED15__REG DENALI_CTL_93 +#define LPDDR4__MC_RESERVED15__FLD LPDDR4__DENALI_CTL_93__MC_RESERVED15 + +#define LPDDR4__DENALI_CTL_93__MC_RESERVED16_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_93__MC_RESERVED16_SHIFT 24U +#define LPDDR4__DENALI_CTL_93__MC_RESERVED16_WIDTH 8U +#define LPDDR4__MC_RESERVED16__REG DENALI_CTL_93 +#define LPDDR4__MC_RESERVED16__FLD LPDDR4__DENALI_CTL_93__MC_RESERVED16 + +#define LPDDR4__DENALI_CTL_94_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_94_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_94__UPD_CTRLUPD_NORM_THRESHOLD_F0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_94__UPD_CTRLUPD_NORM_THRESHOLD_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_94__UPD_CTRLUPD_NORM_THRESHOLD_F0_WIDTH 16U +#define LPDDR4__UPD_CTRLUPD_NORM_THRESHOLD_F0__REG DENALI_CTL_94 +#define LPDDR4__UPD_CTRLUPD_NORM_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_94__UPD_CTRLUPD_NORM_THRESHOLD_F0 + +#define LPDDR4__DENALI_CTL_94__UPD_CTRLUPD_HIGH_THRESHOLD_F0_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_94__UPD_CTRLUPD_HIGH_THRESHOLD_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_94__UPD_CTRLUPD_HIGH_THRESHOLD_F0_WIDTH 16U +#define LPDDR4__UPD_CTRLUPD_HIGH_THRESHOLD_F0__REG DENALI_CTL_94 +#define LPDDR4__UPD_CTRLUPD_HIGH_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_94__UPD_CTRLUPD_HIGH_THRESHOLD_F0 + +#define LPDDR4__DENALI_CTL_95_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_95_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_95__UPD_CTRLUPD_TIMEOUT_F0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_95__UPD_CTRLUPD_TIMEOUT_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_95__UPD_CTRLUPD_TIMEOUT_F0_WIDTH 16U +#define LPDDR4__UPD_CTRLUPD_TIMEOUT_F0__REG DENALI_CTL_95 +#define LPDDR4__UPD_CTRLUPD_TIMEOUT_F0__FLD LPDDR4__DENALI_CTL_95__UPD_CTRLUPD_TIMEOUT_F0 + +#define LPDDR4__DENALI_CTL_95__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F0_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_95__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_95__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F0_WIDTH 16U +#define LPDDR4__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_95 +#define LPDDR4__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_95__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F0 + +#define LPDDR4__DENALI_CTL_96_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_96_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_96__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_96__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_96__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F0_WIDTH 16U +#define LPDDR4__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_96 +#define LPDDR4__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_96__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F0 + +#define LPDDR4__DENALI_CTL_96__UPD_CTRLUPD_NORM_THRESHOLD_F1_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_96__UPD_CTRLUPD_NORM_THRESHOLD_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_96__UPD_CTRLUPD_NORM_THRESHOLD_F1_WIDTH 16U +#define LPDDR4__UPD_CTRLUPD_NORM_THRESHOLD_F1__REG DENALI_CTL_96 +#define LPDDR4__UPD_CTRLUPD_NORM_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_96__UPD_CTRLUPD_NORM_THRESHOLD_F1 + +#define LPDDR4__DENALI_CTL_97_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_97_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_97__UPD_CTRLUPD_HIGH_THRESHOLD_F1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_97__UPD_CTRLUPD_HIGH_THRESHOLD_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_97__UPD_CTRLUPD_HIGH_THRESHOLD_F1_WIDTH 16U +#define LPDDR4__UPD_CTRLUPD_HIGH_THRESHOLD_F1__REG DENALI_CTL_97 +#define LPDDR4__UPD_CTRLUPD_HIGH_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_97__UPD_CTRLUPD_HIGH_THRESHOLD_F1 + +#define LPDDR4__DENALI_CTL_97__UPD_CTRLUPD_TIMEOUT_F1_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_97__UPD_CTRLUPD_TIMEOUT_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_97__UPD_CTRLUPD_TIMEOUT_F1_WIDTH 16U +#define LPDDR4__UPD_CTRLUPD_TIMEOUT_F1__REG DENALI_CTL_97 +#define LPDDR4__UPD_CTRLUPD_TIMEOUT_F1__FLD LPDDR4__DENALI_CTL_97__UPD_CTRLUPD_TIMEOUT_F1 + +#define LPDDR4__DENALI_CTL_98_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_98_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_98__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_98__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_98__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F1_WIDTH 16U +#define LPDDR4__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_98 +#define LPDDR4__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_98__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F1 + +#define LPDDR4__DENALI_CTL_98__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F1_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_98__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_98__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F1_WIDTH 16U +#define LPDDR4__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_98 +#define LPDDR4__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_98__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F1 + +#define LPDDR4__DENALI_CTL_99_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_99_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_99__UPD_CTRLUPD_NORM_THRESHOLD_F2_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_99__UPD_CTRLUPD_NORM_THRESHOLD_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_99__UPD_CTRLUPD_NORM_THRESHOLD_F2_WIDTH 16U +#define LPDDR4__UPD_CTRLUPD_NORM_THRESHOLD_F2__REG DENALI_CTL_99 +#define LPDDR4__UPD_CTRLUPD_NORM_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_99__UPD_CTRLUPD_NORM_THRESHOLD_F2 + +#define LPDDR4__DENALI_CTL_99__UPD_CTRLUPD_HIGH_THRESHOLD_F2_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_99__UPD_CTRLUPD_HIGH_THRESHOLD_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_99__UPD_CTRLUPD_HIGH_THRESHOLD_F2_WIDTH 16U +#define LPDDR4__UPD_CTRLUPD_HIGH_THRESHOLD_F2__REG DENALI_CTL_99 +#define LPDDR4__UPD_CTRLUPD_HIGH_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_99__UPD_CTRLUPD_HIGH_THRESHOLD_F2 + +#define LPDDR4__DENALI_CTL_100_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_100_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_100__UPD_CTRLUPD_TIMEOUT_F2_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_100__UPD_CTRLUPD_TIMEOUT_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_100__UPD_CTRLUPD_TIMEOUT_F2_WIDTH 16U +#define LPDDR4__UPD_CTRLUPD_TIMEOUT_F2__REG DENALI_CTL_100 +#define LPDDR4__UPD_CTRLUPD_TIMEOUT_F2__FLD LPDDR4__DENALI_CTL_100__UPD_CTRLUPD_TIMEOUT_F2 + +#define LPDDR4__DENALI_CTL_100__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F2_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_100__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_100__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F2_WIDTH 16U +#define LPDDR4__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_100 +#define LPDDR4__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_100__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F2 + +#define LPDDR4__DENALI_CTL_101_READ_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_101_WRITE_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_101__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_101__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_101__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2_WIDTH 16U +#define LPDDR4__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_101 +#define LPDDR4__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_101__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2 + +#define LPDDR4__DENALI_CTL_102_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_102_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_102__TDFI_PHYMSTR_MAX_F0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_102__TDFI_PHYMSTR_MAX_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_102__TDFI_PHYMSTR_MAX_F0_WIDTH 32U +#define LPDDR4__TDFI_PHYMSTR_MAX_F0__REG DENALI_CTL_102 +#define LPDDR4__TDFI_PHYMSTR_MAX_F0__FLD LPDDR4__DENALI_CTL_102__TDFI_PHYMSTR_MAX_F0 + +#define LPDDR4__DENALI_CTL_103_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_103_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_103__TDFI_PHYMSTR_MAX_TYPE0_F0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_103__TDFI_PHYMSTR_MAX_TYPE0_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_103__TDFI_PHYMSTR_MAX_TYPE0_F0_WIDTH 32U +#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE0_F0__REG DENALI_CTL_103 +#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE0_F0__FLD LPDDR4__DENALI_CTL_103__TDFI_PHYMSTR_MAX_TYPE0_F0 + +#define LPDDR4__DENALI_CTL_104_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_104_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_104__TDFI_PHYMSTR_MAX_TYPE1_F0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_104__TDFI_PHYMSTR_MAX_TYPE1_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_104__TDFI_PHYMSTR_MAX_TYPE1_F0_WIDTH 32U +#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE1_F0__REG DENALI_CTL_104 +#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE1_F0__FLD LPDDR4__DENALI_CTL_104__TDFI_PHYMSTR_MAX_TYPE1_F0 + +#define LPDDR4__DENALI_CTL_105_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_105_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_105__TDFI_PHYMSTR_MAX_TYPE2_F0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_105__TDFI_PHYMSTR_MAX_TYPE2_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_105__TDFI_PHYMSTR_MAX_TYPE2_F0_WIDTH 32U +#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE2_F0__REG DENALI_CTL_105 +#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE2_F0__FLD LPDDR4__DENALI_CTL_105__TDFI_PHYMSTR_MAX_TYPE2_F0 + +#define LPDDR4__DENALI_CTL_106_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_106_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_106__TDFI_PHYMSTR_MAX_TYPE3_F0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_106__TDFI_PHYMSTR_MAX_TYPE3_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_106__TDFI_PHYMSTR_MAX_TYPE3_F0_WIDTH 32U +#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE3_F0__REG DENALI_CTL_106 +#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE3_F0__FLD LPDDR4__DENALI_CTL_106__TDFI_PHYMSTR_MAX_TYPE3_F0 + +#define LPDDR4__DENALI_CTL_107_READ_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_107_WRITE_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_107__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_107__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_107__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F0_WIDTH 16U +#define LPDDR4__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_107 +#define LPDDR4__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_107__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F0 + +#define LPDDR4__DENALI_CTL_108_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_108_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_108__TDFI_PHYMSTR_RESP_F0_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_108__TDFI_PHYMSTR_RESP_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_108__TDFI_PHYMSTR_RESP_F0_WIDTH 20U +#define LPDDR4__TDFI_PHYMSTR_RESP_F0__REG DENALI_CTL_108 +#define LPDDR4__TDFI_PHYMSTR_RESP_F0__FLD LPDDR4__DENALI_CTL_108__TDFI_PHYMSTR_RESP_F0 + +#define LPDDR4__DENALI_CTL_109_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_109_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_109__TDFI_PHYMSTR_MAX_F1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_109__TDFI_PHYMSTR_MAX_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_109__TDFI_PHYMSTR_MAX_F1_WIDTH 32U +#define LPDDR4__TDFI_PHYMSTR_MAX_F1__REG DENALI_CTL_109 +#define LPDDR4__TDFI_PHYMSTR_MAX_F1__FLD LPDDR4__DENALI_CTL_109__TDFI_PHYMSTR_MAX_F1 + +#define LPDDR4__DENALI_CTL_110_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_110_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_110__TDFI_PHYMSTR_MAX_TYPE0_F1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_110__TDFI_PHYMSTR_MAX_TYPE0_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_110__TDFI_PHYMSTR_MAX_TYPE0_F1_WIDTH 32U +#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE0_F1__REG DENALI_CTL_110 +#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE0_F1__FLD LPDDR4__DENALI_CTL_110__TDFI_PHYMSTR_MAX_TYPE0_F1 + +#define LPDDR4__DENALI_CTL_111_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_111_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_111__TDFI_PHYMSTR_MAX_TYPE1_F1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_111__TDFI_PHYMSTR_MAX_TYPE1_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_111__TDFI_PHYMSTR_MAX_TYPE1_F1_WIDTH 32U +#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE1_F1__REG DENALI_CTL_111 +#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE1_F1__FLD LPDDR4__DENALI_CTL_111__TDFI_PHYMSTR_MAX_TYPE1_F1 + +#define LPDDR4__DENALI_CTL_112_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_112_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_112__TDFI_PHYMSTR_MAX_TYPE2_F1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_112__TDFI_PHYMSTR_MAX_TYPE2_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_112__TDFI_PHYMSTR_MAX_TYPE2_F1_WIDTH 32U +#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE2_F1__REG DENALI_CTL_112 +#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE2_F1__FLD LPDDR4__DENALI_CTL_112__TDFI_PHYMSTR_MAX_TYPE2_F1 + +#define LPDDR4__DENALI_CTL_113_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_113_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_113__TDFI_PHYMSTR_MAX_TYPE3_F1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_113__TDFI_PHYMSTR_MAX_TYPE3_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_113__TDFI_PHYMSTR_MAX_TYPE3_F1_WIDTH 32U +#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE3_F1__REG DENALI_CTL_113 +#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE3_F1__FLD LPDDR4__DENALI_CTL_113__TDFI_PHYMSTR_MAX_TYPE3_F1 + +#define LPDDR4__DENALI_CTL_114_READ_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_114_WRITE_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_114__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_114__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_114__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F1_WIDTH 16U +#define LPDDR4__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_114 +#define LPDDR4__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_114__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F1 + +#define LPDDR4__DENALI_CTL_115_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_115_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_115__TDFI_PHYMSTR_RESP_F1_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_115__TDFI_PHYMSTR_RESP_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_115__TDFI_PHYMSTR_RESP_F1_WIDTH 20U +#define LPDDR4__TDFI_PHYMSTR_RESP_F1__REG DENALI_CTL_115 +#define LPDDR4__TDFI_PHYMSTR_RESP_F1__FLD LPDDR4__DENALI_CTL_115__TDFI_PHYMSTR_RESP_F1 + +#define LPDDR4__DENALI_CTL_116_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_116_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_116__TDFI_PHYMSTR_MAX_F2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_116__TDFI_PHYMSTR_MAX_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_116__TDFI_PHYMSTR_MAX_F2_WIDTH 32U +#define LPDDR4__TDFI_PHYMSTR_MAX_F2__REG DENALI_CTL_116 +#define LPDDR4__TDFI_PHYMSTR_MAX_F2__FLD LPDDR4__DENALI_CTL_116__TDFI_PHYMSTR_MAX_F2 + +#define LPDDR4__DENALI_CTL_117_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_117_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_117__TDFI_PHYMSTR_MAX_TYPE0_F2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_117__TDFI_PHYMSTR_MAX_TYPE0_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_117__TDFI_PHYMSTR_MAX_TYPE0_F2_WIDTH 32U +#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE0_F2__REG DENALI_CTL_117 +#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE0_F2__FLD LPDDR4__DENALI_CTL_117__TDFI_PHYMSTR_MAX_TYPE0_F2 + +#define LPDDR4__DENALI_CTL_118_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_118_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_118__TDFI_PHYMSTR_MAX_TYPE1_F2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_118__TDFI_PHYMSTR_MAX_TYPE1_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_118__TDFI_PHYMSTR_MAX_TYPE1_F2_WIDTH 32U +#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE1_F2__REG DENALI_CTL_118 +#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE1_F2__FLD LPDDR4__DENALI_CTL_118__TDFI_PHYMSTR_MAX_TYPE1_F2 + +#define LPDDR4__DENALI_CTL_119_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_119_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_119__TDFI_PHYMSTR_MAX_TYPE2_F2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_119__TDFI_PHYMSTR_MAX_TYPE2_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_119__TDFI_PHYMSTR_MAX_TYPE2_F2_WIDTH 32U +#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE2_F2__REG DENALI_CTL_119 +#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE2_F2__FLD LPDDR4__DENALI_CTL_119__TDFI_PHYMSTR_MAX_TYPE2_F2 + +#define LPDDR4__DENALI_CTL_120_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_120_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_120__TDFI_PHYMSTR_MAX_TYPE3_F2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_120__TDFI_PHYMSTR_MAX_TYPE3_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_120__TDFI_PHYMSTR_MAX_TYPE3_F2_WIDTH 32U +#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE3_F2__REG DENALI_CTL_120 +#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE3_F2__FLD LPDDR4__DENALI_CTL_120__TDFI_PHYMSTR_MAX_TYPE3_F2 + +#define LPDDR4__DENALI_CTL_121_READ_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_121_WRITE_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_121__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F2_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_121__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_121__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F2_WIDTH 16U +#define LPDDR4__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_121 +#define LPDDR4__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_121__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F2 + +#define LPDDR4__DENALI_CTL_122_READ_MASK 0x010FFFFFU +#define LPDDR4__DENALI_CTL_122_WRITE_MASK 0x010FFFFFU +#define LPDDR4__DENALI_CTL_122__TDFI_PHYMSTR_RESP_F2_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_122__TDFI_PHYMSTR_RESP_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_122__TDFI_PHYMSTR_RESP_F2_WIDTH 20U +#define LPDDR4__TDFI_PHYMSTR_RESP_F2__REG DENALI_CTL_122 +#define LPDDR4__TDFI_PHYMSTR_RESP_F2__FLD LPDDR4__DENALI_CTL_122__TDFI_PHYMSTR_RESP_F2 + +#define LPDDR4__DENALI_CTL_122__PHYMSTR_NO_AREF_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_122__PHYMSTR_NO_AREF_SHIFT 24U +#define LPDDR4__DENALI_CTL_122__PHYMSTR_NO_AREF_WIDTH 1U +#define LPDDR4__DENALI_CTL_122__PHYMSTR_NO_AREF_WOCLR 0U +#define LPDDR4__DENALI_CTL_122__PHYMSTR_NO_AREF_WOSET 0U +#define LPDDR4__PHYMSTR_NO_AREF__REG DENALI_CTL_122 +#define LPDDR4__PHYMSTR_NO_AREF__FLD LPDDR4__DENALI_CTL_122__PHYMSTR_NO_AREF + +#define LPDDR4__DENALI_CTL_123_READ_MASK 0x00010103U +#define LPDDR4__DENALI_CTL_123_WRITE_MASK 0x00010103U +#define LPDDR4__DENALI_CTL_123__PHYMSTR_ERROR_STATUS_MASK 0x00000003U +#define LPDDR4__DENALI_CTL_123__PHYMSTR_ERROR_STATUS_SHIFT 0U +#define LPDDR4__DENALI_CTL_123__PHYMSTR_ERROR_STATUS_WIDTH 2U +#define LPDDR4__PHYMSTR_ERROR_STATUS__REG DENALI_CTL_123 +#define LPDDR4__PHYMSTR_ERROR_STATUS__FLD LPDDR4__DENALI_CTL_123__PHYMSTR_ERROR_STATUS + +#define LPDDR4__DENALI_CTL_123__PHYMSTR_DFI_VERSION_4P0V1_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_123__PHYMSTR_DFI_VERSION_4P0V1_SHIFT 8U +#define LPDDR4__DENALI_CTL_123__PHYMSTR_DFI_VERSION_4P0V1_WIDTH 1U +#define LPDDR4__DENALI_CTL_123__PHYMSTR_DFI_VERSION_4P0V1_WOCLR 0U +#define LPDDR4__DENALI_CTL_123__PHYMSTR_DFI_VERSION_4P0V1_WOSET 0U +#define LPDDR4__PHYMSTR_DFI_VERSION_4P0V1__REG DENALI_CTL_123 +#define LPDDR4__PHYMSTR_DFI_VERSION_4P0V1__FLD LPDDR4__DENALI_CTL_123__PHYMSTR_DFI_VERSION_4P0V1 + +#define LPDDR4__DENALI_CTL_123__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_123__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE_SHIFT 16U +#define LPDDR4__DENALI_CTL_123__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE_WIDTH 1U +#define LPDDR4__DENALI_CTL_123__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE_WOCLR 0U +#define LPDDR4__DENALI_CTL_123__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE_WOSET 0U +#define LPDDR4__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE__REG DENALI_CTL_123 +#define LPDDR4__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE__FLD LPDDR4__DENALI_CTL_123__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE + +#define LPDDR4__DENALI_CTL_124_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_124_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_124__MRR_TEMPCHK_NORM_THRESHOLD_F0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_124__MRR_TEMPCHK_NORM_THRESHOLD_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_124__MRR_TEMPCHK_NORM_THRESHOLD_F0_WIDTH 16U +#define LPDDR4__MRR_TEMPCHK_NORM_THRESHOLD_F0__REG DENALI_CTL_124 +#define LPDDR4__MRR_TEMPCHK_NORM_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_124__MRR_TEMPCHK_NORM_THRESHOLD_F0 + +#define LPDDR4__DENALI_CTL_124__MRR_TEMPCHK_HIGH_THRESHOLD_F0_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_124__MRR_TEMPCHK_HIGH_THRESHOLD_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_124__MRR_TEMPCHK_HIGH_THRESHOLD_F0_WIDTH 16U +#define LPDDR4__MRR_TEMPCHK_HIGH_THRESHOLD_F0__REG DENALI_CTL_124 +#define LPDDR4__MRR_TEMPCHK_HIGH_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_124__MRR_TEMPCHK_HIGH_THRESHOLD_F0 + +#define LPDDR4__DENALI_CTL_125_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_125_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_125__MRR_TEMPCHK_TIMEOUT_F0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_125__MRR_TEMPCHK_TIMEOUT_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_125__MRR_TEMPCHK_TIMEOUT_F0_WIDTH 16U +#define LPDDR4__MRR_TEMPCHK_TIMEOUT_F0__REG DENALI_CTL_125 +#define LPDDR4__MRR_TEMPCHK_TIMEOUT_F0__FLD LPDDR4__DENALI_CTL_125__MRR_TEMPCHK_TIMEOUT_F0 + +#define LPDDR4__DENALI_CTL_125__MRR_TEMPCHK_NORM_THRESHOLD_F1_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_125__MRR_TEMPCHK_NORM_THRESHOLD_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_125__MRR_TEMPCHK_NORM_THRESHOLD_F1_WIDTH 16U +#define LPDDR4__MRR_TEMPCHK_NORM_THRESHOLD_F1__REG DENALI_CTL_125 +#define LPDDR4__MRR_TEMPCHK_NORM_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_125__MRR_TEMPCHK_NORM_THRESHOLD_F1 + +#define LPDDR4__DENALI_CTL_126_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_126_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_126__MRR_TEMPCHK_HIGH_THRESHOLD_F1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_126__MRR_TEMPCHK_HIGH_THRESHOLD_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_126__MRR_TEMPCHK_HIGH_THRESHOLD_F1_WIDTH 16U +#define LPDDR4__MRR_TEMPCHK_HIGH_THRESHOLD_F1__REG DENALI_CTL_126 +#define LPDDR4__MRR_TEMPCHK_HIGH_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_126__MRR_TEMPCHK_HIGH_THRESHOLD_F1 + +#define LPDDR4__DENALI_CTL_126__MRR_TEMPCHK_TIMEOUT_F1_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_126__MRR_TEMPCHK_TIMEOUT_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_126__MRR_TEMPCHK_TIMEOUT_F1_WIDTH 16U +#define LPDDR4__MRR_TEMPCHK_TIMEOUT_F1__REG DENALI_CTL_126 +#define LPDDR4__MRR_TEMPCHK_TIMEOUT_F1__FLD LPDDR4__DENALI_CTL_126__MRR_TEMPCHK_TIMEOUT_F1 + +#define LPDDR4__DENALI_CTL_127_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_127_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_127__MRR_TEMPCHK_NORM_THRESHOLD_F2_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_127__MRR_TEMPCHK_NORM_THRESHOLD_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_127__MRR_TEMPCHK_NORM_THRESHOLD_F2_WIDTH 16U +#define LPDDR4__MRR_TEMPCHK_NORM_THRESHOLD_F2__REG DENALI_CTL_127 +#define LPDDR4__MRR_TEMPCHK_NORM_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_127__MRR_TEMPCHK_NORM_THRESHOLD_F2 + +#define LPDDR4__DENALI_CTL_127__MRR_TEMPCHK_HIGH_THRESHOLD_F2_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_127__MRR_TEMPCHK_HIGH_THRESHOLD_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_127__MRR_TEMPCHK_HIGH_THRESHOLD_F2_WIDTH 16U +#define LPDDR4__MRR_TEMPCHK_HIGH_THRESHOLD_F2__REG DENALI_CTL_127 +#define LPDDR4__MRR_TEMPCHK_HIGH_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_127__MRR_TEMPCHK_HIGH_THRESHOLD_F2 + +#define LPDDR4__DENALI_CTL_128_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_128_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_128__MRR_TEMPCHK_TIMEOUT_F2_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_128__MRR_TEMPCHK_TIMEOUT_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_128__MRR_TEMPCHK_TIMEOUT_F2_WIDTH 16U +#define LPDDR4__MRR_TEMPCHK_TIMEOUT_F2__REG DENALI_CTL_128 +#define LPDDR4__MRR_TEMPCHK_TIMEOUT_F2__FLD LPDDR4__DENALI_CTL_128__MRR_TEMPCHK_TIMEOUT_F2 + +#define LPDDR4__DENALI_CTL_128__PPR_CONTROL_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_128__PPR_CONTROL_SHIFT 16U +#define LPDDR4__DENALI_CTL_128__PPR_CONTROL_WIDTH 1U +#define LPDDR4__DENALI_CTL_128__PPR_CONTROL_WOCLR 0U +#define LPDDR4__DENALI_CTL_128__PPR_CONTROL_WOSET 0U +#define LPDDR4__PPR_CONTROL__REG DENALI_CTL_128 +#define LPDDR4__PPR_CONTROL__FLD LPDDR4__DENALI_CTL_128__PPR_CONTROL + +#define LPDDR4__DENALI_CTL_128__PPR_COMMAND_MASK 0x07000000U +#define LPDDR4__DENALI_CTL_128__PPR_COMMAND_SHIFT 24U +#define LPDDR4__DENALI_CTL_128__PPR_COMMAND_WIDTH 3U +#define LPDDR4__PPR_COMMAND__REG DENALI_CTL_128 +#define LPDDR4__PPR_COMMAND__FLD LPDDR4__DENALI_CTL_128__PPR_COMMAND + +#define LPDDR4__DENALI_CTL_129_READ_MASK 0x01FFFFFFU +#define LPDDR4__DENALI_CTL_129_WRITE_MASK 0x01FFFFFFU +#define LPDDR4__DENALI_CTL_129__PPR_COMMAND_MRW_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_129__PPR_COMMAND_MRW_SHIFT 0U +#define LPDDR4__DENALI_CTL_129__PPR_COMMAND_MRW_WIDTH 8U +#define LPDDR4__PPR_COMMAND_MRW__REG DENALI_CTL_129 +#define LPDDR4__PPR_COMMAND_MRW__FLD LPDDR4__DENALI_CTL_129__PPR_COMMAND_MRW + +#define LPDDR4__DENALI_CTL_129__PPR_ROW_ADDRESS_MASK 0x01FFFF00U +#define LPDDR4__DENALI_CTL_129__PPR_ROW_ADDRESS_SHIFT 8U +#define LPDDR4__DENALI_CTL_129__PPR_ROW_ADDRESS_WIDTH 17U +#define LPDDR4__PPR_ROW_ADDRESS__REG DENALI_CTL_129 +#define LPDDR4__PPR_ROW_ADDRESS__FLD LPDDR4__DENALI_CTL_129__PPR_ROW_ADDRESS + +#define LPDDR4__DENALI_CTL_130_READ_MASK 0x01030107U +#define LPDDR4__DENALI_CTL_130_WRITE_MASK 0x01030107U +#define LPDDR4__DENALI_CTL_130__PPR_BANK_ADDRESS_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_130__PPR_BANK_ADDRESS_SHIFT 0U +#define LPDDR4__DENALI_CTL_130__PPR_BANK_ADDRESS_WIDTH 3U +#define LPDDR4__PPR_BANK_ADDRESS__REG DENALI_CTL_130 +#define LPDDR4__PPR_BANK_ADDRESS__FLD LPDDR4__DENALI_CTL_130__PPR_BANK_ADDRESS + +#define LPDDR4__DENALI_CTL_130__PPR_CS_ADDRESS_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_130__PPR_CS_ADDRESS_SHIFT 8U +#define LPDDR4__DENALI_CTL_130__PPR_CS_ADDRESS_WIDTH 1U +#define LPDDR4__DENALI_CTL_130__PPR_CS_ADDRESS_WOCLR 0U +#define LPDDR4__DENALI_CTL_130__PPR_CS_ADDRESS_WOSET 0U +#define LPDDR4__PPR_CS_ADDRESS__REG DENALI_CTL_130 +#define LPDDR4__PPR_CS_ADDRESS__FLD LPDDR4__DENALI_CTL_130__PPR_CS_ADDRESS + +#define LPDDR4__DENALI_CTL_130__PPR_STATUS_MASK 0x00030000U +#define LPDDR4__DENALI_CTL_130__PPR_STATUS_SHIFT 16U +#define LPDDR4__DENALI_CTL_130__PPR_STATUS_WIDTH 2U +#define LPDDR4__PPR_STATUS__REG DENALI_CTL_130 +#define LPDDR4__PPR_STATUS__FLD LPDDR4__DENALI_CTL_130__PPR_STATUS + +#define LPDDR4__DENALI_CTL_130__FM_OVRIDE_CONTROL_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_130__FM_OVRIDE_CONTROL_SHIFT 24U +#define LPDDR4__DENALI_CTL_130__FM_OVRIDE_CONTROL_WIDTH 1U +#define LPDDR4__DENALI_CTL_130__FM_OVRIDE_CONTROL_WOCLR 0U +#define LPDDR4__DENALI_CTL_130__FM_OVRIDE_CONTROL_WOSET 0U +#define LPDDR4__FM_OVRIDE_CONTROL__REG DENALI_CTL_130 +#define LPDDR4__FM_OVRIDE_CONTROL__FLD LPDDR4__DENALI_CTL_130__FM_OVRIDE_CONTROL + +#define LPDDR4__DENALI_CTL_131_READ_MASK 0xFFFFFF03U +#define LPDDR4__DENALI_CTL_131_WRITE_MASK 0xFFFFFF03U +#define LPDDR4__DENALI_CTL_131__LOWPOWER_REFRESH_ENABLE_MASK 0x00000003U +#define LPDDR4__DENALI_CTL_131__LOWPOWER_REFRESH_ENABLE_SHIFT 0U +#define LPDDR4__DENALI_CTL_131__LOWPOWER_REFRESH_ENABLE_WIDTH 2U +#define LPDDR4__LOWPOWER_REFRESH_ENABLE__REG DENALI_CTL_131 +#define LPDDR4__LOWPOWER_REFRESH_ENABLE__FLD LPDDR4__DENALI_CTL_131__LOWPOWER_REFRESH_ENABLE + +#define LPDDR4__DENALI_CTL_131__CKSRE_F0_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_131__CKSRE_F0_SHIFT 8U +#define LPDDR4__DENALI_CTL_131__CKSRE_F0_WIDTH 8U +#define LPDDR4__CKSRE_F0__REG DENALI_CTL_131 +#define LPDDR4__CKSRE_F0__FLD LPDDR4__DENALI_CTL_131__CKSRE_F0 + +#define LPDDR4__DENALI_CTL_131__CKSRX_F0_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_131__CKSRX_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_131__CKSRX_F0_WIDTH 8U +#define LPDDR4__CKSRX_F0__REG DENALI_CTL_131 +#define LPDDR4__CKSRX_F0__FLD LPDDR4__DENALI_CTL_131__CKSRX_F0 + +#define LPDDR4__DENALI_CTL_131__CKSRE_F1_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_131__CKSRE_F1_SHIFT 24U +#define LPDDR4__DENALI_CTL_131__CKSRE_F1_WIDTH 8U +#define LPDDR4__CKSRE_F1__REG DENALI_CTL_131 +#define LPDDR4__CKSRE_F1__FLD LPDDR4__DENALI_CTL_131__CKSRE_F1 + +#define LPDDR4__DENALI_CTL_132_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_132_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_132__CKSRX_F1_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_132__CKSRX_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_132__CKSRX_F1_WIDTH 8U +#define LPDDR4__CKSRX_F1__REG DENALI_CTL_132 +#define LPDDR4__CKSRX_F1__FLD LPDDR4__DENALI_CTL_132__CKSRX_F1 + +#define LPDDR4__DENALI_CTL_132__CKSRE_F2_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_132__CKSRE_F2_SHIFT 8U +#define LPDDR4__DENALI_CTL_132__CKSRE_F2_WIDTH 8U +#define LPDDR4__CKSRE_F2__REG DENALI_CTL_132 +#define LPDDR4__CKSRE_F2__FLD LPDDR4__DENALI_CTL_132__CKSRE_F2 + +#define LPDDR4__DENALI_CTL_132__CKSRX_F2_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_132__CKSRX_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_132__CKSRX_F2_WIDTH 8U +#define LPDDR4__CKSRX_F2__REG DENALI_CTL_132 +#define LPDDR4__CKSRX_F2__FLD LPDDR4__DENALI_CTL_132__CKSRX_F2 + +#define LPDDR4__DENALI_CTL_132__LP_CMD_MASK 0x7F000000U +#define LPDDR4__DENALI_CTL_132__LP_CMD_SHIFT 24U +#define LPDDR4__DENALI_CTL_132__LP_CMD_WIDTH 7U +#define LPDDR4__LP_CMD__REG DENALI_CTL_132 +#define LPDDR4__LP_CMD__FLD LPDDR4__DENALI_CTL_132__LP_CMD + +#define LPDDR4__DENALI_CTL_133_READ_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_CTL_133_WRITE_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_CTL_133__LPI_CTRL_IDLE_WAKEUP_F0_MASK 0x0000000FU +#define LPDDR4__DENALI_CTL_133__LPI_CTRL_IDLE_WAKEUP_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_133__LPI_CTRL_IDLE_WAKEUP_F0_WIDTH 4U +#define LPDDR4__LPI_CTRL_IDLE_WAKEUP_F0__REG DENALI_CTL_133 +#define LPDDR4__LPI_CTRL_IDLE_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_133__LPI_CTRL_IDLE_WAKEUP_F0 + +#define LPDDR4__DENALI_CTL_133__LPI_SR_SHORT_WAKEUP_F0_MASK 0x00000F00U +#define LPDDR4__DENALI_CTL_133__LPI_SR_SHORT_WAKEUP_F0_SHIFT 8U +#define LPDDR4__DENALI_CTL_133__LPI_SR_SHORT_WAKEUP_F0_WIDTH 4U +#define LPDDR4__LPI_SR_SHORT_WAKEUP_F0__REG DENALI_CTL_133 +#define LPDDR4__LPI_SR_SHORT_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_133__LPI_SR_SHORT_WAKEUP_F0 + +#define LPDDR4__DENALI_CTL_133__LPI_SR_LONG_WAKEUP_F0_MASK 0x000F0000U +#define LPDDR4__DENALI_CTL_133__LPI_SR_LONG_WAKEUP_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_133__LPI_SR_LONG_WAKEUP_F0_WIDTH 4U +#define LPDDR4__LPI_SR_LONG_WAKEUP_F0__REG DENALI_CTL_133 +#define LPDDR4__LPI_SR_LONG_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_133__LPI_SR_LONG_WAKEUP_F0 + +#define LPDDR4__DENALI_CTL_133__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0_MASK 0x0F000000U +#define LPDDR4__DENALI_CTL_133__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0_SHIFT 24U +#define LPDDR4__DENALI_CTL_133__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0_WIDTH 4U +#define LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0__REG DENALI_CTL_133 +#define LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_133__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0 + +#define LPDDR4__DENALI_CTL_134_READ_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_CTL_134_WRITE_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_CTL_134__LPI_PD_WAKEUP_F0_MASK 0x0000000FU +#define LPDDR4__DENALI_CTL_134__LPI_PD_WAKEUP_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_134__LPI_PD_WAKEUP_F0_WIDTH 4U +#define LPDDR4__LPI_PD_WAKEUP_F0__REG DENALI_CTL_134 +#define LPDDR4__LPI_PD_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_134__LPI_PD_WAKEUP_F0 + +#define LPDDR4__DENALI_CTL_134__LPI_SRPD_SHORT_WAKEUP_F0_MASK 0x00000F00U +#define LPDDR4__DENALI_CTL_134__LPI_SRPD_SHORT_WAKEUP_F0_SHIFT 8U +#define LPDDR4__DENALI_CTL_134__LPI_SRPD_SHORT_WAKEUP_F0_WIDTH 4U +#define LPDDR4__LPI_SRPD_SHORT_WAKEUP_F0__REG DENALI_CTL_134 +#define LPDDR4__LPI_SRPD_SHORT_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_134__LPI_SRPD_SHORT_WAKEUP_F0 + +#define LPDDR4__DENALI_CTL_134__LPI_SRPD_LONG_WAKEUP_F0_MASK 0x000F0000U +#define LPDDR4__DENALI_CTL_134__LPI_SRPD_LONG_WAKEUP_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_134__LPI_SRPD_LONG_WAKEUP_F0_WIDTH 4U +#define LPDDR4__LPI_SRPD_LONG_WAKEUP_F0__REG DENALI_CTL_134 +#define LPDDR4__LPI_SRPD_LONG_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_134__LPI_SRPD_LONG_WAKEUP_F0 + +#define LPDDR4__DENALI_CTL_134__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0_MASK 0x0F000000U +#define LPDDR4__DENALI_CTL_134__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0_SHIFT 24U +#define LPDDR4__DENALI_CTL_134__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0_WIDTH 4U +#define LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0__REG DENALI_CTL_134 +#define LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_134__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0 + +#define LPDDR4__DENALI_CTL_135_READ_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_CTL_135_WRITE_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_CTL_135__LPI_TIMER_WAKEUP_F0_MASK 0x0000000FU +#define LPDDR4__DENALI_CTL_135__LPI_TIMER_WAKEUP_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_135__LPI_TIMER_WAKEUP_F0_WIDTH 4U +#define LPDDR4__LPI_TIMER_WAKEUP_F0__REG DENALI_CTL_135 +#define LPDDR4__LPI_TIMER_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_135__LPI_TIMER_WAKEUP_F0 + +#define LPDDR4__DENALI_CTL_135__LPI_CTRL_IDLE_WAKEUP_F1_MASK 0x00000F00U +#define LPDDR4__DENALI_CTL_135__LPI_CTRL_IDLE_WAKEUP_F1_SHIFT 8U +#define LPDDR4__DENALI_CTL_135__LPI_CTRL_IDLE_WAKEUP_F1_WIDTH 4U +#define LPDDR4__LPI_CTRL_IDLE_WAKEUP_F1__REG DENALI_CTL_135 +#define LPDDR4__LPI_CTRL_IDLE_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_135__LPI_CTRL_IDLE_WAKEUP_F1 + +#define LPDDR4__DENALI_CTL_135__LPI_SR_SHORT_WAKEUP_F1_MASK 0x000F0000U +#define LPDDR4__DENALI_CTL_135__LPI_SR_SHORT_WAKEUP_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_135__LPI_SR_SHORT_WAKEUP_F1_WIDTH 4U +#define LPDDR4__LPI_SR_SHORT_WAKEUP_F1__REG DENALI_CTL_135 +#define LPDDR4__LPI_SR_SHORT_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_135__LPI_SR_SHORT_WAKEUP_F1 + +#define LPDDR4__DENALI_CTL_135__LPI_SR_LONG_WAKEUP_F1_MASK 0x0F000000U +#define LPDDR4__DENALI_CTL_135__LPI_SR_LONG_WAKEUP_F1_SHIFT 24U +#define LPDDR4__DENALI_CTL_135__LPI_SR_LONG_WAKEUP_F1_WIDTH 4U +#define LPDDR4__LPI_SR_LONG_WAKEUP_F1__REG DENALI_CTL_135 +#define LPDDR4__LPI_SR_LONG_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_135__LPI_SR_LONG_WAKEUP_F1 + +#define LPDDR4__DENALI_CTL_136_READ_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_CTL_136_WRITE_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_CTL_136__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1_MASK 0x0000000FU +#define LPDDR4__DENALI_CTL_136__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_136__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1_WIDTH 4U +#define LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1__REG DENALI_CTL_136 +#define LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_136__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1 + +#define LPDDR4__DENALI_CTL_136__LPI_PD_WAKEUP_F1_MASK 0x00000F00U +#define LPDDR4__DENALI_CTL_136__LPI_PD_WAKEUP_F1_SHIFT 8U +#define LPDDR4__DENALI_CTL_136__LPI_PD_WAKEUP_F1_WIDTH 4U +#define LPDDR4__LPI_PD_WAKEUP_F1__REG DENALI_CTL_136 +#define LPDDR4__LPI_PD_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_136__LPI_PD_WAKEUP_F1 + +#define LPDDR4__DENALI_CTL_136__LPI_SRPD_SHORT_WAKEUP_F1_MASK 0x000F0000U +#define LPDDR4__DENALI_CTL_136__LPI_SRPD_SHORT_WAKEUP_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_136__LPI_SRPD_SHORT_WAKEUP_F1_WIDTH 4U +#define LPDDR4__LPI_SRPD_SHORT_WAKEUP_F1__REG DENALI_CTL_136 +#define LPDDR4__LPI_SRPD_SHORT_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_136__LPI_SRPD_SHORT_WAKEUP_F1 + +#define LPDDR4__DENALI_CTL_136__LPI_SRPD_LONG_WAKEUP_F1_MASK 0x0F000000U +#define LPDDR4__DENALI_CTL_136__LPI_SRPD_LONG_WAKEUP_F1_SHIFT 24U +#define LPDDR4__DENALI_CTL_136__LPI_SRPD_LONG_WAKEUP_F1_WIDTH 4U +#define LPDDR4__LPI_SRPD_LONG_WAKEUP_F1__REG DENALI_CTL_136 +#define LPDDR4__LPI_SRPD_LONG_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_136__LPI_SRPD_LONG_WAKEUP_F1 + +#define LPDDR4__DENALI_CTL_137_READ_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_CTL_137_WRITE_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_CTL_137__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1_MASK 0x0000000FU +#define LPDDR4__DENALI_CTL_137__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_137__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1_WIDTH 4U +#define LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1__REG DENALI_CTL_137 +#define LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_137__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1 + +#define LPDDR4__DENALI_CTL_137__LPI_TIMER_WAKEUP_F1_MASK 0x00000F00U +#define LPDDR4__DENALI_CTL_137__LPI_TIMER_WAKEUP_F1_SHIFT 8U +#define LPDDR4__DENALI_CTL_137__LPI_TIMER_WAKEUP_F1_WIDTH 4U +#define LPDDR4__LPI_TIMER_WAKEUP_F1__REG DENALI_CTL_137 +#define LPDDR4__LPI_TIMER_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_137__LPI_TIMER_WAKEUP_F1 + +#define LPDDR4__DENALI_CTL_137__LPI_CTRL_IDLE_WAKEUP_F2_MASK 0x000F0000U +#define LPDDR4__DENALI_CTL_137__LPI_CTRL_IDLE_WAKEUP_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_137__LPI_CTRL_IDLE_WAKEUP_F2_WIDTH 4U +#define LPDDR4__LPI_CTRL_IDLE_WAKEUP_F2__REG DENALI_CTL_137 +#define LPDDR4__LPI_CTRL_IDLE_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_137__LPI_CTRL_IDLE_WAKEUP_F2 + +#define LPDDR4__DENALI_CTL_137__LPI_SR_SHORT_WAKEUP_F2_MASK 0x0F000000U +#define LPDDR4__DENALI_CTL_137__LPI_SR_SHORT_WAKEUP_F2_SHIFT 24U +#define LPDDR4__DENALI_CTL_137__LPI_SR_SHORT_WAKEUP_F2_WIDTH 4U +#define LPDDR4__LPI_SR_SHORT_WAKEUP_F2__REG DENALI_CTL_137 +#define LPDDR4__LPI_SR_SHORT_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_137__LPI_SR_SHORT_WAKEUP_F2 + +#define LPDDR4__DENALI_CTL_138_READ_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_CTL_138_WRITE_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_CTL_138__LPI_SR_LONG_WAKEUP_F2_MASK 0x0000000FU +#define LPDDR4__DENALI_CTL_138__LPI_SR_LONG_WAKEUP_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_138__LPI_SR_LONG_WAKEUP_F2_WIDTH 4U +#define LPDDR4__LPI_SR_LONG_WAKEUP_F2__REG DENALI_CTL_138 +#define LPDDR4__LPI_SR_LONG_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_138__LPI_SR_LONG_WAKEUP_F2 + +#define LPDDR4__DENALI_CTL_138__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2_MASK 0x00000F00U +#define LPDDR4__DENALI_CTL_138__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2_SHIFT 8U +#define LPDDR4__DENALI_CTL_138__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2_WIDTH 4U +#define LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2__REG DENALI_CTL_138 +#define LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_138__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2 + +#define LPDDR4__DENALI_CTL_138__LPI_PD_WAKEUP_F2_MASK 0x000F0000U +#define LPDDR4__DENALI_CTL_138__LPI_PD_WAKEUP_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_138__LPI_PD_WAKEUP_F2_WIDTH 4U +#define LPDDR4__LPI_PD_WAKEUP_F2__REG DENALI_CTL_138 +#define LPDDR4__LPI_PD_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_138__LPI_PD_WAKEUP_F2 + +#define LPDDR4__DENALI_CTL_138__LPI_SRPD_SHORT_WAKEUP_F2_MASK 0x0F000000U +#define LPDDR4__DENALI_CTL_138__LPI_SRPD_SHORT_WAKEUP_F2_SHIFT 24U +#define LPDDR4__DENALI_CTL_138__LPI_SRPD_SHORT_WAKEUP_F2_WIDTH 4U +#define LPDDR4__LPI_SRPD_SHORT_WAKEUP_F2__REG DENALI_CTL_138 +#define LPDDR4__LPI_SRPD_SHORT_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_138__LPI_SRPD_SHORT_WAKEUP_F2 + +#define LPDDR4__DENALI_CTL_139_READ_MASK 0x3F0F0F0FU +#define LPDDR4__DENALI_CTL_139_WRITE_MASK 0x3F0F0F0FU +#define LPDDR4__DENALI_CTL_139__LPI_SRPD_LONG_WAKEUP_F2_MASK 0x0000000FU +#define LPDDR4__DENALI_CTL_139__LPI_SRPD_LONG_WAKEUP_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_139__LPI_SRPD_LONG_WAKEUP_F2_WIDTH 4U +#define LPDDR4__LPI_SRPD_LONG_WAKEUP_F2__REG DENALI_CTL_139 +#define LPDDR4__LPI_SRPD_LONG_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_139__LPI_SRPD_LONG_WAKEUP_F2 + +#define LPDDR4__DENALI_CTL_139__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2_MASK 0x00000F00U +#define LPDDR4__DENALI_CTL_139__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2_SHIFT 8U +#define LPDDR4__DENALI_CTL_139__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2_WIDTH 4U +#define LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2__REG DENALI_CTL_139 +#define LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_139__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2 + +#define LPDDR4__DENALI_CTL_139__LPI_TIMER_WAKEUP_F2_MASK 0x000F0000U +#define LPDDR4__DENALI_CTL_139__LPI_TIMER_WAKEUP_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_139__LPI_TIMER_WAKEUP_F2_WIDTH 4U +#define LPDDR4__LPI_TIMER_WAKEUP_F2__REG DENALI_CTL_139 +#define LPDDR4__LPI_TIMER_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_139__LPI_TIMER_WAKEUP_F2 + +#define LPDDR4__DENALI_CTL_139__LPI_WAKEUP_EN_MASK 0x3F000000U +#define LPDDR4__DENALI_CTL_139__LPI_WAKEUP_EN_SHIFT 24U +#define LPDDR4__DENALI_CTL_139__LPI_WAKEUP_EN_WIDTH 6U +#define LPDDR4__LPI_WAKEUP_EN__REG DENALI_CTL_139 +#define LPDDR4__LPI_WAKEUP_EN__FLD LPDDR4__DENALI_CTL_139__LPI_WAKEUP_EN + +#define LPDDR4__DENALI_CTL_140_READ_MASK 0x070FFF01U +#define LPDDR4__DENALI_CTL_140_WRITE_MASK 0x070FFF01U +#define LPDDR4__DENALI_CTL_140__LPI_CTRL_REQ_EN_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_140__LPI_CTRL_REQ_EN_SHIFT 0U +#define LPDDR4__DENALI_CTL_140__LPI_CTRL_REQ_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_140__LPI_CTRL_REQ_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_140__LPI_CTRL_REQ_EN_WOSET 0U +#define LPDDR4__LPI_CTRL_REQ_EN__REG DENALI_CTL_140 +#define LPDDR4__LPI_CTRL_REQ_EN__FLD LPDDR4__DENALI_CTL_140__LPI_CTRL_REQ_EN + +#define LPDDR4__DENALI_CTL_140__LPI_WAKEUP_TIMEOUT_MASK 0x000FFF00U +#define LPDDR4__DENALI_CTL_140__LPI_WAKEUP_TIMEOUT_SHIFT 8U +#define LPDDR4__DENALI_CTL_140__LPI_WAKEUP_TIMEOUT_WIDTH 12U +#define LPDDR4__LPI_WAKEUP_TIMEOUT__REG DENALI_CTL_140 +#define LPDDR4__LPI_WAKEUP_TIMEOUT__FLD LPDDR4__DENALI_CTL_140__LPI_WAKEUP_TIMEOUT + +#define LPDDR4__DENALI_CTL_140__TDFI_LP_RESP_MASK 0x07000000U +#define LPDDR4__DENALI_CTL_140__TDFI_LP_RESP_SHIFT 24U +#define LPDDR4__DENALI_CTL_140__TDFI_LP_RESP_WIDTH 3U +#define LPDDR4__TDFI_LP_RESP__REG DENALI_CTL_140 +#define LPDDR4__TDFI_LP_RESP__FLD LPDDR4__DENALI_CTL_140__TDFI_LP_RESP + +#define LPDDR4__DENALI_CTL_141_READ_MASK 0x0F0F7F7FU +#define LPDDR4__DENALI_CTL_141_WRITE_MASK 0x0F0F7F7FU +#define LPDDR4__DENALI_CTL_141__LP_STATE_CS0_MASK 0x0000007FU +#define LPDDR4__DENALI_CTL_141__LP_STATE_CS0_SHIFT 0U +#define LPDDR4__DENALI_CTL_141__LP_STATE_CS0_WIDTH 7U +#define LPDDR4__LP_STATE_CS0__REG DENALI_CTL_141 +#define LPDDR4__LP_STATE_CS0__FLD LPDDR4__DENALI_CTL_141__LP_STATE_CS0 + +#define LPDDR4__DENALI_CTL_141__LP_STATE_CS1_MASK 0x00007F00U +#define LPDDR4__DENALI_CTL_141__LP_STATE_CS1_SHIFT 8U +#define LPDDR4__DENALI_CTL_141__LP_STATE_CS1_WIDTH 7U +#define LPDDR4__LP_STATE_CS1__REG DENALI_CTL_141 +#define LPDDR4__LP_STATE_CS1__FLD LPDDR4__DENALI_CTL_141__LP_STATE_CS1 + +#define LPDDR4__DENALI_CTL_141__LP_AUTO_ENTRY_EN_MASK 0x000F0000U +#define LPDDR4__DENALI_CTL_141__LP_AUTO_ENTRY_EN_SHIFT 16U +#define LPDDR4__DENALI_CTL_141__LP_AUTO_ENTRY_EN_WIDTH 4U +#define LPDDR4__LP_AUTO_ENTRY_EN__REG DENALI_CTL_141 +#define LPDDR4__LP_AUTO_ENTRY_EN__FLD LPDDR4__DENALI_CTL_141__LP_AUTO_ENTRY_EN + +#define LPDDR4__DENALI_CTL_141__LP_AUTO_EXIT_EN_MASK 0x0F000000U +#define LPDDR4__DENALI_CTL_141__LP_AUTO_EXIT_EN_SHIFT 24U +#define LPDDR4__DENALI_CTL_141__LP_AUTO_EXIT_EN_WIDTH 4U +#define LPDDR4__LP_AUTO_EXIT_EN__REG DENALI_CTL_141 +#define LPDDR4__LP_AUTO_EXIT_EN__FLD LPDDR4__DENALI_CTL_141__LP_AUTO_EXIT_EN + +#define LPDDR4__DENALI_CTL_142_READ_MASK 0x000FFF07U +#define LPDDR4__DENALI_CTL_142_WRITE_MASK 0x000FFF07U +#define LPDDR4__DENALI_CTL_142__LP_AUTO_MEM_GATE_EN_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_142__LP_AUTO_MEM_GATE_EN_SHIFT 0U +#define LPDDR4__DENALI_CTL_142__LP_AUTO_MEM_GATE_EN_WIDTH 3U +#define LPDDR4__LP_AUTO_MEM_GATE_EN__REG DENALI_CTL_142 +#define LPDDR4__LP_AUTO_MEM_GATE_EN__FLD LPDDR4__DENALI_CTL_142__LP_AUTO_MEM_GATE_EN + +#define LPDDR4__DENALI_CTL_142__LP_AUTO_PD_IDLE_MASK 0x000FFF00U +#define LPDDR4__DENALI_CTL_142__LP_AUTO_PD_IDLE_SHIFT 8U +#define LPDDR4__DENALI_CTL_142__LP_AUTO_PD_IDLE_WIDTH 12U +#define LPDDR4__LP_AUTO_PD_IDLE__REG DENALI_CTL_142 +#define LPDDR4__LP_AUTO_PD_IDLE__FLD LPDDR4__DENALI_CTL_142__LP_AUTO_PD_IDLE + +#define LPDDR4__DENALI_CTL_143_READ_MASK 0xFFFF0FFFU +#define LPDDR4__DENALI_CTL_143_WRITE_MASK 0xFFFF0FFFU +#define LPDDR4__DENALI_CTL_143__LP_AUTO_SR_SHORT_IDLE_MASK 0x00000FFFU +#define LPDDR4__DENALI_CTL_143__LP_AUTO_SR_SHORT_IDLE_SHIFT 0U +#define LPDDR4__DENALI_CTL_143__LP_AUTO_SR_SHORT_IDLE_WIDTH 12U +#define LPDDR4__LP_AUTO_SR_SHORT_IDLE__REG DENALI_CTL_143 +#define LPDDR4__LP_AUTO_SR_SHORT_IDLE__FLD LPDDR4__DENALI_CTL_143__LP_AUTO_SR_SHORT_IDLE + +#define LPDDR4__DENALI_CTL_143__LP_AUTO_SR_LONG_IDLE_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_143__LP_AUTO_SR_LONG_IDLE_SHIFT 16U +#define LPDDR4__DENALI_CTL_143__LP_AUTO_SR_LONG_IDLE_WIDTH 8U +#define LPDDR4__LP_AUTO_SR_LONG_IDLE__REG DENALI_CTL_143 +#define LPDDR4__LP_AUTO_SR_LONG_IDLE__FLD LPDDR4__DENALI_CTL_143__LP_AUTO_SR_LONG_IDLE + +#define LPDDR4__DENALI_CTL_143__LP_AUTO_SR_LONG_MC_GATE_IDLE_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_143__LP_AUTO_SR_LONG_MC_GATE_IDLE_SHIFT 24U +#define LPDDR4__DENALI_CTL_143__LP_AUTO_SR_LONG_MC_GATE_IDLE_WIDTH 8U +#define LPDDR4__LP_AUTO_SR_LONG_MC_GATE_IDLE__REG DENALI_CTL_143 +#define LPDDR4__LP_AUTO_SR_LONG_MC_GATE_IDLE__FLD LPDDR4__DENALI_CTL_143__LP_AUTO_SR_LONG_MC_GATE_IDLE + +#define LPDDR4__DENALI_CTL_144_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_144_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_144__HW_PROMOTE_THRESHOLD_F0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_144__HW_PROMOTE_THRESHOLD_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_144__HW_PROMOTE_THRESHOLD_F0_WIDTH 16U +#define LPDDR4__HW_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_144 +#define LPDDR4__HW_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_144__HW_PROMOTE_THRESHOLD_F0 + +#define LPDDR4__DENALI_CTL_144__HW_PROMOTE_THRESHOLD_F1_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_144__HW_PROMOTE_THRESHOLD_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_144__HW_PROMOTE_THRESHOLD_F1_WIDTH 16U +#define LPDDR4__HW_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_144 +#define LPDDR4__HW_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_144__HW_PROMOTE_THRESHOLD_F1 + +#define LPDDR4__DENALI_CTL_145_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_145_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_145__HW_PROMOTE_THRESHOLD_F2_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_145__HW_PROMOTE_THRESHOLD_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_145__HW_PROMOTE_THRESHOLD_F2_WIDTH 16U +#define LPDDR4__HW_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_145 +#define LPDDR4__HW_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_145__HW_PROMOTE_THRESHOLD_F2 + +#define LPDDR4__DENALI_CTL_145__LPC_PROMOTE_THRESHOLD_F0_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_145__LPC_PROMOTE_THRESHOLD_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_145__LPC_PROMOTE_THRESHOLD_F0_WIDTH 16U +#define LPDDR4__LPC_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_145 +#define LPDDR4__LPC_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_145__LPC_PROMOTE_THRESHOLD_F0 + +#define LPDDR4__DENALI_CTL_146_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_146_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_146__LPC_PROMOTE_THRESHOLD_F1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_146__LPC_PROMOTE_THRESHOLD_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_146__LPC_PROMOTE_THRESHOLD_F1_WIDTH 16U +#define LPDDR4__LPC_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_146 +#define LPDDR4__LPC_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_146__LPC_PROMOTE_THRESHOLD_F1 + +#define LPDDR4__DENALI_CTL_146__LPC_PROMOTE_THRESHOLD_F2_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_146__LPC_PROMOTE_THRESHOLD_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_146__LPC_PROMOTE_THRESHOLD_F2_WIDTH 16U +#define LPDDR4__LPC_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_146 +#define LPDDR4__LPC_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_146__LPC_PROMOTE_THRESHOLD_F2 + +#define LPDDR4__DENALI_CTL_147_READ_MASK 0x01010101U +#define LPDDR4__DENALI_CTL_147_WRITE_MASK 0x01010101U +#define LPDDR4__DENALI_CTL_147__LPC_SR_CTRLUPD_EN_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_147__LPC_SR_CTRLUPD_EN_SHIFT 0U +#define LPDDR4__DENALI_CTL_147__LPC_SR_CTRLUPD_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_147__LPC_SR_CTRLUPD_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_147__LPC_SR_CTRLUPD_EN_WOSET 0U +#define LPDDR4__LPC_SR_CTRLUPD_EN__REG DENALI_CTL_147 +#define LPDDR4__LPC_SR_CTRLUPD_EN__FLD LPDDR4__DENALI_CTL_147__LPC_SR_CTRLUPD_EN + +#define LPDDR4__DENALI_CTL_147__LPC_SR_PHYUPD_EN_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_147__LPC_SR_PHYUPD_EN_SHIFT 8U +#define LPDDR4__DENALI_CTL_147__LPC_SR_PHYUPD_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_147__LPC_SR_PHYUPD_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_147__LPC_SR_PHYUPD_EN_WOSET 0U +#define LPDDR4__LPC_SR_PHYUPD_EN__REG DENALI_CTL_147 +#define LPDDR4__LPC_SR_PHYUPD_EN__FLD LPDDR4__DENALI_CTL_147__LPC_SR_PHYUPD_EN + +#define LPDDR4__DENALI_CTL_147__LPC_SR_PHYMSTR_EN_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_147__LPC_SR_PHYMSTR_EN_SHIFT 16U +#define LPDDR4__DENALI_CTL_147__LPC_SR_PHYMSTR_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_147__LPC_SR_PHYMSTR_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_147__LPC_SR_PHYMSTR_EN_WOSET 0U +#define LPDDR4__LPC_SR_PHYMSTR_EN__REG DENALI_CTL_147 +#define LPDDR4__LPC_SR_PHYMSTR_EN__FLD LPDDR4__DENALI_CTL_147__LPC_SR_PHYMSTR_EN + +#define LPDDR4__DENALI_CTL_147__MC_RESERVED17_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_147__MC_RESERVED17_SHIFT 24U +#define LPDDR4__DENALI_CTL_147__MC_RESERVED17_WIDTH 1U +#define LPDDR4__DENALI_CTL_147__MC_RESERVED17_WOCLR 0U +#define LPDDR4__DENALI_CTL_147__MC_RESERVED17_WOSET 0U +#define LPDDR4__MC_RESERVED17__REG DENALI_CTL_147 +#define LPDDR4__MC_RESERVED17__FLD LPDDR4__DENALI_CTL_147__MC_RESERVED17 + +#define LPDDR4__DENALI_CTL_148_READ_MASK 0x3F3F0101U +#define LPDDR4__DENALI_CTL_148_WRITE_MASK 0x3F3F0101U +#define LPDDR4__DENALI_CTL_148__LPC_SR_ZQ_EN_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_148__LPC_SR_ZQ_EN_SHIFT 0U +#define LPDDR4__DENALI_CTL_148__LPC_SR_ZQ_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_148__LPC_SR_ZQ_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_148__LPC_SR_ZQ_EN_WOSET 0U +#define LPDDR4__LPC_SR_ZQ_EN__REG DENALI_CTL_148 +#define LPDDR4__LPC_SR_ZQ_EN__FLD LPDDR4__DENALI_CTL_148__LPC_SR_ZQ_EN + +#define LPDDR4__DENALI_CTL_148__PCPCS_PD_EN_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_148__PCPCS_PD_EN_SHIFT 8U +#define LPDDR4__DENALI_CTL_148__PCPCS_PD_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_148__PCPCS_PD_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_148__PCPCS_PD_EN_WOSET 0U +#define LPDDR4__PCPCS_PD_EN__REG DENALI_CTL_148 +#define LPDDR4__PCPCS_PD_EN__FLD LPDDR4__DENALI_CTL_148__PCPCS_PD_EN + +#define LPDDR4__DENALI_CTL_148__PCPCS_PD_ENTER_DEPTH_MASK 0x003F0000U +#define LPDDR4__DENALI_CTL_148__PCPCS_PD_ENTER_DEPTH_SHIFT 16U +#define LPDDR4__DENALI_CTL_148__PCPCS_PD_ENTER_DEPTH_WIDTH 6U +#define LPDDR4__PCPCS_PD_ENTER_DEPTH__REG DENALI_CTL_148 +#define LPDDR4__PCPCS_PD_ENTER_DEPTH__FLD LPDDR4__DENALI_CTL_148__PCPCS_PD_ENTER_DEPTH + +#define LPDDR4__DENALI_CTL_148__PCPCS_PD_EXIT_DEPTH_MASK 0x3F000000U +#define LPDDR4__DENALI_CTL_148__PCPCS_PD_EXIT_DEPTH_SHIFT 24U +#define LPDDR4__DENALI_CTL_148__PCPCS_PD_EXIT_DEPTH_WIDTH 6U +#define LPDDR4__PCPCS_PD_EXIT_DEPTH__REG DENALI_CTL_148 +#define LPDDR4__PCPCS_PD_EXIT_DEPTH__FLD LPDDR4__DENALI_CTL_148__PCPCS_PD_EXIT_DEPTH + +#define LPDDR4__DENALI_CTL_149_READ_MASK 0x01FF03FFU +#define LPDDR4__DENALI_CTL_149_WRITE_MASK 0x01FF03FFU +#define LPDDR4__DENALI_CTL_149__PCPCS_PD_ENTER_TIMER_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_149__PCPCS_PD_ENTER_TIMER_SHIFT 0U +#define LPDDR4__DENALI_CTL_149__PCPCS_PD_ENTER_TIMER_WIDTH 8U +#define LPDDR4__PCPCS_PD_ENTER_TIMER__REG DENALI_CTL_149 +#define LPDDR4__PCPCS_PD_ENTER_TIMER__FLD LPDDR4__DENALI_CTL_149__PCPCS_PD_ENTER_TIMER + +#define LPDDR4__DENALI_CTL_149__PCPCS_PD_MASK_MASK 0x00000300U +#define LPDDR4__DENALI_CTL_149__PCPCS_PD_MASK_SHIFT 8U +#define LPDDR4__DENALI_CTL_149__PCPCS_PD_MASK_WIDTH 2U +#define LPDDR4__PCPCS_PD_MASK__REG DENALI_CTL_149 +#define LPDDR4__PCPCS_PD_MASK__FLD LPDDR4__DENALI_CTL_149__PCPCS_PD_MASK + +#define LPDDR4__DENALI_CTL_149__MC_RESERVED18_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_149__MC_RESERVED18_SHIFT 16U +#define LPDDR4__DENALI_CTL_149__MC_RESERVED18_WIDTH 8U +#define LPDDR4__MC_RESERVED18__REG DENALI_CTL_149 +#define LPDDR4__MC_RESERVED18__FLD LPDDR4__DENALI_CTL_149__MC_RESERVED18 + +#define LPDDR4__DENALI_CTL_149__DFS_ENABLE_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_149__DFS_ENABLE_SHIFT 24U +#define LPDDR4__DENALI_CTL_149__DFS_ENABLE_WIDTH 1U +#define LPDDR4__DENALI_CTL_149__DFS_ENABLE_WOCLR 0U +#define LPDDR4__DENALI_CTL_149__DFS_ENABLE_WOSET 0U +#define LPDDR4__DFS_ENABLE__REG DENALI_CTL_149 +#define LPDDR4__DFS_ENABLE__FLD LPDDR4__DENALI_CTL_149__DFS_ENABLE + +#define LPDDR4__DENALI_CTL_150_READ_MASK 0xFFFF03FFU +#define LPDDR4__DENALI_CTL_150_WRITE_MASK 0xFFFF03FFU +#define LPDDR4__DENALI_CTL_150__TDFI_INIT_START_F0_MASK 0x000003FFU +#define LPDDR4__DENALI_CTL_150__TDFI_INIT_START_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_150__TDFI_INIT_START_F0_WIDTH 10U +#define LPDDR4__TDFI_INIT_START_F0__REG DENALI_CTL_150 +#define LPDDR4__TDFI_INIT_START_F0__FLD LPDDR4__DENALI_CTL_150__TDFI_INIT_START_F0 + +#define LPDDR4__DENALI_CTL_150__TDFI_INIT_COMPLETE_F0_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_150__TDFI_INIT_COMPLETE_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_150__TDFI_INIT_COMPLETE_F0_WIDTH 16U +#define LPDDR4__TDFI_INIT_COMPLETE_F0__REG DENALI_CTL_150 +#define LPDDR4__TDFI_INIT_COMPLETE_F0__FLD LPDDR4__DENALI_CTL_150__TDFI_INIT_COMPLETE_F0 + +#define LPDDR4__DENALI_CTL_151_READ_MASK 0xFFFF03FFU +#define LPDDR4__DENALI_CTL_151_WRITE_MASK 0xFFFF03FFU +#define LPDDR4__DENALI_CTL_151__TDFI_INIT_START_F1_MASK 0x000003FFU +#define LPDDR4__DENALI_CTL_151__TDFI_INIT_START_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_151__TDFI_INIT_START_F1_WIDTH 10U +#define LPDDR4__TDFI_INIT_START_F1__REG DENALI_CTL_151 +#define LPDDR4__TDFI_INIT_START_F1__FLD LPDDR4__DENALI_CTL_151__TDFI_INIT_START_F1 + +#define LPDDR4__DENALI_CTL_151__TDFI_INIT_COMPLETE_F1_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_151__TDFI_INIT_COMPLETE_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_151__TDFI_INIT_COMPLETE_F1_WIDTH 16U +#define LPDDR4__TDFI_INIT_COMPLETE_F1__REG DENALI_CTL_151 +#define LPDDR4__TDFI_INIT_COMPLETE_F1__FLD LPDDR4__DENALI_CTL_151__TDFI_INIT_COMPLETE_F1 + +#define LPDDR4__DENALI_CTL_152_READ_MASK 0xFFFF03FFU +#define LPDDR4__DENALI_CTL_152_WRITE_MASK 0xFFFF03FFU +#define LPDDR4__DENALI_CTL_152__TDFI_INIT_START_F2_MASK 0x000003FFU +#define LPDDR4__DENALI_CTL_152__TDFI_INIT_START_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_152__TDFI_INIT_START_F2_WIDTH 10U +#define LPDDR4__TDFI_INIT_START_F2__REG DENALI_CTL_152 +#define LPDDR4__TDFI_INIT_START_F2__FLD LPDDR4__DENALI_CTL_152__TDFI_INIT_START_F2 + +#define LPDDR4__DENALI_CTL_152__TDFI_INIT_COMPLETE_F2_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_152__TDFI_INIT_COMPLETE_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_152__TDFI_INIT_COMPLETE_F2_WIDTH 16U +#define LPDDR4__TDFI_INIT_COMPLETE_F2__REG DENALI_CTL_152 +#define LPDDR4__TDFI_INIT_COMPLETE_F2__FLD LPDDR4__DENALI_CTL_152__TDFI_INIT_COMPLETE_F2 + +#define LPDDR4__DENALI_CTL_153_READ_MASK 0x00000103U +#define LPDDR4__DENALI_CTL_153_WRITE_MASK 0x00000103U +#define LPDDR4__DENALI_CTL_153__CURRENT_REG_COPY_MASK 0x00000003U +#define LPDDR4__DENALI_CTL_153__CURRENT_REG_COPY_SHIFT 0U +#define LPDDR4__DENALI_CTL_153__CURRENT_REG_COPY_WIDTH 2U +#define LPDDR4__CURRENT_REG_COPY__REG DENALI_CTL_153 +#define LPDDR4__CURRENT_REG_COPY__FLD LPDDR4__DENALI_CTL_153__CURRENT_REG_COPY + +#define LPDDR4__DENALI_CTL_153__DFS_PHY_REG_WRITE_EN_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_153__DFS_PHY_REG_WRITE_EN_SHIFT 8U +#define LPDDR4__DENALI_CTL_153__DFS_PHY_REG_WRITE_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_153__DFS_PHY_REG_WRITE_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_153__DFS_PHY_REG_WRITE_EN_WOSET 0U +#define LPDDR4__DFS_PHY_REG_WRITE_EN__REG DENALI_CTL_153 +#define LPDDR4__DFS_PHY_REG_WRITE_EN__FLD LPDDR4__DENALI_CTL_153__DFS_PHY_REG_WRITE_EN + +#define LPDDR4__DENALI_CTL_154_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_154_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_154__DFS_PHY_REG_WRITE_ADDR_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_154__DFS_PHY_REG_WRITE_ADDR_SHIFT 0U +#define LPDDR4__DENALI_CTL_154__DFS_PHY_REG_WRITE_ADDR_WIDTH 32U +#define LPDDR4__DFS_PHY_REG_WRITE_ADDR__REG DENALI_CTL_154 +#define LPDDR4__DFS_PHY_REG_WRITE_ADDR__FLD LPDDR4__DENALI_CTL_154__DFS_PHY_REG_WRITE_ADDR + +#define LPDDR4__DENALI_CTL_155_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_155_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_155__DFS_PHY_REG_WRITE_DATA_F0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_155__DFS_PHY_REG_WRITE_DATA_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_155__DFS_PHY_REG_WRITE_DATA_F0_WIDTH 32U +#define LPDDR4__DFS_PHY_REG_WRITE_DATA_F0__REG DENALI_CTL_155 +#define LPDDR4__DFS_PHY_REG_WRITE_DATA_F0__FLD LPDDR4__DENALI_CTL_155__DFS_PHY_REG_WRITE_DATA_F0 + +#define LPDDR4__DENALI_CTL_156_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_156_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_156__DFS_PHY_REG_WRITE_DATA_F1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_156__DFS_PHY_REG_WRITE_DATA_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_156__DFS_PHY_REG_WRITE_DATA_F1_WIDTH 32U +#define LPDDR4__DFS_PHY_REG_WRITE_DATA_F1__REG DENALI_CTL_156 +#define LPDDR4__DFS_PHY_REG_WRITE_DATA_F1__FLD LPDDR4__DENALI_CTL_156__DFS_PHY_REG_WRITE_DATA_F1 + +#define LPDDR4__DENALI_CTL_157_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_157_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_157__DFS_PHY_REG_WRITE_DATA_F2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_157__DFS_PHY_REG_WRITE_DATA_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_157__DFS_PHY_REG_WRITE_DATA_F2_WIDTH 32U +#define LPDDR4__DFS_PHY_REG_WRITE_DATA_F2__REG DENALI_CTL_157 +#define LPDDR4__DFS_PHY_REG_WRITE_DATA_F2__FLD LPDDR4__DENALI_CTL_157__DFS_PHY_REG_WRITE_DATA_F2 + +#define LPDDR4__DENALI_CTL_158_READ_MASK 0x00FFFF0FU +#define LPDDR4__DENALI_CTL_158_WRITE_MASK 0x00FFFF0FU +#define LPDDR4__DENALI_CTL_158__DFS_PHY_REG_WRITE_MASK_MASK 0x0000000FU +#define LPDDR4__DENALI_CTL_158__DFS_PHY_REG_WRITE_MASK_SHIFT 0U +#define LPDDR4__DENALI_CTL_158__DFS_PHY_REG_WRITE_MASK_WIDTH 4U +#define LPDDR4__DFS_PHY_REG_WRITE_MASK__REG DENALI_CTL_158 +#define LPDDR4__DFS_PHY_REG_WRITE_MASK__FLD LPDDR4__DENALI_CTL_158__DFS_PHY_REG_WRITE_MASK + +#define LPDDR4__DENALI_CTL_158__DFS_PHY_REG_WRITE_WAIT_MASK 0x00FFFF00U +#define LPDDR4__DENALI_CTL_158__DFS_PHY_REG_WRITE_WAIT_SHIFT 8U +#define LPDDR4__DENALI_CTL_158__DFS_PHY_REG_WRITE_WAIT_WIDTH 16U +#define LPDDR4__DFS_PHY_REG_WRITE_WAIT__REG DENALI_CTL_158 +#define LPDDR4__DFS_PHY_REG_WRITE_WAIT__FLD LPDDR4__DENALI_CTL_158__DFS_PHY_REG_WRITE_WAIT + +#define LPDDR4__DENALI_CTL_159_READ_MASK 0x07FFFFFFU +#define LPDDR4__DENALI_CTL_159_WRITE_MASK 0x07FFFFFFU +#define LPDDR4__DENALI_CTL_159__WRITE_MODEREG_MASK 0x07FFFFFFU +#define LPDDR4__DENALI_CTL_159__WRITE_MODEREG_SHIFT 0U +#define LPDDR4__DENALI_CTL_159__WRITE_MODEREG_WIDTH 27U +#define LPDDR4__WRITE_MODEREG__REG DENALI_CTL_159 +#define LPDDR4__WRITE_MODEREG__FLD LPDDR4__DENALI_CTL_159__WRITE_MODEREG + +#define LPDDR4__DENALI_CTL_160_READ_MASK 0x01FFFFFFU +#define LPDDR4__DENALI_CTL_160_WRITE_MASK 0x01FFFFFFU +#define LPDDR4__DENALI_CTL_160__MRW_STATUS_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_160__MRW_STATUS_SHIFT 0U +#define LPDDR4__DENALI_CTL_160__MRW_STATUS_WIDTH 8U +#define LPDDR4__MRW_STATUS__REG DENALI_CTL_160 +#define LPDDR4__MRW_STATUS__FLD LPDDR4__DENALI_CTL_160__MRW_STATUS + +#define LPDDR4__DENALI_CTL_160__READ_MODEREG_MASK 0x01FFFF00U +#define LPDDR4__DENALI_CTL_160__READ_MODEREG_SHIFT 8U +#define LPDDR4__DENALI_CTL_160__READ_MODEREG_WIDTH 17U +#define LPDDR4__READ_MODEREG__REG DENALI_CTL_160 +#define LPDDR4__READ_MODEREG__FLD LPDDR4__DENALI_CTL_160__READ_MODEREG + +#define LPDDR4__DENALI_CTL_161_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_161_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_161__PERIPHERAL_MRR_DATA_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_161__PERIPHERAL_MRR_DATA_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_161__PERIPHERAL_MRR_DATA_0_WIDTH 32U +#define LPDDR4__PERIPHERAL_MRR_DATA_0__REG DENALI_CTL_161 +#define LPDDR4__PERIPHERAL_MRR_DATA_0__FLD LPDDR4__DENALI_CTL_161__PERIPHERAL_MRR_DATA_0 + +#define LPDDR4__DENALI_CTL_162_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_162_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_162__PERIPHERAL_MRR_DATA_1_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_162__PERIPHERAL_MRR_DATA_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_162__PERIPHERAL_MRR_DATA_1_WIDTH 8U +#define LPDDR4__PERIPHERAL_MRR_DATA_1__REG DENALI_CTL_162 +#define LPDDR4__PERIPHERAL_MRR_DATA_1__FLD LPDDR4__DENALI_CTL_162__PERIPHERAL_MRR_DATA_1 + +#define LPDDR4__DENALI_CTL_162__AUTO_TEMPCHK_VAL_0_MASK 0x00FFFF00U +#define LPDDR4__DENALI_CTL_162__AUTO_TEMPCHK_VAL_0_SHIFT 8U +#define LPDDR4__DENALI_CTL_162__AUTO_TEMPCHK_VAL_0_WIDTH 16U +#define LPDDR4__AUTO_TEMPCHK_VAL_0__REG DENALI_CTL_162 +#define LPDDR4__AUTO_TEMPCHK_VAL_0__FLD LPDDR4__DENALI_CTL_162__AUTO_TEMPCHK_VAL_0 + +#define LPDDR4__DENALI_CTL_163_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_163_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_163__AUTO_TEMPCHK_VAL_1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_163__AUTO_TEMPCHK_VAL_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_163__AUTO_TEMPCHK_VAL_1_WIDTH 16U +#define LPDDR4__AUTO_TEMPCHK_VAL_1__REG DENALI_CTL_163 +#define LPDDR4__AUTO_TEMPCHK_VAL_1__FLD LPDDR4__DENALI_CTL_163__AUTO_TEMPCHK_VAL_1 + +#define LPDDR4__DENALI_CTL_163__DISABLE_UPDATE_TVRCG_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_163__DISABLE_UPDATE_TVRCG_SHIFT 16U +#define LPDDR4__DENALI_CTL_163__DISABLE_UPDATE_TVRCG_WIDTH 1U +#define LPDDR4__DENALI_CTL_163__DISABLE_UPDATE_TVRCG_WOCLR 0U +#define LPDDR4__DENALI_CTL_163__DISABLE_UPDATE_TVRCG_WOSET 0U +#define LPDDR4__DISABLE_UPDATE_TVRCG__REG DENALI_CTL_163 +#define LPDDR4__DISABLE_UPDATE_TVRCG__FLD LPDDR4__DENALI_CTL_163__DISABLE_UPDATE_TVRCG + +#define LPDDR4__DENALI_CTL_164_READ_MASK 0x03FF0003U +#define LPDDR4__DENALI_CTL_164_WRITE_MASK 0x03FF0003U +#define LPDDR4__DENALI_CTL_164__MRW_DFS_UPDATE_FRC_MASK 0x00000003U +#define LPDDR4__DENALI_CTL_164__MRW_DFS_UPDATE_FRC_SHIFT 0U +#define LPDDR4__DENALI_CTL_164__MRW_DFS_UPDATE_FRC_WIDTH 2U +#define LPDDR4__MRW_DFS_UPDATE_FRC__REG DENALI_CTL_164 +#define LPDDR4__MRW_DFS_UPDATE_FRC__FLD LPDDR4__DENALI_CTL_164__MRW_DFS_UPDATE_FRC + +#define LPDDR4__DENALI_CTL_164__TVRCG_ENABLE_F0_MASK 0x03FF0000U +#define LPDDR4__DENALI_CTL_164__TVRCG_ENABLE_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_164__TVRCG_ENABLE_F0_WIDTH 10U +#define LPDDR4__TVRCG_ENABLE_F0__REG DENALI_CTL_164 +#define LPDDR4__TVRCG_ENABLE_F0__FLD LPDDR4__DENALI_CTL_164__TVRCG_ENABLE_F0 + +#define LPDDR4__DENALI_CTL_165_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_CTL_165_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_CTL_165__TVRCG_DISABLE_F0_MASK 0x000003FFU +#define LPDDR4__DENALI_CTL_165__TVRCG_DISABLE_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_165__TVRCG_DISABLE_F0_WIDTH 10U +#define LPDDR4__TVRCG_DISABLE_F0__REG DENALI_CTL_165 +#define LPDDR4__TVRCG_DISABLE_F0__FLD LPDDR4__DENALI_CTL_165__TVRCG_DISABLE_F0 + +#define LPDDR4__DENALI_CTL_165__TFC_F0_MASK 0x03FF0000U +#define LPDDR4__DENALI_CTL_165__TFC_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_165__TFC_F0_WIDTH 10U +#define LPDDR4__TFC_F0__REG DENALI_CTL_165 +#define LPDDR4__TFC_F0__FLD LPDDR4__DENALI_CTL_165__TFC_F0 + +#define LPDDR4__DENALI_CTL_166_READ_MASK 0xFFFF1F1FU +#define LPDDR4__DENALI_CTL_166_WRITE_MASK 0xFFFF1F1FU +#define LPDDR4__DENALI_CTL_166__TCKFSPE_F0_MASK 0x0000001FU +#define LPDDR4__DENALI_CTL_166__TCKFSPE_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_166__TCKFSPE_F0_WIDTH 5U +#define LPDDR4__TCKFSPE_F0__REG DENALI_CTL_166 +#define LPDDR4__TCKFSPE_F0__FLD LPDDR4__DENALI_CTL_166__TCKFSPE_F0 + +#define LPDDR4__DENALI_CTL_166__TCKFSPX_F0_MASK 0x00001F00U +#define LPDDR4__DENALI_CTL_166__TCKFSPX_F0_SHIFT 8U +#define LPDDR4__DENALI_CTL_166__TCKFSPX_F0_WIDTH 5U +#define LPDDR4__TCKFSPX_F0__REG DENALI_CTL_166 +#define LPDDR4__TCKFSPX_F0__FLD LPDDR4__DENALI_CTL_166__TCKFSPX_F0 + +#define LPDDR4__DENALI_CTL_166__TVREF_LONG_F0_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_166__TVREF_LONG_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_166__TVREF_LONG_F0_WIDTH 16U +#define LPDDR4__TVREF_LONG_F0__REG DENALI_CTL_166 +#define LPDDR4__TVREF_LONG_F0__FLD LPDDR4__DENALI_CTL_166__TVREF_LONG_F0 + +#define LPDDR4__DENALI_CTL_167_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_CTL_167_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_CTL_167__TVRCG_ENABLE_F1_MASK 0x000003FFU +#define LPDDR4__DENALI_CTL_167__TVRCG_ENABLE_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_167__TVRCG_ENABLE_F1_WIDTH 10U +#define LPDDR4__TVRCG_ENABLE_F1__REG DENALI_CTL_167 +#define LPDDR4__TVRCG_ENABLE_F1__FLD LPDDR4__DENALI_CTL_167__TVRCG_ENABLE_F1 + +#define LPDDR4__DENALI_CTL_167__TVRCG_DISABLE_F1_MASK 0x03FF0000U +#define LPDDR4__DENALI_CTL_167__TVRCG_DISABLE_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_167__TVRCG_DISABLE_F1_WIDTH 10U +#define LPDDR4__TVRCG_DISABLE_F1__REG DENALI_CTL_167 +#define LPDDR4__TVRCG_DISABLE_F1__FLD LPDDR4__DENALI_CTL_167__TVRCG_DISABLE_F1 + +#define LPDDR4__DENALI_CTL_168_READ_MASK 0x1F1F03FFU +#define LPDDR4__DENALI_CTL_168_WRITE_MASK 0x1F1F03FFU +#define LPDDR4__DENALI_CTL_168__TFC_F1_MASK 0x000003FFU +#define LPDDR4__DENALI_CTL_168__TFC_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_168__TFC_F1_WIDTH 10U +#define LPDDR4__TFC_F1__REG DENALI_CTL_168 +#define LPDDR4__TFC_F1__FLD LPDDR4__DENALI_CTL_168__TFC_F1 + +#define LPDDR4__DENALI_CTL_168__TCKFSPE_F1_MASK 0x001F0000U +#define LPDDR4__DENALI_CTL_168__TCKFSPE_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_168__TCKFSPE_F1_WIDTH 5U +#define LPDDR4__TCKFSPE_F1__REG DENALI_CTL_168 +#define LPDDR4__TCKFSPE_F1__FLD LPDDR4__DENALI_CTL_168__TCKFSPE_F1 + +#define LPDDR4__DENALI_CTL_168__TCKFSPX_F1_MASK 0x1F000000U +#define LPDDR4__DENALI_CTL_168__TCKFSPX_F1_SHIFT 24U +#define LPDDR4__DENALI_CTL_168__TCKFSPX_F1_WIDTH 5U +#define LPDDR4__TCKFSPX_F1__REG DENALI_CTL_168 +#define LPDDR4__TCKFSPX_F1__FLD LPDDR4__DENALI_CTL_168__TCKFSPX_F1 + +#define LPDDR4__DENALI_CTL_169_READ_MASK 0x03FFFFFFU +#define LPDDR4__DENALI_CTL_169_WRITE_MASK 0x03FFFFFFU +#define LPDDR4__DENALI_CTL_169__TVREF_LONG_F1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_169__TVREF_LONG_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_169__TVREF_LONG_F1_WIDTH 16U +#define LPDDR4__TVREF_LONG_F1__REG DENALI_CTL_169 +#define LPDDR4__TVREF_LONG_F1__FLD LPDDR4__DENALI_CTL_169__TVREF_LONG_F1 + +#define LPDDR4__DENALI_CTL_169__TVRCG_ENABLE_F2_MASK 0x03FF0000U +#define LPDDR4__DENALI_CTL_169__TVRCG_ENABLE_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_169__TVRCG_ENABLE_F2_WIDTH 10U +#define LPDDR4__TVRCG_ENABLE_F2__REG DENALI_CTL_169 +#define LPDDR4__TVRCG_ENABLE_F2__FLD LPDDR4__DENALI_CTL_169__TVRCG_ENABLE_F2 + +#define LPDDR4__DENALI_CTL_170_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_CTL_170_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_CTL_170__TVRCG_DISABLE_F2_MASK 0x000003FFU +#define LPDDR4__DENALI_CTL_170__TVRCG_DISABLE_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_170__TVRCG_DISABLE_F2_WIDTH 10U +#define LPDDR4__TVRCG_DISABLE_F2__REG DENALI_CTL_170 +#define LPDDR4__TVRCG_DISABLE_F2__FLD LPDDR4__DENALI_CTL_170__TVRCG_DISABLE_F2 + +#define LPDDR4__DENALI_CTL_170__TFC_F2_MASK 0x03FF0000U +#define LPDDR4__DENALI_CTL_170__TFC_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_170__TFC_F2_WIDTH 10U +#define LPDDR4__TFC_F2__REG DENALI_CTL_170 +#define LPDDR4__TFC_F2__FLD LPDDR4__DENALI_CTL_170__TFC_F2 + +#define LPDDR4__DENALI_CTL_171_READ_MASK 0xFFFF1F1FU +#define LPDDR4__DENALI_CTL_171_WRITE_MASK 0xFFFF1F1FU +#define LPDDR4__DENALI_CTL_171__TCKFSPE_F2_MASK 0x0000001FU +#define LPDDR4__DENALI_CTL_171__TCKFSPE_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_171__TCKFSPE_F2_WIDTH 5U +#define LPDDR4__TCKFSPE_F2__REG DENALI_CTL_171 +#define LPDDR4__TCKFSPE_F2__FLD LPDDR4__DENALI_CTL_171__TCKFSPE_F2 + +#define LPDDR4__DENALI_CTL_171__TCKFSPX_F2_MASK 0x00001F00U +#define LPDDR4__DENALI_CTL_171__TCKFSPX_F2_SHIFT 8U +#define LPDDR4__DENALI_CTL_171__TCKFSPX_F2_WIDTH 5U +#define LPDDR4__TCKFSPX_F2__REG DENALI_CTL_171 +#define LPDDR4__TCKFSPX_F2__FLD LPDDR4__DENALI_CTL_171__TCKFSPX_F2 + +#define LPDDR4__DENALI_CTL_171__TVREF_LONG_F2_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_171__TVREF_LONG_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_171__TVREF_LONG_F2_WIDTH 16U +#define LPDDR4__TVREF_LONG_F2__REG DENALI_CTL_171 +#define LPDDR4__TVREF_LONG_F2__FLD LPDDR4__DENALI_CTL_171__TVREF_LONG_F2 + +#define LPDDR4__DENALI_CTL_172_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_172_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_172__MRR_PROMOTE_THRESHOLD_F0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_172__MRR_PROMOTE_THRESHOLD_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_172__MRR_PROMOTE_THRESHOLD_F0_WIDTH 16U +#define LPDDR4__MRR_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_172 +#define LPDDR4__MRR_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_172__MRR_PROMOTE_THRESHOLD_F0 + +#define LPDDR4__DENALI_CTL_172__MRR_PROMOTE_THRESHOLD_F1_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_172__MRR_PROMOTE_THRESHOLD_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_172__MRR_PROMOTE_THRESHOLD_F1_WIDTH 16U +#define LPDDR4__MRR_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_172 +#define LPDDR4__MRR_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_172__MRR_PROMOTE_THRESHOLD_F1 + +#define LPDDR4__DENALI_CTL_173_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_173_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_173__MRR_PROMOTE_THRESHOLD_F2_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_173__MRR_PROMOTE_THRESHOLD_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_173__MRR_PROMOTE_THRESHOLD_F2_WIDTH 16U +#define LPDDR4__MRR_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_173 +#define LPDDR4__MRR_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_173__MRR_PROMOTE_THRESHOLD_F2 + +#define LPDDR4__DENALI_CTL_173__MRW_PROMOTE_THRESHOLD_F0_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_173__MRW_PROMOTE_THRESHOLD_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_173__MRW_PROMOTE_THRESHOLD_F0_WIDTH 16U +#define LPDDR4__MRW_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_173 +#define LPDDR4__MRW_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_173__MRW_PROMOTE_THRESHOLD_F0 + +#define LPDDR4__DENALI_CTL_174_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_174_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_174__MRW_PROMOTE_THRESHOLD_F1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_174__MRW_PROMOTE_THRESHOLD_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_174__MRW_PROMOTE_THRESHOLD_F1_WIDTH 16U +#define LPDDR4__MRW_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_174 +#define LPDDR4__MRW_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_174__MRW_PROMOTE_THRESHOLD_F1 + +#define LPDDR4__DENALI_CTL_174__MRW_PROMOTE_THRESHOLD_F2_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_174__MRW_PROMOTE_THRESHOLD_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_174__MRW_PROMOTE_THRESHOLD_F2_WIDTH 16U +#define LPDDR4__MRW_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_174 +#define LPDDR4__MRW_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_174__MRW_PROMOTE_THRESHOLD_F2 + +#define LPDDR4__DENALI_CTL_175_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_175_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_175__MR1_DATA_F0_0_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_175__MR1_DATA_F0_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_175__MR1_DATA_F0_0_WIDTH 8U +#define LPDDR4__MR1_DATA_F0_0__REG DENALI_CTL_175 +#define LPDDR4__MR1_DATA_F0_0__FLD LPDDR4__DENALI_CTL_175__MR1_DATA_F0_0 + +#define LPDDR4__DENALI_CTL_175__MR2_DATA_F0_0_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_175__MR2_DATA_F0_0_SHIFT 8U +#define LPDDR4__DENALI_CTL_175__MR2_DATA_F0_0_WIDTH 8U +#define LPDDR4__MR2_DATA_F0_0__REG DENALI_CTL_175 +#define LPDDR4__MR2_DATA_F0_0__FLD LPDDR4__DENALI_CTL_175__MR2_DATA_F0_0 + +#define LPDDR4__DENALI_CTL_175__MR1_DATA_F1_0_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_175__MR1_DATA_F1_0_SHIFT 16U +#define LPDDR4__DENALI_CTL_175__MR1_DATA_F1_0_WIDTH 8U +#define LPDDR4__MR1_DATA_F1_0__REG DENALI_CTL_175 +#define LPDDR4__MR1_DATA_F1_0__FLD LPDDR4__DENALI_CTL_175__MR1_DATA_F1_0 + +#define LPDDR4__DENALI_CTL_175__MR2_DATA_F1_0_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_175__MR2_DATA_F1_0_SHIFT 24U +#define LPDDR4__DENALI_CTL_175__MR2_DATA_F1_0_WIDTH 8U +#define LPDDR4__MR2_DATA_F1_0__REG DENALI_CTL_175 +#define LPDDR4__MR2_DATA_F1_0__FLD LPDDR4__DENALI_CTL_175__MR2_DATA_F1_0 + +#define LPDDR4__DENALI_CTL_176_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_176_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_176__MR1_DATA_F2_0_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_176__MR1_DATA_F2_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_176__MR1_DATA_F2_0_WIDTH 8U +#define LPDDR4__MR1_DATA_F2_0__REG DENALI_CTL_176 +#define LPDDR4__MR1_DATA_F2_0__FLD LPDDR4__DENALI_CTL_176__MR1_DATA_F2_0 + +#define LPDDR4__DENALI_CTL_176__MR2_DATA_F2_0_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_176__MR2_DATA_F2_0_SHIFT 8U +#define LPDDR4__DENALI_CTL_176__MR2_DATA_F2_0_WIDTH 8U +#define LPDDR4__MR2_DATA_F2_0__REG DENALI_CTL_176 +#define LPDDR4__MR2_DATA_F2_0__FLD LPDDR4__DENALI_CTL_176__MR2_DATA_F2_0 + +#define LPDDR4__DENALI_CTL_176__MRSINGLE_DATA_0_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_176__MRSINGLE_DATA_0_SHIFT 16U +#define LPDDR4__DENALI_CTL_176__MRSINGLE_DATA_0_WIDTH 8U +#define LPDDR4__MRSINGLE_DATA_0__REG DENALI_CTL_176 +#define LPDDR4__MRSINGLE_DATA_0__FLD LPDDR4__DENALI_CTL_176__MRSINGLE_DATA_0 + +#define LPDDR4__DENALI_CTL_176__MR3_DATA_F0_0_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_176__MR3_DATA_F0_0_SHIFT 24U +#define LPDDR4__DENALI_CTL_176__MR3_DATA_F0_0_WIDTH 8U +#define LPDDR4__MR3_DATA_F0_0__REG DENALI_CTL_176 +#define LPDDR4__MR3_DATA_F0_0__FLD LPDDR4__DENALI_CTL_176__MR3_DATA_F0_0 + +#define LPDDR4__DENALI_CTL_177_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_177_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_177__MR3_DATA_F1_0_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_177__MR3_DATA_F1_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_177__MR3_DATA_F1_0_WIDTH 8U +#define LPDDR4__MR3_DATA_F1_0__REG DENALI_CTL_177 +#define LPDDR4__MR3_DATA_F1_0__FLD LPDDR4__DENALI_CTL_177__MR3_DATA_F1_0 + +#define LPDDR4__DENALI_CTL_177__MR3_DATA_F2_0_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_177__MR3_DATA_F2_0_SHIFT 8U +#define LPDDR4__DENALI_CTL_177__MR3_DATA_F2_0_WIDTH 8U +#define LPDDR4__MR3_DATA_F2_0__REG DENALI_CTL_177 +#define LPDDR4__MR3_DATA_F2_0__FLD LPDDR4__DENALI_CTL_177__MR3_DATA_F2_0 + +#define LPDDR4__DENALI_CTL_177__MR4_DATA_F0_0_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_177__MR4_DATA_F0_0_SHIFT 16U +#define LPDDR4__DENALI_CTL_177__MR4_DATA_F0_0_WIDTH 8U +#define LPDDR4__MR4_DATA_F0_0__REG DENALI_CTL_177 +#define LPDDR4__MR4_DATA_F0_0__FLD LPDDR4__DENALI_CTL_177__MR4_DATA_F0_0 + +#define LPDDR4__DENALI_CTL_177__MR4_DATA_F1_0_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_177__MR4_DATA_F1_0_SHIFT 24U +#define LPDDR4__DENALI_CTL_177__MR4_DATA_F1_0_WIDTH 8U +#define LPDDR4__MR4_DATA_F1_0__REG DENALI_CTL_177 +#define LPDDR4__MR4_DATA_F1_0__FLD LPDDR4__DENALI_CTL_177__MR4_DATA_F1_0 + +#define LPDDR4__DENALI_CTL_178_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_178_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_178__MR4_DATA_F2_0_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_178__MR4_DATA_F2_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_178__MR4_DATA_F2_0_WIDTH 8U +#define LPDDR4__MR4_DATA_F2_0__REG DENALI_CTL_178 +#define LPDDR4__MR4_DATA_F2_0__FLD LPDDR4__DENALI_CTL_178__MR4_DATA_F2_0 + +#define LPDDR4__DENALI_CTL_178__MR8_DATA_0_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_178__MR8_DATA_0_SHIFT 8U +#define LPDDR4__DENALI_CTL_178__MR8_DATA_0_WIDTH 8U +#define LPDDR4__MR8_DATA_0__REG DENALI_CTL_178 +#define LPDDR4__MR8_DATA_0__FLD LPDDR4__DENALI_CTL_178__MR8_DATA_0 + +#define LPDDR4__DENALI_CTL_178__MR11_DATA_F0_0_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_178__MR11_DATA_F0_0_SHIFT 16U +#define LPDDR4__DENALI_CTL_178__MR11_DATA_F0_0_WIDTH 8U +#define LPDDR4__MR11_DATA_F0_0__REG DENALI_CTL_178 +#define LPDDR4__MR11_DATA_F0_0__FLD LPDDR4__DENALI_CTL_178__MR11_DATA_F0_0 + +#define LPDDR4__DENALI_CTL_178__MR11_DATA_F1_0_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_178__MR11_DATA_F1_0_SHIFT 24U +#define LPDDR4__DENALI_CTL_178__MR11_DATA_F1_0_WIDTH 8U +#define LPDDR4__MR11_DATA_F1_0__REG DENALI_CTL_178 +#define LPDDR4__MR11_DATA_F1_0__FLD LPDDR4__DENALI_CTL_178__MR11_DATA_F1_0 + +#define LPDDR4__DENALI_CTL_179_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_179_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_179__MR11_DATA_F2_0_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_179__MR11_DATA_F2_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_179__MR11_DATA_F2_0_WIDTH 8U +#define LPDDR4__MR11_DATA_F2_0__REG DENALI_CTL_179 +#define LPDDR4__MR11_DATA_F2_0__FLD LPDDR4__DENALI_CTL_179__MR11_DATA_F2_0 + +#define LPDDR4__DENALI_CTL_179__MR12_DATA_F0_0_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_179__MR12_DATA_F0_0_SHIFT 8U +#define LPDDR4__DENALI_CTL_179__MR12_DATA_F0_0_WIDTH 8U +#define LPDDR4__MR12_DATA_F0_0__REG DENALI_CTL_179 +#define LPDDR4__MR12_DATA_F0_0__FLD LPDDR4__DENALI_CTL_179__MR12_DATA_F0_0 + +#define LPDDR4__DENALI_CTL_179__MR12_DATA_F1_0_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_179__MR12_DATA_F1_0_SHIFT 16U +#define LPDDR4__DENALI_CTL_179__MR12_DATA_F1_0_WIDTH 8U +#define LPDDR4__MR12_DATA_F1_0__REG DENALI_CTL_179 +#define LPDDR4__MR12_DATA_F1_0__FLD LPDDR4__DENALI_CTL_179__MR12_DATA_F1_0 + +#define LPDDR4__DENALI_CTL_179__MR12_DATA_F2_0_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_179__MR12_DATA_F2_0_SHIFT 24U +#define LPDDR4__DENALI_CTL_179__MR12_DATA_F2_0_WIDTH 8U +#define LPDDR4__MR12_DATA_F2_0__REG DENALI_CTL_179 +#define LPDDR4__MR12_DATA_F2_0__FLD LPDDR4__DENALI_CTL_179__MR12_DATA_F2_0 + +#define LPDDR4__DENALI_CTL_180_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_180_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_180__MR13_DATA_0_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_180__MR13_DATA_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_180__MR13_DATA_0_WIDTH 8U +#define LPDDR4__MR13_DATA_0__REG DENALI_CTL_180 +#define LPDDR4__MR13_DATA_0__FLD LPDDR4__DENALI_CTL_180__MR13_DATA_0 + +#define LPDDR4__DENALI_CTL_180__MR14_DATA_F0_0_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_180__MR14_DATA_F0_0_SHIFT 8U +#define LPDDR4__DENALI_CTL_180__MR14_DATA_F0_0_WIDTH 8U +#define LPDDR4__MR14_DATA_F0_0__REG DENALI_CTL_180 +#define LPDDR4__MR14_DATA_F0_0__FLD LPDDR4__DENALI_CTL_180__MR14_DATA_F0_0 + +#define LPDDR4__DENALI_CTL_180__MR14_DATA_F1_0_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_180__MR14_DATA_F1_0_SHIFT 16U +#define LPDDR4__DENALI_CTL_180__MR14_DATA_F1_0_WIDTH 8U +#define LPDDR4__MR14_DATA_F1_0__REG DENALI_CTL_180 +#define LPDDR4__MR14_DATA_F1_0__FLD LPDDR4__DENALI_CTL_180__MR14_DATA_F1_0 + +#define LPDDR4__DENALI_CTL_180__MR14_DATA_F2_0_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_180__MR14_DATA_F2_0_SHIFT 24U +#define LPDDR4__DENALI_CTL_180__MR14_DATA_F2_0_WIDTH 8U +#define LPDDR4__MR14_DATA_F2_0__REG DENALI_CTL_180 +#define LPDDR4__MR14_DATA_F2_0__FLD LPDDR4__DENALI_CTL_180__MR14_DATA_F2_0 + +#define LPDDR4__DENALI_CTL_181_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_181_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_181__MR16_DATA_0_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_181__MR16_DATA_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_181__MR16_DATA_0_WIDTH 8U +#define LPDDR4__MR16_DATA_0__REG DENALI_CTL_181 +#define LPDDR4__MR16_DATA_0__FLD LPDDR4__DENALI_CTL_181__MR16_DATA_0 + +#define LPDDR4__DENALI_CTL_181__MR17_DATA_0_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_181__MR17_DATA_0_SHIFT 8U +#define LPDDR4__DENALI_CTL_181__MR17_DATA_0_WIDTH 8U +#define LPDDR4__MR17_DATA_0__REG DENALI_CTL_181 +#define LPDDR4__MR17_DATA_0__FLD LPDDR4__DENALI_CTL_181__MR17_DATA_0 + +#define LPDDR4__DENALI_CTL_181__MR20_DATA_0_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_181__MR20_DATA_0_SHIFT 16U +#define LPDDR4__DENALI_CTL_181__MR20_DATA_0_WIDTH 8U +#define LPDDR4__MR20_DATA_0__REG DENALI_CTL_181 +#define LPDDR4__MR20_DATA_0__FLD LPDDR4__DENALI_CTL_181__MR20_DATA_0 + +#define LPDDR4__DENALI_CTL_181__MR22_DATA_F0_0_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_181__MR22_DATA_F0_0_SHIFT 24U +#define LPDDR4__DENALI_CTL_181__MR22_DATA_F0_0_WIDTH 8U +#define LPDDR4__MR22_DATA_F0_0__REG DENALI_CTL_181 +#define LPDDR4__MR22_DATA_F0_0__FLD LPDDR4__DENALI_CTL_181__MR22_DATA_F0_0 + +#define LPDDR4__DENALI_CTL_182_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_182_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_182__MR22_DATA_F1_0_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_182__MR22_DATA_F1_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_182__MR22_DATA_F1_0_WIDTH 8U +#define LPDDR4__MR22_DATA_F1_0__REG DENALI_CTL_182 +#define LPDDR4__MR22_DATA_F1_0__FLD LPDDR4__DENALI_CTL_182__MR22_DATA_F1_0 + +#define LPDDR4__DENALI_CTL_182__MR22_DATA_F2_0_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_182__MR22_DATA_F2_0_SHIFT 8U +#define LPDDR4__DENALI_CTL_182__MR22_DATA_F2_0_WIDTH 8U +#define LPDDR4__MR22_DATA_F2_0__REG DENALI_CTL_182 +#define LPDDR4__MR22_DATA_F2_0__FLD LPDDR4__DENALI_CTL_182__MR22_DATA_F2_0 + +#define LPDDR4__DENALI_CTL_182__MR1_DATA_F0_1_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_182__MR1_DATA_F0_1_SHIFT 16U +#define LPDDR4__DENALI_CTL_182__MR1_DATA_F0_1_WIDTH 8U +#define LPDDR4__MR1_DATA_F0_1__REG DENALI_CTL_182 +#define LPDDR4__MR1_DATA_F0_1__FLD LPDDR4__DENALI_CTL_182__MR1_DATA_F0_1 + +#define LPDDR4__DENALI_CTL_182__MR2_DATA_F0_1_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_182__MR2_DATA_F0_1_SHIFT 24U +#define LPDDR4__DENALI_CTL_182__MR2_DATA_F0_1_WIDTH 8U +#define LPDDR4__MR2_DATA_F0_1__REG DENALI_CTL_182 +#define LPDDR4__MR2_DATA_F0_1__FLD LPDDR4__DENALI_CTL_182__MR2_DATA_F0_1 + +#define LPDDR4__DENALI_CTL_183_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_183_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_183__MR1_DATA_F1_1_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_183__MR1_DATA_F1_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_183__MR1_DATA_F1_1_WIDTH 8U +#define LPDDR4__MR1_DATA_F1_1__REG DENALI_CTL_183 +#define LPDDR4__MR1_DATA_F1_1__FLD LPDDR4__DENALI_CTL_183__MR1_DATA_F1_1 + +#define LPDDR4__DENALI_CTL_183__MR2_DATA_F1_1_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_183__MR2_DATA_F1_1_SHIFT 8U +#define LPDDR4__DENALI_CTL_183__MR2_DATA_F1_1_WIDTH 8U +#define LPDDR4__MR2_DATA_F1_1__REG DENALI_CTL_183 +#define LPDDR4__MR2_DATA_F1_1__FLD LPDDR4__DENALI_CTL_183__MR2_DATA_F1_1 + +#define LPDDR4__DENALI_CTL_183__MR1_DATA_F2_1_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_183__MR1_DATA_F2_1_SHIFT 16U +#define LPDDR4__DENALI_CTL_183__MR1_DATA_F2_1_WIDTH 8U +#define LPDDR4__MR1_DATA_F2_1__REG DENALI_CTL_183 +#define LPDDR4__MR1_DATA_F2_1__FLD LPDDR4__DENALI_CTL_183__MR1_DATA_F2_1 + +#define LPDDR4__DENALI_CTL_183__MR2_DATA_F2_1_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_183__MR2_DATA_F2_1_SHIFT 24U +#define LPDDR4__DENALI_CTL_183__MR2_DATA_F2_1_WIDTH 8U +#define LPDDR4__MR2_DATA_F2_1__REG DENALI_CTL_183 +#define LPDDR4__MR2_DATA_F2_1__FLD LPDDR4__DENALI_CTL_183__MR2_DATA_F2_1 + +#define LPDDR4__DENALI_CTL_184_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_184_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_184__MRSINGLE_DATA_1_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_184__MRSINGLE_DATA_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_184__MRSINGLE_DATA_1_WIDTH 8U +#define LPDDR4__MRSINGLE_DATA_1__REG DENALI_CTL_184 +#define LPDDR4__MRSINGLE_DATA_1__FLD LPDDR4__DENALI_CTL_184__MRSINGLE_DATA_1 + +#define LPDDR4__DENALI_CTL_184__MR3_DATA_F0_1_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_184__MR3_DATA_F0_1_SHIFT 8U +#define LPDDR4__DENALI_CTL_184__MR3_DATA_F0_1_WIDTH 8U +#define LPDDR4__MR3_DATA_F0_1__REG DENALI_CTL_184 +#define LPDDR4__MR3_DATA_F0_1__FLD LPDDR4__DENALI_CTL_184__MR3_DATA_F0_1 + +#define LPDDR4__DENALI_CTL_184__MR3_DATA_F1_1_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_184__MR3_DATA_F1_1_SHIFT 16U +#define LPDDR4__DENALI_CTL_184__MR3_DATA_F1_1_WIDTH 8U +#define LPDDR4__MR3_DATA_F1_1__REG DENALI_CTL_184 +#define LPDDR4__MR3_DATA_F1_1__FLD LPDDR4__DENALI_CTL_184__MR3_DATA_F1_1 + +#define LPDDR4__DENALI_CTL_184__MR3_DATA_F2_1_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_184__MR3_DATA_F2_1_SHIFT 24U +#define LPDDR4__DENALI_CTL_184__MR3_DATA_F2_1_WIDTH 8U +#define LPDDR4__MR3_DATA_F2_1__REG DENALI_CTL_184 +#define LPDDR4__MR3_DATA_F2_1__FLD LPDDR4__DENALI_CTL_184__MR3_DATA_F2_1 + +#define LPDDR4__DENALI_CTL_185_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_185_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_185__MR4_DATA_F0_1_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_185__MR4_DATA_F0_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_185__MR4_DATA_F0_1_WIDTH 8U +#define LPDDR4__MR4_DATA_F0_1__REG DENALI_CTL_185 +#define LPDDR4__MR4_DATA_F0_1__FLD LPDDR4__DENALI_CTL_185__MR4_DATA_F0_1 + +#define LPDDR4__DENALI_CTL_185__MR4_DATA_F1_1_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_185__MR4_DATA_F1_1_SHIFT 8U +#define LPDDR4__DENALI_CTL_185__MR4_DATA_F1_1_WIDTH 8U +#define LPDDR4__MR4_DATA_F1_1__REG DENALI_CTL_185 +#define LPDDR4__MR4_DATA_F1_1__FLD LPDDR4__DENALI_CTL_185__MR4_DATA_F1_1 + +#define LPDDR4__DENALI_CTL_185__MR4_DATA_F2_1_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_185__MR4_DATA_F2_1_SHIFT 16U +#define LPDDR4__DENALI_CTL_185__MR4_DATA_F2_1_WIDTH 8U +#define LPDDR4__MR4_DATA_F2_1__REG DENALI_CTL_185 +#define LPDDR4__MR4_DATA_F2_1__FLD LPDDR4__DENALI_CTL_185__MR4_DATA_F2_1 + +#define LPDDR4__DENALI_CTL_185__MR8_DATA_1_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_185__MR8_DATA_1_SHIFT 24U +#define LPDDR4__DENALI_CTL_185__MR8_DATA_1_WIDTH 8U +#define LPDDR4__MR8_DATA_1__REG DENALI_CTL_185 +#define LPDDR4__MR8_DATA_1__FLD LPDDR4__DENALI_CTL_185__MR8_DATA_1 + +#define LPDDR4__DENALI_CTL_186_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_186_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_186__MR11_DATA_F0_1_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_186__MR11_DATA_F0_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_186__MR11_DATA_F0_1_WIDTH 8U +#define LPDDR4__MR11_DATA_F0_1__REG DENALI_CTL_186 +#define LPDDR4__MR11_DATA_F0_1__FLD LPDDR4__DENALI_CTL_186__MR11_DATA_F0_1 + +#define LPDDR4__DENALI_CTL_186__MR11_DATA_F1_1_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_186__MR11_DATA_F1_1_SHIFT 8U +#define LPDDR4__DENALI_CTL_186__MR11_DATA_F1_1_WIDTH 8U +#define LPDDR4__MR11_DATA_F1_1__REG DENALI_CTL_186 +#define LPDDR4__MR11_DATA_F1_1__FLD LPDDR4__DENALI_CTL_186__MR11_DATA_F1_1 + +#define LPDDR4__DENALI_CTL_186__MR11_DATA_F2_1_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_186__MR11_DATA_F2_1_SHIFT 16U +#define LPDDR4__DENALI_CTL_186__MR11_DATA_F2_1_WIDTH 8U +#define LPDDR4__MR11_DATA_F2_1__REG DENALI_CTL_186 +#define LPDDR4__MR11_DATA_F2_1__FLD LPDDR4__DENALI_CTL_186__MR11_DATA_F2_1 + +#define LPDDR4__DENALI_CTL_186__MR12_DATA_F0_1_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_186__MR12_DATA_F0_1_SHIFT 24U +#define LPDDR4__DENALI_CTL_186__MR12_DATA_F0_1_WIDTH 8U +#define LPDDR4__MR12_DATA_F0_1__REG DENALI_CTL_186 +#define LPDDR4__MR12_DATA_F0_1__FLD LPDDR4__DENALI_CTL_186__MR12_DATA_F0_1 + +#define LPDDR4__DENALI_CTL_187_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_187_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_187__MR12_DATA_F1_1_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_187__MR12_DATA_F1_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_187__MR12_DATA_F1_1_WIDTH 8U +#define LPDDR4__MR12_DATA_F1_1__REG DENALI_CTL_187 +#define LPDDR4__MR12_DATA_F1_1__FLD LPDDR4__DENALI_CTL_187__MR12_DATA_F1_1 + +#define LPDDR4__DENALI_CTL_187__MR12_DATA_F2_1_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_187__MR12_DATA_F2_1_SHIFT 8U +#define LPDDR4__DENALI_CTL_187__MR12_DATA_F2_1_WIDTH 8U +#define LPDDR4__MR12_DATA_F2_1__REG DENALI_CTL_187 +#define LPDDR4__MR12_DATA_F2_1__FLD LPDDR4__DENALI_CTL_187__MR12_DATA_F2_1 + +#define LPDDR4__DENALI_CTL_187__MR13_DATA_1_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_187__MR13_DATA_1_SHIFT 16U +#define LPDDR4__DENALI_CTL_187__MR13_DATA_1_WIDTH 8U +#define LPDDR4__MR13_DATA_1__REG DENALI_CTL_187 +#define LPDDR4__MR13_DATA_1__FLD LPDDR4__DENALI_CTL_187__MR13_DATA_1 + +#define LPDDR4__DENALI_CTL_187__MR14_DATA_F0_1_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_187__MR14_DATA_F0_1_SHIFT 24U +#define LPDDR4__DENALI_CTL_187__MR14_DATA_F0_1_WIDTH 8U +#define LPDDR4__MR14_DATA_F0_1__REG DENALI_CTL_187 +#define LPDDR4__MR14_DATA_F0_1__FLD LPDDR4__DENALI_CTL_187__MR14_DATA_F0_1 + +#define LPDDR4__DENALI_CTL_188_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_188_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_188__MR14_DATA_F1_1_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_188__MR14_DATA_F1_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_188__MR14_DATA_F1_1_WIDTH 8U +#define LPDDR4__MR14_DATA_F1_1__REG DENALI_CTL_188 +#define LPDDR4__MR14_DATA_F1_1__FLD LPDDR4__DENALI_CTL_188__MR14_DATA_F1_1 + +#define LPDDR4__DENALI_CTL_188__MR14_DATA_F2_1_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_188__MR14_DATA_F2_1_SHIFT 8U +#define LPDDR4__DENALI_CTL_188__MR14_DATA_F2_1_WIDTH 8U +#define LPDDR4__MR14_DATA_F2_1__REG DENALI_CTL_188 +#define LPDDR4__MR14_DATA_F2_1__FLD LPDDR4__DENALI_CTL_188__MR14_DATA_F2_1 + +#define LPDDR4__DENALI_CTL_188__MR16_DATA_1_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_188__MR16_DATA_1_SHIFT 16U +#define LPDDR4__DENALI_CTL_188__MR16_DATA_1_WIDTH 8U +#define LPDDR4__MR16_DATA_1__REG DENALI_CTL_188 +#define LPDDR4__MR16_DATA_1__FLD LPDDR4__DENALI_CTL_188__MR16_DATA_1 + +#define LPDDR4__DENALI_CTL_188__MR17_DATA_1_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_188__MR17_DATA_1_SHIFT 24U +#define LPDDR4__DENALI_CTL_188__MR17_DATA_1_WIDTH 8U +#define LPDDR4__MR17_DATA_1__REG DENALI_CTL_188 +#define LPDDR4__MR17_DATA_1__FLD LPDDR4__DENALI_CTL_188__MR17_DATA_1 + +#define LPDDR4__DENALI_CTL_189_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_189_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_189__MR20_DATA_1_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_189__MR20_DATA_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_189__MR20_DATA_1_WIDTH 8U +#define LPDDR4__MR20_DATA_1__REG DENALI_CTL_189 +#define LPDDR4__MR20_DATA_1__FLD LPDDR4__DENALI_CTL_189__MR20_DATA_1 + +#define LPDDR4__DENALI_CTL_189__MR22_DATA_F0_1_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_189__MR22_DATA_F0_1_SHIFT 8U +#define LPDDR4__DENALI_CTL_189__MR22_DATA_F0_1_WIDTH 8U +#define LPDDR4__MR22_DATA_F0_1__REG DENALI_CTL_189 +#define LPDDR4__MR22_DATA_F0_1__FLD LPDDR4__DENALI_CTL_189__MR22_DATA_F0_1 + +#define LPDDR4__DENALI_CTL_189__MR22_DATA_F1_1_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_189__MR22_DATA_F1_1_SHIFT 16U +#define LPDDR4__DENALI_CTL_189__MR22_DATA_F1_1_WIDTH 8U +#define LPDDR4__MR22_DATA_F1_1__REG DENALI_CTL_189 +#define LPDDR4__MR22_DATA_F1_1__FLD LPDDR4__DENALI_CTL_189__MR22_DATA_F1_1 + +#define LPDDR4__DENALI_CTL_189__MR22_DATA_F2_1_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_189__MR22_DATA_F2_1_SHIFT 24U +#define LPDDR4__DENALI_CTL_189__MR22_DATA_F2_1_WIDTH 8U +#define LPDDR4__MR22_DATA_F2_1__REG DENALI_CTL_189 +#define LPDDR4__MR22_DATA_F2_1__FLD LPDDR4__DENALI_CTL_189__MR22_DATA_F2_1 + +#define LPDDR4__DENALI_CTL_190_READ_MASK 0x010101FFU +#define LPDDR4__DENALI_CTL_190_WRITE_MASK 0x010101FFU +#define LPDDR4__DENALI_CTL_190__MR23_DATA_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_190__MR23_DATA_SHIFT 0U +#define LPDDR4__DENALI_CTL_190__MR23_DATA_WIDTH 8U +#define LPDDR4__MR23_DATA__REG DENALI_CTL_190 +#define LPDDR4__MR23_DATA__FLD LPDDR4__DENALI_CTL_190__MR23_DATA + +#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F0_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F0_SHIFT 8U +#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F0_WIDTH 1U +#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F0_WOCLR 0U +#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F0_WOSET 0U +#define LPDDR4__MR_FSP_DATA_VALID_F0__REG DENALI_CTL_190 +#define LPDDR4__MR_FSP_DATA_VALID_F0__FLD LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F0 + +#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F1_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F1_WIDTH 1U +#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F1_WOCLR 0U +#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F1_WOSET 0U +#define LPDDR4__MR_FSP_DATA_VALID_F1__REG DENALI_CTL_190 +#define LPDDR4__MR_FSP_DATA_VALID_F1__FLD LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F1 + +#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F2_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F2_SHIFT 24U +#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F2_WIDTH 1U +#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F2_WOCLR 0U +#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F2_WOSET 0U +#define LPDDR4__MR_FSP_DATA_VALID_F2__REG DENALI_CTL_190 +#define LPDDR4__MR_FSP_DATA_VALID_F2__FLD LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F2 + +#define LPDDR4__DENALI_CTL_191_READ_MASK 0x01010103U +#define LPDDR4__DENALI_CTL_191_WRITE_MASK 0x01010103U +#define LPDDR4__DENALI_CTL_191__RL3_SUPPORT_EN_MASK 0x00000003U +#define LPDDR4__DENALI_CTL_191__RL3_SUPPORT_EN_SHIFT 0U +#define LPDDR4__DENALI_CTL_191__RL3_SUPPORT_EN_WIDTH 2U +#define LPDDR4__RL3_SUPPORT_EN__REG DENALI_CTL_191 +#define LPDDR4__RL3_SUPPORT_EN__FLD LPDDR4__DENALI_CTL_191__RL3_SUPPORT_EN + +#define LPDDR4__DENALI_CTL_191__MC_RESERVED19_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_191__MC_RESERVED19_SHIFT 8U +#define LPDDR4__DENALI_CTL_191__MC_RESERVED19_WIDTH 1U +#define LPDDR4__DENALI_CTL_191__MC_RESERVED19_WOCLR 0U +#define LPDDR4__DENALI_CTL_191__MC_RESERVED19_WOSET 0U +#define LPDDR4__MC_RESERVED19__REG DENALI_CTL_191 +#define LPDDR4__MC_RESERVED19__FLD LPDDR4__DENALI_CTL_191__MC_RESERVED19 + +#define LPDDR4__DENALI_CTL_191__MC_RESERVED20_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_191__MC_RESERVED20_SHIFT 16U +#define LPDDR4__DENALI_CTL_191__MC_RESERVED20_WIDTH 1U +#define LPDDR4__DENALI_CTL_191__MC_RESERVED20_WOCLR 0U +#define LPDDR4__DENALI_CTL_191__MC_RESERVED20_WOSET 0U +#define LPDDR4__MC_RESERVED20__REG DENALI_CTL_191 +#define LPDDR4__MC_RESERVED20__FLD LPDDR4__DENALI_CTL_191__MC_RESERVED20 + +#define LPDDR4__DENALI_CTL_191__FSP_PHY_UPDATE_MRW_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_191__FSP_PHY_UPDATE_MRW_SHIFT 24U +#define LPDDR4__DENALI_CTL_191__FSP_PHY_UPDATE_MRW_WIDTH 1U +#define LPDDR4__DENALI_CTL_191__FSP_PHY_UPDATE_MRW_WOCLR 0U +#define LPDDR4__DENALI_CTL_191__FSP_PHY_UPDATE_MRW_WOSET 0U +#define LPDDR4__FSP_PHY_UPDATE_MRW__REG DENALI_CTL_191 +#define LPDDR4__FSP_PHY_UPDATE_MRW__FLD LPDDR4__DENALI_CTL_191__FSP_PHY_UPDATE_MRW + +#define LPDDR4__DENALI_CTL_192_READ_MASK 0x01010101U +#define LPDDR4__DENALI_CTL_192_WRITE_MASK 0x01010101U +#define LPDDR4__DENALI_CTL_192__DFS_ALWAYS_WRITE_FSP_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_192__DFS_ALWAYS_WRITE_FSP_SHIFT 0U +#define LPDDR4__DENALI_CTL_192__DFS_ALWAYS_WRITE_FSP_WIDTH 1U +#define LPDDR4__DENALI_CTL_192__DFS_ALWAYS_WRITE_FSP_WOCLR 0U +#define LPDDR4__DENALI_CTL_192__DFS_ALWAYS_WRITE_FSP_WOSET 0U +#define LPDDR4__DFS_ALWAYS_WRITE_FSP__REG DENALI_CTL_192 +#define LPDDR4__DFS_ALWAYS_WRITE_FSP__FLD LPDDR4__DENALI_CTL_192__DFS_ALWAYS_WRITE_FSP + +#define LPDDR4__DENALI_CTL_192__FSP_STATUS_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_192__FSP_STATUS_SHIFT 8U +#define LPDDR4__DENALI_CTL_192__FSP_STATUS_WIDTH 1U +#define LPDDR4__DENALI_CTL_192__FSP_STATUS_WOCLR 0U +#define LPDDR4__DENALI_CTL_192__FSP_STATUS_WOSET 0U +#define LPDDR4__FSP_STATUS__REG DENALI_CTL_192 +#define LPDDR4__FSP_STATUS__FLD LPDDR4__DENALI_CTL_192__FSP_STATUS + +#define LPDDR4__DENALI_CTL_192__FSP_OP_CURRENT_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_192__FSP_OP_CURRENT_SHIFT 16U +#define LPDDR4__DENALI_CTL_192__FSP_OP_CURRENT_WIDTH 1U +#define LPDDR4__DENALI_CTL_192__FSP_OP_CURRENT_WOCLR 0U +#define LPDDR4__DENALI_CTL_192__FSP_OP_CURRENT_WOSET 0U +#define LPDDR4__FSP_OP_CURRENT__REG DENALI_CTL_192 +#define LPDDR4__FSP_OP_CURRENT__FLD LPDDR4__DENALI_CTL_192__FSP_OP_CURRENT + +#define LPDDR4__DENALI_CTL_192__FSP_WR_CURRENT_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_192__FSP_WR_CURRENT_SHIFT 24U +#define LPDDR4__DENALI_CTL_192__FSP_WR_CURRENT_WIDTH 1U +#define LPDDR4__DENALI_CTL_192__FSP_WR_CURRENT_WOCLR 0U +#define LPDDR4__DENALI_CTL_192__FSP_WR_CURRENT_WOSET 0U +#define LPDDR4__FSP_WR_CURRENT__REG DENALI_CTL_192 +#define LPDDR4__FSP_WR_CURRENT__FLD LPDDR4__DENALI_CTL_192__FSP_WR_CURRENT + +#define LPDDR4__DENALI_CTL_193_READ_MASK 0x03030101U +#define LPDDR4__DENALI_CTL_193_WRITE_MASK 0x03030101U +#define LPDDR4__DENALI_CTL_193__FSP0_FRC_VALID_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_193__FSP0_FRC_VALID_SHIFT 0U +#define LPDDR4__DENALI_CTL_193__FSP0_FRC_VALID_WIDTH 1U +#define LPDDR4__DENALI_CTL_193__FSP0_FRC_VALID_WOCLR 0U +#define LPDDR4__DENALI_CTL_193__FSP0_FRC_VALID_WOSET 0U +#define LPDDR4__FSP0_FRC_VALID__REG DENALI_CTL_193 +#define LPDDR4__FSP0_FRC_VALID__FLD LPDDR4__DENALI_CTL_193__FSP0_FRC_VALID + +#define LPDDR4__DENALI_CTL_193__FSP1_FRC_VALID_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_193__FSP1_FRC_VALID_SHIFT 8U +#define LPDDR4__DENALI_CTL_193__FSP1_FRC_VALID_WIDTH 1U +#define LPDDR4__DENALI_CTL_193__FSP1_FRC_VALID_WOCLR 0U +#define LPDDR4__DENALI_CTL_193__FSP1_FRC_VALID_WOSET 0U +#define LPDDR4__FSP1_FRC_VALID__REG DENALI_CTL_193 +#define LPDDR4__FSP1_FRC_VALID__FLD LPDDR4__DENALI_CTL_193__FSP1_FRC_VALID + +#define LPDDR4__DENALI_CTL_193__FSP0_FRC_MASK 0x00030000U +#define LPDDR4__DENALI_CTL_193__FSP0_FRC_SHIFT 16U +#define LPDDR4__DENALI_CTL_193__FSP0_FRC_WIDTH 2U +#define LPDDR4__FSP0_FRC__REG DENALI_CTL_193 +#define LPDDR4__FSP0_FRC__FLD LPDDR4__DENALI_CTL_193__FSP0_FRC + +#define LPDDR4__DENALI_CTL_193__FSP1_FRC_MASK 0x03000000U +#define LPDDR4__DENALI_CTL_193__FSP1_FRC_SHIFT 24U +#define LPDDR4__DENALI_CTL_193__FSP1_FRC_WIDTH 2U +#define LPDDR4__FSP1_FRC__REG DENALI_CTL_193 +#define LPDDR4__FSP1_FRC__FLD LPDDR4__DENALI_CTL_193__FSP1_FRC + +#define LPDDR4__DENALI_CTL_194_READ_MASK 0x013F0300U +#define LPDDR4__DENALI_CTL_194_WRITE_MASK 0x013F0300U +#define LPDDR4__DENALI_CTL_194__BIST_GO_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_194__BIST_GO_SHIFT 0U +#define LPDDR4__DENALI_CTL_194__BIST_GO_WIDTH 1U +#define LPDDR4__DENALI_CTL_194__BIST_GO_WOCLR 0U +#define LPDDR4__DENALI_CTL_194__BIST_GO_WOSET 0U +#define LPDDR4__BIST_GO__REG DENALI_CTL_194 +#define LPDDR4__BIST_GO__FLD LPDDR4__DENALI_CTL_194__BIST_GO + +#define LPDDR4__DENALI_CTL_194__BIST_RESULT_MASK 0x00000300U +#define LPDDR4__DENALI_CTL_194__BIST_RESULT_SHIFT 8U +#define LPDDR4__DENALI_CTL_194__BIST_RESULT_WIDTH 2U +#define LPDDR4__BIST_RESULT__REG DENALI_CTL_194 +#define LPDDR4__BIST_RESULT__FLD LPDDR4__DENALI_CTL_194__BIST_RESULT + +#define LPDDR4__DENALI_CTL_194__ADDR_SPACE_MASK 0x003F0000U +#define LPDDR4__DENALI_CTL_194__ADDR_SPACE_SHIFT 16U +#define LPDDR4__DENALI_CTL_194__ADDR_SPACE_WIDTH 6U +#define LPDDR4__ADDR_SPACE__REG DENALI_CTL_194 +#define LPDDR4__ADDR_SPACE__FLD LPDDR4__DENALI_CTL_194__ADDR_SPACE + +#define LPDDR4__DENALI_CTL_194__BIST_DATA_CHECK_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_194__BIST_DATA_CHECK_SHIFT 24U +#define LPDDR4__DENALI_CTL_194__BIST_DATA_CHECK_WIDTH 1U +#define LPDDR4__DENALI_CTL_194__BIST_DATA_CHECK_WOCLR 0U +#define LPDDR4__DENALI_CTL_194__BIST_DATA_CHECK_WOSET 0U +#define LPDDR4__BIST_DATA_CHECK__REG DENALI_CTL_194 +#define LPDDR4__BIST_DATA_CHECK__FLD LPDDR4__DENALI_CTL_194__BIST_DATA_CHECK + +#define LPDDR4__DENALI_CTL_195_READ_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_195_WRITE_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_195__BIST_ADDR_CHECK_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_195__BIST_ADDR_CHECK_SHIFT 0U +#define LPDDR4__DENALI_CTL_195__BIST_ADDR_CHECK_WIDTH 1U +#define LPDDR4__DENALI_CTL_195__BIST_ADDR_CHECK_WOCLR 0U +#define LPDDR4__DENALI_CTL_195__BIST_ADDR_CHECK_WOSET 0U +#define LPDDR4__BIST_ADDR_CHECK__REG DENALI_CTL_195 +#define LPDDR4__BIST_ADDR_CHECK__FLD LPDDR4__DENALI_CTL_195__BIST_ADDR_CHECK + +#define LPDDR4__DENALI_CTL_196_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_196_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_196__BIST_START_ADDRESS_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_196__BIST_START_ADDRESS_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_196__BIST_START_ADDRESS_0_WIDTH 32U +#define LPDDR4__BIST_START_ADDRESS_0__REG DENALI_CTL_196 +#define LPDDR4__BIST_START_ADDRESS_0__FLD LPDDR4__DENALI_CTL_196__BIST_START_ADDRESS_0 + +#define LPDDR4__DENALI_CTL_197_READ_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_197_WRITE_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_197__BIST_START_ADDRESS_1_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_197__BIST_START_ADDRESS_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_197__BIST_START_ADDRESS_1_WIDTH 3U +#define LPDDR4__BIST_START_ADDRESS_1__REG DENALI_CTL_197 +#define LPDDR4__BIST_START_ADDRESS_1__FLD LPDDR4__DENALI_CTL_197__BIST_START_ADDRESS_1 + +#define LPDDR4__DENALI_CTL_198_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_198_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_198__BIST_DATA_MASK_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_198__BIST_DATA_MASK_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_198__BIST_DATA_MASK_0_WIDTH 32U +#define LPDDR4__BIST_DATA_MASK_0__REG DENALI_CTL_198 +#define LPDDR4__BIST_DATA_MASK_0__FLD LPDDR4__DENALI_CTL_198__BIST_DATA_MASK_0 + +#define LPDDR4__DENALI_CTL_199_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_199_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_199__BIST_DATA_MASK_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_199__BIST_DATA_MASK_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_199__BIST_DATA_MASK_1_WIDTH 32U +#define LPDDR4__BIST_DATA_MASK_1__REG DENALI_CTL_199 +#define LPDDR4__BIST_DATA_MASK_1__FLD LPDDR4__DENALI_CTL_199__BIST_DATA_MASK_1 + +#define LPDDR4__DENALI_CTL_200_READ_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_200_WRITE_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_200__BIST_TEST_MODE_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_200__BIST_TEST_MODE_SHIFT 0U +#define LPDDR4__DENALI_CTL_200__BIST_TEST_MODE_WIDTH 3U +#define LPDDR4__BIST_TEST_MODE__REG DENALI_CTL_200 +#define LPDDR4__BIST_TEST_MODE__FLD LPDDR4__DENALI_CTL_200__BIST_TEST_MODE + +#define LPDDR4__DENALI_CTL_201_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_201_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_201__BIST_DATA_PATTERN_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_201__BIST_DATA_PATTERN_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_201__BIST_DATA_PATTERN_0_WIDTH 32U +#define LPDDR4__BIST_DATA_PATTERN_0__REG DENALI_CTL_201 +#define LPDDR4__BIST_DATA_PATTERN_0__FLD LPDDR4__DENALI_CTL_201__BIST_DATA_PATTERN_0 + +#define LPDDR4__DENALI_CTL_202_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_202_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_202__BIST_DATA_PATTERN_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_202__BIST_DATA_PATTERN_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_202__BIST_DATA_PATTERN_1_WIDTH 32U +#define LPDDR4__BIST_DATA_PATTERN_1__REG DENALI_CTL_202 +#define LPDDR4__BIST_DATA_PATTERN_1__FLD LPDDR4__DENALI_CTL_202__BIST_DATA_PATTERN_1 + +#define LPDDR4__DENALI_CTL_203_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_203_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_203__BIST_DATA_PATTERN_2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_203__BIST_DATA_PATTERN_2_SHIFT 0U +#define LPDDR4__DENALI_CTL_203__BIST_DATA_PATTERN_2_WIDTH 32U +#define LPDDR4__BIST_DATA_PATTERN_2__REG DENALI_CTL_203 +#define LPDDR4__BIST_DATA_PATTERN_2__FLD LPDDR4__DENALI_CTL_203__BIST_DATA_PATTERN_2 + +#define LPDDR4__DENALI_CTL_204_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_204_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_204__BIST_DATA_PATTERN_3_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_204__BIST_DATA_PATTERN_3_SHIFT 0U +#define LPDDR4__DENALI_CTL_204__BIST_DATA_PATTERN_3_WIDTH 32U +#define LPDDR4__BIST_DATA_PATTERN_3__REG DENALI_CTL_204 +#define LPDDR4__BIST_DATA_PATTERN_3__FLD LPDDR4__DENALI_CTL_204__BIST_DATA_PATTERN_3 + +#define LPDDR4__DENALI_CTL_205_READ_MASK 0x0FFF0100U +#define LPDDR4__DENALI_CTL_205_WRITE_MASK 0x0FFF0100U +#define LPDDR4__DENALI_CTL_205__BIST_RET_STATE_EXIT_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_205__BIST_RET_STATE_EXIT_SHIFT 0U +#define LPDDR4__DENALI_CTL_205__BIST_RET_STATE_EXIT_WIDTH 1U +#define LPDDR4__DENALI_CTL_205__BIST_RET_STATE_EXIT_WOCLR 0U +#define LPDDR4__DENALI_CTL_205__BIST_RET_STATE_EXIT_WOSET 0U +#define LPDDR4__BIST_RET_STATE_EXIT__REG DENALI_CTL_205 +#define LPDDR4__BIST_RET_STATE_EXIT__FLD LPDDR4__DENALI_CTL_205__BIST_RET_STATE_EXIT + +#define LPDDR4__DENALI_CTL_205__BIST_RET_STATE_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_205__BIST_RET_STATE_SHIFT 8U +#define LPDDR4__DENALI_CTL_205__BIST_RET_STATE_WIDTH 1U +#define LPDDR4__DENALI_CTL_205__BIST_RET_STATE_WOCLR 0U +#define LPDDR4__DENALI_CTL_205__BIST_RET_STATE_WOSET 0U +#define LPDDR4__BIST_RET_STATE__REG DENALI_CTL_205 +#define LPDDR4__BIST_RET_STATE__FLD LPDDR4__DENALI_CTL_205__BIST_RET_STATE + +#define LPDDR4__DENALI_CTL_205__BIST_ERR_STOP_MASK 0x0FFF0000U +#define LPDDR4__DENALI_CTL_205__BIST_ERR_STOP_SHIFT 16U +#define LPDDR4__DENALI_CTL_205__BIST_ERR_STOP_WIDTH 12U +#define LPDDR4__BIST_ERR_STOP__REG DENALI_CTL_205 +#define LPDDR4__BIST_ERR_STOP__FLD LPDDR4__DENALI_CTL_205__BIST_ERR_STOP + +#define LPDDR4__DENALI_CTL_206_READ_MASK 0x07030FFFU +#define LPDDR4__DENALI_CTL_206_WRITE_MASK 0x07030FFFU +#define LPDDR4__DENALI_CTL_206__BIST_ERR_COUNT_MASK 0x00000FFFU +#define LPDDR4__DENALI_CTL_206__BIST_ERR_COUNT_SHIFT 0U +#define LPDDR4__DENALI_CTL_206__BIST_ERR_COUNT_WIDTH 12U +#define LPDDR4__BIST_ERR_COUNT__REG DENALI_CTL_206 +#define LPDDR4__BIST_ERR_COUNT__FLD LPDDR4__DENALI_CTL_206__BIST_ERR_COUNT + +#define LPDDR4__DENALI_CTL_206__ECC_ENABLE_MASK 0x00030000U +#define LPDDR4__DENALI_CTL_206__ECC_ENABLE_SHIFT 16U +#define LPDDR4__DENALI_CTL_206__ECC_ENABLE_WIDTH 2U +#define LPDDR4__ECC_ENABLE__REG DENALI_CTL_206 +#define LPDDR4__ECC_ENABLE__FLD LPDDR4__DENALI_CTL_206__ECC_ENABLE + +#define LPDDR4__DENALI_CTL_206__INLINE_ECC_BANK_OFFSET_MASK 0x07000000U +#define LPDDR4__DENALI_CTL_206__INLINE_ECC_BANK_OFFSET_SHIFT 24U +#define LPDDR4__DENALI_CTL_206__INLINE_ECC_BANK_OFFSET_WIDTH 3U +#define LPDDR4__INLINE_ECC_BANK_OFFSET__REG DENALI_CTL_206 +#define LPDDR4__INLINE_ECC_BANK_OFFSET__FLD LPDDR4__DENALI_CTL_206__INLINE_ECC_BANK_OFFSET + +#define LPDDR4__DENALI_CTL_207_READ_MASK 0x010F0101U +#define LPDDR4__DENALI_CTL_207_WRITE_MASK 0x010F0101U +#define LPDDR4__DENALI_CTL_207__ECC_READ_CACHING_EN_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_207__ECC_READ_CACHING_EN_SHIFT 0U +#define LPDDR4__DENALI_CTL_207__ECC_READ_CACHING_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_207__ECC_READ_CACHING_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_207__ECC_READ_CACHING_EN_WOSET 0U +#define LPDDR4__ECC_READ_CACHING_EN__REG DENALI_CTL_207 +#define LPDDR4__ECC_READ_CACHING_EN__FLD LPDDR4__DENALI_CTL_207__ECC_READ_CACHING_EN + +#define LPDDR4__DENALI_CTL_207__ECC_WRITE_COMBINING_EN_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_207__ECC_WRITE_COMBINING_EN_SHIFT 8U +#define LPDDR4__DENALI_CTL_207__ECC_WRITE_COMBINING_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_207__ECC_WRITE_COMBINING_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_207__ECC_WRITE_COMBINING_EN_WOSET 0U +#define LPDDR4__ECC_WRITE_COMBINING_EN__REG DENALI_CTL_207 +#define LPDDR4__ECC_WRITE_COMBINING_EN__FLD LPDDR4__DENALI_CTL_207__ECC_WRITE_COMBINING_EN + +#define LPDDR4__DENALI_CTL_207__MC_RESERVED21_MASK 0x000F0000U +#define LPDDR4__DENALI_CTL_207__MC_RESERVED21_SHIFT 16U +#define LPDDR4__DENALI_CTL_207__MC_RESERVED21_WIDTH 4U +#define LPDDR4__MC_RESERVED21__REG DENALI_CTL_207 +#define LPDDR4__MC_RESERVED21__FLD LPDDR4__DENALI_CTL_207__MC_RESERVED21 + +#define LPDDR4__DENALI_CTL_207__MC_RESERVED22_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_207__MC_RESERVED22_SHIFT 24U +#define LPDDR4__DENALI_CTL_207__MC_RESERVED22_WIDTH 1U +#define LPDDR4__DENALI_CTL_207__MC_RESERVED22_WOCLR 0U +#define LPDDR4__DENALI_CTL_207__MC_RESERVED22_WOSET 0U +#define LPDDR4__MC_RESERVED22__REG DENALI_CTL_207 +#define LPDDR4__MC_RESERVED22__FLD LPDDR4__DENALI_CTL_207__MC_RESERVED22 + +#define LPDDR4__DENALI_CTL_208_READ_MASK 0x01FFFF01U +#define LPDDR4__DENALI_CTL_208_WRITE_MASK 0x01FFFF01U +#define LPDDR4__DENALI_CTL_208__FWC_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_208__FWC_SHIFT 0U +#define LPDDR4__DENALI_CTL_208__FWC_WIDTH 1U +#define LPDDR4__DENALI_CTL_208__FWC_WOCLR 0U +#define LPDDR4__DENALI_CTL_208__FWC_WOSET 0U +#define LPDDR4__FWC__REG DENALI_CTL_208 +#define LPDDR4__FWC__FLD LPDDR4__DENALI_CTL_208__FWC + +#define LPDDR4__DENALI_CTL_208__XOR_CHECK_BITS_MASK 0x00FFFF00U +#define LPDDR4__DENALI_CTL_208__XOR_CHECK_BITS_SHIFT 8U +#define LPDDR4__DENALI_CTL_208__XOR_CHECK_BITS_WIDTH 16U +#define LPDDR4__XOR_CHECK_BITS__REG DENALI_CTL_208 +#define LPDDR4__XOR_CHECK_BITS__FLD LPDDR4__DENALI_CTL_208__XOR_CHECK_BITS + +#define LPDDR4__DENALI_CTL_208__ECC_WRITEBACK_EN_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_208__ECC_WRITEBACK_EN_SHIFT 24U +#define LPDDR4__DENALI_CTL_208__ECC_WRITEBACK_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_208__ECC_WRITEBACK_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_208__ECC_WRITEBACK_EN_WOSET 0U +#define LPDDR4__ECC_WRITEBACK_EN__REG DENALI_CTL_208 +#define LPDDR4__ECC_WRITEBACK_EN__FLD LPDDR4__DENALI_CTL_208__ECC_WRITEBACK_EN + +#define LPDDR4__DENALI_CTL_209_READ_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_209_WRITE_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_209__ECC_DISABLE_W_UC_ERR_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_209__ECC_DISABLE_W_UC_ERR_SHIFT 0U +#define LPDDR4__DENALI_CTL_209__ECC_DISABLE_W_UC_ERR_WIDTH 1U +#define LPDDR4__DENALI_CTL_209__ECC_DISABLE_W_UC_ERR_WOCLR 0U +#define LPDDR4__DENALI_CTL_209__ECC_DISABLE_W_UC_ERR_WOSET 0U +#define LPDDR4__ECC_DISABLE_W_UC_ERR__REG DENALI_CTL_209 +#define LPDDR4__ECC_DISABLE_W_UC_ERR__FLD LPDDR4__DENALI_CTL_209__ECC_DISABLE_W_UC_ERR + +#define LPDDR4__DENALI_CTL_210_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_210_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_210__ECC_U_ADDR_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_210__ECC_U_ADDR_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_210__ECC_U_ADDR_0_WIDTH 32U +#define LPDDR4__ECC_U_ADDR_0__REG DENALI_CTL_210 +#define LPDDR4__ECC_U_ADDR_0__FLD LPDDR4__DENALI_CTL_210__ECC_U_ADDR_0 + +#define LPDDR4__DENALI_CTL_211_READ_MASK 0x0000FF07U +#define LPDDR4__DENALI_CTL_211_WRITE_MASK 0x0000FF07U +#define LPDDR4__DENALI_CTL_211__ECC_U_ADDR_1_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_211__ECC_U_ADDR_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_211__ECC_U_ADDR_1_WIDTH 3U +#define LPDDR4__ECC_U_ADDR_1__REG DENALI_CTL_211 +#define LPDDR4__ECC_U_ADDR_1__FLD LPDDR4__DENALI_CTL_211__ECC_U_ADDR_1 + +#define LPDDR4__DENALI_CTL_211__ECC_U_SYND_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_211__ECC_U_SYND_SHIFT 8U +#define LPDDR4__DENALI_CTL_211__ECC_U_SYND_WIDTH 8U +#define LPDDR4__ECC_U_SYND__REG DENALI_CTL_211 +#define LPDDR4__ECC_U_SYND__FLD LPDDR4__DENALI_CTL_211__ECC_U_SYND + +#define LPDDR4__DENALI_CTL_212_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_212_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_212__ECC_U_DATA_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_212__ECC_U_DATA_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_212__ECC_U_DATA_0_WIDTH 32U +#define LPDDR4__ECC_U_DATA_0__REG DENALI_CTL_212 +#define LPDDR4__ECC_U_DATA_0__FLD LPDDR4__DENALI_CTL_212__ECC_U_DATA_0 + +#define LPDDR4__DENALI_CTL_213_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_213_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_213__ECC_U_DATA_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_213__ECC_U_DATA_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_213__ECC_U_DATA_1_WIDTH 32U +#define LPDDR4__ECC_U_DATA_1__REG DENALI_CTL_213 +#define LPDDR4__ECC_U_DATA_1__FLD LPDDR4__DENALI_CTL_213__ECC_U_DATA_1 + +#define LPDDR4__DENALI_CTL_214_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_214_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_214__ECC_C_ADDR_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_214__ECC_C_ADDR_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_214__ECC_C_ADDR_0_WIDTH 32U +#define LPDDR4__ECC_C_ADDR_0__REG DENALI_CTL_214 +#define LPDDR4__ECC_C_ADDR_0__FLD LPDDR4__DENALI_CTL_214__ECC_C_ADDR_0 + +#define LPDDR4__DENALI_CTL_215_READ_MASK 0x0000FF07U +#define LPDDR4__DENALI_CTL_215_WRITE_MASK 0x0000FF07U +#define LPDDR4__DENALI_CTL_215__ECC_C_ADDR_1_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_215__ECC_C_ADDR_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_215__ECC_C_ADDR_1_WIDTH 3U +#define LPDDR4__ECC_C_ADDR_1__REG DENALI_CTL_215 +#define LPDDR4__ECC_C_ADDR_1__FLD LPDDR4__DENALI_CTL_215__ECC_C_ADDR_1 + +#define LPDDR4__DENALI_CTL_215__ECC_C_SYND_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_215__ECC_C_SYND_SHIFT 8U +#define LPDDR4__DENALI_CTL_215__ECC_C_SYND_WIDTH 8U +#define LPDDR4__ECC_C_SYND__REG DENALI_CTL_215 +#define LPDDR4__ECC_C_SYND__FLD LPDDR4__DENALI_CTL_215__ECC_C_SYND + +#define LPDDR4__DENALI_CTL_216_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_216_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_216__ECC_C_DATA_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_216__ECC_C_DATA_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_216__ECC_C_DATA_0_WIDTH 32U +#define LPDDR4__ECC_C_DATA_0__REG DENALI_CTL_216 +#define LPDDR4__ECC_C_DATA_0__FLD LPDDR4__DENALI_CTL_216__ECC_C_DATA_0 + +#define LPDDR4__DENALI_CTL_217_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_217_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_217__ECC_C_DATA_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_217__ECC_C_DATA_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_217__ECC_C_DATA_1_WIDTH 32U +#define LPDDR4__ECC_C_DATA_1__REG DENALI_CTL_217 +#define LPDDR4__ECC_C_DATA_1__FLD LPDDR4__DENALI_CTL_217__ECC_C_DATA_1 + +#define LPDDR4__DENALI_CTL_218_READ_MASK 0x7FFF3F3FU +#define LPDDR4__DENALI_CTL_218_WRITE_MASK 0x7FFF3F3FU +#define LPDDR4__DENALI_CTL_218__ECC_U_ID_MASK 0x0000003FU +#define LPDDR4__DENALI_CTL_218__ECC_U_ID_SHIFT 0U +#define LPDDR4__DENALI_CTL_218__ECC_U_ID_WIDTH 6U +#define LPDDR4__ECC_U_ID__REG DENALI_CTL_218 +#define LPDDR4__ECC_U_ID__FLD LPDDR4__DENALI_CTL_218__ECC_U_ID + +#define LPDDR4__DENALI_CTL_218__ECC_C_ID_MASK 0x00003F00U +#define LPDDR4__DENALI_CTL_218__ECC_C_ID_SHIFT 8U +#define LPDDR4__DENALI_CTL_218__ECC_C_ID_WIDTH 6U +#define LPDDR4__ECC_C_ID__REG DENALI_CTL_218 +#define LPDDR4__ECC_C_ID__FLD LPDDR4__DENALI_CTL_218__ECC_C_ID + +#define LPDDR4__DENALI_CTL_218__NON_ECC_REGION_START_ADDR_0_MASK 0x7FFF0000U +#define LPDDR4__DENALI_CTL_218__NON_ECC_REGION_START_ADDR_0_SHIFT 16U +#define LPDDR4__DENALI_CTL_218__NON_ECC_REGION_START_ADDR_0_WIDTH 15U +#define LPDDR4__NON_ECC_REGION_START_ADDR_0__REG DENALI_CTL_218 +#define LPDDR4__NON_ECC_REGION_START_ADDR_0__FLD LPDDR4__DENALI_CTL_218__NON_ECC_REGION_START_ADDR_0 + +#define LPDDR4__DENALI_CTL_219_READ_MASK 0x7FFF7FFFU +#define LPDDR4__DENALI_CTL_219_WRITE_MASK 0x7FFF7FFFU +#define LPDDR4__DENALI_CTL_219__NON_ECC_REGION_END_ADDR_0_MASK 0x00007FFFU +#define LPDDR4__DENALI_CTL_219__NON_ECC_REGION_END_ADDR_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_219__NON_ECC_REGION_END_ADDR_0_WIDTH 15U +#define LPDDR4__NON_ECC_REGION_END_ADDR_0__REG DENALI_CTL_219 +#define LPDDR4__NON_ECC_REGION_END_ADDR_0__FLD LPDDR4__DENALI_CTL_219__NON_ECC_REGION_END_ADDR_0 + +#define LPDDR4__DENALI_CTL_219__NON_ECC_REGION_START_ADDR_1_MASK 0x7FFF0000U +#define LPDDR4__DENALI_CTL_219__NON_ECC_REGION_START_ADDR_1_SHIFT 16U +#define LPDDR4__DENALI_CTL_219__NON_ECC_REGION_START_ADDR_1_WIDTH 15U +#define LPDDR4__NON_ECC_REGION_START_ADDR_1__REG DENALI_CTL_219 +#define LPDDR4__NON_ECC_REGION_START_ADDR_1__FLD LPDDR4__DENALI_CTL_219__NON_ECC_REGION_START_ADDR_1 + +#define LPDDR4__DENALI_CTL_220_READ_MASK 0x7FFF7FFFU +#define LPDDR4__DENALI_CTL_220_WRITE_MASK 0x7FFF7FFFU +#define LPDDR4__DENALI_CTL_220__NON_ECC_REGION_END_ADDR_1_MASK 0x00007FFFU +#define LPDDR4__DENALI_CTL_220__NON_ECC_REGION_END_ADDR_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_220__NON_ECC_REGION_END_ADDR_1_WIDTH 15U +#define LPDDR4__NON_ECC_REGION_END_ADDR_1__REG DENALI_CTL_220 +#define LPDDR4__NON_ECC_REGION_END_ADDR_1__FLD LPDDR4__DENALI_CTL_220__NON_ECC_REGION_END_ADDR_1 + +#define LPDDR4__DENALI_CTL_220__NON_ECC_REGION_START_ADDR_2_MASK 0x7FFF0000U +#define LPDDR4__DENALI_CTL_220__NON_ECC_REGION_START_ADDR_2_SHIFT 16U +#define LPDDR4__DENALI_CTL_220__NON_ECC_REGION_START_ADDR_2_WIDTH 15U +#define LPDDR4__NON_ECC_REGION_START_ADDR_2__REG DENALI_CTL_220 +#define LPDDR4__NON_ECC_REGION_START_ADDR_2__FLD LPDDR4__DENALI_CTL_220__NON_ECC_REGION_START_ADDR_2 + +#define LPDDR4__DENALI_CTL_221_READ_MASK 0x00077FFFU +#define LPDDR4__DENALI_CTL_221_WRITE_MASK 0x00077FFFU +#define LPDDR4__DENALI_CTL_221__NON_ECC_REGION_END_ADDR_2_MASK 0x00007FFFU +#define LPDDR4__DENALI_CTL_221__NON_ECC_REGION_END_ADDR_2_SHIFT 0U +#define LPDDR4__DENALI_CTL_221__NON_ECC_REGION_END_ADDR_2_WIDTH 15U +#define LPDDR4__NON_ECC_REGION_END_ADDR_2__REG DENALI_CTL_221 +#define LPDDR4__NON_ECC_REGION_END_ADDR_2__FLD LPDDR4__DENALI_CTL_221__NON_ECC_REGION_END_ADDR_2 + +#define LPDDR4__DENALI_CTL_221__NON_ECC_REGION_ENABLE_MASK 0x00070000U +#define LPDDR4__DENALI_CTL_221__NON_ECC_REGION_ENABLE_SHIFT 16U +#define LPDDR4__DENALI_CTL_221__NON_ECC_REGION_ENABLE_WIDTH 3U +#define LPDDR4__NON_ECC_REGION_ENABLE__REG DENALI_CTL_221 +#define LPDDR4__NON_ECC_REGION_ENABLE__FLD LPDDR4__DENALI_CTL_221__NON_ECC_REGION_ENABLE + +#define LPDDR4__DENALI_CTL_221__ECC_SCRUB_START_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_221__ECC_SCRUB_START_SHIFT 24U +#define LPDDR4__DENALI_CTL_221__ECC_SCRUB_START_WIDTH 1U +#define LPDDR4__DENALI_CTL_221__ECC_SCRUB_START_WOCLR 0U +#define LPDDR4__DENALI_CTL_221__ECC_SCRUB_START_WOSET 0U +#define LPDDR4__ECC_SCRUB_START__REG DENALI_CTL_221 +#define LPDDR4__ECC_SCRUB_START__FLD LPDDR4__DENALI_CTL_221__ECC_SCRUB_START + +#define LPDDR4__DENALI_CTL_222_READ_MASK 0x010FFF01U +#define LPDDR4__DENALI_CTL_222_WRITE_MASK 0x010FFF01U +#define LPDDR4__DENALI_CTL_222__ECC_SCRUB_IN_PROGRESS_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_222__ECC_SCRUB_IN_PROGRESS_SHIFT 0U +#define LPDDR4__DENALI_CTL_222__ECC_SCRUB_IN_PROGRESS_WIDTH 1U +#define LPDDR4__DENALI_CTL_222__ECC_SCRUB_IN_PROGRESS_WOCLR 0U +#define LPDDR4__DENALI_CTL_222__ECC_SCRUB_IN_PROGRESS_WOSET 0U +#define LPDDR4__ECC_SCRUB_IN_PROGRESS__REG DENALI_CTL_222 +#define LPDDR4__ECC_SCRUB_IN_PROGRESS__FLD LPDDR4__DENALI_CTL_222__ECC_SCRUB_IN_PROGRESS + +#define LPDDR4__DENALI_CTL_222__ECC_SCRUB_LEN_MASK 0x000FFF00U +#define LPDDR4__DENALI_CTL_222__ECC_SCRUB_LEN_SHIFT 8U +#define LPDDR4__DENALI_CTL_222__ECC_SCRUB_LEN_WIDTH 12U +#define LPDDR4__ECC_SCRUB_LEN__REG DENALI_CTL_222 +#define LPDDR4__ECC_SCRUB_LEN__FLD LPDDR4__DENALI_CTL_222__ECC_SCRUB_LEN + +#define LPDDR4__DENALI_CTL_222__ECC_SCRUB_MODE_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_222__ECC_SCRUB_MODE_SHIFT 24U +#define LPDDR4__DENALI_CTL_222__ECC_SCRUB_MODE_WIDTH 1U +#define LPDDR4__DENALI_CTL_222__ECC_SCRUB_MODE_WOCLR 0U +#define LPDDR4__DENALI_CTL_222__ECC_SCRUB_MODE_WOSET 0U +#define LPDDR4__ECC_SCRUB_MODE__REG DENALI_CTL_222 +#define LPDDR4__ECC_SCRUB_MODE__FLD LPDDR4__DENALI_CTL_222__ECC_SCRUB_MODE + +#define LPDDR4__DENALI_CTL_223_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_223_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_223__ECC_SCRUB_INTERVAL_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_223__ECC_SCRUB_INTERVAL_SHIFT 0U +#define LPDDR4__DENALI_CTL_223__ECC_SCRUB_INTERVAL_WIDTH 16U +#define LPDDR4__ECC_SCRUB_INTERVAL__REG DENALI_CTL_223 +#define LPDDR4__ECC_SCRUB_INTERVAL__FLD LPDDR4__DENALI_CTL_223__ECC_SCRUB_INTERVAL + +#define LPDDR4__DENALI_CTL_223__ECC_SCRUB_IDLE_CNT_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_223__ECC_SCRUB_IDLE_CNT_SHIFT 16U +#define LPDDR4__DENALI_CTL_223__ECC_SCRUB_IDLE_CNT_WIDTH 16U +#define LPDDR4__ECC_SCRUB_IDLE_CNT__REG DENALI_CTL_223 +#define LPDDR4__ECC_SCRUB_IDLE_CNT__FLD LPDDR4__DENALI_CTL_223__ECC_SCRUB_IDLE_CNT + +#define LPDDR4__DENALI_CTL_224_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_224_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_224__ECC_SCRUB_START_ADDR_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_224__ECC_SCRUB_START_ADDR_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_224__ECC_SCRUB_START_ADDR_0_WIDTH 32U +#define LPDDR4__ECC_SCRUB_START_ADDR_0__REG DENALI_CTL_224 +#define LPDDR4__ECC_SCRUB_START_ADDR_0__FLD LPDDR4__DENALI_CTL_224__ECC_SCRUB_START_ADDR_0 + +#define LPDDR4__DENALI_CTL_225_READ_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_225_WRITE_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_225__ECC_SCRUB_START_ADDR_1_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_225__ECC_SCRUB_START_ADDR_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_225__ECC_SCRUB_START_ADDR_1_WIDTH 3U +#define LPDDR4__ECC_SCRUB_START_ADDR_1__REG DENALI_CTL_225 +#define LPDDR4__ECC_SCRUB_START_ADDR_1__FLD LPDDR4__DENALI_CTL_225__ECC_SCRUB_START_ADDR_1 + +#define LPDDR4__DENALI_CTL_226_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_226_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_226__ECC_SCRUB_END_ADDR_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_226__ECC_SCRUB_END_ADDR_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_226__ECC_SCRUB_END_ADDR_0_WIDTH 32U +#define LPDDR4__ECC_SCRUB_END_ADDR_0__REG DENALI_CTL_226 +#define LPDDR4__ECC_SCRUB_END_ADDR_0__FLD LPDDR4__DENALI_CTL_226__ECC_SCRUB_END_ADDR_0 + +#define LPDDR4__DENALI_CTL_227_READ_MASK 0x1F1F1F07U +#define LPDDR4__DENALI_CTL_227_WRITE_MASK 0x1F1F1F07U +#define LPDDR4__DENALI_CTL_227__ECC_SCRUB_END_ADDR_1_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_227__ECC_SCRUB_END_ADDR_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_227__ECC_SCRUB_END_ADDR_1_WIDTH 3U +#define LPDDR4__ECC_SCRUB_END_ADDR_1__REG DENALI_CTL_227 +#define LPDDR4__ECC_SCRUB_END_ADDR_1__FLD LPDDR4__DENALI_CTL_227__ECC_SCRUB_END_ADDR_1 + +#define LPDDR4__DENALI_CTL_227__LONG_COUNT_MASK_MASK 0x00001F00U +#define LPDDR4__DENALI_CTL_227__LONG_COUNT_MASK_SHIFT 8U +#define LPDDR4__DENALI_CTL_227__LONG_COUNT_MASK_WIDTH 5U +#define LPDDR4__LONG_COUNT_MASK__REG DENALI_CTL_227 +#define LPDDR4__LONG_COUNT_MASK__FLD LPDDR4__DENALI_CTL_227__LONG_COUNT_MASK + +#define LPDDR4__DENALI_CTL_227__AREF_NORM_THRESHOLD_MASK 0x001F0000U +#define LPDDR4__DENALI_CTL_227__AREF_NORM_THRESHOLD_SHIFT 16U +#define LPDDR4__DENALI_CTL_227__AREF_NORM_THRESHOLD_WIDTH 5U +#define LPDDR4__AREF_NORM_THRESHOLD__REG DENALI_CTL_227 +#define LPDDR4__AREF_NORM_THRESHOLD__FLD LPDDR4__DENALI_CTL_227__AREF_NORM_THRESHOLD + +#define LPDDR4__DENALI_CTL_227__AREF_HIGH_THRESHOLD_MASK 0x1F000000U +#define LPDDR4__DENALI_CTL_227__AREF_HIGH_THRESHOLD_SHIFT 24U +#define LPDDR4__DENALI_CTL_227__AREF_HIGH_THRESHOLD_WIDTH 5U +#define LPDDR4__AREF_HIGH_THRESHOLD__REG DENALI_CTL_227 +#define LPDDR4__AREF_HIGH_THRESHOLD__FLD LPDDR4__DENALI_CTL_227__AREF_HIGH_THRESHOLD + +#define LPDDR4__DENALI_CTL_228_READ_MASK 0x000F1F1FU +#define LPDDR4__DENALI_CTL_228_WRITE_MASK 0x000F1F1FU +#define LPDDR4__DENALI_CTL_228__AREF_MAX_DEFICIT_MASK 0x0000001FU +#define LPDDR4__DENALI_CTL_228__AREF_MAX_DEFICIT_SHIFT 0U +#define LPDDR4__DENALI_CTL_228__AREF_MAX_DEFICIT_WIDTH 5U +#define LPDDR4__AREF_MAX_DEFICIT__REG DENALI_CTL_228 +#define LPDDR4__AREF_MAX_DEFICIT__FLD LPDDR4__DENALI_CTL_228__AREF_MAX_DEFICIT + +#define LPDDR4__DENALI_CTL_228__AREF_MAX_CREDIT_MASK 0x00001F00U +#define LPDDR4__DENALI_CTL_228__AREF_MAX_CREDIT_SHIFT 8U +#define LPDDR4__DENALI_CTL_228__AREF_MAX_CREDIT_WIDTH 5U +#define LPDDR4__AREF_MAX_CREDIT__REG DENALI_CTL_228 +#define LPDDR4__AREF_MAX_CREDIT__FLD LPDDR4__DENALI_CTL_228__AREF_MAX_CREDIT + +#define LPDDR4__DENALI_CTL_228__AREF_CMD_MAX_PER_TREFI_MASK 0x000F0000U +#define LPDDR4__DENALI_CTL_228__AREF_CMD_MAX_PER_TREFI_SHIFT 16U +#define LPDDR4__DENALI_CTL_228__AREF_CMD_MAX_PER_TREFI_WIDTH 4U +#define LPDDR4__AREF_CMD_MAX_PER_TREFI__REG DENALI_CTL_228 +#define LPDDR4__AREF_CMD_MAX_PER_TREFI__FLD LPDDR4__DENALI_CTL_228__AREF_CMD_MAX_PER_TREFI + +#define LPDDR4__DENALI_CTL_229_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_229_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_229__ZQ_CALSTART_NORM_THRESHOLD_F0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_229__ZQ_CALSTART_NORM_THRESHOLD_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_229__ZQ_CALSTART_NORM_THRESHOLD_F0_WIDTH 16U +#define LPDDR4__ZQ_CALSTART_NORM_THRESHOLD_F0__REG DENALI_CTL_229 +#define LPDDR4__ZQ_CALSTART_NORM_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_229__ZQ_CALSTART_NORM_THRESHOLD_F0 + +#define LPDDR4__DENALI_CTL_229__ZQ_CALSTART_HIGH_THRESHOLD_F0_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_229__ZQ_CALSTART_HIGH_THRESHOLD_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_229__ZQ_CALSTART_HIGH_THRESHOLD_F0_WIDTH 16U +#define LPDDR4__ZQ_CALSTART_HIGH_THRESHOLD_F0__REG DENALI_CTL_229 +#define LPDDR4__ZQ_CALSTART_HIGH_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_229__ZQ_CALSTART_HIGH_THRESHOLD_F0 + +#define LPDDR4__DENALI_CTL_230_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_230_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_230__ZQ_CALLATCH_HIGH_THRESHOLD_F0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_230__ZQ_CALLATCH_HIGH_THRESHOLD_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_230__ZQ_CALLATCH_HIGH_THRESHOLD_F0_WIDTH 16U +#define LPDDR4__ZQ_CALLATCH_HIGH_THRESHOLD_F0__REG DENALI_CTL_230 +#define LPDDR4__ZQ_CALLATCH_HIGH_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_230__ZQ_CALLATCH_HIGH_THRESHOLD_F0 + +#define LPDDR4__DENALI_CTL_230__ZQ_CS_NORM_THRESHOLD_F0_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_230__ZQ_CS_NORM_THRESHOLD_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_230__ZQ_CS_NORM_THRESHOLD_F0_WIDTH 16U +#define LPDDR4__ZQ_CS_NORM_THRESHOLD_F0__REG DENALI_CTL_230 +#define LPDDR4__ZQ_CS_NORM_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_230__ZQ_CS_NORM_THRESHOLD_F0 + +#define LPDDR4__DENALI_CTL_231_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_231_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_231__ZQ_CS_HIGH_THRESHOLD_F0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_231__ZQ_CS_HIGH_THRESHOLD_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_231__ZQ_CS_HIGH_THRESHOLD_F0_WIDTH 16U +#define LPDDR4__ZQ_CS_HIGH_THRESHOLD_F0__REG DENALI_CTL_231 +#define LPDDR4__ZQ_CS_HIGH_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_231__ZQ_CS_HIGH_THRESHOLD_F0 + +#define LPDDR4__DENALI_CTL_231__ZQ_CALSTART_TIMEOUT_F0_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_231__ZQ_CALSTART_TIMEOUT_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_231__ZQ_CALSTART_TIMEOUT_F0_WIDTH 16U +#define LPDDR4__ZQ_CALSTART_TIMEOUT_F0__REG DENALI_CTL_231 +#define LPDDR4__ZQ_CALSTART_TIMEOUT_F0__FLD LPDDR4__DENALI_CTL_231__ZQ_CALSTART_TIMEOUT_F0 + +#define LPDDR4__DENALI_CTL_232_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_232_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_232__ZQ_CALLATCH_TIMEOUT_F0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_232__ZQ_CALLATCH_TIMEOUT_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_232__ZQ_CALLATCH_TIMEOUT_F0_WIDTH 16U +#define LPDDR4__ZQ_CALLATCH_TIMEOUT_F0__REG DENALI_CTL_232 +#define LPDDR4__ZQ_CALLATCH_TIMEOUT_F0__FLD LPDDR4__DENALI_CTL_232__ZQ_CALLATCH_TIMEOUT_F0 + +#define LPDDR4__DENALI_CTL_232__ZQ_CS_TIMEOUT_F0_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_232__ZQ_CS_TIMEOUT_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_232__ZQ_CS_TIMEOUT_F0_WIDTH 16U +#define LPDDR4__ZQ_CS_TIMEOUT_F0__REG DENALI_CTL_232 +#define LPDDR4__ZQ_CS_TIMEOUT_F0__FLD LPDDR4__DENALI_CTL_232__ZQ_CS_TIMEOUT_F0 + +#define LPDDR4__DENALI_CTL_233_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_233_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_233__ZQ_PROMOTE_THRESHOLD_F0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_233__ZQ_PROMOTE_THRESHOLD_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_233__ZQ_PROMOTE_THRESHOLD_F0_WIDTH 16U +#define LPDDR4__ZQ_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_233 +#define LPDDR4__ZQ_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_233__ZQ_PROMOTE_THRESHOLD_F0 + +#define LPDDR4__DENALI_CTL_233__ZQ_CALSTART_NORM_THRESHOLD_F1_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_233__ZQ_CALSTART_NORM_THRESHOLD_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_233__ZQ_CALSTART_NORM_THRESHOLD_F1_WIDTH 16U +#define LPDDR4__ZQ_CALSTART_NORM_THRESHOLD_F1__REG DENALI_CTL_233 +#define LPDDR4__ZQ_CALSTART_NORM_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_233__ZQ_CALSTART_NORM_THRESHOLD_F1 + +#define LPDDR4__DENALI_CTL_234_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_234_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_234__ZQ_CALSTART_HIGH_THRESHOLD_F1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_234__ZQ_CALSTART_HIGH_THRESHOLD_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_234__ZQ_CALSTART_HIGH_THRESHOLD_F1_WIDTH 16U +#define LPDDR4__ZQ_CALSTART_HIGH_THRESHOLD_F1__REG DENALI_CTL_234 +#define LPDDR4__ZQ_CALSTART_HIGH_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_234__ZQ_CALSTART_HIGH_THRESHOLD_F1 + +#define LPDDR4__DENALI_CTL_234__ZQ_CALLATCH_HIGH_THRESHOLD_F1_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_234__ZQ_CALLATCH_HIGH_THRESHOLD_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_234__ZQ_CALLATCH_HIGH_THRESHOLD_F1_WIDTH 16U +#define LPDDR4__ZQ_CALLATCH_HIGH_THRESHOLD_F1__REG DENALI_CTL_234 +#define LPDDR4__ZQ_CALLATCH_HIGH_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_234__ZQ_CALLATCH_HIGH_THRESHOLD_F1 + +#define LPDDR4__DENALI_CTL_235_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_235_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_235__ZQ_CS_NORM_THRESHOLD_F1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_235__ZQ_CS_NORM_THRESHOLD_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_235__ZQ_CS_NORM_THRESHOLD_F1_WIDTH 16U +#define LPDDR4__ZQ_CS_NORM_THRESHOLD_F1__REG DENALI_CTL_235 +#define LPDDR4__ZQ_CS_NORM_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_235__ZQ_CS_NORM_THRESHOLD_F1 + +#define LPDDR4__DENALI_CTL_235__ZQ_CS_HIGH_THRESHOLD_F1_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_235__ZQ_CS_HIGH_THRESHOLD_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_235__ZQ_CS_HIGH_THRESHOLD_F1_WIDTH 16U +#define LPDDR4__ZQ_CS_HIGH_THRESHOLD_F1__REG DENALI_CTL_235 +#define LPDDR4__ZQ_CS_HIGH_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_235__ZQ_CS_HIGH_THRESHOLD_F1 + +#define LPDDR4__DENALI_CTL_236_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_236_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_236__ZQ_CALSTART_TIMEOUT_F1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_236__ZQ_CALSTART_TIMEOUT_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_236__ZQ_CALSTART_TIMEOUT_F1_WIDTH 16U +#define LPDDR4__ZQ_CALSTART_TIMEOUT_F1__REG DENALI_CTL_236 +#define LPDDR4__ZQ_CALSTART_TIMEOUT_F1__FLD LPDDR4__DENALI_CTL_236__ZQ_CALSTART_TIMEOUT_F1 + +#define LPDDR4__DENALI_CTL_236__ZQ_CALLATCH_TIMEOUT_F1_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_236__ZQ_CALLATCH_TIMEOUT_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_236__ZQ_CALLATCH_TIMEOUT_F1_WIDTH 16U +#define LPDDR4__ZQ_CALLATCH_TIMEOUT_F1__REG DENALI_CTL_236 +#define LPDDR4__ZQ_CALLATCH_TIMEOUT_F1__FLD LPDDR4__DENALI_CTL_236__ZQ_CALLATCH_TIMEOUT_F1 + +#define LPDDR4__DENALI_CTL_237_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_237_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_237__ZQ_CS_TIMEOUT_F1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_237__ZQ_CS_TIMEOUT_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_237__ZQ_CS_TIMEOUT_F1_WIDTH 16U +#define LPDDR4__ZQ_CS_TIMEOUT_F1__REG DENALI_CTL_237 +#define LPDDR4__ZQ_CS_TIMEOUT_F1__FLD LPDDR4__DENALI_CTL_237__ZQ_CS_TIMEOUT_F1 + +#define LPDDR4__DENALI_CTL_237__ZQ_PROMOTE_THRESHOLD_F1_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_237__ZQ_PROMOTE_THRESHOLD_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_237__ZQ_PROMOTE_THRESHOLD_F1_WIDTH 16U +#define LPDDR4__ZQ_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_237 +#define LPDDR4__ZQ_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_237__ZQ_PROMOTE_THRESHOLD_F1 + +#define LPDDR4__DENALI_CTL_238_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_238_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_238__ZQ_CALSTART_NORM_THRESHOLD_F2_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_238__ZQ_CALSTART_NORM_THRESHOLD_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_238__ZQ_CALSTART_NORM_THRESHOLD_F2_WIDTH 16U +#define LPDDR4__ZQ_CALSTART_NORM_THRESHOLD_F2__REG DENALI_CTL_238 +#define LPDDR4__ZQ_CALSTART_NORM_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_238__ZQ_CALSTART_NORM_THRESHOLD_F2 + +#define LPDDR4__DENALI_CTL_238__ZQ_CALSTART_HIGH_THRESHOLD_F2_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_238__ZQ_CALSTART_HIGH_THRESHOLD_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_238__ZQ_CALSTART_HIGH_THRESHOLD_F2_WIDTH 16U +#define LPDDR4__ZQ_CALSTART_HIGH_THRESHOLD_F2__REG DENALI_CTL_238 +#define LPDDR4__ZQ_CALSTART_HIGH_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_238__ZQ_CALSTART_HIGH_THRESHOLD_F2 + +#define LPDDR4__DENALI_CTL_239_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_239_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_239__ZQ_CALLATCH_HIGH_THRESHOLD_F2_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_239__ZQ_CALLATCH_HIGH_THRESHOLD_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_239__ZQ_CALLATCH_HIGH_THRESHOLD_F2_WIDTH 16U +#define LPDDR4__ZQ_CALLATCH_HIGH_THRESHOLD_F2__REG DENALI_CTL_239 +#define LPDDR4__ZQ_CALLATCH_HIGH_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_239__ZQ_CALLATCH_HIGH_THRESHOLD_F2 + +#define LPDDR4__DENALI_CTL_239__ZQ_CS_NORM_THRESHOLD_F2_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_239__ZQ_CS_NORM_THRESHOLD_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_239__ZQ_CS_NORM_THRESHOLD_F2_WIDTH 16U +#define LPDDR4__ZQ_CS_NORM_THRESHOLD_F2__REG DENALI_CTL_239 +#define LPDDR4__ZQ_CS_NORM_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_239__ZQ_CS_NORM_THRESHOLD_F2 + +#define LPDDR4__DENALI_CTL_240_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_240_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_240__ZQ_CS_HIGH_THRESHOLD_F2_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_240__ZQ_CS_HIGH_THRESHOLD_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_240__ZQ_CS_HIGH_THRESHOLD_F2_WIDTH 16U +#define LPDDR4__ZQ_CS_HIGH_THRESHOLD_F2__REG DENALI_CTL_240 +#define LPDDR4__ZQ_CS_HIGH_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_240__ZQ_CS_HIGH_THRESHOLD_F2 + +#define LPDDR4__DENALI_CTL_240__ZQ_CALSTART_TIMEOUT_F2_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_240__ZQ_CALSTART_TIMEOUT_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_240__ZQ_CALSTART_TIMEOUT_F2_WIDTH 16U +#define LPDDR4__ZQ_CALSTART_TIMEOUT_F2__REG DENALI_CTL_240 +#define LPDDR4__ZQ_CALSTART_TIMEOUT_F2__FLD LPDDR4__DENALI_CTL_240__ZQ_CALSTART_TIMEOUT_F2 + +#define LPDDR4__DENALI_CTL_241_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_241_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_241__ZQ_CALLATCH_TIMEOUT_F2_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_241__ZQ_CALLATCH_TIMEOUT_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_241__ZQ_CALLATCH_TIMEOUT_F2_WIDTH 16U +#define LPDDR4__ZQ_CALLATCH_TIMEOUT_F2__REG DENALI_CTL_241 +#define LPDDR4__ZQ_CALLATCH_TIMEOUT_F2__FLD LPDDR4__DENALI_CTL_241__ZQ_CALLATCH_TIMEOUT_F2 + +#define LPDDR4__DENALI_CTL_241__ZQ_CS_TIMEOUT_F2_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_241__ZQ_CS_TIMEOUT_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_241__ZQ_CS_TIMEOUT_F2_WIDTH 16U +#define LPDDR4__ZQ_CS_TIMEOUT_F2__REG DENALI_CTL_241 +#define LPDDR4__ZQ_CS_TIMEOUT_F2__FLD LPDDR4__DENALI_CTL_241__ZQ_CS_TIMEOUT_F2 + +#define LPDDR4__DENALI_CTL_242_READ_MASK 0x0007FFFFU +#define LPDDR4__DENALI_CTL_242_WRITE_MASK 0x0007FFFFU +#define LPDDR4__DENALI_CTL_242__ZQ_PROMOTE_THRESHOLD_F2_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_242__ZQ_PROMOTE_THRESHOLD_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_242__ZQ_PROMOTE_THRESHOLD_F2_WIDTH 16U +#define LPDDR4__ZQ_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_242 +#define LPDDR4__ZQ_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_242__ZQ_PROMOTE_THRESHOLD_F2 + +#define LPDDR4__DENALI_CTL_242__MC_RESERVED23_MASK 0x00070000U +#define LPDDR4__DENALI_CTL_242__MC_RESERVED23_SHIFT 16U +#define LPDDR4__DENALI_CTL_242__MC_RESERVED23_WIDTH 3U +#define LPDDR4__MC_RESERVED23__REG DENALI_CTL_242 +#define LPDDR4__MC_RESERVED23__FLD LPDDR4__DENALI_CTL_242__MC_RESERVED23 + +#define LPDDR4__DENALI_CTL_243_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_243_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_243__WATCHDOG_THRESHOLD_TASK_ARB_F0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_243__WATCHDOG_THRESHOLD_TASK_ARB_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_243__WATCHDOG_THRESHOLD_TASK_ARB_F0_WIDTH 16U +#define LPDDR4__WATCHDOG_THRESHOLD_TASK_ARB_F0__REG DENALI_CTL_243 +#define LPDDR4__WATCHDOG_THRESHOLD_TASK_ARB_F0__FLD LPDDR4__DENALI_CTL_243__WATCHDOG_THRESHOLD_TASK_ARB_F0 + +#define LPDDR4__DENALI_CTL_243__WATCHDOG_THRESHOLD_BUS_ARB_F0_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_243__WATCHDOG_THRESHOLD_BUS_ARB_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_243__WATCHDOG_THRESHOLD_BUS_ARB_F0_WIDTH 16U +#define LPDDR4__WATCHDOG_THRESHOLD_BUS_ARB_F0__REG DENALI_CTL_243 +#define LPDDR4__WATCHDOG_THRESHOLD_BUS_ARB_F0__FLD LPDDR4__DENALI_CTL_243__WATCHDOG_THRESHOLD_BUS_ARB_F0 + +#define LPDDR4__DENALI_CTL_244_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_244_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_244__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_244__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_244__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F0_WIDTH 16U +#define LPDDR4__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F0__REG DENALI_CTL_244 +#define LPDDR4__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F0__FLD LPDDR4__DENALI_CTL_244__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F0 + +#define LPDDR4__DENALI_CTL_244__WATCHDOG_THRESHOLD_SPLIT_F0_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_244__WATCHDOG_THRESHOLD_SPLIT_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_244__WATCHDOG_THRESHOLD_SPLIT_F0_WIDTH 16U +#define LPDDR4__WATCHDOG_THRESHOLD_SPLIT_F0__REG DENALI_CTL_244 +#define LPDDR4__WATCHDOG_THRESHOLD_SPLIT_F0__FLD LPDDR4__DENALI_CTL_244__WATCHDOG_THRESHOLD_SPLIT_F0 + +#define LPDDR4__DENALI_CTL_245_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_245_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_245__WATCHDOG_THRESHOLD_STRATEGY_F0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_245__WATCHDOG_THRESHOLD_STRATEGY_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_245__WATCHDOG_THRESHOLD_STRATEGY_F0_WIDTH 16U +#define LPDDR4__WATCHDOG_THRESHOLD_STRATEGY_F0__REG DENALI_CTL_245 +#define LPDDR4__WATCHDOG_THRESHOLD_STRATEGY_F0__FLD LPDDR4__DENALI_CTL_245__WATCHDOG_THRESHOLD_STRATEGY_F0 + +#define LPDDR4__DENALI_CTL_245__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F0_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_245__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_245__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F0_WIDTH 16U +#define LPDDR4__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F0__REG DENALI_CTL_245 +#define LPDDR4__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F0__FLD LPDDR4__DENALI_CTL_245__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F0 + +#define LPDDR4__DENALI_CTL_246_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_246_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_246__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_246__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_246__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F0_WIDTH 16U +#define LPDDR4__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F0__REG DENALI_CTL_246 +#define LPDDR4__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F0__FLD LPDDR4__DENALI_CTL_246__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F0 + +#define LPDDR4__DENALI_CTL_246__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F0_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_246__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_246__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F0_WIDTH 16U +#define LPDDR4__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F0__REG DENALI_CTL_246 +#define LPDDR4__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F0__FLD LPDDR4__DENALI_CTL_246__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F0 + +#define LPDDR4__DENALI_CTL_247_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_247_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_247__WATCHDOG_THRESHOLD_TASK_ARB_F1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_247__WATCHDOG_THRESHOLD_TASK_ARB_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_247__WATCHDOG_THRESHOLD_TASK_ARB_F1_WIDTH 16U +#define LPDDR4__WATCHDOG_THRESHOLD_TASK_ARB_F1__REG DENALI_CTL_247 +#define LPDDR4__WATCHDOG_THRESHOLD_TASK_ARB_F1__FLD LPDDR4__DENALI_CTL_247__WATCHDOG_THRESHOLD_TASK_ARB_F1 + +#define LPDDR4__DENALI_CTL_247__WATCHDOG_THRESHOLD_BUS_ARB_F1_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_247__WATCHDOG_THRESHOLD_BUS_ARB_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_247__WATCHDOG_THRESHOLD_BUS_ARB_F1_WIDTH 16U +#define LPDDR4__WATCHDOG_THRESHOLD_BUS_ARB_F1__REG DENALI_CTL_247 +#define LPDDR4__WATCHDOG_THRESHOLD_BUS_ARB_F1__FLD LPDDR4__DENALI_CTL_247__WATCHDOG_THRESHOLD_BUS_ARB_F1 + +#define LPDDR4__DENALI_CTL_248_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_248_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_248__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_248__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_248__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F1_WIDTH 16U +#define LPDDR4__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F1__REG DENALI_CTL_248 +#define LPDDR4__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F1__FLD LPDDR4__DENALI_CTL_248__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F1 + +#define LPDDR4__DENALI_CTL_248__WATCHDOG_THRESHOLD_SPLIT_F1_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_248__WATCHDOG_THRESHOLD_SPLIT_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_248__WATCHDOG_THRESHOLD_SPLIT_F1_WIDTH 16U +#define LPDDR4__WATCHDOG_THRESHOLD_SPLIT_F1__REG DENALI_CTL_248 +#define LPDDR4__WATCHDOG_THRESHOLD_SPLIT_F1__FLD LPDDR4__DENALI_CTL_248__WATCHDOG_THRESHOLD_SPLIT_F1 + +#define LPDDR4__DENALI_CTL_249_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_249_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_249__WATCHDOG_THRESHOLD_STRATEGY_F1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_249__WATCHDOG_THRESHOLD_STRATEGY_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_249__WATCHDOG_THRESHOLD_STRATEGY_F1_WIDTH 16U +#define LPDDR4__WATCHDOG_THRESHOLD_STRATEGY_F1__REG DENALI_CTL_249 +#define LPDDR4__WATCHDOG_THRESHOLD_STRATEGY_F1__FLD LPDDR4__DENALI_CTL_249__WATCHDOG_THRESHOLD_STRATEGY_F1 + +#define LPDDR4__DENALI_CTL_249__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F1_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_249__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_249__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F1_WIDTH 16U +#define LPDDR4__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F1__REG DENALI_CTL_249 +#define LPDDR4__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F1__FLD LPDDR4__DENALI_CTL_249__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F1 + +#define LPDDR4__DENALI_CTL_250_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_250_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_250__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_250__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_250__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F1_WIDTH 16U +#define LPDDR4__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F1__REG DENALI_CTL_250 +#define LPDDR4__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F1__FLD LPDDR4__DENALI_CTL_250__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F1 + +#define LPDDR4__DENALI_CTL_250__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F1_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_250__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_250__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F1_WIDTH 16U +#define LPDDR4__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F1__REG DENALI_CTL_250 +#define LPDDR4__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F1__FLD LPDDR4__DENALI_CTL_250__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F1 + +#define LPDDR4__DENALI_CTL_251_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_251_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_251__WATCHDOG_THRESHOLD_TASK_ARB_F2_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_251__WATCHDOG_THRESHOLD_TASK_ARB_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_251__WATCHDOG_THRESHOLD_TASK_ARB_F2_WIDTH 16U +#define LPDDR4__WATCHDOG_THRESHOLD_TASK_ARB_F2__REG DENALI_CTL_251 +#define LPDDR4__WATCHDOG_THRESHOLD_TASK_ARB_F2__FLD LPDDR4__DENALI_CTL_251__WATCHDOG_THRESHOLD_TASK_ARB_F2 + +#define LPDDR4__DENALI_CTL_251__WATCHDOG_THRESHOLD_BUS_ARB_F2_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_251__WATCHDOG_THRESHOLD_BUS_ARB_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_251__WATCHDOG_THRESHOLD_BUS_ARB_F2_WIDTH 16U +#define LPDDR4__WATCHDOG_THRESHOLD_BUS_ARB_F2__REG DENALI_CTL_251 +#define LPDDR4__WATCHDOG_THRESHOLD_BUS_ARB_F2__FLD LPDDR4__DENALI_CTL_251__WATCHDOG_THRESHOLD_BUS_ARB_F2 + +#define LPDDR4__DENALI_CTL_252_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_252_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_252__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F2_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_252__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_252__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F2_WIDTH 16U +#define LPDDR4__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F2__REG DENALI_CTL_252 +#define LPDDR4__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F2__FLD LPDDR4__DENALI_CTL_252__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F2 + +#define LPDDR4__DENALI_CTL_252__WATCHDOG_THRESHOLD_SPLIT_F2_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_252__WATCHDOG_THRESHOLD_SPLIT_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_252__WATCHDOG_THRESHOLD_SPLIT_F2_WIDTH 16U +#define LPDDR4__WATCHDOG_THRESHOLD_SPLIT_F2__REG DENALI_CTL_252 +#define LPDDR4__WATCHDOG_THRESHOLD_SPLIT_F2__FLD LPDDR4__DENALI_CTL_252__WATCHDOG_THRESHOLD_SPLIT_F2 + +#define LPDDR4__DENALI_CTL_253_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_253_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_253__WATCHDOG_THRESHOLD_STRATEGY_F2_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_253__WATCHDOG_THRESHOLD_STRATEGY_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_253__WATCHDOG_THRESHOLD_STRATEGY_F2_WIDTH 16U +#define LPDDR4__WATCHDOG_THRESHOLD_STRATEGY_F2__REG DENALI_CTL_253 +#define LPDDR4__WATCHDOG_THRESHOLD_STRATEGY_F2__FLD LPDDR4__DENALI_CTL_253__WATCHDOG_THRESHOLD_STRATEGY_F2 + +#define LPDDR4__DENALI_CTL_253__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F2_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_253__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_253__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F2_WIDTH 16U +#define LPDDR4__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F2__REG DENALI_CTL_253 +#define LPDDR4__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F2__FLD LPDDR4__DENALI_CTL_253__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F2 + +#define LPDDR4__DENALI_CTL_254_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_254_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_254__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F2_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_254__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_254__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F2_WIDTH 16U +#define LPDDR4__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F2__REG DENALI_CTL_254 +#define LPDDR4__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F2__FLD LPDDR4__DENALI_CTL_254__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F2 + +#define LPDDR4__DENALI_CTL_254__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F2_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_254__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_254__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F2_WIDTH 16U +#define LPDDR4__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F2__REG DENALI_CTL_254 +#define LPDDR4__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F2__FLD LPDDR4__DENALI_CTL_254__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F2 + +#define LPDDR4__DENALI_CTL_255_READ_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_255_WRITE_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_255__WATCHDOG_RELOAD_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_255__WATCHDOG_RELOAD_SHIFT 0U +#define LPDDR4__DENALI_CTL_255__WATCHDOG_RELOAD_WIDTH 8U +#define LPDDR4__WATCHDOG_RELOAD__REG DENALI_CTL_255 +#define LPDDR4__WATCHDOG_RELOAD__FLD LPDDR4__DENALI_CTL_255__WATCHDOG_RELOAD + +#define LPDDR4__DENALI_CTL_255__WATCHDOG_DIAGNOSTIC_MODE_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_255__WATCHDOG_DIAGNOSTIC_MODE_SHIFT 8U +#define LPDDR4__DENALI_CTL_255__WATCHDOG_DIAGNOSTIC_MODE_WIDTH 8U +#define LPDDR4__WATCHDOG_DIAGNOSTIC_MODE__REG DENALI_CTL_255 +#define LPDDR4__WATCHDOG_DIAGNOSTIC_MODE__FLD LPDDR4__DENALI_CTL_255__WATCHDOG_DIAGNOSTIC_MODE + +#define LPDDR4__DENALI_CTL_256_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_256_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_256__TIMEOUT_TIMER_LOG_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_256__TIMEOUT_TIMER_LOG_SHIFT 0U +#define LPDDR4__DENALI_CTL_256__TIMEOUT_TIMER_LOG_WIDTH 20U +#define LPDDR4__TIMEOUT_TIMER_LOG__REG DENALI_CTL_256 +#define LPDDR4__TIMEOUT_TIMER_LOG__FLD LPDDR4__DENALI_CTL_256__TIMEOUT_TIMER_LOG + +#define LPDDR4__DENALI_CTL_257_READ_MASK 0x0FFF0FFFU +#define LPDDR4__DENALI_CTL_257_WRITE_MASK 0x0FFF0FFFU +#define LPDDR4__DENALI_CTL_257__ZQINIT_F0_MASK 0x00000FFFU +#define LPDDR4__DENALI_CTL_257__ZQINIT_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_257__ZQINIT_F0_WIDTH 12U +#define LPDDR4__ZQINIT_F0__REG DENALI_CTL_257 +#define LPDDR4__ZQINIT_F0__FLD LPDDR4__DENALI_CTL_257__ZQINIT_F0 + +#define LPDDR4__DENALI_CTL_257__ZQCL_F0_MASK 0x0FFF0000U +#define LPDDR4__DENALI_CTL_257__ZQCL_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_257__ZQCL_F0_WIDTH 12U +#define LPDDR4__ZQCL_F0__REG DENALI_CTL_257 +#define LPDDR4__ZQCL_F0__FLD LPDDR4__DENALI_CTL_257__ZQCL_F0 + +#define LPDDR4__DENALI_CTL_258_READ_MASK 0x0FFF0FFFU +#define LPDDR4__DENALI_CTL_258_WRITE_MASK 0x0FFF0FFFU +#define LPDDR4__DENALI_CTL_258__ZQCS_F0_MASK 0x00000FFFU +#define LPDDR4__DENALI_CTL_258__ZQCS_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_258__ZQCS_F0_WIDTH 12U +#define LPDDR4__ZQCS_F0__REG DENALI_CTL_258 +#define LPDDR4__ZQCS_F0__FLD LPDDR4__DENALI_CTL_258__ZQCS_F0 + +#define LPDDR4__DENALI_CTL_258__TZQCAL_F0_MASK 0x0FFF0000U +#define LPDDR4__DENALI_CTL_258__TZQCAL_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_258__TZQCAL_F0_WIDTH 12U +#define LPDDR4__TZQCAL_F0__REG DENALI_CTL_258 +#define LPDDR4__TZQCAL_F0__FLD LPDDR4__DENALI_CTL_258__TZQCAL_F0 + +#define LPDDR4__DENALI_CTL_259_READ_MASK 0x000FFF7FU +#define LPDDR4__DENALI_CTL_259_WRITE_MASK 0x000FFF7FU +#define LPDDR4__DENALI_CTL_259__TZQLAT_F0_MASK 0x0000007FU +#define LPDDR4__DENALI_CTL_259__TZQLAT_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_259__TZQLAT_F0_WIDTH 7U +#define LPDDR4__TZQLAT_F0__REG DENALI_CTL_259 +#define LPDDR4__TZQLAT_F0__FLD LPDDR4__DENALI_CTL_259__TZQLAT_F0 + +#define LPDDR4__DENALI_CTL_259__ZQINIT_F1_MASK 0x000FFF00U +#define LPDDR4__DENALI_CTL_259__ZQINIT_F1_SHIFT 8U +#define LPDDR4__DENALI_CTL_259__ZQINIT_F1_WIDTH 12U +#define LPDDR4__ZQINIT_F1__REG DENALI_CTL_259 +#define LPDDR4__ZQINIT_F1__FLD LPDDR4__DENALI_CTL_259__ZQINIT_F1 + +#define LPDDR4__DENALI_CTL_260_READ_MASK 0x0FFF0FFFU +#define LPDDR4__DENALI_CTL_260_WRITE_MASK 0x0FFF0FFFU +#define LPDDR4__DENALI_CTL_260__ZQCL_F1_MASK 0x00000FFFU +#define LPDDR4__DENALI_CTL_260__ZQCL_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_260__ZQCL_F1_WIDTH 12U +#define LPDDR4__ZQCL_F1__REG DENALI_CTL_260 +#define LPDDR4__ZQCL_F1__FLD LPDDR4__DENALI_CTL_260__ZQCL_F1 + +#define LPDDR4__DENALI_CTL_260__ZQCS_F1_MASK 0x0FFF0000U +#define LPDDR4__DENALI_CTL_260__ZQCS_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_260__ZQCS_F1_WIDTH 12U +#define LPDDR4__ZQCS_F1__REG DENALI_CTL_260 +#define LPDDR4__ZQCS_F1__FLD LPDDR4__DENALI_CTL_260__ZQCS_F1 + +#define LPDDR4__DENALI_CTL_261_READ_MASK 0x007F0FFFU +#define LPDDR4__DENALI_CTL_261_WRITE_MASK 0x007F0FFFU +#define LPDDR4__DENALI_CTL_261__TZQCAL_F1_MASK 0x00000FFFU +#define LPDDR4__DENALI_CTL_261__TZQCAL_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_261__TZQCAL_F1_WIDTH 12U +#define LPDDR4__TZQCAL_F1__REG DENALI_CTL_261 +#define LPDDR4__TZQCAL_F1__FLD LPDDR4__DENALI_CTL_261__TZQCAL_F1 + +#define LPDDR4__DENALI_CTL_261__TZQLAT_F1_MASK 0x007F0000U +#define LPDDR4__DENALI_CTL_261__TZQLAT_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_261__TZQLAT_F1_WIDTH 7U +#define LPDDR4__TZQLAT_F1__REG DENALI_CTL_261 +#define LPDDR4__TZQLAT_F1__FLD LPDDR4__DENALI_CTL_261__TZQLAT_F1 + +#define LPDDR4__DENALI_CTL_262_READ_MASK 0x0FFF0FFFU +#define LPDDR4__DENALI_CTL_262_WRITE_MASK 0x0FFF0FFFU +#define LPDDR4__DENALI_CTL_262__ZQINIT_F2_MASK 0x00000FFFU +#define LPDDR4__DENALI_CTL_262__ZQINIT_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_262__ZQINIT_F2_WIDTH 12U +#define LPDDR4__ZQINIT_F2__REG DENALI_CTL_262 +#define LPDDR4__ZQINIT_F2__FLD LPDDR4__DENALI_CTL_262__ZQINIT_F2 + +#define LPDDR4__DENALI_CTL_262__ZQCL_F2_MASK 0x0FFF0000U +#define LPDDR4__DENALI_CTL_262__ZQCL_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_262__ZQCL_F2_WIDTH 12U +#define LPDDR4__ZQCL_F2__REG DENALI_CTL_262 +#define LPDDR4__ZQCL_F2__FLD LPDDR4__DENALI_CTL_262__ZQCL_F2 + +#define LPDDR4__DENALI_CTL_263_READ_MASK 0x0FFF0FFFU +#define LPDDR4__DENALI_CTL_263_WRITE_MASK 0x0FFF0FFFU +#define LPDDR4__DENALI_CTL_263__ZQCS_F2_MASK 0x00000FFFU +#define LPDDR4__DENALI_CTL_263__ZQCS_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_263__ZQCS_F2_WIDTH 12U +#define LPDDR4__ZQCS_F2__REG DENALI_CTL_263 +#define LPDDR4__ZQCS_F2__FLD LPDDR4__DENALI_CTL_263__ZQCS_F2 + +#define LPDDR4__DENALI_CTL_263__TZQCAL_F2_MASK 0x0FFF0000U +#define LPDDR4__DENALI_CTL_263__TZQCAL_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_263__TZQCAL_F2_WIDTH 12U +#define LPDDR4__TZQCAL_F2__REG DENALI_CTL_263 +#define LPDDR4__TZQCAL_F2__FLD LPDDR4__DENALI_CTL_263__TZQCAL_F2 + +#define LPDDR4__DENALI_CTL_264_READ_MASK 0x0100037FU +#define LPDDR4__DENALI_CTL_264_WRITE_MASK 0x0100037FU +#define LPDDR4__DENALI_CTL_264__TZQLAT_F2_MASK 0x0000007FU +#define LPDDR4__DENALI_CTL_264__TZQLAT_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_264__TZQLAT_F2_WIDTH 7U +#define LPDDR4__TZQLAT_F2__REG DENALI_CTL_264 +#define LPDDR4__TZQLAT_F2__FLD LPDDR4__DENALI_CTL_264__TZQLAT_F2 + +#define LPDDR4__DENALI_CTL_264__ZQ_SW_REQ_START_LATCH_MAP_MASK 0x00000300U +#define LPDDR4__DENALI_CTL_264__ZQ_SW_REQ_START_LATCH_MAP_SHIFT 8U +#define LPDDR4__DENALI_CTL_264__ZQ_SW_REQ_START_LATCH_MAP_WIDTH 2U +#define LPDDR4__ZQ_SW_REQ_START_LATCH_MAP__REG DENALI_CTL_264 +#define LPDDR4__ZQ_SW_REQ_START_LATCH_MAP__FLD LPDDR4__DENALI_CTL_264__ZQ_SW_REQ_START_LATCH_MAP + +#define LPDDR4__DENALI_CTL_264__ZQ_REQ_MASK 0x000F0000U +#define LPDDR4__DENALI_CTL_264__ZQ_REQ_SHIFT 16U +#define LPDDR4__DENALI_CTL_264__ZQ_REQ_WIDTH 4U +#define LPDDR4__ZQ_REQ__REG DENALI_CTL_264 +#define LPDDR4__ZQ_REQ__FLD LPDDR4__DENALI_CTL_264__ZQ_REQ + +#define LPDDR4__DENALI_CTL_264__ZQ_REQ_PENDING_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_264__ZQ_REQ_PENDING_SHIFT 24U +#define LPDDR4__DENALI_CTL_264__ZQ_REQ_PENDING_WIDTH 1U +#define LPDDR4__DENALI_CTL_264__ZQ_REQ_PENDING_WOCLR 0U +#define LPDDR4__DENALI_CTL_264__ZQ_REQ_PENDING_WOSET 0U +#define LPDDR4__ZQ_REQ_PENDING__REG DENALI_CTL_264 +#define LPDDR4__ZQ_REQ_PENDING__FLD LPDDR4__DENALI_CTL_264__ZQ_REQ_PENDING + +#define LPDDR4__DENALI_CTL_265_READ_MASK 0x0FFF0FFFU +#define LPDDR4__DENALI_CTL_265_WRITE_MASK 0x0FFF0FFFU +#define LPDDR4__DENALI_CTL_265__ZQRESET_F0_MASK 0x00000FFFU +#define LPDDR4__DENALI_CTL_265__ZQRESET_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_265__ZQRESET_F0_WIDTH 12U +#define LPDDR4__ZQRESET_F0__REG DENALI_CTL_265 +#define LPDDR4__ZQRESET_F0__FLD LPDDR4__DENALI_CTL_265__ZQRESET_F0 + +#define LPDDR4__DENALI_CTL_265__ZQRESET_F1_MASK 0x0FFF0000U +#define LPDDR4__DENALI_CTL_265__ZQRESET_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_265__ZQRESET_F1_WIDTH 12U +#define LPDDR4__ZQRESET_F1__REG DENALI_CTL_265 +#define LPDDR4__ZQRESET_F1__FLD LPDDR4__DENALI_CTL_265__ZQRESET_F1 + +#define LPDDR4__DENALI_CTL_266_READ_MASK 0x01010FFFU +#define LPDDR4__DENALI_CTL_266_WRITE_MASK 0x01010FFFU +#define LPDDR4__DENALI_CTL_266__ZQRESET_F2_MASK 0x00000FFFU +#define LPDDR4__DENALI_CTL_266__ZQRESET_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_266__ZQRESET_F2_WIDTH 12U +#define LPDDR4__ZQRESET_F2__REG DENALI_CTL_266 +#define LPDDR4__ZQRESET_F2__FLD LPDDR4__DENALI_CTL_266__ZQRESET_F2 + +#define LPDDR4__DENALI_CTL_266__NO_ZQ_INIT_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_266__NO_ZQ_INIT_SHIFT 16U +#define LPDDR4__DENALI_CTL_266__NO_ZQ_INIT_WIDTH 1U +#define LPDDR4__DENALI_CTL_266__NO_ZQ_INIT_WOCLR 0U +#define LPDDR4__DENALI_CTL_266__NO_ZQ_INIT_WOSET 0U +#define LPDDR4__NO_ZQ_INIT__REG DENALI_CTL_266 +#define LPDDR4__NO_ZQ_INIT__FLD LPDDR4__DENALI_CTL_266__NO_ZQ_INIT + +#define LPDDR4__DENALI_CTL_266__ZQCS_ROTATE_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_266__ZQCS_ROTATE_SHIFT 24U +#define LPDDR4__DENALI_CTL_266__ZQCS_ROTATE_WIDTH 1U +#define LPDDR4__DENALI_CTL_266__ZQCS_ROTATE_WOCLR 0U +#define LPDDR4__DENALI_CTL_266__ZQCS_ROTATE_WOSET 0U +#define LPDDR4__ZQCS_ROTATE__REG DENALI_CTL_266 +#define LPDDR4__ZQCS_ROTATE__FLD LPDDR4__DENALI_CTL_266__ZQCS_ROTATE + +#define LPDDR4__DENALI_CTL_267_READ_MASK 0x03030303U +#define LPDDR4__DENALI_CTL_267_WRITE_MASK 0x03030303U +#define LPDDR4__DENALI_CTL_267__ZQ_CAL_START_MAP_0_MASK 0x00000003U +#define LPDDR4__DENALI_CTL_267__ZQ_CAL_START_MAP_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_267__ZQ_CAL_START_MAP_0_WIDTH 2U +#define LPDDR4__ZQ_CAL_START_MAP_0__REG DENALI_CTL_267 +#define LPDDR4__ZQ_CAL_START_MAP_0__FLD LPDDR4__DENALI_CTL_267__ZQ_CAL_START_MAP_0 + +#define LPDDR4__DENALI_CTL_267__ZQ_CAL_LATCH_MAP_0_MASK 0x00000300U +#define LPDDR4__DENALI_CTL_267__ZQ_CAL_LATCH_MAP_0_SHIFT 8U +#define LPDDR4__DENALI_CTL_267__ZQ_CAL_LATCH_MAP_0_WIDTH 2U +#define LPDDR4__ZQ_CAL_LATCH_MAP_0__REG DENALI_CTL_267 +#define LPDDR4__ZQ_CAL_LATCH_MAP_0__FLD LPDDR4__DENALI_CTL_267__ZQ_CAL_LATCH_MAP_0 + +#define LPDDR4__DENALI_CTL_267__ZQ_CAL_START_MAP_1_MASK 0x00030000U +#define LPDDR4__DENALI_CTL_267__ZQ_CAL_START_MAP_1_SHIFT 16U +#define LPDDR4__DENALI_CTL_267__ZQ_CAL_START_MAP_1_WIDTH 2U +#define LPDDR4__ZQ_CAL_START_MAP_1__REG DENALI_CTL_267 +#define LPDDR4__ZQ_CAL_START_MAP_1__FLD LPDDR4__DENALI_CTL_267__ZQ_CAL_START_MAP_1 + +#define LPDDR4__DENALI_CTL_267__ZQ_CAL_LATCH_MAP_1_MASK 0x03000000U +#define LPDDR4__DENALI_CTL_267__ZQ_CAL_LATCH_MAP_1_SHIFT 24U +#define LPDDR4__DENALI_CTL_267__ZQ_CAL_LATCH_MAP_1_WIDTH 2U +#define LPDDR4__ZQ_CAL_LATCH_MAP_1__REG DENALI_CTL_267 +#define LPDDR4__ZQ_CAL_LATCH_MAP_1__FLD LPDDR4__DENALI_CTL_267__ZQ_CAL_LATCH_MAP_1 + +#define LPDDR4__DENALI_CTL_268_READ_MASK 0x07070303U +#define LPDDR4__DENALI_CTL_268_WRITE_MASK 0x07070303U +#define LPDDR4__DENALI_CTL_268__BANK_DIFF_0_MASK 0x00000003U +#define LPDDR4__DENALI_CTL_268__BANK_DIFF_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_268__BANK_DIFF_0_WIDTH 2U +#define LPDDR4__BANK_DIFF_0__REG DENALI_CTL_268 +#define LPDDR4__BANK_DIFF_0__FLD LPDDR4__DENALI_CTL_268__BANK_DIFF_0 + +#define LPDDR4__DENALI_CTL_268__BANK_DIFF_1_MASK 0x00000300U +#define LPDDR4__DENALI_CTL_268__BANK_DIFF_1_SHIFT 8U +#define LPDDR4__DENALI_CTL_268__BANK_DIFF_1_WIDTH 2U +#define LPDDR4__BANK_DIFF_1__REG DENALI_CTL_268 +#define LPDDR4__BANK_DIFF_1__FLD LPDDR4__DENALI_CTL_268__BANK_DIFF_1 + +#define LPDDR4__DENALI_CTL_268__ROW_DIFF_0_MASK 0x00070000U +#define LPDDR4__DENALI_CTL_268__ROW_DIFF_0_SHIFT 16U +#define LPDDR4__DENALI_CTL_268__ROW_DIFF_0_WIDTH 3U +#define LPDDR4__ROW_DIFF_0__REG DENALI_CTL_268 +#define LPDDR4__ROW_DIFF_0__FLD LPDDR4__DENALI_CTL_268__ROW_DIFF_0 + +#define LPDDR4__DENALI_CTL_268__ROW_DIFF_1_MASK 0x07000000U +#define LPDDR4__DENALI_CTL_268__ROW_DIFF_1_SHIFT 24U +#define LPDDR4__DENALI_CTL_268__ROW_DIFF_1_WIDTH 3U +#define LPDDR4__ROW_DIFF_1__REG DENALI_CTL_268 +#define LPDDR4__ROW_DIFF_1__FLD LPDDR4__DENALI_CTL_268__ROW_DIFF_1 + +#define LPDDR4__DENALI_CTL_269_READ_MASK 0xFFFF0F0FU +#define LPDDR4__DENALI_CTL_269_WRITE_MASK 0xFFFF0F0FU +#define LPDDR4__DENALI_CTL_269__COL_DIFF_0_MASK 0x0000000FU +#define LPDDR4__DENALI_CTL_269__COL_DIFF_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_269__COL_DIFF_0_WIDTH 4U +#define LPDDR4__COL_DIFF_0__REG DENALI_CTL_269 +#define LPDDR4__COL_DIFF_0__FLD LPDDR4__DENALI_CTL_269__COL_DIFF_0 + +#define LPDDR4__DENALI_CTL_269__COL_DIFF_1_MASK 0x00000F00U +#define LPDDR4__DENALI_CTL_269__COL_DIFF_1_SHIFT 8U +#define LPDDR4__DENALI_CTL_269__COL_DIFF_1_WIDTH 4U +#define LPDDR4__COL_DIFF_1__REG DENALI_CTL_269 +#define LPDDR4__COL_DIFF_1__FLD LPDDR4__DENALI_CTL_269__COL_DIFF_1 + +#define LPDDR4__DENALI_CTL_269__CS_VAL_LOWER_0_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_269__CS_VAL_LOWER_0_SHIFT 16U +#define LPDDR4__DENALI_CTL_269__CS_VAL_LOWER_0_WIDTH 16U +#define LPDDR4__CS_VAL_LOWER_0__REG DENALI_CTL_269 +#define LPDDR4__CS_VAL_LOWER_0__FLD LPDDR4__DENALI_CTL_269__CS_VAL_LOWER_0 + +#define LPDDR4__DENALI_CTL_270_READ_MASK 0x0007FFFFU +#define LPDDR4__DENALI_CTL_270_WRITE_MASK 0x0007FFFFU +#define LPDDR4__DENALI_CTL_270__CS_VAL_UPPER_0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_270__CS_VAL_UPPER_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_270__CS_VAL_UPPER_0_WIDTH 16U +#define LPDDR4__CS_VAL_UPPER_0__REG DENALI_CTL_270 +#define LPDDR4__CS_VAL_UPPER_0__FLD LPDDR4__DENALI_CTL_270__CS_VAL_UPPER_0 + +#define LPDDR4__DENALI_CTL_270__ROW_START_VAL_0_MASK 0x00070000U +#define LPDDR4__DENALI_CTL_270__ROW_START_VAL_0_SHIFT 16U +#define LPDDR4__DENALI_CTL_270__ROW_START_VAL_0_WIDTH 3U +#define LPDDR4__ROW_START_VAL_0__REG DENALI_CTL_270 +#define LPDDR4__ROW_START_VAL_0__FLD LPDDR4__DENALI_CTL_270__ROW_START_VAL_0 + +#define LPDDR4__DENALI_CTL_271_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_271_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_271__CS_VAL_LOWER_1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_271__CS_VAL_LOWER_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_271__CS_VAL_LOWER_1_WIDTH 16U +#define LPDDR4__CS_VAL_LOWER_1__REG DENALI_CTL_271 +#define LPDDR4__CS_VAL_LOWER_1__FLD LPDDR4__DENALI_CTL_271__CS_VAL_LOWER_1 + +#define LPDDR4__DENALI_CTL_271__CS_VAL_UPPER_1_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_271__CS_VAL_UPPER_1_SHIFT 16U +#define LPDDR4__DENALI_CTL_271__CS_VAL_UPPER_1_WIDTH 16U +#define LPDDR4__CS_VAL_UPPER_1__REG DENALI_CTL_271 +#define LPDDR4__CS_VAL_UPPER_1__FLD LPDDR4__DENALI_CTL_271__CS_VAL_UPPER_1 + +#define LPDDR4__DENALI_CTL_272_READ_MASK 0xFFFF0307U +#define LPDDR4__DENALI_CTL_272_WRITE_MASK 0xFFFF0307U +#define LPDDR4__DENALI_CTL_272__ROW_START_VAL_1_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_272__ROW_START_VAL_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_272__ROW_START_VAL_1_WIDTH 3U +#define LPDDR4__ROW_START_VAL_1__REG DENALI_CTL_272 +#define LPDDR4__ROW_START_VAL_1__FLD LPDDR4__DENALI_CTL_272__ROW_START_VAL_1 + +#define LPDDR4__DENALI_CTL_272__CS_MAP_NON_POW2_MASK 0x00000300U +#define LPDDR4__DENALI_CTL_272__CS_MAP_NON_POW2_SHIFT 8U +#define LPDDR4__DENALI_CTL_272__CS_MAP_NON_POW2_WIDTH 2U +#define LPDDR4__CS_MAP_NON_POW2__REG DENALI_CTL_272 +#define LPDDR4__CS_MAP_NON_POW2__FLD LPDDR4__DENALI_CTL_272__CS_MAP_NON_POW2 + +#define LPDDR4__DENALI_CTL_272__CS_MSK_0_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_272__CS_MSK_0_SHIFT 16U +#define LPDDR4__DENALI_CTL_272__CS_MSK_0_WIDTH 16U +#define LPDDR4__CS_MSK_0__REG DENALI_CTL_272 +#define LPDDR4__CS_MSK_0__FLD LPDDR4__DENALI_CTL_272__CS_MSK_0 + +#define LPDDR4__DENALI_CTL_273_READ_MASK 0x1F01FFFFU +#define LPDDR4__DENALI_CTL_273_WRITE_MASK 0x1F01FFFFU +#define LPDDR4__DENALI_CTL_273__CS_MSK_1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_273__CS_MSK_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_273__CS_MSK_1_WIDTH 16U +#define LPDDR4__CS_MSK_1__REG DENALI_CTL_273 +#define LPDDR4__CS_MSK_1__FLD LPDDR4__DENALI_CTL_273__CS_MSK_1 + +#define LPDDR4__DENALI_CTL_273__CS_LOWER_ADDR_EN_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_273__CS_LOWER_ADDR_EN_SHIFT 16U +#define LPDDR4__DENALI_CTL_273__CS_LOWER_ADDR_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_273__CS_LOWER_ADDR_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_273__CS_LOWER_ADDR_EN_WOSET 0U +#define LPDDR4__CS_LOWER_ADDR_EN__REG DENALI_CTL_273 +#define LPDDR4__CS_LOWER_ADDR_EN__FLD LPDDR4__DENALI_CTL_273__CS_LOWER_ADDR_EN + +#define LPDDR4__DENALI_CTL_273__MC_RESERVED24_MASK 0x1F000000U +#define LPDDR4__DENALI_CTL_273__MC_RESERVED24_SHIFT 24U +#define LPDDR4__DENALI_CTL_273__MC_RESERVED24_WIDTH 5U +#define LPDDR4__MC_RESERVED24__REG DENALI_CTL_273 +#define LPDDR4__MC_RESERVED24__FLD LPDDR4__DENALI_CTL_273__MC_RESERVED24 + +#define LPDDR4__DENALI_CTL_274_READ_MASK 0xFFFF1F01U +#define LPDDR4__DENALI_CTL_274_WRITE_MASK 0xFFFF1F01U +#define LPDDR4__DENALI_CTL_274__MC_RESERVED25_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_274__MC_RESERVED25_SHIFT 0U +#define LPDDR4__DENALI_CTL_274__MC_RESERVED25_WIDTH 1U +#define LPDDR4__DENALI_CTL_274__MC_RESERVED25_WOCLR 0U +#define LPDDR4__DENALI_CTL_274__MC_RESERVED25_WOSET 0U +#define LPDDR4__MC_RESERVED25__REG DENALI_CTL_274 +#define LPDDR4__MC_RESERVED25__FLD LPDDR4__DENALI_CTL_274__MC_RESERVED25 + +#define LPDDR4__DENALI_CTL_274__APREBIT_MASK 0x00001F00U +#define LPDDR4__DENALI_CTL_274__APREBIT_SHIFT 8U +#define LPDDR4__DENALI_CTL_274__APREBIT_WIDTH 5U +#define LPDDR4__APREBIT__REG DENALI_CTL_274 +#define LPDDR4__APREBIT__FLD LPDDR4__DENALI_CTL_274__APREBIT + +#define LPDDR4__DENALI_CTL_274__AGE_COUNT_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_274__AGE_COUNT_SHIFT 16U +#define LPDDR4__DENALI_CTL_274__AGE_COUNT_WIDTH 8U +#define LPDDR4__AGE_COUNT__REG DENALI_CTL_274 +#define LPDDR4__AGE_COUNT__FLD LPDDR4__DENALI_CTL_274__AGE_COUNT + +#define LPDDR4__DENALI_CTL_274__COMMAND_AGE_COUNT_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_274__COMMAND_AGE_COUNT_SHIFT 24U +#define LPDDR4__DENALI_CTL_274__COMMAND_AGE_COUNT_WIDTH 8U +#define LPDDR4__COMMAND_AGE_COUNT__REG DENALI_CTL_274 +#define LPDDR4__COMMAND_AGE_COUNT__FLD LPDDR4__DENALI_CTL_274__COMMAND_AGE_COUNT + +#define LPDDR4__DENALI_CTL_275_READ_MASK 0x01010101U +#define LPDDR4__DENALI_CTL_275_WRITE_MASK 0x01010101U +#define LPDDR4__DENALI_CTL_275__ADDR_CMP_EN_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_275__ADDR_CMP_EN_SHIFT 0U +#define LPDDR4__DENALI_CTL_275__ADDR_CMP_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_275__ADDR_CMP_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_275__ADDR_CMP_EN_WOSET 0U +#define LPDDR4__ADDR_CMP_EN__REG DENALI_CTL_275 +#define LPDDR4__ADDR_CMP_EN__FLD LPDDR4__DENALI_CTL_275__ADDR_CMP_EN + +#define LPDDR4__DENALI_CTL_275__ADDR_COLLISION_MPM_DIS_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_275__ADDR_COLLISION_MPM_DIS_SHIFT 8U +#define LPDDR4__DENALI_CTL_275__ADDR_COLLISION_MPM_DIS_WIDTH 1U +#define LPDDR4__DENALI_CTL_275__ADDR_COLLISION_MPM_DIS_WOCLR 0U +#define LPDDR4__DENALI_CTL_275__ADDR_COLLISION_MPM_DIS_WOSET 0U +#define LPDDR4__ADDR_COLLISION_MPM_DIS__REG DENALI_CTL_275 +#define LPDDR4__ADDR_COLLISION_MPM_DIS__FLD LPDDR4__DENALI_CTL_275__ADDR_COLLISION_MPM_DIS + +#define LPDDR4__DENALI_CTL_275__BANK_SPLIT_EN_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_275__BANK_SPLIT_EN_SHIFT 16U +#define LPDDR4__DENALI_CTL_275__BANK_SPLIT_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_275__BANK_SPLIT_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_275__BANK_SPLIT_EN_WOSET 0U +#define LPDDR4__BANK_SPLIT_EN__REG DENALI_CTL_275 +#define LPDDR4__BANK_SPLIT_EN__FLD LPDDR4__DENALI_CTL_275__BANK_SPLIT_EN + +#define LPDDR4__DENALI_CTL_275__PLACEMENT_EN_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_275__PLACEMENT_EN_SHIFT 24U +#define LPDDR4__DENALI_CTL_275__PLACEMENT_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_275__PLACEMENT_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_275__PLACEMENT_EN_WOSET 0U +#define LPDDR4__PLACEMENT_EN__REG DENALI_CTL_275 +#define LPDDR4__PLACEMENT_EN__FLD LPDDR4__DENALI_CTL_275__PLACEMENT_EN + +#define LPDDR4__DENALI_CTL_276_READ_MASK 0x01010101U +#define LPDDR4__DENALI_CTL_276_WRITE_MASK 0x01010101U +#define LPDDR4__DENALI_CTL_276__PRIORITY_EN_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_276__PRIORITY_EN_SHIFT 0U +#define LPDDR4__DENALI_CTL_276__PRIORITY_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_276__PRIORITY_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_276__PRIORITY_EN_WOSET 0U +#define LPDDR4__PRIORITY_EN__REG DENALI_CTL_276 +#define LPDDR4__PRIORITY_EN__FLD LPDDR4__DENALI_CTL_276__PRIORITY_EN + +#define LPDDR4__DENALI_CTL_276__RW_SAME_EN_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_276__RW_SAME_EN_SHIFT 8U +#define LPDDR4__DENALI_CTL_276__RW_SAME_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_276__RW_SAME_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_276__RW_SAME_EN_WOSET 0U +#define LPDDR4__RW_SAME_EN__REG DENALI_CTL_276 +#define LPDDR4__RW_SAME_EN__FLD LPDDR4__DENALI_CTL_276__RW_SAME_EN + +#define LPDDR4__DENALI_CTL_276__RW_SAME_PAGE_EN_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_276__RW_SAME_PAGE_EN_SHIFT 16U +#define LPDDR4__DENALI_CTL_276__RW_SAME_PAGE_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_276__RW_SAME_PAGE_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_276__RW_SAME_PAGE_EN_WOSET 0U +#define LPDDR4__RW_SAME_PAGE_EN__REG DENALI_CTL_276 +#define LPDDR4__RW_SAME_PAGE_EN__FLD LPDDR4__DENALI_CTL_276__RW_SAME_PAGE_EN + +#define LPDDR4__DENALI_CTL_276__CS_SAME_EN_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_276__CS_SAME_EN_SHIFT 24U +#define LPDDR4__DENALI_CTL_276__CS_SAME_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_276__CS_SAME_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_276__CS_SAME_EN_WOSET 0U +#define LPDDR4__CS_SAME_EN__REG DENALI_CTL_276 +#define LPDDR4__CS_SAME_EN__FLD LPDDR4__DENALI_CTL_276__CS_SAME_EN + +#define LPDDR4__DENALI_CTL_277_READ_MASK 0x011F0301U +#define LPDDR4__DENALI_CTL_277_WRITE_MASK 0x011F0301U +#define LPDDR4__DENALI_CTL_277__W2R_SPLIT_EN_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_277__W2R_SPLIT_EN_SHIFT 0U +#define LPDDR4__DENALI_CTL_277__W2R_SPLIT_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_277__W2R_SPLIT_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_277__W2R_SPLIT_EN_WOSET 0U +#define LPDDR4__W2R_SPLIT_EN__REG DENALI_CTL_277 +#define LPDDR4__W2R_SPLIT_EN__FLD LPDDR4__DENALI_CTL_277__W2R_SPLIT_EN + +#define LPDDR4__DENALI_CTL_277__DISABLE_RW_GROUP_W_BNK_CONFLICT_MASK 0x00000300U +#define LPDDR4__DENALI_CTL_277__DISABLE_RW_GROUP_W_BNK_CONFLICT_SHIFT 8U +#define LPDDR4__DENALI_CTL_277__DISABLE_RW_GROUP_W_BNK_CONFLICT_WIDTH 2U +#define LPDDR4__DISABLE_RW_GROUP_W_BNK_CONFLICT__REG DENALI_CTL_277 +#define LPDDR4__DISABLE_RW_GROUP_W_BNK_CONFLICT__FLD LPDDR4__DENALI_CTL_277__DISABLE_RW_GROUP_W_BNK_CONFLICT + +#define LPDDR4__DENALI_CTL_277__NUM_Q_ENTRIES_ACT_DISABLE_MASK 0x001F0000U +#define LPDDR4__DENALI_CTL_277__NUM_Q_ENTRIES_ACT_DISABLE_SHIFT 16U +#define LPDDR4__DENALI_CTL_277__NUM_Q_ENTRIES_ACT_DISABLE_WIDTH 5U +#define LPDDR4__NUM_Q_ENTRIES_ACT_DISABLE__REG DENALI_CTL_277 +#define LPDDR4__NUM_Q_ENTRIES_ACT_DISABLE__FLD LPDDR4__DENALI_CTL_277__NUM_Q_ENTRIES_ACT_DISABLE + +#define LPDDR4__DENALI_CTL_277__SWAP_EN_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_277__SWAP_EN_SHIFT 24U +#define LPDDR4__DENALI_CTL_277__SWAP_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_277__SWAP_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_277__SWAP_EN_WOSET 0U +#define LPDDR4__SWAP_EN__REG DENALI_CTL_277 +#define LPDDR4__SWAP_EN__FLD LPDDR4__DENALI_CTL_277__SWAP_EN + +#define LPDDR4__DENALI_CTL_278_READ_MASK 0x01030301U +#define LPDDR4__DENALI_CTL_278_WRITE_MASK 0x01030301U +#define LPDDR4__DENALI_CTL_278__DISABLE_RD_INTERLEAVE_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_278__DISABLE_RD_INTERLEAVE_SHIFT 0U +#define LPDDR4__DENALI_CTL_278__DISABLE_RD_INTERLEAVE_WIDTH 1U +#define LPDDR4__DENALI_CTL_278__DISABLE_RD_INTERLEAVE_WOCLR 0U +#define LPDDR4__DENALI_CTL_278__DISABLE_RD_INTERLEAVE_WOSET 0U +#define LPDDR4__DISABLE_RD_INTERLEAVE__REG DENALI_CTL_278 +#define LPDDR4__DISABLE_RD_INTERLEAVE__FLD LPDDR4__DENALI_CTL_278__DISABLE_RD_INTERLEAVE + +#define LPDDR4__DENALI_CTL_278__INHIBIT_DRAM_CMD_MASK 0x00000300U +#define LPDDR4__DENALI_CTL_278__INHIBIT_DRAM_CMD_SHIFT 8U +#define LPDDR4__DENALI_CTL_278__INHIBIT_DRAM_CMD_WIDTH 2U +#define LPDDR4__INHIBIT_DRAM_CMD__REG DENALI_CTL_278 +#define LPDDR4__INHIBIT_DRAM_CMD__FLD LPDDR4__DENALI_CTL_278__INHIBIT_DRAM_CMD + +#define LPDDR4__DENALI_CTL_278__CS_MAP_MASK 0x00030000U +#define LPDDR4__DENALI_CTL_278__CS_MAP_SHIFT 16U +#define LPDDR4__DENALI_CTL_278__CS_MAP_WIDTH 2U +#define LPDDR4__CS_MAP__REG DENALI_CTL_278 +#define LPDDR4__CS_MAP__FLD LPDDR4__DENALI_CTL_278__CS_MAP + +#define LPDDR4__DENALI_CTL_278__REDUC_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_278__REDUC_SHIFT 24U +#define LPDDR4__DENALI_CTL_278__REDUC_WIDTH 1U +#define LPDDR4__DENALI_CTL_278__REDUC_WOCLR 0U +#define LPDDR4__DENALI_CTL_278__REDUC_WOSET 0U +#define LPDDR4__REDUC__REG DENALI_CTL_278 +#define LPDDR4__REDUC__FLD LPDDR4__DENALI_CTL_278__REDUC + +#define LPDDR4__DENALI_CTL_279_READ_MASK 0x0003FFFFU +#define LPDDR4__DENALI_CTL_279_WRITE_MASK 0x0003FFFFU +#define LPDDR4__DENALI_CTL_279__FAULT_FIFO_PROTECTION_EN_MASK 0x0003FFFFU +#define LPDDR4__DENALI_CTL_279__FAULT_FIFO_PROTECTION_EN_SHIFT 0U +#define LPDDR4__DENALI_CTL_279__FAULT_FIFO_PROTECTION_EN_WIDTH 18U +#define LPDDR4__FAULT_FIFO_PROTECTION_EN__REG DENALI_CTL_279 +#define LPDDR4__FAULT_FIFO_PROTECTION_EN__FLD LPDDR4__DENALI_CTL_279__FAULT_FIFO_PROTECTION_EN + +#define LPDDR4__DENALI_CTL_280_READ_MASK 0x0003FFFFU +#define LPDDR4__DENALI_CTL_280_WRITE_MASK 0x0003FFFFU +#define LPDDR4__DENALI_CTL_280__FAULT_FIFO_PROTECTION_STATUS_MASK 0x0003FFFFU +#define LPDDR4__DENALI_CTL_280__FAULT_FIFO_PROTECTION_STATUS_SHIFT 0U +#define LPDDR4__DENALI_CTL_280__FAULT_FIFO_PROTECTION_STATUS_WIDTH 18U +#define LPDDR4__FAULT_FIFO_PROTECTION_STATUS__REG DENALI_CTL_280 +#define LPDDR4__FAULT_FIFO_PROTECTION_STATUS__FLD LPDDR4__DENALI_CTL_280__FAULT_FIFO_PROTECTION_STATUS + +#define LPDDR4__DENALI_CTL_281_READ_MASK 0x0103FFFFU +#define LPDDR4__DENALI_CTL_281_WRITE_MASK 0x0103FFFFU +#define LPDDR4__DENALI_CTL_281__FAULT_FIFO_PROTECTION_INJECTION_EN_MASK 0x0003FFFFU +#define LPDDR4__DENALI_CTL_281__FAULT_FIFO_PROTECTION_INJECTION_EN_SHIFT 0U +#define LPDDR4__DENALI_CTL_281__FAULT_FIFO_PROTECTION_INJECTION_EN_WIDTH 18U +#define LPDDR4__FAULT_FIFO_PROTECTION_INJECTION_EN__REG DENALI_CTL_281 +#define LPDDR4__FAULT_FIFO_PROTECTION_INJECTION_EN__FLD LPDDR4__DENALI_CTL_281__FAULT_FIFO_PROTECTION_INJECTION_EN + +#define LPDDR4__DENALI_CTL_281__WRITE_ADDR_CHAN_PARITY_EN_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_281__WRITE_ADDR_CHAN_PARITY_EN_SHIFT 24U +#define LPDDR4__DENALI_CTL_281__WRITE_ADDR_CHAN_PARITY_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_281__WRITE_ADDR_CHAN_PARITY_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_281__WRITE_ADDR_CHAN_PARITY_EN_WOSET 0U +#define LPDDR4__WRITE_ADDR_CHAN_PARITY_EN__REG DENALI_CTL_281 +#define LPDDR4__WRITE_ADDR_CHAN_PARITY_EN__FLD LPDDR4__DENALI_CTL_281__WRITE_ADDR_CHAN_PARITY_EN + +#define LPDDR4__DENALI_CTL_282_READ_MASK 0x01010103U +#define LPDDR4__DENALI_CTL_282_WRITE_MASK 0x01010103U +#define LPDDR4__DENALI_CTL_282__WRITE_DATA_CHAN_PARITY_EN_MASK 0x00000003U +#define LPDDR4__DENALI_CTL_282__WRITE_DATA_CHAN_PARITY_EN_SHIFT 0U +#define LPDDR4__DENALI_CTL_282__WRITE_DATA_CHAN_PARITY_EN_WIDTH 2U +#define LPDDR4__WRITE_DATA_CHAN_PARITY_EN__REG DENALI_CTL_282 +#define LPDDR4__WRITE_DATA_CHAN_PARITY_EN__FLD LPDDR4__DENALI_CTL_282__WRITE_DATA_CHAN_PARITY_EN + +#define LPDDR4__DENALI_CTL_282__WRITE_RESP_CHAN_PARITY_EN_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_282__WRITE_RESP_CHAN_PARITY_EN_SHIFT 8U +#define LPDDR4__DENALI_CTL_282__WRITE_RESP_CHAN_PARITY_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_282__WRITE_RESP_CHAN_PARITY_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_282__WRITE_RESP_CHAN_PARITY_EN_WOSET 0U +#define LPDDR4__WRITE_RESP_CHAN_PARITY_EN__REG DENALI_CTL_282 +#define LPDDR4__WRITE_RESP_CHAN_PARITY_EN__FLD LPDDR4__DENALI_CTL_282__WRITE_RESP_CHAN_PARITY_EN + +#define LPDDR4__DENALI_CTL_282__READ_ADDR_CHAN_PARITY_EN_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_282__READ_ADDR_CHAN_PARITY_EN_SHIFT 16U +#define LPDDR4__DENALI_CTL_282__READ_ADDR_CHAN_PARITY_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_282__READ_ADDR_CHAN_PARITY_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_282__READ_ADDR_CHAN_PARITY_EN_WOSET 0U +#define LPDDR4__READ_ADDR_CHAN_PARITY_EN__REG DENALI_CTL_282 +#define LPDDR4__READ_ADDR_CHAN_PARITY_EN__FLD LPDDR4__DENALI_CTL_282__READ_ADDR_CHAN_PARITY_EN + +#define LPDDR4__DENALI_CTL_282__READ_DATA_CHAN_PARITY_EN_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_282__READ_DATA_CHAN_PARITY_EN_SHIFT 24U +#define LPDDR4__DENALI_CTL_282__READ_DATA_CHAN_PARITY_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_282__READ_DATA_CHAN_PARITY_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_282__READ_DATA_CHAN_PARITY_EN_WOSET 0U +#define LPDDR4__READ_DATA_CHAN_PARITY_EN__REG DENALI_CTL_282 +#define LPDDR4__READ_DATA_CHAN_PARITY_EN__FLD LPDDR4__DENALI_CTL_282__READ_DATA_CHAN_PARITY_EN + +#define LPDDR4__DENALI_CTL_283_READ_MASK 0x01010101U +#define LPDDR4__DENALI_CTL_283_WRITE_MASK 0x01010101U +#define LPDDR4__DENALI_CTL_283__MC_RESERVED26_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_283__MC_RESERVED26_SHIFT 0U +#define LPDDR4__DENALI_CTL_283__MC_RESERVED26_WIDTH 1U +#define LPDDR4__DENALI_CTL_283__MC_RESERVED26_WOCLR 0U +#define LPDDR4__DENALI_CTL_283__MC_RESERVED26_WOSET 0U +#define LPDDR4__MC_RESERVED26__REG DENALI_CTL_283 +#define LPDDR4__MC_RESERVED26__FLD LPDDR4__DENALI_CTL_283__MC_RESERVED26 + +#define LPDDR4__DENALI_CTL_283__MC_RESERVED27_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_283__MC_RESERVED27_SHIFT 8U +#define LPDDR4__DENALI_CTL_283__MC_RESERVED27_WIDTH 1U +#define LPDDR4__DENALI_CTL_283__MC_RESERVED27_WOCLR 0U +#define LPDDR4__DENALI_CTL_283__MC_RESERVED27_WOSET 0U +#define LPDDR4__MC_RESERVED27__REG DENALI_CTL_283 +#define LPDDR4__MC_RESERVED27__FLD LPDDR4__DENALI_CTL_283__MC_RESERVED27 + +#define LPDDR4__DENALI_CTL_283__WRITE_PARITY_ERR_BRESP_EN_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_283__WRITE_PARITY_ERR_BRESP_EN_SHIFT 16U +#define LPDDR4__DENALI_CTL_283__WRITE_PARITY_ERR_BRESP_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_283__WRITE_PARITY_ERR_BRESP_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_283__WRITE_PARITY_ERR_BRESP_EN_WOSET 0U +#define LPDDR4__WRITE_PARITY_ERR_BRESP_EN__REG DENALI_CTL_283 +#define LPDDR4__WRITE_PARITY_ERR_BRESP_EN__FLD LPDDR4__DENALI_CTL_283__WRITE_PARITY_ERR_BRESP_EN + +#define LPDDR4__DENALI_CTL_283__READ_PARITY_ERR_RRESP_EN_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_283__READ_PARITY_ERR_RRESP_EN_SHIFT 24U +#define LPDDR4__DENALI_CTL_283__READ_PARITY_ERR_RRESP_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_283__READ_PARITY_ERR_RRESP_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_283__READ_PARITY_ERR_RRESP_EN_WOSET 0U +#define LPDDR4__READ_PARITY_ERR_RRESP_EN__REG DENALI_CTL_283 +#define LPDDR4__READ_PARITY_ERR_RRESP_EN__FLD LPDDR4__DENALI_CTL_283__READ_PARITY_ERR_RRESP_EN + +#define LPDDR4__DENALI_CTL_284_READ_MASK 0x01010101U +#define LPDDR4__DENALI_CTL_284_WRITE_MASK 0x01010101U +#define LPDDR4__DENALI_CTL_284__WRITE_ADDR_CHAN_TRIGGER_PARITY_EN_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_284__WRITE_ADDR_CHAN_TRIGGER_PARITY_EN_SHIFT 0U +#define LPDDR4__DENALI_CTL_284__WRITE_ADDR_CHAN_TRIGGER_PARITY_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_284__WRITE_ADDR_CHAN_TRIGGER_PARITY_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_284__WRITE_ADDR_CHAN_TRIGGER_PARITY_EN_WOSET 0U +#define LPDDR4__WRITE_ADDR_CHAN_TRIGGER_PARITY_EN__REG DENALI_CTL_284 +#define LPDDR4__WRITE_ADDR_CHAN_TRIGGER_PARITY_EN__FLD LPDDR4__DENALI_CTL_284__WRITE_ADDR_CHAN_TRIGGER_PARITY_EN + +#define LPDDR4__DENALI_CTL_284__WRITE_DATA_CHAN_TRIGGER_PARITY_EN_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_284__WRITE_DATA_CHAN_TRIGGER_PARITY_EN_SHIFT 8U +#define LPDDR4__DENALI_CTL_284__WRITE_DATA_CHAN_TRIGGER_PARITY_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_284__WRITE_DATA_CHAN_TRIGGER_PARITY_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_284__WRITE_DATA_CHAN_TRIGGER_PARITY_EN_WOSET 0U +#define LPDDR4__WRITE_DATA_CHAN_TRIGGER_PARITY_EN__REG DENALI_CTL_284 +#define LPDDR4__WRITE_DATA_CHAN_TRIGGER_PARITY_EN__FLD LPDDR4__DENALI_CTL_284__WRITE_DATA_CHAN_TRIGGER_PARITY_EN + +#define LPDDR4__DENALI_CTL_284__WRITE_RESP_CHAN_CORRUPT_PARITY_EN_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_284__WRITE_RESP_CHAN_CORRUPT_PARITY_EN_SHIFT 16U +#define LPDDR4__DENALI_CTL_284__WRITE_RESP_CHAN_CORRUPT_PARITY_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_284__WRITE_RESP_CHAN_CORRUPT_PARITY_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_284__WRITE_RESP_CHAN_CORRUPT_PARITY_EN_WOSET 0U +#define LPDDR4__WRITE_RESP_CHAN_CORRUPT_PARITY_EN__REG DENALI_CTL_284 +#define LPDDR4__WRITE_RESP_CHAN_CORRUPT_PARITY_EN__FLD LPDDR4__DENALI_CTL_284__WRITE_RESP_CHAN_CORRUPT_PARITY_EN + +#define LPDDR4__DENALI_CTL_284__READ_ADDR_CHAN_TRIGGER_PARITY_EN_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_284__READ_ADDR_CHAN_TRIGGER_PARITY_EN_SHIFT 24U +#define LPDDR4__DENALI_CTL_284__READ_ADDR_CHAN_TRIGGER_PARITY_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_284__READ_ADDR_CHAN_TRIGGER_PARITY_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_284__READ_ADDR_CHAN_TRIGGER_PARITY_EN_WOSET 0U +#define LPDDR4__READ_ADDR_CHAN_TRIGGER_PARITY_EN__REG DENALI_CTL_284 +#define LPDDR4__READ_ADDR_CHAN_TRIGGER_PARITY_EN__FLD LPDDR4__DENALI_CTL_284__READ_ADDR_CHAN_TRIGGER_PARITY_EN + +#define LPDDR4__DENALI_CTL_285_READ_MASK 0x01010101U +#define LPDDR4__DENALI_CTL_285_WRITE_MASK 0x01010101U +#define LPDDR4__DENALI_CTL_285__READ_DATA_CHAN_CORRUPT_PARITY_EN_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_285__READ_DATA_CHAN_CORRUPT_PARITY_EN_SHIFT 0U +#define LPDDR4__DENALI_CTL_285__READ_DATA_CHAN_CORRUPT_PARITY_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_285__READ_DATA_CHAN_CORRUPT_PARITY_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_285__READ_DATA_CHAN_CORRUPT_PARITY_EN_WOSET 0U +#define LPDDR4__READ_DATA_CHAN_CORRUPT_PARITY_EN__REG DENALI_CTL_285 +#define LPDDR4__READ_DATA_CHAN_CORRUPT_PARITY_EN__FLD LPDDR4__DENALI_CTL_285__READ_DATA_CHAN_CORRUPT_PARITY_EN + +#define LPDDR4__DENALI_CTL_285__ECC_AXI_ERROR_RESPONSE_INHIBIT_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_285__ECC_AXI_ERROR_RESPONSE_INHIBIT_SHIFT 8U +#define LPDDR4__DENALI_CTL_285__ECC_AXI_ERROR_RESPONSE_INHIBIT_WIDTH 1U +#define LPDDR4__DENALI_CTL_285__ECC_AXI_ERROR_RESPONSE_INHIBIT_WOCLR 0U +#define LPDDR4__DENALI_CTL_285__ECC_AXI_ERROR_RESPONSE_INHIBIT_WOSET 0U +#define LPDDR4__ECC_AXI_ERROR_RESPONSE_INHIBIT__REG DENALI_CTL_285 +#define LPDDR4__ECC_AXI_ERROR_RESPONSE_INHIBIT__FLD LPDDR4__DENALI_CTL_285__ECC_AXI_ERROR_RESPONSE_INHIBIT + +#define LPDDR4__DENALI_CTL_285__WRITE_PARITY_ERR_CORRUPT_ECC_EN_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_285__WRITE_PARITY_ERR_CORRUPT_ECC_EN_SHIFT 16U +#define LPDDR4__DENALI_CTL_285__WRITE_PARITY_ERR_CORRUPT_ECC_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_285__WRITE_PARITY_ERR_CORRUPT_ECC_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_285__WRITE_PARITY_ERR_CORRUPT_ECC_EN_WOSET 0U +#define LPDDR4__WRITE_PARITY_ERR_CORRUPT_ECC_EN__REG DENALI_CTL_285 +#define LPDDR4__WRITE_PARITY_ERR_CORRUPT_ECC_EN__FLD LPDDR4__DENALI_CTL_285__WRITE_PARITY_ERR_CORRUPT_ECC_EN + +#define LPDDR4__DENALI_CTL_285__ENHANCED_PARITY_PROTECTION_EN_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_285__ENHANCED_PARITY_PROTECTION_EN_SHIFT 24U +#define LPDDR4__DENALI_CTL_285__ENHANCED_PARITY_PROTECTION_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_285__ENHANCED_PARITY_PROTECTION_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_285__ENHANCED_PARITY_PROTECTION_EN_WOSET 0U +#define LPDDR4__ENHANCED_PARITY_PROTECTION_EN__REG DENALI_CTL_285 +#define LPDDR4__ENHANCED_PARITY_PROTECTION_EN__FLD LPDDR4__DENALI_CTL_285__ENHANCED_PARITY_PROTECTION_EN + +#define LPDDR4__DENALI_CTL_286_READ_MASK 0x0F0F0F07U +#define LPDDR4__DENALI_CTL_286_WRITE_MASK 0x0F0F0F07U +#define LPDDR4__DENALI_CTL_286__MEMDATA_RATIO_0_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_286__MEMDATA_RATIO_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_286__MEMDATA_RATIO_0_WIDTH 3U +#define LPDDR4__MEMDATA_RATIO_0__REG DENALI_CTL_286 +#define LPDDR4__MEMDATA_RATIO_0__FLD LPDDR4__DENALI_CTL_286__MEMDATA_RATIO_0 + +#define LPDDR4__DENALI_CTL_286__DEVICE0_BYTE0_CS0_MASK 0x00000F00U +#define LPDDR4__DENALI_CTL_286__DEVICE0_BYTE0_CS0_SHIFT 8U +#define LPDDR4__DENALI_CTL_286__DEVICE0_BYTE0_CS0_WIDTH 4U +#define LPDDR4__DEVICE0_BYTE0_CS0__REG DENALI_CTL_286 +#define LPDDR4__DEVICE0_BYTE0_CS0__FLD LPDDR4__DENALI_CTL_286__DEVICE0_BYTE0_CS0 + +#define LPDDR4__DENALI_CTL_286__DEVICE1_BYTE0_CS0_MASK 0x000F0000U +#define LPDDR4__DENALI_CTL_286__DEVICE1_BYTE0_CS0_SHIFT 16U +#define LPDDR4__DENALI_CTL_286__DEVICE1_BYTE0_CS0_WIDTH 4U +#define LPDDR4__DEVICE1_BYTE0_CS0__REG DENALI_CTL_286 +#define LPDDR4__DEVICE1_BYTE0_CS0__FLD LPDDR4__DENALI_CTL_286__DEVICE1_BYTE0_CS0 + +#define LPDDR4__DENALI_CTL_286__DEVICE2_BYTE0_CS0_MASK 0x0F000000U +#define LPDDR4__DENALI_CTL_286__DEVICE2_BYTE0_CS0_SHIFT 24U +#define LPDDR4__DENALI_CTL_286__DEVICE2_BYTE0_CS0_WIDTH 4U +#define LPDDR4__DEVICE2_BYTE0_CS0__REG DENALI_CTL_286 +#define LPDDR4__DEVICE2_BYTE0_CS0__FLD LPDDR4__DENALI_CTL_286__DEVICE2_BYTE0_CS0 + +#define LPDDR4__DENALI_CTL_287_READ_MASK 0x0F0F070FU +#define LPDDR4__DENALI_CTL_287_WRITE_MASK 0x0F0F070FU +#define LPDDR4__DENALI_CTL_287__DEVICE3_BYTE0_CS0_MASK 0x0000000FU +#define LPDDR4__DENALI_CTL_287__DEVICE3_BYTE0_CS0_SHIFT 0U +#define LPDDR4__DENALI_CTL_287__DEVICE3_BYTE0_CS0_WIDTH 4U +#define LPDDR4__DEVICE3_BYTE0_CS0__REG DENALI_CTL_287 +#define LPDDR4__DEVICE3_BYTE0_CS0__FLD LPDDR4__DENALI_CTL_287__DEVICE3_BYTE0_CS0 + +#define LPDDR4__DENALI_CTL_287__MEMDATA_RATIO_1_MASK 0x00000700U +#define LPDDR4__DENALI_CTL_287__MEMDATA_RATIO_1_SHIFT 8U +#define LPDDR4__DENALI_CTL_287__MEMDATA_RATIO_1_WIDTH 3U +#define LPDDR4__MEMDATA_RATIO_1__REG DENALI_CTL_287 +#define LPDDR4__MEMDATA_RATIO_1__FLD LPDDR4__DENALI_CTL_287__MEMDATA_RATIO_1 + +#define LPDDR4__DENALI_CTL_287__DEVICE0_BYTE0_CS1_MASK 0x000F0000U +#define LPDDR4__DENALI_CTL_287__DEVICE0_BYTE0_CS1_SHIFT 16U +#define LPDDR4__DENALI_CTL_287__DEVICE0_BYTE0_CS1_WIDTH 4U +#define LPDDR4__DEVICE0_BYTE0_CS1__REG DENALI_CTL_287 +#define LPDDR4__DEVICE0_BYTE0_CS1__FLD LPDDR4__DENALI_CTL_287__DEVICE0_BYTE0_CS1 + +#define LPDDR4__DENALI_CTL_287__DEVICE1_BYTE0_CS1_MASK 0x0F000000U +#define LPDDR4__DENALI_CTL_287__DEVICE1_BYTE0_CS1_SHIFT 24U +#define LPDDR4__DENALI_CTL_287__DEVICE1_BYTE0_CS1_WIDTH 4U +#define LPDDR4__DEVICE1_BYTE0_CS1__REG DENALI_CTL_287 +#define LPDDR4__DEVICE1_BYTE0_CS1__FLD LPDDR4__DENALI_CTL_287__DEVICE1_BYTE0_CS1 + +#define LPDDR4__DENALI_CTL_288_READ_MASK 0x011F0F0FU +#define LPDDR4__DENALI_CTL_288_WRITE_MASK 0x011F0F0FU +#define LPDDR4__DENALI_CTL_288__DEVICE2_BYTE0_CS1_MASK 0x0000000FU +#define LPDDR4__DENALI_CTL_288__DEVICE2_BYTE0_CS1_SHIFT 0U +#define LPDDR4__DENALI_CTL_288__DEVICE2_BYTE0_CS1_WIDTH 4U +#define LPDDR4__DEVICE2_BYTE0_CS1__REG DENALI_CTL_288 +#define LPDDR4__DEVICE2_BYTE0_CS1__FLD LPDDR4__DENALI_CTL_288__DEVICE2_BYTE0_CS1 + +#define LPDDR4__DENALI_CTL_288__DEVICE3_BYTE0_CS1_MASK 0x00000F00U +#define LPDDR4__DENALI_CTL_288__DEVICE3_BYTE0_CS1_SHIFT 8U +#define LPDDR4__DENALI_CTL_288__DEVICE3_BYTE0_CS1_WIDTH 4U +#define LPDDR4__DEVICE3_BYTE0_CS1__REG DENALI_CTL_288 +#define LPDDR4__DEVICE3_BYTE0_CS1__FLD LPDDR4__DENALI_CTL_288__DEVICE3_BYTE0_CS1 + +#define LPDDR4__DENALI_CTL_288__Q_FULLNESS_MASK 0x001F0000U +#define LPDDR4__DENALI_CTL_288__Q_FULLNESS_SHIFT 16U +#define LPDDR4__DENALI_CTL_288__Q_FULLNESS_WIDTH 5U +#define LPDDR4__Q_FULLNESS__REG DENALI_CTL_288 +#define LPDDR4__Q_FULLNESS__FLD LPDDR4__DENALI_CTL_288__Q_FULLNESS + +#define LPDDR4__DENALI_CTL_288__IN_ORDER_ACCEPT_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_288__IN_ORDER_ACCEPT_SHIFT 24U +#define LPDDR4__DENALI_CTL_288__IN_ORDER_ACCEPT_WIDTH 1U +#define LPDDR4__DENALI_CTL_288__IN_ORDER_ACCEPT_WOCLR 0U +#define LPDDR4__DENALI_CTL_288__IN_ORDER_ACCEPT_WOSET 0U +#define LPDDR4__IN_ORDER_ACCEPT__REG DENALI_CTL_288 +#define LPDDR4__IN_ORDER_ACCEPT__FLD LPDDR4__DENALI_CTL_288__IN_ORDER_ACCEPT + +#define LPDDR4__DENALI_CTL_289_READ_MASK 0x01000103U +#define LPDDR4__DENALI_CTL_289_WRITE_MASK 0x01000103U +#define LPDDR4__DENALI_CTL_289__WR_ORDER_REQ_MASK 0x00000003U +#define LPDDR4__DENALI_CTL_289__WR_ORDER_REQ_SHIFT 0U +#define LPDDR4__DENALI_CTL_289__WR_ORDER_REQ_WIDTH 2U +#define LPDDR4__WR_ORDER_REQ__REG DENALI_CTL_289 +#define LPDDR4__WR_ORDER_REQ__FLD LPDDR4__DENALI_CTL_289__WR_ORDER_REQ + +#define LPDDR4__DENALI_CTL_289__CONTROLLER_BUSY_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_289__CONTROLLER_BUSY_SHIFT 8U +#define LPDDR4__DENALI_CTL_289__CONTROLLER_BUSY_WIDTH 1U +#define LPDDR4__DENALI_CTL_289__CONTROLLER_BUSY_WOCLR 0U +#define LPDDR4__DENALI_CTL_289__CONTROLLER_BUSY_WOSET 0U +#define LPDDR4__CONTROLLER_BUSY__REG DENALI_CTL_289 +#define LPDDR4__CONTROLLER_BUSY__FLD LPDDR4__DENALI_CTL_289__CONTROLLER_BUSY + +#define LPDDR4__DENALI_CTL_289__CTRLUPD_REQ_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_289__CTRLUPD_REQ_SHIFT 16U +#define LPDDR4__DENALI_CTL_289__CTRLUPD_REQ_WIDTH 1U +#define LPDDR4__DENALI_CTL_289__CTRLUPD_REQ_WOCLR 0U +#define LPDDR4__DENALI_CTL_289__CTRLUPD_REQ_WOSET 0U +#define LPDDR4__CTRLUPD_REQ__REG DENALI_CTL_289 +#define LPDDR4__CTRLUPD_REQ__FLD LPDDR4__DENALI_CTL_289__CTRLUPD_REQ + +#define LPDDR4__DENALI_CTL_289__CTRLUPD_REQ_PER_AREF_EN_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_289__CTRLUPD_REQ_PER_AREF_EN_SHIFT 24U +#define LPDDR4__DENALI_CTL_289__CTRLUPD_REQ_PER_AREF_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_289__CTRLUPD_REQ_PER_AREF_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_289__CTRLUPD_REQ_PER_AREF_EN_WOSET 0U +#define LPDDR4__CTRLUPD_REQ_PER_AREF_EN__REG DENALI_CTL_289 +#define LPDDR4__CTRLUPD_REQ_PER_AREF_EN__FLD LPDDR4__DENALI_CTL_289__CTRLUPD_REQ_PER_AREF_EN + +#define LPDDR4__DENALI_CTL_290_READ_MASK 0x03030301U +#define LPDDR4__DENALI_CTL_290_WRITE_MASK 0x03030301U +#define LPDDR4__DENALI_CTL_290__CTRLUPD_AREF_HP_ENABLE_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_290__CTRLUPD_AREF_HP_ENABLE_SHIFT 0U +#define LPDDR4__DENALI_CTL_290__CTRLUPD_AREF_HP_ENABLE_WIDTH 1U +#define LPDDR4__DENALI_CTL_290__CTRLUPD_AREF_HP_ENABLE_WOCLR 0U +#define LPDDR4__DENALI_CTL_290__CTRLUPD_AREF_HP_ENABLE_WOSET 0U +#define LPDDR4__CTRLUPD_AREF_HP_ENABLE__REG DENALI_CTL_290 +#define LPDDR4__CTRLUPD_AREF_HP_ENABLE__FLD LPDDR4__DENALI_CTL_290__CTRLUPD_AREF_HP_ENABLE + +#define LPDDR4__DENALI_CTL_290__PREAMBLE_SUPPORT_F0_MASK 0x00000300U +#define LPDDR4__DENALI_CTL_290__PREAMBLE_SUPPORT_F0_SHIFT 8U +#define LPDDR4__DENALI_CTL_290__PREAMBLE_SUPPORT_F0_WIDTH 2U +#define LPDDR4__PREAMBLE_SUPPORT_F0__REG DENALI_CTL_290 +#define LPDDR4__PREAMBLE_SUPPORT_F0__FLD LPDDR4__DENALI_CTL_290__PREAMBLE_SUPPORT_F0 + +#define LPDDR4__DENALI_CTL_290__PREAMBLE_SUPPORT_F1_MASK 0x00030000U +#define LPDDR4__DENALI_CTL_290__PREAMBLE_SUPPORT_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_290__PREAMBLE_SUPPORT_F1_WIDTH 2U +#define LPDDR4__PREAMBLE_SUPPORT_F1__REG DENALI_CTL_290 +#define LPDDR4__PREAMBLE_SUPPORT_F1__FLD LPDDR4__DENALI_CTL_290__PREAMBLE_SUPPORT_F1 + +#define LPDDR4__DENALI_CTL_290__PREAMBLE_SUPPORT_F2_MASK 0x03000000U +#define LPDDR4__DENALI_CTL_290__PREAMBLE_SUPPORT_F2_SHIFT 24U +#define LPDDR4__DENALI_CTL_290__PREAMBLE_SUPPORT_F2_WIDTH 2U +#define LPDDR4__PREAMBLE_SUPPORT_F2__REG DENALI_CTL_290 +#define LPDDR4__PREAMBLE_SUPPORT_F2__FLD LPDDR4__DENALI_CTL_290__PREAMBLE_SUPPORT_F2 + +#define LPDDR4__DENALI_CTL_291_READ_MASK 0x1F010101U +#define LPDDR4__DENALI_CTL_291_WRITE_MASK 0x1F010101U +#define LPDDR4__DENALI_CTL_291__RD_PREAMBLE_TRAINING_EN_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_291__RD_PREAMBLE_TRAINING_EN_SHIFT 0U +#define LPDDR4__DENALI_CTL_291__RD_PREAMBLE_TRAINING_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_291__RD_PREAMBLE_TRAINING_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_291__RD_PREAMBLE_TRAINING_EN_WOSET 0U +#define LPDDR4__RD_PREAMBLE_TRAINING_EN__REG DENALI_CTL_291 +#define LPDDR4__RD_PREAMBLE_TRAINING_EN__FLD LPDDR4__DENALI_CTL_291__RD_PREAMBLE_TRAINING_EN + +#define LPDDR4__DENALI_CTL_291__WR_DBI_EN_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_291__WR_DBI_EN_SHIFT 8U +#define LPDDR4__DENALI_CTL_291__WR_DBI_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_291__WR_DBI_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_291__WR_DBI_EN_WOSET 0U +#define LPDDR4__WR_DBI_EN__REG DENALI_CTL_291 +#define LPDDR4__WR_DBI_EN__FLD LPDDR4__DENALI_CTL_291__WR_DBI_EN + +#define LPDDR4__DENALI_CTL_291__RD_DBI_EN_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_291__RD_DBI_EN_SHIFT 16U +#define LPDDR4__DENALI_CTL_291__RD_DBI_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_291__RD_DBI_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_291__RD_DBI_EN_WOSET 0U +#define LPDDR4__RD_DBI_EN__REG DENALI_CTL_291 +#define LPDDR4__RD_DBI_EN__FLD LPDDR4__DENALI_CTL_291__RD_DBI_EN + +#define LPDDR4__DENALI_CTL_291__DFI_ERROR_MASK 0x1F000000U +#define LPDDR4__DENALI_CTL_291__DFI_ERROR_SHIFT 24U +#define LPDDR4__DENALI_CTL_291__DFI_ERROR_WIDTH 5U +#define LPDDR4__DFI_ERROR__REG DENALI_CTL_291 +#define LPDDR4__DFI_ERROR__FLD LPDDR4__DENALI_CTL_291__DFI_ERROR + +#define LPDDR4__DENALI_CTL_292_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_292_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_292__DFI_ERROR_INFO_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_292__DFI_ERROR_INFO_SHIFT 0U +#define LPDDR4__DENALI_CTL_292__DFI_ERROR_INFO_WIDTH 20U +#define LPDDR4__DFI_ERROR_INFO__REG DENALI_CTL_292 +#define LPDDR4__DFI_ERROR_INFO__FLD LPDDR4__DENALI_CTL_292__DFI_ERROR_INFO + +#define LPDDR4__DENALI_CTL_292__MC_RESERVED28_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_292__MC_RESERVED28_SHIFT 24U +#define LPDDR4__DENALI_CTL_292__MC_RESERVED28_WIDTH 1U +#define LPDDR4__DENALI_CTL_292__MC_RESERVED28_WOCLR 0U +#define LPDDR4__DENALI_CTL_292__MC_RESERVED28_WOSET 0U +#define LPDDR4__MC_RESERVED28__REG DENALI_CTL_292 +#define LPDDR4__MC_RESERVED28__FLD LPDDR4__DENALI_CTL_292__MC_RESERVED28 + +#define LPDDR4__DENALI_CTL_293_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_293_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_293__INT_STATUS_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_293__INT_STATUS_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_293__INT_STATUS_0_WIDTH 32U +#define LPDDR4__INT_STATUS_0__REG DENALI_CTL_293 +#define LPDDR4__INT_STATUS_0__FLD LPDDR4__DENALI_CTL_293__INT_STATUS_0 + +#define LPDDR4__DENALI_CTL_294_READ_MASK 0x00001FFFU +#define LPDDR4__DENALI_CTL_294_WRITE_MASK 0x00001FFFU +#define LPDDR4__DENALI_CTL_294__INT_STATUS_1_MASK 0x00001FFFU +#define LPDDR4__DENALI_CTL_294__INT_STATUS_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_294__INT_STATUS_1_WIDTH 13U +#define LPDDR4__INT_STATUS_1__REG DENALI_CTL_294 +#define LPDDR4__INT_STATUS_1__FLD LPDDR4__DENALI_CTL_294__INT_STATUS_1 + +#define LPDDR4__DENALI_CTL_295__INT_ACK_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_295__INT_ACK_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_295__INT_ACK_0_WIDTH 32U +#define LPDDR4__INT_ACK_0__REG DENALI_CTL_295 +#define LPDDR4__INT_ACK_0__FLD LPDDR4__DENALI_CTL_295__INT_ACK_0 + +#define LPDDR4__DENALI_CTL_296__INT_ACK_1_MASK 0x00000FFFU +#define LPDDR4__DENALI_CTL_296__INT_ACK_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_296__INT_ACK_1_WIDTH 12U +#define LPDDR4__INT_ACK_1__REG DENALI_CTL_296 +#define LPDDR4__INT_ACK_1__FLD LPDDR4__DENALI_CTL_296__INT_ACK_1 + +#define LPDDR4__DENALI_CTL_297_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_297_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_297__INT_MASK_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_297__INT_MASK_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_297__INT_MASK_0_WIDTH 32U +#define LPDDR4__INT_MASK_0__REG DENALI_CTL_297 +#define LPDDR4__INT_MASK_0__FLD LPDDR4__DENALI_CTL_297__INT_MASK_0 + +#define LPDDR4__DENALI_CTL_298_READ_MASK 0x00001FFFU +#define LPDDR4__DENALI_CTL_298_WRITE_MASK 0x00001FFFU +#define LPDDR4__DENALI_CTL_298__INT_MASK_1_MASK 0x00001FFFU +#define LPDDR4__DENALI_CTL_298__INT_MASK_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_298__INT_MASK_1_WIDTH 13U +#define LPDDR4__INT_MASK_1__REG DENALI_CTL_298 +#define LPDDR4__INT_MASK_1__FLD LPDDR4__DENALI_CTL_298__INT_MASK_1 + +#define LPDDR4__DENALI_CTL_299_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_299_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_299__OUT_OF_RANGE_ADDR_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_299__OUT_OF_RANGE_ADDR_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_299__OUT_OF_RANGE_ADDR_0_WIDTH 32U +#define LPDDR4__OUT_OF_RANGE_ADDR_0__REG DENALI_CTL_299 +#define LPDDR4__OUT_OF_RANGE_ADDR_0__FLD LPDDR4__DENALI_CTL_299__OUT_OF_RANGE_ADDR_0 + +#define LPDDR4__DENALI_CTL_300_READ_MASK 0x7F0FFF07U +#define LPDDR4__DENALI_CTL_300_WRITE_MASK 0x7F0FFF07U +#define LPDDR4__DENALI_CTL_300__OUT_OF_RANGE_ADDR_1_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_300__OUT_OF_RANGE_ADDR_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_300__OUT_OF_RANGE_ADDR_1_WIDTH 3U +#define LPDDR4__OUT_OF_RANGE_ADDR_1__REG DENALI_CTL_300 +#define LPDDR4__OUT_OF_RANGE_ADDR_1__FLD LPDDR4__DENALI_CTL_300__OUT_OF_RANGE_ADDR_1 + +#define LPDDR4__DENALI_CTL_300__OUT_OF_RANGE_LENGTH_MASK 0x000FFF00U +#define LPDDR4__DENALI_CTL_300__OUT_OF_RANGE_LENGTH_SHIFT 8U +#define LPDDR4__DENALI_CTL_300__OUT_OF_RANGE_LENGTH_WIDTH 12U +#define LPDDR4__OUT_OF_RANGE_LENGTH__REG DENALI_CTL_300 +#define LPDDR4__OUT_OF_RANGE_LENGTH__FLD LPDDR4__DENALI_CTL_300__OUT_OF_RANGE_LENGTH + +#define LPDDR4__DENALI_CTL_300__OUT_OF_RANGE_TYPE_MASK 0x7F000000U +#define LPDDR4__DENALI_CTL_300__OUT_OF_RANGE_TYPE_SHIFT 24U +#define LPDDR4__DENALI_CTL_300__OUT_OF_RANGE_TYPE_WIDTH 7U +#define LPDDR4__OUT_OF_RANGE_TYPE__REG DENALI_CTL_300 +#define LPDDR4__OUT_OF_RANGE_TYPE__FLD LPDDR4__DENALI_CTL_300__OUT_OF_RANGE_TYPE + +#define LPDDR4__DENALI_CTL_301_READ_MASK 0x0000003FU +#define LPDDR4__DENALI_CTL_301_WRITE_MASK 0x0000003FU +#define LPDDR4__DENALI_CTL_301__OUT_OF_RANGE_SOURCE_ID_MASK 0x0000003FU +#define LPDDR4__DENALI_CTL_301__OUT_OF_RANGE_SOURCE_ID_SHIFT 0U +#define LPDDR4__DENALI_CTL_301__OUT_OF_RANGE_SOURCE_ID_WIDTH 6U +#define LPDDR4__OUT_OF_RANGE_SOURCE_ID__REG DENALI_CTL_301 +#define LPDDR4__OUT_OF_RANGE_SOURCE_ID__FLD LPDDR4__DENALI_CTL_301__OUT_OF_RANGE_SOURCE_ID + +#define LPDDR4__DENALI_CTL_302_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_302_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_302__BIST_EXP_DATA_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_302__BIST_EXP_DATA_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_302__BIST_EXP_DATA_0_WIDTH 32U +#define LPDDR4__BIST_EXP_DATA_0__REG DENALI_CTL_302 +#define LPDDR4__BIST_EXP_DATA_0__FLD LPDDR4__DENALI_CTL_302__BIST_EXP_DATA_0 + +#define LPDDR4__DENALI_CTL_303_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_303_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_303__BIST_EXP_DATA_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_303__BIST_EXP_DATA_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_303__BIST_EXP_DATA_1_WIDTH 32U +#define LPDDR4__BIST_EXP_DATA_1__REG DENALI_CTL_303 +#define LPDDR4__BIST_EXP_DATA_1__FLD LPDDR4__DENALI_CTL_303__BIST_EXP_DATA_1 + +#define LPDDR4__DENALI_CTL_304_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_304_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_304__BIST_EXP_DATA_2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_304__BIST_EXP_DATA_2_SHIFT 0U +#define LPDDR4__DENALI_CTL_304__BIST_EXP_DATA_2_WIDTH 32U +#define LPDDR4__BIST_EXP_DATA_2__REG DENALI_CTL_304 +#define LPDDR4__BIST_EXP_DATA_2__FLD LPDDR4__DENALI_CTL_304__BIST_EXP_DATA_2 + +#define LPDDR4__DENALI_CTL_305_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_305_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_305__BIST_EXP_DATA_3_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_305__BIST_EXP_DATA_3_SHIFT 0U +#define LPDDR4__DENALI_CTL_305__BIST_EXP_DATA_3_WIDTH 32U +#define LPDDR4__BIST_EXP_DATA_3__REG DENALI_CTL_305 +#define LPDDR4__BIST_EXP_DATA_3__FLD LPDDR4__DENALI_CTL_305__BIST_EXP_DATA_3 + +#define LPDDR4__DENALI_CTL_306_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_306_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_306__BIST_FAIL_DATA_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_306__BIST_FAIL_DATA_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_306__BIST_FAIL_DATA_0_WIDTH 32U +#define LPDDR4__BIST_FAIL_DATA_0__REG DENALI_CTL_306 +#define LPDDR4__BIST_FAIL_DATA_0__FLD LPDDR4__DENALI_CTL_306__BIST_FAIL_DATA_0 + +#define LPDDR4__DENALI_CTL_307_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_307_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_307__BIST_FAIL_DATA_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_307__BIST_FAIL_DATA_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_307__BIST_FAIL_DATA_1_WIDTH 32U +#define LPDDR4__BIST_FAIL_DATA_1__REG DENALI_CTL_307 +#define LPDDR4__BIST_FAIL_DATA_1__FLD LPDDR4__DENALI_CTL_307__BIST_FAIL_DATA_1 + +#define LPDDR4__DENALI_CTL_308_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_308_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_308__BIST_FAIL_DATA_2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_308__BIST_FAIL_DATA_2_SHIFT 0U +#define LPDDR4__DENALI_CTL_308__BIST_FAIL_DATA_2_WIDTH 32U +#define LPDDR4__BIST_FAIL_DATA_2__REG DENALI_CTL_308 +#define LPDDR4__BIST_FAIL_DATA_2__FLD LPDDR4__DENALI_CTL_308__BIST_FAIL_DATA_2 + +#define LPDDR4__DENALI_CTL_309_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_309_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_309__BIST_FAIL_DATA_3_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_309__BIST_FAIL_DATA_3_SHIFT 0U +#define LPDDR4__DENALI_CTL_309__BIST_FAIL_DATA_3_WIDTH 32U +#define LPDDR4__BIST_FAIL_DATA_3__REG DENALI_CTL_309 +#define LPDDR4__BIST_FAIL_DATA_3__FLD LPDDR4__DENALI_CTL_309__BIST_FAIL_DATA_3 + +#define LPDDR4__DENALI_CTL_310_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_310_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_310__BIST_FAIL_ADDR_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_310__BIST_FAIL_ADDR_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_310__BIST_FAIL_ADDR_0_WIDTH 32U +#define LPDDR4__BIST_FAIL_ADDR_0__REG DENALI_CTL_310 +#define LPDDR4__BIST_FAIL_ADDR_0__FLD LPDDR4__DENALI_CTL_310__BIST_FAIL_ADDR_0 + +#define LPDDR4__DENALI_CTL_311_READ_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_311_WRITE_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_311__BIST_FAIL_ADDR_1_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_311__BIST_FAIL_ADDR_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_311__BIST_FAIL_ADDR_1_WIDTH 3U +#define LPDDR4__BIST_FAIL_ADDR_1__REG DENALI_CTL_311 +#define LPDDR4__BIST_FAIL_ADDR_1__FLD LPDDR4__DENALI_CTL_311__BIST_FAIL_ADDR_1 + +#define LPDDR4__DENALI_CTL_312_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_312_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_312__PORT_CMD_ERROR_ADDR_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_312__PORT_CMD_ERROR_ADDR_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_312__PORT_CMD_ERROR_ADDR_0_WIDTH 32U +#define LPDDR4__PORT_CMD_ERROR_ADDR_0__REG DENALI_CTL_312 +#define LPDDR4__PORT_CMD_ERROR_ADDR_0__FLD LPDDR4__DENALI_CTL_312__PORT_CMD_ERROR_ADDR_0 + +#define LPDDR4__DENALI_CTL_313_READ_MASK 0x03033F07U +#define LPDDR4__DENALI_CTL_313_WRITE_MASK 0x03033F07U +#define LPDDR4__DENALI_CTL_313__PORT_CMD_ERROR_ADDR_1_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_313__PORT_CMD_ERROR_ADDR_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_313__PORT_CMD_ERROR_ADDR_1_WIDTH 3U +#define LPDDR4__PORT_CMD_ERROR_ADDR_1__REG DENALI_CTL_313 +#define LPDDR4__PORT_CMD_ERROR_ADDR_1__FLD LPDDR4__DENALI_CTL_313__PORT_CMD_ERROR_ADDR_1 + +#define LPDDR4__DENALI_CTL_313__PORT_CMD_ERROR_ID_MASK 0x00003F00U +#define LPDDR4__DENALI_CTL_313__PORT_CMD_ERROR_ID_SHIFT 8U +#define LPDDR4__DENALI_CTL_313__PORT_CMD_ERROR_ID_WIDTH 6U +#define LPDDR4__PORT_CMD_ERROR_ID__REG DENALI_CTL_313 +#define LPDDR4__PORT_CMD_ERROR_ID__FLD LPDDR4__DENALI_CTL_313__PORT_CMD_ERROR_ID + +#define LPDDR4__DENALI_CTL_313__PORT_CMD_ERROR_TYPE_MASK 0x00030000U +#define LPDDR4__DENALI_CTL_313__PORT_CMD_ERROR_TYPE_SHIFT 16U +#define LPDDR4__DENALI_CTL_313__PORT_CMD_ERROR_TYPE_WIDTH 2U +#define LPDDR4__PORT_CMD_ERROR_TYPE__REG DENALI_CTL_313 +#define LPDDR4__PORT_CMD_ERROR_TYPE__FLD LPDDR4__DENALI_CTL_313__PORT_CMD_ERROR_TYPE + +#define LPDDR4__DENALI_CTL_313__ODT_RD_MAP_CS0_MASK 0x03000000U +#define LPDDR4__DENALI_CTL_313__ODT_RD_MAP_CS0_SHIFT 24U +#define LPDDR4__DENALI_CTL_313__ODT_RD_MAP_CS0_WIDTH 2U +#define LPDDR4__ODT_RD_MAP_CS0__REG DENALI_CTL_313 +#define LPDDR4__ODT_RD_MAP_CS0__FLD LPDDR4__DENALI_CTL_313__ODT_RD_MAP_CS0 + +#define LPDDR4__DENALI_CTL_314_READ_MASK 0xFF030303U +#define LPDDR4__DENALI_CTL_314_WRITE_MASK 0xFF030303U +#define LPDDR4__DENALI_CTL_314__ODT_WR_MAP_CS0_MASK 0x00000003U +#define LPDDR4__DENALI_CTL_314__ODT_WR_MAP_CS0_SHIFT 0U +#define LPDDR4__DENALI_CTL_314__ODT_WR_MAP_CS0_WIDTH 2U +#define LPDDR4__ODT_WR_MAP_CS0__REG DENALI_CTL_314 +#define LPDDR4__ODT_WR_MAP_CS0__FLD LPDDR4__DENALI_CTL_314__ODT_WR_MAP_CS0 + +#define LPDDR4__DENALI_CTL_314__ODT_RD_MAP_CS1_MASK 0x00000300U +#define LPDDR4__DENALI_CTL_314__ODT_RD_MAP_CS1_SHIFT 8U +#define LPDDR4__DENALI_CTL_314__ODT_RD_MAP_CS1_WIDTH 2U +#define LPDDR4__ODT_RD_MAP_CS1__REG DENALI_CTL_314 +#define LPDDR4__ODT_RD_MAP_CS1__FLD LPDDR4__DENALI_CTL_314__ODT_RD_MAP_CS1 + +#define LPDDR4__DENALI_CTL_314__ODT_WR_MAP_CS1_MASK 0x00030000U +#define LPDDR4__DENALI_CTL_314__ODT_WR_MAP_CS1_SHIFT 16U +#define LPDDR4__DENALI_CTL_314__ODT_WR_MAP_CS1_WIDTH 2U +#define LPDDR4__ODT_WR_MAP_CS1__REG DENALI_CTL_314 +#define LPDDR4__ODT_WR_MAP_CS1__FLD LPDDR4__DENALI_CTL_314__ODT_WR_MAP_CS1 + +#define LPDDR4__DENALI_CTL_314__TODTL_2CMD_F0_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_314__TODTL_2CMD_F0_SHIFT 24U +#define LPDDR4__DENALI_CTL_314__TODTL_2CMD_F0_WIDTH 8U +#define LPDDR4__TODTL_2CMD_F0__REG DENALI_CTL_314 +#define LPDDR4__TODTL_2CMD_F0__FLD LPDDR4__DENALI_CTL_314__TODTL_2CMD_F0 + +#define LPDDR4__DENALI_CTL_315_READ_MASK 0x0FFF0F0FU +#define LPDDR4__DENALI_CTL_315_WRITE_MASK 0x0FFF0F0FU +#define LPDDR4__DENALI_CTL_315__TODTH_WR_F0_MASK 0x0000000FU +#define LPDDR4__DENALI_CTL_315__TODTH_WR_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_315__TODTH_WR_F0_WIDTH 4U +#define LPDDR4__TODTH_WR_F0__REG DENALI_CTL_315 +#define LPDDR4__TODTH_WR_F0__FLD LPDDR4__DENALI_CTL_315__TODTH_WR_F0 + +#define LPDDR4__DENALI_CTL_315__TODTH_RD_F0_MASK 0x00000F00U +#define LPDDR4__DENALI_CTL_315__TODTH_RD_F0_SHIFT 8U +#define LPDDR4__DENALI_CTL_315__TODTH_RD_F0_WIDTH 4U +#define LPDDR4__TODTH_RD_F0__REG DENALI_CTL_315 +#define LPDDR4__TODTH_RD_F0__FLD LPDDR4__DENALI_CTL_315__TODTH_RD_F0 + +#define LPDDR4__DENALI_CTL_315__TODTL_2CMD_F1_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_315__TODTL_2CMD_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_315__TODTL_2CMD_F1_WIDTH 8U +#define LPDDR4__TODTL_2CMD_F1__REG DENALI_CTL_315 +#define LPDDR4__TODTL_2CMD_F1__FLD LPDDR4__DENALI_CTL_315__TODTL_2CMD_F1 + +#define LPDDR4__DENALI_CTL_315__TODTH_WR_F1_MASK 0x0F000000U +#define LPDDR4__DENALI_CTL_315__TODTH_WR_F1_SHIFT 24U +#define LPDDR4__DENALI_CTL_315__TODTH_WR_F1_WIDTH 4U +#define LPDDR4__TODTH_WR_F1__REG DENALI_CTL_315 +#define LPDDR4__TODTH_WR_F1__FLD LPDDR4__DENALI_CTL_315__TODTH_WR_F1 + +#define LPDDR4__DENALI_CTL_316_READ_MASK 0x0F0FFF0FU +#define LPDDR4__DENALI_CTL_316_WRITE_MASK 0x0F0FFF0FU +#define LPDDR4__DENALI_CTL_316__TODTH_RD_F1_MASK 0x0000000FU +#define LPDDR4__DENALI_CTL_316__TODTH_RD_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_316__TODTH_RD_F1_WIDTH 4U +#define LPDDR4__TODTH_RD_F1__REG DENALI_CTL_316 +#define LPDDR4__TODTH_RD_F1__FLD LPDDR4__DENALI_CTL_316__TODTH_RD_F1 + +#define LPDDR4__DENALI_CTL_316__TODTL_2CMD_F2_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_316__TODTL_2CMD_F2_SHIFT 8U +#define LPDDR4__DENALI_CTL_316__TODTL_2CMD_F2_WIDTH 8U +#define LPDDR4__TODTL_2CMD_F2__REG DENALI_CTL_316 +#define LPDDR4__TODTL_2CMD_F2__FLD LPDDR4__DENALI_CTL_316__TODTL_2CMD_F2 + +#define LPDDR4__DENALI_CTL_316__TODTH_WR_F2_MASK 0x000F0000U +#define LPDDR4__DENALI_CTL_316__TODTH_WR_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_316__TODTH_WR_F2_WIDTH 4U +#define LPDDR4__TODTH_WR_F2__REG DENALI_CTL_316 +#define LPDDR4__TODTH_WR_F2__FLD LPDDR4__DENALI_CTL_316__TODTH_WR_F2 + +#define LPDDR4__DENALI_CTL_316__TODTH_RD_F2_MASK 0x0F000000U +#define LPDDR4__DENALI_CTL_316__TODTH_RD_F2_SHIFT 24U +#define LPDDR4__DENALI_CTL_316__TODTH_RD_F2_WIDTH 4U +#define LPDDR4__TODTH_RD_F2__REG DENALI_CTL_316 +#define LPDDR4__TODTH_RD_F2__FLD LPDDR4__DENALI_CTL_316__TODTH_RD_F2 + +#define LPDDR4__DENALI_CTL_317_READ_MASK 0x01010101U +#define LPDDR4__DENALI_CTL_317_WRITE_MASK 0x01010101U +#define LPDDR4__DENALI_CTL_317__ODT_EN_F0_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_317__ODT_EN_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_317__ODT_EN_F0_WIDTH 1U +#define LPDDR4__DENALI_CTL_317__ODT_EN_F0_WOCLR 0U +#define LPDDR4__DENALI_CTL_317__ODT_EN_F0_WOSET 0U +#define LPDDR4__ODT_EN_F0__REG DENALI_CTL_317 +#define LPDDR4__ODT_EN_F0__FLD LPDDR4__DENALI_CTL_317__ODT_EN_F0 + +#define LPDDR4__DENALI_CTL_317__ODT_EN_F1_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_317__ODT_EN_F1_SHIFT 8U +#define LPDDR4__DENALI_CTL_317__ODT_EN_F1_WIDTH 1U +#define LPDDR4__DENALI_CTL_317__ODT_EN_F1_WOCLR 0U +#define LPDDR4__DENALI_CTL_317__ODT_EN_F1_WOSET 0U +#define LPDDR4__ODT_EN_F1__REG DENALI_CTL_317 +#define LPDDR4__ODT_EN_F1__FLD LPDDR4__DENALI_CTL_317__ODT_EN_F1 + +#define LPDDR4__DENALI_CTL_317__ODT_EN_F2_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_317__ODT_EN_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_317__ODT_EN_F2_WIDTH 1U +#define LPDDR4__DENALI_CTL_317__ODT_EN_F2_WOCLR 0U +#define LPDDR4__DENALI_CTL_317__ODT_EN_F2_WOSET 0U +#define LPDDR4__ODT_EN_F2__REG DENALI_CTL_317 +#define LPDDR4__ODT_EN_F2__FLD LPDDR4__DENALI_CTL_317__ODT_EN_F2 + +#define LPDDR4__DENALI_CTL_317__EN_ODT_ASSERT_EXCEPT_RD_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_317__EN_ODT_ASSERT_EXCEPT_RD_SHIFT 24U +#define LPDDR4__DENALI_CTL_317__EN_ODT_ASSERT_EXCEPT_RD_WIDTH 1U +#define LPDDR4__DENALI_CTL_317__EN_ODT_ASSERT_EXCEPT_RD_WOCLR 0U +#define LPDDR4__DENALI_CTL_317__EN_ODT_ASSERT_EXCEPT_RD_WOSET 0U +#define LPDDR4__EN_ODT_ASSERT_EXCEPT_RD__REG DENALI_CTL_317 +#define LPDDR4__EN_ODT_ASSERT_EXCEPT_RD__FLD LPDDR4__DENALI_CTL_317__EN_ODT_ASSERT_EXCEPT_RD + +#define LPDDR4__DENALI_CTL_318_READ_MASK 0x3F3F3F3FU +#define LPDDR4__DENALI_CTL_318_WRITE_MASK 0x3F3F3F3FU +#define LPDDR4__DENALI_CTL_318__WR_TO_ODTH_F0_MASK 0x0000003FU +#define LPDDR4__DENALI_CTL_318__WR_TO_ODTH_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_318__WR_TO_ODTH_F0_WIDTH 6U +#define LPDDR4__WR_TO_ODTH_F0__REG DENALI_CTL_318 +#define LPDDR4__WR_TO_ODTH_F0__FLD LPDDR4__DENALI_CTL_318__WR_TO_ODTH_F0 + +#define LPDDR4__DENALI_CTL_318__WR_TO_ODTH_F1_MASK 0x00003F00U +#define LPDDR4__DENALI_CTL_318__WR_TO_ODTH_F1_SHIFT 8U +#define LPDDR4__DENALI_CTL_318__WR_TO_ODTH_F1_WIDTH 6U +#define LPDDR4__WR_TO_ODTH_F1__REG DENALI_CTL_318 +#define LPDDR4__WR_TO_ODTH_F1__FLD LPDDR4__DENALI_CTL_318__WR_TO_ODTH_F1 + +#define LPDDR4__DENALI_CTL_318__WR_TO_ODTH_F2_MASK 0x003F0000U +#define LPDDR4__DENALI_CTL_318__WR_TO_ODTH_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_318__WR_TO_ODTH_F2_WIDTH 6U +#define LPDDR4__WR_TO_ODTH_F2__REG DENALI_CTL_318 +#define LPDDR4__WR_TO_ODTH_F2__FLD LPDDR4__DENALI_CTL_318__WR_TO_ODTH_F2 + +#define LPDDR4__DENALI_CTL_318__RD_TO_ODTH_F0_MASK 0x3F000000U +#define LPDDR4__DENALI_CTL_318__RD_TO_ODTH_F0_SHIFT 24U +#define LPDDR4__DENALI_CTL_318__RD_TO_ODTH_F0_WIDTH 6U +#define LPDDR4__RD_TO_ODTH_F0__REG DENALI_CTL_318 +#define LPDDR4__RD_TO_ODTH_F0__FLD LPDDR4__DENALI_CTL_318__RD_TO_ODTH_F0 + +#define LPDDR4__DENALI_CTL_319_READ_MASK 0x1F1F3F3FU +#define LPDDR4__DENALI_CTL_319_WRITE_MASK 0x1F1F3F3FU +#define LPDDR4__DENALI_CTL_319__RD_TO_ODTH_F1_MASK 0x0000003FU +#define LPDDR4__DENALI_CTL_319__RD_TO_ODTH_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_319__RD_TO_ODTH_F1_WIDTH 6U +#define LPDDR4__RD_TO_ODTH_F1__REG DENALI_CTL_319 +#define LPDDR4__RD_TO_ODTH_F1__FLD LPDDR4__DENALI_CTL_319__RD_TO_ODTH_F1 + +#define LPDDR4__DENALI_CTL_319__RD_TO_ODTH_F2_MASK 0x00003F00U +#define LPDDR4__DENALI_CTL_319__RD_TO_ODTH_F2_SHIFT 8U +#define LPDDR4__DENALI_CTL_319__RD_TO_ODTH_F2_WIDTH 6U +#define LPDDR4__RD_TO_ODTH_F2__REG DENALI_CTL_319 +#define LPDDR4__RD_TO_ODTH_F2__FLD LPDDR4__DENALI_CTL_319__RD_TO_ODTH_F2 + +#define LPDDR4__DENALI_CTL_319__RW2MRW_DLY_F0_MASK 0x001F0000U +#define LPDDR4__DENALI_CTL_319__RW2MRW_DLY_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_319__RW2MRW_DLY_F0_WIDTH 5U +#define LPDDR4__RW2MRW_DLY_F0__REG DENALI_CTL_319 +#define LPDDR4__RW2MRW_DLY_F0__FLD LPDDR4__DENALI_CTL_319__RW2MRW_DLY_F0 + +#define LPDDR4__DENALI_CTL_319__RW2MRW_DLY_F1_MASK 0x1F000000U +#define LPDDR4__DENALI_CTL_319__RW2MRW_DLY_F1_SHIFT 24U +#define LPDDR4__DENALI_CTL_319__RW2MRW_DLY_F1_WIDTH 5U +#define LPDDR4__RW2MRW_DLY_F1__REG DENALI_CTL_319 +#define LPDDR4__RW2MRW_DLY_F1__FLD LPDDR4__DENALI_CTL_319__RW2MRW_DLY_F1 + +#define LPDDR4__DENALI_CTL_320_READ_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_CTL_320_WRITE_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_CTL_320__RW2MRW_DLY_F2_MASK 0x0000001FU +#define LPDDR4__DENALI_CTL_320__RW2MRW_DLY_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_320__RW2MRW_DLY_F2_WIDTH 5U +#define LPDDR4__RW2MRW_DLY_F2__REG DENALI_CTL_320 +#define LPDDR4__RW2MRW_DLY_F2__FLD LPDDR4__DENALI_CTL_320__RW2MRW_DLY_F2 + +#define LPDDR4__DENALI_CTL_320__R2R_DIFFCS_DLY_F0_MASK 0x00001F00U +#define LPDDR4__DENALI_CTL_320__R2R_DIFFCS_DLY_F0_SHIFT 8U +#define LPDDR4__DENALI_CTL_320__R2R_DIFFCS_DLY_F0_WIDTH 5U +#define LPDDR4__R2R_DIFFCS_DLY_F0__REG DENALI_CTL_320 +#define LPDDR4__R2R_DIFFCS_DLY_F0__FLD LPDDR4__DENALI_CTL_320__R2R_DIFFCS_DLY_F0 + +#define LPDDR4__DENALI_CTL_320__R2W_DIFFCS_DLY_F0_MASK 0x001F0000U +#define LPDDR4__DENALI_CTL_320__R2W_DIFFCS_DLY_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_320__R2W_DIFFCS_DLY_F0_WIDTH 5U +#define LPDDR4__R2W_DIFFCS_DLY_F0__REG DENALI_CTL_320 +#define LPDDR4__R2W_DIFFCS_DLY_F0__FLD LPDDR4__DENALI_CTL_320__R2W_DIFFCS_DLY_F0 + +#define LPDDR4__DENALI_CTL_320__W2R_DIFFCS_DLY_F0_MASK 0x1F000000U +#define LPDDR4__DENALI_CTL_320__W2R_DIFFCS_DLY_F0_SHIFT 24U +#define LPDDR4__DENALI_CTL_320__W2R_DIFFCS_DLY_F0_WIDTH 5U +#define LPDDR4__W2R_DIFFCS_DLY_F0__REG DENALI_CTL_320 +#define LPDDR4__W2R_DIFFCS_DLY_F0__FLD LPDDR4__DENALI_CTL_320__W2R_DIFFCS_DLY_F0 + +#define LPDDR4__DENALI_CTL_321_READ_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_CTL_321_WRITE_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_CTL_321__W2W_DIFFCS_DLY_F0_MASK 0x0000001FU +#define LPDDR4__DENALI_CTL_321__W2W_DIFFCS_DLY_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_321__W2W_DIFFCS_DLY_F0_WIDTH 5U +#define LPDDR4__W2W_DIFFCS_DLY_F0__REG DENALI_CTL_321 +#define LPDDR4__W2W_DIFFCS_DLY_F0__FLD LPDDR4__DENALI_CTL_321__W2W_DIFFCS_DLY_F0 + +#define LPDDR4__DENALI_CTL_321__R2R_DIFFCS_DLY_F1_MASK 0x00001F00U +#define LPDDR4__DENALI_CTL_321__R2R_DIFFCS_DLY_F1_SHIFT 8U +#define LPDDR4__DENALI_CTL_321__R2R_DIFFCS_DLY_F1_WIDTH 5U +#define LPDDR4__R2R_DIFFCS_DLY_F1__REG DENALI_CTL_321 +#define LPDDR4__R2R_DIFFCS_DLY_F1__FLD LPDDR4__DENALI_CTL_321__R2R_DIFFCS_DLY_F1 + +#define LPDDR4__DENALI_CTL_321__R2W_DIFFCS_DLY_F1_MASK 0x001F0000U +#define LPDDR4__DENALI_CTL_321__R2W_DIFFCS_DLY_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_321__R2W_DIFFCS_DLY_F1_WIDTH 5U +#define LPDDR4__R2W_DIFFCS_DLY_F1__REG DENALI_CTL_321 +#define LPDDR4__R2W_DIFFCS_DLY_F1__FLD LPDDR4__DENALI_CTL_321__R2W_DIFFCS_DLY_F1 + +#define LPDDR4__DENALI_CTL_321__W2R_DIFFCS_DLY_F1_MASK 0x1F000000U +#define LPDDR4__DENALI_CTL_321__W2R_DIFFCS_DLY_F1_SHIFT 24U +#define LPDDR4__DENALI_CTL_321__W2R_DIFFCS_DLY_F1_WIDTH 5U +#define LPDDR4__W2R_DIFFCS_DLY_F1__REG DENALI_CTL_321 +#define LPDDR4__W2R_DIFFCS_DLY_F1__FLD LPDDR4__DENALI_CTL_321__W2R_DIFFCS_DLY_F1 + +#define LPDDR4__DENALI_CTL_322_READ_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_CTL_322_WRITE_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_CTL_322__W2W_DIFFCS_DLY_F1_MASK 0x0000001FU +#define LPDDR4__DENALI_CTL_322__W2W_DIFFCS_DLY_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_322__W2W_DIFFCS_DLY_F1_WIDTH 5U +#define LPDDR4__W2W_DIFFCS_DLY_F1__REG DENALI_CTL_322 +#define LPDDR4__W2W_DIFFCS_DLY_F1__FLD LPDDR4__DENALI_CTL_322__W2W_DIFFCS_DLY_F1 + +#define LPDDR4__DENALI_CTL_322__R2R_DIFFCS_DLY_F2_MASK 0x00001F00U +#define LPDDR4__DENALI_CTL_322__R2R_DIFFCS_DLY_F2_SHIFT 8U +#define LPDDR4__DENALI_CTL_322__R2R_DIFFCS_DLY_F2_WIDTH 5U +#define LPDDR4__R2R_DIFFCS_DLY_F2__REG DENALI_CTL_322 +#define LPDDR4__R2R_DIFFCS_DLY_F2__FLD LPDDR4__DENALI_CTL_322__R2R_DIFFCS_DLY_F2 + +#define LPDDR4__DENALI_CTL_322__R2W_DIFFCS_DLY_F2_MASK 0x001F0000U +#define LPDDR4__DENALI_CTL_322__R2W_DIFFCS_DLY_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_322__R2W_DIFFCS_DLY_F2_WIDTH 5U +#define LPDDR4__R2W_DIFFCS_DLY_F2__REG DENALI_CTL_322 +#define LPDDR4__R2W_DIFFCS_DLY_F2__FLD LPDDR4__DENALI_CTL_322__R2W_DIFFCS_DLY_F2 + +#define LPDDR4__DENALI_CTL_322__W2R_DIFFCS_DLY_F2_MASK 0x1F000000U +#define LPDDR4__DENALI_CTL_322__W2R_DIFFCS_DLY_F2_SHIFT 24U +#define LPDDR4__DENALI_CTL_322__W2R_DIFFCS_DLY_F2_WIDTH 5U +#define LPDDR4__W2R_DIFFCS_DLY_F2__REG DENALI_CTL_322 +#define LPDDR4__W2R_DIFFCS_DLY_F2__FLD LPDDR4__DENALI_CTL_322__W2R_DIFFCS_DLY_F2 + +#define LPDDR4__DENALI_CTL_323_READ_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_CTL_323_WRITE_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_CTL_323__W2W_DIFFCS_DLY_F2_MASK 0x0000001FU +#define LPDDR4__DENALI_CTL_323__W2W_DIFFCS_DLY_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_323__W2W_DIFFCS_DLY_F2_WIDTH 5U +#define LPDDR4__W2W_DIFFCS_DLY_F2__REG DENALI_CTL_323 +#define LPDDR4__W2W_DIFFCS_DLY_F2__FLD LPDDR4__DENALI_CTL_323__W2W_DIFFCS_DLY_F2 + +#define LPDDR4__DENALI_CTL_323__R2R_SAMECS_DLY_MASK 0x00001F00U +#define LPDDR4__DENALI_CTL_323__R2R_SAMECS_DLY_SHIFT 8U +#define LPDDR4__DENALI_CTL_323__R2R_SAMECS_DLY_WIDTH 5U +#define LPDDR4__R2R_SAMECS_DLY__REG DENALI_CTL_323 +#define LPDDR4__R2R_SAMECS_DLY__FLD LPDDR4__DENALI_CTL_323__R2R_SAMECS_DLY + +#define LPDDR4__DENALI_CTL_323__R2W_SAMECS_DLY_F0_MASK 0x001F0000U +#define LPDDR4__DENALI_CTL_323__R2W_SAMECS_DLY_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_323__R2W_SAMECS_DLY_F0_WIDTH 5U +#define LPDDR4__R2W_SAMECS_DLY_F0__REG DENALI_CTL_323 +#define LPDDR4__R2W_SAMECS_DLY_F0__FLD LPDDR4__DENALI_CTL_323__R2W_SAMECS_DLY_F0 + +#define LPDDR4__DENALI_CTL_323__R2W_SAMECS_DLY_F1_MASK 0x1F000000U +#define LPDDR4__DENALI_CTL_323__R2W_SAMECS_DLY_F1_SHIFT 24U +#define LPDDR4__DENALI_CTL_323__R2W_SAMECS_DLY_F1_WIDTH 5U +#define LPDDR4__R2W_SAMECS_DLY_F1__REG DENALI_CTL_323 +#define LPDDR4__R2W_SAMECS_DLY_F1__FLD LPDDR4__DENALI_CTL_323__R2W_SAMECS_DLY_F1 + +#define LPDDR4__DENALI_CTL_324_READ_MASK 0x0F1F1F1FU +#define LPDDR4__DENALI_CTL_324_WRITE_MASK 0x0F1F1F1FU +#define LPDDR4__DENALI_CTL_324__R2W_SAMECS_DLY_F2_MASK 0x0000001FU +#define LPDDR4__DENALI_CTL_324__R2W_SAMECS_DLY_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_324__R2W_SAMECS_DLY_F2_WIDTH 5U +#define LPDDR4__R2W_SAMECS_DLY_F2__REG DENALI_CTL_324 +#define LPDDR4__R2W_SAMECS_DLY_F2__FLD LPDDR4__DENALI_CTL_324__R2W_SAMECS_DLY_F2 + +#define LPDDR4__DENALI_CTL_324__W2R_SAMECS_DLY_MASK 0x00001F00U +#define LPDDR4__DENALI_CTL_324__W2R_SAMECS_DLY_SHIFT 8U +#define LPDDR4__DENALI_CTL_324__W2R_SAMECS_DLY_WIDTH 5U +#define LPDDR4__W2R_SAMECS_DLY__REG DENALI_CTL_324 +#define LPDDR4__W2R_SAMECS_DLY__FLD LPDDR4__DENALI_CTL_324__W2R_SAMECS_DLY + +#define LPDDR4__DENALI_CTL_324__W2W_SAMECS_DLY_MASK 0x001F0000U +#define LPDDR4__DENALI_CTL_324__W2W_SAMECS_DLY_SHIFT 16U +#define LPDDR4__DENALI_CTL_324__W2W_SAMECS_DLY_WIDTH 5U +#define LPDDR4__W2W_SAMECS_DLY__REG DENALI_CTL_324 +#define LPDDR4__W2W_SAMECS_DLY__FLD LPDDR4__DENALI_CTL_324__W2W_SAMECS_DLY + +#define LPDDR4__DENALI_CTL_324__TDQSCK_MAX_F0_MASK 0x0F000000U +#define LPDDR4__DENALI_CTL_324__TDQSCK_MAX_F0_SHIFT 24U +#define LPDDR4__DENALI_CTL_324__TDQSCK_MAX_F0_WIDTH 4U +#define LPDDR4__TDQSCK_MAX_F0__REG DENALI_CTL_324 +#define LPDDR4__TDQSCK_MAX_F0__FLD LPDDR4__DENALI_CTL_324__TDQSCK_MAX_F0 + +#define LPDDR4__DENALI_CTL_325_READ_MASK 0x0F070F07U +#define LPDDR4__DENALI_CTL_325_WRITE_MASK 0x0F070F07U +#define LPDDR4__DENALI_CTL_325__TDQSCK_MIN_F0_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_325__TDQSCK_MIN_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_325__TDQSCK_MIN_F0_WIDTH 3U +#define LPDDR4__TDQSCK_MIN_F0__REG DENALI_CTL_325 +#define LPDDR4__TDQSCK_MIN_F0__FLD LPDDR4__DENALI_CTL_325__TDQSCK_MIN_F0 + +#define LPDDR4__DENALI_CTL_325__TDQSCK_MAX_F1_MASK 0x00000F00U +#define LPDDR4__DENALI_CTL_325__TDQSCK_MAX_F1_SHIFT 8U +#define LPDDR4__DENALI_CTL_325__TDQSCK_MAX_F1_WIDTH 4U +#define LPDDR4__TDQSCK_MAX_F1__REG DENALI_CTL_325 +#define LPDDR4__TDQSCK_MAX_F1__FLD LPDDR4__DENALI_CTL_325__TDQSCK_MAX_F1 + +#define LPDDR4__DENALI_CTL_325__TDQSCK_MIN_F1_MASK 0x00070000U +#define LPDDR4__DENALI_CTL_325__TDQSCK_MIN_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_325__TDQSCK_MIN_F1_WIDTH 3U +#define LPDDR4__TDQSCK_MIN_F1__REG DENALI_CTL_325 +#define LPDDR4__TDQSCK_MIN_F1__FLD LPDDR4__DENALI_CTL_325__TDQSCK_MIN_F1 + +#define LPDDR4__DENALI_CTL_325__TDQSCK_MAX_F2_MASK 0x0F000000U +#define LPDDR4__DENALI_CTL_325__TDQSCK_MAX_F2_SHIFT 24U +#define LPDDR4__DENALI_CTL_325__TDQSCK_MAX_F2_WIDTH 4U +#define LPDDR4__TDQSCK_MAX_F2__REG DENALI_CTL_325 +#define LPDDR4__TDQSCK_MAX_F2__FLD LPDDR4__DENALI_CTL_325__TDQSCK_MAX_F2 + +#define LPDDR4__DENALI_CTL_326_READ_MASK 0x00000707U +#define LPDDR4__DENALI_CTL_326_WRITE_MASK 0x00000707U +#define LPDDR4__DENALI_CTL_326__TDQSCK_MIN_F2_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_326__TDQSCK_MIN_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_326__TDQSCK_MIN_F2_WIDTH 3U +#define LPDDR4__TDQSCK_MIN_F2__REG DENALI_CTL_326 +#define LPDDR4__TDQSCK_MIN_F2__FLD LPDDR4__DENALI_CTL_326__TDQSCK_MIN_F2 + +#define LPDDR4__DENALI_CTL_326__SW_LEVELING_MODE_MASK 0x00000700U +#define LPDDR4__DENALI_CTL_326__SW_LEVELING_MODE_SHIFT 8U +#define LPDDR4__DENALI_CTL_326__SW_LEVELING_MODE_WIDTH 3U +#define LPDDR4__SW_LEVELING_MODE__REG DENALI_CTL_326 +#define LPDDR4__SW_LEVELING_MODE__FLD LPDDR4__DENALI_CTL_326__SW_LEVELING_MODE + +#define LPDDR4__DENALI_CTL_326__SWLVL_LOAD_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_326__SWLVL_LOAD_SHIFT 16U +#define LPDDR4__DENALI_CTL_326__SWLVL_LOAD_WIDTH 1U +#define LPDDR4__DENALI_CTL_326__SWLVL_LOAD_WOCLR 0U +#define LPDDR4__DENALI_CTL_326__SWLVL_LOAD_WOSET 0U +#define LPDDR4__SWLVL_LOAD__REG DENALI_CTL_326 +#define LPDDR4__SWLVL_LOAD__FLD LPDDR4__DENALI_CTL_326__SWLVL_LOAD + +#define LPDDR4__DENALI_CTL_326__SWLVL_START_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_326__SWLVL_START_SHIFT 24U +#define LPDDR4__DENALI_CTL_326__SWLVL_START_WIDTH 1U +#define LPDDR4__DENALI_CTL_326__SWLVL_START_WOCLR 0U +#define LPDDR4__DENALI_CTL_326__SWLVL_START_WOSET 0U +#define LPDDR4__SWLVL_START__REG DENALI_CTL_326 +#define LPDDR4__SWLVL_START__FLD LPDDR4__DENALI_CTL_326__SWLVL_START + +#define LPDDR4__DENALI_CTL_327_READ_MASK 0x01010100U +#define LPDDR4__DENALI_CTL_327_WRITE_MASK 0x01010100U +#define LPDDR4__DENALI_CTL_327__SWLVL_EXIT_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_327__SWLVL_EXIT_SHIFT 0U +#define LPDDR4__DENALI_CTL_327__SWLVL_EXIT_WIDTH 1U +#define LPDDR4__DENALI_CTL_327__SWLVL_EXIT_WOCLR 0U +#define LPDDR4__DENALI_CTL_327__SWLVL_EXIT_WOSET 0U +#define LPDDR4__SWLVL_EXIT__REG DENALI_CTL_327 +#define LPDDR4__SWLVL_EXIT__FLD LPDDR4__DENALI_CTL_327__SWLVL_EXIT + +#define LPDDR4__DENALI_CTL_327__SWLVL_OP_DONE_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_327__SWLVL_OP_DONE_SHIFT 8U +#define LPDDR4__DENALI_CTL_327__SWLVL_OP_DONE_WIDTH 1U +#define LPDDR4__DENALI_CTL_327__SWLVL_OP_DONE_WOCLR 0U +#define LPDDR4__DENALI_CTL_327__SWLVL_OP_DONE_WOSET 0U +#define LPDDR4__SWLVL_OP_DONE__REG DENALI_CTL_327 +#define LPDDR4__SWLVL_OP_DONE__FLD LPDDR4__DENALI_CTL_327__SWLVL_OP_DONE + +#define LPDDR4__DENALI_CTL_327__SWLVL_RESP_0_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_327__SWLVL_RESP_0_SHIFT 16U +#define LPDDR4__DENALI_CTL_327__SWLVL_RESP_0_WIDTH 1U +#define LPDDR4__DENALI_CTL_327__SWLVL_RESP_0_WOCLR 0U +#define LPDDR4__DENALI_CTL_327__SWLVL_RESP_0_WOSET 0U +#define LPDDR4__SWLVL_RESP_0__REG DENALI_CTL_327 +#define LPDDR4__SWLVL_RESP_0__FLD LPDDR4__DENALI_CTL_327__SWLVL_RESP_0 + +#define LPDDR4__DENALI_CTL_327__SWLVL_RESP_1_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_327__SWLVL_RESP_1_SHIFT 24U +#define LPDDR4__DENALI_CTL_327__SWLVL_RESP_1_WIDTH 1U +#define LPDDR4__DENALI_CTL_327__SWLVL_RESP_1_WOCLR 0U +#define LPDDR4__DENALI_CTL_327__SWLVL_RESP_1_WOSET 0U +#define LPDDR4__SWLVL_RESP_1__REG DENALI_CTL_327 +#define LPDDR4__SWLVL_RESP_1__FLD LPDDR4__DENALI_CTL_327__SWLVL_RESP_1 + +#define LPDDR4__DENALI_CTL_328_READ_MASK 0x00010101U +#define LPDDR4__DENALI_CTL_328_WRITE_MASK 0x00010101U +#define LPDDR4__DENALI_CTL_328__SWLVL_RESP_2_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_328__SWLVL_RESP_2_SHIFT 0U +#define LPDDR4__DENALI_CTL_328__SWLVL_RESP_2_WIDTH 1U +#define LPDDR4__DENALI_CTL_328__SWLVL_RESP_2_WOCLR 0U +#define LPDDR4__DENALI_CTL_328__SWLVL_RESP_2_WOSET 0U +#define LPDDR4__SWLVL_RESP_2__REG DENALI_CTL_328 +#define LPDDR4__SWLVL_RESP_2__FLD LPDDR4__DENALI_CTL_328__SWLVL_RESP_2 + +#define LPDDR4__DENALI_CTL_328__SWLVL_RESP_3_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_328__SWLVL_RESP_3_SHIFT 8U +#define LPDDR4__DENALI_CTL_328__SWLVL_RESP_3_WIDTH 1U +#define LPDDR4__DENALI_CTL_328__SWLVL_RESP_3_WOCLR 0U +#define LPDDR4__DENALI_CTL_328__SWLVL_RESP_3_WOSET 0U +#define LPDDR4__SWLVL_RESP_3__REG DENALI_CTL_328 +#define LPDDR4__SWLVL_RESP_3__FLD LPDDR4__DENALI_CTL_328__SWLVL_RESP_3 + +#define LPDDR4__DENALI_CTL_328__PHYUPD_APPEND_EN_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_328__PHYUPD_APPEND_EN_SHIFT 16U +#define LPDDR4__DENALI_CTL_328__PHYUPD_APPEND_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_328__PHYUPD_APPEND_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_328__PHYUPD_APPEND_EN_WOSET 0U +#define LPDDR4__PHYUPD_APPEND_EN__REG DENALI_CTL_328 +#define LPDDR4__PHYUPD_APPEND_EN__FLD LPDDR4__DENALI_CTL_328__PHYUPD_APPEND_EN + +#define LPDDR4__DENALI_CTL_328__WRLVL_REQ_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_328__WRLVL_REQ_SHIFT 24U +#define LPDDR4__DENALI_CTL_328__WRLVL_REQ_WIDTH 1U +#define LPDDR4__DENALI_CTL_328__WRLVL_REQ_WOCLR 0U +#define LPDDR4__DENALI_CTL_328__WRLVL_REQ_WOSET 0U +#define LPDDR4__WRLVL_REQ__REG DENALI_CTL_328 +#define LPDDR4__WRLVL_REQ__FLD LPDDR4__DENALI_CTL_328__WRLVL_REQ + +#define LPDDR4__DENALI_CTL_329_READ_MASK 0x013F3F01U +#define LPDDR4__DENALI_CTL_329_WRITE_MASK 0x013F3F01U +#define LPDDR4__DENALI_CTL_329__WRLVL_CS_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_329__WRLVL_CS_SHIFT 0U +#define LPDDR4__DENALI_CTL_329__WRLVL_CS_WIDTH 1U +#define LPDDR4__DENALI_CTL_329__WRLVL_CS_WOCLR 0U +#define LPDDR4__DENALI_CTL_329__WRLVL_CS_WOSET 0U +#define LPDDR4__WRLVL_CS__REG DENALI_CTL_329 +#define LPDDR4__WRLVL_CS__FLD LPDDR4__DENALI_CTL_329__WRLVL_CS + +#define LPDDR4__DENALI_CTL_329__WLDQSEN_MASK 0x00003F00U +#define LPDDR4__DENALI_CTL_329__WLDQSEN_SHIFT 8U +#define LPDDR4__DENALI_CTL_329__WLDQSEN_WIDTH 6U +#define LPDDR4__WLDQSEN__REG DENALI_CTL_329 +#define LPDDR4__WLDQSEN__FLD LPDDR4__DENALI_CTL_329__WLDQSEN + +#define LPDDR4__DENALI_CTL_329__WLMRD_MASK 0x003F0000U +#define LPDDR4__DENALI_CTL_329__WLMRD_SHIFT 16U +#define LPDDR4__DENALI_CTL_329__WLMRD_WIDTH 6U +#define LPDDR4__WLMRD__REG DENALI_CTL_329 +#define LPDDR4__WLMRD__FLD LPDDR4__DENALI_CTL_329__WLMRD + +#define LPDDR4__DENALI_CTL_329__WRLVL_EN_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_329__WRLVL_EN_SHIFT 24U +#define LPDDR4__DENALI_CTL_329__WRLVL_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_329__WRLVL_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_329__WRLVL_EN_WOSET 0U +#define LPDDR4__WRLVL_EN__REG DENALI_CTL_329 +#define LPDDR4__WRLVL_EN__FLD LPDDR4__DENALI_CTL_329__WRLVL_EN + +#define LPDDR4__DENALI_CTL_330_READ_MASK 0x0F010101U +#define LPDDR4__DENALI_CTL_330_WRITE_MASK 0x0F010101U +#define LPDDR4__DENALI_CTL_330__DFI_PHY_WRLVL_MODE_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_330__DFI_PHY_WRLVL_MODE_SHIFT 0U +#define LPDDR4__DENALI_CTL_330__DFI_PHY_WRLVL_MODE_WIDTH 1U +#define LPDDR4__DENALI_CTL_330__DFI_PHY_WRLVL_MODE_WOCLR 0U +#define LPDDR4__DENALI_CTL_330__DFI_PHY_WRLVL_MODE_WOSET 0U +#define LPDDR4__DFI_PHY_WRLVL_MODE__REG DENALI_CTL_330 +#define LPDDR4__DFI_PHY_WRLVL_MODE__FLD LPDDR4__DENALI_CTL_330__DFI_PHY_WRLVL_MODE + +#define LPDDR4__DENALI_CTL_330__WRLVL_PERIODIC_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_330__WRLVL_PERIODIC_SHIFT 8U +#define LPDDR4__DENALI_CTL_330__WRLVL_PERIODIC_WIDTH 1U +#define LPDDR4__DENALI_CTL_330__WRLVL_PERIODIC_WOCLR 0U +#define LPDDR4__DENALI_CTL_330__WRLVL_PERIODIC_WOSET 0U +#define LPDDR4__WRLVL_PERIODIC__REG DENALI_CTL_330 +#define LPDDR4__WRLVL_PERIODIC__FLD LPDDR4__DENALI_CTL_330__WRLVL_PERIODIC + +#define LPDDR4__DENALI_CTL_330__WRLVL_ON_SREF_EXIT_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_330__WRLVL_ON_SREF_EXIT_SHIFT 16U +#define LPDDR4__DENALI_CTL_330__WRLVL_ON_SREF_EXIT_WIDTH 1U +#define LPDDR4__DENALI_CTL_330__WRLVL_ON_SREF_EXIT_WOCLR 0U +#define LPDDR4__DENALI_CTL_330__WRLVL_ON_SREF_EXIT_WOSET 0U +#define LPDDR4__WRLVL_ON_SREF_EXIT__REG DENALI_CTL_330 +#define LPDDR4__WRLVL_ON_SREF_EXIT__FLD LPDDR4__DENALI_CTL_330__WRLVL_ON_SREF_EXIT + +#define LPDDR4__DENALI_CTL_330__WRLVL_RESP_MASK_MASK 0x0F000000U +#define LPDDR4__DENALI_CTL_330__WRLVL_RESP_MASK_SHIFT 24U +#define LPDDR4__DENALI_CTL_330__WRLVL_RESP_MASK_WIDTH 4U +#define LPDDR4__WRLVL_RESP_MASK__REG DENALI_CTL_330 +#define LPDDR4__WRLVL_RESP_MASK__FLD LPDDR4__DENALI_CTL_330__WRLVL_RESP_MASK + +#define LPDDR4__DENALI_CTL_331_READ_MASK 0x07030101U +#define LPDDR4__DENALI_CTL_331_WRITE_MASK 0x07030101U +#define LPDDR4__DENALI_CTL_331__WRLVL_AREF_EN_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_331__WRLVL_AREF_EN_SHIFT 0U +#define LPDDR4__DENALI_CTL_331__WRLVL_AREF_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_331__WRLVL_AREF_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_331__WRLVL_AREF_EN_WOSET 0U +#define LPDDR4__WRLVL_AREF_EN__REG DENALI_CTL_331 +#define LPDDR4__WRLVL_AREF_EN__FLD LPDDR4__DENALI_CTL_331__WRLVL_AREF_EN + +#define LPDDR4__DENALI_CTL_331__WRLVL_ROTATE_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_331__WRLVL_ROTATE_SHIFT 8U +#define LPDDR4__DENALI_CTL_331__WRLVL_ROTATE_WIDTH 1U +#define LPDDR4__DENALI_CTL_331__WRLVL_ROTATE_WOCLR 0U +#define LPDDR4__DENALI_CTL_331__WRLVL_ROTATE_WOSET 0U +#define LPDDR4__WRLVL_ROTATE__REG DENALI_CTL_331 +#define LPDDR4__WRLVL_ROTATE__FLD LPDDR4__DENALI_CTL_331__WRLVL_ROTATE + +#define LPDDR4__DENALI_CTL_331__WRLVL_CS_MAP_MASK 0x00030000U +#define LPDDR4__DENALI_CTL_331__WRLVL_CS_MAP_SHIFT 16U +#define LPDDR4__DENALI_CTL_331__WRLVL_CS_MAP_WIDTH 2U +#define LPDDR4__WRLVL_CS_MAP__REG DENALI_CTL_331 +#define LPDDR4__WRLVL_CS_MAP__FLD LPDDR4__DENALI_CTL_331__WRLVL_CS_MAP + +#define LPDDR4__DENALI_CTL_331__WRLVL_ERROR_STATUS_MASK 0x07000000U +#define LPDDR4__DENALI_CTL_331__WRLVL_ERROR_STATUS_SHIFT 24U +#define LPDDR4__DENALI_CTL_331__WRLVL_ERROR_STATUS_WIDTH 3U +#define LPDDR4__WRLVL_ERROR_STATUS__REG DENALI_CTL_331 +#define LPDDR4__WRLVL_ERROR_STATUS__FLD LPDDR4__DENALI_CTL_331__WRLVL_ERROR_STATUS + +#define LPDDR4__DENALI_CTL_332_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_332_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_332__WRLVL_NORM_THRESHOLD_F0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_332__WRLVL_NORM_THRESHOLD_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_332__WRLVL_NORM_THRESHOLD_F0_WIDTH 16U +#define LPDDR4__WRLVL_NORM_THRESHOLD_F0__REG DENALI_CTL_332 +#define LPDDR4__WRLVL_NORM_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_332__WRLVL_NORM_THRESHOLD_F0 + +#define LPDDR4__DENALI_CTL_332__WRLVL_HIGH_THRESHOLD_F0_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_332__WRLVL_HIGH_THRESHOLD_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_332__WRLVL_HIGH_THRESHOLD_F0_WIDTH 16U +#define LPDDR4__WRLVL_HIGH_THRESHOLD_F0__REG DENALI_CTL_332 +#define LPDDR4__WRLVL_HIGH_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_332__WRLVL_HIGH_THRESHOLD_F0 + +#define LPDDR4__DENALI_CTL_333_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_333_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_333__WRLVL_TIMEOUT_F0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_333__WRLVL_TIMEOUT_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_333__WRLVL_TIMEOUT_F0_WIDTH 16U +#define LPDDR4__WRLVL_TIMEOUT_F0__REG DENALI_CTL_333 +#define LPDDR4__WRLVL_TIMEOUT_F0__FLD LPDDR4__DENALI_CTL_333__WRLVL_TIMEOUT_F0 + +#define LPDDR4__DENALI_CTL_333__WRLVL_SW_PROMOTE_THRESHOLD_F0_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_333__WRLVL_SW_PROMOTE_THRESHOLD_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_333__WRLVL_SW_PROMOTE_THRESHOLD_F0_WIDTH 16U +#define LPDDR4__WRLVL_SW_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_333 +#define LPDDR4__WRLVL_SW_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_333__WRLVL_SW_PROMOTE_THRESHOLD_F0 + +#define LPDDR4__DENALI_CTL_334_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_334_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_334__WRLVL_DFI_PROMOTE_THRESHOLD_F0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_334__WRLVL_DFI_PROMOTE_THRESHOLD_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_334__WRLVL_DFI_PROMOTE_THRESHOLD_F0_WIDTH 16U +#define LPDDR4__WRLVL_DFI_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_334 +#define LPDDR4__WRLVL_DFI_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_334__WRLVL_DFI_PROMOTE_THRESHOLD_F0 + +#define LPDDR4__DENALI_CTL_334__WRLVL_NORM_THRESHOLD_F1_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_334__WRLVL_NORM_THRESHOLD_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_334__WRLVL_NORM_THRESHOLD_F1_WIDTH 16U +#define LPDDR4__WRLVL_NORM_THRESHOLD_F1__REG DENALI_CTL_334 +#define LPDDR4__WRLVL_NORM_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_334__WRLVL_NORM_THRESHOLD_F1 + +#define LPDDR4__DENALI_CTL_335_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_335_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_335__WRLVL_HIGH_THRESHOLD_F1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_335__WRLVL_HIGH_THRESHOLD_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_335__WRLVL_HIGH_THRESHOLD_F1_WIDTH 16U +#define LPDDR4__WRLVL_HIGH_THRESHOLD_F1__REG DENALI_CTL_335 +#define LPDDR4__WRLVL_HIGH_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_335__WRLVL_HIGH_THRESHOLD_F1 + +#define LPDDR4__DENALI_CTL_335__WRLVL_TIMEOUT_F1_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_335__WRLVL_TIMEOUT_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_335__WRLVL_TIMEOUT_F1_WIDTH 16U +#define LPDDR4__WRLVL_TIMEOUT_F1__REG DENALI_CTL_335 +#define LPDDR4__WRLVL_TIMEOUT_F1__FLD LPDDR4__DENALI_CTL_335__WRLVL_TIMEOUT_F1 + +#define LPDDR4__DENALI_CTL_336_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_336_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_336__WRLVL_SW_PROMOTE_THRESHOLD_F1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_336__WRLVL_SW_PROMOTE_THRESHOLD_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_336__WRLVL_SW_PROMOTE_THRESHOLD_F1_WIDTH 16U +#define LPDDR4__WRLVL_SW_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_336 +#define LPDDR4__WRLVL_SW_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_336__WRLVL_SW_PROMOTE_THRESHOLD_F1 + +#define LPDDR4__DENALI_CTL_336__WRLVL_DFI_PROMOTE_THRESHOLD_F1_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_336__WRLVL_DFI_PROMOTE_THRESHOLD_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_336__WRLVL_DFI_PROMOTE_THRESHOLD_F1_WIDTH 16U +#define LPDDR4__WRLVL_DFI_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_336 +#define LPDDR4__WRLVL_DFI_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_336__WRLVL_DFI_PROMOTE_THRESHOLD_F1 + +#define LPDDR4__DENALI_CTL_337_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_337_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_337__WRLVL_NORM_THRESHOLD_F2_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_337__WRLVL_NORM_THRESHOLD_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_337__WRLVL_NORM_THRESHOLD_F2_WIDTH 16U +#define LPDDR4__WRLVL_NORM_THRESHOLD_F2__REG DENALI_CTL_337 +#define LPDDR4__WRLVL_NORM_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_337__WRLVL_NORM_THRESHOLD_F2 + +#define LPDDR4__DENALI_CTL_337__WRLVL_HIGH_THRESHOLD_F2_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_337__WRLVL_HIGH_THRESHOLD_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_337__WRLVL_HIGH_THRESHOLD_F2_WIDTH 16U +#define LPDDR4__WRLVL_HIGH_THRESHOLD_F2__REG DENALI_CTL_337 +#define LPDDR4__WRLVL_HIGH_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_337__WRLVL_HIGH_THRESHOLD_F2 + +#define LPDDR4__DENALI_CTL_338_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_338_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_338__WRLVL_TIMEOUT_F2_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_338__WRLVL_TIMEOUT_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_338__WRLVL_TIMEOUT_F2_WIDTH 16U +#define LPDDR4__WRLVL_TIMEOUT_F2__REG DENALI_CTL_338 +#define LPDDR4__WRLVL_TIMEOUT_F2__FLD LPDDR4__DENALI_CTL_338__WRLVL_TIMEOUT_F2 + +#define LPDDR4__DENALI_CTL_338__WRLVL_SW_PROMOTE_THRESHOLD_F2_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_338__WRLVL_SW_PROMOTE_THRESHOLD_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_338__WRLVL_SW_PROMOTE_THRESHOLD_F2_WIDTH 16U +#define LPDDR4__WRLVL_SW_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_338 +#define LPDDR4__WRLVL_SW_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_338__WRLVL_SW_PROMOTE_THRESHOLD_F2 + +#define LPDDR4__DENALI_CTL_339_READ_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_339_WRITE_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_339__WRLVL_DFI_PROMOTE_THRESHOLD_F2_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_339__WRLVL_DFI_PROMOTE_THRESHOLD_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_339__WRLVL_DFI_PROMOTE_THRESHOLD_F2_WIDTH 16U +#define LPDDR4__WRLVL_DFI_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_339 +#define LPDDR4__WRLVL_DFI_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_339__WRLVL_DFI_PROMOTE_THRESHOLD_F2 + +#define LPDDR4__DENALI_CTL_339__RDLVL_REQ_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_339__RDLVL_REQ_SHIFT 16U +#define LPDDR4__DENALI_CTL_339__RDLVL_REQ_WIDTH 1U +#define LPDDR4__DENALI_CTL_339__RDLVL_REQ_WOCLR 0U +#define LPDDR4__DENALI_CTL_339__RDLVL_REQ_WOSET 0U +#define LPDDR4__RDLVL_REQ__REG DENALI_CTL_339 +#define LPDDR4__RDLVL_REQ__FLD LPDDR4__DENALI_CTL_339__RDLVL_REQ + +#define LPDDR4__DENALI_CTL_339__RDLVL_GATE_REQ_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_339__RDLVL_GATE_REQ_SHIFT 24U +#define LPDDR4__DENALI_CTL_339__RDLVL_GATE_REQ_WIDTH 1U +#define LPDDR4__DENALI_CTL_339__RDLVL_GATE_REQ_WOCLR 0U +#define LPDDR4__DENALI_CTL_339__RDLVL_GATE_REQ_WOSET 0U +#define LPDDR4__RDLVL_GATE_REQ__REG DENALI_CTL_339 +#define LPDDR4__RDLVL_GATE_REQ__FLD LPDDR4__DENALI_CTL_339__RDLVL_GATE_REQ + +#define LPDDR4__DENALI_CTL_340_READ_MASK 0x010F0F01U +#define LPDDR4__DENALI_CTL_340_WRITE_MASK 0x010F0F01U +#define LPDDR4__DENALI_CTL_340__RDLVL_CS_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_340__RDLVL_CS_SHIFT 0U +#define LPDDR4__DENALI_CTL_340__RDLVL_CS_WIDTH 1U +#define LPDDR4__DENALI_CTL_340__RDLVL_CS_WOCLR 0U +#define LPDDR4__DENALI_CTL_340__RDLVL_CS_WOSET 0U +#define LPDDR4__RDLVL_CS__REG DENALI_CTL_340 +#define LPDDR4__RDLVL_CS__FLD LPDDR4__DENALI_CTL_340__RDLVL_CS + +#define LPDDR4__DENALI_CTL_340__RDLVL_SEQ_EN_MASK 0x00000F00U +#define LPDDR4__DENALI_CTL_340__RDLVL_SEQ_EN_SHIFT 8U +#define LPDDR4__DENALI_CTL_340__RDLVL_SEQ_EN_WIDTH 4U +#define LPDDR4__RDLVL_SEQ_EN__REG DENALI_CTL_340 +#define LPDDR4__RDLVL_SEQ_EN__FLD LPDDR4__DENALI_CTL_340__RDLVL_SEQ_EN + +#define LPDDR4__DENALI_CTL_340__RDLVL_GATE_SEQ_EN_MASK 0x000F0000U +#define LPDDR4__DENALI_CTL_340__RDLVL_GATE_SEQ_EN_SHIFT 16U +#define LPDDR4__DENALI_CTL_340__RDLVL_GATE_SEQ_EN_WIDTH 4U +#define LPDDR4__RDLVL_GATE_SEQ_EN__REG DENALI_CTL_340 +#define LPDDR4__RDLVL_GATE_SEQ_EN__FLD LPDDR4__DENALI_CTL_340__RDLVL_GATE_SEQ_EN + +#define LPDDR4__DENALI_CTL_340__DFI_PHY_RDLVL_MODE_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_340__DFI_PHY_RDLVL_MODE_SHIFT 24U +#define LPDDR4__DENALI_CTL_340__DFI_PHY_RDLVL_MODE_WIDTH 1U +#define LPDDR4__DENALI_CTL_340__DFI_PHY_RDLVL_MODE_WOCLR 0U +#define LPDDR4__DENALI_CTL_340__DFI_PHY_RDLVL_MODE_WOSET 0U +#define LPDDR4__DFI_PHY_RDLVL_MODE__REG DENALI_CTL_340 +#define LPDDR4__DFI_PHY_RDLVL_MODE__FLD LPDDR4__DENALI_CTL_340__DFI_PHY_RDLVL_MODE + +#define LPDDR4__DENALI_CTL_341_READ_MASK 0x01010101U +#define LPDDR4__DENALI_CTL_341_WRITE_MASK 0x01010101U +#define LPDDR4__DENALI_CTL_341__DFI_PHY_RDLVL_GATE_MODE_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_341__DFI_PHY_RDLVL_GATE_MODE_SHIFT 0U +#define LPDDR4__DENALI_CTL_341__DFI_PHY_RDLVL_GATE_MODE_WIDTH 1U +#define LPDDR4__DENALI_CTL_341__DFI_PHY_RDLVL_GATE_MODE_WOCLR 0U +#define LPDDR4__DENALI_CTL_341__DFI_PHY_RDLVL_GATE_MODE_WOSET 0U +#define LPDDR4__DFI_PHY_RDLVL_GATE_MODE__REG DENALI_CTL_341 +#define LPDDR4__DFI_PHY_RDLVL_GATE_MODE__FLD LPDDR4__DENALI_CTL_341__DFI_PHY_RDLVL_GATE_MODE + +#define LPDDR4__DENALI_CTL_341__RDLVL_PERIODIC_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_341__RDLVL_PERIODIC_SHIFT 8U +#define LPDDR4__DENALI_CTL_341__RDLVL_PERIODIC_WIDTH 1U +#define LPDDR4__DENALI_CTL_341__RDLVL_PERIODIC_WOCLR 0U +#define LPDDR4__DENALI_CTL_341__RDLVL_PERIODIC_WOSET 0U +#define LPDDR4__RDLVL_PERIODIC__REG DENALI_CTL_341 +#define LPDDR4__RDLVL_PERIODIC__FLD LPDDR4__DENALI_CTL_341__RDLVL_PERIODIC + +#define LPDDR4__DENALI_CTL_341__RDLVL_ON_SREF_EXIT_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_341__RDLVL_ON_SREF_EXIT_SHIFT 16U +#define LPDDR4__DENALI_CTL_341__RDLVL_ON_SREF_EXIT_WIDTH 1U +#define LPDDR4__DENALI_CTL_341__RDLVL_ON_SREF_EXIT_WOCLR 0U +#define LPDDR4__DENALI_CTL_341__RDLVL_ON_SREF_EXIT_WOSET 0U +#define LPDDR4__RDLVL_ON_SREF_EXIT__REG DENALI_CTL_341 +#define LPDDR4__RDLVL_ON_SREF_EXIT__FLD LPDDR4__DENALI_CTL_341__RDLVL_ON_SREF_EXIT + +#define LPDDR4__DENALI_CTL_341__RDLVL_GATE_PERIODIC_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_341__RDLVL_GATE_PERIODIC_SHIFT 24U +#define LPDDR4__DENALI_CTL_341__RDLVL_GATE_PERIODIC_WIDTH 1U +#define LPDDR4__DENALI_CTL_341__RDLVL_GATE_PERIODIC_WOCLR 0U +#define LPDDR4__DENALI_CTL_341__RDLVL_GATE_PERIODIC_WOSET 0U +#define LPDDR4__RDLVL_GATE_PERIODIC__REG DENALI_CTL_341 +#define LPDDR4__RDLVL_GATE_PERIODIC__FLD LPDDR4__DENALI_CTL_341__RDLVL_GATE_PERIODIC + +#define LPDDR4__DENALI_CTL_342_READ_MASK 0x01010101U +#define LPDDR4__DENALI_CTL_342_WRITE_MASK 0x01010101U +#define LPDDR4__DENALI_CTL_342__RDLVL_GATE_ON_SREF_EXIT_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_342__RDLVL_GATE_ON_SREF_EXIT_SHIFT 0U +#define LPDDR4__DENALI_CTL_342__RDLVL_GATE_ON_SREF_EXIT_WIDTH 1U +#define LPDDR4__DENALI_CTL_342__RDLVL_GATE_ON_SREF_EXIT_WOCLR 0U +#define LPDDR4__DENALI_CTL_342__RDLVL_GATE_ON_SREF_EXIT_WOSET 0U +#define LPDDR4__RDLVL_GATE_ON_SREF_EXIT__REG DENALI_CTL_342 +#define LPDDR4__RDLVL_GATE_ON_SREF_EXIT__FLD LPDDR4__DENALI_CTL_342__RDLVL_GATE_ON_SREF_EXIT + +#define LPDDR4__DENALI_CTL_342__RDLVL_AREF_EN_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_342__RDLVL_AREF_EN_SHIFT 8U +#define LPDDR4__DENALI_CTL_342__RDLVL_AREF_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_342__RDLVL_AREF_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_342__RDLVL_AREF_EN_WOSET 0U +#define LPDDR4__RDLVL_AREF_EN__REG DENALI_CTL_342 +#define LPDDR4__RDLVL_AREF_EN__FLD LPDDR4__DENALI_CTL_342__RDLVL_AREF_EN + +#define LPDDR4__DENALI_CTL_342__RDLVL_GATE_AREF_EN_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_342__RDLVL_GATE_AREF_EN_SHIFT 16U +#define LPDDR4__DENALI_CTL_342__RDLVL_GATE_AREF_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_342__RDLVL_GATE_AREF_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_342__RDLVL_GATE_AREF_EN_WOSET 0U +#define LPDDR4__RDLVL_GATE_AREF_EN__REG DENALI_CTL_342 +#define LPDDR4__RDLVL_GATE_AREF_EN__FLD LPDDR4__DENALI_CTL_342__RDLVL_GATE_AREF_EN + +#define LPDDR4__DENALI_CTL_342__MC_RESERVED29_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_342__MC_RESERVED29_SHIFT 24U +#define LPDDR4__DENALI_CTL_342__MC_RESERVED29_WIDTH 1U +#define LPDDR4__DENALI_CTL_342__MC_RESERVED29_WOCLR 0U +#define LPDDR4__DENALI_CTL_342__MC_RESERVED29_WOSET 0U +#define LPDDR4__MC_RESERVED29__REG DENALI_CTL_342 +#define LPDDR4__MC_RESERVED29__FLD LPDDR4__DENALI_CTL_342__MC_RESERVED29 + +#define LPDDR4__DENALI_CTL_343_READ_MASK 0x03030101U +#define LPDDR4__DENALI_CTL_343_WRITE_MASK 0x03030101U +#define LPDDR4__DENALI_CTL_343__RDLVL_ROTATE_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_343__RDLVL_ROTATE_SHIFT 0U +#define LPDDR4__DENALI_CTL_343__RDLVL_ROTATE_WIDTH 1U +#define LPDDR4__DENALI_CTL_343__RDLVL_ROTATE_WOCLR 0U +#define LPDDR4__DENALI_CTL_343__RDLVL_ROTATE_WOSET 0U +#define LPDDR4__RDLVL_ROTATE__REG DENALI_CTL_343 +#define LPDDR4__RDLVL_ROTATE__FLD LPDDR4__DENALI_CTL_343__RDLVL_ROTATE + +#define LPDDR4__DENALI_CTL_343__RDLVL_GATE_ROTATE_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_343__RDLVL_GATE_ROTATE_SHIFT 8U +#define LPDDR4__DENALI_CTL_343__RDLVL_GATE_ROTATE_WIDTH 1U +#define LPDDR4__DENALI_CTL_343__RDLVL_GATE_ROTATE_WOCLR 0U +#define LPDDR4__DENALI_CTL_343__RDLVL_GATE_ROTATE_WOSET 0U +#define LPDDR4__RDLVL_GATE_ROTATE__REG DENALI_CTL_343 +#define LPDDR4__RDLVL_GATE_ROTATE__FLD LPDDR4__DENALI_CTL_343__RDLVL_GATE_ROTATE + +#define LPDDR4__DENALI_CTL_343__RDLVL_CS_MAP_MASK 0x00030000U +#define LPDDR4__DENALI_CTL_343__RDLVL_CS_MAP_SHIFT 16U +#define LPDDR4__DENALI_CTL_343__RDLVL_CS_MAP_WIDTH 2U +#define LPDDR4__RDLVL_CS_MAP__REG DENALI_CTL_343 +#define LPDDR4__RDLVL_CS_MAP__FLD LPDDR4__DENALI_CTL_343__RDLVL_CS_MAP + +#define LPDDR4__DENALI_CTL_343__RDLVL_GATE_CS_MAP_MASK 0x03000000U +#define LPDDR4__DENALI_CTL_343__RDLVL_GATE_CS_MAP_SHIFT 24U +#define LPDDR4__DENALI_CTL_343__RDLVL_GATE_CS_MAP_WIDTH 2U +#define LPDDR4__RDLVL_GATE_CS_MAP__REG DENALI_CTL_343 +#define LPDDR4__RDLVL_GATE_CS_MAP__FLD LPDDR4__DENALI_CTL_343__RDLVL_GATE_CS_MAP + +#define LPDDR4__DENALI_CTL_344_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_344_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_344__RDLVL_NORM_THRESHOLD_F0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_344__RDLVL_NORM_THRESHOLD_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_344__RDLVL_NORM_THRESHOLD_F0_WIDTH 16U +#define LPDDR4__RDLVL_NORM_THRESHOLD_F0__REG DENALI_CTL_344 +#define LPDDR4__RDLVL_NORM_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_344__RDLVL_NORM_THRESHOLD_F0 + +#define LPDDR4__DENALI_CTL_344__RDLVL_HIGH_THRESHOLD_F0_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_344__RDLVL_HIGH_THRESHOLD_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_344__RDLVL_HIGH_THRESHOLD_F0_WIDTH 16U +#define LPDDR4__RDLVL_HIGH_THRESHOLD_F0__REG DENALI_CTL_344 +#define LPDDR4__RDLVL_HIGH_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_344__RDLVL_HIGH_THRESHOLD_F0 + +#define LPDDR4__DENALI_CTL_345_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_345_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_345__RDLVL_TIMEOUT_F0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_345__RDLVL_TIMEOUT_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_345__RDLVL_TIMEOUT_F0_WIDTH 16U +#define LPDDR4__RDLVL_TIMEOUT_F0__REG DENALI_CTL_345 +#define LPDDR4__RDLVL_TIMEOUT_F0__FLD LPDDR4__DENALI_CTL_345__RDLVL_TIMEOUT_F0 + +#define LPDDR4__DENALI_CTL_345__RDLVL_SW_PROMOTE_THRESHOLD_F0_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_345__RDLVL_SW_PROMOTE_THRESHOLD_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_345__RDLVL_SW_PROMOTE_THRESHOLD_F0_WIDTH 16U +#define LPDDR4__RDLVL_SW_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_345 +#define LPDDR4__RDLVL_SW_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_345__RDLVL_SW_PROMOTE_THRESHOLD_F0 + +#define LPDDR4__DENALI_CTL_346_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_346_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_346__RDLVL_DFI_PROMOTE_THRESHOLD_F0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_346__RDLVL_DFI_PROMOTE_THRESHOLD_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_346__RDLVL_DFI_PROMOTE_THRESHOLD_F0_WIDTH 16U +#define LPDDR4__RDLVL_DFI_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_346 +#define LPDDR4__RDLVL_DFI_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_346__RDLVL_DFI_PROMOTE_THRESHOLD_F0 + +#define LPDDR4__DENALI_CTL_346__RDLVL_GATE_NORM_THRESHOLD_F0_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_346__RDLVL_GATE_NORM_THRESHOLD_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_346__RDLVL_GATE_NORM_THRESHOLD_F0_WIDTH 16U +#define LPDDR4__RDLVL_GATE_NORM_THRESHOLD_F0__REG DENALI_CTL_346 +#define LPDDR4__RDLVL_GATE_NORM_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_346__RDLVL_GATE_NORM_THRESHOLD_F0 + +#define LPDDR4__DENALI_CTL_347_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_347_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_347__RDLVL_GATE_HIGH_THRESHOLD_F0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_347__RDLVL_GATE_HIGH_THRESHOLD_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_347__RDLVL_GATE_HIGH_THRESHOLD_F0_WIDTH 16U +#define LPDDR4__RDLVL_GATE_HIGH_THRESHOLD_F0__REG DENALI_CTL_347 +#define LPDDR4__RDLVL_GATE_HIGH_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_347__RDLVL_GATE_HIGH_THRESHOLD_F0 + +#define LPDDR4__DENALI_CTL_347__RDLVL_GATE_TIMEOUT_F0_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_347__RDLVL_GATE_TIMEOUT_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_347__RDLVL_GATE_TIMEOUT_F0_WIDTH 16U +#define LPDDR4__RDLVL_GATE_TIMEOUT_F0__REG DENALI_CTL_347 +#define LPDDR4__RDLVL_GATE_TIMEOUT_F0__FLD LPDDR4__DENALI_CTL_347__RDLVL_GATE_TIMEOUT_F0 + +#define LPDDR4__DENALI_CTL_348_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_348_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_348__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_348__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_348__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F0_WIDTH 16U +#define LPDDR4__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_348 +#define LPDDR4__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_348__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F0 + +#define LPDDR4__DENALI_CTL_348__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F0_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_348__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_348__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F0_WIDTH 16U +#define LPDDR4__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_348 +#define LPDDR4__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_348__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F0 + +#define LPDDR4__DENALI_CTL_349_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_349_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_349__RDLVL_NORM_THRESHOLD_F1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_349__RDLVL_NORM_THRESHOLD_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_349__RDLVL_NORM_THRESHOLD_F1_WIDTH 16U +#define LPDDR4__RDLVL_NORM_THRESHOLD_F1__REG DENALI_CTL_349 +#define LPDDR4__RDLVL_NORM_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_349__RDLVL_NORM_THRESHOLD_F1 + +#define LPDDR4__DENALI_CTL_349__RDLVL_HIGH_THRESHOLD_F1_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_349__RDLVL_HIGH_THRESHOLD_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_349__RDLVL_HIGH_THRESHOLD_F1_WIDTH 16U +#define LPDDR4__RDLVL_HIGH_THRESHOLD_F1__REG DENALI_CTL_349 +#define LPDDR4__RDLVL_HIGH_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_349__RDLVL_HIGH_THRESHOLD_F1 + +#define LPDDR4__DENALI_CTL_350_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_350_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_350__RDLVL_TIMEOUT_F1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_350__RDLVL_TIMEOUT_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_350__RDLVL_TIMEOUT_F1_WIDTH 16U +#define LPDDR4__RDLVL_TIMEOUT_F1__REG DENALI_CTL_350 +#define LPDDR4__RDLVL_TIMEOUT_F1__FLD LPDDR4__DENALI_CTL_350__RDLVL_TIMEOUT_F1 + +#define LPDDR4__DENALI_CTL_350__RDLVL_SW_PROMOTE_THRESHOLD_F1_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_350__RDLVL_SW_PROMOTE_THRESHOLD_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_350__RDLVL_SW_PROMOTE_THRESHOLD_F1_WIDTH 16U +#define LPDDR4__RDLVL_SW_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_350 +#define LPDDR4__RDLVL_SW_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_350__RDLVL_SW_PROMOTE_THRESHOLD_F1 + +#define LPDDR4__DENALI_CTL_351_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_351_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_351__RDLVL_DFI_PROMOTE_THRESHOLD_F1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_351__RDLVL_DFI_PROMOTE_THRESHOLD_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_351__RDLVL_DFI_PROMOTE_THRESHOLD_F1_WIDTH 16U +#define LPDDR4__RDLVL_DFI_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_351 +#define LPDDR4__RDLVL_DFI_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_351__RDLVL_DFI_PROMOTE_THRESHOLD_F1 + +#define LPDDR4__DENALI_CTL_351__RDLVL_GATE_NORM_THRESHOLD_F1_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_351__RDLVL_GATE_NORM_THRESHOLD_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_351__RDLVL_GATE_NORM_THRESHOLD_F1_WIDTH 16U +#define LPDDR4__RDLVL_GATE_NORM_THRESHOLD_F1__REG DENALI_CTL_351 +#define LPDDR4__RDLVL_GATE_NORM_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_351__RDLVL_GATE_NORM_THRESHOLD_F1 + +#define LPDDR4__DENALI_CTL_352_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_352_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_352__RDLVL_GATE_HIGH_THRESHOLD_F1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_352__RDLVL_GATE_HIGH_THRESHOLD_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_352__RDLVL_GATE_HIGH_THRESHOLD_F1_WIDTH 16U +#define LPDDR4__RDLVL_GATE_HIGH_THRESHOLD_F1__REG DENALI_CTL_352 +#define LPDDR4__RDLVL_GATE_HIGH_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_352__RDLVL_GATE_HIGH_THRESHOLD_F1 + +#define LPDDR4__DENALI_CTL_352__RDLVL_GATE_TIMEOUT_F1_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_352__RDLVL_GATE_TIMEOUT_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_352__RDLVL_GATE_TIMEOUT_F1_WIDTH 16U +#define LPDDR4__RDLVL_GATE_TIMEOUT_F1__REG DENALI_CTL_352 +#define LPDDR4__RDLVL_GATE_TIMEOUT_F1__FLD LPDDR4__DENALI_CTL_352__RDLVL_GATE_TIMEOUT_F1 + +#define LPDDR4__DENALI_CTL_353_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_353_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_353__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_353__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_353__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F1_WIDTH 16U +#define LPDDR4__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_353 +#define LPDDR4__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_353__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F1 + +#define LPDDR4__DENALI_CTL_353__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F1_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_353__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_353__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F1_WIDTH 16U +#define LPDDR4__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_353 +#define LPDDR4__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_353__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F1 + +#define LPDDR4__DENALI_CTL_354_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_354_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_354__RDLVL_NORM_THRESHOLD_F2_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_354__RDLVL_NORM_THRESHOLD_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_354__RDLVL_NORM_THRESHOLD_F2_WIDTH 16U +#define LPDDR4__RDLVL_NORM_THRESHOLD_F2__REG DENALI_CTL_354 +#define LPDDR4__RDLVL_NORM_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_354__RDLVL_NORM_THRESHOLD_F2 + +#define LPDDR4__DENALI_CTL_354__RDLVL_HIGH_THRESHOLD_F2_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_354__RDLVL_HIGH_THRESHOLD_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_354__RDLVL_HIGH_THRESHOLD_F2_WIDTH 16U +#define LPDDR4__RDLVL_HIGH_THRESHOLD_F2__REG DENALI_CTL_354 +#define LPDDR4__RDLVL_HIGH_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_354__RDLVL_HIGH_THRESHOLD_F2 + +#define LPDDR4__DENALI_CTL_355_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_355_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_355__RDLVL_TIMEOUT_F2_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_355__RDLVL_TIMEOUT_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_355__RDLVL_TIMEOUT_F2_WIDTH 16U +#define LPDDR4__RDLVL_TIMEOUT_F2__REG DENALI_CTL_355 +#define LPDDR4__RDLVL_TIMEOUT_F2__FLD LPDDR4__DENALI_CTL_355__RDLVL_TIMEOUT_F2 + +#define LPDDR4__DENALI_CTL_355__RDLVL_SW_PROMOTE_THRESHOLD_F2_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_355__RDLVL_SW_PROMOTE_THRESHOLD_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_355__RDLVL_SW_PROMOTE_THRESHOLD_F2_WIDTH 16U +#define LPDDR4__RDLVL_SW_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_355 +#define LPDDR4__RDLVL_SW_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_355__RDLVL_SW_PROMOTE_THRESHOLD_F2 + +#define LPDDR4__DENALI_CTL_356_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_356_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_356__RDLVL_DFI_PROMOTE_THRESHOLD_F2_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_356__RDLVL_DFI_PROMOTE_THRESHOLD_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_356__RDLVL_DFI_PROMOTE_THRESHOLD_F2_WIDTH 16U +#define LPDDR4__RDLVL_DFI_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_356 +#define LPDDR4__RDLVL_DFI_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_356__RDLVL_DFI_PROMOTE_THRESHOLD_F2 + +#define LPDDR4__DENALI_CTL_356__RDLVL_GATE_NORM_THRESHOLD_F2_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_356__RDLVL_GATE_NORM_THRESHOLD_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_356__RDLVL_GATE_NORM_THRESHOLD_F2_WIDTH 16U +#define LPDDR4__RDLVL_GATE_NORM_THRESHOLD_F2__REG DENALI_CTL_356 +#define LPDDR4__RDLVL_GATE_NORM_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_356__RDLVL_GATE_NORM_THRESHOLD_F2 + +#define LPDDR4__DENALI_CTL_357_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_357_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_357__RDLVL_GATE_HIGH_THRESHOLD_F2_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_357__RDLVL_GATE_HIGH_THRESHOLD_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_357__RDLVL_GATE_HIGH_THRESHOLD_F2_WIDTH 16U +#define LPDDR4__RDLVL_GATE_HIGH_THRESHOLD_F2__REG DENALI_CTL_357 +#define LPDDR4__RDLVL_GATE_HIGH_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_357__RDLVL_GATE_HIGH_THRESHOLD_F2 + +#define LPDDR4__DENALI_CTL_357__RDLVL_GATE_TIMEOUT_F2_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_357__RDLVL_GATE_TIMEOUT_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_357__RDLVL_GATE_TIMEOUT_F2_WIDTH 16U +#define LPDDR4__RDLVL_GATE_TIMEOUT_F2__REG DENALI_CTL_357 +#define LPDDR4__RDLVL_GATE_TIMEOUT_F2__FLD LPDDR4__DENALI_CTL_357__RDLVL_GATE_TIMEOUT_F2 + +#define LPDDR4__DENALI_CTL_358_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_358_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_358__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F2_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_358__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_358__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F2_WIDTH 16U +#define LPDDR4__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_358 +#define LPDDR4__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_358__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F2 + +#define LPDDR4__DENALI_CTL_358__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F2_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_358__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_358__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F2_WIDTH 16U +#define LPDDR4__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_358 +#define LPDDR4__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_358__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F2 + +#define LPDDR4__DENALI_CTL_359_READ_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_359_WRITE_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_359__CALVL_REQ_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_359__CALVL_REQ_SHIFT 0U +#define LPDDR4__DENALI_CTL_359__CALVL_REQ_WIDTH 1U +#define LPDDR4__DENALI_CTL_359__CALVL_REQ_WOCLR 0U +#define LPDDR4__DENALI_CTL_359__CALVL_REQ_WOSET 0U +#define LPDDR4__CALVL_REQ__REG DENALI_CTL_359 +#define LPDDR4__CALVL_REQ__FLD LPDDR4__DENALI_CTL_359__CALVL_REQ + +#define LPDDR4__DENALI_CTL_359__CALVL_CS_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_359__CALVL_CS_SHIFT 8U +#define LPDDR4__DENALI_CTL_359__CALVL_CS_WIDTH 1U +#define LPDDR4__DENALI_CTL_359__CALVL_CS_WOCLR 0U +#define LPDDR4__DENALI_CTL_359__CALVL_CS_WOSET 0U +#define LPDDR4__CALVL_CS__REG DENALI_CTL_359 +#define LPDDR4__CALVL_CS__FLD LPDDR4__DENALI_CTL_359__CALVL_CS + +#define LPDDR4__DENALI_CTL_360_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_360_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_360__CALVL_PAT_0_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_360__CALVL_PAT_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_360__CALVL_PAT_0_WIDTH 20U +#define LPDDR4__CALVL_PAT_0__REG DENALI_CTL_360 +#define LPDDR4__CALVL_PAT_0__FLD LPDDR4__DENALI_CTL_360__CALVL_PAT_0 + +#define LPDDR4__DENALI_CTL_361_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_361_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_361__CALVL_BG_PAT_0_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_361__CALVL_BG_PAT_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_361__CALVL_BG_PAT_0_WIDTH 20U +#define LPDDR4__CALVL_BG_PAT_0__REG DENALI_CTL_361 +#define LPDDR4__CALVL_BG_PAT_0__FLD LPDDR4__DENALI_CTL_361__CALVL_BG_PAT_0 + +#define LPDDR4__DENALI_CTL_362_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_362_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_362__CALVL_PAT_1_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_362__CALVL_PAT_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_362__CALVL_PAT_1_WIDTH 20U +#define LPDDR4__CALVL_PAT_1__REG DENALI_CTL_362 +#define LPDDR4__CALVL_PAT_1__FLD LPDDR4__DENALI_CTL_362__CALVL_PAT_1 + +#define LPDDR4__DENALI_CTL_363_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_363_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_363__CALVL_BG_PAT_1_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_363__CALVL_BG_PAT_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_363__CALVL_BG_PAT_1_WIDTH 20U +#define LPDDR4__CALVL_BG_PAT_1__REG DENALI_CTL_363 +#define LPDDR4__CALVL_BG_PAT_1__FLD LPDDR4__DENALI_CTL_363__CALVL_BG_PAT_1 + +#define LPDDR4__DENALI_CTL_364_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_364_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_364__CALVL_PAT_2_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_364__CALVL_PAT_2_SHIFT 0U +#define LPDDR4__DENALI_CTL_364__CALVL_PAT_2_WIDTH 20U +#define LPDDR4__CALVL_PAT_2__REG DENALI_CTL_364 +#define LPDDR4__CALVL_PAT_2__FLD LPDDR4__DENALI_CTL_364__CALVL_PAT_2 + +#define LPDDR4__DENALI_CTL_365_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_365_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_365__CALVL_BG_PAT_2_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_365__CALVL_BG_PAT_2_SHIFT 0U +#define LPDDR4__DENALI_CTL_365__CALVL_BG_PAT_2_WIDTH 20U +#define LPDDR4__CALVL_BG_PAT_2__REG DENALI_CTL_365 +#define LPDDR4__CALVL_BG_PAT_2__FLD LPDDR4__DENALI_CTL_365__CALVL_BG_PAT_2 + +#define LPDDR4__DENALI_CTL_366_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_366_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_366__CALVL_PAT_3_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_366__CALVL_PAT_3_SHIFT 0U +#define LPDDR4__DENALI_CTL_366__CALVL_PAT_3_WIDTH 20U +#define LPDDR4__CALVL_PAT_3__REG DENALI_CTL_366 +#define LPDDR4__CALVL_PAT_3__FLD LPDDR4__DENALI_CTL_366__CALVL_PAT_3 + +#define LPDDR4__DENALI_CTL_367_READ_MASK 0x010FFFFFU +#define LPDDR4__DENALI_CTL_367_WRITE_MASK 0x010FFFFFU +#define LPDDR4__DENALI_CTL_367__CALVL_BG_PAT_3_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_367__CALVL_BG_PAT_3_SHIFT 0U +#define LPDDR4__DENALI_CTL_367__CALVL_BG_PAT_3_WIDTH 20U +#define LPDDR4__CALVL_BG_PAT_3__REG DENALI_CTL_367 +#define LPDDR4__CALVL_BG_PAT_3__FLD LPDDR4__DENALI_CTL_367__CALVL_BG_PAT_3 + +#define LPDDR4__DENALI_CTL_367__MC_RESERVED30_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_367__MC_RESERVED30_SHIFT 24U +#define LPDDR4__DENALI_CTL_367__MC_RESERVED30_WIDTH 1U +#define LPDDR4__DENALI_CTL_367__MC_RESERVED30_WOCLR 0U +#define LPDDR4__DENALI_CTL_367__MC_RESERVED30_WOSET 0U +#define LPDDR4__MC_RESERVED30__REG DENALI_CTL_367 +#define LPDDR4__MC_RESERVED30__FLD LPDDR4__DENALI_CTL_367__MC_RESERVED30 + +#define LPDDR4__DENALI_CTL_368_READ_MASK 0x0101030FU +#define LPDDR4__DENALI_CTL_368_WRITE_MASK 0x0101030FU +#define LPDDR4__DENALI_CTL_368__MC_RESERVED31_MASK 0x0000000FU +#define LPDDR4__DENALI_CTL_368__MC_RESERVED31_SHIFT 0U +#define LPDDR4__DENALI_CTL_368__MC_RESERVED31_WIDTH 4U +#define LPDDR4__MC_RESERVED31__REG DENALI_CTL_368 +#define LPDDR4__MC_RESERVED31__FLD LPDDR4__DENALI_CTL_368__MC_RESERVED31 + +#define LPDDR4__DENALI_CTL_368__CALVL_SEQ_EN_MASK 0x00000300U +#define LPDDR4__DENALI_CTL_368__CALVL_SEQ_EN_SHIFT 8U +#define LPDDR4__DENALI_CTL_368__CALVL_SEQ_EN_WIDTH 2U +#define LPDDR4__CALVL_SEQ_EN__REG DENALI_CTL_368 +#define LPDDR4__CALVL_SEQ_EN__FLD LPDDR4__DENALI_CTL_368__CALVL_SEQ_EN + +#define LPDDR4__DENALI_CTL_368__DFI_PHY_CALVL_MODE_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_368__DFI_PHY_CALVL_MODE_SHIFT 16U +#define LPDDR4__DENALI_CTL_368__DFI_PHY_CALVL_MODE_WIDTH 1U +#define LPDDR4__DENALI_CTL_368__DFI_PHY_CALVL_MODE_WOCLR 0U +#define LPDDR4__DENALI_CTL_368__DFI_PHY_CALVL_MODE_WOSET 0U +#define LPDDR4__DFI_PHY_CALVL_MODE__REG DENALI_CTL_368 +#define LPDDR4__DFI_PHY_CALVL_MODE__FLD LPDDR4__DENALI_CTL_368__DFI_PHY_CALVL_MODE + +#define LPDDR4__DENALI_CTL_368__CALVL_PERIODIC_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_368__CALVL_PERIODIC_SHIFT 24U +#define LPDDR4__DENALI_CTL_368__CALVL_PERIODIC_WIDTH 1U +#define LPDDR4__DENALI_CTL_368__CALVL_PERIODIC_WOCLR 0U +#define LPDDR4__DENALI_CTL_368__CALVL_PERIODIC_WOSET 0U +#define LPDDR4__CALVL_PERIODIC__REG DENALI_CTL_368 +#define LPDDR4__CALVL_PERIODIC__FLD LPDDR4__DENALI_CTL_368__CALVL_PERIODIC + +#define LPDDR4__DENALI_CTL_369_READ_MASK 0x03010101U +#define LPDDR4__DENALI_CTL_369_WRITE_MASK 0x03010101U +#define LPDDR4__DENALI_CTL_369__CALVL_ON_SREF_EXIT_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_369__CALVL_ON_SREF_EXIT_SHIFT 0U +#define LPDDR4__DENALI_CTL_369__CALVL_ON_SREF_EXIT_WIDTH 1U +#define LPDDR4__DENALI_CTL_369__CALVL_ON_SREF_EXIT_WOCLR 0U +#define LPDDR4__DENALI_CTL_369__CALVL_ON_SREF_EXIT_WOSET 0U +#define LPDDR4__CALVL_ON_SREF_EXIT__REG DENALI_CTL_369 +#define LPDDR4__CALVL_ON_SREF_EXIT__FLD LPDDR4__DENALI_CTL_369__CALVL_ON_SREF_EXIT + +#define LPDDR4__DENALI_CTL_369__CALVL_AREF_EN_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_369__CALVL_AREF_EN_SHIFT 8U +#define LPDDR4__DENALI_CTL_369__CALVL_AREF_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_369__CALVL_AREF_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_369__CALVL_AREF_EN_WOSET 0U +#define LPDDR4__CALVL_AREF_EN__REG DENALI_CTL_369 +#define LPDDR4__CALVL_AREF_EN__FLD LPDDR4__DENALI_CTL_369__CALVL_AREF_EN + +#define LPDDR4__DENALI_CTL_369__CALVL_ROTATE_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_369__CALVL_ROTATE_SHIFT 16U +#define LPDDR4__DENALI_CTL_369__CALVL_ROTATE_WIDTH 1U +#define LPDDR4__DENALI_CTL_369__CALVL_ROTATE_WOCLR 0U +#define LPDDR4__DENALI_CTL_369__CALVL_ROTATE_WOSET 0U +#define LPDDR4__CALVL_ROTATE__REG DENALI_CTL_369 +#define LPDDR4__CALVL_ROTATE__FLD LPDDR4__DENALI_CTL_369__CALVL_ROTATE + +#define LPDDR4__DENALI_CTL_369__CALVL_CS_MAP_MASK 0x03000000U +#define LPDDR4__DENALI_CTL_369__CALVL_CS_MAP_SHIFT 24U +#define LPDDR4__DENALI_CTL_369__CALVL_CS_MAP_WIDTH 2U +#define LPDDR4__CALVL_CS_MAP__REG DENALI_CTL_369 +#define LPDDR4__CALVL_CS_MAP__FLD LPDDR4__DENALI_CTL_369__CALVL_CS_MAP + +#define LPDDR4__DENALI_CTL_370_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_370_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_370__CALVL_NORM_THRESHOLD_F0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_370__CALVL_NORM_THRESHOLD_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_370__CALVL_NORM_THRESHOLD_F0_WIDTH 16U +#define LPDDR4__CALVL_NORM_THRESHOLD_F0__REG DENALI_CTL_370 +#define LPDDR4__CALVL_NORM_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_370__CALVL_NORM_THRESHOLD_F0 + +#define LPDDR4__DENALI_CTL_370__CALVL_HIGH_THRESHOLD_F0_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_370__CALVL_HIGH_THRESHOLD_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_370__CALVL_HIGH_THRESHOLD_F0_WIDTH 16U +#define LPDDR4__CALVL_HIGH_THRESHOLD_F0__REG DENALI_CTL_370 +#define LPDDR4__CALVL_HIGH_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_370__CALVL_HIGH_THRESHOLD_F0 + +#define LPDDR4__DENALI_CTL_371_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_371_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_371__CALVL_TIMEOUT_F0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_371__CALVL_TIMEOUT_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_371__CALVL_TIMEOUT_F0_WIDTH 16U +#define LPDDR4__CALVL_TIMEOUT_F0__REG DENALI_CTL_371 +#define LPDDR4__CALVL_TIMEOUT_F0__FLD LPDDR4__DENALI_CTL_371__CALVL_TIMEOUT_F0 + +#define LPDDR4__DENALI_CTL_371__CALVL_SW_PROMOTE_THRESHOLD_F0_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_371__CALVL_SW_PROMOTE_THRESHOLD_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_371__CALVL_SW_PROMOTE_THRESHOLD_F0_WIDTH 16U +#define LPDDR4__CALVL_SW_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_371 +#define LPDDR4__CALVL_SW_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_371__CALVL_SW_PROMOTE_THRESHOLD_F0 + +#define LPDDR4__DENALI_CTL_372_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_372_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_372__CALVL_DFI_PROMOTE_THRESHOLD_F0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_372__CALVL_DFI_PROMOTE_THRESHOLD_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_372__CALVL_DFI_PROMOTE_THRESHOLD_F0_WIDTH 16U +#define LPDDR4__CALVL_DFI_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_372 +#define LPDDR4__CALVL_DFI_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_372__CALVL_DFI_PROMOTE_THRESHOLD_F0 + +#define LPDDR4__DENALI_CTL_372__CALVL_NORM_THRESHOLD_F1_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_372__CALVL_NORM_THRESHOLD_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_372__CALVL_NORM_THRESHOLD_F1_WIDTH 16U +#define LPDDR4__CALVL_NORM_THRESHOLD_F1__REG DENALI_CTL_372 +#define LPDDR4__CALVL_NORM_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_372__CALVL_NORM_THRESHOLD_F1 + +#define LPDDR4__DENALI_CTL_373_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_373_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_373__CALVL_HIGH_THRESHOLD_F1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_373__CALVL_HIGH_THRESHOLD_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_373__CALVL_HIGH_THRESHOLD_F1_WIDTH 16U +#define LPDDR4__CALVL_HIGH_THRESHOLD_F1__REG DENALI_CTL_373 +#define LPDDR4__CALVL_HIGH_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_373__CALVL_HIGH_THRESHOLD_F1 + +#define LPDDR4__DENALI_CTL_373__CALVL_TIMEOUT_F1_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_373__CALVL_TIMEOUT_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_373__CALVL_TIMEOUT_F1_WIDTH 16U +#define LPDDR4__CALVL_TIMEOUT_F1__REG DENALI_CTL_373 +#define LPDDR4__CALVL_TIMEOUT_F1__FLD LPDDR4__DENALI_CTL_373__CALVL_TIMEOUT_F1 + +#define LPDDR4__DENALI_CTL_374_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_374_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_374__CALVL_SW_PROMOTE_THRESHOLD_F1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_374__CALVL_SW_PROMOTE_THRESHOLD_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_374__CALVL_SW_PROMOTE_THRESHOLD_F1_WIDTH 16U +#define LPDDR4__CALVL_SW_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_374 +#define LPDDR4__CALVL_SW_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_374__CALVL_SW_PROMOTE_THRESHOLD_F1 + +#define LPDDR4__DENALI_CTL_374__CALVL_DFI_PROMOTE_THRESHOLD_F1_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_374__CALVL_DFI_PROMOTE_THRESHOLD_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_374__CALVL_DFI_PROMOTE_THRESHOLD_F1_WIDTH 16U +#define LPDDR4__CALVL_DFI_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_374 +#define LPDDR4__CALVL_DFI_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_374__CALVL_DFI_PROMOTE_THRESHOLD_F1 + +#define LPDDR4__DENALI_CTL_375_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_375_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_375__CALVL_NORM_THRESHOLD_F2_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_375__CALVL_NORM_THRESHOLD_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_375__CALVL_NORM_THRESHOLD_F2_WIDTH 16U +#define LPDDR4__CALVL_NORM_THRESHOLD_F2__REG DENALI_CTL_375 +#define LPDDR4__CALVL_NORM_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_375__CALVL_NORM_THRESHOLD_F2 + +#define LPDDR4__DENALI_CTL_375__CALVL_HIGH_THRESHOLD_F2_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_375__CALVL_HIGH_THRESHOLD_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_375__CALVL_HIGH_THRESHOLD_F2_WIDTH 16U +#define LPDDR4__CALVL_HIGH_THRESHOLD_F2__REG DENALI_CTL_375 +#define LPDDR4__CALVL_HIGH_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_375__CALVL_HIGH_THRESHOLD_F2 + +#define LPDDR4__DENALI_CTL_376_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_376_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_376__CALVL_TIMEOUT_F2_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_376__CALVL_TIMEOUT_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_376__CALVL_TIMEOUT_F2_WIDTH 16U +#define LPDDR4__CALVL_TIMEOUT_F2__REG DENALI_CTL_376 +#define LPDDR4__CALVL_TIMEOUT_F2__FLD LPDDR4__DENALI_CTL_376__CALVL_TIMEOUT_F2 + +#define LPDDR4__DENALI_CTL_376__CALVL_SW_PROMOTE_THRESHOLD_F2_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_376__CALVL_SW_PROMOTE_THRESHOLD_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_376__CALVL_SW_PROMOTE_THRESHOLD_F2_WIDTH 16U +#define LPDDR4__CALVL_SW_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_376 +#define LPDDR4__CALVL_SW_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_376__CALVL_SW_PROMOTE_THRESHOLD_F2 + +#define LPDDR4__DENALI_CTL_377_READ_MASK 0x0101FFFFU +#define LPDDR4__DENALI_CTL_377_WRITE_MASK 0x0101FFFFU +#define LPDDR4__DENALI_CTL_377__CALVL_DFI_PROMOTE_THRESHOLD_F2_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_377__CALVL_DFI_PROMOTE_THRESHOLD_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_377__CALVL_DFI_PROMOTE_THRESHOLD_F2_WIDTH 16U +#define LPDDR4__CALVL_DFI_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_377 +#define LPDDR4__CALVL_DFI_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_377__CALVL_DFI_PROMOTE_THRESHOLD_F2 + +#define LPDDR4__DENALI_CTL_377__AXI0_ALL_STROBES_USED_ENABLE_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_377__AXI0_ALL_STROBES_USED_ENABLE_SHIFT 16U +#define LPDDR4__DENALI_CTL_377__AXI0_ALL_STROBES_USED_ENABLE_WIDTH 1U +#define LPDDR4__DENALI_CTL_377__AXI0_ALL_STROBES_USED_ENABLE_WOCLR 0U +#define LPDDR4__DENALI_CTL_377__AXI0_ALL_STROBES_USED_ENABLE_WOSET 0U +#define LPDDR4__AXI0_ALL_STROBES_USED_ENABLE__REG DENALI_CTL_377 +#define LPDDR4__AXI0_ALL_STROBES_USED_ENABLE__FLD LPDDR4__DENALI_CTL_377__AXI0_ALL_STROBES_USED_ENABLE + +#define LPDDR4__DENALI_CTL_377__AXI0_FIXED_PORT_PRIORITY_ENABLE_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_377__AXI0_FIXED_PORT_PRIORITY_ENABLE_SHIFT 24U +#define LPDDR4__DENALI_CTL_377__AXI0_FIXED_PORT_PRIORITY_ENABLE_WIDTH 1U +#define LPDDR4__DENALI_CTL_377__AXI0_FIXED_PORT_PRIORITY_ENABLE_WOCLR 0U +#define LPDDR4__DENALI_CTL_377__AXI0_FIXED_PORT_PRIORITY_ENABLE_WOSET 0U +#define LPDDR4__AXI0_FIXED_PORT_PRIORITY_ENABLE__REG DENALI_CTL_377 +#define LPDDR4__AXI0_FIXED_PORT_PRIORITY_ENABLE__FLD LPDDR4__DENALI_CTL_377__AXI0_FIXED_PORT_PRIORITY_ENABLE + +#define LPDDR4__DENALI_CTL_378_READ_MASK 0x00000707U +#define LPDDR4__DENALI_CTL_378_WRITE_MASK 0x00000707U +#define LPDDR4__DENALI_CTL_378__AXI0_R_PRIORITY_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_378__AXI0_R_PRIORITY_SHIFT 0U +#define LPDDR4__DENALI_CTL_378__AXI0_R_PRIORITY_WIDTH 3U +#define LPDDR4__AXI0_R_PRIORITY__REG DENALI_CTL_378 +#define LPDDR4__AXI0_R_PRIORITY__FLD LPDDR4__DENALI_CTL_378__AXI0_R_PRIORITY + +#define LPDDR4__DENALI_CTL_378__AXI0_W_PRIORITY_MASK 0x00000700U +#define LPDDR4__DENALI_CTL_378__AXI0_W_PRIORITY_SHIFT 8U +#define LPDDR4__DENALI_CTL_378__AXI0_W_PRIORITY_WIDTH 3U +#define LPDDR4__AXI0_W_PRIORITY__REG DENALI_CTL_378 +#define LPDDR4__AXI0_W_PRIORITY__FLD LPDDR4__DENALI_CTL_378__AXI0_W_PRIORITY + +#define LPDDR4__DENALI_CTL_379_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_379_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_379__PARITY_ERROR_ADDRESS_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_379__PARITY_ERROR_ADDRESS_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_379__PARITY_ERROR_ADDRESS_0_WIDTH 32U +#define LPDDR4__PARITY_ERROR_ADDRESS_0__REG DENALI_CTL_379 +#define LPDDR4__PARITY_ERROR_ADDRESS_0__FLD LPDDR4__DENALI_CTL_379__PARITY_ERROR_ADDRESS_0 + +#define LPDDR4__DENALI_CTL_380_READ_MASK 0x1FFF3F07U +#define LPDDR4__DENALI_CTL_380_WRITE_MASK 0x1FFF3F07U +#define LPDDR4__DENALI_CTL_380__PARITY_ERROR_ADDRESS_1_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_380__PARITY_ERROR_ADDRESS_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_380__PARITY_ERROR_ADDRESS_1_WIDTH 3U +#define LPDDR4__PARITY_ERROR_ADDRESS_1__REG DENALI_CTL_380 +#define LPDDR4__PARITY_ERROR_ADDRESS_1__FLD LPDDR4__DENALI_CTL_380__PARITY_ERROR_ADDRESS_1 + +#define LPDDR4__DENALI_CTL_380__PARITY_ERROR_MASTER_ID_MASK 0x00003F00U +#define LPDDR4__DENALI_CTL_380__PARITY_ERROR_MASTER_ID_SHIFT 8U +#define LPDDR4__DENALI_CTL_380__PARITY_ERROR_MASTER_ID_WIDTH 6U +#define LPDDR4__PARITY_ERROR_MASTER_ID__REG DENALI_CTL_380 +#define LPDDR4__PARITY_ERROR_MASTER_ID__FLD LPDDR4__DENALI_CTL_380__PARITY_ERROR_MASTER_ID + +#define LPDDR4__DENALI_CTL_380__PARITY_ERROR_BUS_CHANNEL_MASK 0x1FFF0000U +#define LPDDR4__DENALI_CTL_380__PARITY_ERROR_BUS_CHANNEL_SHIFT 16U +#define LPDDR4__DENALI_CTL_380__PARITY_ERROR_BUS_CHANNEL_WIDTH 13U +#define LPDDR4__PARITY_ERROR_BUS_CHANNEL__REG DENALI_CTL_380 +#define LPDDR4__PARITY_ERROR_BUS_CHANNEL__FLD LPDDR4__DENALI_CTL_380__PARITY_ERROR_BUS_CHANNEL + +#define LPDDR4__DENALI_CTL_381_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_381_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_381__PARITY_ERROR_WRITE_DATA_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_381__PARITY_ERROR_WRITE_DATA_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_381__PARITY_ERROR_WRITE_DATA_0_WIDTH 32U +#define LPDDR4__PARITY_ERROR_WRITE_DATA_0__REG DENALI_CTL_381 +#define LPDDR4__PARITY_ERROR_WRITE_DATA_0__FLD LPDDR4__DENALI_CTL_381__PARITY_ERROR_WRITE_DATA_0 + +#define LPDDR4__DENALI_CTL_382_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_382_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_382__PARITY_ERROR_WRITE_DATA_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_382__PARITY_ERROR_WRITE_DATA_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_382__PARITY_ERROR_WRITE_DATA_1_WIDTH 32U +#define LPDDR4__PARITY_ERROR_WRITE_DATA_1__REG DENALI_CTL_382 +#define LPDDR4__PARITY_ERROR_WRITE_DATA_1__FLD LPDDR4__DENALI_CTL_382__PARITY_ERROR_WRITE_DATA_1 + +#define LPDDR4__DENALI_CTL_383_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_383_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_383__PARITY_ERROR_WRITE_DATA_2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_383__PARITY_ERROR_WRITE_DATA_2_SHIFT 0U +#define LPDDR4__DENALI_CTL_383__PARITY_ERROR_WRITE_DATA_2_WIDTH 32U +#define LPDDR4__PARITY_ERROR_WRITE_DATA_2__REG DENALI_CTL_383 +#define LPDDR4__PARITY_ERROR_WRITE_DATA_2__FLD LPDDR4__DENALI_CTL_383__PARITY_ERROR_WRITE_DATA_2 + +#define LPDDR4__DENALI_CTL_384_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_384_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_384__PARITY_ERROR_WRITE_DATA_3_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_384__PARITY_ERROR_WRITE_DATA_3_SHIFT 0U +#define LPDDR4__DENALI_CTL_384__PARITY_ERROR_WRITE_DATA_3_WIDTH 32U +#define LPDDR4__PARITY_ERROR_WRITE_DATA_3__REG DENALI_CTL_384 +#define LPDDR4__PARITY_ERROR_WRITE_DATA_3__FLD LPDDR4__DENALI_CTL_384__PARITY_ERROR_WRITE_DATA_3 + +#define LPDDR4__DENALI_CTL_385_READ_MASK 0x0103FFFFU +#define LPDDR4__DENALI_CTL_385_WRITE_MASK 0x0103FFFFU +#define LPDDR4__DENALI_CTL_385__PARITY_ERROR_WRITE_DATA_PARITY_VECTOR_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_385__PARITY_ERROR_WRITE_DATA_PARITY_VECTOR_SHIFT 0U +#define LPDDR4__DENALI_CTL_385__PARITY_ERROR_WRITE_DATA_PARITY_VECTOR_WIDTH 16U +#define LPDDR4__PARITY_ERROR_WRITE_DATA_PARITY_VECTOR__REG DENALI_CTL_385 +#define LPDDR4__PARITY_ERROR_WRITE_DATA_PARITY_VECTOR__FLD LPDDR4__DENALI_CTL_385__PARITY_ERROR_WRITE_DATA_PARITY_VECTOR + +#define LPDDR4__DENALI_CTL_385__CKE_STATUS_MASK 0x00030000U +#define LPDDR4__DENALI_CTL_385__CKE_STATUS_SHIFT 16U +#define LPDDR4__DENALI_CTL_385__CKE_STATUS_WIDTH 2U +#define LPDDR4__CKE_STATUS__REG DENALI_CTL_385 +#define LPDDR4__CKE_STATUS__FLD LPDDR4__DENALI_CTL_385__CKE_STATUS + +#define LPDDR4__DENALI_CTL_385__MEM_RST_VALID_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_385__MEM_RST_VALID_SHIFT 24U +#define LPDDR4__DENALI_CTL_385__MEM_RST_VALID_WIDTH 1U +#define LPDDR4__DENALI_CTL_385__MEM_RST_VALID_WOCLR 0U +#define LPDDR4__DENALI_CTL_385__MEM_RST_VALID_WOSET 0U +#define LPDDR4__MEM_RST_VALID__REG DENALI_CTL_385 +#define LPDDR4__MEM_RST_VALID__FLD LPDDR4__DENALI_CTL_385__MEM_RST_VALID + +#define LPDDR4__DENALI_CTL_386_READ_MASK 0x7FFFFFFFU +#define LPDDR4__DENALI_CTL_386_WRITE_MASK 0x7FFFFFFFU +#define LPDDR4__DENALI_CTL_386__DLL_RST_DELAY_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_386__DLL_RST_DELAY_SHIFT 0U +#define LPDDR4__DENALI_CTL_386__DLL_RST_DELAY_WIDTH 16U +#define LPDDR4__DLL_RST_DELAY__REG DENALI_CTL_386 +#define LPDDR4__DLL_RST_DELAY__FLD LPDDR4__DENALI_CTL_386__DLL_RST_DELAY + +#define LPDDR4__DENALI_CTL_386__DLL_RST_ADJ_DLY_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_386__DLL_RST_ADJ_DLY_SHIFT 16U +#define LPDDR4__DENALI_CTL_386__DLL_RST_ADJ_DLY_WIDTH 8U +#define LPDDR4__DLL_RST_ADJ_DLY__REG DENALI_CTL_386 +#define LPDDR4__DLL_RST_ADJ_DLY__FLD LPDDR4__DENALI_CTL_386__DLL_RST_ADJ_DLY + +#define LPDDR4__DENALI_CTL_386__TDFI_PHY_WRLAT_MASK 0x7F000000U +#define LPDDR4__DENALI_CTL_386__TDFI_PHY_WRLAT_SHIFT 24U +#define LPDDR4__DENALI_CTL_386__TDFI_PHY_WRLAT_WIDTH 7U +#define LPDDR4__TDFI_PHY_WRLAT__REG DENALI_CTL_386 +#define LPDDR4__TDFI_PHY_WRLAT__FLD LPDDR4__DENALI_CTL_386__TDFI_PHY_WRLAT + +#define LPDDR4__DENALI_CTL_387_READ_MASK 0x7F7F7F7FU +#define LPDDR4__DENALI_CTL_387_WRITE_MASK 0x7F7F7F7FU +#define LPDDR4__DENALI_CTL_387__UPDATE_ERROR_STATUS_MASK 0x0000007FU +#define LPDDR4__DENALI_CTL_387__UPDATE_ERROR_STATUS_SHIFT 0U +#define LPDDR4__DENALI_CTL_387__UPDATE_ERROR_STATUS_WIDTH 7U +#define LPDDR4__UPDATE_ERROR_STATUS__REG DENALI_CTL_387 +#define LPDDR4__UPDATE_ERROR_STATUS__FLD LPDDR4__DENALI_CTL_387__UPDATE_ERROR_STATUS + +#define LPDDR4__DENALI_CTL_387__TDFI_PHY_RDLAT_F0_MASK 0x00007F00U +#define LPDDR4__DENALI_CTL_387__TDFI_PHY_RDLAT_F0_SHIFT 8U +#define LPDDR4__DENALI_CTL_387__TDFI_PHY_RDLAT_F0_WIDTH 7U +#define LPDDR4__TDFI_PHY_RDLAT_F0__REG DENALI_CTL_387 +#define LPDDR4__TDFI_PHY_RDLAT_F0__FLD LPDDR4__DENALI_CTL_387__TDFI_PHY_RDLAT_F0 + +#define LPDDR4__DENALI_CTL_387__TDFI_PHY_RDLAT_F1_MASK 0x007F0000U +#define LPDDR4__DENALI_CTL_387__TDFI_PHY_RDLAT_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_387__TDFI_PHY_RDLAT_F1_WIDTH 7U +#define LPDDR4__TDFI_PHY_RDLAT_F1__REG DENALI_CTL_387 +#define LPDDR4__TDFI_PHY_RDLAT_F1__FLD LPDDR4__DENALI_CTL_387__TDFI_PHY_RDLAT_F1 + +#define LPDDR4__DENALI_CTL_387__TDFI_PHY_RDLAT_F2_MASK 0x7F000000U +#define LPDDR4__DENALI_CTL_387__TDFI_PHY_RDLAT_F2_SHIFT 24U +#define LPDDR4__DENALI_CTL_387__TDFI_PHY_RDLAT_F2_WIDTH 7U +#define LPDDR4__TDFI_PHY_RDLAT_F2__REG DENALI_CTL_387 +#define LPDDR4__TDFI_PHY_RDLAT_F2__FLD LPDDR4__DENALI_CTL_387__TDFI_PHY_RDLAT_F2 + +#define LPDDR4__DENALI_CTL_388_READ_MASK 0x00FF037FU +#define LPDDR4__DENALI_CTL_388_WRITE_MASK 0x00FF037FU +#define LPDDR4__DENALI_CTL_388__TDFI_RDDATA_EN_MASK 0x0000007FU +#define LPDDR4__DENALI_CTL_388__TDFI_RDDATA_EN_SHIFT 0U +#define LPDDR4__DENALI_CTL_388__TDFI_RDDATA_EN_WIDTH 7U +#define LPDDR4__TDFI_RDDATA_EN__REG DENALI_CTL_388 +#define LPDDR4__TDFI_RDDATA_EN__FLD LPDDR4__DENALI_CTL_388__TDFI_RDDATA_EN + +#define LPDDR4__DENALI_CTL_388__DRAM_CLK_DISABLE_MASK 0x00000300U +#define LPDDR4__DENALI_CTL_388__DRAM_CLK_DISABLE_SHIFT 8U +#define LPDDR4__DENALI_CTL_388__DRAM_CLK_DISABLE_WIDTH 2U +#define LPDDR4__DRAM_CLK_DISABLE__REG DENALI_CTL_388 +#define LPDDR4__DRAM_CLK_DISABLE__FLD LPDDR4__DENALI_CTL_388__DRAM_CLK_DISABLE + +#define LPDDR4__DENALI_CTL_388__TDFI_CTRLUPD_MIN_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_388__TDFI_CTRLUPD_MIN_SHIFT 16U +#define LPDDR4__DENALI_CTL_388__TDFI_CTRLUPD_MIN_WIDTH 8U +#define LPDDR4__TDFI_CTRLUPD_MIN__REG DENALI_CTL_388 +#define LPDDR4__TDFI_CTRLUPD_MIN__FLD LPDDR4__DENALI_CTL_388__TDFI_CTRLUPD_MIN + +#define LPDDR4__DENALI_CTL_389_READ_MASK 0x001FFFFFU +#define LPDDR4__DENALI_CTL_389_WRITE_MASK 0x001FFFFFU +#define LPDDR4__DENALI_CTL_389__TDFI_CTRLUPD_MAX_F0_MASK 0x001FFFFFU +#define LPDDR4__DENALI_CTL_389__TDFI_CTRLUPD_MAX_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_389__TDFI_CTRLUPD_MAX_F0_WIDTH 21U +#define LPDDR4__TDFI_CTRLUPD_MAX_F0__REG DENALI_CTL_389 +#define LPDDR4__TDFI_CTRLUPD_MAX_F0__FLD LPDDR4__DENALI_CTL_389__TDFI_CTRLUPD_MAX_F0 + +#define LPDDR4__DENALI_CTL_390_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_390_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_390__TDFI_PHYUPD_TYPE0_F0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_390__TDFI_PHYUPD_TYPE0_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_390__TDFI_PHYUPD_TYPE0_F0_WIDTH 32U +#define LPDDR4__TDFI_PHYUPD_TYPE0_F0__REG DENALI_CTL_390 +#define LPDDR4__TDFI_PHYUPD_TYPE0_F0__FLD LPDDR4__DENALI_CTL_390__TDFI_PHYUPD_TYPE0_F0 + +#define LPDDR4__DENALI_CTL_391_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_391_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_391__TDFI_PHYUPD_TYPE1_F0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_391__TDFI_PHYUPD_TYPE1_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_391__TDFI_PHYUPD_TYPE1_F0_WIDTH 32U +#define LPDDR4__TDFI_PHYUPD_TYPE1_F0__REG DENALI_CTL_391 +#define LPDDR4__TDFI_PHYUPD_TYPE1_F0__FLD LPDDR4__DENALI_CTL_391__TDFI_PHYUPD_TYPE1_F0 + +#define LPDDR4__DENALI_CTL_392_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_392_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_392__TDFI_PHYUPD_TYPE2_F0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_392__TDFI_PHYUPD_TYPE2_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_392__TDFI_PHYUPD_TYPE2_F0_WIDTH 32U +#define LPDDR4__TDFI_PHYUPD_TYPE2_F0__REG DENALI_CTL_392 +#define LPDDR4__TDFI_PHYUPD_TYPE2_F0__FLD LPDDR4__DENALI_CTL_392__TDFI_PHYUPD_TYPE2_F0 + +#define LPDDR4__DENALI_CTL_393_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_393_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_393__TDFI_PHYUPD_TYPE3_F0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_393__TDFI_PHYUPD_TYPE3_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_393__TDFI_PHYUPD_TYPE3_F0_WIDTH 32U +#define LPDDR4__TDFI_PHYUPD_TYPE3_F0__REG DENALI_CTL_393 +#define LPDDR4__TDFI_PHYUPD_TYPE3_F0__FLD LPDDR4__DENALI_CTL_393__TDFI_PHYUPD_TYPE3_F0 + +#define LPDDR4__DENALI_CTL_394_READ_MASK 0x007FFFFFU +#define LPDDR4__DENALI_CTL_394_WRITE_MASK 0x007FFFFFU +#define LPDDR4__DENALI_CTL_394__TDFI_PHYUPD_RESP_F0_MASK 0x007FFFFFU +#define LPDDR4__DENALI_CTL_394__TDFI_PHYUPD_RESP_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_394__TDFI_PHYUPD_RESP_F0_WIDTH 23U +#define LPDDR4__TDFI_PHYUPD_RESP_F0__REG DENALI_CTL_394 +#define LPDDR4__TDFI_PHYUPD_RESP_F0__FLD LPDDR4__DENALI_CTL_394__TDFI_PHYUPD_RESP_F0 + +#define LPDDR4__DENALI_CTL_395_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_395_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_395__TDFI_CTRLUPD_INTERVAL_F0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_395__TDFI_CTRLUPD_INTERVAL_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_395__TDFI_CTRLUPD_INTERVAL_F0_WIDTH 32U +#define LPDDR4__TDFI_CTRLUPD_INTERVAL_F0__REG DENALI_CTL_395 +#define LPDDR4__TDFI_CTRLUPD_INTERVAL_F0__FLD LPDDR4__DENALI_CTL_395__TDFI_CTRLUPD_INTERVAL_F0 + +#define LPDDR4__DENALI_CTL_396_READ_MASK 0x00007F7FU +#define LPDDR4__DENALI_CTL_396_WRITE_MASK 0x00007F7FU +#define LPDDR4__DENALI_CTL_396__RDLAT_ADJ_F0_MASK 0x0000007FU +#define LPDDR4__DENALI_CTL_396__RDLAT_ADJ_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_396__RDLAT_ADJ_F0_WIDTH 7U +#define LPDDR4__RDLAT_ADJ_F0__REG DENALI_CTL_396 +#define LPDDR4__RDLAT_ADJ_F0__FLD LPDDR4__DENALI_CTL_396__RDLAT_ADJ_F0 + +#define LPDDR4__DENALI_CTL_396__WRLAT_ADJ_F0_MASK 0x00007F00U +#define LPDDR4__DENALI_CTL_396__WRLAT_ADJ_F0_SHIFT 8U +#define LPDDR4__DENALI_CTL_396__WRLAT_ADJ_F0_WIDTH 7U +#define LPDDR4__WRLAT_ADJ_F0__REG DENALI_CTL_396 +#define LPDDR4__WRLAT_ADJ_F0__FLD LPDDR4__DENALI_CTL_396__WRLAT_ADJ_F0 + +#define LPDDR4__DENALI_CTL_397_READ_MASK 0x001FFFFFU +#define LPDDR4__DENALI_CTL_397_WRITE_MASK 0x001FFFFFU +#define LPDDR4__DENALI_CTL_397__TDFI_CTRLUPD_MAX_F1_MASK 0x001FFFFFU +#define LPDDR4__DENALI_CTL_397__TDFI_CTRLUPD_MAX_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_397__TDFI_CTRLUPD_MAX_F1_WIDTH 21U +#define LPDDR4__TDFI_CTRLUPD_MAX_F1__REG DENALI_CTL_397 +#define LPDDR4__TDFI_CTRLUPD_MAX_F1__FLD LPDDR4__DENALI_CTL_397__TDFI_CTRLUPD_MAX_F1 + +#define LPDDR4__DENALI_CTL_398_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_398_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_398__TDFI_PHYUPD_TYPE0_F1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_398__TDFI_PHYUPD_TYPE0_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_398__TDFI_PHYUPD_TYPE0_F1_WIDTH 32U +#define LPDDR4__TDFI_PHYUPD_TYPE0_F1__REG DENALI_CTL_398 +#define LPDDR4__TDFI_PHYUPD_TYPE0_F1__FLD LPDDR4__DENALI_CTL_398__TDFI_PHYUPD_TYPE0_F1 + +#define LPDDR4__DENALI_CTL_399_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_399_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_399__TDFI_PHYUPD_TYPE1_F1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_399__TDFI_PHYUPD_TYPE1_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_399__TDFI_PHYUPD_TYPE1_F1_WIDTH 32U +#define LPDDR4__TDFI_PHYUPD_TYPE1_F1__REG DENALI_CTL_399 +#define LPDDR4__TDFI_PHYUPD_TYPE1_F1__FLD LPDDR4__DENALI_CTL_399__TDFI_PHYUPD_TYPE1_F1 + +#define LPDDR4__DENALI_CTL_400_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_400_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_400__TDFI_PHYUPD_TYPE2_F1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_400__TDFI_PHYUPD_TYPE2_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_400__TDFI_PHYUPD_TYPE2_F1_WIDTH 32U +#define LPDDR4__TDFI_PHYUPD_TYPE2_F1__REG DENALI_CTL_400 +#define LPDDR4__TDFI_PHYUPD_TYPE2_F1__FLD LPDDR4__DENALI_CTL_400__TDFI_PHYUPD_TYPE2_F1 + +#define LPDDR4__DENALI_CTL_401_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_401_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_401__TDFI_PHYUPD_TYPE3_F1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_401__TDFI_PHYUPD_TYPE3_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_401__TDFI_PHYUPD_TYPE3_F1_WIDTH 32U +#define LPDDR4__TDFI_PHYUPD_TYPE3_F1__REG DENALI_CTL_401 +#define LPDDR4__TDFI_PHYUPD_TYPE3_F1__FLD LPDDR4__DENALI_CTL_401__TDFI_PHYUPD_TYPE3_F1 + +#define LPDDR4__DENALI_CTL_402_READ_MASK 0x007FFFFFU +#define LPDDR4__DENALI_CTL_402_WRITE_MASK 0x007FFFFFU +#define LPDDR4__DENALI_CTL_402__TDFI_PHYUPD_RESP_F1_MASK 0x007FFFFFU +#define LPDDR4__DENALI_CTL_402__TDFI_PHYUPD_RESP_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_402__TDFI_PHYUPD_RESP_F1_WIDTH 23U +#define LPDDR4__TDFI_PHYUPD_RESP_F1__REG DENALI_CTL_402 +#define LPDDR4__TDFI_PHYUPD_RESP_F1__FLD LPDDR4__DENALI_CTL_402__TDFI_PHYUPD_RESP_F1 + +#define LPDDR4__DENALI_CTL_403_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_403_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_403__TDFI_CTRLUPD_INTERVAL_F1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_403__TDFI_CTRLUPD_INTERVAL_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_403__TDFI_CTRLUPD_INTERVAL_F1_WIDTH 32U +#define LPDDR4__TDFI_CTRLUPD_INTERVAL_F1__REG DENALI_CTL_403 +#define LPDDR4__TDFI_CTRLUPD_INTERVAL_F1__FLD LPDDR4__DENALI_CTL_403__TDFI_CTRLUPD_INTERVAL_F1 + +#define LPDDR4__DENALI_CTL_404_READ_MASK 0x00007F7FU +#define LPDDR4__DENALI_CTL_404_WRITE_MASK 0x00007F7FU +#define LPDDR4__DENALI_CTL_404__RDLAT_ADJ_F1_MASK 0x0000007FU +#define LPDDR4__DENALI_CTL_404__RDLAT_ADJ_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_404__RDLAT_ADJ_F1_WIDTH 7U +#define LPDDR4__RDLAT_ADJ_F1__REG DENALI_CTL_404 +#define LPDDR4__RDLAT_ADJ_F1__FLD LPDDR4__DENALI_CTL_404__RDLAT_ADJ_F1 + +#define LPDDR4__DENALI_CTL_404__WRLAT_ADJ_F1_MASK 0x00007F00U +#define LPDDR4__DENALI_CTL_404__WRLAT_ADJ_F1_SHIFT 8U +#define LPDDR4__DENALI_CTL_404__WRLAT_ADJ_F1_WIDTH 7U +#define LPDDR4__WRLAT_ADJ_F1__REG DENALI_CTL_404 +#define LPDDR4__WRLAT_ADJ_F1__FLD LPDDR4__DENALI_CTL_404__WRLAT_ADJ_F1 + +#define LPDDR4__DENALI_CTL_405_READ_MASK 0x001FFFFFU +#define LPDDR4__DENALI_CTL_405_WRITE_MASK 0x001FFFFFU +#define LPDDR4__DENALI_CTL_405__TDFI_CTRLUPD_MAX_F2_MASK 0x001FFFFFU +#define LPDDR4__DENALI_CTL_405__TDFI_CTRLUPD_MAX_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_405__TDFI_CTRLUPD_MAX_F2_WIDTH 21U +#define LPDDR4__TDFI_CTRLUPD_MAX_F2__REG DENALI_CTL_405 +#define LPDDR4__TDFI_CTRLUPD_MAX_F2__FLD LPDDR4__DENALI_CTL_405__TDFI_CTRLUPD_MAX_F2 + +#define LPDDR4__DENALI_CTL_406_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_406_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_406__TDFI_PHYUPD_TYPE0_F2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_406__TDFI_PHYUPD_TYPE0_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_406__TDFI_PHYUPD_TYPE0_F2_WIDTH 32U +#define LPDDR4__TDFI_PHYUPD_TYPE0_F2__REG DENALI_CTL_406 +#define LPDDR4__TDFI_PHYUPD_TYPE0_F2__FLD LPDDR4__DENALI_CTL_406__TDFI_PHYUPD_TYPE0_F2 + +#define LPDDR4__DENALI_CTL_407_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_407_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_407__TDFI_PHYUPD_TYPE1_F2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_407__TDFI_PHYUPD_TYPE1_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_407__TDFI_PHYUPD_TYPE1_F2_WIDTH 32U +#define LPDDR4__TDFI_PHYUPD_TYPE1_F2__REG DENALI_CTL_407 +#define LPDDR4__TDFI_PHYUPD_TYPE1_F2__FLD LPDDR4__DENALI_CTL_407__TDFI_PHYUPD_TYPE1_F2 + +#define LPDDR4__DENALI_CTL_408_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_408_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_408__TDFI_PHYUPD_TYPE2_F2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_408__TDFI_PHYUPD_TYPE2_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_408__TDFI_PHYUPD_TYPE2_F2_WIDTH 32U +#define LPDDR4__TDFI_PHYUPD_TYPE2_F2__REG DENALI_CTL_408 +#define LPDDR4__TDFI_PHYUPD_TYPE2_F2__FLD LPDDR4__DENALI_CTL_408__TDFI_PHYUPD_TYPE2_F2 + +#define LPDDR4__DENALI_CTL_409_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_409_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_409__TDFI_PHYUPD_TYPE3_F2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_409__TDFI_PHYUPD_TYPE3_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_409__TDFI_PHYUPD_TYPE3_F2_WIDTH 32U +#define LPDDR4__TDFI_PHYUPD_TYPE3_F2__REG DENALI_CTL_409 +#define LPDDR4__TDFI_PHYUPD_TYPE3_F2__FLD LPDDR4__DENALI_CTL_409__TDFI_PHYUPD_TYPE3_F2 + +#define LPDDR4__DENALI_CTL_410_READ_MASK 0x007FFFFFU +#define LPDDR4__DENALI_CTL_410_WRITE_MASK 0x007FFFFFU +#define LPDDR4__DENALI_CTL_410__TDFI_PHYUPD_RESP_F2_MASK 0x007FFFFFU +#define LPDDR4__DENALI_CTL_410__TDFI_PHYUPD_RESP_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_410__TDFI_PHYUPD_RESP_F2_WIDTH 23U +#define LPDDR4__TDFI_PHYUPD_RESP_F2__REG DENALI_CTL_410 +#define LPDDR4__TDFI_PHYUPD_RESP_F2__FLD LPDDR4__DENALI_CTL_410__TDFI_PHYUPD_RESP_F2 + +#define LPDDR4__DENALI_CTL_411_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_411_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_411__TDFI_CTRLUPD_INTERVAL_F2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_411__TDFI_CTRLUPD_INTERVAL_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_411__TDFI_CTRLUPD_INTERVAL_F2_WIDTH 32U +#define LPDDR4__TDFI_CTRLUPD_INTERVAL_F2__REG DENALI_CTL_411 +#define LPDDR4__TDFI_CTRLUPD_INTERVAL_F2__FLD LPDDR4__DENALI_CTL_411__TDFI_CTRLUPD_INTERVAL_F2 + +#define LPDDR4__DENALI_CTL_412_READ_MASK 0x0F0F7F7FU +#define LPDDR4__DENALI_CTL_412_WRITE_MASK 0x0F0F7F7FU +#define LPDDR4__DENALI_CTL_412__RDLAT_ADJ_F2_MASK 0x0000007FU +#define LPDDR4__DENALI_CTL_412__RDLAT_ADJ_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_412__RDLAT_ADJ_F2_WIDTH 7U +#define LPDDR4__RDLAT_ADJ_F2__REG DENALI_CTL_412 +#define LPDDR4__RDLAT_ADJ_F2__FLD LPDDR4__DENALI_CTL_412__RDLAT_ADJ_F2 + +#define LPDDR4__DENALI_CTL_412__WRLAT_ADJ_F2_MASK 0x00007F00U +#define LPDDR4__DENALI_CTL_412__WRLAT_ADJ_F2_SHIFT 8U +#define LPDDR4__DENALI_CTL_412__WRLAT_ADJ_F2_WIDTH 7U +#define LPDDR4__WRLAT_ADJ_F2__REG DENALI_CTL_412 +#define LPDDR4__WRLAT_ADJ_F2__FLD LPDDR4__DENALI_CTL_412__WRLAT_ADJ_F2 + +#define LPDDR4__DENALI_CTL_412__TDFI_CTRL_DELAY_F0_MASK 0x000F0000U +#define LPDDR4__DENALI_CTL_412__TDFI_CTRL_DELAY_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_412__TDFI_CTRL_DELAY_F0_WIDTH 4U +#define LPDDR4__TDFI_CTRL_DELAY_F0__REG DENALI_CTL_412 +#define LPDDR4__TDFI_CTRL_DELAY_F0__FLD LPDDR4__DENALI_CTL_412__TDFI_CTRL_DELAY_F0 + +#define LPDDR4__DENALI_CTL_412__TDFI_CTRL_DELAY_F1_MASK 0x0F000000U +#define LPDDR4__DENALI_CTL_412__TDFI_CTRL_DELAY_F1_SHIFT 24U +#define LPDDR4__DENALI_CTL_412__TDFI_CTRL_DELAY_F1_WIDTH 4U +#define LPDDR4__TDFI_CTRL_DELAY_F1__REG DENALI_CTL_412 +#define LPDDR4__TDFI_CTRL_DELAY_F1__FLD LPDDR4__DENALI_CTL_412__TDFI_CTRL_DELAY_F1 + +#define LPDDR4__DENALI_CTL_413_READ_MASK 0xFF0F0F0FU +#define LPDDR4__DENALI_CTL_413_WRITE_MASK 0xFF0F0F0FU +#define LPDDR4__DENALI_CTL_413__TDFI_CTRL_DELAY_F2_MASK 0x0000000FU +#define LPDDR4__DENALI_CTL_413__TDFI_CTRL_DELAY_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_413__TDFI_CTRL_DELAY_F2_WIDTH 4U +#define LPDDR4__TDFI_CTRL_DELAY_F2__REG DENALI_CTL_413 +#define LPDDR4__TDFI_CTRL_DELAY_F2__FLD LPDDR4__DENALI_CTL_413__TDFI_CTRL_DELAY_F2 + +#define LPDDR4__DENALI_CTL_413__TDFI_DRAM_CLK_DISABLE_MASK 0x00000F00U +#define LPDDR4__DENALI_CTL_413__TDFI_DRAM_CLK_DISABLE_SHIFT 8U +#define LPDDR4__DENALI_CTL_413__TDFI_DRAM_CLK_DISABLE_WIDTH 4U +#define LPDDR4__TDFI_DRAM_CLK_DISABLE__REG DENALI_CTL_413 +#define LPDDR4__TDFI_DRAM_CLK_DISABLE__FLD LPDDR4__DENALI_CTL_413__TDFI_DRAM_CLK_DISABLE + +#define LPDDR4__DENALI_CTL_413__TDFI_DRAM_CLK_ENABLE_MASK 0x000F0000U +#define LPDDR4__DENALI_CTL_413__TDFI_DRAM_CLK_ENABLE_SHIFT 16U +#define LPDDR4__DENALI_CTL_413__TDFI_DRAM_CLK_ENABLE_WIDTH 4U +#define LPDDR4__TDFI_DRAM_CLK_ENABLE__REG DENALI_CTL_413 +#define LPDDR4__TDFI_DRAM_CLK_ENABLE__FLD LPDDR4__DENALI_CTL_413__TDFI_DRAM_CLK_ENABLE + +#define LPDDR4__DENALI_CTL_413__TDFI_WRLVL_EN_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_413__TDFI_WRLVL_EN_SHIFT 24U +#define LPDDR4__DENALI_CTL_413__TDFI_WRLVL_EN_WIDTH 8U +#define LPDDR4__TDFI_WRLVL_EN__REG DENALI_CTL_413 +#define LPDDR4__TDFI_WRLVL_EN__FLD LPDDR4__DENALI_CTL_413__TDFI_WRLVL_EN + +#define LPDDR4__DENALI_CTL_414_READ_MASK 0x000003FFU +#define LPDDR4__DENALI_CTL_414_WRITE_MASK 0x000003FFU +#define LPDDR4__DENALI_CTL_414__TDFI_WRLVL_WW_MASK 0x000003FFU +#define LPDDR4__DENALI_CTL_414__TDFI_WRLVL_WW_SHIFT 0U +#define LPDDR4__DENALI_CTL_414__TDFI_WRLVL_WW_WIDTH 10U +#define LPDDR4__TDFI_WRLVL_WW__REG DENALI_CTL_414 +#define LPDDR4__TDFI_WRLVL_WW__FLD LPDDR4__DENALI_CTL_414__TDFI_WRLVL_WW + +#define LPDDR4__DENALI_CTL_415_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_415_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_415__TDFI_WRLVL_RESP_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_415__TDFI_WRLVL_RESP_SHIFT 0U +#define LPDDR4__DENALI_CTL_415__TDFI_WRLVL_RESP_WIDTH 32U +#define LPDDR4__TDFI_WRLVL_RESP__REG DENALI_CTL_415 +#define LPDDR4__TDFI_WRLVL_RESP__FLD LPDDR4__DENALI_CTL_415__TDFI_WRLVL_RESP + +#define LPDDR4__DENALI_CTL_416_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_416_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_416__TDFI_WRLVL_MAX_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_416__TDFI_WRLVL_MAX_SHIFT 0U +#define LPDDR4__DENALI_CTL_416__TDFI_WRLVL_MAX_WIDTH 32U +#define LPDDR4__TDFI_WRLVL_MAX__REG DENALI_CTL_416 +#define LPDDR4__TDFI_WRLVL_MAX__FLD LPDDR4__DENALI_CTL_416__TDFI_WRLVL_MAX + +#define LPDDR4__DENALI_CTL_417_READ_MASK 0x0003FFFFU +#define LPDDR4__DENALI_CTL_417_WRITE_MASK 0x0003FFFFU +#define LPDDR4__DENALI_CTL_417__TDFI_RDLVL_EN_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_417__TDFI_RDLVL_EN_SHIFT 0U +#define LPDDR4__DENALI_CTL_417__TDFI_RDLVL_EN_WIDTH 8U +#define LPDDR4__TDFI_RDLVL_EN__REG DENALI_CTL_417 +#define LPDDR4__TDFI_RDLVL_EN__FLD LPDDR4__DENALI_CTL_417__TDFI_RDLVL_EN + +#define LPDDR4__DENALI_CTL_417__TDFI_RDLVL_RR_MASK 0x0003FF00U +#define LPDDR4__DENALI_CTL_417__TDFI_RDLVL_RR_SHIFT 8U +#define LPDDR4__DENALI_CTL_417__TDFI_RDLVL_RR_WIDTH 10U +#define LPDDR4__TDFI_RDLVL_RR__REG DENALI_CTL_417 +#define LPDDR4__TDFI_RDLVL_RR__FLD LPDDR4__DENALI_CTL_417__TDFI_RDLVL_RR + +#define LPDDR4__DENALI_CTL_418_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_418_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_418__TDFI_RDLVL_RESP_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_418__TDFI_RDLVL_RESP_SHIFT 0U +#define LPDDR4__DENALI_CTL_418__TDFI_RDLVL_RESP_WIDTH 32U +#define LPDDR4__TDFI_RDLVL_RESP__REG DENALI_CTL_418 +#define LPDDR4__TDFI_RDLVL_RESP__FLD LPDDR4__DENALI_CTL_418__TDFI_RDLVL_RESP + +#define LPDDR4__DENALI_CTL_419_READ_MASK 0x000101FFU +#define LPDDR4__DENALI_CTL_419_WRITE_MASK 0x000101FFU +#define LPDDR4__DENALI_CTL_419__RDLVL_RESP_MASK_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_419__RDLVL_RESP_MASK_SHIFT 0U +#define LPDDR4__DENALI_CTL_419__RDLVL_RESP_MASK_WIDTH 8U +#define LPDDR4__RDLVL_RESP_MASK__REG DENALI_CTL_419 +#define LPDDR4__RDLVL_RESP_MASK__FLD LPDDR4__DENALI_CTL_419__RDLVL_RESP_MASK + +#define LPDDR4__DENALI_CTL_419__RDLVL_EN_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_419__RDLVL_EN_SHIFT 8U +#define LPDDR4__DENALI_CTL_419__RDLVL_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_419__RDLVL_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_419__RDLVL_EN_WOSET 0U +#define LPDDR4__RDLVL_EN__REG DENALI_CTL_419 +#define LPDDR4__RDLVL_EN__FLD LPDDR4__DENALI_CTL_419__RDLVL_EN + +#define LPDDR4__DENALI_CTL_419__RDLVL_GATE_EN_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_419__RDLVL_GATE_EN_SHIFT 16U +#define LPDDR4__DENALI_CTL_419__RDLVL_GATE_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_419__RDLVL_GATE_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_419__RDLVL_GATE_EN_WOSET 0U +#define LPDDR4__RDLVL_GATE_EN__REG DENALI_CTL_419 +#define LPDDR4__RDLVL_GATE_EN__FLD LPDDR4__DENALI_CTL_419__RDLVL_GATE_EN + +#define LPDDR4__DENALI_CTL_420_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_420_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_420__TDFI_RDLVL_MAX_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_420__TDFI_RDLVL_MAX_SHIFT 0U +#define LPDDR4__DENALI_CTL_420__TDFI_RDLVL_MAX_WIDTH 32U +#define LPDDR4__TDFI_RDLVL_MAX__REG DENALI_CTL_420 +#define LPDDR4__TDFI_RDLVL_MAX__FLD LPDDR4__DENALI_CTL_420__TDFI_RDLVL_MAX + +#define LPDDR4__DENALI_CTL_421_READ_MASK 0x00FF0707U +#define LPDDR4__DENALI_CTL_421_WRITE_MASK 0x00FF0707U +#define LPDDR4__DENALI_CTL_421__RDLVL_ERROR_STATUS_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_421__RDLVL_ERROR_STATUS_SHIFT 0U +#define LPDDR4__DENALI_CTL_421__RDLVL_ERROR_STATUS_WIDTH 3U +#define LPDDR4__RDLVL_ERROR_STATUS__REG DENALI_CTL_421 +#define LPDDR4__RDLVL_ERROR_STATUS__FLD LPDDR4__DENALI_CTL_421__RDLVL_ERROR_STATUS + +#define LPDDR4__DENALI_CTL_421__RDLVL_GATE_ERROR_STATUS_MASK 0x00000700U +#define LPDDR4__DENALI_CTL_421__RDLVL_GATE_ERROR_STATUS_SHIFT 8U +#define LPDDR4__DENALI_CTL_421__RDLVL_GATE_ERROR_STATUS_WIDTH 3U +#define LPDDR4__RDLVL_GATE_ERROR_STATUS__REG DENALI_CTL_421 +#define LPDDR4__RDLVL_GATE_ERROR_STATUS__FLD LPDDR4__DENALI_CTL_421__RDLVL_GATE_ERROR_STATUS + +#define LPDDR4__DENALI_CTL_421__TDFI_CALVL_EN_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_421__TDFI_CALVL_EN_SHIFT 16U +#define LPDDR4__DENALI_CTL_421__TDFI_CALVL_EN_WIDTH 8U +#define LPDDR4__TDFI_CALVL_EN__REG DENALI_CTL_421 +#define LPDDR4__TDFI_CALVL_EN__FLD LPDDR4__DENALI_CTL_421__TDFI_CALVL_EN + +#define LPDDR4__DENALI_CTL_422_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_CTL_422_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_CTL_422__TDFI_CALVL_CC_F0_MASK 0x000003FFU +#define LPDDR4__DENALI_CTL_422__TDFI_CALVL_CC_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_422__TDFI_CALVL_CC_F0_WIDTH 10U +#define LPDDR4__TDFI_CALVL_CC_F0__REG DENALI_CTL_422 +#define LPDDR4__TDFI_CALVL_CC_F0__FLD LPDDR4__DENALI_CTL_422__TDFI_CALVL_CC_F0 + +#define LPDDR4__DENALI_CTL_422__TDFI_CALVL_CAPTURE_F0_MASK 0x03FF0000U +#define LPDDR4__DENALI_CTL_422__TDFI_CALVL_CAPTURE_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_422__TDFI_CALVL_CAPTURE_F0_WIDTH 10U +#define LPDDR4__TDFI_CALVL_CAPTURE_F0__REG DENALI_CTL_422 +#define LPDDR4__TDFI_CALVL_CAPTURE_F0__FLD LPDDR4__DENALI_CTL_422__TDFI_CALVL_CAPTURE_F0 + +#define LPDDR4__DENALI_CTL_423_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_CTL_423_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_CTL_423__TDFI_CALVL_CC_F1_MASK 0x000003FFU +#define LPDDR4__DENALI_CTL_423__TDFI_CALVL_CC_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_423__TDFI_CALVL_CC_F1_WIDTH 10U +#define LPDDR4__TDFI_CALVL_CC_F1__REG DENALI_CTL_423 +#define LPDDR4__TDFI_CALVL_CC_F1__FLD LPDDR4__DENALI_CTL_423__TDFI_CALVL_CC_F1 + +#define LPDDR4__DENALI_CTL_423__TDFI_CALVL_CAPTURE_F1_MASK 0x03FF0000U +#define LPDDR4__DENALI_CTL_423__TDFI_CALVL_CAPTURE_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_423__TDFI_CALVL_CAPTURE_F1_WIDTH 10U +#define LPDDR4__TDFI_CALVL_CAPTURE_F1__REG DENALI_CTL_423 +#define LPDDR4__TDFI_CALVL_CAPTURE_F1__FLD LPDDR4__DENALI_CTL_423__TDFI_CALVL_CAPTURE_F1 + +#define LPDDR4__DENALI_CTL_424_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_CTL_424_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_CTL_424__TDFI_CALVL_CC_F2_MASK 0x000003FFU +#define LPDDR4__DENALI_CTL_424__TDFI_CALVL_CC_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_424__TDFI_CALVL_CC_F2_WIDTH 10U +#define LPDDR4__TDFI_CALVL_CC_F2__REG DENALI_CTL_424 +#define LPDDR4__TDFI_CALVL_CC_F2__FLD LPDDR4__DENALI_CTL_424__TDFI_CALVL_CC_F2 + +#define LPDDR4__DENALI_CTL_424__TDFI_CALVL_CAPTURE_F2_MASK 0x03FF0000U +#define LPDDR4__DENALI_CTL_424__TDFI_CALVL_CAPTURE_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_424__TDFI_CALVL_CAPTURE_F2_WIDTH 10U +#define LPDDR4__TDFI_CALVL_CAPTURE_F2__REG DENALI_CTL_424 +#define LPDDR4__TDFI_CALVL_CAPTURE_F2__FLD LPDDR4__DENALI_CTL_424__TDFI_CALVL_CAPTURE_F2 + +#define LPDDR4__DENALI_CTL_425_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_425_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_425__TDFI_CALVL_RESP_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_425__TDFI_CALVL_RESP_SHIFT 0U +#define LPDDR4__DENALI_CTL_425__TDFI_CALVL_RESP_WIDTH 32U +#define LPDDR4__TDFI_CALVL_RESP__REG DENALI_CTL_425 +#define LPDDR4__TDFI_CALVL_RESP__FLD LPDDR4__DENALI_CTL_425__TDFI_CALVL_RESP + +#define LPDDR4__DENALI_CTL_426_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_426_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_426__TDFI_CALVL_MAX_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_426__TDFI_CALVL_MAX_SHIFT 0U +#define LPDDR4__DENALI_CTL_426__TDFI_CALVL_MAX_WIDTH 32U +#define LPDDR4__TDFI_CALVL_MAX__REG DENALI_CTL_426 +#define LPDDR4__TDFI_CALVL_MAX__FLD LPDDR4__DENALI_CTL_426__TDFI_CALVL_MAX + +#define LPDDR4__DENALI_CTL_427_READ_MASK 0x070F0101U +#define LPDDR4__DENALI_CTL_427_WRITE_MASK 0x070F0101U +#define LPDDR4__DENALI_CTL_427__CALVL_RESP_MASK_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_427__CALVL_RESP_MASK_SHIFT 0U +#define LPDDR4__DENALI_CTL_427__CALVL_RESP_MASK_WIDTH 1U +#define LPDDR4__DENALI_CTL_427__CALVL_RESP_MASK_WOCLR 0U +#define LPDDR4__DENALI_CTL_427__CALVL_RESP_MASK_WOSET 0U +#define LPDDR4__CALVL_RESP_MASK__REG DENALI_CTL_427 +#define LPDDR4__CALVL_RESP_MASK__FLD LPDDR4__DENALI_CTL_427__CALVL_RESP_MASK + +#define LPDDR4__DENALI_CTL_427__CALVL_EN_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_427__CALVL_EN_SHIFT 8U +#define LPDDR4__DENALI_CTL_427__CALVL_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_427__CALVL_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_427__CALVL_EN_WOSET 0U +#define LPDDR4__CALVL_EN__REG DENALI_CTL_427 +#define LPDDR4__CALVL_EN__FLD LPDDR4__DENALI_CTL_427__CALVL_EN + +#define LPDDR4__DENALI_CTL_427__CALVL_ERROR_STATUS_MASK 0x000F0000U +#define LPDDR4__DENALI_CTL_427__CALVL_ERROR_STATUS_SHIFT 16U +#define LPDDR4__DENALI_CTL_427__CALVL_ERROR_STATUS_WIDTH 4U +#define LPDDR4__CALVL_ERROR_STATUS__REG DENALI_CTL_427 +#define LPDDR4__CALVL_ERROR_STATUS__FLD LPDDR4__DENALI_CTL_427__CALVL_ERROR_STATUS + +#define LPDDR4__DENALI_CTL_427__TDFI_PHY_WRDATA_F0_MASK 0x07000000U +#define LPDDR4__DENALI_CTL_427__TDFI_PHY_WRDATA_F0_SHIFT 24U +#define LPDDR4__DENALI_CTL_427__TDFI_PHY_WRDATA_F0_WIDTH 3U +#define LPDDR4__TDFI_PHY_WRDATA_F0__REG DENALI_CTL_427 +#define LPDDR4__TDFI_PHY_WRDATA_F0__FLD LPDDR4__DENALI_CTL_427__TDFI_PHY_WRDATA_F0 + +#define LPDDR4__DENALI_CTL_428_READ_MASK 0x7F7F0707U +#define LPDDR4__DENALI_CTL_428_WRITE_MASK 0x7F7F0707U +#define LPDDR4__DENALI_CTL_428__TDFI_PHY_WRDATA_F1_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_428__TDFI_PHY_WRDATA_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_428__TDFI_PHY_WRDATA_F1_WIDTH 3U +#define LPDDR4__TDFI_PHY_WRDATA_F1__REG DENALI_CTL_428 +#define LPDDR4__TDFI_PHY_WRDATA_F1__FLD LPDDR4__DENALI_CTL_428__TDFI_PHY_WRDATA_F1 + +#define LPDDR4__DENALI_CTL_428__TDFI_PHY_WRDATA_F2_MASK 0x00000700U +#define LPDDR4__DENALI_CTL_428__TDFI_PHY_WRDATA_F2_SHIFT 8U +#define LPDDR4__DENALI_CTL_428__TDFI_PHY_WRDATA_F2_WIDTH 3U +#define LPDDR4__TDFI_PHY_WRDATA_F2__REG DENALI_CTL_428 +#define LPDDR4__TDFI_PHY_WRDATA_F2__FLD LPDDR4__DENALI_CTL_428__TDFI_PHY_WRDATA_F2 + +#define LPDDR4__DENALI_CTL_428__TDFI_RDCSLAT_F0_MASK 0x007F0000U +#define LPDDR4__DENALI_CTL_428__TDFI_RDCSLAT_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_428__TDFI_RDCSLAT_F0_WIDTH 7U +#define LPDDR4__TDFI_RDCSLAT_F0__REG DENALI_CTL_428 +#define LPDDR4__TDFI_RDCSLAT_F0__FLD LPDDR4__DENALI_CTL_428__TDFI_RDCSLAT_F0 + +#define LPDDR4__DENALI_CTL_428__TDFI_WRCSLAT_F0_MASK 0x7F000000U +#define LPDDR4__DENALI_CTL_428__TDFI_WRCSLAT_F0_SHIFT 24U +#define LPDDR4__DENALI_CTL_428__TDFI_WRCSLAT_F0_WIDTH 7U +#define LPDDR4__TDFI_WRCSLAT_F0__REG DENALI_CTL_428 +#define LPDDR4__TDFI_WRCSLAT_F0__FLD LPDDR4__DENALI_CTL_428__TDFI_WRCSLAT_F0 + +#define LPDDR4__DENALI_CTL_429_READ_MASK 0x7F7F7F7FU +#define LPDDR4__DENALI_CTL_429_WRITE_MASK 0x7F7F7F7FU +#define LPDDR4__DENALI_CTL_429__TDFI_RDCSLAT_F1_MASK 0x0000007FU +#define LPDDR4__DENALI_CTL_429__TDFI_RDCSLAT_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_429__TDFI_RDCSLAT_F1_WIDTH 7U +#define LPDDR4__TDFI_RDCSLAT_F1__REG DENALI_CTL_429 +#define LPDDR4__TDFI_RDCSLAT_F1__FLD LPDDR4__DENALI_CTL_429__TDFI_RDCSLAT_F1 + +#define LPDDR4__DENALI_CTL_429__TDFI_WRCSLAT_F1_MASK 0x00007F00U +#define LPDDR4__DENALI_CTL_429__TDFI_WRCSLAT_F1_SHIFT 8U +#define LPDDR4__DENALI_CTL_429__TDFI_WRCSLAT_F1_WIDTH 7U +#define LPDDR4__TDFI_WRCSLAT_F1__REG DENALI_CTL_429 +#define LPDDR4__TDFI_WRCSLAT_F1__FLD LPDDR4__DENALI_CTL_429__TDFI_WRCSLAT_F1 + +#define LPDDR4__DENALI_CTL_429__TDFI_RDCSLAT_F2_MASK 0x007F0000U +#define LPDDR4__DENALI_CTL_429__TDFI_RDCSLAT_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_429__TDFI_RDCSLAT_F2_WIDTH 7U +#define LPDDR4__TDFI_RDCSLAT_F2__REG DENALI_CTL_429 +#define LPDDR4__TDFI_RDCSLAT_F2__FLD LPDDR4__DENALI_CTL_429__TDFI_RDCSLAT_F2 + +#define LPDDR4__DENALI_CTL_429__TDFI_WRCSLAT_F2_MASK 0x7F000000U +#define LPDDR4__DENALI_CTL_429__TDFI_WRCSLAT_F2_SHIFT 24U +#define LPDDR4__DENALI_CTL_429__TDFI_WRCSLAT_F2_WIDTH 7U +#define LPDDR4__TDFI_WRCSLAT_F2__REG DENALI_CTL_429 +#define LPDDR4__TDFI_WRCSLAT_F2__FLD LPDDR4__DENALI_CTL_429__TDFI_WRCSLAT_F2 + +#define LPDDR4__DENALI_CTL_430_READ_MASK 0x010101FFU +#define LPDDR4__DENALI_CTL_430_WRITE_MASK 0x010101FFU +#define LPDDR4__DENALI_CTL_430__TDFI_WRDATA_DELAY_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_430__TDFI_WRDATA_DELAY_SHIFT 0U +#define LPDDR4__DENALI_CTL_430__TDFI_WRDATA_DELAY_WIDTH 8U +#define LPDDR4__TDFI_WRDATA_DELAY__REG DENALI_CTL_430 +#define LPDDR4__TDFI_WRDATA_DELAY__FLD LPDDR4__DENALI_CTL_430__TDFI_WRDATA_DELAY + +#define LPDDR4__DENALI_CTL_430__EN_1T_TIMING_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_430__EN_1T_TIMING_SHIFT 8U +#define LPDDR4__DENALI_CTL_430__EN_1T_TIMING_WIDTH 1U +#define LPDDR4__DENALI_CTL_430__EN_1T_TIMING_WOCLR 0U +#define LPDDR4__DENALI_CTL_430__EN_1T_TIMING_WOSET 0U +#define LPDDR4__EN_1T_TIMING__REG DENALI_CTL_430 +#define LPDDR4__EN_1T_TIMING__FLD LPDDR4__DENALI_CTL_430__EN_1T_TIMING + +#define LPDDR4__DENALI_CTL_430__DISABLE_MEMORY_MASKED_WRITE_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_430__DISABLE_MEMORY_MASKED_WRITE_SHIFT 16U +#define LPDDR4__DENALI_CTL_430__DISABLE_MEMORY_MASKED_WRITE_WIDTH 1U +#define LPDDR4__DENALI_CTL_430__DISABLE_MEMORY_MASKED_WRITE_WOCLR 0U +#define LPDDR4__DENALI_CTL_430__DISABLE_MEMORY_MASKED_WRITE_WOSET 0U +#define LPDDR4__DISABLE_MEMORY_MASKED_WRITE__REG DENALI_CTL_430 +#define LPDDR4__DISABLE_MEMORY_MASKED_WRITE__FLD LPDDR4__DENALI_CTL_430__DISABLE_MEMORY_MASKED_WRITE + +#define LPDDR4__DENALI_CTL_430__BL_ON_FLY_ENABLE_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_430__BL_ON_FLY_ENABLE_SHIFT 24U +#define LPDDR4__DENALI_CTL_430__BL_ON_FLY_ENABLE_WIDTH 1U +#define LPDDR4__DENALI_CTL_430__BL_ON_FLY_ENABLE_WOCLR 0U +#define LPDDR4__DENALI_CTL_430__BL_ON_FLY_ENABLE_WOSET 0U +#define LPDDR4__BL_ON_FLY_ENABLE__REG DENALI_CTL_430 +#define LPDDR4__BL_ON_FLY_ENABLE__FLD LPDDR4__DENALI_CTL_430__BL_ON_FLY_ENABLE + +#define LPDDR4__DENALI_CTL_431_READ_MASK 0x07070701U +#define LPDDR4__DENALI_CTL_431_WRITE_MASK 0x07070701U +#define LPDDR4__DENALI_CTL_431__MC_RESERVED32_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_431__MC_RESERVED32_SHIFT 0U +#define LPDDR4__DENALI_CTL_431__MC_RESERVED32_WIDTH 1U +#define LPDDR4__DENALI_CTL_431__MC_RESERVED32_WOCLR 0U +#define LPDDR4__DENALI_CTL_431__MC_RESERVED32_WOSET 0U +#define LPDDR4__MC_RESERVED32__REG DENALI_CTL_431 +#define LPDDR4__MC_RESERVED32__FLD LPDDR4__DENALI_CTL_431__MC_RESERVED32 + +#define LPDDR4__DENALI_CTL_431__MC_RESERVED33_MASK 0x00000700U +#define LPDDR4__DENALI_CTL_431__MC_RESERVED33_SHIFT 8U +#define LPDDR4__DENALI_CTL_431__MC_RESERVED33_WIDTH 3U +#define LPDDR4__MC_RESERVED33__REG DENALI_CTL_431 +#define LPDDR4__MC_RESERVED33__FLD LPDDR4__DENALI_CTL_431__MC_RESERVED33 + +#define LPDDR4__DENALI_CTL_431__MC_RESERVED34_MASK 0x00070000U +#define LPDDR4__DENALI_CTL_431__MC_RESERVED34_SHIFT 16U +#define LPDDR4__DENALI_CTL_431__MC_RESERVED34_WIDTH 3U +#define LPDDR4__MC_RESERVED34__REG DENALI_CTL_431 +#define LPDDR4__MC_RESERVED34__FLD LPDDR4__DENALI_CTL_431__MC_RESERVED34 + +#define LPDDR4__DENALI_CTL_431__MC_RESERVED35_MASK 0x07000000U +#define LPDDR4__DENALI_CTL_431__MC_RESERVED35_SHIFT 24U +#define LPDDR4__DENALI_CTL_431__MC_RESERVED35_WIDTH 3U +#define LPDDR4__MC_RESERVED35__REG DENALI_CTL_431 +#define LPDDR4__MC_RESERVED35__FLD LPDDR4__DENALI_CTL_431__MC_RESERVED35 + +#define LPDDR4__DENALI_CTL_432_READ_MASK 0x0F070707U +#define LPDDR4__DENALI_CTL_432_WRITE_MASK 0x0F070707U +#define LPDDR4__DENALI_CTL_432__MC_RESERVED36_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_432__MC_RESERVED36_SHIFT 0U +#define LPDDR4__DENALI_CTL_432__MC_RESERVED36_WIDTH 3U +#define LPDDR4__MC_RESERVED36__REG DENALI_CTL_432 +#define LPDDR4__MC_RESERVED36__FLD LPDDR4__DENALI_CTL_432__MC_RESERVED36 + +#define LPDDR4__DENALI_CTL_432__MC_RESERVED37_MASK 0x00000700U +#define LPDDR4__DENALI_CTL_432__MC_RESERVED37_SHIFT 8U +#define LPDDR4__DENALI_CTL_432__MC_RESERVED37_WIDTH 3U +#define LPDDR4__MC_RESERVED37__REG DENALI_CTL_432 +#define LPDDR4__MC_RESERVED37__FLD LPDDR4__DENALI_CTL_432__MC_RESERVED37 + +#define LPDDR4__DENALI_CTL_432__MC_RESERVED38_MASK 0x00070000U +#define LPDDR4__DENALI_CTL_432__MC_RESERVED38_SHIFT 16U +#define LPDDR4__DENALI_CTL_432__MC_RESERVED38_WIDTH 3U +#define LPDDR4__MC_RESERVED38__REG DENALI_CTL_432 +#define LPDDR4__MC_RESERVED38__FLD LPDDR4__DENALI_CTL_432__MC_RESERVED38 + +#define LPDDR4__DENALI_CTL_432__MC_RESERVED39_MASK 0x0F000000U +#define LPDDR4__DENALI_CTL_432__MC_RESERVED39_SHIFT 24U +#define LPDDR4__DENALI_CTL_432__MC_RESERVED39_WIDTH 4U +#define LPDDR4__MC_RESERVED39__REG DENALI_CTL_432 +#define LPDDR4__MC_RESERVED39__FLD LPDDR4__DENALI_CTL_432__MC_RESERVED39 + +#define LPDDR4__DENALI_CTL_433_READ_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_CTL_433_WRITE_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_CTL_433__MC_RESERVED40_MASK 0x0000000FU +#define LPDDR4__DENALI_CTL_433__MC_RESERVED40_SHIFT 0U +#define LPDDR4__DENALI_CTL_433__MC_RESERVED40_WIDTH 4U +#define LPDDR4__MC_RESERVED40__REG DENALI_CTL_433 +#define LPDDR4__MC_RESERVED40__FLD LPDDR4__DENALI_CTL_433__MC_RESERVED40 + +#define LPDDR4__DENALI_CTL_433__MC_RESERVED41_MASK 0x00000F00U +#define LPDDR4__DENALI_CTL_433__MC_RESERVED41_SHIFT 8U +#define LPDDR4__DENALI_CTL_433__MC_RESERVED41_WIDTH 4U +#define LPDDR4__MC_RESERVED41__REG DENALI_CTL_433 +#define LPDDR4__MC_RESERVED41__FLD LPDDR4__DENALI_CTL_433__MC_RESERVED41 + +#define LPDDR4__DENALI_CTL_433__MC_RESERVED42_MASK 0x000F0000U +#define LPDDR4__DENALI_CTL_433__MC_RESERVED42_SHIFT 16U +#define LPDDR4__DENALI_CTL_433__MC_RESERVED42_WIDTH 4U +#define LPDDR4__MC_RESERVED42__REG DENALI_CTL_433 +#define LPDDR4__MC_RESERVED42__FLD LPDDR4__DENALI_CTL_433__MC_RESERVED42 + +#define LPDDR4__DENALI_CTL_433__MC_RESERVED43_MASK 0x0F000000U +#define LPDDR4__DENALI_CTL_433__MC_RESERVED43_SHIFT 24U +#define LPDDR4__DENALI_CTL_433__MC_RESERVED43_WIDTH 4U +#define LPDDR4__MC_RESERVED43__REG DENALI_CTL_433 +#define LPDDR4__MC_RESERVED43__FLD LPDDR4__DENALI_CTL_433__MC_RESERVED43 + +#define LPDDR4__DENALI_CTL_434_READ_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_CTL_434_WRITE_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_CTL_434__MC_RESERVED44_MASK 0x0000000FU +#define LPDDR4__DENALI_CTL_434__MC_RESERVED44_SHIFT 0U +#define LPDDR4__DENALI_CTL_434__MC_RESERVED44_WIDTH 4U +#define LPDDR4__MC_RESERVED44__REG DENALI_CTL_434 +#define LPDDR4__MC_RESERVED44__FLD LPDDR4__DENALI_CTL_434__MC_RESERVED44 + +#define LPDDR4__DENALI_CTL_434__MC_RESERVED45_MASK 0x00000F00U +#define LPDDR4__DENALI_CTL_434__MC_RESERVED45_SHIFT 8U +#define LPDDR4__DENALI_CTL_434__MC_RESERVED45_WIDTH 4U +#define LPDDR4__MC_RESERVED45__REG DENALI_CTL_434 +#define LPDDR4__MC_RESERVED45__FLD LPDDR4__DENALI_CTL_434__MC_RESERVED45 + +#define LPDDR4__DENALI_CTL_434__MC_RESERVED46_MASK 0x000F0000U +#define LPDDR4__DENALI_CTL_434__MC_RESERVED46_SHIFT 16U +#define LPDDR4__DENALI_CTL_434__MC_RESERVED46_WIDTH 4U +#define LPDDR4__MC_RESERVED46__REG DENALI_CTL_434 +#define LPDDR4__MC_RESERVED46__FLD LPDDR4__DENALI_CTL_434__MC_RESERVED46 + +#define LPDDR4__DENALI_CTL_434__MC_RESERVED47_MASK 0x0F000000U +#define LPDDR4__DENALI_CTL_434__MC_RESERVED47_SHIFT 24U +#define LPDDR4__DENALI_CTL_434__MC_RESERVED47_WIDTH 4U +#define LPDDR4__MC_RESERVED47__REG DENALI_CTL_434 +#define LPDDR4__MC_RESERVED47__FLD LPDDR4__DENALI_CTL_434__MC_RESERVED47 + +#define LPDDR4__DENALI_CTL_435_READ_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_CTL_435_WRITE_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_CTL_435__MC_RESERVED48_MASK 0x0000000FU +#define LPDDR4__DENALI_CTL_435__MC_RESERVED48_SHIFT 0U +#define LPDDR4__DENALI_CTL_435__MC_RESERVED48_WIDTH 4U +#define LPDDR4__MC_RESERVED48__REG DENALI_CTL_435 +#define LPDDR4__MC_RESERVED48__FLD LPDDR4__DENALI_CTL_435__MC_RESERVED48 + +#define LPDDR4__DENALI_CTL_435__MC_RESERVED49_MASK 0x00000F00U +#define LPDDR4__DENALI_CTL_435__MC_RESERVED49_SHIFT 8U +#define LPDDR4__DENALI_CTL_435__MC_RESERVED49_WIDTH 4U +#define LPDDR4__MC_RESERVED49__REG DENALI_CTL_435 +#define LPDDR4__MC_RESERVED49__FLD LPDDR4__DENALI_CTL_435__MC_RESERVED49 + +#define LPDDR4__DENALI_CTL_435__MC_RESERVED50_MASK 0x000F0000U +#define LPDDR4__DENALI_CTL_435__MC_RESERVED50_SHIFT 16U +#define LPDDR4__DENALI_CTL_435__MC_RESERVED50_WIDTH 4U +#define LPDDR4__MC_RESERVED50__REG DENALI_CTL_435 +#define LPDDR4__MC_RESERVED50__FLD LPDDR4__DENALI_CTL_435__MC_RESERVED50 + +#define LPDDR4__DENALI_CTL_435__MC_RESERVED51_MASK 0x0F000000U +#define LPDDR4__DENALI_CTL_435__MC_RESERVED51_SHIFT 24U +#define LPDDR4__DENALI_CTL_435__MC_RESERVED51_WIDTH 4U +#define LPDDR4__MC_RESERVED51__REG DENALI_CTL_435 +#define LPDDR4__MC_RESERVED51__FLD LPDDR4__DENALI_CTL_435__MC_RESERVED51 + +#define LPDDR4__DENALI_CTL_436_READ_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_CTL_436_WRITE_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_CTL_436__MC_RESERVED52_MASK 0x0000000FU +#define LPDDR4__DENALI_CTL_436__MC_RESERVED52_SHIFT 0U +#define LPDDR4__DENALI_CTL_436__MC_RESERVED52_WIDTH 4U +#define LPDDR4__MC_RESERVED52__REG DENALI_CTL_436 +#define LPDDR4__MC_RESERVED52__FLD LPDDR4__DENALI_CTL_436__MC_RESERVED52 + +#define LPDDR4__DENALI_CTL_436__MC_RESERVED53_MASK 0x00000F00U +#define LPDDR4__DENALI_CTL_436__MC_RESERVED53_SHIFT 8U +#define LPDDR4__DENALI_CTL_436__MC_RESERVED53_WIDTH 4U +#define LPDDR4__MC_RESERVED53__REG DENALI_CTL_436 +#define LPDDR4__MC_RESERVED53__FLD LPDDR4__DENALI_CTL_436__MC_RESERVED53 + +#define LPDDR4__DENALI_CTL_436__MC_RESERVED54_MASK 0x000F0000U +#define LPDDR4__DENALI_CTL_436__MC_RESERVED54_SHIFT 16U +#define LPDDR4__DENALI_CTL_436__MC_RESERVED54_WIDTH 4U +#define LPDDR4__MC_RESERVED54__REG DENALI_CTL_436 +#define LPDDR4__MC_RESERVED54__FLD LPDDR4__DENALI_CTL_436__MC_RESERVED54 + +#define LPDDR4__DENALI_CTL_436__MC_RESERVED55_MASK 0x0F000000U +#define LPDDR4__DENALI_CTL_436__MC_RESERVED55_SHIFT 24U +#define LPDDR4__DENALI_CTL_436__MC_RESERVED55_WIDTH 4U +#define LPDDR4__MC_RESERVED55__REG DENALI_CTL_436 +#define LPDDR4__MC_RESERVED55__FLD LPDDR4__DENALI_CTL_436__MC_RESERVED55 + +#define LPDDR4__DENALI_CTL_437_READ_MASK 0xFF0F0F0FU +#define LPDDR4__DENALI_CTL_437_WRITE_MASK 0xFF0F0F0FU +#define LPDDR4__DENALI_CTL_437__MC_RESERVED56_MASK 0x0000000FU +#define LPDDR4__DENALI_CTL_437__MC_RESERVED56_SHIFT 0U +#define LPDDR4__DENALI_CTL_437__MC_RESERVED56_WIDTH 4U +#define LPDDR4__MC_RESERVED56__REG DENALI_CTL_437 +#define LPDDR4__MC_RESERVED56__FLD LPDDR4__DENALI_CTL_437__MC_RESERVED56 + +#define LPDDR4__DENALI_CTL_437__MC_RESERVED57_MASK 0x00000F00U +#define LPDDR4__DENALI_CTL_437__MC_RESERVED57_SHIFT 8U +#define LPDDR4__DENALI_CTL_437__MC_RESERVED57_WIDTH 4U +#define LPDDR4__MC_RESERVED57__REG DENALI_CTL_437 +#define LPDDR4__MC_RESERVED57__FLD LPDDR4__DENALI_CTL_437__MC_RESERVED57 + +#define LPDDR4__DENALI_CTL_437__MC_RESERVED58_MASK 0x000F0000U +#define LPDDR4__DENALI_CTL_437__MC_RESERVED58_SHIFT 16U +#define LPDDR4__DENALI_CTL_437__MC_RESERVED58_WIDTH 4U +#define LPDDR4__MC_RESERVED58__REG DENALI_CTL_437 +#define LPDDR4__MC_RESERVED58__FLD LPDDR4__DENALI_CTL_437__MC_RESERVED58 + +#define LPDDR4__DENALI_CTL_437__GLOBAL_ERROR_INFO_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_437__GLOBAL_ERROR_INFO_SHIFT 24U +#define LPDDR4__DENALI_CTL_437__GLOBAL_ERROR_INFO_WIDTH 8U +#define LPDDR4__GLOBAL_ERROR_INFO__REG DENALI_CTL_437 +#define LPDDR4__GLOBAL_ERROR_INFO__FLD LPDDR4__DENALI_CTL_437__GLOBAL_ERROR_INFO + +#define LPDDR4__DENALI_CTL_438_READ_MASK 0xFFFF03FFU +#define LPDDR4__DENALI_CTL_438_WRITE_MASK 0xFFFF03FFU +#define LPDDR4__DENALI_CTL_438__GLOBAL_ERROR_MASK_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_438__GLOBAL_ERROR_MASK_SHIFT 0U +#define LPDDR4__DENALI_CTL_438__GLOBAL_ERROR_MASK_WIDTH 8U +#define LPDDR4__GLOBAL_ERROR_MASK__REG DENALI_CTL_438 +#define LPDDR4__GLOBAL_ERROR_MASK__FLD LPDDR4__DENALI_CTL_438__GLOBAL_ERROR_MASK + +#define LPDDR4__DENALI_CTL_438__AXI_PARITY_ERROR_STATUS_MASK 0x00000300U +#define LPDDR4__DENALI_CTL_438__AXI_PARITY_ERROR_STATUS_SHIFT 8U +#define LPDDR4__DENALI_CTL_438__AXI_PARITY_ERROR_STATUS_WIDTH 2U +#define LPDDR4__AXI_PARITY_ERROR_STATUS__REG DENALI_CTL_438 +#define LPDDR4__AXI_PARITY_ERROR_STATUS__FLD LPDDR4__DENALI_CTL_438__AXI_PARITY_ERROR_STATUS + +#define LPDDR4__DENALI_CTL_438__NWR_F0_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_438__NWR_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_438__NWR_F0_WIDTH 8U +#define LPDDR4__NWR_F0__REG DENALI_CTL_438 +#define LPDDR4__NWR_F0__FLD LPDDR4__DENALI_CTL_438__NWR_F0 + +#define LPDDR4__DENALI_CTL_438__NWR_F1_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_438__NWR_F1_SHIFT 24U +#define LPDDR4__DENALI_CTL_438__NWR_F1_WIDTH 8U +#define LPDDR4__NWR_F1__REG DENALI_CTL_438 +#define LPDDR4__NWR_F1__FLD LPDDR4__DENALI_CTL_438__NWR_F1 + +#define LPDDR4__DENALI_CTL_439_READ_MASK 0x001F01FFU +#define LPDDR4__DENALI_CTL_439_WRITE_MASK 0x001F01FFU +#define LPDDR4__DENALI_CTL_439__NWR_F2_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_439__NWR_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_439__NWR_F2_WIDTH 8U +#define LPDDR4__NWR_F2__REG DENALI_CTL_439 +#define LPDDR4__NWR_F2__FLD LPDDR4__DENALI_CTL_439__NWR_F2 + +#define LPDDR4__DENALI_CTL_439__MC_RESERVED59_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_439__MC_RESERVED59_SHIFT 8U +#define LPDDR4__DENALI_CTL_439__MC_RESERVED59_WIDTH 1U +#define LPDDR4__DENALI_CTL_439__MC_RESERVED59_WOCLR 0U +#define LPDDR4__DENALI_CTL_439__MC_RESERVED59_WOSET 0U +#define LPDDR4__MC_RESERVED59__REG DENALI_CTL_439 +#define LPDDR4__MC_RESERVED59__FLD LPDDR4__DENALI_CTL_439__MC_RESERVED59 + +#define LPDDR4__DENALI_CTL_439__REGPORT_PARAM_PARITY_PROTECTION_STATUS_MASK 0x001F0000U +#define LPDDR4__DENALI_CTL_439__REGPORT_PARAM_PARITY_PROTECTION_STATUS_SHIFT 16U +#define LPDDR4__DENALI_CTL_439__REGPORT_PARAM_PARITY_PROTECTION_STATUS_WIDTH 5U +#define LPDDR4__REGPORT_PARAM_PARITY_PROTECTION_STATUS__REG DENALI_CTL_439 +#define LPDDR4__REGPORT_PARAM_PARITY_PROTECTION_STATUS__FLD LPDDR4__DENALI_CTL_439__REGPORT_PARAM_PARITY_PROTECTION_STATUS + +#define LPDDR4__DENALI_CTL_440_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_440_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_440__MC_PARITY_INJECTION_BYTE_ENABLE_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_440__MC_PARITY_INJECTION_BYTE_ENABLE_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_440__MC_PARITY_INJECTION_BYTE_ENABLE_0_WIDTH 32U +#define LPDDR4__MC_PARITY_INJECTION_BYTE_ENABLE_0__REG DENALI_CTL_440 +#define LPDDR4__MC_PARITY_INJECTION_BYTE_ENABLE_0__FLD LPDDR4__DENALI_CTL_440__MC_PARITY_INJECTION_BYTE_ENABLE_0 + +#define LPDDR4__DENALI_CTL_441_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_441_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_441__MC_PARITY_INJECTION_BYTE_ENABLE_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_441__MC_PARITY_INJECTION_BYTE_ENABLE_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_441__MC_PARITY_INJECTION_BYTE_ENABLE_1_WIDTH 32U +#define LPDDR4__MC_PARITY_INJECTION_BYTE_ENABLE_1__REG DENALI_CTL_441 +#define LPDDR4__MC_PARITY_INJECTION_BYTE_ENABLE_1__FLD LPDDR4__DENALI_CTL_441__MC_PARITY_INJECTION_BYTE_ENABLE_1 + +#define LPDDR4__DENALI_CTL_442_READ_MASK 0x01010101U +#define LPDDR4__DENALI_CTL_442_WRITE_MASK 0x01010101U +#define LPDDR4__DENALI_CTL_442__MC_PARITY_ERROR_TYPE_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_442__MC_PARITY_ERROR_TYPE_SHIFT 0U +#define LPDDR4__DENALI_CTL_442__MC_PARITY_ERROR_TYPE_WIDTH 1U +#define LPDDR4__DENALI_CTL_442__MC_PARITY_ERROR_TYPE_WOCLR 0U +#define LPDDR4__DENALI_CTL_442__MC_PARITY_ERROR_TYPE_WOSET 0U +#define LPDDR4__MC_PARITY_ERROR_TYPE__REG DENALI_CTL_442 +#define LPDDR4__MC_PARITY_ERROR_TYPE__FLD LPDDR4__DENALI_CTL_442__MC_PARITY_ERROR_TYPE + +#define LPDDR4__DENALI_CTL_442__REGPORT_ADDR_PARITY_PROTECTION_EN_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_442__REGPORT_ADDR_PARITY_PROTECTION_EN_SHIFT 8U +#define LPDDR4__DENALI_CTL_442__REGPORT_ADDR_PARITY_PROTECTION_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_442__REGPORT_ADDR_PARITY_PROTECTION_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_442__REGPORT_ADDR_PARITY_PROTECTION_EN_WOSET 0U +#define LPDDR4__REGPORT_ADDR_PARITY_PROTECTION_EN__REG DENALI_CTL_442 +#define LPDDR4__REGPORT_ADDR_PARITY_PROTECTION_EN__FLD LPDDR4__DENALI_CTL_442__REGPORT_ADDR_PARITY_PROTECTION_EN + +#define LPDDR4__DENALI_CTL_442__REGPORT_WRITEMASK_PARITY_PROTECTION_EN_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_442__REGPORT_WRITEMASK_PARITY_PROTECTION_EN_SHIFT 16U +#define LPDDR4__DENALI_CTL_442__REGPORT_WRITEMASK_PARITY_PROTECTION_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_442__REGPORT_WRITEMASK_PARITY_PROTECTION_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_442__REGPORT_WRITEMASK_PARITY_PROTECTION_EN_WOSET 0U +#define LPDDR4__REGPORT_WRITEMASK_PARITY_PROTECTION_EN__REG DENALI_CTL_442 +#define LPDDR4__REGPORT_WRITEMASK_PARITY_PROTECTION_EN__FLD LPDDR4__DENALI_CTL_442__REGPORT_WRITEMASK_PARITY_PROTECTION_EN + +#define LPDDR4__DENALI_CTL_442__REGPORT_WRITE_PARITY_PROTECTION_EN_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_442__REGPORT_WRITE_PARITY_PROTECTION_EN_SHIFT 24U +#define LPDDR4__DENALI_CTL_442__REGPORT_WRITE_PARITY_PROTECTION_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_442__REGPORT_WRITE_PARITY_PROTECTION_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_442__REGPORT_WRITE_PARITY_PROTECTION_EN_WOSET 0U +#define LPDDR4__REGPORT_WRITE_PARITY_PROTECTION_EN__REG DENALI_CTL_442 +#define LPDDR4__REGPORT_WRITE_PARITY_PROTECTION_EN__FLD LPDDR4__DENALI_CTL_442__REGPORT_WRITE_PARITY_PROTECTION_EN + +#define LPDDR4__DENALI_CTL_443_READ_MASK 0x01010101U +#define LPDDR4__DENALI_CTL_443_WRITE_MASK 0x01010101U +#define LPDDR4__DENALI_CTL_443__REGPORT_READ_PARITY_PROTECTION_EN_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_443__REGPORT_READ_PARITY_PROTECTION_EN_SHIFT 0U +#define LPDDR4__DENALI_CTL_443__REGPORT_READ_PARITY_PROTECTION_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_443__REGPORT_READ_PARITY_PROTECTION_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_443__REGPORT_READ_PARITY_PROTECTION_EN_WOSET 0U +#define LPDDR4__REGPORT_READ_PARITY_PROTECTION_EN__REG DENALI_CTL_443 +#define LPDDR4__REGPORT_READ_PARITY_PROTECTION_EN__FLD LPDDR4__DENALI_CTL_443__REGPORT_READ_PARITY_PROTECTION_EN + +#define LPDDR4__DENALI_CTL_443__PARAMREG_PARITY_PROTECTION_EN_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_443__PARAMREG_PARITY_PROTECTION_EN_SHIFT 8U +#define LPDDR4__DENALI_CTL_443__PARAMREG_PARITY_PROTECTION_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_443__PARAMREG_PARITY_PROTECTION_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_443__PARAMREG_PARITY_PROTECTION_EN_WOSET 0U +#define LPDDR4__PARAMREG_PARITY_PROTECTION_EN__REG DENALI_CTL_443 +#define LPDDR4__PARAMREG_PARITY_PROTECTION_EN__FLD LPDDR4__DENALI_CTL_443__PARAMREG_PARITY_PROTECTION_EN + +#define LPDDR4__DENALI_CTL_443__REGPORT_ADDR_PARITY_PROTECTION_INJECTION_EN_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_443__REGPORT_ADDR_PARITY_PROTECTION_INJECTION_EN_SHIFT 16U +#define LPDDR4__DENALI_CTL_443__REGPORT_ADDR_PARITY_PROTECTION_INJECTION_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_443__REGPORT_ADDR_PARITY_PROTECTION_INJECTION_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_443__REGPORT_ADDR_PARITY_PROTECTION_INJECTION_EN_WOSET 0U +#define LPDDR4__REGPORT_ADDR_PARITY_PROTECTION_INJECTION_EN__REG DENALI_CTL_443 +#define LPDDR4__REGPORT_ADDR_PARITY_PROTECTION_INJECTION_EN__FLD LPDDR4__DENALI_CTL_443__REGPORT_ADDR_PARITY_PROTECTION_INJECTION_EN + +#define LPDDR4__DENALI_CTL_443__REGPORT_WRITEMASK_PARITY_PROTECTION_INJECTION_EN_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_443__REGPORT_WRITEMASK_PARITY_PROTECTION_INJECTION_EN_SHIFT 24U +#define LPDDR4__DENALI_CTL_443__REGPORT_WRITEMASK_PARITY_PROTECTION_INJECTION_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_443__REGPORT_WRITEMASK_PARITY_PROTECTION_INJECTION_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_443__REGPORT_WRITEMASK_PARITY_PROTECTION_INJECTION_EN_WOSET 0U +#define LPDDR4__REGPORT_WRITEMASK_PARITY_PROTECTION_INJECTION_EN__REG DENALI_CTL_443 +#define LPDDR4__REGPORT_WRITEMASK_PARITY_PROTECTION_INJECTION_EN__FLD LPDDR4__DENALI_CTL_443__REGPORT_WRITEMASK_PARITY_PROTECTION_INJECTION_EN + +#define LPDDR4__DENALI_CTL_444_READ_MASK 0x00010101U +#define LPDDR4__DENALI_CTL_444_WRITE_MASK 0x00010101U +#define LPDDR4__DENALI_CTL_444__REGPORT_WRITE_PARITY_PROTECTION_INJECTION_EN_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_444__REGPORT_WRITE_PARITY_PROTECTION_INJECTION_EN_SHIFT 0U +#define LPDDR4__DENALI_CTL_444__REGPORT_WRITE_PARITY_PROTECTION_INJECTION_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_444__REGPORT_WRITE_PARITY_PROTECTION_INJECTION_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_444__REGPORT_WRITE_PARITY_PROTECTION_INJECTION_EN_WOSET 0U +#define LPDDR4__REGPORT_WRITE_PARITY_PROTECTION_INJECTION_EN__REG DENALI_CTL_444 +#define LPDDR4__REGPORT_WRITE_PARITY_PROTECTION_INJECTION_EN__FLD LPDDR4__DENALI_CTL_444__REGPORT_WRITE_PARITY_PROTECTION_INJECTION_EN + +#define LPDDR4__DENALI_CTL_444__REGPORT_READ_PARITY_PROTECTION_INJECTION_EN_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_444__REGPORT_READ_PARITY_PROTECTION_INJECTION_EN_SHIFT 8U +#define LPDDR4__DENALI_CTL_444__REGPORT_READ_PARITY_PROTECTION_INJECTION_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_444__REGPORT_READ_PARITY_PROTECTION_INJECTION_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_444__REGPORT_READ_PARITY_PROTECTION_INJECTION_EN_WOSET 0U +#define LPDDR4__REGPORT_READ_PARITY_PROTECTION_INJECTION_EN__REG DENALI_CTL_444 +#define LPDDR4__REGPORT_READ_PARITY_PROTECTION_INJECTION_EN__FLD LPDDR4__DENALI_CTL_444__REGPORT_READ_PARITY_PROTECTION_INJECTION_EN + +#define LPDDR4__DENALI_CTL_444__PARAMREG_PARITY_PROTECTION_INJECTION_EN_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_444__PARAMREG_PARITY_PROTECTION_INJECTION_EN_SHIFT 16U +#define LPDDR4__DENALI_CTL_444__PARAMREG_PARITY_PROTECTION_INJECTION_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_444__PARAMREG_PARITY_PROTECTION_INJECTION_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_444__PARAMREG_PARITY_PROTECTION_INJECTION_EN_WOSET 0U +#define LPDDR4__PARAMREG_PARITY_PROTECTION_INJECTION_EN__REG DENALI_CTL_444 +#define LPDDR4__PARAMREG_PARITY_PROTECTION_INJECTION_EN__FLD LPDDR4__DENALI_CTL_444__PARAMREG_PARITY_PROTECTION_INJECTION_EN + +#define LPDDR4__DENALI_CTL_445_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_445_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_445__MC_RESERVED60_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_445__MC_RESERVED60_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_445__MC_RESERVED60_0_WIDTH 32U +#define LPDDR4__MC_RESERVED60_0__REG DENALI_CTL_445 +#define LPDDR4__MC_RESERVED60_0__FLD LPDDR4__DENALI_CTL_445__MC_RESERVED60_0 + +#define LPDDR4__DENALI_CTL_446_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_446_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_446__MC_RESERVED60_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_446__MC_RESERVED60_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_446__MC_RESERVED60_1_WIDTH 32U +#define LPDDR4__MC_RESERVED60_1__REG DENALI_CTL_446 +#define LPDDR4__MC_RESERVED60_1__FLD LPDDR4__DENALI_CTL_446__MC_RESERVED60_1 + +#define LPDDR4__DENALI_CTL_447_READ_MASK 0x00000107U +#define LPDDR4__DENALI_CTL_447_WRITE_MASK 0x00000107U +#define LPDDR4__DENALI_CTL_447__MC_RESERVED60_2_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_447__MC_RESERVED60_2_SHIFT 0U +#define LPDDR4__DENALI_CTL_447__MC_RESERVED60_2_WIDTH 3U +#define LPDDR4__MC_RESERVED60_2__REG DENALI_CTL_447 +#define LPDDR4__MC_RESERVED60_2__FLD LPDDR4__DENALI_CTL_447__MC_RESERVED60_2 + +#define LPDDR4__DENALI_CTL_447__PORT_TO_CORE_PROTECTION_EN_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_447__PORT_TO_CORE_PROTECTION_EN_SHIFT 8U +#define LPDDR4__DENALI_CTL_447__PORT_TO_CORE_PROTECTION_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_447__PORT_TO_CORE_PROTECTION_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_447__PORT_TO_CORE_PROTECTION_EN_WOSET 0U +#define LPDDR4__PORT_TO_CORE_PROTECTION_EN__REG DENALI_CTL_447 +#define LPDDR4__PORT_TO_CORE_PROTECTION_EN__FLD LPDDR4__DENALI_CTL_447__PORT_TO_CORE_PROTECTION_EN + +#define LPDDR4__DENALI_CTL_448_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_448_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_448__PORT_TO_CORE_PROTECTION_INJECTION_EN_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_448__PORT_TO_CORE_PROTECTION_INJECTION_EN_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_448__PORT_TO_CORE_PROTECTION_INJECTION_EN_0_WIDTH 32U +#define LPDDR4__PORT_TO_CORE_PROTECTION_INJECTION_EN_0__REG DENALI_CTL_448 +#define LPDDR4__PORT_TO_CORE_PROTECTION_INJECTION_EN_0__FLD LPDDR4__DENALI_CTL_448__PORT_TO_CORE_PROTECTION_INJECTION_EN_0 + +#define LPDDR4__DENALI_CTL_449_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_449_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_449__PORT_TO_CORE_PROTECTION_INJECTION_EN_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_449__PORT_TO_CORE_PROTECTION_INJECTION_EN_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_449__PORT_TO_CORE_PROTECTION_INJECTION_EN_1_WIDTH 32U +#define LPDDR4__PORT_TO_CORE_PROTECTION_INJECTION_EN_1__REG DENALI_CTL_449 +#define LPDDR4__PORT_TO_CORE_PROTECTION_INJECTION_EN_1__FLD LPDDR4__DENALI_CTL_449__PORT_TO_CORE_PROTECTION_INJECTION_EN_1 + +#define LPDDR4__DENALI_CTL_450_READ_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_450_WRITE_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_450__PORT_TO_CORE_PROTECTION_INJECTION_EN_2_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_450__PORT_TO_CORE_PROTECTION_INJECTION_EN_2_SHIFT 0U +#define LPDDR4__DENALI_CTL_450__PORT_TO_CORE_PROTECTION_INJECTION_EN_2_WIDTH 3U +#define LPDDR4__PORT_TO_CORE_PROTECTION_INJECTION_EN_2__REG DENALI_CTL_450 +#define LPDDR4__PORT_TO_CORE_PROTECTION_INJECTION_EN_2__FLD LPDDR4__DENALI_CTL_450__PORT_TO_CORE_PROTECTION_INJECTION_EN_2 + +#define LPDDR4__DENALI_CTL_451_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_451_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_451__MC_RESERVED61_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_451__MC_RESERVED61_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_451__MC_RESERVED61_0_WIDTH 32U +#define LPDDR4__MC_RESERVED61_0__REG DENALI_CTL_451 +#define LPDDR4__MC_RESERVED61_0__FLD LPDDR4__DENALI_CTL_451__MC_RESERVED61_0 + +#define LPDDR4__DENALI_CTL_452_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_452_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_452__MC_RESERVED61_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_452__MC_RESERVED61_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_452__MC_RESERVED61_1_WIDTH 32U +#define LPDDR4__MC_RESERVED61_1__REG DENALI_CTL_452 +#define LPDDR4__MC_RESERVED61_1__FLD LPDDR4__DENALI_CTL_452__MC_RESERVED61_1 + +#define LPDDR4__DENALI_CTL_453_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_453_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_453__MC_RESERVED61_2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_453__MC_RESERVED61_2_SHIFT 0U +#define LPDDR4__DENALI_CTL_453__MC_RESERVED61_2_WIDTH 32U +#define LPDDR4__MC_RESERVED61_2__REG DENALI_CTL_453 +#define LPDDR4__MC_RESERVED61_2__FLD LPDDR4__DENALI_CTL_453__MC_RESERVED61_2 + +#define LPDDR4__DENALI_CTL_454_READ_MASK 0x0000000FU +#define LPDDR4__DENALI_CTL_454_WRITE_MASK 0x0000000FU +#define LPDDR4__DENALI_CTL_454__MC_RESERVED61_3_MASK 0x0000000FU +#define LPDDR4__DENALI_CTL_454__MC_RESERVED61_3_SHIFT 0U +#define LPDDR4__DENALI_CTL_454__MC_RESERVED61_3_WIDTH 4U +#define LPDDR4__MC_RESERVED61_3__REG DENALI_CTL_454 +#define LPDDR4__MC_RESERVED61_3__FLD LPDDR4__DENALI_CTL_454__MC_RESERVED61_3 + +#define LPDDR4__DENALI_CTL_455_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_455_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_455__PORT_TO_CORE_LR_ERR_INJ_EN_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_455__PORT_TO_CORE_LR_ERR_INJ_EN_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_455__PORT_TO_CORE_LR_ERR_INJ_EN_0_WIDTH 32U +#define LPDDR4__PORT_TO_CORE_LR_ERR_INJ_EN_0__REG DENALI_CTL_455 +#define LPDDR4__PORT_TO_CORE_LR_ERR_INJ_EN_0__FLD LPDDR4__DENALI_CTL_455__PORT_TO_CORE_LR_ERR_INJ_EN_0 + +#define LPDDR4__DENALI_CTL_456_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_456_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_456__PORT_TO_CORE_LR_ERR_INJ_EN_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_456__PORT_TO_CORE_LR_ERR_INJ_EN_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_456__PORT_TO_CORE_LR_ERR_INJ_EN_1_WIDTH 32U +#define LPDDR4__PORT_TO_CORE_LR_ERR_INJ_EN_1__REG DENALI_CTL_456 +#define LPDDR4__PORT_TO_CORE_LR_ERR_INJ_EN_1__FLD LPDDR4__DENALI_CTL_456__PORT_TO_CORE_LR_ERR_INJ_EN_1 + +#define LPDDR4__DENALI_CTL_457_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_457_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_457__PORT_TO_CORE_LR_ERR_INJ_EN_2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_457__PORT_TO_CORE_LR_ERR_INJ_EN_2_SHIFT 0U +#define LPDDR4__DENALI_CTL_457__PORT_TO_CORE_LR_ERR_INJ_EN_2_WIDTH 32U +#define LPDDR4__PORT_TO_CORE_LR_ERR_INJ_EN_2__REG DENALI_CTL_457 +#define LPDDR4__PORT_TO_CORE_LR_ERR_INJ_EN_2__FLD LPDDR4__DENALI_CTL_457__PORT_TO_CORE_LR_ERR_INJ_EN_2 + +#define LPDDR4__DENALI_CTL_458_READ_MASK 0x0000000FU +#define LPDDR4__DENALI_CTL_458_WRITE_MASK 0x0000000FU +#define LPDDR4__DENALI_CTL_458__PORT_TO_CORE_LR_ERR_INJ_EN_3_MASK 0x0000000FU +#define LPDDR4__DENALI_CTL_458__PORT_TO_CORE_LR_ERR_INJ_EN_3_SHIFT 0U +#define LPDDR4__DENALI_CTL_458__PORT_TO_CORE_LR_ERR_INJ_EN_3_WIDTH 4U +#define LPDDR4__PORT_TO_CORE_LR_ERR_INJ_EN_3__REG DENALI_CTL_458 +#define LPDDR4__PORT_TO_CORE_LR_ERR_INJ_EN_3__FLD LPDDR4__DENALI_CTL_458__PORT_TO_CORE_LR_ERR_INJ_EN_3 + +#endif /* REG_LPDDR4_DDR_CONTROLLER_MACROS_H_ */ diff --git a/drivers/ram/k3-j721e/lpddr4_if.h b/drivers/ram/k3-j721e/lpddr4_if.h new file mode 100644 index 0000000..66ec3c5 --- /dev/null +++ b/drivers/ram/k3-j721e/lpddr4_if.h @@ -0,0 +1,578 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/********************************************************************** + * Copyright (C) 2012-2019 Cadence Design Systems, Inc. + ********************************************************************** + * WARNING: This file is auto-generated using api-generator utility. + * api-generator: 12.02.13bb8d5 + * Do not edit it manually. + ********************************************************************** + * Cadence Core Driver for LPDDR4. + ********************************************************************** + */ + +#ifndef LPDDR4_IF_H +#define LPDDR4_IF_H + +#include <linux/types.h> + +/** @defgroup ConfigInfo Configuration and Hardware Operation Information + * The following definitions specify the driver operation environment that + * is defined by hardware configuration or client code. These defines are + * located in the header file of the core driver. + * @{ + */ + +/********************************************************************** +* Defines +**********************************************************************/ +/** Number of chip-selects */ +#define LPDDR4_MAX_CS (2U) + +/** Number of accessible registers for controller. */ +#define LPDDR4_CTL_REG_COUNT (459U) + +/** Number of accessible registers for PHY Independent Module. */ +#define LPDDR4_PHY_INDEP_REG_COUNT (300U) + +/** Number of accessible registers for PHY. */ +#define LPDDR4_PHY_REG_COUNT (1423U) + +/** + * @} + */ + +/** @defgroup DataStructure Dynamic Data Structures + * This section defines the data structures used by the driver to provide + * hardware information, modification and dynamic operation of the driver. + * These data structures are defined in the header file of the core driver + * and utilized by the API. + * @{ + */ + +/********************************************************************** +* Forward declarations +**********************************************************************/ +typedef struct lpddr4_config_s lpddr4_config; +typedef struct lpddr4_privatedata_s lpddr4_privatedata; +typedef struct lpddr4_debuginfo_s lpddr4_debuginfo; +typedef struct lpddr4_fspmoderegs_s lpddr4_fspmoderegs; +typedef struct lpddr4_reginitdata_s lpddr4_reginitdata; + +/********************************************************************** +* Enumerations +**********************************************************************/ +/** This is used to indicate whether the Controller, PHY, or PHY Independent module is addressed. */ +typedef enum +{ + LPDDR4_CTL_REGS = 0U, + LPDDR4_PHY_REGS = 1U, + LPDDR4_PHY_INDEP_REGS = 2U +} lpddr4_regblock; + +/** Controller status or error interrupts. */ +typedef enum +{ + LPDDR4_RESET_DONE = 0U, + LPDDR4_BUS_ACCESS_ERROR = 1U, + LPDDR4_MULTIPLE_BUS_ACCESS_ERROR = 2U, + LPDDR4_ECC_MULTIPLE_CORR_ERROR = 3U, + LPDDR4_ECC_MULTIPLE_UNCORR_ERROR = 4U, + LPDDR4_ECC_WRITEBACK_EXEC_ERROR = 5U, + LPDDR4_ECC_SCRUB_DONE = 6U, + LPDDR4_ECC_SCRUB_ERROR = 7U, + LPDDR4_PORT_COMMAND_ERROR = 8U, + LPDDR4_MC_INIT_DONE = 9U, + LPDDR4_LP_DONE = 10U, + LPDDR4_BIST_DONE = 11U, + LPDDR4_WRAP_ERROR = 12U, + LPDDR4_INVALID_BURST_ERROR = 13U, + LPDDR4_RDLVL_ERROR = 14U, + LPDDR4_RDLVL_GATE_ERROR = 15U, + LPDDR4_WRLVL_ERROR = 16U, + LPDDR4_CA_TRAINING_ERROR = 17U, + LPDDR4_DFI_UPDATE_ERROR = 18U, + LPDDR4_MRR_ERROR = 19U, + LPDDR4_PHY_MASTER_ERROR = 20U, + LPDDR4_WRLVL_REQ = 21U, + LPDDR4_RDLVL_REQ = 22U, + LPDDR4_RDLVL_GATE_REQ = 23U, + LPDDR4_CA_TRAINING_REQ = 24U, + LPDDR4_LEVELING_DONE = 25U, + LPDDR4_PHY_ERROR = 26U, + LPDDR4_MR_READ_DONE = 27U, + LPDDR4_TEMP_CHANGE = 28U, + LPDDR4_TEMP_ALERT = 29U, + LPDDR4_SW_DQS_COMPLETE = 30U, + LPDDR4_DQS_OSC_BV_UPDATED = 31U, + LPDDR4_DQS_OSC_OVERFLOW = 32U, + LPDDR4_DQS_OSC_VAR_OUT = 33U, + LPDDR4_MR_WRITE_DONE = 34U, + LPDDR4_INHIBIT_DRAM_DONE = 35U, + LPDDR4_DFI_INIT_STATE = 36U, + LPDDR4_DLL_RESYNC_DONE = 37U, + LPDDR4_TDFI_TO = 38U, + LPDDR4_DFS_DONE = 39U, + LPDDR4_DFS_STATUS = 40U, + LPDDR4_REFRESH_STATUS = 41U, + LPDDR4_ZQ_STATUS = 42U, + LPDDR4_SW_REQ_MODE = 43U, + LPDDR4_LOR_BITS = 44U +} lpddr4_ctlinterrupt; + +/** PHY Independent Module status or error interrupts. */ +typedef enum +{ + LPDDR4_PHY_INDEP_INIT_DONE_BIT = 0U, + LPDDR4_PHY_INDEP_CONTROL_ERROR_BIT = 1U, + LPDDR4_PHY_INDEP_CA_PARITY_ERR_BIT = 2U, + LPDDR4_PHY_INDEP_RDLVL_ERROR_BIT = 3U, + LPDDR4_PHY_INDEP_RDLVL_GATE_ERROR_BIT = 4U, + LPDDR4_PHY_INDEP_WRLVL_ERROR_BIT = 5U, + LPDDR4_PHY_INDEP_CALVL_ERROR_BIT = 6U, + LPDDR4_PHY_INDEP_WDQLVL_ERROR_BIT = 7U, + LPDDR4_PHY_INDEP_UPDATE_ERROR_BIT = 8U, + LPDDR4_PHY_INDEP_RDLVL_REQ_BIT = 9U, + LPDDR4_PHY_INDEP_RDLVL_GATE_REQ_BIT = 10U, + LPDDR4_PHY_INDEP_WRLVL_REQ_BIT = 11U, + LPDDR4_PHY_INDEP_CALVL_REQ_BIT = 12U, + LPDDR4_PHY_INDEP_WDQLVL_REQ_BIT = 13U, + LPDDR4_PHY_INDEP_LVL_DONE_BIT = 14U, + LPDDR4_PHY_INDEP_BIST_DONE_BIT = 15U, + LPDDR4_PHY_INDEP_TDFI_INIT_TIME_OUT_BIT = 16U, + LPDDR4_PHY_INDEP_DLL_LOCK_STATE_CHANGE_BIT = 17U +} lpddr4_phyindepinterrupt; + +/** List of informations and warnings from driver. */ +typedef enum +{ + LPDDR4_DRV_NONE = 0U, + LPDDR4_DRV_SOC_PLL_UPDATE = 1U +} lpddr4_infotype; + +/** Low power interface wake up timing parameters */ +typedef enum +{ + LPDDR4_LPI_PD_WAKEUP_FN = 0U, + LPDDR4_LPI_SR_SHORT_WAKEUP_FN = 1U, + LPDDR4_LPI_SR_LONG_WAKEUP_FN = 2U, + LPDDR4_LPI_SR_LONG_MCCLK_GATE_WAKEUP_FN = 3U, + LPDDR4_LPI_SRPD_SHORT_WAKEUP_FN = 4U, + LPDDR4_LPI_SRPD_LONG_WAKEUP_FN = 5U, + LPDDR4_LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_FN = 6U +} lpddr4_lpiwakeupparam; + +/** Half Datapath mode setting */ +typedef enum +{ + LPDDR4_REDUC_ON = 0U, + LPDDR4_REDUC_OFF = 1U +} lpddr4_reducmode; + +/** ECC Control parameter setting */ +typedef enum +{ + LPDDR4_ECC_DISABLED = 0U, + LPDDR4_ECC_ENABLED = 1U, + LPDDR4_ECC_ERR_DETECT = 2U, + LPDDR4_ECC_ERR_DETECT_CORRECT = 3U +} lpddr4_eccenable; + +/** Data Byte Inversion mode setting */ +typedef enum +{ + LPDDR4_DBI_RD_ON = 0U, + LPDDR4_DBI_RD_OFF = 1U, + LPDDR4_DBI_WR_ON = 2U, + LPDDR4_DBI_WR_OFF = 3U +} lpddr4_dbimode; + +/** Controller Frequency Set Point number */ +typedef enum +{ + LPDDR4_FSP_0 = 0U, + LPDDR4_FSP_1 = 1U, + LPDDR4_FSP_2 = 2U +} lpddr4_ctlfspnum; + +/********************************************************************** +* Callbacks +**********************************************************************/ +/** + * Reports informations and warnings that need to be communicated. + * Params: + * pD - driver state info specific to this instance. + * infoType - Type of information. + */ +typedef void (*lpddr4_infocallback)(const lpddr4_privatedata* pd, lpddr4_infotype infotype); + +/** + * Reports interrupts received by the controller. + * Params: + * pD - driver state info specific to this instance. + * ctlInterrupt - Interrupt raised + * chipSelect - Chip for which interrupt raised + */ +typedef void (*lpddr4_ctlcallback)(const lpddr4_privatedata* pd, lpddr4_ctlinterrupt ctlinterrupt, uint8_t chipselect); + +/** + * Reports interrupts received by the PHY Independent Module. + * Params: + * privateData - driver state info specific to this instance. + * phyIndepInterrupt - Interrupt raised + * chipSelect - Chip for which interrupt raised + */ +typedef void (*lpddr4_phyindepcallback)(const lpddr4_privatedata* pd, lpddr4_phyindepinterrupt phyindepinterrupt, uint8_t chipselect); + +/** + * @} + */ + +/** @defgroup DriverFunctionAPI Driver Function API + * Prototypes for the driver API functions. The user application can link statically to the + * necessary API functions and call them directly. + * @{ + */ + +/********************************************************************** +* API methods +**********************************************************************/ + +/** + * Checks configuration object. + * @param[in] config Driver/hardware configuration required. + * @param[out] configSize Size of memory allocations required. + * @return CDN_EOK on success (requirements structure filled). + * @return ENOTSUP if configuration cannot be supported due to driver/hardware constraints. + */ +uint32_t lpddr4_probe(const lpddr4_config* config, uint16_t* configsize); + +/** + * Init function to be called after LPDDR4_probe() to set up the + * driver configuration. Memory should be allocated for drv_data + * (using the size determined using LPDDR4_probe) before calling this + * API. init_settings should be initialised with base addresses for + * PHY Indepenent Module, Controller and PHY before calling this + * function. If callbacks are required for interrupt handling, these + * should also be configured in init_settings. + * @param[in] pD Driver state info specific to this instance. + * @param[in] cfg Specifies driver/hardware configuration. + * @return CDN_EOK on success + * @return EINVAL if illegal/inconsistent values in cfg. + * @return ENOTSUP if hardware has an inconsistent configuration or doesn't support feature(s) required by 'config' parameters. + */ +uint32_t lpddr4_init(lpddr4_privatedata* pd, const lpddr4_config* cfg); + +/** + * Start the driver. + * @param[in] pD Driver state info specific to this instance. + */ +uint32_t lpddr4_start(const lpddr4_privatedata* pd); + +/** + * Read a register from the controller, PHY or PHY Independent Module + * @param[in] pD Driver state info specific to this instance. + * @param[in] cpp Indicates whether controller, PHY or PHY Independent Module register + * @param[in] regOffset Register offset + * @param[out] regValue Register value read + * @return CDN_EOK on success. + * @return EINVAL if regOffset if out of range or regValue is NULL + */ +uint32_t lpddr4_readreg(const lpddr4_privatedata* pd, lpddr4_regblock cpp, uint32_t regoffset, uint32_t* regvalue); + +/** + * Write a register in the controller, PHY or PHY Independent Module + * @param[in] pD Driver state info specific to this instance. + * @param[in] cpp Indicates whether controller, PHY or PHY Independent Module register + * @param[in] regOffset Register offset + * @param[in] regValue Register value to be written + * @return CDN_EOK on success. + * @return EINVAL if regOffset is out of range or regValue is NULL + */ +uint32_t lpddr4_writereg(const lpddr4_privatedata* pd, lpddr4_regblock cpp, uint32_t regoffset, uint32_t regvalue); + +/** + * Read a memory mode register from DRAM + * @param[in] pD Driver state info specific to this instance. + * @param[in] readModeRegVal Value to set in 'read_modereg' parameter. + * @param[out] mmrValue Value which is read from memory mode register(mmr) for all devices. + * @param[out] mmrStatus Status of mode register read(mrr) instruction. + * @return CDN_EOK on success. + * @return EINVAL if regNumber is out of range or regValue is NULL + */ +uint32_t lpddr4_getmmrregister(const lpddr4_privatedata* pd, uint32_t readmoderegval, uint64_t* mmrvalue, uint8_t* mmrstatus); + +/** + * Write a memory mode register in DRAM + * @param[in] pD Driver state info specific to this instance. + * @param[in] writeModeRegVal Value to set in 'write_modereg' parameter. + * @param[out] mrwStatus Status of mode register write(mrw) instruction. + * @return CDN_EOK on success. + * @return EINVAL if regNumber is out of range or regValue is NULL + */ +uint32_t lpddr4_setmmrregister(const lpddr4_privatedata* pd, uint32_t writemoderegval, uint8_t* mrwstatus); + +/** + * Write a set of initialisation values to the controller registers + * @param[in] pD Driver state info specific to this instance. + * @param[in] regValues Register values to be written + * @return CDN_EOK on success. + * @return EINVAL if regValues is NULL + */ +uint32_t lpddr4_writectlconfig(const lpddr4_privatedata* pd, const lpddr4_reginitdata* regvalues); + +/** + * Write a set of initialisation values to the PHY registers + * @param[in] pD Driver state info specific to this instance. + * @param[in] regValues Register values to be written + * @return CDN_EOK on success. + * @return EINVAL if regValues is NULL + */ +uint32_t lpddr4_writephyconfig(const lpddr4_privatedata* pd, const lpddr4_reginitdata* regvalues); + +/** + * Write a set of initialisation values to the PHY Independent Module + * registers + * @param[in] pD Driver state info specific to this instance. + * @param[in] regValues Register values to be written + * @return CDN_EOK on success. + * @return EINVAL if regValues is NULL + */ +uint32_t lpddr4_writephyindepconfig(const lpddr4_privatedata* pd, const lpddr4_reginitdata* regvalues); + +/** + * Read values of the controller registers in bulk (Set 'updateCtlReg' + * to read) and store in memory. + * @param[in] pD Driver state info specific to this instance. + * @param[out] regValues Register values which are read + * @return CDN_EOK on success. + * @return EINVAL if regValues is NULL + */ +uint32_t lpddr4_readctlconfig(const lpddr4_privatedata* pd, lpddr4_reginitdata* regvalues); + +/** + * Read the values of the PHY module registers in bulk (Set + * 'updatePhyReg' to read) and store in memory. + * @param[in] pD Driver state info specific to this instance. + * @param[out] regValues Register values which are read + * @return CDN_EOK on success. + * @return EINVAL if regValues is NULL + */ +uint32_t lpddr4_readphyconfig(const lpddr4_privatedata* pd, lpddr4_reginitdata* regvalues); + +/** + * Read the values of the PHY Independent module registers in bulk(Set + * 'updatePhyIndepReg' to read) and store in memory. + * @param[in] pD Driver state info specific to this instance. + * @param[out] regValues Register values which are read + * @return CDN_EOK on success. + * @return EINVAL if regValues is NULL + */ +uint32_t lpddr4_readphyindepconfig(const lpddr4_privatedata* pd, lpddr4_reginitdata* regvalues); + +/** + * Read the current interrupt mask for the controller + * @param[in] pD Driver state info specific to this instance. + * @param[out] mask Value of interrupt mask + * @return CDN_EOK on success. + * @return EINVAL if mask pointer is NULL + */ +uint32_t lpddr4_getctlinterruptmask(const lpddr4_privatedata* pd, uint64_t* mask); + +/** + * Sets the interrupt mask for the controller + * @param[in] pD Driver state info specific to this instance. + * @param[in] mask Value of interrupt mask to be written + * @return CDN_EOK on success. + * @return EINVAL if mask pointer is NULL + */ +uint32_t lpddr4_setctlinterruptmask(const lpddr4_privatedata* pd, const uint64_t* mask); + +/** + * Check whether a specific controller interrupt is active + * @param[in] pD Driver state info specific to this instance. + * @param[in] intr Interrupt to be checked + * @param[out] irqStatus Status of the interrupt, TRUE if active + * @return CDN_EOK on success. + * @return EINVAL if intr is not valid + */ +uint32_t lpddr4_checkctlinterrupt(const lpddr4_privatedata* pd, lpddr4_ctlinterrupt intr, bool* irqstatus); + +/** + * Acknowledge a specific controller interrupt + * @param[in] pD Driver state info specific to this instance. + * @param[in] intr Interrupt to be acknowledged + * @return CDN_EOK on success. + * @return EINVAL if intr is not valid + */ +uint32_t lpddr4_ackctlinterrupt(const lpddr4_privatedata* pd, lpddr4_ctlinterrupt intr); + +/** + * Read the current interrupt mask for the PHY Independent Module + * @param[in] pD Driver state info specific to this instance. + * @param[out] mask Value of interrupt mask + * @return CDN_EOK on success. + * @return EINVAL if mask pointer is NULL + */ +uint32_t lpddr4_getphyindepinterruptmask(const lpddr4_privatedata* pd, uint32_t* mask); + +/** + * Sets the interrupt mask for the PHY Independent Module + * @param[in] pD Driver state info specific to this instance. + * @param[in] mask Value of interrupt mask to be written + * @return CDN_EOK on success. + * @return EINVAL if mask pointer is NULL + */ +uint32_t lpddr4_setphyindepinterruptmask(const lpddr4_privatedata* pd, const uint32_t* mask); + +/** + * Check whether a specific PHY Independent Module interrupt is active + * @param[in] pD Driver state info specific to this instance. + * @param[in] intr Interrupt to be checked + * @param[out] irqStatus Status of the interrupt, TRUE if active + * @return CDN_EOK on success. + * @return EINVAL if intr is not valid + */ +uint32_t lpddr4_checkphyindepinterrupt(const lpddr4_privatedata* pd, lpddr4_phyindepinterrupt intr, bool* irqstatus); + +/** + * Acknowledge a specific PHY Independent Module interrupt + * @param[in] pD Driver state info specific to this instance. + * @param[in] intr Interrupt to be acknowledged + * @return CDN_EOK on success. + * @return EINVAL if intr is not valid + */ +uint32_t lpddr4_ackphyindepinterrupt(const lpddr4_privatedata* pd, lpddr4_phyindepinterrupt intr); + +/** + * Retrieve status information after a failed init. The + * DebugStructInfo will be filled in with error codes which can be + * referenced against the driver documentation for further details. + * @param[in] pD Driver state info specific to this instance. + * @param[out] debugInfo status + * @return CDN_EOK on success. + * @return EINVAL if debugInfo is NULL + */ +uint32_t lpddr4_getdebuginitinfo(const lpddr4_privatedata* pd, lpddr4_debuginfo* debuginfo); + +/** + * Get the current value of Low power Interface wake up time. + * @param[in] pD Driver state info specific to this instance. + * @param[in] lpiWakeUpParam LPI timing parameter + * @param[in] fspNum Frequency copy + * @param[out] cycles Timing value(in cycles) + * @return CDN_EOK on success. + * @return EINVAL if powerMode is NULL + */ +uint32_t lpddr4_getlpiwakeuptime(const lpddr4_privatedata* pd, const lpddr4_lpiwakeupparam* lpiwakeupparam, const lpddr4_ctlfspnum* fspnum, uint32_t* cycles); + +/** + * Set the current value of Low power Interface wake up time. + * @param[in] pD Driver state info specific to this instance. + * @param[in] lpiWakeUpParam LPI timing parameter + * @param[in] fspNum Frequency copy + * @param[in] cycles Timing value(in cycles) + * @return CDN_EOK on success. + * @return EINVAL if powerMode is NULL + */ +uint32_t lpddr4_setlpiwakeuptime(const lpddr4_privatedata* pd, const lpddr4_lpiwakeupparam* lpiwakeupparam, const lpddr4_ctlfspnum* fspnum, const uint32_t* cycles); + +/** + * Get the current value for ECC auto correction + * @param[in] pD Driver state info specific to this instance. + * @param[out] eccParam ECC parameter setting + * @return CDN_EOK on success. + * @return EINVAL if on_off is NULL + */ +uint32_t lpddr4_geteccenable(const lpddr4_privatedata* pd, lpddr4_eccenable* eccparam); + +/** + * Set the value for ECC auto correction. This API must be called + * before startup of memory. + * @param[in] pD Driver state info specific to this instance. + * @param[in] eccParam ECC control parameter setting + * @return CDN_EOK on success. + * @return EINVAL if on_off is NULL + */ +uint32_t lpddr4_seteccenable(const lpddr4_privatedata* pd, const lpddr4_eccenable* eccparam); + +/** + * Get the current value for the Half Datapath option + * @param[in] pD Driver state info specific to this instance. + * @param[out] mode Half Datapath setting + * @return CDN_EOK on success. + * @return EINVAL if mode is NULL + */ +uint32_t lpddr4_getreducmode(const lpddr4_privatedata* pd, lpddr4_reducmode* mode); + +/** + * Set the value for the Half Datapath option. This API must be + * called before startup of memory. + * @param[in] pD Driver state info specific to this instance. + * @param[in] mode Half Datapath setting + * @return CDN_EOK on success. + * @return EINVAL if mode is NULL + */ +uint32_t lpddr4_setreducmode(const lpddr4_privatedata* pd, const lpddr4_reducmode* mode); + +/** + * Get the current value for Data Bus Inversion setting. This will be + * compared with the current DRAM setting using the MR3 register. + * @param[in] pD Driver state info specific to this instance. + * @param[out] on_off DBI read value + * @return CDN_EOK on success. + * @return EINVAL if on_off is NULL + */ +uint32_t lpddr4_getdbireadmode(const lpddr4_privatedata* pd, bool* on_off); + +/** + * Get the current value for Data Bus Inversion setting. This will be + * compared with the current DRAM setting using the MR3 register. + * @param[in] pD Driver state info specific to this instance. + * @param[out] on_off DBI write value + * @return CDN_EOK on success. + * @return EINVAL if on_off is NULL + */ +uint32_t lpddr4_getdbiwritemode(const lpddr4_privatedata* pd, bool* on_off); + +/** + * Set the mode for Data Bus Inversion. This will also be set in DRAM + * using the MR3 controller register. This API must be called before + * startup of memory. + * @param[in] pD Driver state info specific to this instance. + * @param[in] mode status + * @return CDN_EOK on success. + * @return EINVAL if mode is NULL + */ +uint32_t lpddr4_setdbimode(const lpddr4_privatedata* pd, const lpddr4_dbimode* mode); + +/** + * Get the current value for the refresh rate (reading Refresh per + * command timing). + * @param[in] pD Driver state info specific to this instance. + * @param[in] fspNum Frequency set number + * @param[out] cycles Refresh rate (in cycles) + * @return CDN_EOK on success. + * @return EINVAL if rate is NULL + */ +uint32_t lpddr4_getrefreshrate(const lpddr4_privatedata* pd, const lpddr4_ctlfspnum* fspnum, uint32_t* cycles); + +/** + * Set the refresh rate (writing Refresh per command timing). + * @param[in] pD Driver state info specific to this instance. + * @param[in] fspNum Frequency set number + * @param[in] cycles Refresh rate (in cycles) + * @return CDN_EOK on success. + * @return EINVAL if rate is NULL + */ +uint32_t lpddr4_setrefreshrate(const lpddr4_privatedata* pd, const lpddr4_ctlfspnum* fspnum, const uint32_t* cycles); + +/** + * Handle Refreshing per chip select + * @param[in] pD Driver state info specific to this instance. + * @param[in] trefInterval status + * @return CDN_EOK on success. + * @return EINVAL if chipSelect is invalid + */ +uint32_t lpddr4_refreshperchipselect(const lpddr4_privatedata* pd, const uint32_t trefinterval); + +#endif /* LPDDR4_IF_H */ diff --git a/drivers/ram/k3-j721e/lpddr4_obj_if.c b/drivers/ram/k3-j721e/lpddr4_obj_if.c new file mode 100644 index 0000000..35b3db6 --- /dev/null +++ b/drivers/ram/k3-j721e/lpddr4_obj_if.c @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: BSD-3-Clause +/********************************************************************** + * Copyright (C) 2012-2019 Cadence Design Systems, Inc. + ********************************************************************** + * WARNING: This file is auto-generated using api-generator utility. + * api-generator: 12.02.13bb8d5 + * Do not edit it manually. + ********************************************************************** + * Cadence Core Driver for LPDDR4. + ********************************************************************** + */ + +#include "lpddr4_obj_if.h" + +LPDDR4_OBJ *lpddr4_getinstance(void) +{ + static LPDDR4_OBJ driver = { + .probe = lpddr4_probe, + .init = lpddr4_init, + .start = lpddr4_start, + .readreg = lpddr4_readreg, + .writereg = lpddr4_writereg, + .getmmrregister = lpddr4_getmmrregister, + .setmmrregister = lpddr4_setmmrregister, + .writectlconfig = lpddr4_writectlconfig, + .writephyconfig = lpddr4_writephyconfig, + .writephyindepconfig = lpddr4_writephyindepconfig, + .readctlconfig = lpddr4_readctlconfig, + .readphyconfig = lpddr4_readphyconfig, + .readphyindepconfig = lpddr4_readphyindepconfig, + .getctlinterruptmask = lpddr4_getctlinterruptmask, + .setctlinterruptmask = lpddr4_setctlinterruptmask, + .checkctlinterrupt = lpddr4_checkctlinterrupt, + .ackctlinterrupt = lpddr4_ackctlinterrupt, + .getphyindepinterruptmask = lpddr4_getphyindepinterruptmask, + .setphyindepinterruptmask = lpddr4_setphyindepinterruptmask, + .checkphyindepinterrupt = lpddr4_checkphyindepinterrupt, + .ackphyindepinterrupt = lpddr4_ackphyindepinterrupt, + .getdebuginitinfo = lpddr4_getdebuginitinfo, + .getlpiwakeuptime = lpddr4_getlpiwakeuptime, + .setlpiwakeuptime = lpddr4_setlpiwakeuptime, + .geteccenable = lpddr4_geteccenable, + .seteccenable = lpddr4_seteccenable, + .getreducmode = lpddr4_getreducmode, + .setreducmode = lpddr4_setreducmode, + .getdbireadmode = lpddr4_getdbireadmode, + .getdbiwritemode = lpddr4_getdbiwritemode, + .setdbimode = lpddr4_setdbimode, + .getrefreshrate = lpddr4_getrefreshrate, + .setrefreshrate = lpddr4_setrefreshrate, + .refreshperchipselect = lpddr4_refreshperchipselect, + }; + + return &driver; +} diff --git a/drivers/ram/k3-j721e/lpddr4_obj_if.h b/drivers/ram/k3-j721e/lpddr4_obj_if.h new file mode 100644 index 0000000..33dae6f --- /dev/null +++ b/drivers/ram/k3-j721e/lpddr4_obj_if.h @@ -0,0 +1,383 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/********************************************************************** + * Copyright (C) 2012-2019 Cadence Design Systems, Inc. + ********************************************************************** + * WARNING: This file is auto-generated using api-generator utility. + * api-generator: 12.02.13bb8d5 + * Do not edit it manually. + ********************************************************************** + * Cadence Core Driver for LPDDR4. + ********************************************************************** + */ +#ifndef LPDDR4_OBJ_IF_H +#define LPDDR4_OBJ_IF_H + +#include "lpddr4_if.h" + +/** @defgroup DriverObject Driver API Object + * API listing for the driver. The API is contained in the object as + * function pointers in the object structure. As the actual functions + * resides in the Driver Object, the client software must first use the + * global GetInstance function to obtain the Driver Object Pointer. + * The actual APIs then can be invoked using obj->(api_name)() syntax. + * These functions are defined in the header file of the core driver + * and utilized by the API. + * @{ + */ + +/********************************************************************** +* API methods +**********************************************************************/ +typedef struct lpddr4_obj_s +{ + /** + * Checks configuration object. + * @param[in] config Driver/hardware configuration required. + * @param[out] configSize Size of memory allocations required. + * @return CDN_EOK on success (requirements structure filled). + * @return ENOTSUP if configuration cannot be supported due to driver/hardware constraints. + */ + uint32_t (*probe)(const lpddr4_config* config, uint16_t* configsize); + + /** + * Init function to be called after LPDDR4_probe() to set up the + * driver configuration. Memory should be allocated for drv_data + * (using the size determined using LPDDR4_probe) before calling + * this API. init_settings should be initialised with base addresses + * for PHY Indepenent Module, Controller and PHY before calling this + * function. If callbacks are required for interrupt handling, these + * should also be configured in init_settings. + * @param[in] pD Driver state info specific to this instance. + * @param[in] cfg Specifies driver/hardware configuration. + * @return CDN_EOK on success + * @return EINVAL if illegal/inconsistent values in cfg. + * @return ENOTSUP if hardware has an inconsistent configuration or doesn't support feature(s) required by 'config' parameters. + */ + uint32_t (*init)(lpddr4_privatedata* pd, const lpddr4_config* cfg); + + /** + * Start the driver. + * @param[in] pD Driver state info specific to this instance. + */ + uint32_t (*start)(const lpddr4_privatedata* pd); + + /** + * Read a register from the controller, PHY or PHY Independent Module + * @param[in] pD Driver state info specific to this instance. + * @param[in] cpp Indicates whether controller, PHY or PHY Independent Module register + * @param[in] regOffset Register offset + * @param[out] regValue Register value read + * @return CDN_EOK on success. + * @return EINVAL if regOffset if out of range or regValue is NULL + */ + uint32_t (*readreg)(const lpddr4_privatedata* pd, lpddr4_regblock cpp, uint32_t regoffset, uint32_t* regvalue); + + /** + * Write a register in the controller, PHY or PHY Independent Module + * @param[in] pD Driver state info specific to this instance. + * @param[in] cpp Indicates whether controller, PHY or PHY Independent Module register + * @param[in] regOffset Register offset + * @param[in] regValue Register value to be written + * @return CDN_EOK on success. + * @return EINVAL if regOffset is out of range or regValue is NULL + */ + uint32_t (*writereg)(const lpddr4_privatedata* pd, lpddr4_regblock cpp, uint32_t regoffset, uint32_t regvalue); + + /** + * Read a memory mode register from DRAM + * @param[in] pD Driver state info specific to this instance. + * @param[in] readModeRegVal Value to set in 'read_modereg' parameter. + * @param[out] mmrValue Value which is read from memory mode register(mmr) for all devices. + * @param[out] mmrStatus Status of mode register read(mrr) instruction. + * @return CDN_EOK on success. + * @return EINVAL if regNumber is out of range or regValue is NULL + */ + uint32_t (*getmmrregister)(const lpddr4_privatedata* pd, uint32_t readmoderegval, uint64_t* mmrvalue, uint8_t* mmrstatus); + + /** + * Write a memory mode register in DRAM + * @param[in] pD Driver state info specific to this instance. + * @param[in] writeModeRegVal Value to set in 'write_modereg' parameter. + * @param[out] mrwStatus Status of mode register write(mrw) instruction. + * @return CDN_EOK on success. + * @return EINVAL if regNumber is out of range or regValue is NULL + */ + uint32_t (*setmmrregister)(const lpddr4_privatedata* pd, uint32_t writemoderegval, uint8_t* mrwstatus); + + /** + * Write a set of initialisation values to the controller registers + * @param[in] pD Driver state info specific to this instance. + * @param[in] regValues Register values to be written + * @return CDN_EOK on success. + * @return EINVAL if regValues is NULL + */ + uint32_t (*writectlconfig)(const lpddr4_privatedata* pd, const lpddr4_reginitdata* regvalues); + + /** + * Write a set of initialisation values to the PHY registers + * @param[in] pD Driver state info specific to this instance. + * @param[in] regValues Register values to be written + * @return CDN_EOK on success. + * @return EINVAL if regValues is NULL + */ + uint32_t (*writephyconfig)(const lpddr4_privatedata* pd, const lpddr4_reginitdata* regvalues); + + /** + * Write a set of initialisation values to the PHY Independent Module + * registers + * @param[in] pD Driver state info specific to this instance. + * @param[in] regValues Register values to be written + * @return CDN_EOK on success. + * @return EINVAL if regValues is NULL + */ + uint32_t (*writephyindepconfig)(const lpddr4_privatedata* pd, const lpddr4_reginitdata* regvalues); + + /** + * Read values of the controller registers in bulk (Set + * 'updateCtlReg' to read) and store in memory. + * @param[in] pD Driver state info specific to this instance. + * @param[out] regValues Register values which are read + * @return CDN_EOK on success. + * @return EINVAL if regValues is NULL + */ + uint32_t (*readctlconfig)(const lpddr4_privatedata* pd, lpddr4_reginitdata* regvalues); + + /** + * Read the values of the PHY module registers in bulk (Set + * 'updatePhyReg' to read) and store in memory. + * @param[in] pD Driver state info specific to this instance. + * @param[out] regValues Register values which are read + * @return CDN_EOK on success. + * @return EINVAL if regValues is NULL + */ + uint32_t (*readphyconfig)(const lpddr4_privatedata* pd, lpddr4_reginitdata* regvalues); + + /** + * Read the values of the PHY Independent module registers in + * bulk(Set 'updatePhyIndepReg' to read) and store in memory. + * @param[in] pD Driver state info specific to this instance. + * @param[out] regValues Register values which are read + * @return CDN_EOK on success. + * @return EINVAL if regValues is NULL + */ + uint32_t (*readphyindepconfig)(const lpddr4_privatedata* pd, lpddr4_reginitdata* regvalues); + + /** + * Read the current interrupt mask for the controller + * @param[in] pD Driver state info specific to this instance. + * @param[out] mask Value of interrupt mask + * @return CDN_EOK on success. + * @return EINVAL if mask pointer is NULL + */ + uint32_t (*getctlinterruptmask)(const lpddr4_privatedata* pd, uint64_t* mask); + + /** + * Sets the interrupt mask for the controller + * @param[in] pD Driver state info specific to this instance. + * @param[in] mask Value of interrupt mask to be written + * @return CDN_EOK on success. + * @return EINVAL if mask pointer is NULL + */ + uint32_t (*setctlinterruptmask)(const lpddr4_privatedata* pd, const uint64_t* mask); + + /** + * Check whether a specific controller interrupt is active + * @param[in] pD Driver state info specific to this instance. + * @param[in] intr Interrupt to be checked + * @param[out] irqStatus Status of the interrupt, TRUE if active + * @return CDN_EOK on success. + * @return EINVAL if intr is not valid + */ + uint32_t (*checkctlinterrupt)(const lpddr4_privatedata* pd, lpddr4_ctlinterrupt intr, bool* irqstatus); + + /** + * Acknowledge a specific controller interrupt + * @param[in] pD Driver state info specific to this instance. + * @param[in] intr Interrupt to be acknowledged + * @return CDN_EOK on success. + * @return EINVAL if intr is not valid + */ + uint32_t (*ackctlinterrupt)(const lpddr4_privatedata* pd, lpddr4_ctlinterrupt intr); + + /** + * Read the current interrupt mask for the PHY Independent Module + * @param[in] pD Driver state info specific to this instance. + * @param[out] mask Value of interrupt mask + * @return CDN_EOK on success. + * @return EINVAL if mask pointer is NULL + */ + uint32_t (*getphyindepinterruptmask)(const lpddr4_privatedata* pd, uint32_t* mask); + + /** + * Sets the interrupt mask for the PHY Independent Module + * @param[in] pD Driver state info specific to this instance. + * @param[in] mask Value of interrupt mask to be written + * @return CDN_EOK on success. + * @return EINVAL if mask pointer is NULL + */ + uint32_t (*setphyindepinterruptmask)(const lpddr4_privatedata* pd, const uint32_t* mask); + + /** + * Check whether a specific PHY Independent Module interrupt is + * active + * @param[in] pD Driver state info specific to this instance. + * @param[in] intr Interrupt to be checked + * @param[out] irqStatus Status of the interrupt, TRUE if active + * @return CDN_EOK on success. + * @return EINVAL if intr is not valid + */ + uint32_t (*checkphyindepinterrupt)(const lpddr4_privatedata* pd, lpddr4_phyindepinterrupt intr, bool* irqstatus); + + /** + * Acknowledge a specific PHY Independent Module interrupt + * @param[in] pD Driver state info specific to this instance. + * @param[in] intr Interrupt to be acknowledged + * @return CDN_EOK on success. + * @return EINVAL if intr is not valid + */ + uint32_t (*ackphyindepinterrupt)(const lpddr4_privatedata* pd, lpddr4_phyindepinterrupt intr); + + /** + * Retrieve status information after a failed init. The + * DebugStructInfo will be filled in with error codes which can be + * referenced against the driver documentation for further details. + * @param[in] pD Driver state info specific to this instance. + * @param[out] debugInfo status + * @return CDN_EOK on success. + * @return EINVAL if debugInfo is NULL + */ + uint32_t (*getdebuginitinfo)(const lpddr4_privatedata* pd, lpddr4_debuginfo* debuginfo); + + /** + * Get the current value of Low power Interface wake up time. + * @param[in] pD Driver state info specific to this instance. + * @param[in] lpiWakeUpParam LPI timing parameter + * @param[in] fspNum Frequency copy + * @param[out] cycles Timing value(in cycles) + * @return CDN_EOK on success. + * @return EINVAL if powerMode is NULL + */ + uint32_t (*getlpiwakeuptime)(const lpddr4_privatedata* pd, const lpddr4_lpiwakeupparam* lpiwakeupparam, const lpddr4_ctlfspnum* fspnum, uint32_t* cycles); + + /** + * Set the current value of Low power Interface wake up time. + * @param[in] pD Driver state info specific to this instance. + * @param[in] lpiWakeUpParam LPI timing parameter + * @param[in] fspNum Frequency copy + * @param[in] cycles Timing value(in cycles) + * @return CDN_EOK on success. + * @return EINVAL if powerMode is NULL + */ + uint32_t (*setlpiwakeuptime)(const lpddr4_privatedata* pd, const lpddr4_lpiwakeupparam* lpiwakeupparam, const lpddr4_ctlfspnum* fspnum, const uint32_t* cycles); + + /** + * Get the current value for ECC auto correction + * @param[in] pD Driver state info specific to this instance. + * @param[out] eccParam ECC parameter setting + * @return CDN_EOK on success. + * @return EINVAL if on_off is NULL + */ + uint32_t (*geteccenable)(const lpddr4_privatedata* pd, lpddr4_eccenable* eccparam); + + /** + * Set the value for ECC auto correction. This API must be called + * before startup of memory. + * @param[in] pD Driver state info specific to this instance. + * @param[in] eccParam ECC control parameter setting + * @return CDN_EOK on success. + * @return EINVAL if on_off is NULL + */ + uint32_t (*seteccenable)(const lpddr4_privatedata* pd, const lpddr4_eccenable* eccparam); + + /** + * Get the current value for the Half Datapath option + * @param[in] pD Driver state info specific to this instance. + * @param[out] mode Half Datapath setting + * @return CDN_EOK on success. + * @return EINVAL if mode is NULL + */ + uint32_t (*getreducmode)(const lpddr4_privatedata* pd, lpddr4_reducmode* mode); + + /** + * Set the value for the Half Datapath option. This API must be + * called before startup of memory. + * @param[in] pD Driver state info specific to this instance. + * @param[in] mode Half Datapath setting + * @return CDN_EOK on success. + * @return EINVAL if mode is NULL + */ + uint32_t (*setreducmode)(const lpddr4_privatedata* pd, const lpddr4_reducmode* mode); + + /** + * Get the current value for Data Bus Inversion setting. This will + * be compared with the current DRAM setting using the MR3 + * register. + * @param[in] pD Driver state info specific to this instance. + * @param[out] on_off DBI read value + * @return CDN_EOK on success. + * @return EINVAL if on_off is NULL + */ + uint32_t (*getdbireadmode)(const lpddr4_privatedata* pd, bool* on_off); + + /** + * Get the current value for Data Bus Inversion setting. This will + * be compared with the current DRAM setting using the MR3 + * register. + * @param[in] pD Driver state info specific to this instance. + * @param[out] on_off DBI write value + * @return CDN_EOK on success. + * @return EINVAL if on_off is NULL + */ + uint32_t (*getdbiwritemode)(const lpddr4_privatedata* pd, bool* on_off); + + /** + * Set the mode for Data Bus Inversion. This will also be set in DRAM + * using the MR3 controller register. This API must be called + * before startup of memory. + * @param[in] pD Driver state info specific to this instance. + * @param[in] mode status + * @return CDN_EOK on success. + * @return EINVAL if mode is NULL + */ + uint32_t (*setdbimode)(const lpddr4_privatedata* pd, const lpddr4_dbimode* mode); + + /** + * Get the current value for the refresh rate (reading Refresh per + * command timing). + * @param[in] pD Driver state info specific to this instance. + * @param[in] fspNum Frequency set number + * @param[out] cycles Refresh rate (in cycles) + * @return CDN_EOK on success. + * @return EINVAL if rate is NULL + */ + uint32_t (*getrefreshrate)(const lpddr4_privatedata* pd, const lpddr4_ctlfspnum* fspnum, uint32_t* cycles); + + /** + * Set the refresh rate (writing Refresh per command timing). + * @param[in] pD Driver state info specific to this instance. + * @param[in] fspNum Frequency set number + * @param[in] cycles Refresh rate (in cycles) + * @return CDN_EOK on success. + * @return EINVAL if rate is NULL + */ + uint32_t (*setrefreshrate)(const lpddr4_privatedata* pd, const lpddr4_ctlfspnum* fspnum, const uint32_t* cycles); + + /** + * Handle Refreshing per chip select + * @param[in] pD Driver state info specific to this instance. + * @param[in] trefInterval status + * @return CDN_EOK on success. + * @return EINVAL if chipSelect is invalid + */ + uint32_t (*refreshperchipselect)(const lpddr4_privatedata* pd, const uint32_t trefinterval); + +} LPDDR4_OBJ; + +/** + * In order to access the LPDDR4 APIs, the upper layer software must call + * this global function to obtain the pointer to the driver object. + * @return LPDDR4_OBJ* Driver Object Pointer + */ +extern LPDDR4_OBJ *lpddr4_getinstance(void); + +#endif /* LPDDR4_OBJ_IF_H */ diff --git a/drivers/ram/k3-j721e/lpddr4_phy_core_macros.h b/drivers/ram/k3-j721e/lpddr4_phy_core_macros.h new file mode 100644 index 0000000..e8579ff --- /dev/null +++ b/drivers/ram/k3-j721e/lpddr4_phy_core_macros.h @@ -0,0 +1,2061 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/********************************************************************** + * Copyright (C) 2012-2019 Cadence Design Systems, Inc. + * + * THIS FILE IS AUTOMATICALLY GENERATED, DO NOT EDIT + * + ********************************************************************** + */ + +#ifndef REG_LPDDR4_PHY_CORE_MACROS_H_ +#define REG_LPDDR4_PHY_CORE_MACROS_H_ + +#define LPDDR4__DENALI_PHY_1280_READ_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_1280_WRITE_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_1280__PHY_FREQ_SEL_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_1280__PHY_FREQ_SEL_SHIFT 0U +#define LPDDR4__DENALI_PHY_1280__PHY_FREQ_SEL_WIDTH 2U +#define LPDDR4__PHY_FREQ_SEL__REG DENALI_PHY_1280 +#define LPDDR4__PHY_FREQ_SEL__FLD LPDDR4__DENALI_PHY_1280__PHY_FREQ_SEL + +#define LPDDR4__DENALI_PHY_1281_READ_MASK 0x1F030101U +#define LPDDR4__DENALI_PHY_1281_WRITE_MASK 0x1F030101U +#define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_FROM_REGIF_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_FROM_REGIF_SHIFT 0U +#define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_FROM_REGIF_WIDTH 1U +#define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_FROM_REGIF_WOCLR 0U +#define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_FROM_REGIF_WOSET 0U +#define LPDDR4__PHY_FREQ_SEL_FROM_REGIF__REG DENALI_PHY_1281 +#define LPDDR4__PHY_FREQ_SEL_FROM_REGIF__FLD LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_FROM_REGIF + +#define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_MULTICAST_EN_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_MULTICAST_EN_SHIFT 8U +#define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_MULTICAST_EN_WIDTH 1U +#define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_MULTICAST_EN_WOCLR 0U +#define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_MULTICAST_EN_WOSET 0U +#define LPDDR4__PHY_FREQ_SEL_MULTICAST_EN__REG DENALI_PHY_1281 +#define LPDDR4__PHY_FREQ_SEL_MULTICAST_EN__FLD LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_MULTICAST_EN + +#define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_INDEX_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_INDEX_SHIFT 16U +#define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_INDEX_WIDTH 2U +#define LPDDR4__PHY_FREQ_SEL_INDEX__REG DENALI_PHY_1281 +#define LPDDR4__PHY_FREQ_SEL_INDEX__FLD LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_INDEX + +#define LPDDR4__DENALI_PHY_1281__PHY_SW_GRP0_SHIFT_0_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_1281__PHY_SW_GRP0_SHIFT_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_1281__PHY_SW_GRP0_SHIFT_0_WIDTH 5U +#define LPDDR4__PHY_SW_GRP0_SHIFT_0__REG DENALI_PHY_1281 +#define LPDDR4__PHY_SW_GRP0_SHIFT_0__FLD LPDDR4__DENALI_PHY_1281__PHY_SW_GRP0_SHIFT_0 + +#define LPDDR4__DENALI_PHY_1282_READ_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_PHY_1282_WRITE_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP1_SHIFT_0_MASK 0x0000001FU +#define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP1_SHIFT_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP1_SHIFT_0_WIDTH 5U +#define LPDDR4__PHY_SW_GRP1_SHIFT_0__REG DENALI_PHY_1282 +#define LPDDR4__PHY_SW_GRP1_SHIFT_0__FLD LPDDR4__DENALI_PHY_1282__PHY_SW_GRP1_SHIFT_0 + +#define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP2_SHIFT_0_MASK 0x00001F00U +#define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP2_SHIFT_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP2_SHIFT_0_WIDTH 5U +#define LPDDR4__PHY_SW_GRP2_SHIFT_0__REG DENALI_PHY_1282 +#define LPDDR4__PHY_SW_GRP2_SHIFT_0__FLD LPDDR4__DENALI_PHY_1282__PHY_SW_GRP2_SHIFT_0 + +#define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP3_SHIFT_0_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP3_SHIFT_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP3_SHIFT_0_WIDTH 5U +#define LPDDR4__PHY_SW_GRP3_SHIFT_0__REG DENALI_PHY_1282 +#define LPDDR4__PHY_SW_GRP3_SHIFT_0__FLD LPDDR4__DENALI_PHY_1282__PHY_SW_GRP3_SHIFT_0 + +#define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP0_SHIFT_1_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP0_SHIFT_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP0_SHIFT_1_WIDTH 5U +#define LPDDR4__PHY_SW_GRP0_SHIFT_1__REG DENALI_PHY_1282 +#define LPDDR4__PHY_SW_GRP0_SHIFT_1__FLD LPDDR4__DENALI_PHY_1282__PHY_SW_GRP0_SHIFT_1 + +#define LPDDR4__DENALI_PHY_1283_READ_MASK 0x001F1F1FU +#define LPDDR4__DENALI_PHY_1283_WRITE_MASK 0x001F1F1FU +#define LPDDR4__DENALI_PHY_1283__PHY_SW_GRP1_SHIFT_1_MASK 0x0000001FU +#define LPDDR4__DENALI_PHY_1283__PHY_SW_GRP1_SHIFT_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_1283__PHY_SW_GRP1_SHIFT_1_WIDTH 5U +#define LPDDR4__PHY_SW_GRP1_SHIFT_1__REG DENALI_PHY_1283 +#define LPDDR4__PHY_SW_GRP1_SHIFT_1__FLD LPDDR4__DENALI_PHY_1283__PHY_SW_GRP1_SHIFT_1 + +#define LPDDR4__DENALI_PHY_1283__PHY_SW_GRP2_SHIFT_1_MASK 0x00001F00U +#define LPDDR4__DENALI_PHY_1283__PHY_SW_GRP2_SHIFT_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_1283__PHY_SW_GRP2_SHIFT_1_WIDTH 5U +#define LPDDR4__PHY_SW_GRP2_SHIFT_1__REG DENALI_PHY_1283 +#define LPDDR4__PHY_SW_GRP2_SHIFT_1__FLD LPDDR4__DENALI_PHY_1283__PHY_SW_GRP2_SHIFT_1 + +#define LPDDR4__DENALI_PHY_1283__PHY_SW_GRP3_SHIFT_1_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_1283__PHY_SW_GRP3_SHIFT_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_1283__PHY_SW_GRP3_SHIFT_1_WIDTH 5U +#define LPDDR4__PHY_SW_GRP3_SHIFT_1__REG DENALI_PHY_1283 +#define LPDDR4__PHY_SW_GRP3_SHIFT_1__FLD LPDDR4__DENALI_PHY_1283__PHY_SW_GRP3_SHIFT_1 + +#define LPDDR4__DENALI_PHY_1284_READ_MASK 0x011F07FFU +#define LPDDR4__DENALI_PHY_1284_WRITE_MASK 0x011F07FFU +#define LPDDR4__DENALI_PHY_1284__PHY_GRP_BYPASS_SLAVE_DELAY_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1284__PHY_GRP_BYPASS_SLAVE_DELAY_SHIFT 0U +#define LPDDR4__DENALI_PHY_1284__PHY_GRP_BYPASS_SLAVE_DELAY_WIDTH 11U +#define LPDDR4__PHY_GRP_BYPASS_SLAVE_DELAY__REG DENALI_PHY_1284 +#define LPDDR4__PHY_GRP_BYPASS_SLAVE_DELAY__FLD LPDDR4__DENALI_PHY_1284__PHY_GRP_BYPASS_SLAVE_DELAY + +#define LPDDR4__DENALI_PHY_1284__PHY_SW_GRP_BYPASS_SHIFT_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_1284__PHY_SW_GRP_BYPASS_SHIFT_SHIFT 16U +#define LPDDR4__DENALI_PHY_1284__PHY_SW_GRP_BYPASS_SHIFT_WIDTH 5U +#define LPDDR4__PHY_SW_GRP_BYPASS_SHIFT__REG DENALI_PHY_1284 +#define LPDDR4__PHY_SW_GRP_BYPASS_SHIFT__FLD LPDDR4__DENALI_PHY_1284__PHY_SW_GRP_BYPASS_SHIFT + +#define LPDDR4__DENALI_PHY_1284__PHY_GRP_BYPASS_OVERRIDE_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_1284__PHY_GRP_BYPASS_OVERRIDE_SHIFT 24U +#define LPDDR4__DENALI_PHY_1284__PHY_GRP_BYPASS_OVERRIDE_WIDTH 1U +#define LPDDR4__DENALI_PHY_1284__PHY_GRP_BYPASS_OVERRIDE_WOCLR 0U +#define LPDDR4__DENALI_PHY_1284__PHY_GRP_BYPASS_OVERRIDE_WOSET 0U +#define LPDDR4__PHY_GRP_BYPASS_OVERRIDE__REG DENALI_PHY_1284 +#define LPDDR4__PHY_GRP_BYPASS_OVERRIDE__FLD LPDDR4__DENALI_PHY_1284__PHY_GRP_BYPASS_OVERRIDE + +#define LPDDR4__DENALI_PHY_1285_READ_MASK 0x07FF0100U +#define LPDDR4__DENALI_PHY_1285_WRITE_MASK 0x07FF0100U +#define LPDDR4__DENALI_PHY_1285__SC_PHY_MANUAL_UPDATE_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_1285__SC_PHY_MANUAL_UPDATE_SHIFT 0U +#define LPDDR4__DENALI_PHY_1285__SC_PHY_MANUAL_UPDATE_WIDTH 1U +#define LPDDR4__DENALI_PHY_1285__SC_PHY_MANUAL_UPDATE_WOCLR 0U +#define LPDDR4__DENALI_PHY_1285__SC_PHY_MANUAL_UPDATE_WOSET 0U +#define LPDDR4__SC_PHY_MANUAL_UPDATE__REG DENALI_PHY_1285 +#define LPDDR4__SC_PHY_MANUAL_UPDATE__FLD LPDDR4__DENALI_PHY_1285__SC_PHY_MANUAL_UPDATE + +#define LPDDR4__DENALI_PHY_1285__PHY_MANUAL_UPDATE_PHYUPD_ENABLE_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_1285__PHY_MANUAL_UPDATE_PHYUPD_ENABLE_SHIFT 8U +#define LPDDR4__DENALI_PHY_1285__PHY_MANUAL_UPDATE_PHYUPD_ENABLE_WIDTH 1U +#define LPDDR4__DENALI_PHY_1285__PHY_MANUAL_UPDATE_PHYUPD_ENABLE_WOCLR 0U +#define LPDDR4__DENALI_PHY_1285__PHY_MANUAL_UPDATE_PHYUPD_ENABLE_WOSET 0U +#define LPDDR4__PHY_MANUAL_UPDATE_PHYUPD_ENABLE__REG DENALI_PHY_1285 +#define LPDDR4__PHY_MANUAL_UPDATE_PHYUPD_ENABLE__FLD LPDDR4__DENALI_PHY_1285__PHY_MANUAL_UPDATE_PHYUPD_ENABLE + +#define LPDDR4__DENALI_PHY_1285__PHY_CSLVL_START_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_1285__PHY_CSLVL_START_SHIFT 16U +#define LPDDR4__DENALI_PHY_1285__PHY_CSLVL_START_WIDTH 11U +#define LPDDR4__PHY_CSLVL_START__REG DENALI_PHY_1285 +#define LPDDR4__PHY_CSLVL_START__FLD LPDDR4__DENALI_PHY_1285__PHY_CSLVL_START + +#define LPDDR4__DENALI_PHY_1286_READ_MASK 0x000107FFU +#define LPDDR4__DENALI_PHY_1286_WRITE_MASK 0x000107FFU +#define LPDDR4__DENALI_PHY_1286__PHY_CSLVL_COARSE_DLY_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1286__PHY_CSLVL_COARSE_DLY_SHIFT 0U +#define LPDDR4__DENALI_PHY_1286__PHY_CSLVL_COARSE_DLY_WIDTH 11U +#define LPDDR4__PHY_CSLVL_COARSE_DLY__REG DENALI_PHY_1286 +#define LPDDR4__PHY_CSLVL_COARSE_DLY__FLD LPDDR4__DENALI_PHY_1286__PHY_CSLVL_COARSE_DLY + +#define LPDDR4__DENALI_PHY_1286__PHY_CSLVL_DEBUG_MODE_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_1286__PHY_CSLVL_DEBUG_MODE_SHIFT 16U +#define LPDDR4__DENALI_PHY_1286__PHY_CSLVL_DEBUG_MODE_WIDTH 1U +#define LPDDR4__DENALI_PHY_1286__PHY_CSLVL_DEBUG_MODE_WOCLR 0U +#define LPDDR4__DENALI_PHY_1286__PHY_CSLVL_DEBUG_MODE_WOSET 0U +#define LPDDR4__PHY_CSLVL_DEBUG_MODE__REG DENALI_PHY_1286 +#define LPDDR4__PHY_CSLVL_DEBUG_MODE__FLD LPDDR4__DENALI_PHY_1286__PHY_CSLVL_DEBUG_MODE + +#define LPDDR4__DENALI_PHY_1286__SC_PHY_CSLVL_DEBUG_CONT_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_1286__SC_PHY_CSLVL_DEBUG_CONT_SHIFT 24U +#define LPDDR4__DENALI_PHY_1286__SC_PHY_CSLVL_DEBUG_CONT_WIDTH 1U +#define LPDDR4__DENALI_PHY_1286__SC_PHY_CSLVL_DEBUG_CONT_WOCLR 0U +#define LPDDR4__DENALI_PHY_1286__SC_PHY_CSLVL_DEBUG_CONT_WOSET 0U +#define LPDDR4__SC_PHY_CSLVL_DEBUG_CONT__REG DENALI_PHY_1286 +#define LPDDR4__SC_PHY_CSLVL_DEBUG_CONT__FLD LPDDR4__DENALI_PHY_1286__SC_PHY_CSLVL_DEBUG_CONT + +#define LPDDR4__DENALI_PHY_1287__SC_PHY_CSLVL_ERROR_CLR_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_1287__SC_PHY_CSLVL_ERROR_CLR_SHIFT 0U +#define LPDDR4__DENALI_PHY_1287__SC_PHY_CSLVL_ERROR_CLR_WIDTH 1U +#define LPDDR4__DENALI_PHY_1287__SC_PHY_CSLVL_ERROR_CLR_WOCLR 0U +#define LPDDR4__DENALI_PHY_1287__SC_PHY_CSLVL_ERROR_CLR_WOSET 0U +#define LPDDR4__SC_PHY_CSLVL_ERROR_CLR__REG DENALI_PHY_1287 +#define LPDDR4__SC_PHY_CSLVL_ERROR_CLR__FLD LPDDR4__DENALI_PHY_1287__SC_PHY_CSLVL_ERROR_CLR + +#define LPDDR4__DENALI_PHY_1288_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1288_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1288__PHY_CSLVL_OBS0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1288__PHY_CSLVL_OBS0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1288__PHY_CSLVL_OBS0_WIDTH 32U +#define LPDDR4__PHY_CSLVL_OBS0__REG DENALI_PHY_1288 +#define LPDDR4__PHY_CSLVL_OBS0__FLD LPDDR4__DENALI_PHY_1288__PHY_CSLVL_OBS0 + +#define LPDDR4__DENALI_PHY_1289_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1289_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1289__PHY_CSLVL_OBS1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1289__PHY_CSLVL_OBS1_SHIFT 0U +#define LPDDR4__DENALI_PHY_1289__PHY_CSLVL_OBS1_WIDTH 32U +#define LPDDR4__PHY_CSLVL_OBS1__REG DENALI_PHY_1289 +#define LPDDR4__PHY_CSLVL_OBS1__FLD LPDDR4__DENALI_PHY_1289__PHY_CSLVL_OBS1 + +#define LPDDR4__DENALI_PHY_1290_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1290_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1290__PHY_CSLVL_OBS2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1290__PHY_CSLVL_OBS2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1290__PHY_CSLVL_OBS2_WIDTH 32U +#define LPDDR4__PHY_CSLVL_OBS2__REG DENALI_PHY_1290 +#define LPDDR4__PHY_CSLVL_OBS2__FLD LPDDR4__DENALI_PHY_1290__PHY_CSLVL_OBS2 + +#define LPDDR4__DENALI_PHY_1291_READ_MASK 0x0101FF01U +#define LPDDR4__DENALI_PHY_1291_WRITE_MASK 0x0101FF01U +#define LPDDR4__DENALI_PHY_1291__PHY_CSLVL_ENABLE_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_1291__PHY_CSLVL_ENABLE_SHIFT 0U +#define LPDDR4__DENALI_PHY_1291__PHY_CSLVL_ENABLE_WIDTH 1U +#define LPDDR4__DENALI_PHY_1291__PHY_CSLVL_ENABLE_WOCLR 0U +#define LPDDR4__DENALI_PHY_1291__PHY_CSLVL_ENABLE_WOSET 0U +#define LPDDR4__PHY_CSLVL_ENABLE__REG DENALI_PHY_1291 +#define LPDDR4__PHY_CSLVL_ENABLE__FLD LPDDR4__DENALI_PHY_1291__PHY_CSLVL_ENABLE + +#define LPDDR4__DENALI_PHY_1291__PHY_CSLVL_PERIODIC_START_OFFSET_MASK 0x0001FF00U +#define LPDDR4__DENALI_PHY_1291__PHY_CSLVL_PERIODIC_START_OFFSET_SHIFT 8U +#define LPDDR4__DENALI_PHY_1291__PHY_CSLVL_PERIODIC_START_OFFSET_WIDTH 9U +#define LPDDR4__PHY_CSLVL_PERIODIC_START_OFFSET__REG DENALI_PHY_1291 +#define LPDDR4__PHY_CSLVL_PERIODIC_START_OFFSET__FLD LPDDR4__DENALI_PHY_1291__PHY_CSLVL_PERIODIC_START_OFFSET + +#define LPDDR4__DENALI_PHY_1291__PHY_LP4_BOOT_DISABLE_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_1291__PHY_LP4_BOOT_DISABLE_SHIFT 24U +#define LPDDR4__DENALI_PHY_1291__PHY_LP4_BOOT_DISABLE_WIDTH 1U +#define LPDDR4__DENALI_PHY_1291__PHY_LP4_BOOT_DISABLE_WOCLR 0U +#define LPDDR4__DENALI_PHY_1291__PHY_LP4_BOOT_DISABLE_WOSET 0U +#define LPDDR4__PHY_LP4_BOOT_DISABLE__REG DENALI_PHY_1291 +#define LPDDR4__PHY_LP4_BOOT_DISABLE__FLD LPDDR4__DENALI_PHY_1291__PHY_LP4_BOOT_DISABLE + +#define LPDDR4__DENALI_PHY_1292_READ_MASK 0x0007FF0FU +#define LPDDR4__DENALI_PHY_1292_WRITE_MASK 0x0007FF0FU +#define LPDDR4__DENALI_PHY_1292__PHY_CSLVL_CS_MAP_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_1292__PHY_CSLVL_CS_MAP_SHIFT 0U +#define LPDDR4__DENALI_PHY_1292__PHY_CSLVL_CS_MAP_WIDTH 4U +#define LPDDR4__PHY_CSLVL_CS_MAP__REG DENALI_PHY_1292 +#define LPDDR4__PHY_CSLVL_CS_MAP__FLD LPDDR4__DENALI_PHY_1292__PHY_CSLVL_CS_MAP + +#define LPDDR4__DENALI_PHY_1292__PHY_CSLVL_QTR_MASK 0x0007FF00U +#define LPDDR4__DENALI_PHY_1292__PHY_CSLVL_QTR_SHIFT 8U +#define LPDDR4__DENALI_PHY_1292__PHY_CSLVL_QTR_WIDTH 11U +#define LPDDR4__PHY_CSLVL_QTR__REG DENALI_PHY_1292 +#define LPDDR4__PHY_CSLVL_QTR__FLD LPDDR4__DENALI_PHY_1292__PHY_CSLVL_QTR + +#define LPDDR4__DENALI_PHY_1293_READ_MASK 0xFF0F07FFU +#define LPDDR4__DENALI_PHY_1293_WRITE_MASK 0xFF0F07FFU +#define LPDDR4__DENALI_PHY_1293__PHY_CSLVL_COARSE_CHK_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1293__PHY_CSLVL_COARSE_CHK_SHIFT 0U +#define LPDDR4__DENALI_PHY_1293__PHY_CSLVL_COARSE_CHK_WIDTH 11U +#define LPDDR4__PHY_CSLVL_COARSE_CHK__REG DENALI_PHY_1293 +#define LPDDR4__PHY_CSLVL_COARSE_CHK__FLD LPDDR4__DENALI_PHY_1293__PHY_CSLVL_COARSE_CHK + +#define LPDDR4__DENALI_PHY_1293__PHY_CSLVL_COARSE_CAPTURE_CNT_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_1293__PHY_CSLVL_COARSE_CAPTURE_CNT_SHIFT 16U +#define LPDDR4__DENALI_PHY_1293__PHY_CSLVL_COARSE_CAPTURE_CNT_WIDTH 4U +#define LPDDR4__PHY_CSLVL_COARSE_CAPTURE_CNT__REG DENALI_PHY_1293 +#define LPDDR4__PHY_CSLVL_COARSE_CAPTURE_CNT__FLD LPDDR4__DENALI_PHY_1293__PHY_CSLVL_COARSE_CAPTURE_CNT + +#define LPDDR4__DENALI_PHY_1293__PHY_CALVL_CS_MAP_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_1293__PHY_CALVL_CS_MAP_SHIFT 24U +#define LPDDR4__DENALI_PHY_1293__PHY_CALVL_CS_MAP_WIDTH 8U +#define LPDDR4__PHY_CALVL_CS_MAP__REG DENALI_PHY_1293 +#define LPDDR4__PHY_CALVL_CS_MAP__FLD LPDDR4__DENALI_PHY_1293__PHY_CALVL_CS_MAP + +#define LPDDR4__DENALI_PHY_1294_READ_MASK 0x01030007U +#define LPDDR4__DENALI_PHY_1294_WRITE_MASK 0x01030007U +#define LPDDR4__DENALI_PHY_1294__PHY_ADRCTL_SLAVE_LOOP_CNT_UPDATE_MASK 0x00000007U +#define LPDDR4__DENALI_PHY_1294__PHY_ADRCTL_SLAVE_LOOP_CNT_UPDATE_SHIFT 0U +#define LPDDR4__DENALI_PHY_1294__PHY_ADRCTL_SLAVE_LOOP_CNT_UPDATE_WIDTH 3U +#define LPDDR4__PHY_ADRCTL_SLAVE_LOOP_CNT_UPDATE__REG DENALI_PHY_1294 +#define LPDDR4__PHY_ADRCTL_SLAVE_LOOP_CNT_UPDATE__FLD LPDDR4__DENALI_PHY_1294__PHY_ADRCTL_SLAVE_LOOP_CNT_UPDATE + +#define LPDDR4__DENALI_PHY_1294__PHY_ADRCTL_SNAP_OBS_REGS_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_1294__PHY_ADRCTL_SNAP_OBS_REGS_SHIFT 8U +#define LPDDR4__DENALI_PHY_1294__PHY_ADRCTL_SNAP_OBS_REGS_WIDTH 1U +#define LPDDR4__DENALI_PHY_1294__PHY_ADRCTL_SNAP_OBS_REGS_WOCLR 0U +#define LPDDR4__DENALI_PHY_1294__PHY_ADRCTL_SNAP_OBS_REGS_WOSET 0U +#define LPDDR4__PHY_ADRCTL_SNAP_OBS_REGS__REG DENALI_PHY_1294 +#define LPDDR4__PHY_ADRCTL_SNAP_OBS_REGS__FLD LPDDR4__DENALI_PHY_1294__PHY_ADRCTL_SNAP_OBS_REGS + +#define LPDDR4__DENALI_PHY_1294__PHY_DFI_PHYUPD_TYPE_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_1294__PHY_DFI_PHYUPD_TYPE_SHIFT 16U +#define LPDDR4__DENALI_PHY_1294__PHY_DFI_PHYUPD_TYPE_WIDTH 2U +#define LPDDR4__PHY_DFI_PHYUPD_TYPE__REG DENALI_PHY_1294 +#define LPDDR4__PHY_DFI_PHYUPD_TYPE__FLD LPDDR4__DENALI_PHY_1294__PHY_DFI_PHYUPD_TYPE + +#define LPDDR4__DENALI_PHY_1294__PHY_ADRCTL_LPDDR_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_1294__PHY_ADRCTL_LPDDR_SHIFT 24U +#define LPDDR4__DENALI_PHY_1294__PHY_ADRCTL_LPDDR_WIDTH 1U +#define LPDDR4__DENALI_PHY_1294__PHY_ADRCTL_LPDDR_WOCLR 0U +#define LPDDR4__DENALI_PHY_1294__PHY_ADRCTL_LPDDR_WOSET 0U +#define LPDDR4__PHY_ADRCTL_LPDDR__REG DENALI_PHY_1294 +#define LPDDR4__PHY_ADRCTL_LPDDR__FLD LPDDR4__DENALI_PHY_1294__PHY_ADRCTL_LPDDR + +#define LPDDR4__DENALI_PHY_1295_READ_MASK 0xFFFF0101U +#define LPDDR4__DENALI_PHY_1295_WRITE_MASK 0xFFFF0101U +#define LPDDR4__DENALI_PHY_1295__PHY_LP4_ACTIVE_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_1295__PHY_LP4_ACTIVE_SHIFT 0U +#define LPDDR4__DENALI_PHY_1295__PHY_LP4_ACTIVE_WIDTH 1U +#define LPDDR4__DENALI_PHY_1295__PHY_LP4_ACTIVE_WOCLR 0U +#define LPDDR4__DENALI_PHY_1295__PHY_LP4_ACTIVE_WOSET 0U +#define LPDDR4__PHY_LP4_ACTIVE__REG DENALI_PHY_1295 +#define LPDDR4__PHY_LP4_ACTIVE__FLD LPDDR4__DENALI_PHY_1295__PHY_LP4_ACTIVE + +#define LPDDR4__DENALI_PHY_1295__PHY_LPDDR3_CS_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_1295__PHY_LPDDR3_CS_SHIFT 8U +#define LPDDR4__DENALI_PHY_1295__PHY_LPDDR3_CS_WIDTH 1U +#define LPDDR4__DENALI_PHY_1295__PHY_LPDDR3_CS_WOCLR 0U +#define LPDDR4__DENALI_PHY_1295__PHY_LPDDR3_CS_WOSET 0U +#define LPDDR4__PHY_LPDDR3_CS__REG DENALI_PHY_1295 +#define LPDDR4__PHY_LPDDR3_CS__FLD LPDDR4__DENALI_PHY_1295__PHY_LPDDR3_CS + +#define LPDDR4__DENALI_PHY_1295__PHY_CLK_DC_CAL_SAMPLE_WAIT_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_1295__PHY_CLK_DC_CAL_SAMPLE_WAIT_SHIFT 16U +#define LPDDR4__DENALI_PHY_1295__PHY_CLK_DC_CAL_SAMPLE_WAIT_WIDTH 8U +#define LPDDR4__PHY_CLK_DC_CAL_SAMPLE_WAIT__REG DENALI_PHY_1295 +#define LPDDR4__PHY_CLK_DC_CAL_SAMPLE_WAIT__FLD LPDDR4__DENALI_PHY_1295__PHY_CLK_DC_CAL_SAMPLE_WAIT + +#define LPDDR4__DENALI_PHY_1295__PHY_CLK_DC_CAL_TIMEOUT_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_1295__PHY_CLK_DC_CAL_TIMEOUT_SHIFT 24U +#define LPDDR4__DENALI_PHY_1295__PHY_CLK_DC_CAL_TIMEOUT_WIDTH 8U +#define LPDDR4__PHY_CLK_DC_CAL_TIMEOUT__REG DENALI_PHY_1295 +#define LPDDR4__PHY_CLK_DC_CAL_TIMEOUT__FLD LPDDR4__DENALI_PHY_1295__PHY_CLK_DC_CAL_TIMEOUT + +#define LPDDR4__DENALI_PHY_1296_READ_MASK 0xFF3F0103U +#define LPDDR4__DENALI_PHY_1296_WRITE_MASK 0xFF3F0103U +#define LPDDR4__DENALI_PHY_1296__PHY_CLK_DC_WEIGHT_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_1296__PHY_CLK_DC_WEIGHT_SHIFT 0U +#define LPDDR4__DENALI_PHY_1296__PHY_CLK_DC_WEIGHT_WIDTH 2U +#define LPDDR4__PHY_CLK_DC_WEIGHT__REG DENALI_PHY_1296 +#define LPDDR4__PHY_CLK_DC_WEIGHT__FLD LPDDR4__DENALI_PHY_1296__PHY_CLK_DC_WEIGHT + +#define LPDDR4__DENALI_PHY_1296__PHY_CLK_DC_FREQ_CHG_ADJ_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_1296__PHY_CLK_DC_FREQ_CHG_ADJ_SHIFT 8U +#define LPDDR4__DENALI_PHY_1296__PHY_CLK_DC_FREQ_CHG_ADJ_WIDTH 1U +#define LPDDR4__DENALI_PHY_1296__PHY_CLK_DC_FREQ_CHG_ADJ_WOCLR 0U +#define LPDDR4__DENALI_PHY_1296__PHY_CLK_DC_FREQ_CHG_ADJ_WOSET 0U +#define LPDDR4__PHY_CLK_DC_FREQ_CHG_ADJ__REG DENALI_PHY_1296 +#define LPDDR4__PHY_CLK_DC_FREQ_CHG_ADJ__FLD LPDDR4__DENALI_PHY_1296__PHY_CLK_DC_FREQ_CHG_ADJ + +#define LPDDR4__DENALI_PHY_1296__PHY_CLK_DC_ADJUST_START_MASK 0x003F0000U +#define LPDDR4__DENALI_PHY_1296__PHY_CLK_DC_ADJUST_START_SHIFT 16U +#define LPDDR4__DENALI_PHY_1296__PHY_CLK_DC_ADJUST_START_WIDTH 6U +#define LPDDR4__PHY_CLK_DC_ADJUST_START__REG DENALI_PHY_1296 +#define LPDDR4__PHY_CLK_DC_ADJUST_START__FLD LPDDR4__DENALI_PHY_1296__PHY_CLK_DC_ADJUST_START + +#define LPDDR4__DENALI_PHY_1296__PHY_CLK_DC_ADJUST_SAMPLE_CNT_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_1296__PHY_CLK_DC_ADJUST_SAMPLE_CNT_SHIFT 24U +#define LPDDR4__DENALI_PHY_1296__PHY_CLK_DC_ADJUST_SAMPLE_CNT_WIDTH 8U +#define LPDDR4__PHY_CLK_DC_ADJUST_SAMPLE_CNT__REG DENALI_PHY_1296 +#define LPDDR4__PHY_CLK_DC_ADJUST_SAMPLE_CNT__FLD LPDDR4__DENALI_PHY_1296__PHY_CLK_DC_ADJUST_SAMPLE_CNT + +#define LPDDR4__DENALI_PHY_1297_READ_MASK 0x010101FFU +#define LPDDR4__DENALI_PHY_1297_WRITE_MASK 0x010101FFU +#define LPDDR4__DENALI_PHY_1297__PHY_CLK_DC_ADJUST_THRSHLD_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_1297__PHY_CLK_DC_ADJUST_THRSHLD_SHIFT 0U +#define LPDDR4__DENALI_PHY_1297__PHY_CLK_DC_ADJUST_THRSHLD_WIDTH 8U +#define LPDDR4__PHY_CLK_DC_ADJUST_THRSHLD__REG DENALI_PHY_1297 +#define LPDDR4__PHY_CLK_DC_ADJUST_THRSHLD__FLD LPDDR4__DENALI_PHY_1297__PHY_CLK_DC_ADJUST_THRSHLD + +#define LPDDR4__DENALI_PHY_1297__PHY_CLK_DC_ADJUST_DIRECT_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_1297__PHY_CLK_DC_ADJUST_DIRECT_SHIFT 8U +#define LPDDR4__DENALI_PHY_1297__PHY_CLK_DC_ADJUST_DIRECT_WIDTH 1U +#define LPDDR4__DENALI_PHY_1297__PHY_CLK_DC_ADJUST_DIRECT_WOCLR 0U +#define LPDDR4__DENALI_PHY_1297__PHY_CLK_DC_ADJUST_DIRECT_WOSET 0U +#define LPDDR4__PHY_CLK_DC_ADJUST_DIRECT__REG DENALI_PHY_1297 +#define LPDDR4__PHY_CLK_DC_ADJUST_DIRECT__FLD LPDDR4__DENALI_PHY_1297__PHY_CLK_DC_ADJUST_DIRECT + +#define LPDDR4__DENALI_PHY_1297__PHY_CLK_DC_CAL_POLARITY_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_1297__PHY_CLK_DC_CAL_POLARITY_SHIFT 16U +#define LPDDR4__DENALI_PHY_1297__PHY_CLK_DC_CAL_POLARITY_WIDTH 1U +#define LPDDR4__DENALI_PHY_1297__PHY_CLK_DC_CAL_POLARITY_WOCLR 0U +#define LPDDR4__DENALI_PHY_1297__PHY_CLK_DC_CAL_POLARITY_WOSET 0U +#define LPDDR4__PHY_CLK_DC_CAL_POLARITY__REG DENALI_PHY_1297 +#define LPDDR4__PHY_CLK_DC_CAL_POLARITY__FLD LPDDR4__DENALI_PHY_1297__PHY_CLK_DC_CAL_POLARITY + +#define LPDDR4__DENALI_PHY_1297__PHY_CLK_DC_CAL_START_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_1297__PHY_CLK_DC_CAL_START_SHIFT 24U +#define LPDDR4__DENALI_PHY_1297__PHY_CLK_DC_CAL_START_WIDTH 1U +#define LPDDR4__DENALI_PHY_1297__PHY_CLK_DC_CAL_START_WOCLR 0U +#define LPDDR4__DENALI_PHY_1297__PHY_CLK_DC_CAL_START_WOSET 0U +#define LPDDR4__PHY_CLK_DC_CAL_START__REG DENALI_PHY_1297 +#define LPDDR4__PHY_CLK_DC_CAL_START__FLD LPDDR4__DENALI_PHY_1297__PHY_CLK_DC_CAL_START + +#define LPDDR4__DENALI_PHY_1298_READ_MASK 0x0F0F0100U +#define LPDDR4__DENALI_PHY_1298_WRITE_MASK 0x0F0F0100U +#define LPDDR4__DENALI_PHY_1298__SC_PHY_UPDATE_CLK_CAL_VALUES_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_1298__SC_PHY_UPDATE_CLK_CAL_VALUES_SHIFT 0U +#define LPDDR4__DENALI_PHY_1298__SC_PHY_UPDATE_CLK_CAL_VALUES_WIDTH 1U +#define LPDDR4__DENALI_PHY_1298__SC_PHY_UPDATE_CLK_CAL_VALUES_WOCLR 0U +#define LPDDR4__DENALI_PHY_1298__SC_PHY_UPDATE_CLK_CAL_VALUES_WOSET 0U +#define LPDDR4__SC_PHY_UPDATE_CLK_CAL_VALUES__REG DENALI_PHY_1298 +#define LPDDR4__SC_PHY_UPDATE_CLK_CAL_VALUES__FLD LPDDR4__DENALI_PHY_1298__SC_PHY_UPDATE_CLK_CAL_VALUES + +#define LPDDR4__DENALI_PHY_1298__PHY_CONTINUOUS_CLK_CAL_UPDATE_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_1298__PHY_CONTINUOUS_CLK_CAL_UPDATE_SHIFT 8U +#define LPDDR4__DENALI_PHY_1298__PHY_CONTINUOUS_CLK_CAL_UPDATE_WIDTH 1U +#define LPDDR4__DENALI_PHY_1298__PHY_CONTINUOUS_CLK_CAL_UPDATE_WOCLR 0U +#define LPDDR4__DENALI_PHY_1298__PHY_CONTINUOUS_CLK_CAL_UPDATE_WOSET 0U +#define LPDDR4__PHY_CONTINUOUS_CLK_CAL_UPDATE__REG DENALI_PHY_1298 +#define LPDDR4__PHY_CONTINUOUS_CLK_CAL_UPDATE__FLD LPDDR4__DENALI_PHY_1298__PHY_CONTINUOUS_CLK_CAL_UPDATE + +#define LPDDR4__DENALI_PHY_1298__PHY_SW_TXIO_CTRL_0_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_1298__PHY_SW_TXIO_CTRL_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1298__PHY_SW_TXIO_CTRL_0_WIDTH 4U +#define LPDDR4__PHY_SW_TXIO_CTRL_0__REG DENALI_PHY_1298 +#define LPDDR4__PHY_SW_TXIO_CTRL_0__FLD LPDDR4__DENALI_PHY_1298__PHY_SW_TXIO_CTRL_0 + +#define LPDDR4__DENALI_PHY_1298__PHY_SW_TXIO_CTRL_1_MASK 0x0F000000U +#define LPDDR4__DENALI_PHY_1298__PHY_SW_TXIO_CTRL_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_1298__PHY_SW_TXIO_CTRL_1_WIDTH 4U +#define LPDDR4__PHY_SW_TXIO_CTRL_1__REG DENALI_PHY_1298 +#define LPDDR4__PHY_SW_TXIO_CTRL_1__FLD LPDDR4__DENALI_PHY_1298__PHY_SW_TXIO_CTRL_1 + +#define LPDDR4__DENALI_PHY_1299_READ_MASK 0x010F0F01U +#define LPDDR4__DENALI_PHY_1299_WRITE_MASK 0x010F0F01U +#define LPDDR4__DENALI_PHY_1299__PHY_MEMCLK_SW_TXIO_CTRL_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_1299__PHY_MEMCLK_SW_TXIO_CTRL_SHIFT 0U +#define LPDDR4__DENALI_PHY_1299__PHY_MEMCLK_SW_TXIO_CTRL_WIDTH 1U +#define LPDDR4__DENALI_PHY_1299__PHY_MEMCLK_SW_TXIO_CTRL_WOCLR 0U +#define LPDDR4__DENALI_PHY_1299__PHY_MEMCLK_SW_TXIO_CTRL_WOSET 0U +#define LPDDR4__PHY_MEMCLK_SW_TXIO_CTRL__REG DENALI_PHY_1299 +#define LPDDR4__PHY_MEMCLK_SW_TXIO_CTRL__FLD LPDDR4__DENALI_PHY_1299__PHY_MEMCLK_SW_TXIO_CTRL + +#define LPDDR4__DENALI_PHY_1299__PHY_ADRCTL_SW_TXPWR_CTRL_0_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_1299__PHY_ADRCTL_SW_TXPWR_CTRL_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_1299__PHY_ADRCTL_SW_TXPWR_CTRL_0_WIDTH 4U +#define LPDDR4__PHY_ADRCTL_SW_TXPWR_CTRL_0__REG DENALI_PHY_1299 +#define LPDDR4__PHY_ADRCTL_SW_TXPWR_CTRL_0__FLD LPDDR4__DENALI_PHY_1299__PHY_ADRCTL_SW_TXPWR_CTRL_0 + +#define LPDDR4__DENALI_PHY_1299__PHY_ADRCTL_SW_TXPWR_CTRL_1_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_1299__PHY_ADRCTL_SW_TXPWR_CTRL_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_1299__PHY_ADRCTL_SW_TXPWR_CTRL_1_WIDTH 4U +#define LPDDR4__PHY_ADRCTL_SW_TXPWR_CTRL_1__REG DENALI_PHY_1299 +#define LPDDR4__PHY_ADRCTL_SW_TXPWR_CTRL_1__FLD LPDDR4__DENALI_PHY_1299__PHY_ADRCTL_SW_TXPWR_CTRL_1 + +#define LPDDR4__DENALI_PHY_1299__PHY_MEMCLK_SW_TXPWR_CTRL_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_1299__PHY_MEMCLK_SW_TXPWR_CTRL_SHIFT 24U +#define LPDDR4__DENALI_PHY_1299__PHY_MEMCLK_SW_TXPWR_CTRL_WIDTH 1U +#define LPDDR4__DENALI_PHY_1299__PHY_MEMCLK_SW_TXPWR_CTRL_WOCLR 0U +#define LPDDR4__DENALI_PHY_1299__PHY_MEMCLK_SW_TXPWR_CTRL_WOSET 0U +#define LPDDR4__PHY_MEMCLK_SW_TXPWR_CTRL__REG DENALI_PHY_1299 +#define LPDDR4__PHY_MEMCLK_SW_TXPWR_CTRL__FLD LPDDR4__DENALI_PHY_1299__PHY_MEMCLK_SW_TXPWR_CTRL + +#define LPDDR4__DENALI_PHY_1300_READ_MASK 0xFFFF0101U +#define LPDDR4__DENALI_PHY_1300_WRITE_MASK 0xFFFF0101U +#define LPDDR4__DENALI_PHY_1300__PHY_TOP_STATIC_TOG_DISABLE_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_1300__PHY_TOP_STATIC_TOG_DISABLE_SHIFT 0U +#define LPDDR4__DENALI_PHY_1300__PHY_TOP_STATIC_TOG_DISABLE_WIDTH 1U +#define LPDDR4__DENALI_PHY_1300__PHY_TOP_STATIC_TOG_DISABLE_WOCLR 0U +#define LPDDR4__DENALI_PHY_1300__PHY_TOP_STATIC_TOG_DISABLE_WOSET 0U +#define LPDDR4__PHY_TOP_STATIC_TOG_DISABLE__REG DENALI_PHY_1300 +#define LPDDR4__PHY_TOP_STATIC_TOG_DISABLE__FLD LPDDR4__DENALI_PHY_1300__PHY_TOP_STATIC_TOG_DISABLE + +#define LPDDR4__DENALI_PHY_1300__PHY_BYTE_DISABLE_STATIC_TOG_DISABLE_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_1300__PHY_BYTE_DISABLE_STATIC_TOG_DISABLE_SHIFT 8U +#define LPDDR4__DENALI_PHY_1300__PHY_BYTE_DISABLE_STATIC_TOG_DISABLE_WIDTH 1U +#define LPDDR4__DENALI_PHY_1300__PHY_BYTE_DISABLE_STATIC_TOG_DISABLE_WOCLR 0U +#define LPDDR4__DENALI_PHY_1300__PHY_BYTE_DISABLE_STATIC_TOG_DISABLE_WOSET 0U +#define LPDDR4__PHY_BYTE_DISABLE_STATIC_TOG_DISABLE__REG DENALI_PHY_1300 +#define LPDDR4__PHY_BYTE_DISABLE_STATIC_TOG_DISABLE__FLD LPDDR4__DENALI_PHY_1300__PHY_BYTE_DISABLE_STATIC_TOG_DISABLE + +#define LPDDR4__DENALI_PHY_1300__PHY_STATIC_TOG_CONTROL_MASK 0xFFFF0000U +#define LPDDR4__DENALI_PHY_1300__PHY_STATIC_TOG_CONTROL_SHIFT 16U +#define LPDDR4__DENALI_PHY_1300__PHY_STATIC_TOG_CONTROL_WIDTH 16U +#define LPDDR4__PHY_STATIC_TOG_CONTROL__REG DENALI_PHY_1300 +#define LPDDR4__PHY_STATIC_TOG_CONTROL__FLD LPDDR4__DENALI_PHY_1300__PHY_STATIC_TOG_CONTROL + +#define LPDDR4__DENALI_PHY_1301_READ_MASK 0x0001010FU +#define LPDDR4__DENALI_PHY_1301_WRITE_MASK 0x0001010FU +#define LPDDR4__DENALI_PHY_1301__PHY_ADRCTL_STATIC_TOG_DISABLE_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_1301__PHY_ADRCTL_STATIC_TOG_DISABLE_SHIFT 0U +#define LPDDR4__DENALI_PHY_1301__PHY_ADRCTL_STATIC_TOG_DISABLE_WIDTH 4U +#define LPDDR4__PHY_ADRCTL_STATIC_TOG_DISABLE__REG DENALI_PHY_1301 +#define LPDDR4__PHY_ADRCTL_STATIC_TOG_DISABLE__FLD LPDDR4__DENALI_PHY_1301__PHY_ADRCTL_STATIC_TOG_DISABLE + +#define LPDDR4__DENALI_PHY_1301__PHY_MEMCLK_STATIC_TOG_DISABLE_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_1301__PHY_MEMCLK_STATIC_TOG_DISABLE_SHIFT 8U +#define LPDDR4__DENALI_PHY_1301__PHY_MEMCLK_STATIC_TOG_DISABLE_WIDTH 1U +#define LPDDR4__DENALI_PHY_1301__PHY_MEMCLK_STATIC_TOG_DISABLE_WOCLR 0U +#define LPDDR4__DENALI_PHY_1301__PHY_MEMCLK_STATIC_TOG_DISABLE_WOSET 0U +#define LPDDR4__PHY_MEMCLK_STATIC_TOG_DISABLE__REG DENALI_PHY_1301 +#define LPDDR4__PHY_MEMCLK_STATIC_TOG_DISABLE__FLD LPDDR4__DENALI_PHY_1301__PHY_MEMCLK_STATIC_TOG_DISABLE + +#define LPDDR4__DENALI_PHY_1301__PHY_LP4_BOOT_PLL_BYPASS_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_1301__PHY_LP4_BOOT_PLL_BYPASS_SHIFT 16U +#define LPDDR4__DENALI_PHY_1301__PHY_LP4_BOOT_PLL_BYPASS_WIDTH 1U +#define LPDDR4__DENALI_PHY_1301__PHY_LP4_BOOT_PLL_BYPASS_WOCLR 0U +#define LPDDR4__DENALI_PHY_1301__PHY_LP4_BOOT_PLL_BYPASS_WOSET 0U +#define LPDDR4__PHY_LP4_BOOT_PLL_BYPASS__REG DENALI_PHY_1301 +#define LPDDR4__PHY_LP4_BOOT_PLL_BYPASS__FLD LPDDR4__DENALI_PHY_1301__PHY_LP4_BOOT_PLL_BYPASS + +#define LPDDR4__DENALI_PHY_1302_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1302_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1302__PHY_CLK_SWITCH_OBS_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1302__PHY_CLK_SWITCH_OBS_SHIFT 0U +#define LPDDR4__DENALI_PHY_1302__PHY_CLK_SWITCH_OBS_WIDTH 32U +#define LPDDR4__PHY_CLK_SWITCH_OBS__REG DENALI_PHY_1302 +#define LPDDR4__PHY_CLK_SWITCH_OBS__FLD LPDDR4__DENALI_PHY_1302__PHY_CLK_SWITCH_OBS + +#define LPDDR4__DENALI_PHY_1303_READ_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_1303_WRITE_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_1303__PHY_PLL_WAIT_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_1303__PHY_PLL_WAIT_SHIFT 0U +#define LPDDR4__DENALI_PHY_1303__PHY_PLL_WAIT_WIDTH 16U +#define LPDDR4__PHY_PLL_WAIT__REG DENALI_PHY_1303 +#define LPDDR4__PHY_PLL_WAIT__FLD LPDDR4__DENALI_PHY_1303__PHY_PLL_WAIT + +#define LPDDR4__DENALI_PHY_1304_READ_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_1304_WRITE_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_1304__PHY_SW_PLL_BYPASS_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_1304__PHY_SW_PLL_BYPASS_SHIFT 0U +#define LPDDR4__DENALI_PHY_1304__PHY_SW_PLL_BYPASS_WIDTH 1U +#define LPDDR4__DENALI_PHY_1304__PHY_SW_PLL_BYPASS_WOCLR 0U +#define LPDDR4__DENALI_PHY_1304__PHY_SW_PLL_BYPASS_WOSET 0U +#define LPDDR4__PHY_SW_PLL_BYPASS__REG DENALI_PHY_1304 +#define LPDDR4__PHY_SW_PLL_BYPASS__FLD LPDDR4__DENALI_PHY_1304__PHY_SW_PLL_BYPASS + +#define LPDDR4__DENALI_PHY_1305_READ_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_PHY_1305_WRITE_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_PHY_1305__PHY_SET_DFI_INPUT_0_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_1305__PHY_SET_DFI_INPUT_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1305__PHY_SET_DFI_INPUT_0_WIDTH 4U +#define LPDDR4__PHY_SET_DFI_INPUT_0__REG DENALI_PHY_1305 +#define LPDDR4__PHY_SET_DFI_INPUT_0__FLD LPDDR4__DENALI_PHY_1305__PHY_SET_DFI_INPUT_0 + +#define LPDDR4__DENALI_PHY_1305__PHY_SET_DFI_INPUT_1_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_1305__PHY_SET_DFI_INPUT_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_1305__PHY_SET_DFI_INPUT_1_WIDTH 4U +#define LPDDR4__PHY_SET_DFI_INPUT_1__REG DENALI_PHY_1305 +#define LPDDR4__PHY_SET_DFI_INPUT_1__FLD LPDDR4__DENALI_PHY_1305__PHY_SET_DFI_INPUT_1 + +#define LPDDR4__DENALI_PHY_1305__PHY_CS_ACS_ALLOCATION_BIT0_0_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_1305__PHY_CS_ACS_ALLOCATION_BIT0_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1305__PHY_CS_ACS_ALLOCATION_BIT0_0_WIDTH 4U +#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT0_0__REG DENALI_PHY_1305 +#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT0_0__FLD LPDDR4__DENALI_PHY_1305__PHY_CS_ACS_ALLOCATION_BIT0_0 + +#define LPDDR4__DENALI_PHY_1305__PHY_CS_ACS_ALLOCATION_BIT1_0_MASK 0x0F000000U +#define LPDDR4__DENALI_PHY_1305__PHY_CS_ACS_ALLOCATION_BIT1_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_1305__PHY_CS_ACS_ALLOCATION_BIT1_0_WIDTH 4U +#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT1_0__REG DENALI_PHY_1305 +#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT1_0__FLD LPDDR4__DENALI_PHY_1305__PHY_CS_ACS_ALLOCATION_BIT1_0 + +#define LPDDR4__DENALI_PHY_1306_READ_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_PHY_1306_WRITE_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_PHY_1306__PHY_CS_ACS_ALLOCATION_BIT2_0_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_1306__PHY_CS_ACS_ALLOCATION_BIT2_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1306__PHY_CS_ACS_ALLOCATION_BIT2_0_WIDTH 4U +#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT2_0__REG DENALI_PHY_1306 +#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT2_0__FLD LPDDR4__DENALI_PHY_1306__PHY_CS_ACS_ALLOCATION_BIT2_0 + +#define LPDDR4__DENALI_PHY_1306__PHY_CS_ACS_ALLOCATION_BIT3_0_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_1306__PHY_CS_ACS_ALLOCATION_BIT3_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_1306__PHY_CS_ACS_ALLOCATION_BIT3_0_WIDTH 4U +#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT3_0__REG DENALI_PHY_1306 +#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT3_0__FLD LPDDR4__DENALI_PHY_1306__PHY_CS_ACS_ALLOCATION_BIT3_0 + +#define LPDDR4__DENALI_PHY_1306__PHY_CS_ACS_ALLOCATION_BIT0_1_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_1306__PHY_CS_ACS_ALLOCATION_BIT0_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_1306__PHY_CS_ACS_ALLOCATION_BIT0_1_WIDTH 4U +#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT0_1__REG DENALI_PHY_1306 +#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT0_1__FLD LPDDR4__DENALI_PHY_1306__PHY_CS_ACS_ALLOCATION_BIT0_1 + +#define LPDDR4__DENALI_PHY_1306__PHY_CS_ACS_ALLOCATION_BIT1_1_MASK 0x0F000000U +#define LPDDR4__DENALI_PHY_1306__PHY_CS_ACS_ALLOCATION_BIT1_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_1306__PHY_CS_ACS_ALLOCATION_BIT1_1_WIDTH 4U +#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT1_1__REG DENALI_PHY_1306 +#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT1_1__FLD LPDDR4__DENALI_PHY_1306__PHY_CS_ACS_ALLOCATION_BIT1_1 + +#define LPDDR4__DENALI_PHY_1307_READ_MASK 0x01FF0F0FU +#define LPDDR4__DENALI_PHY_1307_WRITE_MASK 0x01FF0F0FU +#define LPDDR4__DENALI_PHY_1307__PHY_CS_ACS_ALLOCATION_BIT2_1_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_1307__PHY_CS_ACS_ALLOCATION_BIT2_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_1307__PHY_CS_ACS_ALLOCATION_BIT2_1_WIDTH 4U +#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT2_1__REG DENALI_PHY_1307 +#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT2_1__FLD LPDDR4__DENALI_PHY_1307__PHY_CS_ACS_ALLOCATION_BIT2_1 + +#define LPDDR4__DENALI_PHY_1307__PHY_CS_ACS_ALLOCATION_BIT3_1_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_1307__PHY_CS_ACS_ALLOCATION_BIT3_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_1307__PHY_CS_ACS_ALLOCATION_BIT3_1_WIDTH 4U +#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT3_1__REG DENALI_PHY_1307 +#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT3_1__FLD LPDDR4__DENALI_PHY_1307__PHY_CS_ACS_ALLOCATION_BIT3_1 + +#define LPDDR4__DENALI_PHY_1307__PHY_CLK_DC_ADJUST_0_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_1307__PHY_CLK_DC_ADJUST_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1307__PHY_CLK_DC_ADJUST_0_WIDTH 8U +#define LPDDR4__PHY_CLK_DC_ADJUST_0__REG DENALI_PHY_1307 +#define LPDDR4__PHY_CLK_DC_ADJUST_0__FLD LPDDR4__DENALI_PHY_1307__PHY_CLK_DC_ADJUST_0 + +#define LPDDR4__DENALI_PHY_1307__PHY_CLK_DC_INIT_DISABLE_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_1307__PHY_CLK_DC_INIT_DISABLE_SHIFT 24U +#define LPDDR4__DENALI_PHY_1307__PHY_CLK_DC_INIT_DISABLE_WIDTH 1U +#define LPDDR4__DENALI_PHY_1307__PHY_CLK_DC_INIT_DISABLE_WOCLR 0U +#define LPDDR4__DENALI_PHY_1307__PHY_CLK_DC_INIT_DISABLE_WOSET 0U +#define LPDDR4__PHY_CLK_DC_INIT_DISABLE__REG DENALI_PHY_1307 +#define LPDDR4__PHY_CLK_DC_INIT_DISABLE__FLD LPDDR4__DENALI_PHY_1307__PHY_CLK_DC_INIT_DISABLE + +#define LPDDR4__DENALI_PHY_1308_READ_MASK 0x001FFFFFU +#define LPDDR4__DENALI_PHY_1308_WRITE_MASK 0x001FFFFFU +#define LPDDR4__DENALI_PHY_1308__PHY_CLK_DC_DM_THRSHLD_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_1308__PHY_CLK_DC_DM_THRSHLD_SHIFT 0U +#define LPDDR4__DENALI_PHY_1308__PHY_CLK_DC_DM_THRSHLD_WIDTH 8U +#define LPDDR4__PHY_CLK_DC_DM_THRSHLD__REG DENALI_PHY_1308 +#define LPDDR4__PHY_CLK_DC_DM_THRSHLD__FLD LPDDR4__DENALI_PHY_1308__PHY_CLK_DC_DM_THRSHLD + +#define LPDDR4__DENALI_PHY_1308__PHY_LP4_BOOT_PLL_CTRL_MASK 0x001FFF00U +#define LPDDR4__DENALI_PHY_1308__PHY_LP4_BOOT_PLL_CTRL_SHIFT 8U +#define LPDDR4__DENALI_PHY_1308__PHY_LP4_BOOT_PLL_CTRL_WIDTH 13U +#define LPDDR4__PHY_LP4_BOOT_PLL_CTRL__REG DENALI_PHY_1308 +#define LPDDR4__PHY_LP4_BOOT_PLL_CTRL__FLD LPDDR4__DENALI_PHY_1308__PHY_LP4_BOOT_PLL_CTRL + +#define LPDDR4__DENALI_PHY_1309_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PHY_1309_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PHY_1309__PHY_PLL_CTRL_OVERRIDE_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_1309__PHY_PLL_CTRL_OVERRIDE_SHIFT 0U +#define LPDDR4__DENALI_PHY_1309__PHY_PLL_CTRL_OVERRIDE_WIDTH 16U +#define LPDDR4__PHY_PLL_CTRL_OVERRIDE__REG DENALI_PHY_1309 +#define LPDDR4__PHY_PLL_CTRL_OVERRIDE__FLD LPDDR4__DENALI_PHY_1309__PHY_PLL_CTRL_OVERRIDE + +#define LPDDR4__DENALI_PHY_1309__PHY_USE_PLL_DSKEWCALLOCK_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_1309__PHY_USE_PLL_DSKEWCALLOCK_SHIFT 16U +#define LPDDR4__DENALI_PHY_1309__PHY_USE_PLL_DSKEWCALLOCK_WIDTH 1U +#define LPDDR4__DENALI_PHY_1309__PHY_USE_PLL_DSKEWCALLOCK_WOCLR 0U +#define LPDDR4__DENALI_PHY_1309__PHY_USE_PLL_DSKEWCALLOCK_WOSET 0U +#define LPDDR4__PHY_USE_PLL_DSKEWCALLOCK__REG DENALI_PHY_1309 +#define LPDDR4__PHY_USE_PLL_DSKEWCALLOCK__FLD LPDDR4__DENALI_PHY_1309__PHY_USE_PLL_DSKEWCALLOCK + +#define LPDDR4__DENALI_PHY_1310_READ_MASK 0x0007FFFFU +#define LPDDR4__DENALI_PHY_1310_WRITE_MASK 0x0007FFFFU +#define LPDDR4__DENALI_PHY_1310__PHY_PLL_SPO_CAL_CTRL_MASK 0x0007FFFFU +#define LPDDR4__DENALI_PHY_1310__PHY_PLL_SPO_CAL_CTRL_SHIFT 0U +#define LPDDR4__DENALI_PHY_1310__PHY_PLL_SPO_CAL_CTRL_WIDTH 19U +#define LPDDR4__PHY_PLL_SPO_CAL_CTRL__REG DENALI_PHY_1310 +#define LPDDR4__PHY_PLL_SPO_CAL_CTRL__FLD LPDDR4__DENALI_PHY_1310__PHY_PLL_SPO_CAL_CTRL + +#define LPDDR4__DENALI_PHY_1310__SC_PHY_PLL_SPO_CAL_SNAP_OBS_MASK 0x03000000U +#define LPDDR4__DENALI_PHY_1310__SC_PHY_PLL_SPO_CAL_SNAP_OBS_SHIFT 24U +#define LPDDR4__DENALI_PHY_1310__SC_PHY_PLL_SPO_CAL_SNAP_OBS_WIDTH 2U +#define LPDDR4__SC_PHY_PLL_SPO_CAL_SNAP_OBS__REG DENALI_PHY_1310 +#define LPDDR4__SC_PHY_PLL_SPO_CAL_SNAP_OBS__FLD LPDDR4__DENALI_PHY_1310__SC_PHY_PLL_SPO_CAL_SNAP_OBS + +#define LPDDR4__DENALI_PHY_1311_READ_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_1311_WRITE_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_1311__PHY_PLL_CAL_CLK_MEAS_CYCLES_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_1311__PHY_PLL_CAL_CLK_MEAS_CYCLES_SHIFT 0U +#define LPDDR4__DENALI_PHY_1311__PHY_PLL_CAL_CLK_MEAS_CYCLES_WIDTH 10U +#define LPDDR4__PHY_PLL_CAL_CLK_MEAS_CYCLES__REG DENALI_PHY_1311 +#define LPDDR4__PHY_PLL_CAL_CLK_MEAS_CYCLES__FLD LPDDR4__DENALI_PHY_1311__PHY_PLL_CAL_CLK_MEAS_CYCLES + +#define LPDDR4__DENALI_PHY_1311__SC_PHY_PLL_CAL_CLK_MEAS_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_1311__SC_PHY_PLL_CAL_CLK_MEAS_SHIFT 16U +#define LPDDR4__DENALI_PHY_1311__SC_PHY_PLL_CAL_CLK_MEAS_WIDTH 2U +#define LPDDR4__SC_PHY_PLL_CAL_CLK_MEAS__REG DENALI_PHY_1311 +#define LPDDR4__SC_PHY_PLL_CAL_CLK_MEAS__FLD LPDDR4__DENALI_PHY_1311__SC_PHY_PLL_CAL_CLK_MEAS + +#define LPDDR4__DENALI_PHY_1312_READ_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_1312_WRITE_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_1312__PHY_PLL_OBS_0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_1312__PHY_PLL_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1312__PHY_PLL_OBS_0_WIDTH 16U +#define LPDDR4__PHY_PLL_OBS_0__REG DENALI_PHY_1312 +#define LPDDR4__PHY_PLL_OBS_0__FLD LPDDR4__DENALI_PHY_1312__PHY_PLL_OBS_0 + +#define LPDDR4__DENALI_PHY_1313_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PHY_1313_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PHY_1313__PHY_PLL_SPO_CAL_OBS_0_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PHY_1313__PHY_PLL_SPO_CAL_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1313__PHY_PLL_SPO_CAL_OBS_0_WIDTH 17U +#define LPDDR4__PHY_PLL_SPO_CAL_OBS_0__REG DENALI_PHY_1313 +#define LPDDR4__PHY_PLL_SPO_CAL_OBS_0__FLD LPDDR4__DENALI_PHY_1313__PHY_PLL_SPO_CAL_OBS_0 + +#define LPDDR4__DENALI_PHY_1314_READ_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1314_WRITE_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1314__PHY_PLL_CAL_CLK_MEAS_OBS_0_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1314__PHY_PLL_CAL_CLK_MEAS_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1314__PHY_PLL_CAL_CLK_MEAS_OBS_0_WIDTH 18U +#define LPDDR4__PHY_PLL_CAL_CLK_MEAS_OBS_0__REG DENALI_PHY_1314 +#define LPDDR4__PHY_PLL_CAL_CLK_MEAS_OBS_0__FLD LPDDR4__DENALI_PHY_1314__PHY_PLL_CAL_CLK_MEAS_OBS_0 + +#define LPDDR4__DENALI_PHY_1315_READ_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_1315_WRITE_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_1315__PHY_PLL_OBS_1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_1315__PHY_PLL_OBS_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_1315__PHY_PLL_OBS_1_WIDTH 16U +#define LPDDR4__PHY_PLL_OBS_1__REG DENALI_PHY_1315 +#define LPDDR4__PHY_PLL_OBS_1__FLD LPDDR4__DENALI_PHY_1315__PHY_PLL_OBS_1 + +#define LPDDR4__DENALI_PHY_1316_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PHY_1316_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PHY_1316__PHY_PLL_SPO_CAL_OBS_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PHY_1316__PHY_PLL_SPO_CAL_OBS_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_1316__PHY_PLL_SPO_CAL_OBS_1_WIDTH 17U +#define LPDDR4__PHY_PLL_SPO_CAL_OBS_1__REG DENALI_PHY_1316 +#define LPDDR4__PHY_PLL_SPO_CAL_OBS_1__FLD LPDDR4__DENALI_PHY_1316__PHY_PLL_SPO_CAL_OBS_1 + +#define LPDDR4__DENALI_PHY_1317_READ_MASK 0x0103FFFFU +#define LPDDR4__DENALI_PHY_1317_WRITE_MASK 0x0103FFFFU +#define LPDDR4__DENALI_PHY_1317__PHY_PLL_CAL_CLK_MEAS_OBS_1_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1317__PHY_PLL_CAL_CLK_MEAS_OBS_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_1317__PHY_PLL_CAL_CLK_MEAS_OBS_1_WIDTH 18U +#define LPDDR4__PHY_PLL_CAL_CLK_MEAS_OBS_1__REG DENALI_PHY_1317 +#define LPDDR4__PHY_PLL_CAL_CLK_MEAS_OBS_1__FLD LPDDR4__DENALI_PHY_1317__PHY_PLL_CAL_CLK_MEAS_OBS_1 + +#define LPDDR4__DENALI_PHY_1317__PHY_LP4_BOOT_LOW_FREQ_SEL_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_1317__PHY_LP4_BOOT_LOW_FREQ_SEL_SHIFT 24U +#define LPDDR4__DENALI_PHY_1317__PHY_LP4_BOOT_LOW_FREQ_SEL_WIDTH 1U +#define LPDDR4__DENALI_PHY_1317__PHY_LP4_BOOT_LOW_FREQ_SEL_WOCLR 0U +#define LPDDR4__DENALI_PHY_1317__PHY_LP4_BOOT_LOW_FREQ_SEL_WOSET 0U +#define LPDDR4__PHY_LP4_BOOT_LOW_FREQ_SEL__REG DENALI_PHY_1317 +#define LPDDR4__PHY_LP4_BOOT_LOW_FREQ_SEL__FLD LPDDR4__DENALI_PHY_1317__PHY_LP4_BOOT_LOW_FREQ_SEL + +#define LPDDR4__DENALI_PHY_1318_READ_MASK 0x0001FF0FU +#define LPDDR4__DENALI_PHY_1318_WRITE_MASK 0x0001FF0FU +#define LPDDR4__DENALI_PHY_1318__PHY_TCKSRE_WAIT_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_1318__PHY_TCKSRE_WAIT_SHIFT 0U +#define LPDDR4__DENALI_PHY_1318__PHY_TCKSRE_WAIT_WIDTH 4U +#define LPDDR4__PHY_TCKSRE_WAIT__REG DENALI_PHY_1318 +#define LPDDR4__PHY_TCKSRE_WAIT__FLD LPDDR4__DENALI_PHY_1318__PHY_TCKSRE_WAIT + +#define LPDDR4__DENALI_PHY_1318__PHY_LP_WAKEUP_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_1318__PHY_LP_WAKEUP_SHIFT 8U +#define LPDDR4__DENALI_PHY_1318__PHY_LP_WAKEUP_WIDTH 8U +#define LPDDR4__PHY_LP_WAKEUP__REG DENALI_PHY_1318 +#define LPDDR4__PHY_LP_WAKEUP__FLD LPDDR4__DENALI_PHY_1318__PHY_LP_WAKEUP + +#define LPDDR4__DENALI_PHY_1318__PHY_LS_IDLE_EN_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_1318__PHY_LS_IDLE_EN_SHIFT 16U +#define LPDDR4__DENALI_PHY_1318__PHY_LS_IDLE_EN_WIDTH 1U +#define LPDDR4__DENALI_PHY_1318__PHY_LS_IDLE_EN_WOCLR 0U +#define LPDDR4__DENALI_PHY_1318__PHY_LS_IDLE_EN_WOSET 0U +#define LPDDR4__PHY_LS_IDLE_EN__REG DENALI_PHY_1318 +#define LPDDR4__PHY_LS_IDLE_EN__FLD LPDDR4__DENALI_PHY_1318__PHY_LS_IDLE_EN + +#define LPDDR4__DENALI_PHY_1319_READ_MASK 0x000103FFU +#define LPDDR4__DENALI_PHY_1319_WRITE_MASK 0x000103FFU +#define LPDDR4__DENALI_PHY_1319__PHY_LP_CTRLUPD_CNTR_CFG_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_1319__PHY_LP_CTRLUPD_CNTR_CFG_SHIFT 0U +#define LPDDR4__DENALI_PHY_1319__PHY_LP_CTRLUPD_CNTR_CFG_WIDTH 10U +#define LPDDR4__PHY_LP_CTRLUPD_CNTR_CFG__REG DENALI_PHY_1319 +#define LPDDR4__PHY_LP_CTRLUPD_CNTR_CFG__FLD LPDDR4__DENALI_PHY_1319__PHY_LP_CTRLUPD_CNTR_CFG + +#define LPDDR4__DENALI_PHY_1319__PHY_TDFI_PHY_WRDELAY_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_1319__PHY_TDFI_PHY_WRDELAY_SHIFT 16U +#define LPDDR4__DENALI_PHY_1319__PHY_TDFI_PHY_WRDELAY_WIDTH 1U +#define LPDDR4__DENALI_PHY_1319__PHY_TDFI_PHY_WRDELAY_WOCLR 0U +#define LPDDR4__DENALI_PHY_1319__PHY_TDFI_PHY_WRDELAY_WOSET 0U +#define LPDDR4__PHY_TDFI_PHY_WRDELAY__REG DENALI_PHY_1319 +#define LPDDR4__PHY_TDFI_PHY_WRDELAY__FLD LPDDR4__DENALI_PHY_1319__PHY_TDFI_PHY_WRDELAY + +#define LPDDR4__DENALI_PHY_1320_READ_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1320_WRITE_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1320__PHY_PAD_FDBK_TERM_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1320__PHY_PAD_FDBK_TERM_SHIFT 0U +#define LPDDR4__DENALI_PHY_1320__PHY_PAD_FDBK_TERM_WIDTH 18U +#define LPDDR4__PHY_PAD_FDBK_TERM__REG DENALI_PHY_1320 +#define LPDDR4__PHY_PAD_FDBK_TERM__FLD LPDDR4__DENALI_PHY_1320__PHY_PAD_FDBK_TERM + +#define LPDDR4__DENALI_PHY_1321_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PHY_1321_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PHY_1321__PHY_PAD_DATA_TERM_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PHY_1321__PHY_PAD_DATA_TERM_SHIFT 0U +#define LPDDR4__DENALI_PHY_1321__PHY_PAD_DATA_TERM_WIDTH 17U +#define LPDDR4__PHY_PAD_DATA_TERM__REG DENALI_PHY_1321 +#define LPDDR4__PHY_PAD_DATA_TERM__FLD LPDDR4__DENALI_PHY_1321__PHY_PAD_DATA_TERM + +#define LPDDR4__DENALI_PHY_1322_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PHY_1322_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PHY_1322__PHY_PAD_DQS_TERM_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PHY_1322__PHY_PAD_DQS_TERM_SHIFT 0U +#define LPDDR4__DENALI_PHY_1322__PHY_PAD_DQS_TERM_WIDTH 17U +#define LPDDR4__PHY_PAD_DQS_TERM__REG DENALI_PHY_1322 +#define LPDDR4__PHY_PAD_DQS_TERM__FLD LPDDR4__DENALI_PHY_1322__PHY_PAD_DQS_TERM + +#define LPDDR4__DENALI_PHY_1323_READ_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1323_WRITE_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1323__PHY_PAD_ADDR_TERM_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1323__PHY_PAD_ADDR_TERM_SHIFT 0U +#define LPDDR4__DENALI_PHY_1323__PHY_PAD_ADDR_TERM_WIDTH 18U +#define LPDDR4__PHY_PAD_ADDR_TERM__REG DENALI_PHY_1323 +#define LPDDR4__PHY_PAD_ADDR_TERM__FLD LPDDR4__DENALI_PHY_1323__PHY_PAD_ADDR_TERM + +#define LPDDR4__DENALI_PHY_1324_READ_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1324_WRITE_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1324__PHY_PAD_CLK_TERM_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1324__PHY_PAD_CLK_TERM_SHIFT 0U +#define LPDDR4__DENALI_PHY_1324__PHY_PAD_CLK_TERM_WIDTH 18U +#define LPDDR4__PHY_PAD_CLK_TERM__REG DENALI_PHY_1324 +#define LPDDR4__PHY_PAD_CLK_TERM__FLD LPDDR4__DENALI_PHY_1324__PHY_PAD_CLK_TERM + +#define LPDDR4__DENALI_PHY_1325_READ_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1325_WRITE_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1325__PHY_PAD_CKE_TERM_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1325__PHY_PAD_CKE_TERM_SHIFT 0U +#define LPDDR4__DENALI_PHY_1325__PHY_PAD_CKE_TERM_WIDTH 18U +#define LPDDR4__PHY_PAD_CKE_TERM__REG DENALI_PHY_1325 +#define LPDDR4__PHY_PAD_CKE_TERM__FLD LPDDR4__DENALI_PHY_1325__PHY_PAD_CKE_TERM + +#define LPDDR4__DENALI_PHY_1326_READ_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1326_WRITE_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1326__PHY_PAD_RST_TERM_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1326__PHY_PAD_RST_TERM_SHIFT 0U +#define LPDDR4__DENALI_PHY_1326__PHY_PAD_RST_TERM_WIDTH 18U +#define LPDDR4__PHY_PAD_RST_TERM__REG DENALI_PHY_1326 +#define LPDDR4__PHY_PAD_RST_TERM__FLD LPDDR4__DENALI_PHY_1326__PHY_PAD_RST_TERM + +#define LPDDR4__DENALI_PHY_1327_READ_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1327_WRITE_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1327__PHY_PAD_CS_TERM_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1327__PHY_PAD_CS_TERM_SHIFT 0U +#define LPDDR4__DENALI_PHY_1327__PHY_PAD_CS_TERM_WIDTH 18U +#define LPDDR4__PHY_PAD_CS_TERM__REG DENALI_PHY_1327 +#define LPDDR4__PHY_PAD_CS_TERM__FLD LPDDR4__DENALI_PHY_1327__PHY_PAD_CS_TERM + +#define LPDDR4__DENALI_PHY_1328_READ_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1328_WRITE_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1328__PHY_PAD_ODT_TERM_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1328__PHY_PAD_ODT_TERM_SHIFT 0U +#define LPDDR4__DENALI_PHY_1328__PHY_PAD_ODT_TERM_WIDTH 18U +#define LPDDR4__PHY_PAD_ODT_TERM__REG DENALI_PHY_1328 +#define LPDDR4__PHY_PAD_ODT_TERM__FLD LPDDR4__DENALI_PHY_1328__PHY_PAD_ODT_TERM + +#define LPDDR4__DENALI_PHY_1329_READ_MASK 0x1FFF03FFU +#define LPDDR4__DENALI_PHY_1329_WRITE_MASK 0x1FFF03FFU +#define LPDDR4__DENALI_PHY_1329__PHY_ADRCTL_RX_CAL_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_1329__PHY_ADRCTL_RX_CAL_SHIFT 0U +#define LPDDR4__DENALI_PHY_1329__PHY_ADRCTL_RX_CAL_WIDTH 10U +#define LPDDR4__PHY_ADRCTL_RX_CAL__REG DENALI_PHY_1329 +#define LPDDR4__PHY_ADRCTL_RX_CAL__FLD LPDDR4__DENALI_PHY_1329__PHY_ADRCTL_RX_CAL + +#define LPDDR4__DENALI_PHY_1329__PHY_ADRCTL_LP3_RX_CAL_MASK 0x1FFF0000U +#define LPDDR4__DENALI_PHY_1329__PHY_ADRCTL_LP3_RX_CAL_SHIFT 16U +#define LPDDR4__DENALI_PHY_1329__PHY_ADRCTL_LP3_RX_CAL_WIDTH 13U +#define LPDDR4__PHY_ADRCTL_LP3_RX_CAL__REG DENALI_PHY_1329 +#define LPDDR4__PHY_ADRCTL_LP3_RX_CAL__FLD LPDDR4__DENALI_PHY_1329__PHY_ADRCTL_LP3_RX_CAL + +#define LPDDR4__DENALI_PHY_1330_READ_MASK 0x00001FFFU +#define LPDDR4__DENALI_PHY_1330_WRITE_MASK 0x00001FFFU +#define LPDDR4__DENALI_PHY_1330__PHY_CAL_MODE_0_MASK 0x00001FFFU +#define LPDDR4__DENALI_PHY_1330__PHY_CAL_MODE_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1330__PHY_CAL_MODE_0_WIDTH 13U +#define LPDDR4__PHY_CAL_MODE_0__REG DENALI_PHY_1330 +#define LPDDR4__PHY_CAL_MODE_0__FLD LPDDR4__DENALI_PHY_1330__PHY_CAL_MODE_0 + +#define LPDDR4__DENALI_PHY_1330__PHY_CAL_CLEAR_0_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_1330__PHY_CAL_CLEAR_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1330__PHY_CAL_CLEAR_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_1330__PHY_CAL_CLEAR_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_1330__PHY_CAL_CLEAR_0_WOSET 0U +#define LPDDR4__PHY_CAL_CLEAR_0__REG DENALI_PHY_1330 +#define LPDDR4__PHY_CAL_CLEAR_0__FLD LPDDR4__DENALI_PHY_1330__PHY_CAL_CLEAR_0 + +#define LPDDR4__DENALI_PHY_1330__PHY_CAL_START_0_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_1330__PHY_CAL_START_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_1330__PHY_CAL_START_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_1330__PHY_CAL_START_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_1330__PHY_CAL_START_0_WOSET 0U +#define LPDDR4__PHY_CAL_START_0__REG DENALI_PHY_1330 +#define LPDDR4__PHY_CAL_START_0__FLD LPDDR4__DENALI_PHY_1330__PHY_CAL_START_0 + +#define LPDDR4__DENALI_PHY_1331_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1331_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1331__PHY_CAL_INTERVAL_COUNT_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1331__PHY_CAL_INTERVAL_COUNT_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1331__PHY_CAL_INTERVAL_COUNT_0_WIDTH 32U +#define LPDDR4__PHY_CAL_INTERVAL_COUNT_0__REG DENALI_PHY_1331 +#define LPDDR4__PHY_CAL_INTERVAL_COUNT_0__FLD LPDDR4__DENALI_PHY_1331__PHY_CAL_INTERVAL_COUNT_0 + +#define LPDDR4__DENALI_PHY_1332_READ_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1332_WRITE_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1332__PHY_CAL_SAMPLE_WAIT_0_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_1332__PHY_CAL_SAMPLE_WAIT_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1332__PHY_CAL_SAMPLE_WAIT_0_WIDTH 8U +#define LPDDR4__PHY_CAL_SAMPLE_WAIT_0__REG DENALI_PHY_1332 +#define LPDDR4__PHY_CAL_SAMPLE_WAIT_0__FLD LPDDR4__DENALI_PHY_1332__PHY_CAL_SAMPLE_WAIT_0 + +#define LPDDR4__DENALI_PHY_1332__PHY_LP4_BOOT_CAL_CLK_SELECT_0_MASK 0x00000700U +#define LPDDR4__DENALI_PHY_1332__PHY_LP4_BOOT_CAL_CLK_SELECT_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_1332__PHY_LP4_BOOT_CAL_CLK_SELECT_0_WIDTH 3U +#define LPDDR4__PHY_LP4_BOOT_CAL_CLK_SELECT_0__REG DENALI_PHY_1332 +#define LPDDR4__PHY_LP4_BOOT_CAL_CLK_SELECT_0__FLD LPDDR4__DENALI_PHY_1332__PHY_LP4_BOOT_CAL_CLK_SELECT_0 + +#define LPDDR4__DENALI_PHY_1333_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PHY_1333_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PHY_1333__PHY_CAL_RESULT_OBS_0_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PHY_1333__PHY_CAL_RESULT_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1333__PHY_CAL_RESULT_OBS_0_WIDTH 24U +#define LPDDR4__PHY_CAL_RESULT_OBS_0__REG DENALI_PHY_1333 +#define LPDDR4__PHY_CAL_RESULT_OBS_0__FLD LPDDR4__DENALI_PHY_1333__PHY_CAL_RESULT_OBS_0 + +#define LPDDR4__DENALI_PHY_1334_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PHY_1334_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PHY_1334__PHY_CAL_RESULT2_OBS_0_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PHY_1334__PHY_CAL_RESULT2_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1334__PHY_CAL_RESULT2_OBS_0_WIDTH 24U +#define LPDDR4__PHY_CAL_RESULT2_OBS_0__REG DENALI_PHY_1334 +#define LPDDR4__PHY_CAL_RESULT2_OBS_0__FLD LPDDR4__DENALI_PHY_1334__PHY_CAL_RESULT2_OBS_0 + +#define LPDDR4__DENALI_PHY_1335_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PHY_1335_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PHY_1335__PHY_CAL_RESULT4_OBS_0_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PHY_1335__PHY_CAL_RESULT4_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1335__PHY_CAL_RESULT4_OBS_0_WIDTH 24U +#define LPDDR4__PHY_CAL_RESULT4_OBS_0__REG DENALI_PHY_1335 +#define LPDDR4__PHY_CAL_RESULT4_OBS_0__FLD LPDDR4__DENALI_PHY_1335__PHY_CAL_RESULT4_OBS_0 + +#define LPDDR4__DENALI_PHY_1336_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PHY_1336_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PHY_1336__PHY_CAL_RESULT5_OBS_0_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PHY_1336__PHY_CAL_RESULT5_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1336__PHY_CAL_RESULT5_OBS_0_WIDTH 24U +#define LPDDR4__PHY_CAL_RESULT5_OBS_0__REG DENALI_PHY_1336 +#define LPDDR4__PHY_CAL_RESULT5_OBS_0__FLD LPDDR4__DENALI_PHY_1336__PHY_CAL_RESULT5_OBS_0 + +#define LPDDR4__DENALI_PHY_1337_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PHY_1337_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PHY_1337__PHY_CAL_RESULT6_OBS_0_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PHY_1337__PHY_CAL_RESULT6_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1337__PHY_CAL_RESULT6_OBS_0_WIDTH 24U +#define LPDDR4__PHY_CAL_RESULT6_OBS_0__REG DENALI_PHY_1337 +#define LPDDR4__PHY_CAL_RESULT6_OBS_0__FLD LPDDR4__DENALI_PHY_1337__PHY_CAL_RESULT6_OBS_0 + +#define LPDDR4__DENALI_PHY_1338_READ_MASK 0x7FFFFFFFU +#define LPDDR4__DENALI_PHY_1338_WRITE_MASK 0x7FFFFFFFU +#define LPDDR4__DENALI_PHY_1338__PHY_CAL_RESULT7_OBS_0_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PHY_1338__PHY_CAL_RESULT7_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1338__PHY_CAL_RESULT7_OBS_0_WIDTH 24U +#define LPDDR4__PHY_CAL_RESULT7_OBS_0__REG DENALI_PHY_1338 +#define LPDDR4__PHY_CAL_RESULT7_OBS_0__FLD LPDDR4__DENALI_PHY_1338__PHY_CAL_RESULT7_OBS_0 + +#define LPDDR4__DENALI_PHY_1338__PHY_CAL_CPTR_CNT_0_MASK 0x7F000000U +#define LPDDR4__DENALI_PHY_1338__PHY_CAL_CPTR_CNT_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_1338__PHY_CAL_CPTR_CNT_0_WIDTH 7U +#define LPDDR4__PHY_CAL_CPTR_CNT_0__REG DENALI_PHY_1338 +#define LPDDR4__PHY_CAL_CPTR_CNT_0__FLD LPDDR4__DENALI_PHY_1338__PHY_CAL_CPTR_CNT_0 + +#define LPDDR4__DENALI_PHY_1339_READ_MASK 0x01FFFFFFU +#define LPDDR4__DENALI_PHY_1339_WRITE_MASK 0x01FFFFFFU +#define LPDDR4__DENALI_PHY_1339__PHY_CAL_PU_FINE_ADJ_0_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_1339__PHY_CAL_PU_FINE_ADJ_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1339__PHY_CAL_PU_FINE_ADJ_0_WIDTH 8U +#define LPDDR4__PHY_CAL_PU_FINE_ADJ_0__REG DENALI_PHY_1339 +#define LPDDR4__PHY_CAL_PU_FINE_ADJ_0__FLD LPDDR4__DENALI_PHY_1339__PHY_CAL_PU_FINE_ADJ_0 + +#define LPDDR4__DENALI_PHY_1339__PHY_CAL_PD_FINE_ADJ_0_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_1339__PHY_CAL_PD_FINE_ADJ_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_1339__PHY_CAL_PD_FINE_ADJ_0_WIDTH 8U +#define LPDDR4__PHY_CAL_PD_FINE_ADJ_0__REG DENALI_PHY_1339 +#define LPDDR4__PHY_CAL_PD_FINE_ADJ_0__FLD LPDDR4__DENALI_PHY_1339__PHY_CAL_PD_FINE_ADJ_0 + +#define LPDDR4__DENALI_PHY_1339__PHY_CAL_RCV_FINE_ADJ_0_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_1339__PHY_CAL_RCV_FINE_ADJ_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1339__PHY_CAL_RCV_FINE_ADJ_0_WIDTH 8U +#define LPDDR4__PHY_CAL_RCV_FINE_ADJ_0__REG DENALI_PHY_1339 +#define LPDDR4__PHY_CAL_RCV_FINE_ADJ_0__FLD LPDDR4__DENALI_PHY_1339__PHY_CAL_RCV_FINE_ADJ_0 + +#define LPDDR4__DENALI_PHY_1339__PHY_CAL_DBG_CFG_0_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_1339__PHY_CAL_DBG_CFG_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_1339__PHY_CAL_DBG_CFG_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_1339__PHY_CAL_DBG_CFG_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_1339__PHY_CAL_DBG_CFG_0_WOSET 0U +#define LPDDR4__PHY_CAL_DBG_CFG_0__REG DENALI_PHY_1339 +#define LPDDR4__PHY_CAL_DBG_CFG_0__FLD LPDDR4__DENALI_PHY_1339__PHY_CAL_DBG_CFG_0 + +#define LPDDR4__DENALI_PHY_1340__SC_PHY_PAD_DBG_CONT_0_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_1340__SC_PHY_PAD_DBG_CONT_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1340__SC_PHY_PAD_DBG_CONT_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_1340__SC_PHY_PAD_DBG_CONT_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_1340__SC_PHY_PAD_DBG_CONT_0_WOSET 0U +#define LPDDR4__SC_PHY_PAD_DBG_CONT_0__REG DENALI_PHY_1340 +#define LPDDR4__SC_PHY_PAD_DBG_CONT_0__FLD LPDDR4__DENALI_PHY_1340__SC_PHY_PAD_DBG_CONT_0 + +#define LPDDR4__DENALI_PHY_1341_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1341_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1341__PHY_CAL_RESULT3_OBS_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1341__PHY_CAL_RESULT3_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1341__PHY_CAL_RESULT3_OBS_0_WIDTH 32U +#define LPDDR4__PHY_CAL_RESULT3_OBS_0__REG DENALI_PHY_1341 +#define LPDDR4__PHY_CAL_RESULT3_OBS_0__FLD LPDDR4__DENALI_PHY_1341__PHY_CAL_RESULT3_OBS_0 + +#define LPDDR4__DENALI_PHY_1342_READ_MASK 0x0FFFFF7FU +#define LPDDR4__DENALI_PHY_1342_WRITE_MASK 0x0FFFFF7FU +#define LPDDR4__DENALI_PHY_1342__PHY_ADRCTL_PVT_MAP_0_MASK 0x0000007FU +#define LPDDR4__DENALI_PHY_1342__PHY_ADRCTL_PVT_MAP_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1342__PHY_ADRCTL_PVT_MAP_0_WIDTH 7U +#define LPDDR4__PHY_ADRCTL_PVT_MAP_0__REG DENALI_PHY_1342 +#define LPDDR4__PHY_ADRCTL_PVT_MAP_0__FLD LPDDR4__DENALI_PHY_1342__PHY_ADRCTL_PVT_MAP_0 + +#define LPDDR4__DENALI_PHY_1342__PHY_CAL_SLOPE_ADJ_0_MASK 0x0FFFFF00U +#define LPDDR4__DENALI_PHY_1342__PHY_CAL_SLOPE_ADJ_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_1342__PHY_CAL_SLOPE_ADJ_0_WIDTH 20U +#define LPDDR4__PHY_CAL_SLOPE_ADJ_0__REG DENALI_PHY_1342 +#define LPDDR4__PHY_CAL_SLOPE_ADJ_0__FLD LPDDR4__DENALI_PHY_1342__PHY_CAL_SLOPE_ADJ_0 + +#define LPDDR4__DENALI_PHY_1343_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1343_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1343__PHY_CAL_SLOPE_ADJ_PASS2_0_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1343__PHY_CAL_SLOPE_ADJ_PASS2_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1343__PHY_CAL_SLOPE_ADJ_PASS2_0_WIDTH 20U +#define LPDDR4__PHY_CAL_SLOPE_ADJ_PASS2_0__REG DENALI_PHY_1343 +#define LPDDR4__PHY_CAL_SLOPE_ADJ_PASS2_0__FLD LPDDR4__DENALI_PHY_1343__PHY_CAL_SLOPE_ADJ_PASS2_0 + +#define LPDDR4__DENALI_PHY_1344_READ_MASK 0x01FFFFFFU +#define LPDDR4__DENALI_PHY_1344_WRITE_MASK 0x01FFFFFFU +#define LPDDR4__DENALI_PHY_1344__PHY_CAL_TWO_PASS_CFG_0_MASK 0x01FFFFFFU +#define LPDDR4__DENALI_PHY_1344__PHY_CAL_TWO_PASS_CFG_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1344__PHY_CAL_TWO_PASS_CFG_0_WIDTH 25U +#define LPDDR4__PHY_CAL_TWO_PASS_CFG_0__REG DENALI_PHY_1344 +#define LPDDR4__PHY_CAL_TWO_PASS_CFG_0__FLD LPDDR4__DENALI_PHY_1344__PHY_CAL_TWO_PASS_CFG_0 + +#define LPDDR4__DENALI_PHY_1345_READ_MASK 0x3F7FFFFFU +#define LPDDR4__DENALI_PHY_1345_WRITE_MASK 0x3F7FFFFFU +#define LPDDR4__DENALI_PHY_1345__PHY_CAL_SW_CAL_CFG_0_MASK 0x007FFFFFU +#define LPDDR4__DENALI_PHY_1345__PHY_CAL_SW_CAL_CFG_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1345__PHY_CAL_SW_CAL_CFG_0_WIDTH 23U +#define LPDDR4__PHY_CAL_SW_CAL_CFG_0__REG DENALI_PHY_1345 +#define LPDDR4__PHY_CAL_SW_CAL_CFG_0__FLD LPDDR4__DENALI_PHY_1345__PHY_CAL_SW_CAL_CFG_0 + +#define LPDDR4__DENALI_PHY_1345__PHY_CAL_RANGE_PASS1_PU_MAX_DELTA_0_MASK 0x3F000000U +#define LPDDR4__DENALI_PHY_1345__PHY_CAL_RANGE_PASS1_PU_MAX_DELTA_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_1345__PHY_CAL_RANGE_PASS1_PU_MAX_DELTA_0_WIDTH 6U +#define LPDDR4__PHY_CAL_RANGE_PASS1_PU_MAX_DELTA_0__REG DENALI_PHY_1345 +#define LPDDR4__PHY_CAL_RANGE_PASS1_PU_MAX_DELTA_0__FLD LPDDR4__DENALI_PHY_1345__PHY_CAL_RANGE_PASS1_PU_MAX_DELTA_0 + +#define LPDDR4__DENALI_PHY_1346_READ_MASK 0x3F3F1F3FU +#define LPDDR4__DENALI_PHY_1346_WRITE_MASK 0x3F3F1F3FU +#define LPDDR4__DENALI_PHY_1346__PHY_CAL_RANGE_PASS1_PD_MAX_DELTA_0_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_1346__PHY_CAL_RANGE_PASS1_PD_MAX_DELTA_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1346__PHY_CAL_RANGE_PASS1_PD_MAX_DELTA_0_WIDTH 6U +#define LPDDR4__PHY_CAL_RANGE_PASS1_PD_MAX_DELTA_0__REG DENALI_PHY_1346 +#define LPDDR4__PHY_CAL_RANGE_PASS1_PD_MAX_DELTA_0__FLD LPDDR4__DENALI_PHY_1346__PHY_CAL_RANGE_PASS1_PD_MAX_DELTA_0 + +#define LPDDR4__DENALI_PHY_1346__PHY_CAL_RANGE_PASS1_RX_MAX_DELTA_0_MASK 0x00001F00U +#define LPDDR4__DENALI_PHY_1346__PHY_CAL_RANGE_PASS1_RX_MAX_DELTA_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_1346__PHY_CAL_RANGE_PASS1_RX_MAX_DELTA_0_WIDTH 5U +#define LPDDR4__PHY_CAL_RANGE_PASS1_RX_MAX_DELTA_0__REG DENALI_PHY_1346 +#define LPDDR4__PHY_CAL_RANGE_PASS1_RX_MAX_DELTA_0__FLD LPDDR4__DENALI_PHY_1346__PHY_CAL_RANGE_PASS1_RX_MAX_DELTA_0 + +#define LPDDR4__DENALI_PHY_1346__PHY_CAL_RANGE_PASS2_PU_MAX_DELTA_0_MASK 0x003F0000U +#define LPDDR4__DENALI_PHY_1346__PHY_CAL_RANGE_PASS2_PU_MAX_DELTA_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1346__PHY_CAL_RANGE_PASS2_PU_MAX_DELTA_0_WIDTH 6U +#define LPDDR4__PHY_CAL_RANGE_PASS2_PU_MAX_DELTA_0__REG DENALI_PHY_1346 +#define LPDDR4__PHY_CAL_RANGE_PASS2_PU_MAX_DELTA_0__FLD LPDDR4__DENALI_PHY_1346__PHY_CAL_RANGE_PASS2_PU_MAX_DELTA_0 + +#define LPDDR4__DENALI_PHY_1346__PHY_CAL_RANGE_PASS2_PD_MAX_DELTA_0_MASK 0x3F000000U +#define LPDDR4__DENALI_PHY_1346__PHY_CAL_RANGE_PASS2_PD_MAX_DELTA_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_1346__PHY_CAL_RANGE_PASS2_PD_MAX_DELTA_0_WIDTH 6U +#define LPDDR4__PHY_CAL_RANGE_PASS2_PD_MAX_DELTA_0__REG DENALI_PHY_1346 +#define LPDDR4__PHY_CAL_RANGE_PASS2_PD_MAX_DELTA_0__FLD LPDDR4__DENALI_PHY_1346__PHY_CAL_RANGE_PASS2_PD_MAX_DELTA_0 + +#define LPDDR4__DENALI_PHY_1347_READ_MASK 0x1F3F3F1FU +#define LPDDR4__DENALI_PHY_1347_WRITE_MASK 0x1F3F3F1FU +#define LPDDR4__DENALI_PHY_1347__PHY_CAL_RANGE_PASS2_RX_MAX_DELTA_0_MASK 0x0000001FU +#define LPDDR4__DENALI_PHY_1347__PHY_CAL_RANGE_PASS2_RX_MAX_DELTA_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1347__PHY_CAL_RANGE_PASS2_RX_MAX_DELTA_0_WIDTH 5U +#define LPDDR4__PHY_CAL_RANGE_PASS2_RX_MAX_DELTA_0__REG DENALI_PHY_1347 +#define LPDDR4__PHY_CAL_RANGE_PASS2_RX_MAX_DELTA_0__FLD LPDDR4__DENALI_PHY_1347__PHY_CAL_RANGE_PASS2_RX_MAX_DELTA_0 + +#define LPDDR4__DENALI_PHY_1347__PHY_CAL_RANGE_PASS1_PU_MIN_DELTA_0_MASK 0x00003F00U +#define LPDDR4__DENALI_PHY_1347__PHY_CAL_RANGE_PASS1_PU_MIN_DELTA_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_1347__PHY_CAL_RANGE_PASS1_PU_MIN_DELTA_0_WIDTH 6U +#define LPDDR4__PHY_CAL_RANGE_PASS1_PU_MIN_DELTA_0__REG DENALI_PHY_1347 +#define LPDDR4__PHY_CAL_RANGE_PASS1_PU_MIN_DELTA_0__FLD LPDDR4__DENALI_PHY_1347__PHY_CAL_RANGE_PASS1_PU_MIN_DELTA_0 + +#define LPDDR4__DENALI_PHY_1347__PHY_CAL_RANGE_PASS1_PD_MIN_DELTA_0_MASK 0x003F0000U +#define LPDDR4__DENALI_PHY_1347__PHY_CAL_RANGE_PASS1_PD_MIN_DELTA_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1347__PHY_CAL_RANGE_PASS1_PD_MIN_DELTA_0_WIDTH 6U +#define LPDDR4__PHY_CAL_RANGE_PASS1_PD_MIN_DELTA_0__REG DENALI_PHY_1347 +#define LPDDR4__PHY_CAL_RANGE_PASS1_PD_MIN_DELTA_0__FLD LPDDR4__DENALI_PHY_1347__PHY_CAL_RANGE_PASS1_PD_MIN_DELTA_0 + +#define LPDDR4__DENALI_PHY_1347__PHY_CAL_RANGE_PASS1_RX_MIN_DELTA_0_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_1347__PHY_CAL_RANGE_PASS1_RX_MIN_DELTA_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_1347__PHY_CAL_RANGE_PASS1_RX_MIN_DELTA_0_WIDTH 5U +#define LPDDR4__PHY_CAL_RANGE_PASS1_RX_MIN_DELTA_0__REG DENALI_PHY_1347 +#define LPDDR4__PHY_CAL_RANGE_PASS1_RX_MIN_DELTA_0__FLD LPDDR4__DENALI_PHY_1347__PHY_CAL_RANGE_PASS1_RX_MIN_DELTA_0 + +#define LPDDR4__DENALI_PHY_1348_READ_MASK 0x001F3F3FU +#define LPDDR4__DENALI_PHY_1348_WRITE_MASK 0x001F3F3FU +#define LPDDR4__DENALI_PHY_1348__PHY_CAL_RANGE_PASS2_PU_MIN_DELTA_0_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_1348__PHY_CAL_RANGE_PASS2_PU_MIN_DELTA_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1348__PHY_CAL_RANGE_PASS2_PU_MIN_DELTA_0_WIDTH 6U +#define LPDDR4__PHY_CAL_RANGE_PASS2_PU_MIN_DELTA_0__REG DENALI_PHY_1348 +#define LPDDR4__PHY_CAL_RANGE_PASS2_PU_MIN_DELTA_0__FLD LPDDR4__DENALI_PHY_1348__PHY_CAL_RANGE_PASS2_PU_MIN_DELTA_0 + +#define LPDDR4__DENALI_PHY_1348__PHY_CAL_RANGE_PASS2_PD_MIN_DELTA_0_MASK 0x00003F00U +#define LPDDR4__DENALI_PHY_1348__PHY_CAL_RANGE_PASS2_PD_MIN_DELTA_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_1348__PHY_CAL_RANGE_PASS2_PD_MIN_DELTA_0_WIDTH 6U +#define LPDDR4__PHY_CAL_RANGE_PASS2_PD_MIN_DELTA_0__REG DENALI_PHY_1348 +#define LPDDR4__PHY_CAL_RANGE_PASS2_PD_MIN_DELTA_0__FLD LPDDR4__DENALI_PHY_1348__PHY_CAL_RANGE_PASS2_PD_MIN_DELTA_0 + +#define LPDDR4__DENALI_PHY_1348__PHY_CAL_RANGE_PASS2_RX_MIN_DELTA_0_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_1348__PHY_CAL_RANGE_PASS2_RX_MIN_DELTA_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1348__PHY_CAL_RANGE_PASS2_RX_MIN_DELTA_0_WIDTH 5U +#define LPDDR4__PHY_CAL_RANGE_PASS2_RX_MIN_DELTA_0__REG DENALI_PHY_1348 +#define LPDDR4__PHY_CAL_RANGE_PASS2_RX_MIN_DELTA_0__FLD LPDDR4__DENALI_PHY_1348__PHY_CAL_RANGE_PASS2_RX_MIN_DELTA_0 + +#define LPDDR4__DENALI_PHY_1349_READ_MASK 0x07FFFFFFU +#define LPDDR4__DENALI_PHY_1349_WRITE_MASK 0x07FFFFFFU +#define LPDDR4__DENALI_PHY_1349__PHY_PAD_ATB_CTRL_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_1349__PHY_PAD_ATB_CTRL_SHIFT 0U +#define LPDDR4__DENALI_PHY_1349__PHY_PAD_ATB_CTRL_WIDTH 16U +#define LPDDR4__PHY_PAD_ATB_CTRL__REG DENALI_PHY_1349 +#define LPDDR4__PHY_PAD_ATB_CTRL__FLD LPDDR4__DENALI_PHY_1349__PHY_PAD_ATB_CTRL + +#define LPDDR4__DENALI_PHY_1349__PHY_PARITY_ERROR_REGIF_AC_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_1349__PHY_PARITY_ERROR_REGIF_AC_SHIFT 16U +#define LPDDR4__DENALI_PHY_1349__PHY_PARITY_ERROR_REGIF_AC_WIDTH 11U +#define LPDDR4__PHY_PARITY_ERROR_REGIF_AC__REG DENALI_PHY_1349 +#define LPDDR4__PHY_PARITY_ERROR_REGIF_AC__FLD LPDDR4__DENALI_PHY_1349__PHY_PARITY_ERROR_REGIF_AC + +#define LPDDR4__DENALI_PHY_1350_READ_MASK 0x03010000U +#define LPDDR4__DENALI_PHY_1350_WRITE_MASK 0x03010000U +#define LPDDR4__DENALI_PHY_1350__PHY_ADRCTL_MANUAL_UPDATE_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_1350__PHY_ADRCTL_MANUAL_UPDATE_SHIFT 0U +#define LPDDR4__DENALI_PHY_1350__PHY_ADRCTL_MANUAL_UPDATE_WIDTH 1U +#define LPDDR4__DENALI_PHY_1350__PHY_ADRCTL_MANUAL_UPDATE_WOCLR 0U +#define LPDDR4__DENALI_PHY_1350__PHY_ADRCTL_MANUAL_UPDATE_WOSET 0U +#define LPDDR4__PHY_ADRCTL_MANUAL_UPDATE__REG DENALI_PHY_1350 +#define LPDDR4__PHY_ADRCTL_MANUAL_UPDATE__FLD LPDDR4__DENALI_PHY_1350__PHY_ADRCTL_MANUAL_UPDATE + +#define LPDDR4__DENALI_PHY_1350__PHY_AC_LPBK_ERR_CLEAR_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_1350__PHY_AC_LPBK_ERR_CLEAR_SHIFT 8U +#define LPDDR4__DENALI_PHY_1350__PHY_AC_LPBK_ERR_CLEAR_WIDTH 1U +#define LPDDR4__DENALI_PHY_1350__PHY_AC_LPBK_ERR_CLEAR_WOCLR 0U +#define LPDDR4__DENALI_PHY_1350__PHY_AC_LPBK_ERR_CLEAR_WOSET 0U +#define LPDDR4__PHY_AC_LPBK_ERR_CLEAR__REG DENALI_PHY_1350 +#define LPDDR4__PHY_AC_LPBK_ERR_CLEAR__FLD LPDDR4__DENALI_PHY_1350__PHY_AC_LPBK_ERR_CLEAR + +#define LPDDR4__DENALI_PHY_1350__PHY_AC_LPBK_OBS_SELECT_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_1350__PHY_AC_LPBK_OBS_SELECT_SHIFT 16U +#define LPDDR4__DENALI_PHY_1350__PHY_AC_LPBK_OBS_SELECT_WIDTH 1U +#define LPDDR4__DENALI_PHY_1350__PHY_AC_LPBK_OBS_SELECT_WOCLR 0U +#define LPDDR4__DENALI_PHY_1350__PHY_AC_LPBK_OBS_SELECT_WOSET 0U +#define LPDDR4__PHY_AC_LPBK_OBS_SELECT__REG DENALI_PHY_1350 +#define LPDDR4__PHY_AC_LPBK_OBS_SELECT__FLD LPDDR4__DENALI_PHY_1350__PHY_AC_LPBK_OBS_SELECT + +#define LPDDR4__DENALI_PHY_1350__PHY_AC_LPBK_ENABLE_MASK 0x03000000U +#define LPDDR4__DENALI_PHY_1350__PHY_AC_LPBK_ENABLE_SHIFT 24U +#define LPDDR4__DENALI_PHY_1350__PHY_AC_LPBK_ENABLE_WIDTH 2U +#define LPDDR4__PHY_AC_LPBK_ENABLE__REG DENALI_PHY_1350 +#define LPDDR4__PHY_AC_LPBK_ENABLE__FLD LPDDR4__DENALI_PHY_1350__PHY_AC_LPBK_ENABLE + +#define LPDDR4__DENALI_PHY_1351_READ_MASK 0x0F7F01FFU +#define LPDDR4__DENALI_PHY_1351_WRITE_MASK 0x0F7F01FFU +#define LPDDR4__DENALI_PHY_1351__PHY_AC_LPBK_CONTROL_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_1351__PHY_AC_LPBK_CONTROL_SHIFT 0U +#define LPDDR4__DENALI_PHY_1351__PHY_AC_LPBK_CONTROL_WIDTH 9U +#define LPDDR4__PHY_AC_LPBK_CONTROL__REG DENALI_PHY_1351 +#define LPDDR4__PHY_AC_LPBK_CONTROL__FLD LPDDR4__DENALI_PHY_1351__PHY_AC_LPBK_CONTROL + +#define LPDDR4__DENALI_PHY_1351__PHY_AC_PRBS_PATTERN_START_MASK 0x007F0000U +#define LPDDR4__DENALI_PHY_1351__PHY_AC_PRBS_PATTERN_START_SHIFT 16U +#define LPDDR4__DENALI_PHY_1351__PHY_AC_PRBS_PATTERN_START_WIDTH 7U +#define LPDDR4__PHY_AC_PRBS_PATTERN_START__REG DENALI_PHY_1351 +#define LPDDR4__PHY_AC_PRBS_PATTERN_START__FLD LPDDR4__DENALI_PHY_1351__PHY_AC_PRBS_PATTERN_START + +#define LPDDR4__DENALI_PHY_1351__PHY_AC_PRBS_PATTERN_MASK_MASK 0x0F000000U +#define LPDDR4__DENALI_PHY_1351__PHY_AC_PRBS_PATTERN_MASK_SHIFT 24U +#define LPDDR4__DENALI_PHY_1351__PHY_AC_PRBS_PATTERN_MASK_WIDTH 4U +#define LPDDR4__PHY_AC_PRBS_PATTERN_MASK__REG DENALI_PHY_1351 +#define LPDDR4__PHY_AC_PRBS_PATTERN_MASK__FLD LPDDR4__DENALI_PHY_1351__PHY_AC_PRBS_PATTERN_MASK + +#define LPDDR4__DENALI_PHY_1352_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1352_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1352__PHY_AC_LPBK_RESULT_OBS_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1352__PHY_AC_LPBK_RESULT_OBS_SHIFT 0U +#define LPDDR4__DENALI_PHY_1352__PHY_AC_LPBK_RESULT_OBS_WIDTH 32U +#define LPDDR4__PHY_AC_LPBK_RESULT_OBS__REG DENALI_PHY_1352 +#define LPDDR4__PHY_AC_LPBK_RESULT_OBS__FLD LPDDR4__DENALI_PHY_1352__PHY_AC_LPBK_RESULT_OBS + +#define LPDDR4__DENALI_PHY_1353_READ_MASK 0x003F0101U +#define LPDDR4__DENALI_PHY_1353_WRITE_MASK 0x003F0101U +#define LPDDR4__DENALI_PHY_1353__PHY_AC_CLK_LPBK_OBS_SELECT_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_1353__PHY_AC_CLK_LPBK_OBS_SELECT_SHIFT 0U +#define LPDDR4__DENALI_PHY_1353__PHY_AC_CLK_LPBK_OBS_SELECT_WIDTH 1U +#define LPDDR4__DENALI_PHY_1353__PHY_AC_CLK_LPBK_OBS_SELECT_WOCLR 0U +#define LPDDR4__DENALI_PHY_1353__PHY_AC_CLK_LPBK_OBS_SELECT_WOSET 0U +#define LPDDR4__PHY_AC_CLK_LPBK_OBS_SELECT__REG DENALI_PHY_1353 +#define LPDDR4__PHY_AC_CLK_LPBK_OBS_SELECT__FLD LPDDR4__DENALI_PHY_1353__PHY_AC_CLK_LPBK_OBS_SELECT + +#define LPDDR4__DENALI_PHY_1353__PHY_AC_CLK_LPBK_ENABLE_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_1353__PHY_AC_CLK_LPBK_ENABLE_SHIFT 8U +#define LPDDR4__DENALI_PHY_1353__PHY_AC_CLK_LPBK_ENABLE_WIDTH 1U +#define LPDDR4__DENALI_PHY_1353__PHY_AC_CLK_LPBK_ENABLE_WOCLR 0U +#define LPDDR4__DENALI_PHY_1353__PHY_AC_CLK_LPBK_ENABLE_WOSET 0U +#define LPDDR4__PHY_AC_CLK_LPBK_ENABLE__REG DENALI_PHY_1353 +#define LPDDR4__PHY_AC_CLK_LPBK_ENABLE__FLD LPDDR4__DENALI_PHY_1353__PHY_AC_CLK_LPBK_ENABLE + +#define LPDDR4__DENALI_PHY_1353__PHY_AC_CLK_LPBK_CONTROL_MASK 0x003F0000U +#define LPDDR4__DENALI_PHY_1353__PHY_AC_CLK_LPBK_CONTROL_SHIFT 16U +#define LPDDR4__DENALI_PHY_1353__PHY_AC_CLK_LPBK_CONTROL_WIDTH 6U +#define LPDDR4__PHY_AC_CLK_LPBK_CONTROL__REG DENALI_PHY_1353 +#define LPDDR4__PHY_AC_CLK_LPBK_CONTROL__FLD LPDDR4__DENALI_PHY_1353__PHY_AC_CLK_LPBK_CONTROL + +#define LPDDR4__DENALI_PHY_1354_READ_MASK 0x0101FFFFU +#define LPDDR4__DENALI_PHY_1354_WRITE_MASK 0x0101FFFFU +#define LPDDR4__DENALI_PHY_1354__PHY_AC_CLK_LPBK_RESULT_OBS_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_1354__PHY_AC_CLK_LPBK_RESULT_OBS_SHIFT 0U +#define LPDDR4__DENALI_PHY_1354__PHY_AC_CLK_LPBK_RESULT_OBS_WIDTH 16U +#define LPDDR4__PHY_AC_CLK_LPBK_RESULT_OBS__REG DENALI_PHY_1354 +#define LPDDR4__PHY_AC_CLK_LPBK_RESULT_OBS__FLD LPDDR4__DENALI_PHY_1354__PHY_AC_CLK_LPBK_RESULT_OBS + +#define LPDDR4__DENALI_PHY_1354__PHY_AC_PWR_RDC_DISABLE_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_1354__PHY_AC_PWR_RDC_DISABLE_SHIFT 16U +#define LPDDR4__DENALI_PHY_1354__PHY_AC_PWR_RDC_DISABLE_WIDTH 1U +#define LPDDR4__DENALI_PHY_1354__PHY_AC_PWR_RDC_DISABLE_WOCLR 0U +#define LPDDR4__DENALI_PHY_1354__PHY_AC_PWR_RDC_DISABLE_WOSET 0U +#define LPDDR4__PHY_AC_PWR_RDC_DISABLE__REG DENALI_PHY_1354 +#define LPDDR4__PHY_AC_PWR_RDC_DISABLE__FLD LPDDR4__DENALI_PHY_1354__PHY_AC_PWR_RDC_DISABLE + +#define LPDDR4__DENALI_PHY_1354__PHY_TOP_PWR_RDC_DISABLE_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_1354__PHY_TOP_PWR_RDC_DISABLE_SHIFT 24U +#define LPDDR4__DENALI_PHY_1354__PHY_TOP_PWR_RDC_DISABLE_WIDTH 1U +#define LPDDR4__DENALI_PHY_1354__PHY_TOP_PWR_RDC_DISABLE_WOCLR 0U +#define LPDDR4__DENALI_PHY_1354__PHY_TOP_PWR_RDC_DISABLE_WOSET 0U +#define LPDDR4__PHY_TOP_PWR_RDC_DISABLE__REG DENALI_PHY_1354 +#define LPDDR4__PHY_TOP_PWR_RDC_DISABLE__FLD LPDDR4__DENALI_PHY_1354__PHY_TOP_PWR_RDC_DISABLE + +#define LPDDR4__DENALI_PHY_1355_READ_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_1355_WRITE_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_1355__PHY_AC_SLV_DLY_CTRL_GATE_DISABLE_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_1355__PHY_AC_SLV_DLY_CTRL_GATE_DISABLE_SHIFT 0U +#define LPDDR4__DENALI_PHY_1355__PHY_AC_SLV_DLY_CTRL_GATE_DISABLE_WIDTH 1U +#define LPDDR4__DENALI_PHY_1355__PHY_AC_SLV_DLY_CTRL_GATE_DISABLE_WOCLR 0U +#define LPDDR4__DENALI_PHY_1355__PHY_AC_SLV_DLY_CTRL_GATE_DISABLE_WOSET 0U +#define LPDDR4__PHY_AC_SLV_DLY_CTRL_GATE_DISABLE__REG DENALI_PHY_1355 +#define LPDDR4__PHY_AC_SLV_DLY_CTRL_GATE_DISABLE__FLD LPDDR4__DENALI_PHY_1355__PHY_AC_SLV_DLY_CTRL_GATE_DISABLE + +#define LPDDR4__DENALI_PHY_1356_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1356_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1356__PHY_DATA_BYTE_ORDER_SEL_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1356__PHY_DATA_BYTE_ORDER_SEL_SHIFT 0U +#define LPDDR4__DENALI_PHY_1356__PHY_DATA_BYTE_ORDER_SEL_WIDTH 32U +#define LPDDR4__PHY_DATA_BYTE_ORDER_SEL__REG DENALI_PHY_1356 +#define LPDDR4__PHY_DATA_BYTE_ORDER_SEL__FLD LPDDR4__DENALI_PHY_1356__PHY_DATA_BYTE_ORDER_SEL + +#define LPDDR4__DENALI_PHY_1357_READ_MASK 0x031F01FFU +#define LPDDR4__DENALI_PHY_1357_WRITE_MASK 0x031F01FFU +#define LPDDR4__DENALI_PHY_1357__PHY_DATA_BYTE_ORDER_SEL_HIGH_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_1357__PHY_DATA_BYTE_ORDER_SEL_HIGH_SHIFT 0U +#define LPDDR4__DENALI_PHY_1357__PHY_DATA_BYTE_ORDER_SEL_HIGH_WIDTH 8U +#define LPDDR4__PHY_DATA_BYTE_ORDER_SEL_HIGH__REG DENALI_PHY_1357 +#define LPDDR4__PHY_DATA_BYTE_ORDER_SEL_HIGH__FLD LPDDR4__DENALI_PHY_1357__PHY_DATA_BYTE_ORDER_SEL_HIGH + +#define LPDDR4__DENALI_PHY_1357__PHY_LPDDR4_CONNECT_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_1357__PHY_LPDDR4_CONNECT_SHIFT 8U +#define LPDDR4__DENALI_PHY_1357__PHY_LPDDR4_CONNECT_WIDTH 1U +#define LPDDR4__DENALI_PHY_1357__PHY_LPDDR4_CONNECT_WOCLR 0U +#define LPDDR4__DENALI_PHY_1357__PHY_LPDDR4_CONNECT_WOSET 0U +#define LPDDR4__PHY_LPDDR4_CONNECT__REG DENALI_PHY_1357 +#define LPDDR4__PHY_LPDDR4_CONNECT__FLD LPDDR4__DENALI_PHY_1357__PHY_LPDDR4_CONNECT + +#define LPDDR4__DENALI_PHY_1357__PHY_CALVL_DEVICE_MAP_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_1357__PHY_CALVL_DEVICE_MAP_SHIFT 16U +#define LPDDR4__DENALI_PHY_1357__PHY_CALVL_DEVICE_MAP_WIDTH 5U +#define LPDDR4__PHY_CALVL_DEVICE_MAP__REG DENALI_PHY_1357 +#define LPDDR4__PHY_CALVL_DEVICE_MAP__FLD LPDDR4__DENALI_PHY_1357__PHY_CALVL_DEVICE_MAP + +#define LPDDR4__DENALI_PHY_1357__PHY_ADRCTL_MSTR_DLY_ENC_SEL_0_MASK 0x03000000U +#define LPDDR4__DENALI_PHY_1357__PHY_ADRCTL_MSTR_DLY_ENC_SEL_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_1357__PHY_ADRCTL_MSTR_DLY_ENC_SEL_0_WIDTH 2U +#define LPDDR4__PHY_ADRCTL_MSTR_DLY_ENC_SEL_0__REG DENALI_PHY_1357 +#define LPDDR4__PHY_ADRCTL_MSTR_DLY_ENC_SEL_0__FLD LPDDR4__DENALI_PHY_1357__PHY_ADRCTL_MSTR_DLY_ENC_SEL_0 + +#define LPDDR4__DENALI_PHY_1358_READ_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_1358_WRITE_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_1358__PHY_ADRCTL_MSTR_DLY_ENC_SEL_1_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_1358__PHY_ADRCTL_MSTR_DLY_ENC_SEL_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_1358__PHY_ADRCTL_MSTR_DLY_ENC_SEL_1_WIDTH 2U +#define LPDDR4__PHY_ADRCTL_MSTR_DLY_ENC_SEL_1__REG DENALI_PHY_1358 +#define LPDDR4__PHY_ADRCTL_MSTR_DLY_ENC_SEL_1__FLD LPDDR4__DENALI_PHY_1358__PHY_ADRCTL_MSTR_DLY_ENC_SEL_1 + +#define LPDDR4__DENALI_PHY_1359_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1359_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1359__PHY_DDL_AC_ENABLE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1359__PHY_DDL_AC_ENABLE_SHIFT 0U +#define LPDDR4__DENALI_PHY_1359__PHY_DDL_AC_ENABLE_WIDTH 32U +#define LPDDR4__PHY_DDL_AC_ENABLE__REG DENALI_PHY_1359 +#define LPDDR4__PHY_DDL_AC_ENABLE__FLD LPDDR4__DENALI_PHY_1359__PHY_DDL_AC_ENABLE + +#define LPDDR4__DENALI_PHY_1360_READ_MASK 0x03FFFFFFU +#define LPDDR4__DENALI_PHY_1360_WRITE_MASK 0x03FFFFFFU +#define LPDDR4__DENALI_PHY_1360__PHY_DDL_AC_MODE_MASK 0x03FFFFFFU +#define LPDDR4__DENALI_PHY_1360__PHY_DDL_AC_MODE_SHIFT 0U +#define LPDDR4__DENALI_PHY_1360__PHY_DDL_AC_MODE_WIDTH 26U +#define LPDDR4__PHY_DDL_AC_MODE__REG DENALI_PHY_1360 +#define LPDDR4__PHY_DDL_AC_MODE__FLD LPDDR4__DENALI_PHY_1360__PHY_DDL_AC_MODE + +#define LPDDR4__DENALI_PHY_1361_READ_MASK 0x07FF073FU +#define LPDDR4__DENALI_PHY_1361_WRITE_MASK 0x07FF073FU +#define LPDDR4__DENALI_PHY_1361__PHY_DDL_AC_MASK_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_1361__PHY_DDL_AC_MASK_SHIFT 0U +#define LPDDR4__DENALI_PHY_1361__PHY_DDL_AC_MASK_WIDTH 6U +#define LPDDR4__PHY_DDL_AC_MASK__REG DENALI_PHY_1361 +#define LPDDR4__PHY_DDL_AC_MASK__FLD LPDDR4__DENALI_PHY_1361__PHY_DDL_AC_MASK + +#define LPDDR4__DENALI_PHY_1361__PHY_INIT_UPDATE_CONFIG_MASK 0x00000700U +#define LPDDR4__DENALI_PHY_1361__PHY_INIT_UPDATE_CONFIG_SHIFT 8U +#define LPDDR4__DENALI_PHY_1361__PHY_INIT_UPDATE_CONFIG_WIDTH 3U +#define LPDDR4__PHY_INIT_UPDATE_CONFIG__REG DENALI_PHY_1361 +#define LPDDR4__PHY_INIT_UPDATE_CONFIG__FLD LPDDR4__DENALI_PHY_1361__PHY_INIT_UPDATE_CONFIG + +#define LPDDR4__DENALI_PHY_1361__PHY_DDL_TRACK_UPD_THRESHOLD_AC_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_1361__PHY_DDL_TRACK_UPD_THRESHOLD_AC_SHIFT 16U +#define LPDDR4__DENALI_PHY_1361__PHY_DDL_TRACK_UPD_THRESHOLD_AC_WIDTH 8U +#define LPDDR4__PHY_DDL_TRACK_UPD_THRESHOLD_AC__REG DENALI_PHY_1361 +#define LPDDR4__PHY_DDL_TRACK_UPD_THRESHOLD_AC__FLD LPDDR4__DENALI_PHY_1361__PHY_DDL_TRACK_UPD_THRESHOLD_AC + +#define LPDDR4__DENALI_PHY_1361__PHY_ERR_MASK_EN_MASK 0x07000000U +#define LPDDR4__DENALI_PHY_1361__PHY_ERR_MASK_EN_SHIFT 24U +#define LPDDR4__DENALI_PHY_1361__PHY_ERR_MASK_EN_WIDTH 3U +#define LPDDR4__PHY_ERR_MASK_EN__REG DENALI_PHY_1361 +#define LPDDR4__PHY_ERR_MASK_EN__FLD LPDDR4__DENALI_PHY_1361__PHY_ERR_MASK_EN + +#define LPDDR4__DENALI_PHY_1362_READ_MASK 0x00000007U +#define LPDDR4__DENALI_PHY_1362_WRITE_MASK 0x00000007U +#define LPDDR4__DENALI_PHY_1362__PHY_ERR_STATUS_MASK 0x00000007U +#define LPDDR4__DENALI_PHY_1362__PHY_ERR_STATUS_SHIFT 0U +#define LPDDR4__DENALI_PHY_1362__PHY_ERR_STATUS_WIDTH 3U +#define LPDDR4__PHY_ERR_STATUS__REG DENALI_PHY_1362 +#define LPDDR4__PHY_ERR_STATUS__FLD LPDDR4__DENALI_PHY_1362__PHY_ERR_STATUS + +#define LPDDR4__DENALI_PHY_1363_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1363_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1363__PHY_DS0_DQS_ERR_COUNTER_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1363__PHY_DS0_DQS_ERR_COUNTER_SHIFT 0U +#define LPDDR4__DENALI_PHY_1363__PHY_DS0_DQS_ERR_COUNTER_WIDTH 32U +#define LPDDR4__PHY_DS0_DQS_ERR_COUNTER__REG DENALI_PHY_1363 +#define LPDDR4__PHY_DS0_DQS_ERR_COUNTER__FLD LPDDR4__DENALI_PHY_1363__PHY_DS0_DQS_ERR_COUNTER + +#define LPDDR4__DENALI_PHY_1364_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1364_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1364__PHY_DS1_DQS_ERR_COUNTER_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1364__PHY_DS1_DQS_ERR_COUNTER_SHIFT 0U +#define LPDDR4__DENALI_PHY_1364__PHY_DS1_DQS_ERR_COUNTER_WIDTH 32U +#define LPDDR4__PHY_DS1_DQS_ERR_COUNTER__REG DENALI_PHY_1364 +#define LPDDR4__PHY_DS1_DQS_ERR_COUNTER__FLD LPDDR4__DENALI_PHY_1364__PHY_DS1_DQS_ERR_COUNTER + +#define LPDDR4__DENALI_PHY_1365_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1365_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1365__PHY_DS2_DQS_ERR_COUNTER_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1365__PHY_DS2_DQS_ERR_COUNTER_SHIFT 0U +#define LPDDR4__DENALI_PHY_1365__PHY_DS2_DQS_ERR_COUNTER_WIDTH 32U +#define LPDDR4__PHY_DS2_DQS_ERR_COUNTER__REG DENALI_PHY_1365 +#define LPDDR4__PHY_DS2_DQS_ERR_COUNTER__FLD LPDDR4__DENALI_PHY_1365__PHY_DS2_DQS_ERR_COUNTER + +#define LPDDR4__DENALI_PHY_1366_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1366_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1366__PHY_DS3_DQS_ERR_COUNTER_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1366__PHY_DS3_DQS_ERR_COUNTER_SHIFT 0U +#define LPDDR4__DENALI_PHY_1366__PHY_DS3_DQS_ERR_COUNTER_WIDTH 32U +#define LPDDR4__PHY_DS3_DQS_ERR_COUNTER__REG DENALI_PHY_1366 +#define LPDDR4__PHY_DS3_DQS_ERR_COUNTER__FLD LPDDR4__DENALI_PHY_1366__PHY_DS3_DQS_ERR_COUNTER + +#define LPDDR4__DENALI_PHY_1367_READ_MASK 0x0F03FF03U +#define LPDDR4__DENALI_PHY_1367_WRITE_MASK 0x0F03FF03U +#define LPDDR4__DENALI_PHY_1367__PHY_DLL_RST_EN_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_1367__PHY_DLL_RST_EN_SHIFT 0U +#define LPDDR4__DENALI_PHY_1367__PHY_DLL_RST_EN_WIDTH 2U +#define LPDDR4__PHY_DLL_RST_EN__REG DENALI_PHY_1367 +#define LPDDR4__PHY_DLL_RST_EN__FLD LPDDR4__DENALI_PHY_1367__PHY_DLL_RST_EN + +#define LPDDR4__DENALI_PHY_1367__PHY_AC_INIT_COMPLETE_OBS_MASK 0x0003FF00U +#define LPDDR4__DENALI_PHY_1367__PHY_AC_INIT_COMPLETE_OBS_SHIFT 8U +#define LPDDR4__DENALI_PHY_1367__PHY_AC_INIT_COMPLETE_OBS_WIDTH 10U +#define LPDDR4__PHY_AC_INIT_COMPLETE_OBS__REG DENALI_PHY_1367 +#define LPDDR4__PHY_AC_INIT_COMPLETE_OBS__FLD LPDDR4__DENALI_PHY_1367__PHY_AC_INIT_COMPLETE_OBS + +#define LPDDR4__DENALI_PHY_1367__PHY_DS_INIT_COMPLETE_OBS_MASK 0x0F000000U +#define LPDDR4__DENALI_PHY_1367__PHY_DS_INIT_COMPLETE_OBS_SHIFT 24U +#define LPDDR4__DENALI_PHY_1367__PHY_DS_INIT_COMPLETE_OBS_WIDTH 4U +#define LPDDR4__PHY_DS_INIT_COMPLETE_OBS__REG DENALI_PHY_1367 +#define LPDDR4__PHY_DS_INIT_COMPLETE_OBS__FLD LPDDR4__DENALI_PHY_1367__PHY_DS_INIT_COMPLETE_OBS + +#define LPDDR4__DENALI_PHY_1368_READ_MASK 0x070F0101U +#define LPDDR4__DENALI_PHY_1368_WRITE_MASK 0x070F0101U +#define LPDDR4__DENALI_PHY_1368__PHY_UPDATE_MASK_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_1368__PHY_UPDATE_MASK_SHIFT 0U +#define LPDDR4__DENALI_PHY_1368__PHY_UPDATE_MASK_WIDTH 1U +#define LPDDR4__DENALI_PHY_1368__PHY_UPDATE_MASK_WOCLR 0U +#define LPDDR4__DENALI_PHY_1368__PHY_UPDATE_MASK_WOSET 0U +#define LPDDR4__PHY_UPDATE_MASK__REG DENALI_PHY_1368 +#define LPDDR4__PHY_UPDATE_MASK__FLD LPDDR4__DENALI_PHY_1368__PHY_UPDATE_MASK + +#define LPDDR4__DENALI_PHY_1368__PHY_AC_DCC_RXCAL_CTRL_GATE_DISABLE_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_1368__PHY_AC_DCC_RXCAL_CTRL_GATE_DISABLE_SHIFT 8U +#define LPDDR4__DENALI_PHY_1368__PHY_AC_DCC_RXCAL_CTRL_GATE_DISABLE_WIDTH 1U +#define LPDDR4__DENALI_PHY_1368__PHY_AC_DCC_RXCAL_CTRL_GATE_DISABLE_WOCLR 0U +#define LPDDR4__DENALI_PHY_1368__PHY_AC_DCC_RXCAL_CTRL_GATE_DISABLE_WOSET 0U +#define LPDDR4__PHY_AC_DCC_RXCAL_CTRL_GATE_DISABLE__REG DENALI_PHY_1368 +#define LPDDR4__PHY_AC_DCC_RXCAL_CTRL_GATE_DISABLE__FLD LPDDR4__DENALI_PHY_1368__PHY_AC_DCC_RXCAL_CTRL_GATE_DISABLE + +#define LPDDR4__DENALI_PHY_1368__PHY_GRP_SLV_DLY_ENC_OBS_SELECT_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_1368__PHY_GRP_SLV_DLY_ENC_OBS_SELECT_SHIFT 16U +#define LPDDR4__DENALI_PHY_1368__PHY_GRP_SLV_DLY_ENC_OBS_SELECT_WIDTH 4U +#define LPDDR4__PHY_GRP_SLV_DLY_ENC_OBS_SELECT__REG DENALI_PHY_1368 +#define LPDDR4__PHY_GRP_SLV_DLY_ENC_OBS_SELECT__FLD LPDDR4__DENALI_PHY_1368__PHY_GRP_SLV_DLY_ENC_OBS_SELECT + +#define LPDDR4__DENALI_PHY_1368__PHY_GRP_SHIFT_OBS_SELECT_MASK 0x07000000U +#define LPDDR4__DENALI_PHY_1368__PHY_GRP_SHIFT_OBS_SELECT_SHIFT 24U +#define LPDDR4__DENALI_PHY_1368__PHY_GRP_SHIFT_OBS_SELECT_WIDTH 3U +#define LPDDR4__PHY_GRP_SHIFT_OBS_SELECT__REG DENALI_PHY_1368 +#define LPDDR4__PHY_GRP_SHIFT_OBS_SELECT__FLD LPDDR4__DENALI_PHY_1368__PHY_GRP_SHIFT_OBS_SELECT + +#define LPDDR4__DENALI_PHY_1369_READ_MASK 0x000707FFU +#define LPDDR4__DENALI_PHY_1369_WRITE_MASK 0x000707FFU +#define LPDDR4__DENALI_PHY_1369__PHY_GRP_SLV_DLY_ENC_OBS_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1369__PHY_GRP_SLV_DLY_ENC_OBS_SHIFT 0U +#define LPDDR4__DENALI_PHY_1369__PHY_GRP_SLV_DLY_ENC_OBS_WIDTH 11U +#define LPDDR4__PHY_GRP_SLV_DLY_ENC_OBS__REG DENALI_PHY_1369 +#define LPDDR4__PHY_GRP_SLV_DLY_ENC_OBS__FLD LPDDR4__DENALI_PHY_1369__PHY_GRP_SLV_DLY_ENC_OBS + +#define LPDDR4__DENALI_PHY_1369__PHY_GRP_SHIFT_OBS_MASK 0x00070000U +#define LPDDR4__DENALI_PHY_1369__PHY_GRP_SHIFT_OBS_SHIFT 16U +#define LPDDR4__DENALI_PHY_1369__PHY_GRP_SHIFT_OBS_WIDTH 3U +#define LPDDR4__PHY_GRP_SHIFT_OBS__REG DENALI_PHY_1369 +#define LPDDR4__PHY_GRP_SHIFT_OBS__FLD LPDDR4__DENALI_PHY_1369__PHY_GRP_SHIFT_OBS + +#define LPDDR4__DENALI_PHY_1370_READ_MASK 0x0707FF01U +#define LPDDR4__DENALI_PHY_1370_WRITE_MASK 0x0707FF01U +#define LPDDR4__DENALI_PHY_1370__PHY_PARITY_ERROR_INJECTION_ENABLE_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_1370__PHY_PARITY_ERROR_INJECTION_ENABLE_SHIFT 0U +#define LPDDR4__DENALI_PHY_1370__PHY_PARITY_ERROR_INJECTION_ENABLE_WIDTH 1U +#define LPDDR4__DENALI_PHY_1370__PHY_PARITY_ERROR_INJECTION_ENABLE_WOCLR 0U +#define LPDDR4__DENALI_PHY_1370__PHY_PARITY_ERROR_INJECTION_ENABLE_WOSET 0U +#define LPDDR4__PHY_PARITY_ERROR_INJECTION_ENABLE__REG DENALI_PHY_1370 +#define LPDDR4__PHY_PARITY_ERROR_INJECTION_ENABLE__FLD LPDDR4__DENALI_PHY_1370__PHY_PARITY_ERROR_INJECTION_ENABLE + +#define LPDDR4__DENALI_PHY_1370__PHY_PARITY_ERROR_REGIF_PS_MASK 0x0007FF00U +#define LPDDR4__DENALI_PHY_1370__PHY_PARITY_ERROR_REGIF_PS_SHIFT 8U +#define LPDDR4__DENALI_PHY_1370__PHY_PARITY_ERROR_REGIF_PS_WIDTH 11U +#define LPDDR4__PHY_PARITY_ERROR_REGIF_PS__REG DENALI_PHY_1370 +#define LPDDR4__PHY_PARITY_ERROR_REGIF_PS__FLD LPDDR4__DENALI_PHY_1370__PHY_PARITY_ERROR_REGIF_PS + +#define LPDDR4__DENALI_PHY_1370__PHY_PLL_LOCK_DEASSERT_MASK_MASK 0x07000000U +#define LPDDR4__DENALI_PHY_1370__PHY_PLL_LOCK_DEASSERT_MASK_SHIFT 24U +#define LPDDR4__DENALI_PHY_1370__PHY_PLL_LOCK_DEASSERT_MASK_WIDTH 3U +#define LPDDR4__PHY_PLL_LOCK_DEASSERT_MASK__REG DENALI_PHY_1370 +#define LPDDR4__PHY_PLL_LOCK_DEASSERT_MASK__FLD LPDDR4__DENALI_PHY_1370__PHY_PLL_LOCK_DEASSERT_MASK + +#define LPDDR4__DENALI_PHY_1371_READ_MASK 0x00007F7FU +#define LPDDR4__DENALI_PHY_1371_WRITE_MASK 0x00007F7FU +#define LPDDR4__DENALI_PHY_1371__PHY_PARITY_ERROR_INFO_MASK 0x0000007FU +#define LPDDR4__DENALI_PHY_1371__PHY_PARITY_ERROR_INFO_SHIFT 0U +#define LPDDR4__DENALI_PHY_1371__PHY_PARITY_ERROR_INFO_WIDTH 7U +#define LPDDR4__PHY_PARITY_ERROR_INFO__REG DENALI_PHY_1371 +#define LPDDR4__PHY_PARITY_ERROR_INFO__FLD LPDDR4__DENALI_PHY_1371__PHY_PARITY_ERROR_INFO + +#define LPDDR4__DENALI_PHY_1371__PHY_PARITY_ERROR_INFO_MASK_MASK 0x00007F00U +#define LPDDR4__DENALI_PHY_1371__PHY_PARITY_ERROR_INFO_MASK_SHIFT 8U +#define LPDDR4__DENALI_PHY_1371__PHY_PARITY_ERROR_INFO_MASK_WIDTH 7U +#define LPDDR4__PHY_PARITY_ERROR_INFO_MASK__REG DENALI_PHY_1371 +#define LPDDR4__PHY_PARITY_ERROR_INFO_MASK__FLD LPDDR4__DENALI_PHY_1371__PHY_PARITY_ERROR_INFO_MASK + +#define LPDDR4__DENALI_PHY_1371__SC_PHY_PARITY_ERROR_INFO_WOCLR_MASK 0x007F0000U +#define LPDDR4__DENALI_PHY_1371__SC_PHY_PARITY_ERROR_INFO_WOCLR_SHIFT 16U +#define LPDDR4__DENALI_PHY_1371__SC_PHY_PARITY_ERROR_INFO_WOCLR_WIDTH 7U +#define LPDDR4__SC_PHY_PARITY_ERROR_INFO_WOCLR__REG DENALI_PHY_1371 +#define LPDDR4__SC_PHY_PARITY_ERROR_INFO_WOCLR__FLD LPDDR4__DENALI_PHY_1371__SC_PHY_PARITY_ERROR_INFO_WOCLR + +#define LPDDR4__DENALI_PHY_1372_READ_MASK 0x3FFF3FFFU +#define LPDDR4__DENALI_PHY_1372_WRITE_MASK 0x3FFF3FFFU +#define LPDDR4__DENALI_PHY_1372__PHY_TIMEOUT_ERROR_INFO_MASK 0x00003FFFU +#define LPDDR4__DENALI_PHY_1372__PHY_TIMEOUT_ERROR_INFO_SHIFT 0U +#define LPDDR4__DENALI_PHY_1372__PHY_TIMEOUT_ERROR_INFO_WIDTH 14U +#define LPDDR4__PHY_TIMEOUT_ERROR_INFO__REG DENALI_PHY_1372 +#define LPDDR4__PHY_TIMEOUT_ERROR_INFO__FLD LPDDR4__DENALI_PHY_1372__PHY_TIMEOUT_ERROR_INFO + +#define LPDDR4__DENALI_PHY_1372__PHY_TIMEOUT_ERROR_INFO_MASK_MASK 0x3FFF0000U +#define LPDDR4__DENALI_PHY_1372__PHY_TIMEOUT_ERROR_INFO_MASK_SHIFT 16U +#define LPDDR4__DENALI_PHY_1372__PHY_TIMEOUT_ERROR_INFO_MASK_WIDTH 14U +#define LPDDR4__PHY_TIMEOUT_ERROR_INFO_MASK__REG DENALI_PHY_1372 +#define LPDDR4__PHY_TIMEOUT_ERROR_INFO_MASK__FLD LPDDR4__DENALI_PHY_1372__PHY_TIMEOUT_ERROR_INFO_MASK + +#define LPDDR4__DENALI_PHY_1373_READ_MASK 0x3F0F0000U +#define LPDDR4__DENALI_PHY_1373_WRITE_MASK 0x3F0F0000U +#define LPDDR4__DENALI_PHY_1373__SC_PHY_TIMEOUT_ERROR_INFO_WOCLR_MASK 0x00003FFFU +#define LPDDR4__DENALI_PHY_1373__SC_PHY_TIMEOUT_ERROR_INFO_WOCLR_SHIFT 0U +#define LPDDR4__DENALI_PHY_1373__SC_PHY_TIMEOUT_ERROR_INFO_WOCLR_WIDTH 14U +#define LPDDR4__SC_PHY_TIMEOUT_ERROR_INFO_WOCLR__REG DENALI_PHY_1373 +#define LPDDR4__SC_PHY_TIMEOUT_ERROR_INFO_WOCLR__FLD LPDDR4__DENALI_PHY_1373__SC_PHY_TIMEOUT_ERROR_INFO_WOCLR + +#define LPDDR4__DENALI_PHY_1373__PHY_PLL_FREQUENCY_ERROR_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_1373__PHY_PLL_FREQUENCY_ERROR_SHIFT 16U +#define LPDDR4__DENALI_PHY_1373__PHY_PLL_FREQUENCY_ERROR_WIDTH 4U +#define LPDDR4__PHY_PLL_FREQUENCY_ERROR__REG DENALI_PHY_1373 +#define LPDDR4__PHY_PLL_FREQUENCY_ERROR__FLD LPDDR4__DENALI_PHY_1373__PHY_PLL_FREQUENCY_ERROR + +#define LPDDR4__DENALI_PHY_1373__PHY_PLL_FREQUENCY_ERROR_MASK_MASK 0x3F000000U +#define LPDDR4__DENALI_PHY_1373__PHY_PLL_FREQUENCY_ERROR_MASK_SHIFT 24U +#define LPDDR4__DENALI_PHY_1373__PHY_PLL_FREQUENCY_ERROR_MASK_WIDTH 6U +#define LPDDR4__PHY_PLL_FREQUENCY_ERROR_MASK__REG DENALI_PHY_1373 +#define LPDDR4__PHY_PLL_FREQUENCY_ERROR_MASK__FLD LPDDR4__DENALI_PHY_1373__PHY_PLL_FREQUENCY_ERROR_MASK + +#define LPDDR4__DENALI_PHY_1374_READ_MASK 0x000FFF00U +#define LPDDR4__DENALI_PHY_1374_WRITE_MASK 0x000FFF00U +#define LPDDR4__DENALI_PHY_1374__SC_PHY_PLL_FREQUENCY_ERROR_WOCLR_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_1374__SC_PHY_PLL_FREQUENCY_ERROR_WOCLR_SHIFT 0U +#define LPDDR4__DENALI_PHY_1374__SC_PHY_PLL_FREQUENCY_ERROR_WOCLR_WIDTH 6U +#define LPDDR4__SC_PHY_PLL_FREQUENCY_ERROR_WOCLR__REG DENALI_PHY_1374 +#define LPDDR4__SC_PHY_PLL_FREQUENCY_ERROR_WOCLR__FLD LPDDR4__DENALI_PHY_1374__SC_PHY_PLL_FREQUENCY_ERROR_WOCLR + +#define LPDDR4__DENALI_PHY_1374__PHY_PLL_DSKEWCALOUT_MIN_MASK 0x000FFF00U +#define LPDDR4__DENALI_PHY_1374__PHY_PLL_DSKEWCALOUT_MIN_SHIFT 8U +#define LPDDR4__DENALI_PHY_1374__PHY_PLL_DSKEWCALOUT_MIN_WIDTH 12U +#define LPDDR4__PHY_PLL_DSKEWCALOUT_MIN__REG DENALI_PHY_1374 +#define LPDDR4__PHY_PLL_DSKEWCALOUT_MIN__FLD LPDDR4__DENALI_PHY_1374__PHY_PLL_DSKEWCALOUT_MIN + +#define LPDDR4__DENALI_PHY_1375_READ_MASK 0x03030FFFU +#define LPDDR4__DENALI_PHY_1375_WRITE_MASK 0x03030FFFU +#define LPDDR4__DENALI_PHY_1375__PHY_PLL_DSKEWCALOUT_MAX_MASK 0x00000FFFU +#define LPDDR4__DENALI_PHY_1375__PHY_PLL_DSKEWCALOUT_MAX_SHIFT 0U +#define LPDDR4__DENALI_PHY_1375__PHY_PLL_DSKEWCALOUT_MAX_WIDTH 12U +#define LPDDR4__PHY_PLL_DSKEWCALOUT_MAX__REG DENALI_PHY_1375 +#define LPDDR4__PHY_PLL_DSKEWCALOUT_MAX__FLD LPDDR4__DENALI_PHY_1375__PHY_PLL_DSKEWCALOUT_MAX + +#define LPDDR4__DENALI_PHY_1375__PHY_PLL_DSKEWCALOUT_ERROR_INFO_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_1375__PHY_PLL_DSKEWCALOUT_ERROR_INFO_SHIFT 16U +#define LPDDR4__DENALI_PHY_1375__PHY_PLL_DSKEWCALOUT_ERROR_INFO_WIDTH 2U +#define LPDDR4__PHY_PLL_DSKEWCALOUT_ERROR_INFO__REG DENALI_PHY_1375 +#define LPDDR4__PHY_PLL_DSKEWCALOUT_ERROR_INFO__FLD LPDDR4__DENALI_PHY_1375__PHY_PLL_DSKEWCALOUT_ERROR_INFO + +#define LPDDR4__DENALI_PHY_1375__PHY_PLL_DSKEWCALOUT_ERROR_INFO_MASK_MASK 0x03000000U +#define LPDDR4__DENALI_PHY_1375__PHY_PLL_DSKEWCALOUT_ERROR_INFO_MASK_SHIFT 24U +#define LPDDR4__DENALI_PHY_1375__PHY_PLL_DSKEWCALOUT_ERROR_INFO_MASK_WIDTH 2U +#define LPDDR4__PHY_PLL_DSKEWCALOUT_ERROR_INFO_MASK__REG DENALI_PHY_1375 +#define LPDDR4__PHY_PLL_DSKEWCALOUT_ERROR_INFO_MASK__FLD LPDDR4__DENALI_PHY_1375__PHY_PLL_DSKEWCALOUT_ERROR_INFO_MASK + +#define LPDDR4__DENALI_PHY_1376_READ_MASK 0x0001FF00U +#define LPDDR4__DENALI_PHY_1376_WRITE_MASK 0x0001FF00U +#define LPDDR4__DENALI_PHY_1376__SC_PHY_PLL_DSKEWCALOUT_ERROR_INFO_WOCLR_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_1376__SC_PHY_PLL_DSKEWCALOUT_ERROR_INFO_WOCLR_SHIFT 0U +#define LPDDR4__DENALI_PHY_1376__SC_PHY_PLL_DSKEWCALOUT_ERROR_INFO_WOCLR_WIDTH 2U +#define LPDDR4__SC_PHY_PLL_DSKEWCALOUT_ERROR_INFO_WOCLR__REG DENALI_PHY_1376 +#define LPDDR4__SC_PHY_PLL_DSKEWCALOUT_ERROR_INFO_WOCLR__FLD LPDDR4__DENALI_PHY_1376__SC_PHY_PLL_DSKEWCALOUT_ERROR_INFO_WOCLR + +#define LPDDR4__DENALI_PHY_1376__PHY_TOP_FSM_ERROR_INFO_MASK 0x0001FF00U +#define LPDDR4__DENALI_PHY_1376__PHY_TOP_FSM_ERROR_INFO_SHIFT 8U +#define LPDDR4__DENALI_PHY_1376__PHY_TOP_FSM_ERROR_INFO_WIDTH 9U +#define LPDDR4__PHY_TOP_FSM_ERROR_INFO__REG DENALI_PHY_1376 +#define LPDDR4__PHY_TOP_FSM_ERROR_INFO__FLD LPDDR4__DENALI_PHY_1376__PHY_TOP_FSM_ERROR_INFO + +#define LPDDR4__DENALI_PHY_1377_READ_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_1377_WRITE_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_1377__PHY_TOP_FSM_ERROR_INFO_MASK_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_1377__PHY_TOP_FSM_ERROR_INFO_MASK_SHIFT 0U +#define LPDDR4__DENALI_PHY_1377__PHY_TOP_FSM_ERROR_INFO_MASK_WIDTH 9U +#define LPDDR4__PHY_TOP_FSM_ERROR_INFO_MASK__REG DENALI_PHY_1377 +#define LPDDR4__PHY_TOP_FSM_ERROR_INFO_MASK__FLD LPDDR4__DENALI_PHY_1377__PHY_TOP_FSM_ERROR_INFO_MASK + +#define LPDDR4__DENALI_PHY_1377__SC_PHY_TOP_FSM_ERROR_INFO_WOCLR_MASK 0x01FF0000U +#define LPDDR4__DENALI_PHY_1377__SC_PHY_TOP_FSM_ERROR_INFO_WOCLR_SHIFT 16U +#define LPDDR4__DENALI_PHY_1377__SC_PHY_TOP_FSM_ERROR_INFO_WOCLR_WIDTH 9U +#define LPDDR4__SC_PHY_TOP_FSM_ERROR_INFO_WOCLR__REG DENALI_PHY_1377 +#define LPDDR4__SC_PHY_TOP_FSM_ERROR_INFO_WOCLR__FLD LPDDR4__DENALI_PHY_1377__SC_PHY_TOP_FSM_ERROR_INFO_WOCLR + +#define LPDDR4__DENALI_PHY_1378_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_1378_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_1378__PHY_FSM_TRANSIENT_ERROR_INFO_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_1378__PHY_FSM_TRANSIENT_ERROR_INFO_SHIFT 0U +#define LPDDR4__DENALI_PHY_1378__PHY_FSM_TRANSIENT_ERROR_INFO_WIDTH 10U +#define LPDDR4__PHY_FSM_TRANSIENT_ERROR_INFO__REG DENALI_PHY_1378 +#define LPDDR4__PHY_FSM_TRANSIENT_ERROR_INFO__FLD LPDDR4__DENALI_PHY_1378__PHY_FSM_TRANSIENT_ERROR_INFO + +#define LPDDR4__DENALI_PHY_1378__PHY_FSM_TRANSIENT_ERROR_INFO_MASK_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_1378__PHY_FSM_TRANSIENT_ERROR_INFO_MASK_SHIFT 16U +#define LPDDR4__DENALI_PHY_1378__PHY_FSM_TRANSIENT_ERROR_INFO_MASK_WIDTH 10U +#define LPDDR4__PHY_FSM_TRANSIENT_ERROR_INFO_MASK__REG DENALI_PHY_1378 +#define LPDDR4__PHY_FSM_TRANSIENT_ERROR_INFO_MASK__FLD LPDDR4__DENALI_PHY_1378__PHY_FSM_TRANSIENT_ERROR_INFO_MASK + +#define LPDDR4__DENALI_PHY_1379_READ_MASK 0x03030000U +#define LPDDR4__DENALI_PHY_1379_WRITE_MASK 0x03030000U +#define LPDDR4__DENALI_PHY_1379__SC_PHY_FSM_TRANSIENT_ERROR_INFO_WOCLR_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_1379__SC_PHY_FSM_TRANSIENT_ERROR_INFO_WOCLR_SHIFT 0U +#define LPDDR4__DENALI_PHY_1379__SC_PHY_FSM_TRANSIENT_ERROR_INFO_WOCLR_WIDTH 10U +#define LPDDR4__SC_PHY_FSM_TRANSIENT_ERROR_INFO_WOCLR__REG DENALI_PHY_1379 +#define LPDDR4__SC_PHY_FSM_TRANSIENT_ERROR_INFO_WOCLR__FLD LPDDR4__DENALI_PHY_1379__SC_PHY_FSM_TRANSIENT_ERROR_INFO_WOCLR + +#define LPDDR4__DENALI_PHY_1379__PHY_TOP_TRAIN_CALIB_ERROR_INFO_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_1379__PHY_TOP_TRAIN_CALIB_ERROR_INFO_SHIFT 16U +#define LPDDR4__DENALI_PHY_1379__PHY_TOP_TRAIN_CALIB_ERROR_INFO_WIDTH 2U +#define LPDDR4__PHY_TOP_TRAIN_CALIB_ERROR_INFO__REG DENALI_PHY_1379 +#define LPDDR4__PHY_TOP_TRAIN_CALIB_ERROR_INFO__FLD LPDDR4__DENALI_PHY_1379__PHY_TOP_TRAIN_CALIB_ERROR_INFO + +#define LPDDR4__DENALI_PHY_1379__PHY_TOP_TRAIN_CALIB_ERROR_INFO_MASK_MASK 0x03000000U +#define LPDDR4__DENALI_PHY_1379__PHY_TOP_TRAIN_CALIB_ERROR_INFO_MASK_SHIFT 24U +#define LPDDR4__DENALI_PHY_1379__PHY_TOP_TRAIN_CALIB_ERROR_INFO_MASK_WIDTH 2U +#define LPDDR4__PHY_TOP_TRAIN_CALIB_ERROR_INFO_MASK__REG DENALI_PHY_1379 +#define LPDDR4__PHY_TOP_TRAIN_CALIB_ERROR_INFO_MASK__FLD LPDDR4__DENALI_PHY_1379__PHY_TOP_TRAIN_CALIB_ERROR_INFO_MASK + +#define LPDDR4__DENALI_PHY_1380_READ_MASK 0x007F7F00U +#define LPDDR4__DENALI_PHY_1380_WRITE_MASK 0x007F7F00U +#define LPDDR4__DENALI_PHY_1380__SC_PHY_TOP_TRAIN_CALIB_ERROR_INFO_WOCLR_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_1380__SC_PHY_TOP_TRAIN_CALIB_ERROR_INFO_WOCLR_SHIFT 0U +#define LPDDR4__DENALI_PHY_1380__SC_PHY_TOP_TRAIN_CALIB_ERROR_INFO_WOCLR_WIDTH 2U +#define LPDDR4__SC_PHY_TOP_TRAIN_CALIB_ERROR_INFO_WOCLR__REG DENALI_PHY_1380 +#define LPDDR4__SC_PHY_TOP_TRAIN_CALIB_ERROR_INFO_WOCLR__FLD LPDDR4__DENALI_PHY_1380__SC_PHY_TOP_TRAIN_CALIB_ERROR_INFO_WOCLR + +#define LPDDR4__DENALI_PHY_1380__PHY_TRAIN_CALIB_ERROR_INFO_MASK 0x00007F00U +#define LPDDR4__DENALI_PHY_1380__PHY_TRAIN_CALIB_ERROR_INFO_SHIFT 8U +#define LPDDR4__DENALI_PHY_1380__PHY_TRAIN_CALIB_ERROR_INFO_WIDTH 7U +#define LPDDR4__PHY_TRAIN_CALIB_ERROR_INFO__REG DENALI_PHY_1380 +#define LPDDR4__PHY_TRAIN_CALIB_ERROR_INFO__FLD LPDDR4__DENALI_PHY_1380__PHY_TRAIN_CALIB_ERROR_INFO + +#define LPDDR4__DENALI_PHY_1380__PHY_TRAIN_CALIB_ERROR_INFO_MASK_MASK 0x007F0000U +#define LPDDR4__DENALI_PHY_1380__PHY_TRAIN_CALIB_ERROR_INFO_MASK_SHIFT 16U +#define LPDDR4__DENALI_PHY_1380__PHY_TRAIN_CALIB_ERROR_INFO_MASK_WIDTH 7U +#define LPDDR4__PHY_TRAIN_CALIB_ERROR_INFO_MASK__REG DENALI_PHY_1380 +#define LPDDR4__PHY_TRAIN_CALIB_ERROR_INFO_MASK__FLD LPDDR4__DENALI_PHY_1380__PHY_TRAIN_CALIB_ERROR_INFO_MASK + +#define LPDDR4__DENALI_PHY_1380__SC_PHY_TRAIN_CALIB_ERROR_INFO_WOCLR_MASK 0x7F000000U +#define LPDDR4__DENALI_PHY_1380__SC_PHY_TRAIN_CALIB_ERROR_INFO_WOCLR_SHIFT 24U +#define LPDDR4__DENALI_PHY_1380__SC_PHY_TRAIN_CALIB_ERROR_INFO_WOCLR_WIDTH 7U +#define LPDDR4__SC_PHY_TRAIN_CALIB_ERROR_INFO_WOCLR__REG DENALI_PHY_1380 +#define LPDDR4__SC_PHY_TRAIN_CALIB_ERROR_INFO_WOCLR__FLD LPDDR4__DENALI_PHY_1380__SC_PHY_TRAIN_CALIB_ERROR_INFO_WOCLR + +#define LPDDR4__DENALI_PHY_1381_READ_MASK 0x00003F3FU +#define LPDDR4__DENALI_PHY_1381_WRITE_MASK 0x00003F3FU +#define LPDDR4__DENALI_PHY_1381__PHY_GLOBAL_ERROR_INFO_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_1381__PHY_GLOBAL_ERROR_INFO_SHIFT 0U +#define LPDDR4__DENALI_PHY_1381__PHY_GLOBAL_ERROR_INFO_WIDTH 6U +#define LPDDR4__PHY_GLOBAL_ERROR_INFO__REG DENALI_PHY_1381 +#define LPDDR4__PHY_GLOBAL_ERROR_INFO__FLD LPDDR4__DENALI_PHY_1381__PHY_GLOBAL_ERROR_INFO + +#define LPDDR4__DENALI_PHY_1381__PHY_GLOBAL_ERROR_INFO_MASK_MASK 0x00003F00U +#define LPDDR4__DENALI_PHY_1381__PHY_GLOBAL_ERROR_INFO_MASK_SHIFT 8U +#define LPDDR4__DENALI_PHY_1381__PHY_GLOBAL_ERROR_INFO_MASK_WIDTH 6U +#define LPDDR4__PHY_GLOBAL_ERROR_INFO_MASK__REG DENALI_PHY_1381 +#define LPDDR4__PHY_GLOBAL_ERROR_INFO_MASK__FLD LPDDR4__DENALI_PHY_1381__PHY_GLOBAL_ERROR_INFO_MASK + +#define LPDDR4__DENALI_PHY_1382_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1382_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1382__PHY_TRAINING_TIMEOUT_VALUE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1382__PHY_TRAINING_TIMEOUT_VALUE_SHIFT 0U +#define LPDDR4__DENALI_PHY_1382__PHY_TRAINING_TIMEOUT_VALUE_WIDTH 20U +#define LPDDR4__PHY_TRAINING_TIMEOUT_VALUE__REG DENALI_PHY_1382 +#define LPDDR4__PHY_TRAINING_TIMEOUT_VALUE__FLD LPDDR4__DENALI_PHY_1382__PHY_TRAINING_TIMEOUT_VALUE + +#define LPDDR4__DENALI_PHY_1383_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1383_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1383__PHY_INIT_TIMEOUT_VALUE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1383__PHY_INIT_TIMEOUT_VALUE_SHIFT 0U +#define LPDDR4__DENALI_PHY_1383__PHY_INIT_TIMEOUT_VALUE_WIDTH 20U +#define LPDDR4__PHY_INIT_TIMEOUT_VALUE__REG DENALI_PHY_1383 +#define LPDDR4__PHY_INIT_TIMEOUT_VALUE__FLD LPDDR4__DENALI_PHY_1383__PHY_INIT_TIMEOUT_VALUE + +#define LPDDR4__DENALI_PHY_1384_READ_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_1384_WRITE_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_1384__PHY_LP_TIMEOUT_VALUE_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_1384__PHY_LP_TIMEOUT_VALUE_SHIFT 0U +#define LPDDR4__DENALI_PHY_1384__PHY_LP_TIMEOUT_VALUE_WIDTH 16U +#define LPDDR4__PHY_LP_TIMEOUT_VALUE__REG DENALI_PHY_1384 +#define LPDDR4__PHY_LP_TIMEOUT_VALUE__FLD LPDDR4__DENALI_PHY_1384__PHY_LP_TIMEOUT_VALUE + +#define LPDDR4__DENALI_PHY_1385_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1385_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1385__PHY_PHYUPD_TIMEOUT_VALUE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1385__PHY_PHYUPD_TIMEOUT_VALUE_SHIFT 0U +#define LPDDR4__DENALI_PHY_1385__PHY_PHYUPD_TIMEOUT_VALUE_WIDTH 32U +#define LPDDR4__PHY_PHYUPD_TIMEOUT_VALUE__REG DENALI_PHY_1385 +#define LPDDR4__PHY_PHYUPD_TIMEOUT_VALUE__FLD LPDDR4__DENALI_PHY_1385__PHY_PHYUPD_TIMEOUT_VALUE + +#define LPDDR4__DENALI_PHY_1386_READ_MASK 0x1F0FFFFFU +#define LPDDR4__DENALI_PHY_1386_WRITE_MASK 0x1F0FFFFFU +#define LPDDR4__DENALI_PHY_1386__PHY_PHYMSTR_TIMEOUT_VALUE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1386__PHY_PHYMSTR_TIMEOUT_VALUE_SHIFT 0U +#define LPDDR4__DENALI_PHY_1386__PHY_PHYMSTR_TIMEOUT_VALUE_WIDTH 20U +#define LPDDR4__PHY_PHYMSTR_TIMEOUT_VALUE__REG DENALI_PHY_1386 +#define LPDDR4__PHY_PHYMSTR_TIMEOUT_VALUE__FLD LPDDR4__DENALI_PHY_1386__PHY_PHYMSTR_TIMEOUT_VALUE + +#define LPDDR4__DENALI_PHY_1386__PHY_PLL_LOCK_0_MIN_VALUE_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_1386__PHY_PLL_LOCK_0_MIN_VALUE_SHIFT 24U +#define LPDDR4__DENALI_PHY_1386__PHY_PLL_LOCK_0_MIN_VALUE_WIDTH 5U +#define LPDDR4__PHY_PLL_LOCK_0_MIN_VALUE__REG DENALI_PHY_1386 +#define LPDDR4__PHY_PLL_LOCK_0_MIN_VALUE__FLD LPDDR4__DENALI_PHY_1386__PHY_PLL_LOCK_0_MIN_VALUE + +#define LPDDR4__DENALI_PHY_1387_READ_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_1387_WRITE_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_1387__PHY_PLL_LOCK_TIMEOUT_VALUE_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_1387__PHY_PLL_LOCK_TIMEOUT_VALUE_SHIFT 0U +#define LPDDR4__DENALI_PHY_1387__PHY_PLL_LOCK_TIMEOUT_VALUE_WIDTH 16U +#define LPDDR4__PHY_PLL_LOCK_TIMEOUT_VALUE__REG DENALI_PHY_1387 +#define LPDDR4__PHY_PLL_LOCK_TIMEOUT_VALUE__FLD LPDDR4__DENALI_PHY_1387__PHY_PLL_LOCK_TIMEOUT_VALUE + +#define LPDDR4__DENALI_PHY_1387__PHY_RDDATA_VALID_TIMEOUT_VALUE_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_1387__PHY_RDDATA_VALID_TIMEOUT_VALUE_SHIFT 16U +#define LPDDR4__DENALI_PHY_1387__PHY_RDDATA_VALID_TIMEOUT_VALUE_WIDTH 8U +#define LPDDR4__PHY_RDDATA_VALID_TIMEOUT_VALUE__REG DENALI_PHY_1387 +#define LPDDR4__PHY_RDDATA_VALID_TIMEOUT_VALUE__FLD LPDDR4__DENALI_PHY_1387__PHY_RDDATA_VALID_TIMEOUT_VALUE + +#define LPDDR4__DENALI_PHY_1387__PHY_PLL_FREQUENCY_DELTA_MASK 0x0F000000U +#define LPDDR4__DENALI_PHY_1387__PHY_PLL_FREQUENCY_DELTA_SHIFT 24U +#define LPDDR4__DENALI_PHY_1387__PHY_PLL_FREQUENCY_DELTA_WIDTH 4U +#define LPDDR4__PHY_PLL_FREQUENCY_DELTA__REG DENALI_PHY_1387 +#define LPDDR4__PHY_PLL_FREQUENCY_DELTA__FLD LPDDR4__DENALI_PHY_1387__PHY_PLL_FREQUENCY_DELTA + +#define LPDDR4__DENALI_PHY_1388_READ_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_1388_WRITE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_1388__PHY_PLL_FREQUENCY_COMPARE_INTERVAL_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_1388__PHY_PLL_FREQUENCY_COMPARE_INTERVAL_SHIFT 0U +#define LPDDR4__DENALI_PHY_1388__PHY_PLL_FREQUENCY_COMPARE_INTERVAL_WIDTH 16U +#define LPDDR4__PHY_PLL_FREQUENCY_COMPARE_INTERVAL__REG DENALI_PHY_1388 +#define LPDDR4__PHY_PLL_FREQUENCY_COMPARE_INTERVAL__FLD LPDDR4__DENALI_PHY_1388__PHY_PLL_FREQUENCY_COMPARE_INTERVAL + +#define LPDDR4__DENALI_PHY_1388__PHY_ADRCTL_FSM_ERROR_INFO_0_MASK 0x3FFF0000U +#define LPDDR4__DENALI_PHY_1388__PHY_ADRCTL_FSM_ERROR_INFO_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1388__PHY_ADRCTL_FSM_ERROR_INFO_0_WIDTH 14U +#define LPDDR4__PHY_ADRCTL_FSM_ERROR_INFO_0__REG DENALI_PHY_1388 +#define LPDDR4__PHY_ADRCTL_FSM_ERROR_INFO_0__FLD LPDDR4__DENALI_PHY_1388__PHY_ADRCTL_FSM_ERROR_INFO_0 + +#define LPDDR4__DENALI_PHY_1389_READ_MASK 0x00003FFFU +#define LPDDR4__DENALI_PHY_1389_WRITE_MASK 0x00003FFFU +#define LPDDR4__DENALI_PHY_1389__PHY_ADRCTL_FSM_ERROR_INFO_MASK_0_MASK 0x00003FFFU +#define LPDDR4__DENALI_PHY_1389__PHY_ADRCTL_FSM_ERROR_INFO_MASK_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1389__PHY_ADRCTL_FSM_ERROR_INFO_MASK_0_WIDTH 14U +#define LPDDR4__PHY_ADRCTL_FSM_ERROR_INFO_MASK_0__REG DENALI_PHY_1389 +#define LPDDR4__PHY_ADRCTL_FSM_ERROR_INFO_MASK_0__FLD LPDDR4__DENALI_PHY_1389__PHY_ADRCTL_FSM_ERROR_INFO_MASK_0 + +#define LPDDR4__DENALI_PHY_1389__SC_PHY_ADRCTL_FSM_ERROR_INFO_WOCLR_0_MASK 0x3FFF0000U +#define LPDDR4__DENALI_PHY_1389__SC_PHY_ADRCTL_FSM_ERROR_INFO_WOCLR_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1389__SC_PHY_ADRCTL_FSM_ERROR_INFO_WOCLR_0_WIDTH 14U +#define LPDDR4__SC_PHY_ADRCTL_FSM_ERROR_INFO_WOCLR_0__REG DENALI_PHY_1389 +#define LPDDR4__SC_PHY_ADRCTL_FSM_ERROR_INFO_WOCLR_0__FLD LPDDR4__DENALI_PHY_1389__SC_PHY_ADRCTL_FSM_ERROR_INFO_WOCLR_0 + +#define LPDDR4__DENALI_PHY_1390_READ_MASK 0x3FFF3FFFU +#define LPDDR4__DENALI_PHY_1390_WRITE_MASK 0x3FFF3FFFU +#define LPDDR4__DENALI_PHY_1390__PHY_ADRCTL_FSM_ERROR_INFO_1_MASK 0x00003FFFU +#define LPDDR4__DENALI_PHY_1390__PHY_ADRCTL_FSM_ERROR_INFO_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_1390__PHY_ADRCTL_FSM_ERROR_INFO_1_WIDTH 14U +#define LPDDR4__PHY_ADRCTL_FSM_ERROR_INFO_1__REG DENALI_PHY_1390 +#define LPDDR4__PHY_ADRCTL_FSM_ERROR_INFO_1__FLD LPDDR4__DENALI_PHY_1390__PHY_ADRCTL_FSM_ERROR_INFO_1 + +#define LPDDR4__DENALI_PHY_1390__PHY_ADRCTL_FSM_ERROR_INFO_MASK_1_MASK 0x3FFF0000U +#define LPDDR4__DENALI_PHY_1390__PHY_ADRCTL_FSM_ERROR_INFO_MASK_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_1390__PHY_ADRCTL_FSM_ERROR_INFO_MASK_1_WIDTH 14U +#define LPDDR4__PHY_ADRCTL_FSM_ERROR_INFO_MASK_1__REG DENALI_PHY_1390 +#define LPDDR4__PHY_ADRCTL_FSM_ERROR_INFO_MASK_1__FLD LPDDR4__DENALI_PHY_1390__PHY_ADRCTL_FSM_ERROR_INFO_MASK_1 + +#define LPDDR4__DENALI_PHY_1391_READ_MASK 0x3FFF0000U +#define LPDDR4__DENALI_PHY_1391_WRITE_MASK 0x3FFF0000U +#define LPDDR4__DENALI_PHY_1391__SC_PHY_ADRCTL_FSM_ERROR_INFO_WOCLR_1_MASK 0x00003FFFU +#define LPDDR4__DENALI_PHY_1391__SC_PHY_ADRCTL_FSM_ERROR_INFO_WOCLR_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_1391__SC_PHY_ADRCTL_FSM_ERROR_INFO_WOCLR_1_WIDTH 14U +#define LPDDR4__SC_PHY_ADRCTL_FSM_ERROR_INFO_WOCLR_1__REG DENALI_PHY_1391 +#define LPDDR4__SC_PHY_ADRCTL_FSM_ERROR_INFO_WOCLR_1__FLD LPDDR4__DENALI_PHY_1391__SC_PHY_ADRCTL_FSM_ERROR_INFO_WOCLR_1 + +#define LPDDR4__DENALI_PHY_1391__PHY_MEMCLK_FSM_ERROR_INFO_0_MASK 0x3FFF0000U +#define LPDDR4__DENALI_PHY_1391__PHY_MEMCLK_FSM_ERROR_INFO_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1391__PHY_MEMCLK_FSM_ERROR_INFO_0_WIDTH 14U +#define LPDDR4__PHY_MEMCLK_FSM_ERROR_INFO_0__REG DENALI_PHY_1391 +#define LPDDR4__PHY_MEMCLK_FSM_ERROR_INFO_0__FLD LPDDR4__DENALI_PHY_1391__PHY_MEMCLK_FSM_ERROR_INFO_0 + +#define LPDDR4__DENALI_PHY_1392_READ_MASK 0x00003FFFU +#define LPDDR4__DENALI_PHY_1392_WRITE_MASK 0x00003FFFU +#define LPDDR4__DENALI_PHY_1392__PHY_MEMCLK_FSM_ERROR_INFO_MASK_0_MASK 0x00003FFFU +#define LPDDR4__DENALI_PHY_1392__PHY_MEMCLK_FSM_ERROR_INFO_MASK_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1392__PHY_MEMCLK_FSM_ERROR_INFO_MASK_0_WIDTH 14U +#define LPDDR4__PHY_MEMCLK_FSM_ERROR_INFO_MASK_0__REG DENALI_PHY_1392 +#define LPDDR4__PHY_MEMCLK_FSM_ERROR_INFO_MASK_0__FLD LPDDR4__DENALI_PHY_1392__PHY_MEMCLK_FSM_ERROR_INFO_MASK_0 + +#define LPDDR4__DENALI_PHY_1392__SC_PHY_MEMCLK_FSM_ERROR_INFO_WOCLR_0_MASK 0x3FFF0000U +#define LPDDR4__DENALI_PHY_1392__SC_PHY_MEMCLK_FSM_ERROR_INFO_WOCLR_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1392__SC_PHY_MEMCLK_FSM_ERROR_INFO_WOCLR_0_WIDTH 14U +#define LPDDR4__SC_PHY_MEMCLK_FSM_ERROR_INFO_WOCLR_0__REG DENALI_PHY_1392 +#define LPDDR4__SC_PHY_MEMCLK_FSM_ERROR_INFO_WOCLR_0__FLD LPDDR4__DENALI_PHY_1392__SC_PHY_MEMCLK_FSM_ERROR_INFO_WOCLR_0 + +#define LPDDR4__DENALI_PHY_1393_READ_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1393_WRITE_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1393__PHY_PAD_CAL_IO_CFG_0_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1393__PHY_PAD_CAL_IO_CFG_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1393__PHY_PAD_CAL_IO_CFG_0_WIDTH 18U +#define LPDDR4__PHY_PAD_CAL_IO_CFG_0__REG DENALI_PHY_1393 +#define LPDDR4__PHY_PAD_CAL_IO_CFG_0__FLD LPDDR4__DENALI_PHY_1393__PHY_PAD_CAL_IO_CFG_0 + +#define LPDDR4__DENALI_PHY_1394_READ_MASK 0x00003FFFU +#define LPDDR4__DENALI_PHY_1394_WRITE_MASK 0x00003FFFU +#define LPDDR4__DENALI_PHY_1394__PHY_PAD_ACS_IO_CFG_MASK 0x00003FFFU +#define LPDDR4__DENALI_PHY_1394__PHY_PAD_ACS_IO_CFG_SHIFT 0U +#define LPDDR4__DENALI_PHY_1394__PHY_PAD_ACS_IO_CFG_WIDTH 14U +#define LPDDR4__PHY_PAD_ACS_IO_CFG__REG DENALI_PHY_1394 +#define LPDDR4__PHY_PAD_ACS_IO_CFG__FLD LPDDR4__DENALI_PHY_1394__PHY_PAD_ACS_IO_CFG + +#define LPDDR4__DENALI_PHY_1395_READ_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_1395_WRITE_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_1395__PHY_PLL_BYPASS_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_1395__PHY_PLL_BYPASS_SHIFT 0U +#define LPDDR4__DENALI_PHY_1395__PHY_PLL_BYPASS_WIDTH 1U +#define LPDDR4__DENALI_PHY_1395__PHY_PLL_BYPASS_WOCLR 0U +#define LPDDR4__DENALI_PHY_1395__PHY_PLL_BYPASS_WOSET 0U +#define LPDDR4__PHY_PLL_BYPASS__REG DENALI_PHY_1395 +#define LPDDR4__PHY_PLL_BYPASS__FLD LPDDR4__DENALI_PHY_1395__PHY_PLL_BYPASS + +#define LPDDR4__DENALI_PHY_1396_READ_MASK 0x00011FFFU +#define LPDDR4__DENALI_PHY_1396_WRITE_MASK 0x00011FFFU +#define LPDDR4__DENALI_PHY_1396__PHY_PLL_CTRL_MASK 0x00001FFFU +#define LPDDR4__DENALI_PHY_1396__PHY_PLL_CTRL_SHIFT 0U +#define LPDDR4__DENALI_PHY_1396__PHY_PLL_CTRL_WIDTH 13U +#define LPDDR4__PHY_PLL_CTRL__REG DENALI_PHY_1396 +#define LPDDR4__PHY_PLL_CTRL__FLD LPDDR4__DENALI_PHY_1396__PHY_PLL_CTRL + +#define LPDDR4__DENALI_PHY_1396__PHY_LOW_FREQ_SEL_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_1396__PHY_LOW_FREQ_SEL_SHIFT 16U +#define LPDDR4__DENALI_PHY_1396__PHY_LOW_FREQ_SEL_WIDTH 1U +#define LPDDR4__DENALI_PHY_1396__PHY_LOW_FREQ_SEL_WOCLR 0U +#define LPDDR4__DENALI_PHY_1396__PHY_LOW_FREQ_SEL_WOSET 0U +#define LPDDR4__PHY_LOW_FREQ_SEL__REG DENALI_PHY_1396 +#define LPDDR4__PHY_LOW_FREQ_SEL__FLD LPDDR4__DENALI_PHY_1396__PHY_LOW_FREQ_SEL + +#define LPDDR4__DENALI_PHY_1397_READ_MASK 0x0F0F0FFFU +#define LPDDR4__DENALI_PHY_1397_WRITE_MASK 0x0F0F0FFFU +#define LPDDR4__DENALI_PHY_1397__PHY_PAD_VREF_CTRL_AC_MASK 0x00000FFFU +#define LPDDR4__DENALI_PHY_1397__PHY_PAD_VREF_CTRL_AC_SHIFT 0U +#define LPDDR4__DENALI_PHY_1397__PHY_PAD_VREF_CTRL_AC_WIDTH 12U +#define LPDDR4__PHY_PAD_VREF_CTRL_AC__REG DENALI_PHY_1397 +#define LPDDR4__PHY_PAD_VREF_CTRL_AC__FLD LPDDR4__DENALI_PHY_1397__PHY_PAD_VREF_CTRL_AC + +#define LPDDR4__DENALI_PHY_1397__PHY_CSLVL_CAPTURE_CNT_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_1397__PHY_CSLVL_CAPTURE_CNT_SHIFT 16U +#define LPDDR4__DENALI_PHY_1397__PHY_CSLVL_CAPTURE_CNT_WIDTH 4U +#define LPDDR4__PHY_CSLVL_CAPTURE_CNT__REG DENALI_PHY_1397 +#define LPDDR4__PHY_CSLVL_CAPTURE_CNT__FLD LPDDR4__DENALI_PHY_1397__PHY_CSLVL_CAPTURE_CNT + +#define LPDDR4__DENALI_PHY_1397__PHY_CSLVL_DLY_STEP_MASK 0x0F000000U +#define LPDDR4__DENALI_PHY_1397__PHY_CSLVL_DLY_STEP_SHIFT 24U +#define LPDDR4__DENALI_PHY_1397__PHY_CSLVL_DLY_STEP_WIDTH 4U +#define LPDDR4__PHY_CSLVL_DLY_STEP__REG DENALI_PHY_1397 +#define LPDDR4__PHY_CSLVL_DLY_STEP__FLD LPDDR4__DENALI_PHY_1397__PHY_CSLVL_DLY_STEP + +#define LPDDR4__DENALI_PHY_1398_READ_MASK 0x010101FFU +#define LPDDR4__DENALI_PHY_1398_WRITE_MASK 0x010101FFU +#define LPDDR4__DENALI_PHY_1398__PHY_SW_CSLVL_DVW_MIN_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_1398__PHY_SW_CSLVL_DVW_MIN_SHIFT 0U +#define LPDDR4__DENALI_PHY_1398__PHY_SW_CSLVL_DVW_MIN_WIDTH 9U +#define LPDDR4__PHY_SW_CSLVL_DVW_MIN__REG DENALI_PHY_1398 +#define LPDDR4__PHY_SW_CSLVL_DVW_MIN__FLD LPDDR4__DENALI_PHY_1398__PHY_SW_CSLVL_DVW_MIN + +#define LPDDR4__DENALI_PHY_1398__PHY_SW_CSLVL_DVW_MIN_EN_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_1398__PHY_SW_CSLVL_DVW_MIN_EN_SHIFT 16U +#define LPDDR4__DENALI_PHY_1398__PHY_SW_CSLVL_DVW_MIN_EN_WIDTH 1U +#define LPDDR4__DENALI_PHY_1398__PHY_SW_CSLVL_DVW_MIN_EN_WOCLR 0U +#define LPDDR4__DENALI_PHY_1398__PHY_SW_CSLVL_DVW_MIN_EN_WOSET 0U +#define LPDDR4__PHY_SW_CSLVL_DVW_MIN_EN__REG DENALI_PHY_1398 +#define LPDDR4__PHY_SW_CSLVL_DVW_MIN_EN__FLD LPDDR4__DENALI_PHY_1398__PHY_SW_CSLVL_DVW_MIN_EN + +#define LPDDR4__DENALI_PHY_1398__PHY_LVL_MEAS_DLY_STEP_ENABLE_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_1398__PHY_LVL_MEAS_DLY_STEP_ENABLE_SHIFT 24U +#define LPDDR4__DENALI_PHY_1398__PHY_LVL_MEAS_DLY_STEP_ENABLE_WIDTH 1U +#define LPDDR4__DENALI_PHY_1398__PHY_LVL_MEAS_DLY_STEP_ENABLE_WOCLR 0U +#define LPDDR4__DENALI_PHY_1398__PHY_LVL_MEAS_DLY_STEP_ENABLE_WOSET 0U +#define LPDDR4__PHY_LVL_MEAS_DLY_STEP_ENABLE__REG DENALI_PHY_1398 +#define LPDDR4__PHY_LVL_MEAS_DLY_STEP_ENABLE__FLD LPDDR4__DENALI_PHY_1398__PHY_LVL_MEAS_DLY_STEP_ENABLE + +#define LPDDR4__DENALI_PHY_1399_READ_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_1399_WRITE_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_1399__PHY_GRP0_SLAVE_DELAY_0_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1399__PHY_GRP0_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1399__PHY_GRP0_SLAVE_DELAY_0_WIDTH 11U +#define LPDDR4__PHY_GRP0_SLAVE_DELAY_0__REG DENALI_PHY_1399 +#define LPDDR4__PHY_GRP0_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1399__PHY_GRP0_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_1399__PHY_GRP1_SLAVE_DELAY_0_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_1399__PHY_GRP1_SLAVE_DELAY_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1399__PHY_GRP1_SLAVE_DELAY_0_WIDTH 11U +#define LPDDR4__PHY_GRP1_SLAVE_DELAY_0__REG DENALI_PHY_1399 +#define LPDDR4__PHY_GRP1_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1399__PHY_GRP1_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_1400_READ_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_1400_WRITE_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_1400__PHY_GRP2_SLAVE_DELAY_0_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1400__PHY_GRP2_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1400__PHY_GRP2_SLAVE_DELAY_0_WIDTH 11U +#define LPDDR4__PHY_GRP2_SLAVE_DELAY_0__REG DENALI_PHY_1400 +#define LPDDR4__PHY_GRP2_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1400__PHY_GRP2_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_1400__PHY_GRP3_SLAVE_DELAY_0_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_1400__PHY_GRP3_SLAVE_DELAY_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1400__PHY_GRP3_SLAVE_DELAY_0_WIDTH 11U +#define LPDDR4__PHY_GRP3_SLAVE_DELAY_0__REG DENALI_PHY_1400 +#define LPDDR4__PHY_GRP3_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1400__PHY_GRP3_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_1401_READ_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1401_WRITE_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1401__PHY_GRP0_SLAVE_DELAY_1_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1401__PHY_GRP0_SLAVE_DELAY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_1401__PHY_GRP0_SLAVE_DELAY_1_WIDTH 11U +#define LPDDR4__PHY_GRP0_SLAVE_DELAY_1__REG DENALI_PHY_1401 +#define LPDDR4__PHY_GRP0_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_1401__PHY_GRP0_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_1402_READ_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1402_WRITE_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1402__PHY_GRP1_SLAVE_DELAY_1_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1402__PHY_GRP1_SLAVE_DELAY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_1402__PHY_GRP1_SLAVE_DELAY_1_WIDTH 11U +#define LPDDR4__PHY_GRP1_SLAVE_DELAY_1__REG DENALI_PHY_1402 +#define LPDDR4__PHY_GRP1_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_1402__PHY_GRP1_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_1403_READ_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1403_WRITE_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1403__PHY_GRP2_SLAVE_DELAY_1_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1403__PHY_GRP2_SLAVE_DELAY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_1403__PHY_GRP2_SLAVE_DELAY_1_WIDTH 11U +#define LPDDR4__PHY_GRP2_SLAVE_DELAY_1__REG DENALI_PHY_1403 +#define LPDDR4__PHY_GRP2_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_1403__PHY_GRP2_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_1404_READ_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1404_WRITE_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1404__PHY_GRP3_SLAVE_DELAY_1_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1404__PHY_GRP3_SLAVE_DELAY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_1404__PHY_GRP3_SLAVE_DELAY_1_WIDTH 11U +#define LPDDR4__PHY_GRP3_SLAVE_DELAY_1__REG DENALI_PHY_1404 +#define LPDDR4__PHY_GRP3_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_1404__PHY_GRP3_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_1405_READ_MASK 0x00000007U +#define LPDDR4__DENALI_PHY_1405_WRITE_MASK 0x00000007U +#define LPDDR4__DENALI_PHY_1405__PHY_CLK_DC_CAL_CLK_SEL_MASK 0x00000007U +#define LPDDR4__DENALI_PHY_1405__PHY_CLK_DC_CAL_CLK_SEL_SHIFT 0U +#define LPDDR4__DENALI_PHY_1405__PHY_CLK_DC_CAL_CLK_SEL_WIDTH 3U +#define LPDDR4__PHY_CLK_DC_CAL_CLK_SEL__REG DENALI_PHY_1405 +#define LPDDR4__PHY_CLK_DC_CAL_CLK_SEL__FLD LPDDR4__DENALI_PHY_1405__PHY_CLK_DC_CAL_CLK_SEL + +#define LPDDR4__DENALI_PHY_1406_READ_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_1406_WRITE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_1406__PHY_PAD_FDBK_DRIVE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_1406__PHY_PAD_FDBK_DRIVE_SHIFT 0U +#define LPDDR4__DENALI_PHY_1406__PHY_PAD_FDBK_DRIVE_WIDTH 30U +#define LPDDR4__PHY_PAD_FDBK_DRIVE__REG DENALI_PHY_1406 +#define LPDDR4__PHY_PAD_FDBK_DRIVE__FLD LPDDR4__DENALI_PHY_1406__PHY_PAD_FDBK_DRIVE + +#define LPDDR4__DENALI_PHY_1407_READ_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1407_WRITE_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1407__PHY_PAD_FDBK_DRIVE2_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1407__PHY_PAD_FDBK_DRIVE2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1407__PHY_PAD_FDBK_DRIVE2_WIDTH 18U +#define LPDDR4__PHY_PAD_FDBK_DRIVE2__REG DENALI_PHY_1407 +#define LPDDR4__PHY_PAD_FDBK_DRIVE2__FLD LPDDR4__DENALI_PHY_1407__PHY_PAD_FDBK_DRIVE2 + +#define LPDDR4__DENALI_PHY_1408_READ_MASK 0x7FFFFFFFU +#define LPDDR4__DENALI_PHY_1408_WRITE_MASK 0x7FFFFFFFU +#define LPDDR4__DENALI_PHY_1408__PHY_PAD_DATA_DRIVE_MASK 0x7FFFFFFFU +#define LPDDR4__DENALI_PHY_1408__PHY_PAD_DATA_DRIVE_SHIFT 0U +#define LPDDR4__DENALI_PHY_1408__PHY_PAD_DATA_DRIVE_WIDTH 31U +#define LPDDR4__PHY_PAD_DATA_DRIVE__REG DENALI_PHY_1408 +#define LPDDR4__PHY_PAD_DATA_DRIVE__FLD LPDDR4__DENALI_PHY_1408__PHY_PAD_DATA_DRIVE + +#define LPDDR4__DENALI_PHY_1409_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1409_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1409__PHY_PAD_DQS_DRIVE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1409__PHY_PAD_DQS_DRIVE_SHIFT 0U +#define LPDDR4__DENALI_PHY_1409__PHY_PAD_DQS_DRIVE_WIDTH 32U +#define LPDDR4__PHY_PAD_DQS_DRIVE__REG DENALI_PHY_1409 +#define LPDDR4__PHY_PAD_DQS_DRIVE__FLD LPDDR4__DENALI_PHY_1409__PHY_PAD_DQS_DRIVE + +#define LPDDR4__DENALI_PHY_1410_READ_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_1410_WRITE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_1410__PHY_PAD_ADDR_DRIVE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_1410__PHY_PAD_ADDR_DRIVE_SHIFT 0U +#define LPDDR4__DENALI_PHY_1410__PHY_PAD_ADDR_DRIVE_WIDTH 30U +#define LPDDR4__PHY_PAD_ADDR_DRIVE__REG DENALI_PHY_1410 +#define LPDDR4__PHY_PAD_ADDR_DRIVE__FLD LPDDR4__DENALI_PHY_1410__PHY_PAD_ADDR_DRIVE + +#define LPDDR4__DENALI_PHY_1411_READ_MASK 0x07FFFFFFU +#define LPDDR4__DENALI_PHY_1411_WRITE_MASK 0x07FFFFFFU +#define LPDDR4__DENALI_PHY_1411__PHY_PAD_ADDR_DRIVE2_MASK 0x07FFFFFFU +#define LPDDR4__DENALI_PHY_1411__PHY_PAD_ADDR_DRIVE2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1411__PHY_PAD_ADDR_DRIVE2_WIDTH 27U +#define LPDDR4__PHY_PAD_ADDR_DRIVE2__REG DENALI_PHY_1411 +#define LPDDR4__PHY_PAD_ADDR_DRIVE2__FLD LPDDR4__DENALI_PHY_1411__PHY_PAD_ADDR_DRIVE2 + +#define LPDDR4__DENALI_PHY_1412_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1412_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1412__PHY_PAD_CLK_DRIVE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1412__PHY_PAD_CLK_DRIVE_SHIFT 0U +#define LPDDR4__DENALI_PHY_1412__PHY_PAD_CLK_DRIVE_WIDTH 32U +#define LPDDR4__PHY_PAD_CLK_DRIVE__REG DENALI_PHY_1412 +#define LPDDR4__PHY_PAD_CLK_DRIVE__FLD LPDDR4__DENALI_PHY_1412__PHY_PAD_CLK_DRIVE + +#define LPDDR4__DENALI_PHY_1413_READ_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1413_WRITE_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1413__PHY_PAD_CLK_DRIVE2_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1413__PHY_PAD_CLK_DRIVE2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1413__PHY_PAD_CLK_DRIVE2_WIDTH 18U +#define LPDDR4__PHY_PAD_CLK_DRIVE2__REG DENALI_PHY_1413 +#define LPDDR4__PHY_PAD_CLK_DRIVE2__FLD LPDDR4__DENALI_PHY_1413__PHY_PAD_CLK_DRIVE2 + +#define LPDDR4__DENALI_PHY_1414_READ_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_1414_WRITE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_1414__PHY_PAD_CKE_DRIVE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_1414__PHY_PAD_CKE_DRIVE_SHIFT 0U +#define LPDDR4__DENALI_PHY_1414__PHY_PAD_CKE_DRIVE_WIDTH 30U +#define LPDDR4__PHY_PAD_CKE_DRIVE__REG DENALI_PHY_1414 +#define LPDDR4__PHY_PAD_CKE_DRIVE__FLD LPDDR4__DENALI_PHY_1414__PHY_PAD_CKE_DRIVE + +#define LPDDR4__DENALI_PHY_1415_READ_MASK 0x07FFFFFFU +#define LPDDR4__DENALI_PHY_1415_WRITE_MASK 0x07FFFFFFU +#define LPDDR4__DENALI_PHY_1415__PHY_PAD_CKE_DRIVE2_MASK 0x07FFFFFFU +#define LPDDR4__DENALI_PHY_1415__PHY_PAD_CKE_DRIVE2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1415__PHY_PAD_CKE_DRIVE2_WIDTH 27U +#define LPDDR4__PHY_PAD_CKE_DRIVE2__REG DENALI_PHY_1415 +#define LPDDR4__PHY_PAD_CKE_DRIVE2__FLD LPDDR4__DENALI_PHY_1415__PHY_PAD_CKE_DRIVE2 + +#define LPDDR4__DENALI_PHY_1416_READ_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_1416_WRITE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_1416__PHY_PAD_RST_DRIVE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_1416__PHY_PAD_RST_DRIVE_SHIFT 0U +#define LPDDR4__DENALI_PHY_1416__PHY_PAD_RST_DRIVE_WIDTH 30U +#define LPDDR4__PHY_PAD_RST_DRIVE__REG DENALI_PHY_1416 +#define LPDDR4__PHY_PAD_RST_DRIVE__FLD LPDDR4__DENALI_PHY_1416__PHY_PAD_RST_DRIVE + +#define LPDDR4__DENALI_PHY_1417_READ_MASK 0x07FFFFFFU +#define LPDDR4__DENALI_PHY_1417_WRITE_MASK 0x07FFFFFFU +#define LPDDR4__DENALI_PHY_1417__PHY_PAD_RST_DRIVE2_MASK 0x07FFFFFFU +#define LPDDR4__DENALI_PHY_1417__PHY_PAD_RST_DRIVE2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1417__PHY_PAD_RST_DRIVE2_WIDTH 27U +#define LPDDR4__PHY_PAD_RST_DRIVE2__REG DENALI_PHY_1417 +#define LPDDR4__PHY_PAD_RST_DRIVE2__FLD LPDDR4__DENALI_PHY_1417__PHY_PAD_RST_DRIVE2 + +#define LPDDR4__DENALI_PHY_1418_READ_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_1418_WRITE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_1418__PHY_PAD_CS_DRIVE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_1418__PHY_PAD_CS_DRIVE_SHIFT 0U +#define LPDDR4__DENALI_PHY_1418__PHY_PAD_CS_DRIVE_WIDTH 30U +#define LPDDR4__PHY_PAD_CS_DRIVE__REG DENALI_PHY_1418 +#define LPDDR4__PHY_PAD_CS_DRIVE__FLD LPDDR4__DENALI_PHY_1418__PHY_PAD_CS_DRIVE + +#define LPDDR4__DENALI_PHY_1419_READ_MASK 0x07FFFFFFU +#define LPDDR4__DENALI_PHY_1419_WRITE_MASK 0x07FFFFFFU +#define LPDDR4__DENALI_PHY_1419__PHY_PAD_CS_DRIVE2_MASK 0x07FFFFFFU +#define LPDDR4__DENALI_PHY_1419__PHY_PAD_CS_DRIVE2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1419__PHY_PAD_CS_DRIVE2_WIDTH 27U +#define LPDDR4__PHY_PAD_CS_DRIVE2__REG DENALI_PHY_1419 +#define LPDDR4__PHY_PAD_CS_DRIVE2__FLD LPDDR4__DENALI_PHY_1419__PHY_PAD_CS_DRIVE2 + +#define LPDDR4__DENALI_PHY_1420_READ_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_1420_WRITE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_1420__PHY_PAD_ODT_DRIVE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_1420__PHY_PAD_ODT_DRIVE_SHIFT 0U +#define LPDDR4__DENALI_PHY_1420__PHY_PAD_ODT_DRIVE_WIDTH 30U +#define LPDDR4__PHY_PAD_ODT_DRIVE__REG DENALI_PHY_1420 +#define LPDDR4__PHY_PAD_ODT_DRIVE__FLD LPDDR4__DENALI_PHY_1420__PHY_PAD_ODT_DRIVE + +#define LPDDR4__DENALI_PHY_1421_READ_MASK 0x07FFFFFFU +#define LPDDR4__DENALI_PHY_1421_WRITE_MASK 0x07FFFFFFU +#define LPDDR4__DENALI_PHY_1421__PHY_PAD_ODT_DRIVE2_MASK 0x07FFFFFFU +#define LPDDR4__DENALI_PHY_1421__PHY_PAD_ODT_DRIVE2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1421__PHY_PAD_ODT_DRIVE2_WIDTH 27U +#define LPDDR4__PHY_PAD_ODT_DRIVE2__REG DENALI_PHY_1421 +#define LPDDR4__PHY_PAD_ODT_DRIVE2__FLD LPDDR4__DENALI_PHY_1421__PHY_PAD_ODT_DRIVE2 + +#define LPDDR4__DENALI_PHY_1422_READ_MASK 0x7FFFFF07U +#define LPDDR4__DENALI_PHY_1422_WRITE_MASK 0x7FFFFF07U +#define LPDDR4__DENALI_PHY_1422__PHY_CAL_CLK_SELECT_0_MASK 0x00000007U +#define LPDDR4__DENALI_PHY_1422__PHY_CAL_CLK_SELECT_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1422__PHY_CAL_CLK_SELECT_0_WIDTH 3U +#define LPDDR4__PHY_CAL_CLK_SELECT_0__REG DENALI_PHY_1422 +#define LPDDR4__PHY_CAL_CLK_SELECT_0__FLD LPDDR4__DENALI_PHY_1422__PHY_CAL_CLK_SELECT_0 + +#define LPDDR4__DENALI_PHY_1422__PHY_CAL_VREF_SWITCH_TIMER_0_MASK 0x00FFFF00U +#define LPDDR4__DENALI_PHY_1422__PHY_CAL_VREF_SWITCH_TIMER_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_1422__PHY_CAL_VREF_SWITCH_TIMER_0_WIDTH 16U +#define LPDDR4__PHY_CAL_VREF_SWITCH_TIMER_0__REG DENALI_PHY_1422 +#define LPDDR4__PHY_CAL_VREF_SWITCH_TIMER_0__FLD LPDDR4__DENALI_PHY_1422__PHY_CAL_VREF_SWITCH_TIMER_0 + +#define LPDDR4__DENALI_PHY_1422__PHY_CAL_SETTLING_PRD_0_MASK 0x7F000000U +#define LPDDR4__DENALI_PHY_1422__PHY_CAL_SETTLING_PRD_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_1422__PHY_CAL_SETTLING_PRD_0_WIDTH 7U +#define LPDDR4__PHY_CAL_SETTLING_PRD_0__REG DENALI_PHY_1422 +#define LPDDR4__PHY_CAL_SETTLING_PRD_0__FLD LPDDR4__DENALI_PHY_1422__PHY_CAL_SETTLING_PRD_0 + +#endif /* REG_LPDDR4_PHY_CORE_MACROS_H_ */ diff --git a/drivers/ram/k3-j721e/lpddr4_pi_macros.h b/drivers/ram/k3-j721e/lpddr4_pi_macros.h new file mode 100644 index 0000000..23b31f2 --- /dev/null +++ b/drivers/ram/k3-j721e/lpddr4_pi_macros.h @@ -0,0 +1,5397 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/********************************************************************** + * Copyright (C) 2012-2019 Cadence Design Systems, Inc. + * + * THIS FILE IS AUTOMATICALLY GENERATED, DO NOT EDIT + * + ********************************************************************** + */ + +#ifndef REG_LPDDR4_PI_MACROS_H_ +#define REG_LPDDR4_PI_MACROS_H_ + +#define LPDDR4__DENALI_PI_0_READ_MASK 0x00000F01U +#define LPDDR4__DENALI_PI_0_WRITE_MASK 0x00000F01U +#define LPDDR4__DENALI_PI_0__PI_START_MASK 0x00000001U +#define LPDDR4__DENALI_PI_0__PI_START_SHIFT 0U +#define LPDDR4__DENALI_PI_0__PI_START_WIDTH 1U +#define LPDDR4__DENALI_PI_0__PI_START_WOCLR 0U +#define LPDDR4__DENALI_PI_0__PI_START_WOSET 0U +#define LPDDR4__PI_START__REG DENALI_PI_0 +#define LPDDR4__PI_START__FLD LPDDR4__DENALI_PI_0__PI_START + +#define LPDDR4__DENALI_PI_0__PI_DRAM_CLASS_MASK 0x00000F00U +#define LPDDR4__DENALI_PI_0__PI_DRAM_CLASS_SHIFT 8U +#define LPDDR4__DENALI_PI_0__PI_DRAM_CLASS_WIDTH 4U +#define LPDDR4__PI_DRAM_CLASS__REG DENALI_PI_0 +#define LPDDR4__PI_DRAM_CLASS__FLD LPDDR4__DENALI_PI_0__PI_DRAM_CLASS + +#define LPDDR4__DENALI_PI_1_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_1_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_1__PI_VERSION_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_1__PI_VERSION_0_SHIFT 0U +#define LPDDR4__DENALI_PI_1__PI_VERSION_0_WIDTH 32U +#define LPDDR4__PI_VERSION_0__REG DENALI_PI_1 +#define LPDDR4__PI_VERSION_0__FLD LPDDR4__DENALI_PI_1__PI_VERSION_0 + +#define LPDDR4__DENALI_PI_2_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_2_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_2__PI_VERSION_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_2__PI_VERSION_1_SHIFT 0U +#define LPDDR4__DENALI_PI_2__PI_VERSION_1_WIDTH 32U +#define LPDDR4__PI_VERSION_1__REG DENALI_PI_2 +#define LPDDR4__PI_VERSION_1__FLD LPDDR4__DENALI_PI_2__PI_VERSION_1 + +#define LPDDR4__DENALI_PI_3_READ_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PI_3_WRITE_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PI_3__PI_ID_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PI_3__PI_ID_SHIFT 0U +#define LPDDR4__DENALI_PI_3__PI_ID_WIDTH 16U +#define LPDDR4__PI_ID__REG DENALI_PI_3 +#define LPDDR4__PI_ID__FLD LPDDR4__DENALI_PI_3__PI_ID + +#define LPDDR4__DENALI_PI_4_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_4_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_4__DENALI_PI_UNUSED_REG_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_4__DENALI_PI_UNUSED_REG_0_SHIFT 0U +#define LPDDR4__DENALI_PI_4__DENALI_PI_UNUSED_REG_0_WIDTH 32U +#define LPDDR4__DENALI_PI_UNUSED_REG_0__REG DENALI_PI_4 +#define LPDDR4__DENALI_PI_UNUSED_REG_0__FLD LPDDR4__DENALI_PI_4__DENALI_PI_UNUSED_REG_0 + +#define LPDDR4__DENALI_PI_5_READ_MASK 0x00010101U +#define LPDDR4__DENALI_PI_5_WRITE_MASK 0x00010101U +#define LPDDR4__DENALI_PI_5__PI_NORMAL_LVL_SEQ_MASK 0x00000001U +#define LPDDR4__DENALI_PI_5__PI_NORMAL_LVL_SEQ_SHIFT 0U +#define LPDDR4__DENALI_PI_5__PI_NORMAL_LVL_SEQ_WIDTH 1U +#define LPDDR4__DENALI_PI_5__PI_NORMAL_LVL_SEQ_WOCLR 0U +#define LPDDR4__DENALI_PI_5__PI_NORMAL_LVL_SEQ_WOSET 0U +#define LPDDR4__PI_NORMAL_LVL_SEQ__REG DENALI_PI_5 +#define LPDDR4__PI_NORMAL_LVL_SEQ__FLD LPDDR4__DENALI_PI_5__PI_NORMAL_LVL_SEQ + +#define LPDDR4__DENALI_PI_5__PI_INIT_LVL_EN_MASK 0x00000100U +#define LPDDR4__DENALI_PI_5__PI_INIT_LVL_EN_SHIFT 8U +#define LPDDR4__DENALI_PI_5__PI_INIT_LVL_EN_WIDTH 1U +#define LPDDR4__DENALI_PI_5__PI_INIT_LVL_EN_WOCLR 0U +#define LPDDR4__DENALI_PI_5__PI_INIT_LVL_EN_WOSET 0U +#define LPDDR4__PI_INIT_LVL_EN__REG DENALI_PI_5 +#define LPDDR4__PI_INIT_LVL_EN__FLD LPDDR4__DENALI_PI_5__PI_INIT_LVL_EN + +#define LPDDR4__DENALI_PI_5__PI_NOTCARE_PHYUPD_MASK 0x00010000U +#define LPDDR4__DENALI_PI_5__PI_NOTCARE_PHYUPD_SHIFT 16U +#define LPDDR4__DENALI_PI_5__PI_NOTCARE_PHYUPD_WIDTH 1U +#define LPDDR4__DENALI_PI_5__PI_NOTCARE_PHYUPD_WOCLR 0U +#define LPDDR4__DENALI_PI_5__PI_NOTCARE_PHYUPD_WOSET 0U +#define LPDDR4__PI_NOTCARE_PHYUPD__REG DENALI_PI_5 +#define LPDDR4__PI_NOTCARE_PHYUPD__FLD LPDDR4__DENALI_PI_5__PI_NOTCARE_PHYUPD + +#define LPDDR4__DENALI_PI_6_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_6_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_6__PI_TCMD_GAP_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PI_6__PI_TCMD_GAP_SHIFT 0U +#define LPDDR4__DENALI_PI_6__PI_TCMD_GAP_WIDTH 16U +#define LPDDR4__PI_TCMD_GAP__REG DENALI_PI_6 +#define LPDDR4__PI_TCMD_GAP__FLD LPDDR4__DENALI_PI_6__PI_TCMD_GAP + +#define LPDDR4__DENALI_PI_6__PI_RESERVED0_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_6__PI_RESERVED0_SHIFT 16U +#define LPDDR4__DENALI_PI_6__PI_RESERVED0_WIDTH 8U +#define LPDDR4__PI_RESERVED0__REG DENALI_PI_6 +#define LPDDR4__PI_RESERVED0__FLD LPDDR4__DENALI_PI_6__PI_RESERVED0 + +#define LPDDR4__DENALI_PI_6__PI_TRAIN_ALL_FREQ_REQ_MASK 0x01000000U +#define LPDDR4__DENALI_PI_6__PI_TRAIN_ALL_FREQ_REQ_SHIFT 24U +#define LPDDR4__DENALI_PI_6__PI_TRAIN_ALL_FREQ_REQ_WIDTH 1U +#define LPDDR4__DENALI_PI_6__PI_TRAIN_ALL_FREQ_REQ_WOCLR 0U +#define LPDDR4__DENALI_PI_6__PI_TRAIN_ALL_FREQ_REQ_WOSET 0U +#define LPDDR4__PI_TRAIN_ALL_FREQ_REQ__REG DENALI_PI_6 +#define LPDDR4__PI_TRAIN_ALL_FREQ_REQ__FLD LPDDR4__DENALI_PI_6__PI_TRAIN_ALL_FREQ_REQ + +#define LPDDR4__DENALI_PI_7_READ_MASK 0x01010301U +#define LPDDR4__DENALI_PI_7_WRITE_MASK 0x01010301U +#define LPDDR4__DENALI_PI_7__PI_DFI_VERSION_MASK 0x00000001U +#define LPDDR4__DENALI_PI_7__PI_DFI_VERSION_SHIFT 0U +#define LPDDR4__DENALI_PI_7__PI_DFI_VERSION_WIDTH 1U +#define LPDDR4__DENALI_PI_7__PI_DFI_VERSION_WOCLR 0U +#define LPDDR4__DENALI_PI_7__PI_DFI_VERSION_WOSET 0U +#define LPDDR4__PI_DFI_VERSION__REG DENALI_PI_7 +#define LPDDR4__PI_DFI_VERSION__FLD LPDDR4__DENALI_PI_7__PI_DFI_VERSION + +#define LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_TYPE_MASK 0x00000300U +#define LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_TYPE_SHIFT 8U +#define LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_TYPE_WIDTH 2U +#define LPDDR4__PI_DFI_PHYMSTR_TYPE__REG DENALI_PI_7 +#define LPDDR4__PI_DFI_PHYMSTR_TYPE__FLD LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_TYPE + +#define LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_CS_STATE_R_MASK 0x00010000U +#define LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_CS_STATE_R_SHIFT 16U +#define LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_CS_STATE_R_WIDTH 1U +#define LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_CS_STATE_R_WOCLR 0U +#define LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_CS_STATE_R_WOSET 0U +#define LPDDR4__PI_DFI_PHYMSTR_CS_STATE_R__REG DENALI_PI_7 +#define LPDDR4__PI_DFI_PHYMSTR_CS_STATE_R__FLD LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_CS_STATE_R + +#define LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_STATE_SEL_R_MASK 0x01000000U +#define LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_STATE_SEL_R_SHIFT 24U +#define LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_STATE_SEL_R_WIDTH 1U +#define LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_STATE_SEL_R_WOCLR 0U +#define LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_STATE_SEL_R_WOSET 0U +#define LPDDR4__PI_DFI_PHYMSTR_STATE_SEL_R__REG DENALI_PI_7 +#define LPDDR4__PI_DFI_PHYMSTR_STATE_SEL_R__FLD LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_STATE_SEL_R + +#define LPDDR4__DENALI_PI_8_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_8_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_8__PI_TDFI_PHYMSTR_MAX_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_8__PI_TDFI_PHYMSTR_MAX_SHIFT 0U +#define LPDDR4__DENALI_PI_8__PI_TDFI_PHYMSTR_MAX_WIDTH 32U +#define LPDDR4__PI_TDFI_PHYMSTR_MAX__REG DENALI_PI_8 +#define LPDDR4__PI_TDFI_PHYMSTR_MAX__FLD LPDDR4__DENALI_PI_8__PI_TDFI_PHYMSTR_MAX + +#define LPDDR4__DENALI_PI_9_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PI_9_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PI_9__PI_TDFI_PHYMSTR_RESP_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PI_9__PI_TDFI_PHYMSTR_RESP_SHIFT 0U +#define LPDDR4__DENALI_PI_9__PI_TDFI_PHYMSTR_RESP_WIDTH 20U +#define LPDDR4__PI_TDFI_PHYMSTR_RESP__REG DENALI_PI_9 +#define LPDDR4__PI_TDFI_PHYMSTR_RESP__FLD LPDDR4__DENALI_PI_9__PI_TDFI_PHYMSTR_RESP + +#define LPDDR4__DENALI_PI_10_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PI_10_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PI_10__PI_TDFI_PHYUPD_RESP_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PI_10__PI_TDFI_PHYUPD_RESP_SHIFT 0U +#define LPDDR4__DENALI_PI_10__PI_TDFI_PHYUPD_RESP_WIDTH 20U +#define LPDDR4__PI_TDFI_PHYUPD_RESP__REG DENALI_PI_10 +#define LPDDR4__PI_TDFI_PHYUPD_RESP__FLD LPDDR4__DENALI_PI_10__PI_TDFI_PHYUPD_RESP + +#define LPDDR4__DENALI_PI_11_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_11_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_11__PI_TDFI_PHYUPD_MAX_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_11__PI_TDFI_PHYUPD_MAX_SHIFT 0U +#define LPDDR4__DENALI_PI_11__PI_TDFI_PHYUPD_MAX_WIDTH 32U +#define LPDDR4__PI_TDFI_PHYUPD_MAX__REG DENALI_PI_11 +#define LPDDR4__PI_TDFI_PHYUPD_MAX__FLD LPDDR4__DENALI_PI_11__PI_TDFI_PHYUPD_MAX + +#define LPDDR4__DENALI_PI_12_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_12_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_12__PI_FREQ_MAP_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_12__PI_FREQ_MAP_SHIFT 0U +#define LPDDR4__DENALI_PI_12__PI_FREQ_MAP_WIDTH 32U +#define LPDDR4__PI_FREQ_MAP__REG DENALI_PI_12 +#define LPDDR4__PI_FREQ_MAP__FLD LPDDR4__DENALI_PI_12__PI_FREQ_MAP + +#define LPDDR4__DENALI_PI_13_READ_MASK 0x0101011FU +#define LPDDR4__DENALI_PI_13_WRITE_MASK 0x0101011FU +#define LPDDR4__DENALI_PI_13__PI_INIT_WORK_FREQ_MASK 0x0000001FU +#define LPDDR4__DENALI_PI_13__PI_INIT_WORK_FREQ_SHIFT 0U +#define LPDDR4__DENALI_PI_13__PI_INIT_WORK_FREQ_WIDTH 5U +#define LPDDR4__PI_INIT_WORK_FREQ__REG DENALI_PI_13 +#define LPDDR4__PI_INIT_WORK_FREQ__FLD LPDDR4__DENALI_PI_13__PI_INIT_WORK_FREQ + +#define LPDDR4__DENALI_PI_13__PI_INIT_DFS_CALVL_ONLY_MASK 0x00000100U +#define LPDDR4__DENALI_PI_13__PI_INIT_DFS_CALVL_ONLY_SHIFT 8U +#define LPDDR4__DENALI_PI_13__PI_INIT_DFS_CALVL_ONLY_WIDTH 1U +#define LPDDR4__DENALI_PI_13__PI_INIT_DFS_CALVL_ONLY_WOCLR 0U +#define LPDDR4__DENALI_PI_13__PI_INIT_DFS_CALVL_ONLY_WOSET 0U +#define LPDDR4__PI_INIT_DFS_CALVL_ONLY__REG DENALI_PI_13 +#define LPDDR4__PI_INIT_DFS_CALVL_ONLY__FLD LPDDR4__DENALI_PI_13__PI_INIT_DFS_CALVL_ONLY + +#define LPDDR4__DENALI_PI_13__PI_SW_RST_N_MASK 0x00010000U +#define LPDDR4__DENALI_PI_13__PI_SW_RST_N_SHIFT 16U +#define LPDDR4__DENALI_PI_13__PI_SW_RST_N_WIDTH 1U +#define LPDDR4__DENALI_PI_13__PI_SW_RST_N_WOCLR 0U +#define LPDDR4__DENALI_PI_13__PI_SW_RST_N_WOSET 0U +#define LPDDR4__PI_SW_RST_N__REG DENALI_PI_13 +#define LPDDR4__PI_SW_RST_N__FLD LPDDR4__DENALI_PI_13__PI_SW_RST_N + +#define LPDDR4__DENALI_PI_13__PI_RESERVED1_MASK 0x01000000U +#define LPDDR4__DENALI_PI_13__PI_RESERVED1_SHIFT 24U +#define LPDDR4__DENALI_PI_13__PI_RESERVED1_WIDTH 1U +#define LPDDR4__DENALI_PI_13__PI_RESERVED1_WOCLR 0U +#define LPDDR4__DENALI_PI_13__PI_RESERVED1_WOSET 0U +#define LPDDR4__PI_RESERVED1__REG DENALI_PI_13 +#define LPDDR4__PI_RESERVED1__FLD LPDDR4__DENALI_PI_13__PI_RESERVED1 + +#define LPDDR4__DENALI_PI_14_READ_MASK 0x0F011F0FU +#define LPDDR4__DENALI_PI_14_WRITE_MASK 0x0F011F0FU +#define LPDDR4__DENALI_PI_14__PI_CS_MAP_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_14__PI_CS_MAP_SHIFT 0U +#define LPDDR4__DENALI_PI_14__PI_CS_MAP_WIDTH 4U +#define LPDDR4__PI_CS_MAP__REG DENALI_PI_14 +#define LPDDR4__PI_CS_MAP__FLD LPDDR4__DENALI_PI_14__PI_CS_MAP + +#define LPDDR4__DENALI_PI_14__PI_RANK_NUM_PER_CKE_MASK 0x00001F00U +#define LPDDR4__DENALI_PI_14__PI_RANK_NUM_PER_CKE_SHIFT 8U +#define LPDDR4__DENALI_PI_14__PI_RANK_NUM_PER_CKE_WIDTH 5U +#define LPDDR4__PI_RANK_NUM_PER_CKE__REG DENALI_PI_14 +#define LPDDR4__PI_RANK_NUM_PER_CKE__FLD LPDDR4__DENALI_PI_14__PI_RANK_NUM_PER_CKE + +#define LPDDR4__DENALI_PI_14__PI_SRX_LVL_TARGET_CS_EN_MASK 0x00010000U +#define LPDDR4__DENALI_PI_14__PI_SRX_LVL_TARGET_CS_EN_SHIFT 16U +#define LPDDR4__DENALI_PI_14__PI_SRX_LVL_TARGET_CS_EN_WIDTH 1U +#define LPDDR4__DENALI_PI_14__PI_SRX_LVL_TARGET_CS_EN_WOCLR 0U +#define LPDDR4__DENALI_PI_14__PI_SRX_LVL_TARGET_CS_EN_WOSET 0U +#define LPDDR4__PI_SRX_LVL_TARGET_CS_EN__REG DENALI_PI_14 +#define LPDDR4__PI_SRX_LVL_TARGET_CS_EN__FLD LPDDR4__DENALI_PI_14__PI_SRX_LVL_TARGET_CS_EN + +#define LPDDR4__DENALI_PI_14__PI_TMRR_MASK 0x0F000000U +#define LPDDR4__DENALI_PI_14__PI_TMRR_SHIFT 24U +#define LPDDR4__DENALI_PI_14__PI_TMRR_WIDTH 4U +#define LPDDR4__PI_TMRR__REG DENALI_PI_14 +#define LPDDR4__PI_TMRR__FLD LPDDR4__DENALI_PI_14__PI_TMRR + +#define LPDDR4__DENALI_PI_15_READ_MASK 0x00010103U +#define LPDDR4__DENALI_PI_15_WRITE_MASK 0x00010103U +#define LPDDR4__DENALI_PI_15__PI_PREAMBLE_SUPPORT_MASK 0x00000003U +#define LPDDR4__DENALI_PI_15__PI_PREAMBLE_SUPPORT_SHIFT 0U +#define LPDDR4__DENALI_PI_15__PI_PREAMBLE_SUPPORT_WIDTH 2U +#define LPDDR4__PI_PREAMBLE_SUPPORT__REG DENALI_PI_15 +#define LPDDR4__PI_PREAMBLE_SUPPORT__FLD LPDDR4__DENALI_PI_15__PI_PREAMBLE_SUPPORT + +#define LPDDR4__DENALI_PI_15__PI_MCAREF_FORWARD_ONLY_MASK 0x00000100U +#define LPDDR4__DENALI_PI_15__PI_MCAREF_FORWARD_ONLY_SHIFT 8U +#define LPDDR4__DENALI_PI_15__PI_MCAREF_FORWARD_ONLY_WIDTH 1U +#define LPDDR4__DENALI_PI_15__PI_MCAREF_FORWARD_ONLY_WOCLR 0U +#define LPDDR4__DENALI_PI_15__PI_MCAREF_FORWARD_ONLY_WOSET 0U +#define LPDDR4__PI_MCAREF_FORWARD_ONLY__REG DENALI_PI_15 +#define LPDDR4__PI_MCAREF_FORWARD_ONLY__FLD LPDDR4__DENALI_PI_15__PI_MCAREF_FORWARD_ONLY + +#define LPDDR4__DENALI_PI_15__PI_RESERVED2_MASK 0x00010000U +#define LPDDR4__DENALI_PI_15__PI_RESERVED2_SHIFT 16U +#define LPDDR4__DENALI_PI_15__PI_RESERVED2_WIDTH 1U +#define LPDDR4__DENALI_PI_15__PI_RESERVED2_WOCLR 0U +#define LPDDR4__DENALI_PI_15__PI_RESERVED2_WOSET 0U +#define LPDDR4__PI_RESERVED2__REG DENALI_PI_15 +#define LPDDR4__PI_RESERVED2__FLD LPDDR4__DENALI_PI_15__PI_RESERVED2 + +#define LPDDR4__DENALI_PI_16_READ_MASK 0x010FFFFFU +#define LPDDR4__DENALI_PI_16_WRITE_MASK 0x010FFFFFU +#define LPDDR4__DENALI_PI_16__PI_TREF_INTERVAL_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PI_16__PI_TREF_INTERVAL_SHIFT 0U +#define LPDDR4__DENALI_PI_16__PI_TREF_INTERVAL_WIDTH 20U +#define LPDDR4__PI_TREF_INTERVAL__REG DENALI_PI_16 +#define LPDDR4__PI_TREF_INTERVAL__FLD LPDDR4__DENALI_PI_16__PI_TREF_INTERVAL + +#define LPDDR4__DENALI_PI_16__PI_ON_DFIBUS_MASK 0x01000000U +#define LPDDR4__DENALI_PI_16__PI_ON_DFIBUS_SHIFT 24U +#define LPDDR4__DENALI_PI_16__PI_ON_DFIBUS_WIDTH 1U +#define LPDDR4__DENALI_PI_16__PI_ON_DFIBUS_WOCLR 0U +#define LPDDR4__DENALI_PI_16__PI_ON_DFIBUS_WOSET 0U +#define LPDDR4__PI_ON_DFIBUS__REG DENALI_PI_16 +#define LPDDR4__PI_ON_DFIBUS__FLD LPDDR4__DENALI_PI_16__PI_ON_DFIBUS + +#define LPDDR4__DENALI_PI_17_READ_MASK 0x01010001U +#define LPDDR4__DENALI_PI_17_WRITE_MASK 0x01010001U +#define LPDDR4__DENALI_PI_17__PI_DATA_RETENTION_MASK 0x00000001U +#define LPDDR4__DENALI_PI_17__PI_DATA_RETENTION_SHIFT 0U +#define LPDDR4__DENALI_PI_17__PI_DATA_RETENTION_WIDTH 1U +#define LPDDR4__DENALI_PI_17__PI_DATA_RETENTION_WOCLR 0U +#define LPDDR4__DENALI_PI_17__PI_DATA_RETENTION_WOSET 0U +#define LPDDR4__PI_DATA_RETENTION__REG DENALI_PI_17 +#define LPDDR4__PI_DATA_RETENTION__FLD LPDDR4__DENALI_PI_17__PI_DATA_RETENTION + +#define LPDDR4__DENALI_PI_17__PI_SWLVL_LOAD_MASK 0x00000100U +#define LPDDR4__DENALI_PI_17__PI_SWLVL_LOAD_SHIFT 8U +#define LPDDR4__DENALI_PI_17__PI_SWLVL_LOAD_WIDTH 1U +#define LPDDR4__DENALI_PI_17__PI_SWLVL_LOAD_WOCLR 0U +#define LPDDR4__DENALI_PI_17__PI_SWLVL_LOAD_WOSET 0U +#define LPDDR4__PI_SWLVL_LOAD__REG DENALI_PI_17 +#define LPDDR4__PI_SWLVL_LOAD__FLD LPDDR4__DENALI_PI_17__PI_SWLVL_LOAD + +#define LPDDR4__DENALI_PI_17__PI_SWLVL_OP_DONE_MASK 0x00010000U +#define LPDDR4__DENALI_PI_17__PI_SWLVL_OP_DONE_SHIFT 16U +#define LPDDR4__DENALI_PI_17__PI_SWLVL_OP_DONE_WIDTH 1U +#define LPDDR4__DENALI_PI_17__PI_SWLVL_OP_DONE_WOCLR 0U +#define LPDDR4__DENALI_PI_17__PI_SWLVL_OP_DONE_WOSET 0U +#define LPDDR4__PI_SWLVL_OP_DONE__REG DENALI_PI_17 +#define LPDDR4__PI_SWLVL_OP_DONE__FLD LPDDR4__DENALI_PI_17__PI_SWLVL_OP_DONE + +#define LPDDR4__DENALI_PI_17__PI_SW_WRLVL_RESP_0_MASK 0x01000000U +#define LPDDR4__DENALI_PI_17__PI_SW_WRLVL_RESP_0_SHIFT 24U +#define LPDDR4__DENALI_PI_17__PI_SW_WRLVL_RESP_0_WIDTH 1U +#define LPDDR4__DENALI_PI_17__PI_SW_WRLVL_RESP_0_WOCLR 0U +#define LPDDR4__DENALI_PI_17__PI_SW_WRLVL_RESP_0_WOSET 0U +#define LPDDR4__PI_SW_WRLVL_RESP_0__REG DENALI_PI_17 +#define LPDDR4__PI_SW_WRLVL_RESP_0__FLD LPDDR4__DENALI_PI_17__PI_SW_WRLVL_RESP_0 + +#define LPDDR4__DENALI_PI_18_READ_MASK 0x03010101U +#define LPDDR4__DENALI_PI_18_WRITE_MASK 0x03010101U +#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_1_MASK 0x00000001U +#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_1_SHIFT 0U +#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_1_WIDTH 1U +#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_1_WOCLR 0U +#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_1_WOSET 0U +#define LPDDR4__PI_SW_WRLVL_RESP_1__REG DENALI_PI_18 +#define LPDDR4__PI_SW_WRLVL_RESP_1__FLD LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_1 + +#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_2_MASK 0x00000100U +#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_2_SHIFT 8U +#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_2_WIDTH 1U +#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_2_WOCLR 0U +#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_2_WOSET 0U +#define LPDDR4__PI_SW_WRLVL_RESP_2__REG DENALI_PI_18 +#define LPDDR4__PI_SW_WRLVL_RESP_2__FLD LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_2 + +#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_3_MASK 0x00010000U +#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_3_SHIFT 16U +#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_3_WIDTH 1U +#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_3_WOCLR 0U +#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_3_WOSET 0U +#define LPDDR4__PI_SW_WRLVL_RESP_3__REG DENALI_PI_18 +#define LPDDR4__PI_SW_WRLVL_RESP_3__FLD LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_3 + +#define LPDDR4__DENALI_PI_18__PI_SW_RDLVL_RESP_0_MASK 0x03000000U +#define LPDDR4__DENALI_PI_18__PI_SW_RDLVL_RESP_0_SHIFT 24U +#define LPDDR4__DENALI_PI_18__PI_SW_RDLVL_RESP_0_WIDTH 2U +#define LPDDR4__PI_SW_RDLVL_RESP_0__REG DENALI_PI_18 +#define LPDDR4__PI_SW_RDLVL_RESP_0__FLD LPDDR4__DENALI_PI_18__PI_SW_RDLVL_RESP_0 + +#define LPDDR4__DENALI_PI_19_READ_MASK 0x03030303U +#define LPDDR4__DENALI_PI_19_WRITE_MASK 0x03030303U +#define LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_1_MASK 0x00000003U +#define LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_1_SHIFT 0U +#define LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_1_WIDTH 2U +#define LPDDR4__PI_SW_RDLVL_RESP_1__REG DENALI_PI_19 +#define LPDDR4__PI_SW_RDLVL_RESP_1__FLD LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_1 + +#define LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_2_MASK 0x00000300U +#define LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_2_SHIFT 8U +#define LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_2_WIDTH 2U +#define LPDDR4__PI_SW_RDLVL_RESP_2__REG DENALI_PI_19 +#define LPDDR4__PI_SW_RDLVL_RESP_2__FLD LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_2 + +#define LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_3_MASK 0x00030000U +#define LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_3_SHIFT 16U +#define LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_3_WIDTH 2U +#define LPDDR4__PI_SW_RDLVL_RESP_3__REG DENALI_PI_19 +#define LPDDR4__PI_SW_RDLVL_RESP_3__FLD LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_3 + +#define LPDDR4__DENALI_PI_19__PI_SW_CALVL_RESP_0_MASK 0x03000000U +#define LPDDR4__DENALI_PI_19__PI_SW_CALVL_RESP_0_SHIFT 24U +#define LPDDR4__DENALI_PI_19__PI_SW_CALVL_RESP_0_WIDTH 2U +#define LPDDR4__PI_SW_CALVL_RESP_0__REG DENALI_PI_19 +#define LPDDR4__PI_SW_CALVL_RESP_0__FLD LPDDR4__DENALI_PI_19__PI_SW_CALVL_RESP_0 + +#define LPDDR4__DENALI_PI_20_READ_MASK 0x00000007U +#define LPDDR4__DENALI_PI_20_WRITE_MASK 0x00000007U +#define LPDDR4__DENALI_PI_20__PI_SW_LEVELING_MODE_MASK 0x00000007U +#define LPDDR4__DENALI_PI_20__PI_SW_LEVELING_MODE_SHIFT 0U +#define LPDDR4__DENALI_PI_20__PI_SW_LEVELING_MODE_WIDTH 3U +#define LPDDR4__PI_SW_LEVELING_MODE__REG DENALI_PI_20 +#define LPDDR4__PI_SW_LEVELING_MODE__FLD LPDDR4__DENALI_PI_20__PI_SW_LEVELING_MODE + +#define LPDDR4__DENALI_PI_20__PI_SWLVL_START_MASK 0x00000100U +#define LPDDR4__DENALI_PI_20__PI_SWLVL_START_SHIFT 8U +#define LPDDR4__DENALI_PI_20__PI_SWLVL_START_WIDTH 1U +#define LPDDR4__DENALI_PI_20__PI_SWLVL_START_WOCLR 0U +#define LPDDR4__DENALI_PI_20__PI_SWLVL_START_WOSET 0U +#define LPDDR4__PI_SWLVL_START__REG DENALI_PI_20 +#define LPDDR4__PI_SWLVL_START__FLD LPDDR4__DENALI_PI_20__PI_SWLVL_START + +#define LPDDR4__DENALI_PI_20__PI_SWLVL_EXIT_MASK 0x00010000U +#define LPDDR4__DENALI_PI_20__PI_SWLVL_EXIT_SHIFT 16U +#define LPDDR4__DENALI_PI_20__PI_SWLVL_EXIT_WIDTH 1U +#define LPDDR4__DENALI_PI_20__PI_SWLVL_EXIT_WOCLR 0U +#define LPDDR4__DENALI_PI_20__PI_SWLVL_EXIT_WOSET 0U +#define LPDDR4__PI_SWLVL_EXIT__REG DENALI_PI_20 +#define LPDDR4__PI_SWLVL_EXIT__FLD LPDDR4__DENALI_PI_20__PI_SWLVL_EXIT + +#define LPDDR4__DENALI_PI_20__PI_SWLVL_WR_SLICE_0_MASK 0x01000000U +#define LPDDR4__DENALI_PI_20__PI_SWLVL_WR_SLICE_0_SHIFT 24U +#define LPDDR4__DENALI_PI_20__PI_SWLVL_WR_SLICE_0_WIDTH 1U +#define LPDDR4__DENALI_PI_20__PI_SWLVL_WR_SLICE_0_WOCLR 0U +#define LPDDR4__DENALI_PI_20__PI_SWLVL_WR_SLICE_0_WOSET 0U +#define LPDDR4__PI_SWLVL_WR_SLICE_0__REG DENALI_PI_20 +#define LPDDR4__PI_SWLVL_WR_SLICE_0__FLD LPDDR4__DENALI_PI_20__PI_SWLVL_WR_SLICE_0 + +#define LPDDR4__DENALI_PI_21_READ_MASK 0x00030000U +#define LPDDR4__DENALI_PI_21_WRITE_MASK 0x00030000U +#define LPDDR4__DENALI_PI_21__PI_SWLVL_RD_SLICE_0_MASK 0x00000001U +#define LPDDR4__DENALI_PI_21__PI_SWLVL_RD_SLICE_0_SHIFT 0U +#define LPDDR4__DENALI_PI_21__PI_SWLVL_RD_SLICE_0_WIDTH 1U +#define LPDDR4__DENALI_PI_21__PI_SWLVL_RD_SLICE_0_WOCLR 0U +#define LPDDR4__DENALI_PI_21__PI_SWLVL_RD_SLICE_0_WOSET 0U +#define LPDDR4__PI_SWLVL_RD_SLICE_0__REG DENALI_PI_21 +#define LPDDR4__PI_SWLVL_RD_SLICE_0__FLD LPDDR4__DENALI_PI_21__PI_SWLVL_RD_SLICE_0 + +#define LPDDR4__DENALI_PI_21__PI_SWLVL_VREF_UPDATE_SLICE_0_MASK 0x00000100U +#define LPDDR4__DENALI_PI_21__PI_SWLVL_VREF_UPDATE_SLICE_0_SHIFT 8U +#define LPDDR4__DENALI_PI_21__PI_SWLVL_VREF_UPDATE_SLICE_0_WIDTH 1U +#define LPDDR4__DENALI_PI_21__PI_SWLVL_VREF_UPDATE_SLICE_0_WOCLR 0U +#define LPDDR4__DENALI_PI_21__PI_SWLVL_VREF_UPDATE_SLICE_0_WOSET 0U +#define LPDDR4__PI_SWLVL_VREF_UPDATE_SLICE_0__REG DENALI_PI_21 +#define LPDDR4__PI_SWLVL_VREF_UPDATE_SLICE_0__FLD LPDDR4__DENALI_PI_21__PI_SWLVL_VREF_UPDATE_SLICE_0 + +#define LPDDR4__DENALI_PI_21__PI_SW_WDQLVL_RESP_0_MASK 0x00030000U +#define LPDDR4__DENALI_PI_21__PI_SW_WDQLVL_RESP_0_SHIFT 16U +#define LPDDR4__DENALI_PI_21__PI_SW_WDQLVL_RESP_0_WIDTH 2U +#define LPDDR4__PI_SW_WDQLVL_RESP_0__REG DENALI_PI_21 +#define LPDDR4__PI_SW_WDQLVL_RESP_0__FLD LPDDR4__DENALI_PI_21__PI_SW_WDQLVL_RESP_0 + +#define LPDDR4__DENALI_PI_21__PI_SWLVL_WR_SLICE_1_MASK 0x01000000U +#define LPDDR4__DENALI_PI_21__PI_SWLVL_WR_SLICE_1_SHIFT 24U +#define LPDDR4__DENALI_PI_21__PI_SWLVL_WR_SLICE_1_WIDTH 1U +#define LPDDR4__DENALI_PI_21__PI_SWLVL_WR_SLICE_1_WOCLR 0U +#define LPDDR4__DENALI_PI_21__PI_SWLVL_WR_SLICE_1_WOSET 0U +#define LPDDR4__PI_SWLVL_WR_SLICE_1__REG DENALI_PI_21 +#define LPDDR4__PI_SWLVL_WR_SLICE_1__FLD LPDDR4__DENALI_PI_21__PI_SWLVL_WR_SLICE_1 + +#define LPDDR4__DENALI_PI_22_READ_MASK 0x00030000U +#define LPDDR4__DENALI_PI_22_WRITE_MASK 0x00030000U +#define LPDDR4__DENALI_PI_22__PI_SWLVL_RD_SLICE_1_MASK 0x00000001U +#define LPDDR4__DENALI_PI_22__PI_SWLVL_RD_SLICE_1_SHIFT 0U +#define LPDDR4__DENALI_PI_22__PI_SWLVL_RD_SLICE_1_WIDTH 1U +#define LPDDR4__DENALI_PI_22__PI_SWLVL_RD_SLICE_1_WOCLR 0U +#define LPDDR4__DENALI_PI_22__PI_SWLVL_RD_SLICE_1_WOSET 0U +#define LPDDR4__PI_SWLVL_RD_SLICE_1__REG DENALI_PI_22 +#define LPDDR4__PI_SWLVL_RD_SLICE_1__FLD LPDDR4__DENALI_PI_22__PI_SWLVL_RD_SLICE_1 + +#define LPDDR4__DENALI_PI_22__PI_SWLVL_VREF_UPDATE_SLICE_1_MASK 0x00000100U +#define LPDDR4__DENALI_PI_22__PI_SWLVL_VREF_UPDATE_SLICE_1_SHIFT 8U +#define LPDDR4__DENALI_PI_22__PI_SWLVL_VREF_UPDATE_SLICE_1_WIDTH 1U +#define LPDDR4__DENALI_PI_22__PI_SWLVL_VREF_UPDATE_SLICE_1_WOCLR 0U +#define LPDDR4__DENALI_PI_22__PI_SWLVL_VREF_UPDATE_SLICE_1_WOSET 0U +#define LPDDR4__PI_SWLVL_VREF_UPDATE_SLICE_1__REG DENALI_PI_22 +#define LPDDR4__PI_SWLVL_VREF_UPDATE_SLICE_1__FLD LPDDR4__DENALI_PI_22__PI_SWLVL_VREF_UPDATE_SLICE_1 + +#define LPDDR4__DENALI_PI_22__PI_SW_WDQLVL_RESP_1_MASK 0x00030000U +#define LPDDR4__DENALI_PI_22__PI_SW_WDQLVL_RESP_1_SHIFT 16U +#define LPDDR4__DENALI_PI_22__PI_SW_WDQLVL_RESP_1_WIDTH 2U +#define LPDDR4__PI_SW_WDQLVL_RESP_1__REG DENALI_PI_22 +#define LPDDR4__PI_SW_WDQLVL_RESP_1__FLD LPDDR4__DENALI_PI_22__PI_SW_WDQLVL_RESP_1 + +#define LPDDR4__DENALI_PI_22__PI_SWLVL_WR_SLICE_2_MASK 0x01000000U +#define LPDDR4__DENALI_PI_22__PI_SWLVL_WR_SLICE_2_SHIFT 24U +#define LPDDR4__DENALI_PI_22__PI_SWLVL_WR_SLICE_2_WIDTH 1U +#define LPDDR4__DENALI_PI_22__PI_SWLVL_WR_SLICE_2_WOCLR 0U +#define LPDDR4__DENALI_PI_22__PI_SWLVL_WR_SLICE_2_WOSET 0U +#define LPDDR4__PI_SWLVL_WR_SLICE_2__REG DENALI_PI_22 +#define LPDDR4__PI_SWLVL_WR_SLICE_2__FLD LPDDR4__DENALI_PI_22__PI_SWLVL_WR_SLICE_2 + +#define LPDDR4__DENALI_PI_23_READ_MASK 0x00030000U +#define LPDDR4__DENALI_PI_23_WRITE_MASK 0x00030000U +#define LPDDR4__DENALI_PI_23__PI_SWLVL_RD_SLICE_2_MASK 0x00000001U +#define LPDDR4__DENALI_PI_23__PI_SWLVL_RD_SLICE_2_SHIFT 0U +#define LPDDR4__DENALI_PI_23__PI_SWLVL_RD_SLICE_2_WIDTH 1U +#define LPDDR4__DENALI_PI_23__PI_SWLVL_RD_SLICE_2_WOCLR 0U +#define LPDDR4__DENALI_PI_23__PI_SWLVL_RD_SLICE_2_WOSET 0U +#define LPDDR4__PI_SWLVL_RD_SLICE_2__REG DENALI_PI_23 +#define LPDDR4__PI_SWLVL_RD_SLICE_2__FLD LPDDR4__DENALI_PI_23__PI_SWLVL_RD_SLICE_2 + +#define LPDDR4__DENALI_PI_23__PI_SWLVL_VREF_UPDATE_SLICE_2_MASK 0x00000100U +#define LPDDR4__DENALI_PI_23__PI_SWLVL_VREF_UPDATE_SLICE_2_SHIFT 8U +#define LPDDR4__DENALI_PI_23__PI_SWLVL_VREF_UPDATE_SLICE_2_WIDTH 1U +#define LPDDR4__DENALI_PI_23__PI_SWLVL_VREF_UPDATE_SLICE_2_WOCLR 0U +#define LPDDR4__DENALI_PI_23__PI_SWLVL_VREF_UPDATE_SLICE_2_WOSET 0U +#define LPDDR4__PI_SWLVL_VREF_UPDATE_SLICE_2__REG DENALI_PI_23 +#define LPDDR4__PI_SWLVL_VREF_UPDATE_SLICE_2__FLD LPDDR4__DENALI_PI_23__PI_SWLVL_VREF_UPDATE_SLICE_2 + +#define LPDDR4__DENALI_PI_23__PI_SW_WDQLVL_RESP_2_MASK 0x00030000U +#define LPDDR4__DENALI_PI_23__PI_SW_WDQLVL_RESP_2_SHIFT 16U +#define LPDDR4__DENALI_PI_23__PI_SW_WDQLVL_RESP_2_WIDTH 2U +#define LPDDR4__PI_SW_WDQLVL_RESP_2__REG DENALI_PI_23 +#define LPDDR4__PI_SW_WDQLVL_RESP_2__FLD LPDDR4__DENALI_PI_23__PI_SW_WDQLVL_RESP_2 + +#define LPDDR4__DENALI_PI_23__PI_SWLVL_WR_SLICE_3_MASK 0x01000000U +#define LPDDR4__DENALI_PI_23__PI_SWLVL_WR_SLICE_3_SHIFT 24U +#define LPDDR4__DENALI_PI_23__PI_SWLVL_WR_SLICE_3_WIDTH 1U +#define LPDDR4__DENALI_PI_23__PI_SWLVL_WR_SLICE_3_WOCLR 0U +#define LPDDR4__DENALI_PI_23__PI_SWLVL_WR_SLICE_3_WOSET 0U +#define LPDDR4__PI_SWLVL_WR_SLICE_3__REG DENALI_PI_23 +#define LPDDR4__PI_SWLVL_WR_SLICE_3__FLD LPDDR4__DENALI_PI_23__PI_SWLVL_WR_SLICE_3 + +#define LPDDR4__DENALI_PI_24_READ_MASK 0x00030000U +#define LPDDR4__DENALI_PI_24_WRITE_MASK 0x00030000U +#define LPDDR4__DENALI_PI_24__PI_SWLVL_RD_SLICE_3_MASK 0x00000001U +#define LPDDR4__DENALI_PI_24__PI_SWLVL_RD_SLICE_3_SHIFT 0U +#define LPDDR4__DENALI_PI_24__PI_SWLVL_RD_SLICE_3_WIDTH 1U +#define LPDDR4__DENALI_PI_24__PI_SWLVL_RD_SLICE_3_WOCLR 0U +#define LPDDR4__DENALI_PI_24__PI_SWLVL_RD_SLICE_3_WOSET 0U +#define LPDDR4__PI_SWLVL_RD_SLICE_3__REG DENALI_PI_24 +#define LPDDR4__PI_SWLVL_RD_SLICE_3__FLD LPDDR4__DENALI_PI_24__PI_SWLVL_RD_SLICE_3 + +#define LPDDR4__DENALI_PI_24__PI_SWLVL_VREF_UPDATE_SLICE_3_MASK 0x00000100U +#define LPDDR4__DENALI_PI_24__PI_SWLVL_VREF_UPDATE_SLICE_3_SHIFT 8U +#define LPDDR4__DENALI_PI_24__PI_SWLVL_VREF_UPDATE_SLICE_3_WIDTH 1U +#define LPDDR4__DENALI_PI_24__PI_SWLVL_VREF_UPDATE_SLICE_3_WOCLR 0U +#define LPDDR4__DENALI_PI_24__PI_SWLVL_VREF_UPDATE_SLICE_3_WOSET 0U +#define LPDDR4__PI_SWLVL_VREF_UPDATE_SLICE_3__REG DENALI_PI_24 +#define LPDDR4__PI_SWLVL_VREF_UPDATE_SLICE_3__FLD LPDDR4__DENALI_PI_24__PI_SWLVL_VREF_UPDATE_SLICE_3 + +#define LPDDR4__DENALI_PI_24__PI_SW_WDQLVL_RESP_3_MASK 0x00030000U +#define LPDDR4__DENALI_PI_24__PI_SW_WDQLVL_RESP_3_SHIFT 16U +#define LPDDR4__DENALI_PI_24__PI_SW_WDQLVL_RESP_3_WIDTH 2U +#define LPDDR4__PI_SW_WDQLVL_RESP_3__REG DENALI_PI_24 +#define LPDDR4__PI_SW_WDQLVL_RESP_3__FLD LPDDR4__DENALI_PI_24__PI_SW_WDQLVL_RESP_3 + +#define LPDDR4__DENALI_PI_24__PI_SWLVL_SM2_START_MASK 0x01000000U +#define LPDDR4__DENALI_PI_24__PI_SWLVL_SM2_START_SHIFT 24U +#define LPDDR4__DENALI_PI_24__PI_SWLVL_SM2_START_WIDTH 1U +#define LPDDR4__DENALI_PI_24__PI_SWLVL_SM2_START_WOCLR 0U +#define LPDDR4__DENALI_PI_24__PI_SWLVL_SM2_START_WOSET 0U +#define LPDDR4__PI_SWLVL_SM2_START__REG DENALI_PI_24 +#define LPDDR4__PI_SWLVL_SM2_START__FLD LPDDR4__DENALI_PI_24__PI_SWLVL_SM2_START + +#define LPDDR4__DENALI_PI_25_READ_MASK 0x01000000U +#define LPDDR4__DENALI_PI_25_WRITE_MASK 0x01000000U +#define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_WR_MASK 0x00000001U +#define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_WR_SHIFT 0U +#define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_WR_WIDTH 1U +#define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_WR_WOCLR 0U +#define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_WR_WOSET 0U +#define LPDDR4__PI_SWLVL_SM2_WR__REG DENALI_PI_25 +#define LPDDR4__PI_SWLVL_SM2_WR__FLD LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_WR + +#define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_RD_MASK 0x00000100U +#define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_RD_SHIFT 8U +#define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_RD_WIDTH 1U +#define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_RD_WOCLR 0U +#define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_RD_WOSET 0U +#define LPDDR4__PI_SWLVL_SM2_RD__REG DENALI_PI_25 +#define LPDDR4__PI_SWLVL_SM2_RD__FLD LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_RD + +#define LPDDR4__DENALI_PI_25__PI_SEQUENTIAL_LVL_REQ_MASK 0x00010000U +#define LPDDR4__DENALI_PI_25__PI_SEQUENTIAL_LVL_REQ_SHIFT 16U +#define LPDDR4__DENALI_PI_25__PI_SEQUENTIAL_LVL_REQ_WIDTH 1U +#define LPDDR4__DENALI_PI_25__PI_SEQUENTIAL_LVL_REQ_WOCLR 0U +#define LPDDR4__DENALI_PI_25__PI_SEQUENTIAL_LVL_REQ_WOSET 0U +#define LPDDR4__PI_SEQUENTIAL_LVL_REQ__REG DENALI_PI_25 +#define LPDDR4__PI_SEQUENTIAL_LVL_REQ__FLD LPDDR4__DENALI_PI_25__PI_SEQUENTIAL_LVL_REQ + +#define LPDDR4__DENALI_PI_25__PI_DFS_PERIOD_EN_MASK 0x01000000U +#define LPDDR4__DENALI_PI_25__PI_DFS_PERIOD_EN_SHIFT 24U +#define LPDDR4__DENALI_PI_25__PI_DFS_PERIOD_EN_WIDTH 1U +#define LPDDR4__DENALI_PI_25__PI_DFS_PERIOD_EN_WOCLR 0U +#define LPDDR4__DENALI_PI_25__PI_DFS_PERIOD_EN_WOSET 0U +#define LPDDR4__PI_DFS_PERIOD_EN__REG DENALI_PI_25 +#define LPDDR4__PI_DFS_PERIOD_EN__FLD LPDDR4__DENALI_PI_25__PI_DFS_PERIOD_EN + +#define LPDDR4__DENALI_PI_26_READ_MASK 0x00010101U +#define LPDDR4__DENALI_PI_26_WRITE_MASK 0x00010101U +#define LPDDR4__DENALI_PI_26__PI_SRE_PERIOD_EN_MASK 0x00000001U +#define LPDDR4__DENALI_PI_26__PI_SRE_PERIOD_EN_SHIFT 0U +#define LPDDR4__DENALI_PI_26__PI_SRE_PERIOD_EN_WIDTH 1U +#define LPDDR4__DENALI_PI_26__PI_SRE_PERIOD_EN_WOCLR 0U +#define LPDDR4__DENALI_PI_26__PI_SRE_PERIOD_EN_WOSET 0U +#define LPDDR4__PI_SRE_PERIOD_EN__REG DENALI_PI_26 +#define LPDDR4__PI_SRE_PERIOD_EN__FLD LPDDR4__DENALI_PI_26__PI_SRE_PERIOD_EN + +#define LPDDR4__DENALI_PI_26__PI_DFI40_POLARITY_MASK 0x00000100U +#define LPDDR4__DENALI_PI_26__PI_DFI40_POLARITY_SHIFT 8U +#define LPDDR4__DENALI_PI_26__PI_DFI40_POLARITY_WIDTH 1U +#define LPDDR4__DENALI_PI_26__PI_DFI40_POLARITY_WOCLR 0U +#define LPDDR4__DENALI_PI_26__PI_DFI40_POLARITY_WOSET 0U +#define LPDDR4__PI_DFI40_POLARITY__REG DENALI_PI_26 +#define LPDDR4__PI_DFI40_POLARITY__FLD LPDDR4__DENALI_PI_26__PI_DFI40_POLARITY + +#define LPDDR4__DENALI_PI_26__PI_16BIT_DRAM_CONNECT_MASK 0x00010000U +#define LPDDR4__DENALI_PI_26__PI_16BIT_DRAM_CONNECT_SHIFT 16U +#define LPDDR4__DENALI_PI_26__PI_16BIT_DRAM_CONNECT_WIDTH 1U +#define LPDDR4__DENALI_PI_26__PI_16BIT_DRAM_CONNECT_WOCLR 0U +#define LPDDR4__DENALI_PI_26__PI_16BIT_DRAM_CONNECT_WOSET 0U +#define LPDDR4__PI_16BIT_DRAM_CONNECT__REG DENALI_PI_26 +#define LPDDR4__PI_16BIT_DRAM_CONNECT__FLD LPDDR4__DENALI_PI_26__PI_16BIT_DRAM_CONNECT + +#define LPDDR4__DENALI_PI_26__PI_WRLVL_REQ_MASK 0x01000000U +#define LPDDR4__DENALI_PI_26__PI_WRLVL_REQ_SHIFT 24U +#define LPDDR4__DENALI_PI_26__PI_WRLVL_REQ_WIDTH 1U +#define LPDDR4__DENALI_PI_26__PI_WRLVL_REQ_WOCLR 0U +#define LPDDR4__DENALI_PI_26__PI_WRLVL_REQ_WOSET 0U +#define LPDDR4__PI_WRLVL_REQ__REG DENALI_PI_26 +#define LPDDR4__PI_WRLVL_REQ__FLD LPDDR4__DENALI_PI_26__PI_WRLVL_REQ + +#define LPDDR4__DENALI_PI_27_READ_MASK 0x003F3F03U +#define LPDDR4__DENALI_PI_27_WRITE_MASK 0x003F3F03U +#define LPDDR4__DENALI_PI_27__PI_WRLVL_CS_MASK 0x00000003U +#define LPDDR4__DENALI_PI_27__PI_WRLVL_CS_SHIFT 0U +#define LPDDR4__DENALI_PI_27__PI_WRLVL_CS_WIDTH 2U +#define LPDDR4__PI_WRLVL_CS__REG DENALI_PI_27 +#define LPDDR4__PI_WRLVL_CS__FLD LPDDR4__DENALI_PI_27__PI_WRLVL_CS + +#define LPDDR4__DENALI_PI_27__PI_WLDQSEN_MASK 0x00003F00U +#define LPDDR4__DENALI_PI_27__PI_WLDQSEN_SHIFT 8U +#define LPDDR4__DENALI_PI_27__PI_WLDQSEN_WIDTH 6U +#define LPDDR4__PI_WLDQSEN__REG DENALI_PI_27 +#define LPDDR4__PI_WLDQSEN__FLD LPDDR4__DENALI_PI_27__PI_WLDQSEN + +#define LPDDR4__DENALI_PI_27__PI_WLMRD_MASK 0x003F0000U +#define LPDDR4__DENALI_PI_27__PI_WLMRD_SHIFT 16U +#define LPDDR4__DENALI_PI_27__PI_WLMRD_WIDTH 6U +#define LPDDR4__PI_WLMRD__REG DENALI_PI_27 +#define LPDDR4__PI_WLMRD__FLD LPDDR4__DENALI_PI_27__PI_WLMRD + +#define LPDDR4__DENALI_PI_28_READ_MASK 0x0101FFFFU +#define LPDDR4__DENALI_PI_28_WRITE_MASK 0x0101FFFFU +#define LPDDR4__DENALI_PI_28__PI_WRLVL_INTERVAL_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PI_28__PI_WRLVL_INTERVAL_SHIFT 0U +#define LPDDR4__DENALI_PI_28__PI_WRLVL_INTERVAL_WIDTH 16U +#define LPDDR4__PI_WRLVL_INTERVAL__REG DENALI_PI_28 +#define LPDDR4__PI_WRLVL_INTERVAL__FLD LPDDR4__DENALI_PI_28__PI_WRLVL_INTERVAL + +#define LPDDR4__DENALI_PI_28__PI_WRLVL_PERIODIC_MASK 0x00010000U +#define LPDDR4__DENALI_PI_28__PI_WRLVL_PERIODIC_SHIFT 16U +#define LPDDR4__DENALI_PI_28__PI_WRLVL_PERIODIC_WIDTH 1U +#define LPDDR4__DENALI_PI_28__PI_WRLVL_PERIODIC_WOCLR 0U +#define LPDDR4__DENALI_PI_28__PI_WRLVL_PERIODIC_WOSET 0U +#define LPDDR4__PI_WRLVL_PERIODIC__REG DENALI_PI_28 +#define LPDDR4__PI_WRLVL_PERIODIC__FLD LPDDR4__DENALI_PI_28__PI_WRLVL_PERIODIC + +#define LPDDR4__DENALI_PI_28__PI_WRLVL_ON_SREF_EXIT_MASK 0x01000000U +#define LPDDR4__DENALI_PI_28__PI_WRLVL_ON_SREF_EXIT_SHIFT 24U +#define LPDDR4__DENALI_PI_28__PI_WRLVL_ON_SREF_EXIT_WIDTH 1U +#define LPDDR4__DENALI_PI_28__PI_WRLVL_ON_SREF_EXIT_WOCLR 0U +#define LPDDR4__DENALI_PI_28__PI_WRLVL_ON_SREF_EXIT_WOSET 0U +#define LPDDR4__PI_WRLVL_ON_SREF_EXIT__REG DENALI_PI_28 +#define LPDDR4__PI_WRLVL_ON_SREF_EXIT__FLD LPDDR4__DENALI_PI_28__PI_WRLVL_ON_SREF_EXIT + +#define LPDDR4__DENALI_PI_29_READ_MASK 0x0F010F01U +#define LPDDR4__DENALI_PI_29_WRITE_MASK 0x0F010F01U +#define LPDDR4__DENALI_PI_29__PI_WRLVL_DISABLE_DFS_MASK 0x00000001U +#define LPDDR4__DENALI_PI_29__PI_WRLVL_DISABLE_DFS_SHIFT 0U +#define LPDDR4__DENALI_PI_29__PI_WRLVL_DISABLE_DFS_WIDTH 1U +#define LPDDR4__DENALI_PI_29__PI_WRLVL_DISABLE_DFS_WOCLR 0U +#define LPDDR4__DENALI_PI_29__PI_WRLVL_DISABLE_DFS_WOSET 0U +#define LPDDR4__PI_WRLVL_DISABLE_DFS__REG DENALI_PI_29 +#define LPDDR4__PI_WRLVL_DISABLE_DFS__FLD LPDDR4__DENALI_PI_29__PI_WRLVL_DISABLE_DFS + +#define LPDDR4__DENALI_PI_29__PI_WRLVL_RESP_MASK_MASK 0x00000F00U +#define LPDDR4__DENALI_PI_29__PI_WRLVL_RESP_MASK_SHIFT 8U +#define LPDDR4__DENALI_PI_29__PI_WRLVL_RESP_MASK_WIDTH 4U +#define LPDDR4__PI_WRLVL_RESP_MASK__REG DENALI_PI_29 +#define LPDDR4__PI_WRLVL_RESP_MASK__FLD LPDDR4__DENALI_PI_29__PI_WRLVL_RESP_MASK + +#define LPDDR4__DENALI_PI_29__PI_WRLVL_ROTATE_MASK 0x00010000U +#define LPDDR4__DENALI_PI_29__PI_WRLVL_ROTATE_SHIFT 16U +#define LPDDR4__DENALI_PI_29__PI_WRLVL_ROTATE_WIDTH 1U +#define LPDDR4__DENALI_PI_29__PI_WRLVL_ROTATE_WOCLR 0U +#define LPDDR4__DENALI_PI_29__PI_WRLVL_ROTATE_WOSET 0U +#define LPDDR4__PI_WRLVL_ROTATE__REG DENALI_PI_29 +#define LPDDR4__PI_WRLVL_ROTATE__FLD LPDDR4__DENALI_PI_29__PI_WRLVL_ROTATE + +#define LPDDR4__DENALI_PI_29__PI_WRLVL_CS_MAP_MASK 0x0F000000U +#define LPDDR4__DENALI_PI_29__PI_WRLVL_CS_MAP_SHIFT 24U +#define LPDDR4__DENALI_PI_29__PI_WRLVL_CS_MAP_WIDTH 4U +#define LPDDR4__PI_WRLVL_CS_MAP__REG DENALI_PI_29 +#define LPDDR4__PI_WRLVL_CS_MAP__FLD LPDDR4__DENALI_PI_29__PI_WRLVL_CS_MAP + +#define LPDDR4__DENALI_PI_30_READ_MASK 0x0000FF01U +#define LPDDR4__DENALI_PI_30_WRITE_MASK 0x0000FF01U +#define LPDDR4__DENALI_PI_30__PI_WRLVL_ERROR_STATUS_MASK 0x00000001U +#define LPDDR4__DENALI_PI_30__PI_WRLVL_ERROR_STATUS_SHIFT 0U +#define LPDDR4__DENALI_PI_30__PI_WRLVL_ERROR_STATUS_WIDTH 1U +#define LPDDR4__DENALI_PI_30__PI_WRLVL_ERROR_STATUS_WOCLR 0U +#define LPDDR4__DENALI_PI_30__PI_WRLVL_ERROR_STATUS_WOSET 0U +#define LPDDR4__PI_WRLVL_ERROR_STATUS__REG DENALI_PI_30 +#define LPDDR4__PI_WRLVL_ERROR_STATUS__FLD LPDDR4__DENALI_PI_30__PI_WRLVL_ERROR_STATUS + +#define LPDDR4__DENALI_PI_30__PI_TDFI_WRLVL_EN_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_30__PI_TDFI_WRLVL_EN_SHIFT 8U +#define LPDDR4__DENALI_PI_30__PI_TDFI_WRLVL_EN_WIDTH 8U +#define LPDDR4__PI_TDFI_WRLVL_EN__REG DENALI_PI_30 +#define LPDDR4__PI_TDFI_WRLVL_EN__FLD LPDDR4__DENALI_PI_30__PI_TDFI_WRLVL_EN + +#define LPDDR4__DENALI_PI_31_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_31_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_31__PI_TDFI_WRLVL_RESP_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_31__PI_TDFI_WRLVL_RESP_SHIFT 0U +#define LPDDR4__DENALI_PI_31__PI_TDFI_WRLVL_RESP_WIDTH 32U +#define LPDDR4__PI_TDFI_WRLVL_RESP__REG DENALI_PI_31 +#define LPDDR4__PI_TDFI_WRLVL_RESP__FLD LPDDR4__DENALI_PI_31__PI_TDFI_WRLVL_RESP + +#define LPDDR4__DENALI_PI_32_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_32_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_32__PI_TDFI_WRLVL_MAX_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_32__PI_TDFI_WRLVL_MAX_SHIFT 0U +#define LPDDR4__DENALI_PI_32__PI_TDFI_WRLVL_MAX_WIDTH 32U +#define LPDDR4__PI_TDFI_WRLVL_MAX__REG DENALI_PI_32 +#define LPDDR4__PI_TDFI_WRLVL_MAX__FLD LPDDR4__DENALI_PI_32__PI_TDFI_WRLVL_MAX + +#define LPDDR4__DENALI_PI_33_READ_MASK 0x0F0F0F1FU +#define LPDDR4__DENALI_PI_33_WRITE_MASK 0x0F0F0F1FU +#define LPDDR4__DENALI_PI_33__PI_WRLVL_STROBE_NUM_MASK 0x0000001FU +#define LPDDR4__DENALI_PI_33__PI_WRLVL_STROBE_NUM_SHIFT 0U +#define LPDDR4__DENALI_PI_33__PI_WRLVL_STROBE_NUM_WIDTH 5U +#define LPDDR4__PI_WRLVL_STROBE_NUM__REG DENALI_PI_33 +#define LPDDR4__PI_WRLVL_STROBE_NUM__FLD LPDDR4__DENALI_PI_33__PI_WRLVL_STROBE_NUM + +#define LPDDR4__DENALI_PI_33__PI_TODTH_WR_MASK 0x00000F00U +#define LPDDR4__DENALI_PI_33__PI_TODTH_WR_SHIFT 8U +#define LPDDR4__DENALI_PI_33__PI_TODTH_WR_WIDTH 4U +#define LPDDR4__PI_TODTH_WR__REG DENALI_PI_33 +#define LPDDR4__PI_TODTH_WR__FLD LPDDR4__DENALI_PI_33__PI_TODTH_WR + +#define LPDDR4__DENALI_PI_33__PI_TODTH_RD_MASK 0x000F0000U +#define LPDDR4__DENALI_PI_33__PI_TODTH_RD_SHIFT 16U +#define LPDDR4__DENALI_PI_33__PI_TODTH_RD_WIDTH 4U +#define LPDDR4__PI_TODTH_RD__REG DENALI_PI_33 +#define LPDDR4__PI_TODTH_RD__FLD LPDDR4__DENALI_PI_33__PI_TODTH_RD + +#define LPDDR4__DENALI_PI_33__PI_ODT_VALUE_MASK 0x0F000000U +#define LPDDR4__DENALI_PI_33__PI_ODT_VALUE_SHIFT 24U +#define LPDDR4__DENALI_PI_33__PI_ODT_VALUE_WIDTH 4U +#define LPDDR4__PI_ODT_VALUE__REG DENALI_PI_33 +#define LPDDR4__PI_ODT_VALUE__FLD LPDDR4__DENALI_PI_33__PI_ODT_VALUE + +#define LPDDR4__DENALI_PI_34_READ_MASK 0x00030000U +#define LPDDR4__DENALI_PI_34_WRITE_MASK 0x00030000U +#define LPDDR4__DENALI_PI_34__PI_RDLVL_REQ_MASK 0x00000001U +#define LPDDR4__DENALI_PI_34__PI_RDLVL_REQ_SHIFT 0U +#define LPDDR4__DENALI_PI_34__PI_RDLVL_REQ_WIDTH 1U +#define LPDDR4__DENALI_PI_34__PI_RDLVL_REQ_WOCLR 0U +#define LPDDR4__DENALI_PI_34__PI_RDLVL_REQ_WOSET 0U +#define LPDDR4__PI_RDLVL_REQ__REG DENALI_PI_34 +#define LPDDR4__PI_RDLVL_REQ__FLD LPDDR4__DENALI_PI_34__PI_RDLVL_REQ + +#define LPDDR4__DENALI_PI_34__PI_RDLVL_GATE_REQ_MASK 0x00000100U +#define LPDDR4__DENALI_PI_34__PI_RDLVL_GATE_REQ_SHIFT 8U +#define LPDDR4__DENALI_PI_34__PI_RDLVL_GATE_REQ_WIDTH 1U +#define LPDDR4__DENALI_PI_34__PI_RDLVL_GATE_REQ_WOCLR 0U +#define LPDDR4__DENALI_PI_34__PI_RDLVL_GATE_REQ_WOSET 0U +#define LPDDR4__PI_RDLVL_GATE_REQ__REG DENALI_PI_34 +#define LPDDR4__PI_RDLVL_GATE_REQ__FLD LPDDR4__DENALI_PI_34__PI_RDLVL_GATE_REQ + +#define LPDDR4__DENALI_PI_34__PI_RDLVL_CS_MASK 0x00030000U +#define LPDDR4__DENALI_PI_34__PI_RDLVL_CS_SHIFT 16U +#define LPDDR4__DENALI_PI_34__PI_RDLVL_CS_WIDTH 2U +#define LPDDR4__PI_RDLVL_CS__REG DENALI_PI_34 +#define LPDDR4__PI_RDLVL_CS__FLD LPDDR4__DENALI_PI_34__PI_RDLVL_CS + +#define LPDDR4__DENALI_PI_35_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_35_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_35__PI_RDLVL_PAT_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_35__PI_RDLVL_PAT_0_SHIFT 0U +#define LPDDR4__DENALI_PI_35__PI_RDLVL_PAT_0_WIDTH 32U +#define LPDDR4__PI_RDLVL_PAT_0__REG DENALI_PI_35 +#define LPDDR4__PI_RDLVL_PAT_0__FLD LPDDR4__DENALI_PI_35__PI_RDLVL_PAT_0 + +#define LPDDR4__DENALI_PI_36_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_36_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_36__PI_RDLVL_PAT_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_36__PI_RDLVL_PAT_1_SHIFT 0U +#define LPDDR4__DENALI_PI_36__PI_RDLVL_PAT_1_WIDTH 32U +#define LPDDR4__PI_RDLVL_PAT_1__REG DENALI_PI_36 +#define LPDDR4__PI_RDLVL_PAT_1__FLD LPDDR4__DENALI_PI_36__PI_RDLVL_PAT_1 + +#define LPDDR4__DENALI_PI_37_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_37_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_37__PI_RDLVL_PAT_2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_37__PI_RDLVL_PAT_2_SHIFT 0U +#define LPDDR4__DENALI_PI_37__PI_RDLVL_PAT_2_WIDTH 32U +#define LPDDR4__PI_RDLVL_PAT_2__REG DENALI_PI_37 +#define LPDDR4__PI_RDLVL_PAT_2__FLD LPDDR4__DENALI_PI_37__PI_RDLVL_PAT_2 + +#define LPDDR4__DENALI_PI_38_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_38_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_38__PI_RDLVL_PAT_3_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_38__PI_RDLVL_PAT_3_SHIFT 0U +#define LPDDR4__DENALI_PI_38__PI_RDLVL_PAT_3_WIDTH 32U +#define LPDDR4__PI_RDLVL_PAT_3__REG DENALI_PI_38 +#define LPDDR4__PI_RDLVL_PAT_3__FLD LPDDR4__DENALI_PI_38__PI_RDLVL_PAT_3 + +#define LPDDR4__DENALI_PI_39_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_39_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_39__PI_RDLVL_PAT_4_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_39__PI_RDLVL_PAT_4_SHIFT 0U +#define LPDDR4__DENALI_PI_39__PI_RDLVL_PAT_4_WIDTH 32U +#define LPDDR4__PI_RDLVL_PAT_4__REG DENALI_PI_39 +#define LPDDR4__PI_RDLVL_PAT_4__FLD LPDDR4__DENALI_PI_39__PI_RDLVL_PAT_4 + +#define LPDDR4__DENALI_PI_40_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_40_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_40__PI_RDLVL_PAT_5_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_40__PI_RDLVL_PAT_5_SHIFT 0U +#define LPDDR4__DENALI_PI_40__PI_RDLVL_PAT_5_WIDTH 32U +#define LPDDR4__PI_RDLVL_PAT_5__REG DENALI_PI_40 +#define LPDDR4__PI_RDLVL_PAT_5__FLD LPDDR4__DENALI_PI_40__PI_RDLVL_PAT_5 + +#define LPDDR4__DENALI_PI_41_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_41_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_41__PI_RDLVL_PAT_6_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_41__PI_RDLVL_PAT_6_SHIFT 0U +#define LPDDR4__DENALI_PI_41__PI_RDLVL_PAT_6_WIDTH 32U +#define LPDDR4__PI_RDLVL_PAT_6__REG DENALI_PI_41 +#define LPDDR4__PI_RDLVL_PAT_6__FLD LPDDR4__DENALI_PI_41__PI_RDLVL_PAT_6 + +#define LPDDR4__DENALI_PI_42_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_42_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_42__PI_RDLVL_PAT_7_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_42__PI_RDLVL_PAT_7_SHIFT 0U +#define LPDDR4__DENALI_PI_42__PI_RDLVL_PAT_7_WIDTH 32U +#define LPDDR4__PI_RDLVL_PAT_7__REG DENALI_PI_42 +#define LPDDR4__PI_RDLVL_PAT_7__FLD LPDDR4__DENALI_PI_42__PI_RDLVL_PAT_7 + +#define LPDDR4__DENALI_PI_43_READ_MASK 0x0101010FU +#define LPDDR4__DENALI_PI_43_WRITE_MASK 0x0101010FU +#define LPDDR4__DENALI_PI_43__PI_RDLVL_SEQ_EN_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_43__PI_RDLVL_SEQ_EN_SHIFT 0U +#define LPDDR4__DENALI_PI_43__PI_RDLVL_SEQ_EN_WIDTH 4U +#define LPDDR4__PI_RDLVL_SEQ_EN__REG DENALI_PI_43 +#define LPDDR4__PI_RDLVL_SEQ_EN__FLD LPDDR4__DENALI_PI_43__PI_RDLVL_SEQ_EN + +#define LPDDR4__DENALI_PI_43__PI_RDLVL_PERIODIC_MASK 0x00000100U +#define LPDDR4__DENALI_PI_43__PI_RDLVL_PERIODIC_SHIFT 8U +#define LPDDR4__DENALI_PI_43__PI_RDLVL_PERIODIC_WIDTH 1U +#define LPDDR4__DENALI_PI_43__PI_RDLVL_PERIODIC_WOCLR 0U +#define LPDDR4__DENALI_PI_43__PI_RDLVL_PERIODIC_WOSET 0U +#define LPDDR4__PI_RDLVL_PERIODIC__REG DENALI_PI_43 +#define LPDDR4__PI_RDLVL_PERIODIC__FLD LPDDR4__DENALI_PI_43__PI_RDLVL_PERIODIC + +#define LPDDR4__DENALI_PI_43__PI_RDLVL_ON_SREF_EXIT_MASK 0x00010000U +#define LPDDR4__DENALI_PI_43__PI_RDLVL_ON_SREF_EXIT_SHIFT 16U +#define LPDDR4__DENALI_PI_43__PI_RDLVL_ON_SREF_EXIT_WIDTH 1U +#define LPDDR4__DENALI_PI_43__PI_RDLVL_ON_SREF_EXIT_WOCLR 0U +#define LPDDR4__DENALI_PI_43__PI_RDLVL_ON_SREF_EXIT_WOSET 0U +#define LPDDR4__PI_RDLVL_ON_SREF_EXIT__REG DENALI_PI_43 +#define LPDDR4__PI_RDLVL_ON_SREF_EXIT__FLD LPDDR4__DENALI_PI_43__PI_RDLVL_ON_SREF_EXIT + +#define LPDDR4__DENALI_PI_43__PI_RDLVL_DISABLE_DFS_MASK 0x01000000U +#define LPDDR4__DENALI_PI_43__PI_RDLVL_DISABLE_DFS_SHIFT 24U +#define LPDDR4__DENALI_PI_43__PI_RDLVL_DISABLE_DFS_WIDTH 1U +#define LPDDR4__DENALI_PI_43__PI_RDLVL_DISABLE_DFS_WOCLR 0U +#define LPDDR4__DENALI_PI_43__PI_RDLVL_DISABLE_DFS_WOSET 0U +#define LPDDR4__PI_RDLVL_DISABLE_DFS__REG DENALI_PI_43 +#define LPDDR4__PI_RDLVL_DISABLE_DFS__FLD LPDDR4__DENALI_PI_43__PI_RDLVL_DISABLE_DFS + +#define LPDDR4__DENALI_PI_44_READ_MASK 0x01010101U +#define LPDDR4__DENALI_PI_44_WRITE_MASK 0x01010101U +#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_PERIODIC_MASK 0x00000001U +#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_PERIODIC_SHIFT 0U +#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_PERIODIC_WIDTH 1U +#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_PERIODIC_WOCLR 0U +#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_PERIODIC_WOSET 0U +#define LPDDR4__PI_RDLVL_GATE_PERIODIC__REG DENALI_PI_44 +#define LPDDR4__PI_RDLVL_GATE_PERIODIC__FLD LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_PERIODIC + +#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_ON_SREF_EXIT_MASK 0x00000100U +#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_ON_SREF_EXIT_SHIFT 8U +#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_ON_SREF_EXIT_WIDTH 1U +#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_ON_SREF_EXIT_WOCLR 0U +#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_ON_SREF_EXIT_WOSET 0U +#define LPDDR4__PI_RDLVL_GATE_ON_SREF_EXIT__REG DENALI_PI_44 +#define LPDDR4__PI_RDLVL_GATE_ON_SREF_EXIT__FLD LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_ON_SREF_EXIT + +#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_DISABLE_DFS_MASK 0x00010000U +#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_DISABLE_DFS_SHIFT 16U +#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_DISABLE_DFS_WIDTH 1U +#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_DISABLE_DFS_WOCLR 0U +#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_DISABLE_DFS_WOSET 0U +#define LPDDR4__PI_RDLVL_GATE_DISABLE_DFS__REG DENALI_PI_44 +#define LPDDR4__PI_RDLVL_GATE_DISABLE_DFS__FLD LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_DISABLE_DFS + +#define LPDDR4__DENALI_PI_44__PI_RDLVL_ROTATE_MASK 0x01000000U +#define LPDDR4__DENALI_PI_44__PI_RDLVL_ROTATE_SHIFT 24U +#define LPDDR4__DENALI_PI_44__PI_RDLVL_ROTATE_WIDTH 1U +#define LPDDR4__DENALI_PI_44__PI_RDLVL_ROTATE_WOCLR 0U +#define LPDDR4__DENALI_PI_44__PI_RDLVL_ROTATE_WOSET 0U +#define LPDDR4__PI_RDLVL_ROTATE__REG DENALI_PI_44 +#define LPDDR4__PI_RDLVL_ROTATE__FLD LPDDR4__DENALI_PI_44__PI_RDLVL_ROTATE + +#define LPDDR4__DENALI_PI_45_READ_MASK 0x000F0F01U +#define LPDDR4__DENALI_PI_45_WRITE_MASK 0x000F0F01U +#define LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_ROTATE_MASK 0x00000001U +#define LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_ROTATE_SHIFT 0U +#define LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_ROTATE_WIDTH 1U +#define LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_ROTATE_WOCLR 0U +#define LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_ROTATE_WOSET 0U +#define LPDDR4__PI_RDLVL_GATE_ROTATE__REG DENALI_PI_45 +#define LPDDR4__PI_RDLVL_GATE_ROTATE__FLD LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_ROTATE + +#define LPDDR4__DENALI_PI_45__PI_RDLVL_CS_MAP_MASK 0x00000F00U +#define LPDDR4__DENALI_PI_45__PI_RDLVL_CS_MAP_SHIFT 8U +#define LPDDR4__DENALI_PI_45__PI_RDLVL_CS_MAP_WIDTH 4U +#define LPDDR4__PI_RDLVL_CS_MAP__REG DENALI_PI_45 +#define LPDDR4__PI_RDLVL_CS_MAP__FLD LPDDR4__DENALI_PI_45__PI_RDLVL_CS_MAP + +#define LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_CS_MAP_MASK 0x000F0000U +#define LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_CS_MAP_SHIFT 16U +#define LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_CS_MAP_WIDTH 4U +#define LPDDR4__PI_RDLVL_GATE_CS_MAP__REG DENALI_PI_45 +#define LPDDR4__PI_RDLVL_GATE_CS_MAP__FLD LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_CS_MAP + +#define LPDDR4__DENALI_PI_46_READ_MASK 0x000003FFU +#define LPDDR4__DENALI_PI_46_WRITE_MASK 0x000003FFU +#define LPDDR4__DENALI_PI_46__PI_TDFI_RDLVL_RR_MASK 0x000003FFU +#define LPDDR4__DENALI_PI_46__PI_TDFI_RDLVL_RR_SHIFT 0U +#define LPDDR4__DENALI_PI_46__PI_TDFI_RDLVL_RR_WIDTH 10U +#define LPDDR4__PI_TDFI_RDLVL_RR__REG DENALI_PI_46 +#define LPDDR4__PI_TDFI_RDLVL_RR__FLD LPDDR4__DENALI_PI_46__PI_TDFI_RDLVL_RR + +#define LPDDR4__DENALI_PI_47_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_47_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_47__PI_TDFI_RDLVL_RESP_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_47__PI_TDFI_RDLVL_RESP_SHIFT 0U +#define LPDDR4__DENALI_PI_47__PI_TDFI_RDLVL_RESP_WIDTH 32U +#define LPDDR4__PI_TDFI_RDLVL_RESP__REG DENALI_PI_47 +#define LPDDR4__PI_TDFI_RDLVL_RESP__FLD LPDDR4__DENALI_PI_47__PI_TDFI_RDLVL_RESP + +#define LPDDR4__DENALI_PI_48_READ_MASK 0x0000FF0FU +#define LPDDR4__DENALI_PI_48_WRITE_MASK 0x0000FF0FU +#define LPDDR4__DENALI_PI_48__PI_RDLVL_RESP_MASK_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_48__PI_RDLVL_RESP_MASK_SHIFT 0U +#define LPDDR4__DENALI_PI_48__PI_RDLVL_RESP_MASK_WIDTH 4U +#define LPDDR4__PI_RDLVL_RESP_MASK__REG DENALI_PI_48 +#define LPDDR4__PI_RDLVL_RESP_MASK__FLD LPDDR4__DENALI_PI_48__PI_RDLVL_RESP_MASK + +#define LPDDR4__DENALI_PI_48__PI_TDFI_RDLVL_EN_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_48__PI_TDFI_RDLVL_EN_SHIFT 8U +#define LPDDR4__DENALI_PI_48__PI_TDFI_RDLVL_EN_WIDTH 8U +#define LPDDR4__PI_TDFI_RDLVL_EN__REG DENALI_PI_48 +#define LPDDR4__PI_TDFI_RDLVL_EN__FLD LPDDR4__DENALI_PI_48__PI_TDFI_RDLVL_EN + +#define LPDDR4__DENALI_PI_49_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_49_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_49__PI_TDFI_RDLVL_MAX_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_49__PI_TDFI_RDLVL_MAX_SHIFT 0U +#define LPDDR4__DENALI_PI_49__PI_TDFI_RDLVL_MAX_WIDTH 32U +#define LPDDR4__PI_TDFI_RDLVL_MAX__REG DENALI_PI_49 +#define LPDDR4__PI_TDFI_RDLVL_MAX__FLD LPDDR4__DENALI_PI_49__PI_TDFI_RDLVL_MAX + +#define LPDDR4__DENALI_PI_50_READ_MASK 0x00FFFF01U +#define LPDDR4__DENALI_PI_50_WRITE_MASK 0x00FFFF01U +#define LPDDR4__DENALI_PI_50__PI_RDLVL_ERROR_STATUS_MASK 0x00000001U +#define LPDDR4__DENALI_PI_50__PI_RDLVL_ERROR_STATUS_SHIFT 0U +#define LPDDR4__DENALI_PI_50__PI_RDLVL_ERROR_STATUS_WIDTH 1U +#define LPDDR4__DENALI_PI_50__PI_RDLVL_ERROR_STATUS_WOCLR 0U +#define LPDDR4__DENALI_PI_50__PI_RDLVL_ERROR_STATUS_WOSET 0U +#define LPDDR4__PI_RDLVL_ERROR_STATUS__REG DENALI_PI_50 +#define LPDDR4__PI_RDLVL_ERROR_STATUS__FLD LPDDR4__DENALI_PI_50__PI_RDLVL_ERROR_STATUS + +#define LPDDR4__DENALI_PI_50__PI_RDLVL_INTERVAL_MASK 0x00FFFF00U +#define LPDDR4__DENALI_PI_50__PI_RDLVL_INTERVAL_SHIFT 8U +#define LPDDR4__DENALI_PI_50__PI_RDLVL_INTERVAL_WIDTH 16U +#define LPDDR4__PI_RDLVL_INTERVAL__REG DENALI_PI_50 +#define LPDDR4__PI_RDLVL_INTERVAL__FLD LPDDR4__DENALI_PI_50__PI_RDLVL_INTERVAL + +#define LPDDR4__DENALI_PI_51_READ_MASK 0x0F0FFFFFU +#define LPDDR4__DENALI_PI_51_WRITE_MASK 0x0F0FFFFFU +#define LPDDR4__DENALI_PI_51__PI_RDLVL_GATE_INTERVAL_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PI_51__PI_RDLVL_GATE_INTERVAL_SHIFT 0U +#define LPDDR4__DENALI_PI_51__PI_RDLVL_GATE_INTERVAL_WIDTH 16U +#define LPDDR4__PI_RDLVL_GATE_INTERVAL__REG DENALI_PI_51 +#define LPDDR4__PI_RDLVL_GATE_INTERVAL__FLD LPDDR4__DENALI_PI_51__PI_RDLVL_GATE_INTERVAL + +#define LPDDR4__DENALI_PI_51__PI_RDLVL_PATTERN_START_MASK 0x000F0000U +#define LPDDR4__DENALI_PI_51__PI_RDLVL_PATTERN_START_SHIFT 16U +#define LPDDR4__DENALI_PI_51__PI_RDLVL_PATTERN_START_WIDTH 4U +#define LPDDR4__PI_RDLVL_PATTERN_START__REG DENALI_PI_51 +#define LPDDR4__PI_RDLVL_PATTERN_START__FLD LPDDR4__DENALI_PI_51__PI_RDLVL_PATTERN_START + +#define LPDDR4__DENALI_PI_51__PI_RDLVL_PATTERN_NUM_MASK 0x0F000000U +#define LPDDR4__DENALI_PI_51__PI_RDLVL_PATTERN_NUM_SHIFT 24U +#define LPDDR4__DENALI_PI_51__PI_RDLVL_PATTERN_NUM_WIDTH 4U +#define LPDDR4__PI_RDLVL_PATTERN_NUM__REG DENALI_PI_51 +#define LPDDR4__PI_RDLVL_PATTERN_NUM__FLD LPDDR4__DENALI_PI_51__PI_RDLVL_PATTERN_NUM + +#define LPDDR4__DENALI_PI_52_READ_MASK 0x01011F1FU +#define LPDDR4__DENALI_PI_52_WRITE_MASK 0x01011F1FU +#define LPDDR4__DENALI_PI_52__PI_RDLVL_STROBE_NUM_MASK 0x0000001FU +#define LPDDR4__DENALI_PI_52__PI_RDLVL_STROBE_NUM_SHIFT 0U +#define LPDDR4__DENALI_PI_52__PI_RDLVL_STROBE_NUM_WIDTH 5U +#define LPDDR4__PI_RDLVL_STROBE_NUM__REG DENALI_PI_52 +#define LPDDR4__PI_RDLVL_STROBE_NUM__FLD LPDDR4__DENALI_PI_52__PI_RDLVL_STROBE_NUM + +#define LPDDR4__DENALI_PI_52__PI_RDLVL_GATE_STROBE_NUM_MASK 0x00001F00U +#define LPDDR4__DENALI_PI_52__PI_RDLVL_GATE_STROBE_NUM_SHIFT 8U +#define LPDDR4__DENALI_PI_52__PI_RDLVL_GATE_STROBE_NUM_WIDTH 5U +#define LPDDR4__PI_RDLVL_GATE_STROBE_NUM__REG DENALI_PI_52 +#define LPDDR4__PI_RDLVL_GATE_STROBE_NUM__FLD LPDDR4__DENALI_PI_52__PI_RDLVL_GATE_STROBE_NUM + +#define LPDDR4__DENALI_PI_52__PI_RD_PREAMBLE_TRAINING_EN_MASK 0x00010000U +#define LPDDR4__DENALI_PI_52__PI_RD_PREAMBLE_TRAINING_EN_SHIFT 16U +#define LPDDR4__DENALI_PI_52__PI_RD_PREAMBLE_TRAINING_EN_WIDTH 1U +#define LPDDR4__DENALI_PI_52__PI_RD_PREAMBLE_TRAINING_EN_WOCLR 0U +#define LPDDR4__DENALI_PI_52__PI_RD_PREAMBLE_TRAINING_EN_WOSET 0U +#define LPDDR4__PI_RD_PREAMBLE_TRAINING_EN__REG DENALI_PI_52 +#define LPDDR4__PI_RD_PREAMBLE_TRAINING_EN__FLD LPDDR4__DENALI_PI_52__PI_RD_PREAMBLE_TRAINING_EN + +#define LPDDR4__DENALI_PI_52__PI_REG_DIMM_ENABLE_MASK 0x01000000U +#define LPDDR4__DENALI_PI_52__PI_REG_DIMM_ENABLE_SHIFT 24U +#define LPDDR4__DENALI_PI_52__PI_REG_DIMM_ENABLE_WIDTH 1U +#define LPDDR4__DENALI_PI_52__PI_REG_DIMM_ENABLE_WOCLR 0U +#define LPDDR4__DENALI_PI_52__PI_REG_DIMM_ENABLE_WOSET 0U +#define LPDDR4__PI_REG_DIMM_ENABLE__REG DENALI_PI_52 +#define LPDDR4__PI_REG_DIMM_ENABLE__FLD LPDDR4__DENALI_PI_52__PI_REG_DIMM_ENABLE + +#define LPDDR4__DENALI_PI_53_READ_MASK 0x03007F7FU +#define LPDDR4__DENALI_PI_53_WRITE_MASK 0x03007F7FU +#define LPDDR4__DENALI_PI_53__PI_TDFI_RDDATA_EN_MASK 0x0000007FU +#define LPDDR4__DENALI_PI_53__PI_TDFI_RDDATA_EN_SHIFT 0U +#define LPDDR4__DENALI_PI_53__PI_TDFI_RDDATA_EN_WIDTH 7U +#define LPDDR4__PI_TDFI_RDDATA_EN__REG DENALI_PI_53 +#define LPDDR4__PI_TDFI_RDDATA_EN__FLD LPDDR4__DENALI_PI_53__PI_TDFI_RDDATA_EN + +#define LPDDR4__DENALI_PI_53__PI_TDFI_PHY_WRLAT_MASK 0x00007F00U +#define LPDDR4__DENALI_PI_53__PI_TDFI_PHY_WRLAT_SHIFT 8U +#define LPDDR4__DENALI_PI_53__PI_TDFI_PHY_WRLAT_WIDTH 7U +#define LPDDR4__PI_TDFI_PHY_WRLAT__REG DENALI_PI_53 +#define LPDDR4__PI_TDFI_PHY_WRLAT__FLD LPDDR4__DENALI_PI_53__PI_TDFI_PHY_WRLAT + +#define LPDDR4__DENALI_PI_53__PI_CALVL_REQ_MASK 0x00010000U +#define LPDDR4__DENALI_PI_53__PI_CALVL_REQ_SHIFT 16U +#define LPDDR4__DENALI_PI_53__PI_CALVL_REQ_WIDTH 1U +#define LPDDR4__DENALI_PI_53__PI_CALVL_REQ_WOCLR 0U +#define LPDDR4__DENALI_PI_53__PI_CALVL_REQ_WOSET 0U +#define LPDDR4__PI_CALVL_REQ__REG DENALI_PI_53 +#define LPDDR4__PI_CALVL_REQ__FLD LPDDR4__DENALI_PI_53__PI_CALVL_REQ + +#define LPDDR4__DENALI_PI_53__PI_CALVL_CS_MASK 0x03000000U +#define LPDDR4__DENALI_PI_53__PI_CALVL_CS_SHIFT 24U +#define LPDDR4__DENALI_PI_53__PI_CALVL_CS_WIDTH 2U +#define LPDDR4__PI_CALVL_CS__REG DENALI_PI_53 +#define LPDDR4__PI_CALVL_CS__FLD LPDDR4__DENALI_PI_53__PI_CALVL_CS + +#define LPDDR4__DENALI_PI_54_READ_MASK 0x01030F01U +#define LPDDR4__DENALI_PI_54_WRITE_MASK 0x01030F01U +#define LPDDR4__DENALI_PI_54__PI_RESERVED3_MASK 0x00000001U +#define LPDDR4__DENALI_PI_54__PI_RESERVED3_SHIFT 0U +#define LPDDR4__DENALI_PI_54__PI_RESERVED3_WIDTH 1U +#define LPDDR4__DENALI_PI_54__PI_RESERVED3_WOCLR 0U +#define LPDDR4__DENALI_PI_54__PI_RESERVED3_WOSET 0U +#define LPDDR4__PI_RESERVED3__REG DENALI_PI_54 +#define LPDDR4__PI_RESERVED3__FLD LPDDR4__DENALI_PI_54__PI_RESERVED3 + +#define LPDDR4__DENALI_PI_54__PI_RESERVED4_MASK 0x00000F00U +#define LPDDR4__DENALI_PI_54__PI_RESERVED4_SHIFT 8U +#define LPDDR4__DENALI_PI_54__PI_RESERVED4_WIDTH 4U +#define LPDDR4__PI_RESERVED4__REG DENALI_PI_54 +#define LPDDR4__PI_RESERVED4__FLD LPDDR4__DENALI_PI_54__PI_RESERVED4 + +#define LPDDR4__DENALI_PI_54__PI_CALVL_SEQ_EN_MASK 0x00030000U +#define LPDDR4__DENALI_PI_54__PI_CALVL_SEQ_EN_SHIFT 16U +#define LPDDR4__DENALI_PI_54__PI_CALVL_SEQ_EN_WIDTH 2U +#define LPDDR4__PI_CALVL_SEQ_EN__REG DENALI_PI_54 +#define LPDDR4__PI_CALVL_SEQ_EN__FLD LPDDR4__DENALI_PI_54__PI_CALVL_SEQ_EN + +#define LPDDR4__DENALI_PI_54__PI_CALVL_PERIODIC_MASK 0x01000000U +#define LPDDR4__DENALI_PI_54__PI_CALVL_PERIODIC_SHIFT 24U +#define LPDDR4__DENALI_PI_54__PI_CALVL_PERIODIC_WIDTH 1U +#define LPDDR4__DENALI_PI_54__PI_CALVL_PERIODIC_WOCLR 0U +#define LPDDR4__DENALI_PI_54__PI_CALVL_PERIODIC_WOSET 0U +#define LPDDR4__PI_CALVL_PERIODIC__REG DENALI_PI_54 +#define LPDDR4__PI_CALVL_PERIODIC__FLD LPDDR4__DENALI_PI_54__PI_CALVL_PERIODIC + +#define LPDDR4__DENALI_PI_55_READ_MASK 0x0F010101U +#define LPDDR4__DENALI_PI_55_WRITE_MASK 0x0F010101U +#define LPDDR4__DENALI_PI_55__PI_CALVL_ON_SREF_EXIT_MASK 0x00000001U +#define LPDDR4__DENALI_PI_55__PI_CALVL_ON_SREF_EXIT_SHIFT 0U +#define LPDDR4__DENALI_PI_55__PI_CALVL_ON_SREF_EXIT_WIDTH 1U +#define LPDDR4__DENALI_PI_55__PI_CALVL_ON_SREF_EXIT_WOCLR 0U +#define LPDDR4__DENALI_PI_55__PI_CALVL_ON_SREF_EXIT_WOSET 0U +#define LPDDR4__PI_CALVL_ON_SREF_EXIT__REG DENALI_PI_55 +#define LPDDR4__PI_CALVL_ON_SREF_EXIT__FLD LPDDR4__DENALI_PI_55__PI_CALVL_ON_SREF_EXIT + +#define LPDDR4__DENALI_PI_55__PI_CALVL_DISABLE_DFS_MASK 0x00000100U +#define LPDDR4__DENALI_PI_55__PI_CALVL_DISABLE_DFS_SHIFT 8U +#define LPDDR4__DENALI_PI_55__PI_CALVL_DISABLE_DFS_WIDTH 1U +#define LPDDR4__DENALI_PI_55__PI_CALVL_DISABLE_DFS_WOCLR 0U +#define LPDDR4__DENALI_PI_55__PI_CALVL_DISABLE_DFS_WOSET 0U +#define LPDDR4__PI_CALVL_DISABLE_DFS__REG DENALI_PI_55 +#define LPDDR4__PI_CALVL_DISABLE_DFS__FLD LPDDR4__DENALI_PI_55__PI_CALVL_DISABLE_DFS + +#define LPDDR4__DENALI_PI_55__PI_CALVL_ROTATE_MASK 0x00010000U +#define LPDDR4__DENALI_PI_55__PI_CALVL_ROTATE_SHIFT 16U +#define LPDDR4__DENALI_PI_55__PI_CALVL_ROTATE_WIDTH 1U +#define LPDDR4__DENALI_PI_55__PI_CALVL_ROTATE_WOCLR 0U +#define LPDDR4__DENALI_PI_55__PI_CALVL_ROTATE_WOSET 0U +#define LPDDR4__PI_CALVL_ROTATE__REG DENALI_PI_55 +#define LPDDR4__PI_CALVL_ROTATE__FLD LPDDR4__DENALI_PI_55__PI_CALVL_ROTATE + +#define LPDDR4__DENALI_PI_55__PI_CALVL_CS_MAP_MASK 0x0F000000U +#define LPDDR4__DENALI_PI_55__PI_CALVL_CS_MAP_SHIFT 24U +#define LPDDR4__DENALI_PI_55__PI_CALVL_CS_MAP_WIDTH 4U +#define LPDDR4__PI_CALVL_CS_MAP__REG DENALI_PI_55 +#define LPDDR4__PI_CALVL_CS_MAP__FLD LPDDR4__DENALI_PI_55__PI_CALVL_CS_MAP + +#define LPDDR4__DENALI_PI_56_READ_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_56_WRITE_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_56__PI_TDFI_CALVL_EN_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_56__PI_TDFI_CALVL_EN_SHIFT 0U +#define LPDDR4__DENALI_PI_56__PI_TDFI_CALVL_EN_WIDTH 8U +#define LPDDR4__PI_TDFI_CALVL_EN__REG DENALI_PI_56 +#define LPDDR4__PI_TDFI_CALVL_EN__FLD LPDDR4__DENALI_PI_56__PI_TDFI_CALVL_EN + +#define LPDDR4__DENALI_PI_57_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_57_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_57__PI_TDFI_CALVL_RESP_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_57__PI_TDFI_CALVL_RESP_SHIFT 0U +#define LPDDR4__DENALI_PI_57__PI_TDFI_CALVL_RESP_WIDTH 32U +#define LPDDR4__PI_TDFI_CALVL_RESP__REG DENALI_PI_57 +#define LPDDR4__PI_TDFI_CALVL_RESP__FLD LPDDR4__DENALI_PI_57__PI_TDFI_CALVL_RESP + +#define LPDDR4__DENALI_PI_58_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_58_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_58__PI_TDFI_CALVL_MAX_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_58__PI_TDFI_CALVL_MAX_SHIFT 0U +#define LPDDR4__DENALI_PI_58__PI_TDFI_CALVL_MAX_WIDTH 32U +#define LPDDR4__PI_TDFI_CALVL_MAX__REG DENALI_PI_58 +#define LPDDR4__PI_TDFI_CALVL_MAX__FLD LPDDR4__DENALI_PI_58__PI_TDFI_CALVL_MAX + +#define LPDDR4__DENALI_PI_59_READ_MASK 0xFFFF0301U +#define LPDDR4__DENALI_PI_59_WRITE_MASK 0xFFFF0301U +#define LPDDR4__DENALI_PI_59__PI_CALVL_RESP_MASK_MASK 0x00000001U +#define LPDDR4__DENALI_PI_59__PI_CALVL_RESP_MASK_SHIFT 0U +#define LPDDR4__DENALI_PI_59__PI_CALVL_RESP_MASK_WIDTH 1U +#define LPDDR4__DENALI_PI_59__PI_CALVL_RESP_MASK_WOCLR 0U +#define LPDDR4__DENALI_PI_59__PI_CALVL_RESP_MASK_WOSET 0U +#define LPDDR4__PI_CALVL_RESP_MASK__REG DENALI_PI_59 +#define LPDDR4__PI_CALVL_RESP_MASK__FLD LPDDR4__DENALI_PI_59__PI_CALVL_RESP_MASK + +#define LPDDR4__DENALI_PI_59__PI_CALVL_ERROR_STATUS_MASK 0x00000300U +#define LPDDR4__DENALI_PI_59__PI_CALVL_ERROR_STATUS_SHIFT 8U +#define LPDDR4__DENALI_PI_59__PI_CALVL_ERROR_STATUS_WIDTH 2U +#define LPDDR4__PI_CALVL_ERROR_STATUS__REG DENALI_PI_59 +#define LPDDR4__PI_CALVL_ERROR_STATUS__FLD LPDDR4__DENALI_PI_59__PI_CALVL_ERROR_STATUS + +#define LPDDR4__DENALI_PI_59__PI_CALVL_INTERVAL_MASK 0xFFFF0000U +#define LPDDR4__DENALI_PI_59__PI_CALVL_INTERVAL_SHIFT 16U +#define LPDDR4__DENALI_PI_59__PI_CALVL_INTERVAL_WIDTH 16U +#define LPDDR4__PI_CALVL_INTERVAL__REG DENALI_PI_59 +#define LPDDR4__PI_CALVL_INTERVAL__FLD LPDDR4__DENALI_PI_59__PI_CALVL_INTERVAL + +#define LPDDR4__DENALI_PI_60_READ_MASK 0x1F1F3F1FU +#define LPDDR4__DENALI_PI_60_WRITE_MASK 0x1F1F3F1FU +#define LPDDR4__DENALI_PI_60__PI_TCACKEL_MASK 0x0000001FU +#define LPDDR4__DENALI_PI_60__PI_TCACKEL_SHIFT 0U +#define LPDDR4__DENALI_PI_60__PI_TCACKEL_WIDTH 5U +#define LPDDR4__PI_TCACKEL__REG DENALI_PI_60 +#define LPDDR4__PI_TCACKEL__FLD LPDDR4__DENALI_PI_60__PI_TCACKEL + +#define LPDDR4__DENALI_PI_60__PI_TCAMRD_MASK 0x00003F00U +#define LPDDR4__DENALI_PI_60__PI_TCAMRD_SHIFT 8U +#define LPDDR4__DENALI_PI_60__PI_TCAMRD_WIDTH 6U +#define LPDDR4__PI_TCAMRD__REG DENALI_PI_60 +#define LPDDR4__PI_TCAMRD__FLD LPDDR4__DENALI_PI_60__PI_TCAMRD + +#define LPDDR4__DENALI_PI_60__PI_TCACKEH_MASK 0x001F0000U +#define LPDDR4__DENALI_PI_60__PI_TCACKEH_SHIFT 16U +#define LPDDR4__DENALI_PI_60__PI_TCACKEH_WIDTH 5U +#define LPDDR4__PI_TCACKEH__REG DENALI_PI_60 +#define LPDDR4__PI_TCACKEH__FLD LPDDR4__DENALI_PI_60__PI_TCACKEH + +#define LPDDR4__DENALI_PI_60__PI_TCAEXT_MASK 0x1F000000U +#define LPDDR4__DENALI_PI_60__PI_TCAEXT_SHIFT 24U +#define LPDDR4__DENALI_PI_60__PI_TCAEXT_WIDTH 5U +#define LPDDR4__PI_TCAEXT__REG DENALI_PI_60 +#define LPDDR4__PI_TCAEXT__FLD LPDDR4__DENALI_PI_60__PI_TCAEXT + +#define LPDDR4__DENALI_PI_61_READ_MASK 0xFF0F0F01U +#define LPDDR4__DENALI_PI_61_WRITE_MASK 0xFF0F0F01U +#define LPDDR4__DENALI_PI_61__PI_CA_TRAIN_VREF_EN_MASK 0x00000001U +#define LPDDR4__DENALI_PI_61__PI_CA_TRAIN_VREF_EN_SHIFT 0U +#define LPDDR4__DENALI_PI_61__PI_CA_TRAIN_VREF_EN_WIDTH 1U +#define LPDDR4__DENALI_PI_61__PI_CA_TRAIN_VREF_EN_WOCLR 0U +#define LPDDR4__DENALI_PI_61__PI_CA_TRAIN_VREF_EN_WOSET 0U +#define LPDDR4__PI_CA_TRAIN_VREF_EN__REG DENALI_PI_61 +#define LPDDR4__PI_CA_TRAIN_VREF_EN__FLD LPDDR4__DENALI_PI_61__PI_CA_TRAIN_VREF_EN + +#define LPDDR4__DENALI_PI_61__PI_CALVL_VREF_INITIAL_STEPSIZE_MASK 0x00000F00U +#define LPDDR4__DENALI_PI_61__PI_CALVL_VREF_INITIAL_STEPSIZE_SHIFT 8U +#define LPDDR4__DENALI_PI_61__PI_CALVL_VREF_INITIAL_STEPSIZE_WIDTH 4U +#define LPDDR4__PI_CALVL_VREF_INITIAL_STEPSIZE__REG DENALI_PI_61 +#define LPDDR4__PI_CALVL_VREF_INITIAL_STEPSIZE__FLD LPDDR4__DENALI_PI_61__PI_CALVL_VREF_INITIAL_STEPSIZE + +#define LPDDR4__DENALI_PI_61__PI_CALVL_VREF_NORMAL_STEPSIZE_MASK 0x000F0000U +#define LPDDR4__DENALI_PI_61__PI_CALVL_VREF_NORMAL_STEPSIZE_SHIFT 16U +#define LPDDR4__DENALI_PI_61__PI_CALVL_VREF_NORMAL_STEPSIZE_WIDTH 4U +#define LPDDR4__PI_CALVL_VREF_NORMAL_STEPSIZE__REG DENALI_PI_61 +#define LPDDR4__PI_CALVL_VREF_NORMAL_STEPSIZE__FLD LPDDR4__DENALI_PI_61__PI_CALVL_VREF_NORMAL_STEPSIZE + +#define LPDDR4__DENALI_PI_61__PI_TDFI_INIT_START_MIN_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_61__PI_TDFI_INIT_START_MIN_SHIFT 24U +#define LPDDR4__DENALI_PI_61__PI_TDFI_INIT_START_MIN_WIDTH 8U +#define LPDDR4__PI_TDFI_INIT_START_MIN__REG DENALI_PI_61 +#define LPDDR4__PI_TDFI_INIT_START_MIN__FLD LPDDR4__DENALI_PI_61__PI_TDFI_INIT_START_MIN + +#define LPDDR4__DENALI_PI_62_READ_MASK 0x7F1F0FFFU +#define LPDDR4__DENALI_PI_62_WRITE_MASK 0x7F1F0FFFU +#define LPDDR4__DENALI_PI_62__PI_TDFI_INIT_COMPLETE_MIN_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_62__PI_TDFI_INIT_COMPLETE_MIN_SHIFT 0U +#define LPDDR4__DENALI_PI_62__PI_TDFI_INIT_COMPLETE_MIN_WIDTH 8U +#define LPDDR4__PI_TDFI_INIT_COMPLETE_MIN__REG DENALI_PI_62 +#define LPDDR4__PI_TDFI_INIT_COMPLETE_MIN__FLD LPDDR4__DENALI_PI_62__PI_TDFI_INIT_COMPLETE_MIN + +#define LPDDR4__DENALI_PI_62__PI_TCKCKEH_MASK 0x00000F00U +#define LPDDR4__DENALI_PI_62__PI_TCKCKEH_SHIFT 8U +#define LPDDR4__DENALI_PI_62__PI_TCKCKEH_WIDTH 4U +#define LPDDR4__PI_TCKCKEH__REG DENALI_PI_62 +#define LPDDR4__PI_TCKCKEH__FLD LPDDR4__DENALI_PI_62__PI_TCKCKEH + +#define LPDDR4__DENALI_PI_62__PI_CALVL_STROBE_NUM_MASK 0x001F0000U +#define LPDDR4__DENALI_PI_62__PI_CALVL_STROBE_NUM_SHIFT 16U +#define LPDDR4__DENALI_PI_62__PI_CALVL_STROBE_NUM_WIDTH 5U +#define LPDDR4__PI_CALVL_STROBE_NUM__REG DENALI_PI_62 +#define LPDDR4__PI_CALVL_STROBE_NUM__FLD LPDDR4__DENALI_PI_62__PI_CALVL_STROBE_NUM + +#define LPDDR4__DENALI_PI_62__PI_SW_CA_TRAIN_VREF_MASK 0x7F000000U +#define LPDDR4__DENALI_PI_62__PI_SW_CA_TRAIN_VREF_SHIFT 24U +#define LPDDR4__DENALI_PI_62__PI_SW_CA_TRAIN_VREF_WIDTH 7U +#define LPDDR4__PI_SW_CA_TRAIN_VREF__REG DENALI_PI_62 +#define LPDDR4__PI_SW_CA_TRAIN_VREF__FLD LPDDR4__DENALI_PI_62__PI_SW_CA_TRAIN_VREF + +#define LPDDR4__DENALI_PI_63_READ_MASK 0x0101FFFFU +#define LPDDR4__DENALI_PI_63_WRITE_MASK 0x0101FFFFU +#define LPDDR4__DENALI_PI_63__PI_CLKDISABLE_2_INIT_START_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_63__PI_CLKDISABLE_2_INIT_START_SHIFT 0U +#define LPDDR4__DENALI_PI_63__PI_CLKDISABLE_2_INIT_START_WIDTH 8U +#define LPDDR4__PI_CLKDISABLE_2_INIT_START__REG DENALI_PI_63 +#define LPDDR4__PI_CLKDISABLE_2_INIT_START__FLD LPDDR4__DENALI_PI_63__PI_CLKDISABLE_2_INIT_START + +#define LPDDR4__DENALI_PI_63__PI_INIT_STARTORCOMPLETE_2_CLKDISABLE_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_63__PI_INIT_STARTORCOMPLETE_2_CLKDISABLE_SHIFT 8U +#define LPDDR4__DENALI_PI_63__PI_INIT_STARTORCOMPLETE_2_CLKDISABLE_WIDTH 8U +#define LPDDR4__PI_INIT_STARTORCOMPLETE_2_CLKDISABLE__REG DENALI_PI_63 +#define LPDDR4__PI_INIT_STARTORCOMPLETE_2_CLKDISABLE__FLD LPDDR4__DENALI_PI_63__PI_INIT_STARTORCOMPLETE_2_CLKDISABLE + +#define LPDDR4__DENALI_PI_63__PI_DRAM_CLK_DISABLE_DEASSERT_SEL_MASK 0x00010000U +#define LPDDR4__DENALI_PI_63__PI_DRAM_CLK_DISABLE_DEASSERT_SEL_SHIFT 16U +#define LPDDR4__DENALI_PI_63__PI_DRAM_CLK_DISABLE_DEASSERT_SEL_WIDTH 1U +#define LPDDR4__DENALI_PI_63__PI_DRAM_CLK_DISABLE_DEASSERT_SEL_WOCLR 0U +#define LPDDR4__DENALI_PI_63__PI_DRAM_CLK_DISABLE_DEASSERT_SEL_WOSET 0U +#define LPDDR4__PI_DRAM_CLK_DISABLE_DEASSERT_SEL__REG DENALI_PI_63 +#define LPDDR4__PI_DRAM_CLK_DISABLE_DEASSERT_SEL__FLD LPDDR4__DENALI_PI_63__PI_DRAM_CLK_DISABLE_DEASSERT_SEL + +#define LPDDR4__DENALI_PI_63__PI_REFRESH_BETWEEN_SEGMENT_DISABLE_MASK 0x01000000U +#define LPDDR4__DENALI_PI_63__PI_REFRESH_BETWEEN_SEGMENT_DISABLE_SHIFT 24U +#define LPDDR4__DENALI_PI_63__PI_REFRESH_BETWEEN_SEGMENT_DISABLE_WIDTH 1U +#define LPDDR4__DENALI_PI_63__PI_REFRESH_BETWEEN_SEGMENT_DISABLE_WOCLR 0U +#define LPDDR4__DENALI_PI_63__PI_REFRESH_BETWEEN_SEGMENT_DISABLE_WOSET 0U +#define LPDDR4__PI_REFRESH_BETWEEN_SEGMENT_DISABLE__REG DENALI_PI_63 +#define LPDDR4__PI_REFRESH_BETWEEN_SEGMENT_DISABLE__FLD LPDDR4__DENALI_PI_63__PI_REFRESH_BETWEEN_SEGMENT_DISABLE + +#define LPDDR4__DENALI_PI_64_READ_MASK 0x00FFFF01U +#define LPDDR4__DENALI_PI_64_WRITE_MASK 0x00FFFF01U +#define LPDDR4__DENALI_PI_64__PI_MC_DFS_PI_SET_VREF_ENABLE_MASK 0x00000001U +#define LPDDR4__DENALI_PI_64__PI_MC_DFS_PI_SET_VREF_ENABLE_SHIFT 0U +#define LPDDR4__DENALI_PI_64__PI_MC_DFS_PI_SET_VREF_ENABLE_WIDTH 1U +#define LPDDR4__DENALI_PI_64__PI_MC_DFS_PI_SET_VREF_ENABLE_WOCLR 0U +#define LPDDR4__DENALI_PI_64__PI_MC_DFS_PI_SET_VREF_ENABLE_WOSET 0U +#define LPDDR4__PI_MC_DFS_PI_SET_VREF_ENABLE__REG DENALI_PI_64 +#define LPDDR4__PI_MC_DFS_PI_SET_VREF_ENABLE__FLD LPDDR4__DENALI_PI_64__PI_MC_DFS_PI_SET_VREF_ENABLE + +#define LPDDR4__DENALI_PI_64__PI_FSM_ERROR_INFO_MASK_MASK 0x00FFFF00U +#define LPDDR4__DENALI_PI_64__PI_FSM_ERROR_INFO_MASK_SHIFT 8U +#define LPDDR4__DENALI_PI_64__PI_FSM_ERROR_INFO_MASK_WIDTH 16U +#define LPDDR4__PI_FSM_ERROR_INFO_MASK__REG DENALI_PI_64 +#define LPDDR4__PI_FSM_ERROR_INFO_MASK__FLD LPDDR4__DENALI_PI_64__PI_FSM_ERROR_INFO_MASK + +#define LPDDR4__DENALI_PI_65_READ_MASK 0xFFFF0000U +#define LPDDR4__DENALI_PI_65_WRITE_MASK 0xFFFF0000U +#define LPDDR4__DENALI_PI_65__PI_SC_FSM_ERROR_INFO_WOCLR_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PI_65__PI_SC_FSM_ERROR_INFO_WOCLR_SHIFT 0U +#define LPDDR4__DENALI_PI_65__PI_SC_FSM_ERROR_INFO_WOCLR_WIDTH 16U +#define LPDDR4__PI_SC_FSM_ERROR_INFO_WOCLR__REG DENALI_PI_65 +#define LPDDR4__PI_SC_FSM_ERROR_INFO_WOCLR__FLD LPDDR4__DENALI_PI_65__PI_SC_FSM_ERROR_INFO_WOCLR + +#define LPDDR4__DENALI_PI_65__PI_FSM_ERROR_INFO_MASK 0xFFFF0000U +#define LPDDR4__DENALI_PI_65__PI_FSM_ERROR_INFO_SHIFT 16U +#define LPDDR4__DENALI_PI_65__PI_FSM_ERROR_INFO_WIDTH 16U +#define LPDDR4__PI_FSM_ERROR_INFO__REG DENALI_PI_65 +#define LPDDR4__PI_FSM_ERROR_INFO__FLD LPDDR4__DENALI_PI_65__PI_FSM_ERROR_INFO + +#define LPDDR4__DENALI_PI_66_READ_MASK 0x010F0701U +#define LPDDR4__DENALI_PI_66_WRITE_MASK 0x010F0701U +#define LPDDR4__DENALI_PI_66__PI_WDQLVL_VREF_EN_MASK 0x00000001U +#define LPDDR4__DENALI_PI_66__PI_WDQLVL_VREF_EN_SHIFT 0U +#define LPDDR4__DENALI_PI_66__PI_WDQLVL_VREF_EN_WIDTH 1U +#define LPDDR4__DENALI_PI_66__PI_WDQLVL_VREF_EN_WOCLR 0U +#define LPDDR4__DENALI_PI_66__PI_WDQLVL_VREF_EN_WOSET 0U +#define LPDDR4__PI_WDQLVL_VREF_EN__REG DENALI_PI_66 +#define LPDDR4__PI_WDQLVL_VREF_EN__FLD LPDDR4__DENALI_PI_66__PI_WDQLVL_VREF_EN + +#define LPDDR4__DENALI_PI_66__PI_WDQLVL_BST_NUM_MASK 0x00000700U +#define LPDDR4__DENALI_PI_66__PI_WDQLVL_BST_NUM_SHIFT 8U +#define LPDDR4__DENALI_PI_66__PI_WDQLVL_BST_NUM_WIDTH 3U +#define LPDDR4__PI_WDQLVL_BST_NUM__REG DENALI_PI_66 +#define LPDDR4__PI_WDQLVL_BST_NUM__FLD LPDDR4__DENALI_PI_66__PI_WDQLVL_BST_NUM + +#define LPDDR4__DENALI_PI_66__PI_WDQLVL_RESP_MASK_MASK 0x000F0000U +#define LPDDR4__DENALI_PI_66__PI_WDQLVL_RESP_MASK_SHIFT 16U +#define LPDDR4__DENALI_PI_66__PI_WDQLVL_RESP_MASK_WIDTH 4U +#define LPDDR4__PI_WDQLVL_RESP_MASK__REG DENALI_PI_66 +#define LPDDR4__PI_WDQLVL_RESP_MASK__FLD LPDDR4__DENALI_PI_66__PI_WDQLVL_RESP_MASK + +#define LPDDR4__DENALI_PI_66__PI_WDQLVL_ROTATE_MASK 0x01000000U +#define LPDDR4__DENALI_PI_66__PI_WDQLVL_ROTATE_SHIFT 24U +#define LPDDR4__DENALI_PI_66__PI_WDQLVL_ROTATE_WIDTH 1U +#define LPDDR4__DENALI_PI_66__PI_WDQLVL_ROTATE_WOCLR 0U +#define LPDDR4__DENALI_PI_66__PI_WDQLVL_ROTATE_WOSET 0U +#define LPDDR4__PI_WDQLVL_ROTATE__REG DENALI_PI_66 +#define LPDDR4__PI_WDQLVL_ROTATE__FLD LPDDR4__DENALI_PI_66__PI_WDQLVL_ROTATE + +#define LPDDR4__DENALI_PI_67_READ_MASK 0x011F1F0FU +#define LPDDR4__DENALI_PI_67_WRITE_MASK 0x011F1F0FU +#define LPDDR4__DENALI_PI_67__PI_WDQLVL_CS_MAP_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_67__PI_WDQLVL_CS_MAP_SHIFT 0U +#define LPDDR4__DENALI_PI_67__PI_WDQLVL_CS_MAP_WIDTH 4U +#define LPDDR4__PI_WDQLVL_CS_MAP__REG DENALI_PI_67 +#define LPDDR4__PI_WDQLVL_CS_MAP__FLD LPDDR4__DENALI_PI_67__PI_WDQLVL_CS_MAP + +#define LPDDR4__DENALI_PI_67__PI_WDQLVL_VREF_INITIAL_STEPSIZE_MASK 0x00001F00U +#define LPDDR4__DENALI_PI_67__PI_WDQLVL_VREF_INITIAL_STEPSIZE_SHIFT 8U +#define LPDDR4__DENALI_PI_67__PI_WDQLVL_VREF_INITIAL_STEPSIZE_WIDTH 5U +#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STEPSIZE__REG DENALI_PI_67 +#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STEPSIZE__FLD LPDDR4__DENALI_PI_67__PI_WDQLVL_VREF_INITIAL_STEPSIZE + +#define LPDDR4__DENALI_PI_67__PI_WDQLVL_VREF_NORMAL_STEPSIZE_MASK 0x001F0000U +#define LPDDR4__DENALI_PI_67__PI_WDQLVL_VREF_NORMAL_STEPSIZE_SHIFT 16U +#define LPDDR4__DENALI_PI_67__PI_WDQLVL_VREF_NORMAL_STEPSIZE_WIDTH 5U +#define LPDDR4__PI_WDQLVL_VREF_NORMAL_STEPSIZE__REG DENALI_PI_67 +#define LPDDR4__PI_WDQLVL_VREF_NORMAL_STEPSIZE__FLD LPDDR4__DENALI_PI_67__PI_WDQLVL_VREF_NORMAL_STEPSIZE + +#define LPDDR4__DENALI_PI_67__PI_WDQLVL_PERIODIC_MASK 0x01000000U +#define LPDDR4__DENALI_PI_67__PI_WDQLVL_PERIODIC_SHIFT 24U +#define LPDDR4__DENALI_PI_67__PI_WDQLVL_PERIODIC_WIDTH 1U +#define LPDDR4__DENALI_PI_67__PI_WDQLVL_PERIODIC_WOCLR 0U +#define LPDDR4__DENALI_PI_67__PI_WDQLVL_PERIODIC_WOSET 0U +#define LPDDR4__PI_WDQLVL_PERIODIC__REG DENALI_PI_67 +#define LPDDR4__PI_WDQLVL_PERIODIC__FLD LPDDR4__DENALI_PI_67__PI_WDQLVL_PERIODIC + +#define LPDDR4__DENALI_PI_68_READ_MASK 0x00FF0300U +#define LPDDR4__DENALI_PI_68_WRITE_MASK 0x00FF0300U +#define LPDDR4__DENALI_PI_68__PI_WDQLVL_REQ_MASK 0x00000001U +#define LPDDR4__DENALI_PI_68__PI_WDQLVL_REQ_SHIFT 0U +#define LPDDR4__DENALI_PI_68__PI_WDQLVL_REQ_WIDTH 1U +#define LPDDR4__DENALI_PI_68__PI_WDQLVL_REQ_WOCLR 0U +#define LPDDR4__DENALI_PI_68__PI_WDQLVL_REQ_WOSET 0U +#define LPDDR4__PI_WDQLVL_REQ__REG DENALI_PI_68 +#define LPDDR4__PI_WDQLVL_REQ__FLD LPDDR4__DENALI_PI_68__PI_WDQLVL_REQ + +#define LPDDR4__DENALI_PI_68__PI_WDQLVL_CS_MASK 0x00000300U +#define LPDDR4__DENALI_PI_68__PI_WDQLVL_CS_SHIFT 8U +#define LPDDR4__DENALI_PI_68__PI_WDQLVL_CS_WIDTH 2U +#define LPDDR4__PI_WDQLVL_CS__REG DENALI_PI_68 +#define LPDDR4__PI_WDQLVL_CS__FLD LPDDR4__DENALI_PI_68__PI_WDQLVL_CS + +#define LPDDR4__DENALI_PI_68__PI_TDFI_WDQLVL_EN_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_68__PI_TDFI_WDQLVL_EN_SHIFT 16U +#define LPDDR4__DENALI_PI_68__PI_TDFI_WDQLVL_EN_WIDTH 8U +#define LPDDR4__PI_TDFI_WDQLVL_EN__REG DENALI_PI_68 +#define LPDDR4__PI_TDFI_WDQLVL_EN__FLD LPDDR4__DENALI_PI_68__PI_TDFI_WDQLVL_EN + +#define LPDDR4__DENALI_PI_69_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_69_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_69__PI_TDFI_WDQLVL_RESP_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_69__PI_TDFI_WDQLVL_RESP_SHIFT 0U +#define LPDDR4__DENALI_PI_69__PI_TDFI_WDQLVL_RESP_WIDTH 32U +#define LPDDR4__PI_TDFI_WDQLVL_RESP__REG DENALI_PI_69 +#define LPDDR4__PI_TDFI_WDQLVL_RESP__FLD LPDDR4__DENALI_PI_69__PI_TDFI_WDQLVL_RESP + +#define LPDDR4__DENALI_PI_70_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_70_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_70__PI_TDFI_WDQLVL_MAX_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_70__PI_TDFI_WDQLVL_MAX_SHIFT 0U +#define LPDDR4__DENALI_PI_70__PI_TDFI_WDQLVL_MAX_WIDTH 32U +#define LPDDR4__PI_TDFI_WDQLVL_MAX__REG DENALI_PI_70 +#define LPDDR4__PI_TDFI_WDQLVL_MAX__FLD LPDDR4__DENALI_PI_70__PI_TDFI_WDQLVL_MAX + +#define LPDDR4__DENALI_PI_71_READ_MASK 0x0101FFFFU +#define LPDDR4__DENALI_PI_71_WRITE_MASK 0x0101FFFFU +#define LPDDR4__DENALI_PI_71__PI_WDQLVL_INTERVAL_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PI_71__PI_WDQLVL_INTERVAL_SHIFT 0U +#define LPDDR4__DENALI_PI_71__PI_WDQLVL_INTERVAL_WIDTH 16U +#define LPDDR4__PI_WDQLVL_INTERVAL__REG DENALI_PI_71 +#define LPDDR4__PI_WDQLVL_INTERVAL__FLD LPDDR4__DENALI_PI_71__PI_WDQLVL_INTERVAL + +#define LPDDR4__DENALI_PI_71__PI_WDQLVL_ON_SREF_EXIT_MASK 0x00010000U +#define LPDDR4__DENALI_PI_71__PI_WDQLVL_ON_SREF_EXIT_SHIFT 16U +#define LPDDR4__DENALI_PI_71__PI_WDQLVL_ON_SREF_EXIT_WIDTH 1U +#define LPDDR4__DENALI_PI_71__PI_WDQLVL_ON_SREF_EXIT_WOCLR 0U +#define LPDDR4__DENALI_PI_71__PI_WDQLVL_ON_SREF_EXIT_WOSET 0U +#define LPDDR4__PI_WDQLVL_ON_SREF_EXIT__REG DENALI_PI_71 +#define LPDDR4__PI_WDQLVL_ON_SREF_EXIT__FLD LPDDR4__DENALI_PI_71__PI_WDQLVL_ON_SREF_EXIT + +#define LPDDR4__DENALI_PI_71__PI_WDQLVL_DISABLE_DFS_MASK 0x01000000U +#define LPDDR4__DENALI_PI_71__PI_WDQLVL_DISABLE_DFS_SHIFT 24U +#define LPDDR4__DENALI_PI_71__PI_WDQLVL_DISABLE_DFS_WIDTH 1U +#define LPDDR4__DENALI_PI_71__PI_WDQLVL_DISABLE_DFS_WOCLR 0U +#define LPDDR4__DENALI_PI_71__PI_WDQLVL_DISABLE_DFS_WOSET 0U +#define LPDDR4__PI_WDQLVL_DISABLE_DFS__REG DENALI_PI_71 +#define LPDDR4__PI_WDQLVL_DISABLE_DFS__FLD LPDDR4__DENALI_PI_71__PI_WDQLVL_DISABLE_DFS + +#define LPDDR4__DENALI_PI_72_READ_MASK 0x01010103U +#define LPDDR4__DENALI_PI_72_WRITE_MASK 0x01010103U +#define LPDDR4__DENALI_PI_72__PI_WDQLVL_ERROR_STATUS_MASK 0x00000003U +#define LPDDR4__DENALI_PI_72__PI_WDQLVL_ERROR_STATUS_SHIFT 0U +#define LPDDR4__DENALI_PI_72__PI_WDQLVL_ERROR_STATUS_WIDTH 2U +#define LPDDR4__PI_WDQLVL_ERROR_STATUS__REG DENALI_PI_72 +#define LPDDR4__PI_WDQLVL_ERROR_STATUS__FLD LPDDR4__DENALI_PI_72__PI_WDQLVL_ERROR_STATUS + +#define LPDDR4__DENALI_PI_72__PI_WDQLVL_OSC_EN_MASK 0x00000100U +#define LPDDR4__DENALI_PI_72__PI_WDQLVL_OSC_EN_SHIFT 8U +#define LPDDR4__DENALI_PI_72__PI_WDQLVL_OSC_EN_WIDTH 1U +#define LPDDR4__DENALI_PI_72__PI_WDQLVL_OSC_EN_WOCLR 0U +#define LPDDR4__DENALI_PI_72__PI_WDQLVL_OSC_EN_WOSET 0U +#define LPDDR4__PI_WDQLVL_OSC_EN__REG DENALI_PI_72 +#define LPDDR4__PI_WDQLVL_OSC_EN__FLD LPDDR4__DENALI_PI_72__PI_WDQLVL_OSC_EN + +#define LPDDR4__DENALI_PI_72__PI_DQS_OSC_PERIOD_EN_MASK 0x00010000U +#define LPDDR4__DENALI_PI_72__PI_DQS_OSC_PERIOD_EN_SHIFT 16U +#define LPDDR4__DENALI_PI_72__PI_DQS_OSC_PERIOD_EN_WIDTH 1U +#define LPDDR4__DENALI_PI_72__PI_DQS_OSC_PERIOD_EN_WOCLR 0U +#define LPDDR4__DENALI_PI_72__PI_DQS_OSC_PERIOD_EN_WOSET 0U +#define LPDDR4__PI_DQS_OSC_PERIOD_EN__REG DENALI_PI_72 +#define LPDDR4__PI_DQS_OSC_PERIOD_EN__FLD LPDDR4__DENALI_PI_72__PI_DQS_OSC_PERIOD_EN + +#define LPDDR4__DENALI_PI_72__PI_PARALLEL_WDQLVL_EN_MASK 0x01000000U +#define LPDDR4__DENALI_PI_72__PI_PARALLEL_WDQLVL_EN_SHIFT 24U +#define LPDDR4__DENALI_PI_72__PI_PARALLEL_WDQLVL_EN_WIDTH 1U +#define LPDDR4__DENALI_PI_72__PI_PARALLEL_WDQLVL_EN_WOCLR 0U +#define LPDDR4__DENALI_PI_72__PI_PARALLEL_WDQLVL_EN_WOSET 0U +#define LPDDR4__PI_PARALLEL_WDQLVL_EN__REG DENALI_PI_72 +#define LPDDR4__PI_PARALLEL_WDQLVL_EN__FLD LPDDR4__DENALI_PI_72__PI_PARALLEL_WDQLVL_EN + +#define LPDDR4__DENALI_PI_73_READ_MASK 0x0F1F0703U +#define LPDDR4__DENALI_PI_73_WRITE_MASK 0x0F1F0703U +#define LPDDR4__DENALI_PI_73__PI_BANK_DIFF_MASK 0x00000003U +#define LPDDR4__DENALI_PI_73__PI_BANK_DIFF_SHIFT 0U +#define LPDDR4__DENALI_PI_73__PI_BANK_DIFF_WIDTH 2U +#define LPDDR4__PI_BANK_DIFF__REG DENALI_PI_73 +#define LPDDR4__PI_BANK_DIFF__FLD LPDDR4__DENALI_PI_73__PI_BANK_DIFF + +#define LPDDR4__DENALI_PI_73__PI_ROW_DIFF_MASK 0x00000700U +#define LPDDR4__DENALI_PI_73__PI_ROW_DIFF_SHIFT 8U +#define LPDDR4__DENALI_PI_73__PI_ROW_DIFF_WIDTH 3U +#define LPDDR4__PI_ROW_DIFF__REG DENALI_PI_73 +#define LPDDR4__PI_ROW_DIFF__FLD LPDDR4__DENALI_PI_73__PI_ROW_DIFF + +#define LPDDR4__DENALI_PI_73__PI_TCCD_MASK 0x001F0000U +#define LPDDR4__DENALI_PI_73__PI_TCCD_SHIFT 16U +#define LPDDR4__DENALI_PI_73__PI_TCCD_WIDTH 5U +#define LPDDR4__PI_TCCD__REG DENALI_PI_73 +#define LPDDR4__PI_TCCD__FLD LPDDR4__DENALI_PI_73__PI_TCCD + +#define LPDDR4__DENALI_PI_73__PI_RESERVED5_MASK 0x0F000000U +#define LPDDR4__DENALI_PI_73__PI_RESERVED5_SHIFT 24U +#define LPDDR4__DENALI_PI_73__PI_RESERVED5_WIDTH 4U +#define LPDDR4__PI_RESERVED5__REG DENALI_PI_73 +#define LPDDR4__PI_RESERVED5__FLD LPDDR4__DENALI_PI_73__PI_RESERVED5 + +#define LPDDR4__DENALI_PI_74_READ_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_PI_74_WRITE_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_PI_74__PI_RESERVED6_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_74__PI_RESERVED6_SHIFT 0U +#define LPDDR4__DENALI_PI_74__PI_RESERVED6_WIDTH 4U +#define LPDDR4__PI_RESERVED6__REG DENALI_PI_74 +#define LPDDR4__PI_RESERVED6__FLD LPDDR4__DENALI_PI_74__PI_RESERVED6 + +#define LPDDR4__DENALI_PI_74__PI_RESERVED7_MASK 0x00000F00U +#define LPDDR4__DENALI_PI_74__PI_RESERVED7_SHIFT 8U +#define LPDDR4__DENALI_PI_74__PI_RESERVED7_WIDTH 4U +#define LPDDR4__PI_RESERVED7__REG DENALI_PI_74 +#define LPDDR4__PI_RESERVED7__FLD LPDDR4__DENALI_PI_74__PI_RESERVED7 + +#define LPDDR4__DENALI_PI_74__PI_RESERVED8_MASK 0x000F0000U +#define LPDDR4__DENALI_PI_74__PI_RESERVED8_SHIFT 16U +#define LPDDR4__DENALI_PI_74__PI_RESERVED8_WIDTH 4U +#define LPDDR4__PI_RESERVED8__REG DENALI_PI_74 +#define LPDDR4__PI_RESERVED8__FLD LPDDR4__DENALI_PI_74__PI_RESERVED8 + +#define LPDDR4__DENALI_PI_74__PI_RESERVED9_MASK 0x0F000000U +#define LPDDR4__DENALI_PI_74__PI_RESERVED9_SHIFT 24U +#define LPDDR4__DENALI_PI_74__PI_RESERVED9_WIDTH 4U +#define LPDDR4__PI_RESERVED9__REG DENALI_PI_74 +#define LPDDR4__PI_RESERVED9__FLD LPDDR4__DENALI_PI_74__PI_RESERVED9 + +#define LPDDR4__DENALI_PI_75_READ_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_PI_75_WRITE_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_PI_75__PI_RESERVED10_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_75__PI_RESERVED10_SHIFT 0U +#define LPDDR4__DENALI_PI_75__PI_RESERVED10_WIDTH 4U +#define LPDDR4__PI_RESERVED10__REG DENALI_PI_75 +#define LPDDR4__PI_RESERVED10__FLD LPDDR4__DENALI_PI_75__PI_RESERVED10 + +#define LPDDR4__DENALI_PI_75__PI_RESERVED11_MASK 0x00000F00U +#define LPDDR4__DENALI_PI_75__PI_RESERVED11_SHIFT 8U +#define LPDDR4__DENALI_PI_75__PI_RESERVED11_WIDTH 4U +#define LPDDR4__PI_RESERVED11__REG DENALI_PI_75 +#define LPDDR4__PI_RESERVED11__FLD LPDDR4__DENALI_PI_75__PI_RESERVED11 + +#define LPDDR4__DENALI_PI_75__PI_RESERVED12_MASK 0x000F0000U +#define LPDDR4__DENALI_PI_75__PI_RESERVED12_SHIFT 16U +#define LPDDR4__DENALI_PI_75__PI_RESERVED12_WIDTH 4U +#define LPDDR4__PI_RESERVED12__REG DENALI_PI_75 +#define LPDDR4__PI_RESERVED12__FLD LPDDR4__DENALI_PI_75__PI_RESERVED12 + +#define LPDDR4__DENALI_PI_75__PI_RESERVED13_MASK 0x0F000000U +#define LPDDR4__DENALI_PI_75__PI_RESERVED13_SHIFT 24U +#define LPDDR4__DENALI_PI_75__PI_RESERVED13_WIDTH 4U +#define LPDDR4__PI_RESERVED13__REG DENALI_PI_75 +#define LPDDR4__PI_RESERVED13__FLD LPDDR4__DENALI_PI_75__PI_RESERVED13 + +#define LPDDR4__DENALI_PI_76_READ_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_PI_76_WRITE_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_PI_76__PI_RESERVED14_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_76__PI_RESERVED14_SHIFT 0U +#define LPDDR4__DENALI_PI_76__PI_RESERVED14_WIDTH 4U +#define LPDDR4__PI_RESERVED14__REG DENALI_PI_76 +#define LPDDR4__PI_RESERVED14__FLD LPDDR4__DENALI_PI_76__PI_RESERVED14 + +#define LPDDR4__DENALI_PI_76__PI_RESERVED15_MASK 0x00000F00U +#define LPDDR4__DENALI_PI_76__PI_RESERVED15_SHIFT 8U +#define LPDDR4__DENALI_PI_76__PI_RESERVED15_WIDTH 4U +#define LPDDR4__PI_RESERVED15__REG DENALI_PI_76 +#define LPDDR4__PI_RESERVED15__FLD LPDDR4__DENALI_PI_76__PI_RESERVED15 + +#define LPDDR4__DENALI_PI_76__PI_RESERVED16_MASK 0x000F0000U +#define LPDDR4__DENALI_PI_76__PI_RESERVED16_SHIFT 16U +#define LPDDR4__DENALI_PI_76__PI_RESERVED16_WIDTH 4U +#define LPDDR4__PI_RESERVED16__REG DENALI_PI_76 +#define LPDDR4__PI_RESERVED16__FLD LPDDR4__DENALI_PI_76__PI_RESERVED16 + +#define LPDDR4__DENALI_PI_76__PI_RESERVED17_MASK 0x0F000000U +#define LPDDR4__DENALI_PI_76__PI_RESERVED17_SHIFT 24U +#define LPDDR4__DENALI_PI_76__PI_RESERVED17_WIDTH 4U +#define LPDDR4__PI_RESERVED17__REG DENALI_PI_76 +#define LPDDR4__PI_RESERVED17__FLD LPDDR4__DENALI_PI_76__PI_RESERVED17 + +#define LPDDR4__DENALI_PI_77_READ_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_PI_77_WRITE_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_PI_77__PI_RESERVED18_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_77__PI_RESERVED18_SHIFT 0U +#define LPDDR4__DENALI_PI_77__PI_RESERVED18_WIDTH 4U +#define LPDDR4__PI_RESERVED18__REG DENALI_PI_77 +#define LPDDR4__PI_RESERVED18__FLD LPDDR4__DENALI_PI_77__PI_RESERVED18 + +#define LPDDR4__DENALI_PI_77__PI_RESERVED19_MASK 0x00000F00U +#define LPDDR4__DENALI_PI_77__PI_RESERVED19_SHIFT 8U +#define LPDDR4__DENALI_PI_77__PI_RESERVED19_WIDTH 4U +#define LPDDR4__PI_RESERVED19__REG DENALI_PI_77 +#define LPDDR4__PI_RESERVED19__FLD LPDDR4__DENALI_PI_77__PI_RESERVED19 + +#define LPDDR4__DENALI_PI_77__PI_RESERVED20_MASK 0x000F0000U +#define LPDDR4__DENALI_PI_77__PI_RESERVED20_SHIFT 16U +#define LPDDR4__DENALI_PI_77__PI_RESERVED20_WIDTH 4U +#define LPDDR4__PI_RESERVED20__REG DENALI_PI_77 +#define LPDDR4__PI_RESERVED20__FLD LPDDR4__DENALI_PI_77__PI_RESERVED20 + +#define LPDDR4__DENALI_PI_77__PI_RESERVED21_MASK 0x0F000000U +#define LPDDR4__DENALI_PI_77__PI_RESERVED21_SHIFT 24U +#define LPDDR4__DENALI_PI_77__PI_RESERVED21_WIDTH 4U +#define LPDDR4__PI_RESERVED21__REG DENALI_PI_77 +#define LPDDR4__PI_RESERVED21__FLD LPDDR4__DENALI_PI_77__PI_RESERVED21 + +#define LPDDR4__DENALI_PI_78_READ_MASK 0x000F0F0FU +#define LPDDR4__DENALI_PI_78_WRITE_MASK 0x000F0F0FU +#define LPDDR4__DENALI_PI_78__PI_RESERVED22_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_78__PI_RESERVED22_SHIFT 0U +#define LPDDR4__DENALI_PI_78__PI_RESERVED22_WIDTH 4U +#define LPDDR4__PI_RESERVED22__REG DENALI_PI_78 +#define LPDDR4__PI_RESERVED22__FLD LPDDR4__DENALI_PI_78__PI_RESERVED22 + +#define LPDDR4__DENALI_PI_78__PI_RESERVED23_MASK 0x00000F00U +#define LPDDR4__DENALI_PI_78__PI_RESERVED23_SHIFT 8U +#define LPDDR4__DENALI_PI_78__PI_RESERVED23_WIDTH 4U +#define LPDDR4__PI_RESERVED23__REG DENALI_PI_78 +#define LPDDR4__PI_RESERVED23__FLD LPDDR4__DENALI_PI_78__PI_RESERVED23 + +#define LPDDR4__DENALI_PI_78__PI_RESERVED24_MASK 0x000F0000U +#define LPDDR4__DENALI_PI_78__PI_RESERVED24_SHIFT 16U +#define LPDDR4__DENALI_PI_78__PI_RESERVED24_WIDTH 4U +#define LPDDR4__PI_RESERVED24__REG DENALI_PI_78 +#define LPDDR4__PI_RESERVED24__FLD LPDDR4__DENALI_PI_78__PI_RESERVED24 + +#define LPDDR4__DENALI_PI_79_READ_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PI_79_WRITE_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PI_79__PI_INT_STATUS_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PI_79__PI_INT_STATUS_SHIFT 0U +#define LPDDR4__DENALI_PI_79__PI_INT_STATUS_WIDTH 28U +#define LPDDR4__PI_INT_STATUS__REG DENALI_PI_79 +#define LPDDR4__PI_INT_STATUS__FLD LPDDR4__DENALI_PI_79__PI_INT_STATUS + +#define LPDDR4__DENALI_PI_80__PI_INT_ACK_MASK 0x07FFFFFFU +#define LPDDR4__DENALI_PI_80__PI_INT_ACK_SHIFT 0U +#define LPDDR4__DENALI_PI_80__PI_INT_ACK_WIDTH 27U +#define LPDDR4__PI_INT_ACK__REG DENALI_PI_80 +#define LPDDR4__PI_INT_ACK__FLD LPDDR4__DENALI_PI_80__PI_INT_ACK + +#define LPDDR4__DENALI_PI_81_READ_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PI_81_WRITE_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PI_81__PI_INT_MASK_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PI_81__PI_INT_MASK_SHIFT 0U +#define LPDDR4__DENALI_PI_81__PI_INT_MASK_WIDTH 28U +#define LPDDR4__PI_INT_MASK__REG DENALI_PI_81 +#define LPDDR4__PI_INT_MASK__FLD LPDDR4__DENALI_PI_81__PI_INT_MASK + +#define LPDDR4__DENALI_PI_82_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_82_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_82__PI_BIST_EXP_DATA_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_82__PI_BIST_EXP_DATA_0_SHIFT 0U +#define LPDDR4__DENALI_PI_82__PI_BIST_EXP_DATA_0_WIDTH 32U +#define LPDDR4__PI_BIST_EXP_DATA_0__REG DENALI_PI_82 +#define LPDDR4__PI_BIST_EXP_DATA_0__FLD LPDDR4__DENALI_PI_82__PI_BIST_EXP_DATA_0 + +#define LPDDR4__DENALI_PI_83_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_83_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_83__PI_BIST_EXP_DATA_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_83__PI_BIST_EXP_DATA_1_SHIFT 0U +#define LPDDR4__DENALI_PI_83__PI_BIST_EXP_DATA_1_WIDTH 32U +#define LPDDR4__PI_BIST_EXP_DATA_1__REG DENALI_PI_83 +#define LPDDR4__PI_BIST_EXP_DATA_1__FLD LPDDR4__DENALI_PI_83__PI_BIST_EXP_DATA_1 + +#define LPDDR4__DENALI_PI_84_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_84_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_84__PI_BIST_EXP_DATA_2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_84__PI_BIST_EXP_DATA_2_SHIFT 0U +#define LPDDR4__DENALI_PI_84__PI_BIST_EXP_DATA_2_WIDTH 32U +#define LPDDR4__PI_BIST_EXP_DATA_2__REG DENALI_PI_84 +#define LPDDR4__PI_BIST_EXP_DATA_2__FLD LPDDR4__DENALI_PI_84__PI_BIST_EXP_DATA_2 + +#define LPDDR4__DENALI_PI_85_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_85_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_85__PI_BIST_EXP_DATA_3_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_85__PI_BIST_EXP_DATA_3_SHIFT 0U +#define LPDDR4__DENALI_PI_85__PI_BIST_EXP_DATA_3_WIDTH 32U +#define LPDDR4__PI_BIST_EXP_DATA_3__REG DENALI_PI_85 +#define LPDDR4__PI_BIST_EXP_DATA_3__FLD LPDDR4__DENALI_PI_85__PI_BIST_EXP_DATA_3 + +#define LPDDR4__DENALI_PI_86_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_86_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_86__PI_BIST_FAIL_DATA_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_86__PI_BIST_FAIL_DATA_0_SHIFT 0U +#define LPDDR4__DENALI_PI_86__PI_BIST_FAIL_DATA_0_WIDTH 32U +#define LPDDR4__PI_BIST_FAIL_DATA_0__REG DENALI_PI_86 +#define LPDDR4__PI_BIST_FAIL_DATA_0__FLD LPDDR4__DENALI_PI_86__PI_BIST_FAIL_DATA_0 + +#define LPDDR4__DENALI_PI_87_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_87_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_87__PI_BIST_FAIL_DATA_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_87__PI_BIST_FAIL_DATA_1_SHIFT 0U +#define LPDDR4__DENALI_PI_87__PI_BIST_FAIL_DATA_1_WIDTH 32U +#define LPDDR4__PI_BIST_FAIL_DATA_1__REG DENALI_PI_87 +#define LPDDR4__PI_BIST_FAIL_DATA_1__FLD LPDDR4__DENALI_PI_87__PI_BIST_FAIL_DATA_1 + +#define LPDDR4__DENALI_PI_88_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_88_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_88__PI_BIST_FAIL_DATA_2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_88__PI_BIST_FAIL_DATA_2_SHIFT 0U +#define LPDDR4__DENALI_PI_88__PI_BIST_FAIL_DATA_2_WIDTH 32U +#define LPDDR4__PI_BIST_FAIL_DATA_2__REG DENALI_PI_88 +#define LPDDR4__PI_BIST_FAIL_DATA_2__FLD LPDDR4__DENALI_PI_88__PI_BIST_FAIL_DATA_2 + +#define LPDDR4__DENALI_PI_89_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_89_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_89__PI_BIST_FAIL_DATA_3_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_89__PI_BIST_FAIL_DATA_3_SHIFT 0U +#define LPDDR4__DENALI_PI_89__PI_BIST_FAIL_DATA_3_WIDTH 32U +#define LPDDR4__PI_BIST_FAIL_DATA_3__REG DENALI_PI_89 +#define LPDDR4__PI_BIST_FAIL_DATA_3__FLD LPDDR4__DENALI_PI_89__PI_BIST_FAIL_DATA_3 + +#define LPDDR4__DENALI_PI_90_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_90_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_90__PI_BIST_FAIL_ADDR_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_90__PI_BIST_FAIL_ADDR_0_SHIFT 0U +#define LPDDR4__DENALI_PI_90__PI_BIST_FAIL_ADDR_0_WIDTH 32U +#define LPDDR4__PI_BIST_FAIL_ADDR_0__REG DENALI_PI_90 +#define LPDDR4__PI_BIST_FAIL_ADDR_0__FLD LPDDR4__DENALI_PI_90__PI_BIST_FAIL_ADDR_0 + +#define LPDDR4__DENALI_PI_91_READ_MASK 0x011F1F07U +#define LPDDR4__DENALI_PI_91_WRITE_MASK 0x011F1F07U +#define LPDDR4__DENALI_PI_91__PI_BIST_FAIL_ADDR_1_MASK 0x00000007U +#define LPDDR4__DENALI_PI_91__PI_BIST_FAIL_ADDR_1_SHIFT 0U +#define LPDDR4__DENALI_PI_91__PI_BIST_FAIL_ADDR_1_WIDTH 3U +#define LPDDR4__PI_BIST_FAIL_ADDR_1__REG DENALI_PI_91 +#define LPDDR4__PI_BIST_FAIL_ADDR_1__FLD LPDDR4__DENALI_PI_91__PI_BIST_FAIL_ADDR_1 + +#define LPDDR4__DENALI_PI_91__PI_BSTLEN_MASK 0x00001F00U +#define LPDDR4__DENALI_PI_91__PI_BSTLEN_SHIFT 8U +#define LPDDR4__DENALI_PI_91__PI_BSTLEN_WIDTH 5U +#define LPDDR4__PI_BSTLEN__REG DENALI_PI_91 +#define LPDDR4__PI_BSTLEN__FLD LPDDR4__DENALI_PI_91__PI_BSTLEN + +#define LPDDR4__DENALI_PI_91__PI_LONG_COUNT_MASK_MASK 0x001F0000U +#define LPDDR4__DENALI_PI_91__PI_LONG_COUNT_MASK_SHIFT 16U +#define LPDDR4__DENALI_PI_91__PI_LONG_COUNT_MASK_WIDTH 5U +#define LPDDR4__PI_LONG_COUNT_MASK__REG DENALI_PI_91 +#define LPDDR4__PI_LONG_COUNT_MASK__FLD LPDDR4__DENALI_PI_91__PI_LONG_COUNT_MASK + +#define LPDDR4__DENALI_PI_91__PI_CMD_SWAP_EN_MASK 0x01000000U +#define LPDDR4__DENALI_PI_91__PI_CMD_SWAP_EN_SHIFT 24U +#define LPDDR4__DENALI_PI_91__PI_CMD_SWAP_EN_WIDTH 1U +#define LPDDR4__DENALI_PI_91__PI_CMD_SWAP_EN_WOCLR 0U +#define LPDDR4__DENALI_PI_91__PI_CMD_SWAP_EN_WOSET 0U +#define LPDDR4__PI_CMD_SWAP_EN__REG DENALI_PI_91 +#define LPDDR4__PI_CMD_SWAP_EN__FLD LPDDR4__DENALI_PI_91__PI_CMD_SWAP_EN + +#define LPDDR4__DENALI_PI_92_READ_MASK 0x03030301U +#define LPDDR4__DENALI_PI_92_WRITE_MASK 0x03030301U +#define LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_EN_MASK 0x00000001U +#define LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_EN_SHIFT 0U +#define LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_EN_WIDTH 1U +#define LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_EN_WOCLR 0U +#define LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_EN_WOSET 0U +#define LPDDR4__PI_DATA_BYTE_SWAP_EN__REG DENALI_PI_92 +#define LPDDR4__PI_DATA_BYTE_SWAP_EN__FLD LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_EN + +#define LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_SLICE0_MASK 0x00000300U +#define LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_SLICE0_SHIFT 8U +#define LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_SLICE0_WIDTH 2U +#define LPDDR4__PI_DATA_BYTE_SWAP_SLICE0__REG DENALI_PI_92 +#define LPDDR4__PI_DATA_BYTE_SWAP_SLICE0__FLD LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_SLICE0 + +#define LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_SLICE1_MASK 0x00030000U +#define LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_SLICE1_SHIFT 16U +#define LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_SLICE1_WIDTH 2U +#define LPDDR4__PI_DATA_BYTE_SWAP_SLICE1__REG DENALI_PI_92 +#define LPDDR4__PI_DATA_BYTE_SWAP_SLICE1__FLD LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_SLICE1 + +#define LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_SLICE2_MASK 0x03000000U +#define LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_SLICE2_SHIFT 24U +#define LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_SLICE2_WIDTH 2U +#define LPDDR4__PI_DATA_BYTE_SWAP_SLICE2__REG DENALI_PI_92 +#define LPDDR4__PI_DATA_BYTE_SWAP_SLICE2__FLD LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_SLICE2 + +#define LPDDR4__DENALI_PI_93_READ_MASK 0x03FF0103U +#define LPDDR4__DENALI_PI_93_WRITE_MASK 0x03FF0103U +#define LPDDR4__DENALI_PI_93__PI_DATA_BYTE_SWAP_SLICE3_MASK 0x00000003U +#define LPDDR4__DENALI_PI_93__PI_DATA_BYTE_SWAP_SLICE3_SHIFT 0U +#define LPDDR4__DENALI_PI_93__PI_DATA_BYTE_SWAP_SLICE3_WIDTH 2U +#define LPDDR4__PI_DATA_BYTE_SWAP_SLICE3__REG DENALI_PI_93 +#define LPDDR4__PI_DATA_BYTE_SWAP_SLICE3__FLD LPDDR4__DENALI_PI_93__PI_DATA_BYTE_SWAP_SLICE3 + +#define LPDDR4__DENALI_PI_93__PI_CTRLUPD_REQ_PER_AREF_EN_MASK 0x00000100U +#define LPDDR4__DENALI_PI_93__PI_CTRLUPD_REQ_PER_AREF_EN_SHIFT 8U +#define LPDDR4__DENALI_PI_93__PI_CTRLUPD_REQ_PER_AREF_EN_WIDTH 1U +#define LPDDR4__DENALI_PI_93__PI_CTRLUPD_REQ_PER_AREF_EN_WOCLR 0U +#define LPDDR4__DENALI_PI_93__PI_CTRLUPD_REQ_PER_AREF_EN_WOSET 0U +#define LPDDR4__PI_CTRLUPD_REQ_PER_AREF_EN__REG DENALI_PI_93 +#define LPDDR4__PI_CTRLUPD_REQ_PER_AREF_EN__FLD LPDDR4__DENALI_PI_93__PI_CTRLUPD_REQ_PER_AREF_EN + +#define LPDDR4__DENALI_PI_93__PI_TDFI_CTRLUPD_MIN_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_93__PI_TDFI_CTRLUPD_MIN_SHIFT 16U +#define LPDDR4__DENALI_PI_93__PI_TDFI_CTRLUPD_MIN_WIDTH 8U +#define LPDDR4__PI_TDFI_CTRLUPD_MIN__REG DENALI_PI_93 +#define LPDDR4__PI_TDFI_CTRLUPD_MIN__FLD LPDDR4__DENALI_PI_93__PI_TDFI_CTRLUPD_MIN + +#define LPDDR4__DENALI_PI_93__PI_UPDATE_ERROR_STATUS_MASK 0x03000000U +#define LPDDR4__DENALI_PI_93__PI_UPDATE_ERROR_STATUS_SHIFT 24U +#define LPDDR4__DENALI_PI_93__PI_UPDATE_ERROR_STATUS_WIDTH 2U +#define LPDDR4__PI_UPDATE_ERROR_STATUS__REG DENALI_PI_93 +#define LPDDR4__PI_UPDATE_ERROR_STATUS__FLD LPDDR4__DENALI_PI_93__PI_UPDATE_ERROR_STATUS + +#define LPDDR4__DENALI_PI_94_READ_MASK 0x013F0301U +#define LPDDR4__DENALI_PI_94_WRITE_MASK 0x013F0301U +#define LPDDR4__DENALI_PI_94__PI_BIST_GO_MASK 0x00000001U +#define LPDDR4__DENALI_PI_94__PI_BIST_GO_SHIFT 0U +#define LPDDR4__DENALI_PI_94__PI_BIST_GO_WIDTH 1U +#define LPDDR4__DENALI_PI_94__PI_BIST_GO_WOCLR 0U +#define LPDDR4__DENALI_PI_94__PI_BIST_GO_WOSET 0U +#define LPDDR4__PI_BIST_GO__REG DENALI_PI_94 +#define LPDDR4__PI_BIST_GO__FLD LPDDR4__DENALI_PI_94__PI_BIST_GO + +#define LPDDR4__DENALI_PI_94__PI_BIST_RESULT_MASK 0x00000300U +#define LPDDR4__DENALI_PI_94__PI_BIST_RESULT_SHIFT 8U +#define LPDDR4__DENALI_PI_94__PI_BIST_RESULT_WIDTH 2U +#define LPDDR4__PI_BIST_RESULT__REG DENALI_PI_94 +#define LPDDR4__PI_BIST_RESULT__FLD LPDDR4__DENALI_PI_94__PI_BIST_RESULT + +#define LPDDR4__DENALI_PI_94__PI_ADDR_SPACE_MASK 0x003F0000U +#define LPDDR4__DENALI_PI_94__PI_ADDR_SPACE_SHIFT 16U +#define LPDDR4__DENALI_PI_94__PI_ADDR_SPACE_WIDTH 6U +#define LPDDR4__PI_ADDR_SPACE__REG DENALI_PI_94 +#define LPDDR4__PI_ADDR_SPACE__FLD LPDDR4__DENALI_PI_94__PI_ADDR_SPACE + +#define LPDDR4__DENALI_PI_94__PI_BIST_DATA_CHECK_MASK 0x01000000U +#define LPDDR4__DENALI_PI_94__PI_BIST_DATA_CHECK_SHIFT 24U +#define LPDDR4__DENALI_PI_94__PI_BIST_DATA_CHECK_WIDTH 1U +#define LPDDR4__DENALI_PI_94__PI_BIST_DATA_CHECK_WOCLR 0U +#define LPDDR4__DENALI_PI_94__PI_BIST_DATA_CHECK_WOSET 0U +#define LPDDR4__PI_BIST_DATA_CHECK__REG DENALI_PI_94 +#define LPDDR4__PI_BIST_DATA_CHECK__FLD LPDDR4__DENALI_PI_94__PI_BIST_DATA_CHECK + +#define LPDDR4__DENALI_PI_95_READ_MASK 0x00000001U +#define LPDDR4__DENALI_PI_95_WRITE_MASK 0x00000001U +#define LPDDR4__DENALI_PI_95__PI_BIST_ADDR_CHECK_MASK 0x00000001U +#define LPDDR4__DENALI_PI_95__PI_BIST_ADDR_CHECK_SHIFT 0U +#define LPDDR4__DENALI_PI_95__PI_BIST_ADDR_CHECK_WIDTH 1U +#define LPDDR4__DENALI_PI_95__PI_BIST_ADDR_CHECK_WOCLR 0U +#define LPDDR4__DENALI_PI_95__PI_BIST_ADDR_CHECK_WOSET 0U +#define LPDDR4__PI_BIST_ADDR_CHECK__REG DENALI_PI_95 +#define LPDDR4__PI_BIST_ADDR_CHECK__FLD LPDDR4__DENALI_PI_95__PI_BIST_ADDR_CHECK + +#define LPDDR4__DENALI_PI_96_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_96_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_96__PI_BIST_START_ADDRESS_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_96__PI_BIST_START_ADDRESS_0_SHIFT 0U +#define LPDDR4__DENALI_PI_96__PI_BIST_START_ADDRESS_0_WIDTH 32U +#define LPDDR4__PI_BIST_START_ADDRESS_0__REG DENALI_PI_96 +#define LPDDR4__PI_BIST_START_ADDRESS_0__FLD LPDDR4__DENALI_PI_96__PI_BIST_START_ADDRESS_0 + +#define LPDDR4__DENALI_PI_97_READ_MASK 0x0000FF07U +#define LPDDR4__DENALI_PI_97_WRITE_MASK 0x0000FF07U +#define LPDDR4__DENALI_PI_97__PI_BIST_START_ADDRESS_1_MASK 0x00000007U +#define LPDDR4__DENALI_PI_97__PI_BIST_START_ADDRESS_1_SHIFT 0U +#define LPDDR4__DENALI_PI_97__PI_BIST_START_ADDRESS_1_WIDTH 3U +#define LPDDR4__PI_BIST_START_ADDRESS_1__REG DENALI_PI_97 +#define LPDDR4__PI_BIST_START_ADDRESS_1__FLD LPDDR4__DENALI_PI_97__PI_BIST_START_ADDRESS_1 + +#define LPDDR4__DENALI_PI_97__PI_MBIST_INIT_PATTERN_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_97__PI_MBIST_INIT_PATTERN_SHIFT 8U +#define LPDDR4__DENALI_PI_97__PI_MBIST_INIT_PATTERN_WIDTH 8U +#define LPDDR4__PI_MBIST_INIT_PATTERN__REG DENALI_PI_97 +#define LPDDR4__PI_MBIST_INIT_PATTERN__FLD LPDDR4__DENALI_PI_97__PI_MBIST_INIT_PATTERN + +#define LPDDR4__DENALI_PI_98_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_98_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_98__PI_BIST_DATA_MASK_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_98__PI_BIST_DATA_MASK_0_SHIFT 0U +#define LPDDR4__DENALI_PI_98__PI_BIST_DATA_MASK_0_WIDTH 32U +#define LPDDR4__PI_BIST_DATA_MASK_0__REG DENALI_PI_98 +#define LPDDR4__PI_BIST_DATA_MASK_0__FLD LPDDR4__DENALI_PI_98__PI_BIST_DATA_MASK_0 + +#define LPDDR4__DENALI_PI_99_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_99_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_99__PI_BIST_DATA_MASK_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_99__PI_BIST_DATA_MASK_1_SHIFT 0U +#define LPDDR4__DENALI_PI_99__PI_BIST_DATA_MASK_1_WIDTH 32U +#define LPDDR4__PI_BIST_DATA_MASK_1__REG DENALI_PI_99 +#define LPDDR4__PI_BIST_DATA_MASK_1__FLD LPDDR4__DENALI_PI_99__PI_BIST_DATA_MASK_1 + +#define LPDDR4__DENALI_PI_100_READ_MASK 0x0FFF0FFFU +#define LPDDR4__DENALI_PI_100_WRITE_MASK 0x0FFF0FFFU +#define LPDDR4__DENALI_PI_100__PI_BIST_ERR_COUNT_MASK 0x00000FFFU +#define LPDDR4__DENALI_PI_100__PI_BIST_ERR_COUNT_SHIFT 0U +#define LPDDR4__DENALI_PI_100__PI_BIST_ERR_COUNT_WIDTH 12U +#define LPDDR4__PI_BIST_ERR_COUNT__REG DENALI_PI_100 +#define LPDDR4__PI_BIST_ERR_COUNT__FLD LPDDR4__DENALI_PI_100__PI_BIST_ERR_COUNT + +#define LPDDR4__DENALI_PI_100__PI_BIST_ERR_STOP_MASK 0x0FFF0000U +#define LPDDR4__DENALI_PI_100__PI_BIST_ERR_STOP_SHIFT 16U +#define LPDDR4__DENALI_PI_100__PI_BIST_ERR_STOP_WIDTH 12U +#define LPDDR4__PI_BIST_ERR_STOP__REG DENALI_PI_100 +#define LPDDR4__PI_BIST_ERR_STOP__FLD LPDDR4__DENALI_PI_100__PI_BIST_ERR_STOP + +#define LPDDR4__DENALI_PI_101_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_101_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_101__PI_BIST_ADDR_MASK_0_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_101__PI_BIST_ADDR_MASK_0_0_SHIFT 0U +#define LPDDR4__DENALI_PI_101__PI_BIST_ADDR_MASK_0_0_WIDTH 32U +#define LPDDR4__PI_BIST_ADDR_MASK_0_0__REG DENALI_PI_101 +#define LPDDR4__PI_BIST_ADDR_MASK_0_0__FLD LPDDR4__DENALI_PI_101__PI_BIST_ADDR_MASK_0_0 + +#define LPDDR4__DENALI_PI_102_READ_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_102_WRITE_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_102__PI_BIST_ADDR_MASK_0_1_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_102__PI_BIST_ADDR_MASK_0_1_SHIFT 0U +#define LPDDR4__DENALI_PI_102__PI_BIST_ADDR_MASK_0_1_WIDTH 4U +#define LPDDR4__PI_BIST_ADDR_MASK_0_1__REG DENALI_PI_102 +#define LPDDR4__PI_BIST_ADDR_MASK_0_1__FLD LPDDR4__DENALI_PI_102__PI_BIST_ADDR_MASK_0_1 + +#define LPDDR4__DENALI_PI_103_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_103_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_103__PI_BIST_ADDR_MASK_1_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_103__PI_BIST_ADDR_MASK_1_0_SHIFT 0U +#define LPDDR4__DENALI_PI_103__PI_BIST_ADDR_MASK_1_0_WIDTH 32U +#define LPDDR4__PI_BIST_ADDR_MASK_1_0__REG DENALI_PI_103 +#define LPDDR4__PI_BIST_ADDR_MASK_1_0__FLD LPDDR4__DENALI_PI_103__PI_BIST_ADDR_MASK_1_0 + +#define LPDDR4__DENALI_PI_104_READ_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_104_WRITE_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_104__PI_BIST_ADDR_MASK_1_1_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_104__PI_BIST_ADDR_MASK_1_1_SHIFT 0U +#define LPDDR4__DENALI_PI_104__PI_BIST_ADDR_MASK_1_1_WIDTH 4U +#define LPDDR4__PI_BIST_ADDR_MASK_1_1__REG DENALI_PI_104 +#define LPDDR4__PI_BIST_ADDR_MASK_1_1__FLD LPDDR4__DENALI_PI_104__PI_BIST_ADDR_MASK_1_1 + +#define LPDDR4__DENALI_PI_105_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_105_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_105__PI_BIST_ADDR_MASK_2_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_105__PI_BIST_ADDR_MASK_2_0_SHIFT 0U +#define LPDDR4__DENALI_PI_105__PI_BIST_ADDR_MASK_2_0_WIDTH 32U +#define LPDDR4__PI_BIST_ADDR_MASK_2_0__REG DENALI_PI_105 +#define LPDDR4__PI_BIST_ADDR_MASK_2_0__FLD LPDDR4__DENALI_PI_105__PI_BIST_ADDR_MASK_2_0 + +#define LPDDR4__DENALI_PI_106_READ_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_106_WRITE_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_106__PI_BIST_ADDR_MASK_2_1_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_106__PI_BIST_ADDR_MASK_2_1_SHIFT 0U +#define LPDDR4__DENALI_PI_106__PI_BIST_ADDR_MASK_2_1_WIDTH 4U +#define LPDDR4__PI_BIST_ADDR_MASK_2_1__REG DENALI_PI_106 +#define LPDDR4__PI_BIST_ADDR_MASK_2_1__FLD LPDDR4__DENALI_PI_106__PI_BIST_ADDR_MASK_2_1 + +#define LPDDR4__DENALI_PI_107_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_107_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_107__PI_BIST_ADDR_MASK_3_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_107__PI_BIST_ADDR_MASK_3_0_SHIFT 0U +#define LPDDR4__DENALI_PI_107__PI_BIST_ADDR_MASK_3_0_WIDTH 32U +#define LPDDR4__PI_BIST_ADDR_MASK_3_0__REG DENALI_PI_107 +#define LPDDR4__PI_BIST_ADDR_MASK_3_0__FLD LPDDR4__DENALI_PI_107__PI_BIST_ADDR_MASK_3_0 + +#define LPDDR4__DENALI_PI_108_READ_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_108_WRITE_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_108__PI_BIST_ADDR_MASK_3_1_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_108__PI_BIST_ADDR_MASK_3_1_SHIFT 0U +#define LPDDR4__DENALI_PI_108__PI_BIST_ADDR_MASK_3_1_WIDTH 4U +#define LPDDR4__PI_BIST_ADDR_MASK_3_1__REG DENALI_PI_108 +#define LPDDR4__PI_BIST_ADDR_MASK_3_1__FLD LPDDR4__DENALI_PI_108__PI_BIST_ADDR_MASK_3_1 + +#define LPDDR4__DENALI_PI_109_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_109_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_109__PI_BIST_ADDR_MASK_4_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_109__PI_BIST_ADDR_MASK_4_0_SHIFT 0U +#define LPDDR4__DENALI_PI_109__PI_BIST_ADDR_MASK_4_0_WIDTH 32U +#define LPDDR4__PI_BIST_ADDR_MASK_4_0__REG DENALI_PI_109 +#define LPDDR4__PI_BIST_ADDR_MASK_4_0__FLD LPDDR4__DENALI_PI_109__PI_BIST_ADDR_MASK_4_0 + +#define LPDDR4__DENALI_PI_110_READ_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_110_WRITE_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_110__PI_BIST_ADDR_MASK_4_1_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_110__PI_BIST_ADDR_MASK_4_1_SHIFT 0U +#define LPDDR4__DENALI_PI_110__PI_BIST_ADDR_MASK_4_1_WIDTH 4U +#define LPDDR4__PI_BIST_ADDR_MASK_4_1__REG DENALI_PI_110 +#define LPDDR4__PI_BIST_ADDR_MASK_4_1__FLD LPDDR4__DENALI_PI_110__PI_BIST_ADDR_MASK_4_1 + +#define LPDDR4__DENALI_PI_111_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_111_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_111__PI_BIST_ADDR_MASK_5_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_111__PI_BIST_ADDR_MASK_5_0_SHIFT 0U +#define LPDDR4__DENALI_PI_111__PI_BIST_ADDR_MASK_5_0_WIDTH 32U +#define LPDDR4__PI_BIST_ADDR_MASK_5_0__REG DENALI_PI_111 +#define LPDDR4__PI_BIST_ADDR_MASK_5_0__FLD LPDDR4__DENALI_PI_111__PI_BIST_ADDR_MASK_5_0 + +#define LPDDR4__DENALI_PI_112_READ_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_112_WRITE_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_112__PI_BIST_ADDR_MASK_5_1_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_112__PI_BIST_ADDR_MASK_5_1_SHIFT 0U +#define LPDDR4__DENALI_PI_112__PI_BIST_ADDR_MASK_5_1_WIDTH 4U +#define LPDDR4__PI_BIST_ADDR_MASK_5_1__REG DENALI_PI_112 +#define LPDDR4__PI_BIST_ADDR_MASK_5_1__FLD LPDDR4__DENALI_PI_112__PI_BIST_ADDR_MASK_5_1 + +#define LPDDR4__DENALI_PI_113_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_113_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_113__PI_BIST_ADDR_MASK_6_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_113__PI_BIST_ADDR_MASK_6_0_SHIFT 0U +#define LPDDR4__DENALI_PI_113__PI_BIST_ADDR_MASK_6_0_WIDTH 32U +#define LPDDR4__PI_BIST_ADDR_MASK_6_0__REG DENALI_PI_113 +#define LPDDR4__PI_BIST_ADDR_MASK_6_0__FLD LPDDR4__DENALI_PI_113__PI_BIST_ADDR_MASK_6_0 + +#define LPDDR4__DENALI_PI_114_READ_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_114_WRITE_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_114__PI_BIST_ADDR_MASK_6_1_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_114__PI_BIST_ADDR_MASK_6_1_SHIFT 0U +#define LPDDR4__DENALI_PI_114__PI_BIST_ADDR_MASK_6_1_WIDTH 4U +#define LPDDR4__PI_BIST_ADDR_MASK_6_1__REG DENALI_PI_114 +#define LPDDR4__PI_BIST_ADDR_MASK_6_1__FLD LPDDR4__DENALI_PI_114__PI_BIST_ADDR_MASK_6_1 + +#define LPDDR4__DENALI_PI_115_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_115_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_115__PI_BIST_ADDR_MASK_7_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_115__PI_BIST_ADDR_MASK_7_0_SHIFT 0U +#define LPDDR4__DENALI_PI_115__PI_BIST_ADDR_MASK_7_0_WIDTH 32U +#define LPDDR4__PI_BIST_ADDR_MASK_7_0__REG DENALI_PI_115 +#define LPDDR4__PI_BIST_ADDR_MASK_7_0__FLD LPDDR4__DENALI_PI_115__PI_BIST_ADDR_MASK_7_0 + +#define LPDDR4__DENALI_PI_116_READ_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_116_WRITE_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_116__PI_BIST_ADDR_MASK_7_1_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_116__PI_BIST_ADDR_MASK_7_1_SHIFT 0U +#define LPDDR4__DENALI_PI_116__PI_BIST_ADDR_MASK_7_1_WIDTH 4U +#define LPDDR4__PI_BIST_ADDR_MASK_7_1__REG DENALI_PI_116 +#define LPDDR4__PI_BIST_ADDR_MASK_7_1__FLD LPDDR4__DENALI_PI_116__PI_BIST_ADDR_MASK_7_1 + +#define LPDDR4__DENALI_PI_117_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_117_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_117__PI_BIST_ADDR_MASK_8_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_117__PI_BIST_ADDR_MASK_8_0_SHIFT 0U +#define LPDDR4__DENALI_PI_117__PI_BIST_ADDR_MASK_8_0_WIDTH 32U +#define LPDDR4__PI_BIST_ADDR_MASK_8_0__REG DENALI_PI_117 +#define LPDDR4__PI_BIST_ADDR_MASK_8_0__FLD LPDDR4__DENALI_PI_117__PI_BIST_ADDR_MASK_8_0 + +#define LPDDR4__DENALI_PI_118_READ_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_118_WRITE_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_118__PI_BIST_ADDR_MASK_8_1_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_118__PI_BIST_ADDR_MASK_8_1_SHIFT 0U +#define LPDDR4__DENALI_PI_118__PI_BIST_ADDR_MASK_8_1_WIDTH 4U +#define LPDDR4__PI_BIST_ADDR_MASK_8_1__REG DENALI_PI_118 +#define LPDDR4__PI_BIST_ADDR_MASK_8_1__FLD LPDDR4__DENALI_PI_118__PI_BIST_ADDR_MASK_8_1 + +#define LPDDR4__DENALI_PI_119_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_119_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_119__PI_BIST_ADDR_MASK_9_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_119__PI_BIST_ADDR_MASK_9_0_SHIFT 0U +#define LPDDR4__DENALI_PI_119__PI_BIST_ADDR_MASK_9_0_WIDTH 32U +#define LPDDR4__PI_BIST_ADDR_MASK_9_0__REG DENALI_PI_119 +#define LPDDR4__PI_BIST_ADDR_MASK_9_0__FLD LPDDR4__DENALI_PI_119__PI_BIST_ADDR_MASK_9_0 + +#define LPDDR4__DENALI_PI_120_READ_MASK 0x0303070FU +#define LPDDR4__DENALI_PI_120_WRITE_MASK 0x0303070FU +#define LPDDR4__DENALI_PI_120__PI_BIST_ADDR_MASK_9_1_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_120__PI_BIST_ADDR_MASK_9_1_SHIFT 0U +#define LPDDR4__DENALI_PI_120__PI_BIST_ADDR_MASK_9_1_WIDTH 4U +#define LPDDR4__PI_BIST_ADDR_MASK_9_1__REG DENALI_PI_120 +#define LPDDR4__PI_BIST_ADDR_MASK_9_1__FLD LPDDR4__DENALI_PI_120__PI_BIST_ADDR_MASK_9_1 + +#define LPDDR4__DENALI_PI_120__PI_BIST_MODE_MASK 0x00000700U +#define LPDDR4__DENALI_PI_120__PI_BIST_MODE_SHIFT 8U +#define LPDDR4__DENALI_PI_120__PI_BIST_MODE_WIDTH 3U +#define LPDDR4__PI_BIST_MODE__REG DENALI_PI_120 +#define LPDDR4__PI_BIST_MODE__FLD LPDDR4__DENALI_PI_120__PI_BIST_MODE + +#define LPDDR4__DENALI_PI_120__PI_BIST_ADDR_MODE_MASK 0x00030000U +#define LPDDR4__DENALI_PI_120__PI_BIST_ADDR_MODE_SHIFT 16U +#define LPDDR4__DENALI_PI_120__PI_BIST_ADDR_MODE_WIDTH 2U +#define LPDDR4__PI_BIST_ADDR_MODE__REG DENALI_PI_120 +#define LPDDR4__PI_BIST_ADDR_MODE__FLD LPDDR4__DENALI_PI_120__PI_BIST_ADDR_MODE + +#define LPDDR4__DENALI_PI_120__PI_BIST_PAT_MODE_MASK 0x03000000U +#define LPDDR4__DENALI_PI_120__PI_BIST_PAT_MODE_SHIFT 24U +#define LPDDR4__DENALI_PI_120__PI_BIST_PAT_MODE_WIDTH 2U +#define LPDDR4__PI_BIST_PAT_MODE__REG DENALI_PI_120 +#define LPDDR4__PI_BIST_PAT_MODE__FLD LPDDR4__DENALI_PI_120__PI_BIST_PAT_MODE + +#define LPDDR4__DENALI_PI_121_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_121_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_121__PI_BIST_USER_PAT_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_121__PI_BIST_USER_PAT_0_SHIFT 0U +#define LPDDR4__DENALI_PI_121__PI_BIST_USER_PAT_0_WIDTH 32U +#define LPDDR4__PI_BIST_USER_PAT_0__REG DENALI_PI_121 +#define LPDDR4__PI_BIST_USER_PAT_0__FLD LPDDR4__DENALI_PI_121__PI_BIST_USER_PAT_0 + +#define LPDDR4__DENALI_PI_122_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_122_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_122__PI_BIST_USER_PAT_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_122__PI_BIST_USER_PAT_1_SHIFT 0U +#define LPDDR4__DENALI_PI_122__PI_BIST_USER_PAT_1_WIDTH 32U +#define LPDDR4__PI_BIST_USER_PAT_1__REG DENALI_PI_122 +#define LPDDR4__PI_BIST_USER_PAT_1__FLD LPDDR4__DENALI_PI_122__PI_BIST_USER_PAT_1 + +#define LPDDR4__DENALI_PI_123_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_123_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_123__PI_BIST_USER_PAT_2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_123__PI_BIST_USER_PAT_2_SHIFT 0U +#define LPDDR4__DENALI_PI_123__PI_BIST_USER_PAT_2_WIDTH 32U +#define LPDDR4__PI_BIST_USER_PAT_2__REG DENALI_PI_123 +#define LPDDR4__PI_BIST_USER_PAT_2__FLD LPDDR4__DENALI_PI_123__PI_BIST_USER_PAT_2 + +#define LPDDR4__DENALI_PI_124_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_124_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_124__PI_BIST_USER_PAT_3_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_124__PI_BIST_USER_PAT_3_SHIFT 0U +#define LPDDR4__DENALI_PI_124__PI_BIST_USER_PAT_3_WIDTH 32U +#define LPDDR4__PI_BIST_USER_PAT_3__REG DENALI_PI_124 +#define LPDDR4__PI_BIST_USER_PAT_3__FLD LPDDR4__DENALI_PI_124__PI_BIST_USER_PAT_3 + +#define LPDDR4__DENALI_PI_125_READ_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_125_WRITE_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_125__PI_BIST_PAT_NUM_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_125__PI_BIST_PAT_NUM_SHIFT 0U +#define LPDDR4__DENALI_PI_125__PI_BIST_PAT_NUM_WIDTH 4U +#define LPDDR4__PI_BIST_PAT_NUM__REG DENALI_PI_125 +#define LPDDR4__PI_BIST_PAT_NUM__FLD LPDDR4__DENALI_PI_125__PI_BIST_PAT_NUM + +#define LPDDR4__DENALI_PI_126_READ_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PI_126_WRITE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PI_126__PI_BIST_STAGE_0_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PI_126__PI_BIST_STAGE_0_SHIFT 0U +#define LPDDR4__DENALI_PI_126__PI_BIST_STAGE_0_WIDTH 30U +#define LPDDR4__PI_BIST_STAGE_0__REG DENALI_PI_126 +#define LPDDR4__PI_BIST_STAGE_0__FLD LPDDR4__DENALI_PI_126__PI_BIST_STAGE_0 + +#define LPDDR4__DENALI_PI_127_READ_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PI_127_WRITE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PI_127__PI_BIST_STAGE_1_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PI_127__PI_BIST_STAGE_1_SHIFT 0U +#define LPDDR4__DENALI_PI_127__PI_BIST_STAGE_1_WIDTH 30U +#define LPDDR4__PI_BIST_STAGE_1__REG DENALI_PI_127 +#define LPDDR4__PI_BIST_STAGE_1__FLD LPDDR4__DENALI_PI_127__PI_BIST_STAGE_1 + +#define LPDDR4__DENALI_PI_128_READ_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PI_128_WRITE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PI_128__PI_BIST_STAGE_2_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PI_128__PI_BIST_STAGE_2_SHIFT 0U +#define LPDDR4__DENALI_PI_128__PI_BIST_STAGE_2_WIDTH 30U +#define LPDDR4__PI_BIST_STAGE_2__REG DENALI_PI_128 +#define LPDDR4__PI_BIST_STAGE_2__FLD LPDDR4__DENALI_PI_128__PI_BIST_STAGE_2 + +#define LPDDR4__DENALI_PI_129_READ_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PI_129_WRITE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PI_129__PI_BIST_STAGE_3_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PI_129__PI_BIST_STAGE_3_SHIFT 0U +#define LPDDR4__DENALI_PI_129__PI_BIST_STAGE_3_WIDTH 30U +#define LPDDR4__PI_BIST_STAGE_3__REG DENALI_PI_129 +#define LPDDR4__PI_BIST_STAGE_3__FLD LPDDR4__DENALI_PI_129__PI_BIST_STAGE_3 + +#define LPDDR4__DENALI_PI_130_READ_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PI_130_WRITE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PI_130__PI_BIST_STAGE_4_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PI_130__PI_BIST_STAGE_4_SHIFT 0U +#define LPDDR4__DENALI_PI_130__PI_BIST_STAGE_4_WIDTH 30U +#define LPDDR4__PI_BIST_STAGE_4__REG DENALI_PI_130 +#define LPDDR4__PI_BIST_STAGE_4__FLD LPDDR4__DENALI_PI_130__PI_BIST_STAGE_4 + +#define LPDDR4__DENALI_PI_131_READ_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PI_131_WRITE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PI_131__PI_BIST_STAGE_5_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PI_131__PI_BIST_STAGE_5_SHIFT 0U +#define LPDDR4__DENALI_PI_131__PI_BIST_STAGE_5_WIDTH 30U +#define LPDDR4__PI_BIST_STAGE_5__REG DENALI_PI_131 +#define LPDDR4__PI_BIST_STAGE_5__FLD LPDDR4__DENALI_PI_131__PI_BIST_STAGE_5 + +#define LPDDR4__DENALI_PI_132_READ_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PI_132_WRITE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PI_132__PI_BIST_STAGE_6_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PI_132__PI_BIST_STAGE_6_SHIFT 0U +#define LPDDR4__DENALI_PI_132__PI_BIST_STAGE_6_WIDTH 30U +#define LPDDR4__PI_BIST_STAGE_6__REG DENALI_PI_132 +#define LPDDR4__PI_BIST_STAGE_6__FLD LPDDR4__DENALI_PI_132__PI_BIST_STAGE_6 + +#define LPDDR4__DENALI_PI_133_READ_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PI_133_WRITE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PI_133__PI_BIST_STAGE_7_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PI_133__PI_BIST_STAGE_7_SHIFT 0U +#define LPDDR4__DENALI_PI_133__PI_BIST_STAGE_7_WIDTH 30U +#define LPDDR4__PI_BIST_STAGE_7__REG DENALI_PI_133 +#define LPDDR4__PI_BIST_STAGE_7__FLD LPDDR4__DENALI_PI_133__PI_BIST_STAGE_7 + +#define LPDDR4__DENALI_PI_134_READ_MASK 0x0101010FU +#define LPDDR4__DENALI_PI_134_WRITE_MASK 0x0101010FU +#define LPDDR4__DENALI_PI_134__PI_COL_DIFF_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_134__PI_COL_DIFF_SHIFT 0U +#define LPDDR4__DENALI_PI_134__PI_COL_DIFF_WIDTH 4U +#define LPDDR4__PI_COL_DIFF__REG DENALI_PI_134 +#define LPDDR4__PI_COL_DIFF__FLD LPDDR4__DENALI_PI_134__PI_COL_DIFF + +#define LPDDR4__DENALI_PI_134__PI_SELF_REFRESH_EN_MASK 0x00000100U +#define LPDDR4__DENALI_PI_134__PI_SELF_REFRESH_EN_SHIFT 8U +#define LPDDR4__DENALI_PI_134__PI_SELF_REFRESH_EN_WIDTH 1U +#define LPDDR4__DENALI_PI_134__PI_SELF_REFRESH_EN_WOCLR 0U +#define LPDDR4__DENALI_PI_134__PI_SELF_REFRESH_EN_WOSET 0U +#define LPDDR4__PI_SELF_REFRESH_EN__REG DENALI_PI_134 +#define LPDDR4__PI_SELF_REFRESH_EN__FLD LPDDR4__DENALI_PI_134__PI_SELF_REFRESH_EN + +#define LPDDR4__DENALI_PI_134__PI_PWRUP_SREFRESH_EXIT_MASK 0x00010000U +#define LPDDR4__DENALI_PI_134__PI_PWRUP_SREFRESH_EXIT_SHIFT 16U +#define LPDDR4__DENALI_PI_134__PI_PWRUP_SREFRESH_EXIT_WIDTH 1U +#define LPDDR4__DENALI_PI_134__PI_PWRUP_SREFRESH_EXIT_WOCLR 0U +#define LPDDR4__DENALI_PI_134__PI_PWRUP_SREFRESH_EXIT_WOSET 0U +#define LPDDR4__PI_PWRUP_SREFRESH_EXIT__REG DENALI_PI_134 +#define LPDDR4__PI_PWRUP_SREFRESH_EXIT__FLD LPDDR4__DENALI_PI_134__PI_PWRUP_SREFRESH_EXIT + +#define LPDDR4__DENALI_PI_134__PI_SREFRESH_EXIT_NO_REFRESH_MASK 0x01000000U +#define LPDDR4__DENALI_PI_134__PI_SREFRESH_EXIT_NO_REFRESH_SHIFT 24U +#define LPDDR4__DENALI_PI_134__PI_SREFRESH_EXIT_NO_REFRESH_WIDTH 1U +#define LPDDR4__DENALI_PI_134__PI_SREFRESH_EXIT_NO_REFRESH_WOCLR 0U +#define LPDDR4__DENALI_PI_134__PI_SREFRESH_EXIT_NO_REFRESH_WOSET 0U +#define LPDDR4__PI_SREFRESH_EXIT_NO_REFRESH__REG DENALI_PI_134 +#define LPDDR4__PI_SREFRESH_EXIT_NO_REFRESH__FLD LPDDR4__DENALI_PI_134__PI_SREFRESH_EXIT_NO_REFRESH + +#define LPDDR4__DENALI_PI_135_READ_MASK 0x01010100U +#define LPDDR4__DENALI_PI_135_WRITE_MASK 0x01010100U +#define LPDDR4__DENALI_PI_135__PI_SREF_ENTRY_REQ_MASK 0x00000001U +#define LPDDR4__DENALI_PI_135__PI_SREF_ENTRY_REQ_SHIFT 0U +#define LPDDR4__DENALI_PI_135__PI_SREF_ENTRY_REQ_WIDTH 1U +#define LPDDR4__DENALI_PI_135__PI_SREF_ENTRY_REQ_WOCLR 0U +#define LPDDR4__DENALI_PI_135__PI_SREF_ENTRY_REQ_WOSET 0U +#define LPDDR4__PI_SREF_ENTRY_REQ__REG DENALI_PI_135 +#define LPDDR4__PI_SREF_ENTRY_REQ__FLD LPDDR4__DENALI_PI_135__PI_SREF_ENTRY_REQ + +#define LPDDR4__DENALI_PI_135__PI_NO_MRW_BT_INIT_MASK 0x00000100U +#define LPDDR4__DENALI_PI_135__PI_NO_MRW_BT_INIT_SHIFT 8U +#define LPDDR4__DENALI_PI_135__PI_NO_MRW_BT_INIT_WIDTH 1U +#define LPDDR4__DENALI_PI_135__PI_NO_MRW_BT_INIT_WOCLR 0U +#define LPDDR4__DENALI_PI_135__PI_NO_MRW_BT_INIT_WOSET 0U +#define LPDDR4__PI_NO_MRW_BT_INIT__REG DENALI_PI_135 +#define LPDDR4__PI_NO_MRW_BT_INIT__FLD LPDDR4__DENALI_PI_135__PI_NO_MRW_BT_INIT + +#define LPDDR4__DENALI_PI_135__PI_NO_MRW_INIT_MASK 0x00010000U +#define LPDDR4__DENALI_PI_135__PI_NO_MRW_INIT_SHIFT 16U +#define LPDDR4__DENALI_PI_135__PI_NO_MRW_INIT_WIDTH 1U +#define LPDDR4__DENALI_PI_135__PI_NO_MRW_INIT_WOCLR 0U +#define LPDDR4__DENALI_PI_135__PI_NO_MRW_INIT_WOSET 0U +#define LPDDR4__PI_NO_MRW_INIT__REG DENALI_PI_135 +#define LPDDR4__PI_NO_MRW_INIT__FLD LPDDR4__DENALI_PI_135__PI_NO_MRW_INIT + +#define LPDDR4__DENALI_PI_135__PI_NO_PHY_IND_TRAIN_INIT_MASK 0x01000000U +#define LPDDR4__DENALI_PI_135__PI_NO_PHY_IND_TRAIN_INIT_SHIFT 24U +#define LPDDR4__DENALI_PI_135__PI_NO_PHY_IND_TRAIN_INIT_WIDTH 1U +#define LPDDR4__DENALI_PI_135__PI_NO_PHY_IND_TRAIN_INIT_WOCLR 0U +#define LPDDR4__DENALI_PI_135__PI_NO_PHY_IND_TRAIN_INIT_WOSET 0U +#define LPDDR4__PI_NO_PHY_IND_TRAIN_INIT__REG DENALI_PI_135 +#define LPDDR4__PI_NO_PHY_IND_TRAIN_INIT__FLD LPDDR4__DENALI_PI_135__PI_NO_PHY_IND_TRAIN_INIT + +#define LPDDR4__DENALI_PI_136_READ_MASK 0x00000001U +#define LPDDR4__DENALI_PI_136_WRITE_MASK 0x00000001U +#define LPDDR4__DENALI_PI_136__PI_NO_AUTO_MRR_INIT_MASK 0x00000001U +#define LPDDR4__DENALI_PI_136__PI_NO_AUTO_MRR_INIT_SHIFT 0U +#define LPDDR4__DENALI_PI_136__PI_NO_AUTO_MRR_INIT_WIDTH 1U +#define LPDDR4__DENALI_PI_136__PI_NO_AUTO_MRR_INIT_WOCLR 0U +#define LPDDR4__DENALI_PI_136__PI_NO_AUTO_MRR_INIT_WOSET 0U +#define LPDDR4__PI_NO_AUTO_MRR_INIT__REG DENALI_PI_136 +#define LPDDR4__PI_NO_AUTO_MRR_INIT__FLD LPDDR4__DENALI_PI_136__PI_NO_AUTO_MRR_INIT + +#define LPDDR4__DENALI_PI_137_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_137_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_137__PI_TRST_PWRON_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_137__PI_TRST_PWRON_SHIFT 0U +#define LPDDR4__DENALI_PI_137__PI_TRST_PWRON_WIDTH 32U +#define LPDDR4__PI_TRST_PWRON__REG DENALI_PI_137 +#define LPDDR4__PI_TRST_PWRON__FLD LPDDR4__DENALI_PI_137__PI_TRST_PWRON + +#define LPDDR4__DENALI_PI_138_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_138_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_138__PI_CKE_INACTIVE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_138__PI_CKE_INACTIVE_SHIFT 0U +#define LPDDR4__DENALI_PI_138__PI_CKE_INACTIVE_WIDTH 32U +#define LPDDR4__PI_CKE_INACTIVE__REG DENALI_PI_138 +#define LPDDR4__PI_CKE_INACTIVE__FLD LPDDR4__DENALI_PI_138__PI_CKE_INACTIVE + +#define LPDDR4__DENALI_PI_139_READ_MASK 0xFFFF0101U +#define LPDDR4__DENALI_PI_139_WRITE_MASK 0xFFFF0101U +#define LPDDR4__DENALI_PI_139__PI_DLL_RST_MASK 0x00000001U +#define LPDDR4__DENALI_PI_139__PI_DLL_RST_SHIFT 0U +#define LPDDR4__DENALI_PI_139__PI_DLL_RST_WIDTH 1U +#define LPDDR4__DENALI_PI_139__PI_DLL_RST_WOCLR 0U +#define LPDDR4__DENALI_PI_139__PI_DLL_RST_WOSET 0U +#define LPDDR4__PI_DLL_RST__REG DENALI_PI_139 +#define LPDDR4__PI_DLL_RST__FLD LPDDR4__DENALI_PI_139__PI_DLL_RST + +#define LPDDR4__DENALI_PI_139__PI_DRAM_INIT_EN_MASK 0x00000100U +#define LPDDR4__DENALI_PI_139__PI_DRAM_INIT_EN_SHIFT 8U +#define LPDDR4__DENALI_PI_139__PI_DRAM_INIT_EN_WIDTH 1U +#define LPDDR4__DENALI_PI_139__PI_DRAM_INIT_EN_WOCLR 0U +#define LPDDR4__DENALI_PI_139__PI_DRAM_INIT_EN_WOSET 0U +#define LPDDR4__PI_DRAM_INIT_EN__REG DENALI_PI_139 +#define LPDDR4__PI_DRAM_INIT_EN__FLD LPDDR4__DENALI_PI_139__PI_DRAM_INIT_EN + +#define LPDDR4__DENALI_PI_139__PI_DLL_RST_DELAY_MASK 0xFFFF0000U +#define LPDDR4__DENALI_PI_139__PI_DLL_RST_DELAY_SHIFT 16U +#define LPDDR4__DENALI_PI_139__PI_DLL_RST_DELAY_WIDTH 16U +#define LPDDR4__PI_DLL_RST_DELAY__REG DENALI_PI_139 +#define LPDDR4__PI_DLL_RST_DELAY__FLD LPDDR4__DENALI_PI_139__PI_DLL_RST_DELAY + +#define LPDDR4__DENALI_PI_140_READ_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_140_WRITE_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_140__PI_DLL_RST_ADJ_DLY_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_140__PI_DLL_RST_ADJ_DLY_SHIFT 0U +#define LPDDR4__DENALI_PI_140__PI_DLL_RST_ADJ_DLY_WIDTH 8U +#define LPDDR4__PI_DLL_RST_ADJ_DLY__REG DENALI_PI_140 +#define LPDDR4__PI_DLL_RST_ADJ_DLY__FLD LPDDR4__DENALI_PI_140__PI_DLL_RST_ADJ_DLY + +#define LPDDR4__DENALI_PI_141_READ_MASK 0x03FFFFFFU +#define LPDDR4__DENALI_PI_141_WRITE_MASK 0x03FFFFFFU +#define LPDDR4__DENALI_PI_141__PI_WRITE_MODEREG_MASK 0x03FFFFFFU +#define LPDDR4__DENALI_PI_141__PI_WRITE_MODEREG_SHIFT 0U +#define LPDDR4__DENALI_PI_141__PI_WRITE_MODEREG_WIDTH 26U +#define LPDDR4__PI_WRITE_MODEREG__REG DENALI_PI_141 +#define LPDDR4__PI_WRITE_MODEREG__FLD LPDDR4__DENALI_PI_141__PI_WRITE_MODEREG + +#define LPDDR4__DENALI_PI_142_READ_MASK 0x01FFFFFFU +#define LPDDR4__DENALI_PI_142_WRITE_MASK 0x01FFFFFFU +#define LPDDR4__DENALI_PI_142__PI_MRW_STATUS_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_142__PI_MRW_STATUS_SHIFT 0U +#define LPDDR4__DENALI_PI_142__PI_MRW_STATUS_WIDTH 8U +#define LPDDR4__PI_MRW_STATUS__REG DENALI_PI_142 +#define LPDDR4__PI_MRW_STATUS__FLD LPDDR4__DENALI_PI_142__PI_MRW_STATUS + +#define LPDDR4__DENALI_PI_142__PI_READ_MODEREG_MASK 0x01FFFF00U +#define LPDDR4__DENALI_PI_142__PI_READ_MODEREG_SHIFT 8U +#define LPDDR4__DENALI_PI_142__PI_READ_MODEREG_WIDTH 17U +#define LPDDR4__PI_READ_MODEREG__REG DENALI_PI_142 +#define LPDDR4__PI_READ_MODEREG__FLD LPDDR4__DENALI_PI_142__PI_READ_MODEREG + +#define LPDDR4__DENALI_PI_143_READ_MASK 0x01FFFFFFU +#define LPDDR4__DENALI_PI_143_WRITE_MASK 0x01FFFFFFU +#define LPDDR4__DENALI_PI_143__PI_PERIPHERAL_MRR_DATA_0_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_143__PI_PERIPHERAL_MRR_DATA_0_SHIFT 0U +#define LPDDR4__DENALI_PI_143__PI_PERIPHERAL_MRR_DATA_0_WIDTH 24U +#define LPDDR4__PI_PERIPHERAL_MRR_DATA_0__REG DENALI_PI_143 +#define LPDDR4__PI_PERIPHERAL_MRR_DATA_0__FLD LPDDR4__DENALI_PI_143__PI_PERIPHERAL_MRR_DATA_0 + +#define LPDDR4__DENALI_PI_143__PI_NO_ZQ_INIT_MASK 0x01000000U +#define LPDDR4__DENALI_PI_143__PI_NO_ZQ_INIT_SHIFT 24U +#define LPDDR4__DENALI_PI_143__PI_NO_ZQ_INIT_WIDTH 1U +#define LPDDR4__DENALI_PI_143__PI_NO_ZQ_INIT_WOCLR 0U +#define LPDDR4__DENALI_PI_143__PI_NO_ZQ_INIT_WOSET 0U +#define LPDDR4__PI_NO_ZQ_INIT__REG DENALI_PI_143 +#define LPDDR4__PI_NO_ZQ_INIT__FLD LPDDR4__DENALI_PI_143__PI_NO_ZQ_INIT + +#define LPDDR4__DENALI_PI_144_READ_MASK 0x0101000FU +#define LPDDR4__DENALI_PI_144_WRITE_MASK 0x0101000FU +#define LPDDR4__DENALI_PI_144__PI_RESERVED25_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_144__PI_RESERVED25_SHIFT 0U +#define LPDDR4__DENALI_PI_144__PI_RESERVED25_WIDTH 4U +#define LPDDR4__PI_RESERVED25__REG DENALI_PI_144 +#define LPDDR4__PI_RESERVED25__FLD LPDDR4__DENALI_PI_144__PI_RESERVED25 + +#define LPDDR4__DENALI_PI_144__PI_RESERVED26_MASK 0x00000F00U +#define LPDDR4__DENALI_PI_144__PI_RESERVED26_SHIFT 8U +#define LPDDR4__DENALI_PI_144__PI_RESERVED26_WIDTH 4U +#define LPDDR4__PI_RESERVED26__REG DENALI_PI_144 +#define LPDDR4__PI_RESERVED26__FLD LPDDR4__DENALI_PI_144__PI_RESERVED26 + +#define LPDDR4__DENALI_PI_144__PI_ZQ_REQ_PENDING_MASK 0x00010000U +#define LPDDR4__DENALI_PI_144__PI_ZQ_REQ_PENDING_SHIFT 16U +#define LPDDR4__DENALI_PI_144__PI_ZQ_REQ_PENDING_WIDTH 1U +#define LPDDR4__DENALI_PI_144__PI_ZQ_REQ_PENDING_WOCLR 0U +#define LPDDR4__DENALI_PI_144__PI_ZQ_REQ_PENDING_WOSET 0U +#define LPDDR4__PI_ZQ_REQ_PENDING__REG DENALI_PI_144 +#define LPDDR4__PI_ZQ_REQ_PENDING__FLD LPDDR4__DENALI_PI_144__PI_ZQ_REQ_PENDING + +#define LPDDR4__DENALI_PI_144__PI_RESERVED27_MASK 0x01000000U +#define LPDDR4__DENALI_PI_144__PI_RESERVED27_SHIFT 24U +#define LPDDR4__DENALI_PI_144__PI_RESERVED27_WIDTH 1U +#define LPDDR4__DENALI_PI_144__PI_RESERVED27_WOCLR 0U +#define LPDDR4__DENALI_PI_144__PI_RESERVED27_WOSET 0U +#define LPDDR4__PI_RESERVED27__REG DENALI_PI_144 +#define LPDDR4__PI_RESERVED27__FLD LPDDR4__DENALI_PI_144__PI_RESERVED27 + +#define LPDDR4__DENALI_PI_145_READ_MASK 0xFF010F07U +#define LPDDR4__DENALI_PI_145_WRITE_MASK 0xFF010F07U +#define LPDDR4__DENALI_PI_145__PI_RESERVED28_MASK 0x00000007U +#define LPDDR4__DENALI_PI_145__PI_RESERVED28_SHIFT 0U +#define LPDDR4__DENALI_PI_145__PI_RESERVED28_WIDTH 3U +#define LPDDR4__PI_RESERVED28__REG DENALI_PI_145 +#define LPDDR4__PI_RESERVED28__FLD LPDDR4__DENALI_PI_145__PI_RESERVED28 + +#define LPDDR4__DENALI_PI_145__PI_MONITOR_SRC_SEL_0_MASK 0x00000F00U +#define LPDDR4__DENALI_PI_145__PI_MONITOR_SRC_SEL_0_SHIFT 8U +#define LPDDR4__DENALI_PI_145__PI_MONITOR_SRC_SEL_0_WIDTH 4U +#define LPDDR4__PI_MONITOR_SRC_SEL_0__REG DENALI_PI_145 +#define LPDDR4__PI_MONITOR_SRC_SEL_0__FLD LPDDR4__DENALI_PI_145__PI_MONITOR_SRC_SEL_0 + +#define LPDDR4__DENALI_PI_145__PI_MONITOR_CAP_SEL_0_MASK 0x00010000U +#define LPDDR4__DENALI_PI_145__PI_MONITOR_CAP_SEL_0_SHIFT 16U +#define LPDDR4__DENALI_PI_145__PI_MONITOR_CAP_SEL_0_WIDTH 1U +#define LPDDR4__DENALI_PI_145__PI_MONITOR_CAP_SEL_0_WOCLR 0U +#define LPDDR4__DENALI_PI_145__PI_MONITOR_CAP_SEL_0_WOSET 0U +#define LPDDR4__PI_MONITOR_CAP_SEL_0__REG DENALI_PI_145 +#define LPDDR4__PI_MONITOR_CAP_SEL_0__FLD LPDDR4__DENALI_PI_145__PI_MONITOR_CAP_SEL_0 + +#define LPDDR4__DENALI_PI_145__PI_MONITOR_0_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_145__PI_MONITOR_0_SHIFT 24U +#define LPDDR4__DENALI_PI_145__PI_MONITOR_0_WIDTH 8U +#define LPDDR4__PI_MONITOR_0__REG DENALI_PI_145 +#define LPDDR4__PI_MONITOR_0__FLD LPDDR4__DENALI_PI_145__PI_MONITOR_0 + +#define LPDDR4__DENALI_PI_146_READ_MASK 0x0FFF010FU +#define LPDDR4__DENALI_PI_146_WRITE_MASK 0x0FFF010FU +#define LPDDR4__DENALI_PI_146__PI_MONITOR_SRC_SEL_1_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_146__PI_MONITOR_SRC_SEL_1_SHIFT 0U +#define LPDDR4__DENALI_PI_146__PI_MONITOR_SRC_SEL_1_WIDTH 4U +#define LPDDR4__PI_MONITOR_SRC_SEL_1__REG DENALI_PI_146 +#define LPDDR4__PI_MONITOR_SRC_SEL_1__FLD LPDDR4__DENALI_PI_146__PI_MONITOR_SRC_SEL_1 + +#define LPDDR4__DENALI_PI_146__PI_MONITOR_CAP_SEL_1_MASK 0x00000100U +#define LPDDR4__DENALI_PI_146__PI_MONITOR_CAP_SEL_1_SHIFT 8U +#define LPDDR4__DENALI_PI_146__PI_MONITOR_CAP_SEL_1_WIDTH 1U +#define LPDDR4__DENALI_PI_146__PI_MONITOR_CAP_SEL_1_WOCLR 0U +#define LPDDR4__DENALI_PI_146__PI_MONITOR_CAP_SEL_1_WOSET 0U +#define LPDDR4__PI_MONITOR_CAP_SEL_1__REG DENALI_PI_146 +#define LPDDR4__PI_MONITOR_CAP_SEL_1__FLD LPDDR4__DENALI_PI_146__PI_MONITOR_CAP_SEL_1 + +#define LPDDR4__DENALI_PI_146__PI_MONITOR_1_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_146__PI_MONITOR_1_SHIFT 16U +#define LPDDR4__DENALI_PI_146__PI_MONITOR_1_WIDTH 8U +#define LPDDR4__PI_MONITOR_1__REG DENALI_PI_146 +#define LPDDR4__PI_MONITOR_1__FLD LPDDR4__DENALI_PI_146__PI_MONITOR_1 + +#define LPDDR4__DENALI_PI_146__PI_MONITOR_SRC_SEL_2_MASK 0x0F000000U +#define LPDDR4__DENALI_PI_146__PI_MONITOR_SRC_SEL_2_SHIFT 24U +#define LPDDR4__DENALI_PI_146__PI_MONITOR_SRC_SEL_2_WIDTH 4U +#define LPDDR4__PI_MONITOR_SRC_SEL_2__REG DENALI_PI_146 +#define LPDDR4__PI_MONITOR_SRC_SEL_2__FLD LPDDR4__DENALI_PI_146__PI_MONITOR_SRC_SEL_2 + +#define LPDDR4__DENALI_PI_147_READ_MASK 0x010FFF01U +#define LPDDR4__DENALI_PI_147_WRITE_MASK 0x010FFF01U +#define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_2_MASK 0x00000001U +#define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_2_SHIFT 0U +#define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_2_WIDTH 1U +#define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_2_WOCLR 0U +#define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_2_WOSET 0U +#define LPDDR4__PI_MONITOR_CAP_SEL_2__REG DENALI_PI_147 +#define LPDDR4__PI_MONITOR_CAP_SEL_2__FLD LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_2 + +#define LPDDR4__DENALI_PI_147__PI_MONITOR_2_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_147__PI_MONITOR_2_SHIFT 8U +#define LPDDR4__DENALI_PI_147__PI_MONITOR_2_WIDTH 8U +#define LPDDR4__PI_MONITOR_2__REG DENALI_PI_147 +#define LPDDR4__PI_MONITOR_2__FLD LPDDR4__DENALI_PI_147__PI_MONITOR_2 + +#define LPDDR4__DENALI_PI_147__PI_MONITOR_SRC_SEL_3_MASK 0x000F0000U +#define LPDDR4__DENALI_PI_147__PI_MONITOR_SRC_SEL_3_SHIFT 16U +#define LPDDR4__DENALI_PI_147__PI_MONITOR_SRC_SEL_3_WIDTH 4U +#define LPDDR4__PI_MONITOR_SRC_SEL_3__REG DENALI_PI_147 +#define LPDDR4__PI_MONITOR_SRC_SEL_3__FLD LPDDR4__DENALI_PI_147__PI_MONITOR_SRC_SEL_3 + +#define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_3_MASK 0x01000000U +#define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_3_SHIFT 24U +#define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_3_WIDTH 1U +#define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_3_WOCLR 0U +#define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_3_WOSET 0U +#define LPDDR4__PI_MONITOR_CAP_SEL_3__REG DENALI_PI_147 +#define LPDDR4__PI_MONITOR_CAP_SEL_3__FLD LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_3 + +#define LPDDR4__DENALI_PI_148_READ_MASK 0xFF010FFFU +#define LPDDR4__DENALI_PI_148_WRITE_MASK 0xFF010FFFU +#define LPDDR4__DENALI_PI_148__PI_MONITOR_3_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_148__PI_MONITOR_3_SHIFT 0U +#define LPDDR4__DENALI_PI_148__PI_MONITOR_3_WIDTH 8U +#define LPDDR4__PI_MONITOR_3__REG DENALI_PI_148 +#define LPDDR4__PI_MONITOR_3__FLD LPDDR4__DENALI_PI_148__PI_MONITOR_3 + +#define LPDDR4__DENALI_PI_148__PI_MONITOR_SRC_SEL_4_MASK 0x00000F00U +#define LPDDR4__DENALI_PI_148__PI_MONITOR_SRC_SEL_4_SHIFT 8U +#define LPDDR4__DENALI_PI_148__PI_MONITOR_SRC_SEL_4_WIDTH 4U +#define LPDDR4__PI_MONITOR_SRC_SEL_4__REG DENALI_PI_148 +#define LPDDR4__PI_MONITOR_SRC_SEL_4__FLD LPDDR4__DENALI_PI_148__PI_MONITOR_SRC_SEL_4 + +#define LPDDR4__DENALI_PI_148__PI_MONITOR_CAP_SEL_4_MASK 0x00010000U +#define LPDDR4__DENALI_PI_148__PI_MONITOR_CAP_SEL_4_SHIFT 16U +#define LPDDR4__DENALI_PI_148__PI_MONITOR_CAP_SEL_4_WIDTH 1U +#define LPDDR4__DENALI_PI_148__PI_MONITOR_CAP_SEL_4_WOCLR 0U +#define LPDDR4__DENALI_PI_148__PI_MONITOR_CAP_SEL_4_WOSET 0U +#define LPDDR4__PI_MONITOR_CAP_SEL_4__REG DENALI_PI_148 +#define LPDDR4__PI_MONITOR_CAP_SEL_4__FLD LPDDR4__DENALI_PI_148__PI_MONITOR_CAP_SEL_4 + +#define LPDDR4__DENALI_PI_148__PI_MONITOR_4_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_148__PI_MONITOR_4_SHIFT 24U +#define LPDDR4__DENALI_PI_148__PI_MONITOR_4_WIDTH 8U +#define LPDDR4__PI_MONITOR_4__REG DENALI_PI_148 +#define LPDDR4__PI_MONITOR_4__FLD LPDDR4__DENALI_PI_148__PI_MONITOR_4 + +#define LPDDR4__DENALI_PI_149_READ_MASK 0x0FFF010FU +#define LPDDR4__DENALI_PI_149_WRITE_MASK 0x0FFF010FU +#define LPDDR4__DENALI_PI_149__PI_MONITOR_SRC_SEL_5_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_149__PI_MONITOR_SRC_SEL_5_SHIFT 0U +#define LPDDR4__DENALI_PI_149__PI_MONITOR_SRC_SEL_5_WIDTH 4U +#define LPDDR4__PI_MONITOR_SRC_SEL_5__REG DENALI_PI_149 +#define LPDDR4__PI_MONITOR_SRC_SEL_5__FLD LPDDR4__DENALI_PI_149__PI_MONITOR_SRC_SEL_5 + +#define LPDDR4__DENALI_PI_149__PI_MONITOR_CAP_SEL_5_MASK 0x00000100U +#define LPDDR4__DENALI_PI_149__PI_MONITOR_CAP_SEL_5_SHIFT 8U +#define LPDDR4__DENALI_PI_149__PI_MONITOR_CAP_SEL_5_WIDTH 1U +#define LPDDR4__DENALI_PI_149__PI_MONITOR_CAP_SEL_5_WOCLR 0U +#define LPDDR4__DENALI_PI_149__PI_MONITOR_CAP_SEL_5_WOSET 0U +#define LPDDR4__PI_MONITOR_CAP_SEL_5__REG DENALI_PI_149 +#define LPDDR4__PI_MONITOR_CAP_SEL_5__FLD LPDDR4__DENALI_PI_149__PI_MONITOR_CAP_SEL_5 + +#define LPDDR4__DENALI_PI_149__PI_MONITOR_5_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_149__PI_MONITOR_5_SHIFT 16U +#define LPDDR4__DENALI_PI_149__PI_MONITOR_5_WIDTH 8U +#define LPDDR4__PI_MONITOR_5__REG DENALI_PI_149 +#define LPDDR4__PI_MONITOR_5__FLD LPDDR4__DENALI_PI_149__PI_MONITOR_5 + +#define LPDDR4__DENALI_PI_149__PI_MONITOR_SRC_SEL_6_MASK 0x0F000000U +#define LPDDR4__DENALI_PI_149__PI_MONITOR_SRC_SEL_6_SHIFT 24U +#define LPDDR4__DENALI_PI_149__PI_MONITOR_SRC_SEL_6_WIDTH 4U +#define LPDDR4__PI_MONITOR_SRC_SEL_6__REG DENALI_PI_149 +#define LPDDR4__PI_MONITOR_SRC_SEL_6__FLD LPDDR4__DENALI_PI_149__PI_MONITOR_SRC_SEL_6 + +#define LPDDR4__DENALI_PI_150_READ_MASK 0x010FFF01U +#define LPDDR4__DENALI_PI_150_WRITE_MASK 0x010FFF01U +#define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_6_MASK 0x00000001U +#define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_6_SHIFT 0U +#define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_6_WIDTH 1U +#define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_6_WOCLR 0U +#define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_6_WOSET 0U +#define LPDDR4__PI_MONITOR_CAP_SEL_6__REG DENALI_PI_150 +#define LPDDR4__PI_MONITOR_CAP_SEL_6__FLD LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_6 + +#define LPDDR4__DENALI_PI_150__PI_MONITOR_6_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_150__PI_MONITOR_6_SHIFT 8U +#define LPDDR4__DENALI_PI_150__PI_MONITOR_6_WIDTH 8U +#define LPDDR4__PI_MONITOR_6__REG DENALI_PI_150 +#define LPDDR4__PI_MONITOR_6__FLD LPDDR4__DENALI_PI_150__PI_MONITOR_6 + +#define LPDDR4__DENALI_PI_150__PI_MONITOR_SRC_SEL_7_MASK 0x000F0000U +#define LPDDR4__DENALI_PI_150__PI_MONITOR_SRC_SEL_7_SHIFT 16U +#define LPDDR4__DENALI_PI_150__PI_MONITOR_SRC_SEL_7_WIDTH 4U +#define LPDDR4__PI_MONITOR_SRC_SEL_7__REG DENALI_PI_150 +#define LPDDR4__PI_MONITOR_SRC_SEL_7__FLD LPDDR4__DENALI_PI_150__PI_MONITOR_SRC_SEL_7 + +#define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_7_MASK 0x01000000U +#define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_7_SHIFT 24U +#define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_7_WIDTH 1U +#define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_7_WOCLR 0U +#define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_7_WOSET 0U +#define LPDDR4__PI_MONITOR_CAP_SEL_7__REG DENALI_PI_150 +#define LPDDR4__PI_MONITOR_CAP_SEL_7__FLD LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_7 + +#define LPDDR4__DENALI_PI_151_READ_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_151_WRITE_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_151__PI_MONITOR_7_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_151__PI_MONITOR_7_SHIFT 0U +#define LPDDR4__DENALI_PI_151__PI_MONITOR_7_WIDTH 8U +#define LPDDR4__PI_MONITOR_7__REG DENALI_PI_151 +#define LPDDR4__PI_MONITOR_7__FLD LPDDR4__DENALI_PI_151__PI_MONITOR_7 + +#define LPDDR4__DENALI_PI_152__PI_MONITOR_STROBE_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_152__PI_MONITOR_STROBE_SHIFT 0U +#define LPDDR4__DENALI_PI_152__PI_MONITOR_STROBE_WIDTH 8U +#define LPDDR4__PI_MONITOR_STROBE__REG DENALI_PI_152 +#define LPDDR4__PI_MONITOR_STROBE__FLD LPDDR4__DENALI_PI_152__PI_MONITOR_STROBE + +#define LPDDR4__DENALI_PI_153_READ_MASK 0x011F1F01U +#define LPDDR4__DENALI_PI_153_WRITE_MASK 0x011F1F01U +#define LPDDR4__DENALI_PI_153__PI_DLL_LOCK_MASK 0x00000001U +#define LPDDR4__DENALI_PI_153__PI_DLL_LOCK_SHIFT 0U +#define LPDDR4__DENALI_PI_153__PI_DLL_LOCK_WIDTH 1U +#define LPDDR4__DENALI_PI_153__PI_DLL_LOCK_WOCLR 0U +#define LPDDR4__DENALI_PI_153__PI_DLL_LOCK_WOSET 0U +#define LPDDR4__PI_DLL_LOCK__REG DENALI_PI_153 +#define LPDDR4__PI_DLL_LOCK__FLD LPDDR4__DENALI_PI_153__PI_DLL_LOCK + +#define LPDDR4__DENALI_PI_153__PI_FREQ_NUMBER_STATUS_MASK 0x00001F00U +#define LPDDR4__DENALI_PI_153__PI_FREQ_NUMBER_STATUS_SHIFT 8U +#define LPDDR4__DENALI_PI_153__PI_FREQ_NUMBER_STATUS_WIDTH 5U +#define LPDDR4__PI_FREQ_NUMBER_STATUS__REG DENALI_PI_153 +#define LPDDR4__PI_FREQ_NUMBER_STATUS__FLD LPDDR4__DENALI_PI_153__PI_FREQ_NUMBER_STATUS + +#define LPDDR4__DENALI_PI_153__PI_FREQ_RETENTION_NUM_MASK 0x001F0000U +#define LPDDR4__DENALI_PI_153__PI_FREQ_RETENTION_NUM_SHIFT 16U +#define LPDDR4__DENALI_PI_153__PI_FREQ_RETENTION_NUM_WIDTH 5U +#define LPDDR4__PI_FREQ_RETENTION_NUM__REG DENALI_PI_153 +#define LPDDR4__PI_FREQ_RETENTION_NUM__FLD LPDDR4__DENALI_PI_153__PI_FREQ_RETENTION_NUM + +#define LPDDR4__DENALI_PI_153__PI_RESERVED29_MASK 0x01000000U +#define LPDDR4__DENALI_PI_153__PI_RESERVED29_SHIFT 24U +#define LPDDR4__DENALI_PI_153__PI_RESERVED29_WIDTH 1U +#define LPDDR4__DENALI_PI_153__PI_RESERVED29_WOCLR 0U +#define LPDDR4__DENALI_PI_153__PI_RESERVED29_WOSET 0U +#define LPDDR4__PI_RESERVED29__REG DENALI_PI_153 +#define LPDDR4__PI_RESERVED29__FLD LPDDR4__DENALI_PI_153__PI_RESERVED29 + +#define LPDDR4__DENALI_PI_154_READ_MASK 0x01010103U +#define LPDDR4__DENALI_PI_154_WRITE_MASK 0x01010103U +#define LPDDR4__DENALI_PI_154__PI_PHYMSTR_TYPE_MASK 0x00000003U +#define LPDDR4__DENALI_PI_154__PI_PHYMSTR_TYPE_SHIFT 0U +#define LPDDR4__DENALI_PI_154__PI_PHYMSTR_TYPE_WIDTH 2U +#define LPDDR4__PI_PHYMSTR_TYPE__REG DENALI_PI_154 +#define LPDDR4__PI_PHYMSTR_TYPE__FLD LPDDR4__DENALI_PI_154__PI_PHYMSTR_TYPE + +#define LPDDR4__DENALI_PI_154__PI_RESERVED30_MASK 0x00000100U +#define LPDDR4__DENALI_PI_154__PI_RESERVED30_SHIFT 8U +#define LPDDR4__DENALI_PI_154__PI_RESERVED30_WIDTH 1U +#define LPDDR4__DENALI_PI_154__PI_RESERVED30_WOCLR 0U +#define LPDDR4__DENALI_PI_154__PI_RESERVED30_WOSET 0U +#define LPDDR4__PI_RESERVED30__REG DENALI_PI_154 +#define LPDDR4__PI_RESERVED30__FLD LPDDR4__DENALI_PI_154__PI_RESERVED30 + +#define LPDDR4__DENALI_PI_154__PI_POWER_REDUC_EN_MASK 0x00010000U +#define LPDDR4__DENALI_PI_154__PI_POWER_REDUC_EN_SHIFT 16U +#define LPDDR4__DENALI_PI_154__PI_POWER_REDUC_EN_WIDTH 1U +#define LPDDR4__DENALI_PI_154__PI_POWER_REDUC_EN_WOCLR 0U +#define LPDDR4__DENALI_PI_154__PI_POWER_REDUC_EN_WOSET 0U +#define LPDDR4__PI_POWER_REDUC_EN__REG DENALI_PI_154 +#define LPDDR4__PI_POWER_REDUC_EN__FLD LPDDR4__DENALI_PI_154__PI_POWER_REDUC_EN + +#define LPDDR4__DENALI_PI_154__PI_RESERVED31_MASK 0x01000000U +#define LPDDR4__DENALI_PI_154__PI_RESERVED31_SHIFT 24U +#define LPDDR4__DENALI_PI_154__PI_RESERVED31_WIDTH 1U +#define LPDDR4__DENALI_PI_154__PI_RESERVED31_WOCLR 0U +#define LPDDR4__DENALI_PI_154__PI_RESERVED31_WOSET 0U +#define LPDDR4__PI_RESERVED31__REG DENALI_PI_154 +#define LPDDR4__PI_RESERVED31__FLD LPDDR4__DENALI_PI_154__PI_RESERVED31 + +#define LPDDR4__DENALI_PI_155_READ_MASK 0x01010101U +#define LPDDR4__DENALI_PI_155_WRITE_MASK 0x01010101U +#define LPDDR4__DENALI_PI_155__PI_RESERVED32_MASK 0x00000001U +#define LPDDR4__DENALI_PI_155__PI_RESERVED32_SHIFT 0U +#define LPDDR4__DENALI_PI_155__PI_RESERVED32_WIDTH 1U +#define LPDDR4__DENALI_PI_155__PI_RESERVED32_WOCLR 0U +#define LPDDR4__DENALI_PI_155__PI_RESERVED32_WOSET 0U +#define LPDDR4__PI_RESERVED32__REG DENALI_PI_155 +#define LPDDR4__PI_RESERVED32__FLD LPDDR4__DENALI_PI_155__PI_RESERVED32 + +#define LPDDR4__DENALI_PI_155__PI_RESERVED33_MASK 0x00000100U +#define LPDDR4__DENALI_PI_155__PI_RESERVED33_SHIFT 8U +#define LPDDR4__DENALI_PI_155__PI_RESERVED33_WIDTH 1U +#define LPDDR4__DENALI_PI_155__PI_RESERVED33_WOCLR 0U +#define LPDDR4__DENALI_PI_155__PI_RESERVED33_WOSET 0U +#define LPDDR4__PI_RESERVED33__REG DENALI_PI_155 +#define LPDDR4__PI_RESERVED33__FLD LPDDR4__DENALI_PI_155__PI_RESERVED33 + +#define LPDDR4__DENALI_PI_155__PI_RESERVED34_MASK 0x00010000U +#define LPDDR4__DENALI_PI_155__PI_RESERVED34_SHIFT 16U +#define LPDDR4__DENALI_PI_155__PI_RESERVED34_WIDTH 1U +#define LPDDR4__DENALI_PI_155__PI_RESERVED34_WOCLR 0U +#define LPDDR4__DENALI_PI_155__PI_RESERVED34_WOSET 0U +#define LPDDR4__PI_RESERVED34__REG DENALI_PI_155 +#define LPDDR4__PI_RESERVED34__FLD LPDDR4__DENALI_PI_155__PI_RESERVED34 + +#define LPDDR4__DENALI_PI_155__PI_RESERVED35_MASK 0x01000000U +#define LPDDR4__DENALI_PI_155__PI_RESERVED35_SHIFT 24U +#define LPDDR4__DENALI_PI_155__PI_RESERVED35_WIDTH 1U +#define LPDDR4__DENALI_PI_155__PI_RESERVED35_WOCLR 0U +#define LPDDR4__DENALI_PI_155__PI_RESERVED35_WOSET 0U +#define LPDDR4__PI_RESERVED35__REG DENALI_PI_155 +#define LPDDR4__PI_RESERVED35__FLD LPDDR4__DENALI_PI_155__PI_RESERVED35 + +#define LPDDR4__DENALI_PI_156_READ_MASK 0x01010101U +#define LPDDR4__DENALI_PI_156_WRITE_MASK 0x01010101U +#define LPDDR4__DENALI_PI_156__PI_RESERVED36_MASK 0x00000001U +#define LPDDR4__DENALI_PI_156__PI_RESERVED36_SHIFT 0U +#define LPDDR4__DENALI_PI_156__PI_RESERVED36_WIDTH 1U +#define LPDDR4__DENALI_PI_156__PI_RESERVED36_WOCLR 0U +#define LPDDR4__DENALI_PI_156__PI_RESERVED36_WOSET 0U +#define LPDDR4__PI_RESERVED36__REG DENALI_PI_156 +#define LPDDR4__PI_RESERVED36__FLD LPDDR4__DENALI_PI_156__PI_RESERVED36 + +#define LPDDR4__DENALI_PI_156__PI_RESERVED37_MASK 0x00000100U +#define LPDDR4__DENALI_PI_156__PI_RESERVED37_SHIFT 8U +#define LPDDR4__DENALI_PI_156__PI_RESERVED37_WIDTH 1U +#define LPDDR4__DENALI_PI_156__PI_RESERVED37_WOCLR 0U +#define LPDDR4__DENALI_PI_156__PI_RESERVED37_WOSET 0U +#define LPDDR4__PI_RESERVED37__REG DENALI_PI_156 +#define LPDDR4__PI_RESERVED37__FLD LPDDR4__DENALI_PI_156__PI_RESERVED37 + +#define LPDDR4__DENALI_PI_156__PI_RESERVED38_MASK 0x00010000U +#define LPDDR4__DENALI_PI_156__PI_RESERVED38_SHIFT 16U +#define LPDDR4__DENALI_PI_156__PI_RESERVED38_WIDTH 1U +#define LPDDR4__DENALI_PI_156__PI_RESERVED38_WOCLR 0U +#define LPDDR4__DENALI_PI_156__PI_RESERVED38_WOSET 0U +#define LPDDR4__PI_RESERVED38__REG DENALI_PI_156 +#define LPDDR4__PI_RESERVED38__FLD LPDDR4__DENALI_PI_156__PI_RESERVED38 + +#define LPDDR4__DENALI_PI_156__PI_RESERVED39_MASK 0x01000000U +#define LPDDR4__DENALI_PI_156__PI_RESERVED39_SHIFT 24U +#define LPDDR4__DENALI_PI_156__PI_RESERVED39_WIDTH 1U +#define LPDDR4__DENALI_PI_156__PI_RESERVED39_WOCLR 0U +#define LPDDR4__DENALI_PI_156__PI_RESERVED39_WOSET 0U +#define LPDDR4__PI_RESERVED39__REG DENALI_PI_156 +#define LPDDR4__PI_RESERVED39__FLD LPDDR4__DENALI_PI_156__PI_RESERVED39 + +#define LPDDR4__DENALI_PI_157_READ_MASK 0x01010101U +#define LPDDR4__DENALI_PI_157_WRITE_MASK 0x01010101U +#define LPDDR4__DENALI_PI_157__PI_RESERVED40_MASK 0x00000001U +#define LPDDR4__DENALI_PI_157__PI_RESERVED40_SHIFT 0U +#define LPDDR4__DENALI_PI_157__PI_RESERVED40_WIDTH 1U +#define LPDDR4__DENALI_PI_157__PI_RESERVED40_WOCLR 0U +#define LPDDR4__DENALI_PI_157__PI_RESERVED40_WOSET 0U +#define LPDDR4__PI_RESERVED40__REG DENALI_PI_157 +#define LPDDR4__PI_RESERVED40__FLD LPDDR4__DENALI_PI_157__PI_RESERVED40 + +#define LPDDR4__DENALI_PI_157__PI_RESERVED41_MASK 0x00000100U +#define LPDDR4__DENALI_PI_157__PI_RESERVED41_SHIFT 8U +#define LPDDR4__DENALI_PI_157__PI_RESERVED41_WIDTH 1U +#define LPDDR4__DENALI_PI_157__PI_RESERVED41_WOCLR 0U +#define LPDDR4__DENALI_PI_157__PI_RESERVED41_WOSET 0U +#define LPDDR4__PI_RESERVED41__REG DENALI_PI_157 +#define LPDDR4__PI_RESERVED41__FLD LPDDR4__DENALI_PI_157__PI_RESERVED41 + +#define LPDDR4__DENALI_PI_157__PI_RESERVED42_MASK 0x00010000U +#define LPDDR4__DENALI_PI_157__PI_RESERVED42_SHIFT 16U +#define LPDDR4__DENALI_PI_157__PI_RESERVED42_WIDTH 1U +#define LPDDR4__DENALI_PI_157__PI_RESERVED42_WOCLR 0U +#define LPDDR4__DENALI_PI_157__PI_RESERVED42_WOSET 0U +#define LPDDR4__PI_RESERVED42__REG DENALI_PI_157 +#define LPDDR4__PI_RESERVED42__FLD LPDDR4__DENALI_PI_157__PI_RESERVED42 + +#define LPDDR4__DENALI_PI_157__PI_RESERVED43_MASK 0x01000000U +#define LPDDR4__DENALI_PI_157__PI_RESERVED43_SHIFT 24U +#define LPDDR4__DENALI_PI_157__PI_RESERVED43_WIDTH 1U +#define LPDDR4__DENALI_PI_157__PI_RESERVED43_WOCLR 0U +#define LPDDR4__DENALI_PI_157__PI_RESERVED43_WOSET 0U +#define LPDDR4__PI_RESERVED43__REG DENALI_PI_157 +#define LPDDR4__PI_RESERVED43__FLD LPDDR4__DENALI_PI_157__PI_RESERVED43 + +#define LPDDR4__DENALI_PI_158_READ_MASK 0x01010101U +#define LPDDR4__DENALI_PI_158_WRITE_MASK 0x01010101U +#define LPDDR4__DENALI_PI_158__PI_RESERVED44_MASK 0x00000001U +#define LPDDR4__DENALI_PI_158__PI_RESERVED44_SHIFT 0U +#define LPDDR4__DENALI_PI_158__PI_RESERVED44_WIDTH 1U +#define LPDDR4__DENALI_PI_158__PI_RESERVED44_WOCLR 0U +#define LPDDR4__DENALI_PI_158__PI_RESERVED44_WOSET 0U +#define LPDDR4__PI_RESERVED44__REG DENALI_PI_158 +#define LPDDR4__PI_RESERVED44__FLD LPDDR4__DENALI_PI_158__PI_RESERVED44 + +#define LPDDR4__DENALI_PI_158__PI_RESERVED45_MASK 0x00000100U +#define LPDDR4__DENALI_PI_158__PI_RESERVED45_SHIFT 8U +#define LPDDR4__DENALI_PI_158__PI_RESERVED45_WIDTH 1U +#define LPDDR4__DENALI_PI_158__PI_RESERVED45_WOCLR 0U +#define LPDDR4__DENALI_PI_158__PI_RESERVED45_WOSET 0U +#define LPDDR4__PI_RESERVED45__REG DENALI_PI_158 +#define LPDDR4__PI_RESERVED45__FLD LPDDR4__DENALI_PI_158__PI_RESERVED45 + +#define LPDDR4__DENALI_PI_158__PI_RESERVED46_MASK 0x00010000U +#define LPDDR4__DENALI_PI_158__PI_RESERVED46_SHIFT 16U +#define LPDDR4__DENALI_PI_158__PI_RESERVED46_WIDTH 1U +#define LPDDR4__DENALI_PI_158__PI_RESERVED46_WOCLR 0U +#define LPDDR4__DENALI_PI_158__PI_RESERVED46_WOSET 0U +#define LPDDR4__PI_RESERVED46__REG DENALI_PI_158 +#define LPDDR4__PI_RESERVED46__FLD LPDDR4__DENALI_PI_158__PI_RESERVED46 + +#define LPDDR4__DENALI_PI_158__PI_RESERVED47_MASK 0x01000000U +#define LPDDR4__DENALI_PI_158__PI_RESERVED47_SHIFT 24U +#define LPDDR4__DENALI_PI_158__PI_RESERVED47_WIDTH 1U +#define LPDDR4__DENALI_PI_158__PI_RESERVED47_WOCLR 0U +#define LPDDR4__DENALI_PI_158__PI_RESERVED47_WOSET 0U +#define LPDDR4__PI_RESERVED47__REG DENALI_PI_158 +#define LPDDR4__PI_RESERVED47__FLD LPDDR4__DENALI_PI_158__PI_RESERVED47 + +#define LPDDR4__DENALI_PI_159_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_159_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_159__PI_WRLVL_MAX_STROBE_PEND_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_159__PI_WRLVL_MAX_STROBE_PEND_SHIFT 0U +#define LPDDR4__DENALI_PI_159__PI_WRLVL_MAX_STROBE_PEND_WIDTH 8U +#define LPDDR4__PI_WRLVL_MAX_STROBE_PEND__REG DENALI_PI_159 +#define LPDDR4__PI_WRLVL_MAX_STROBE_PEND__FLD LPDDR4__DENALI_PI_159__PI_WRLVL_MAX_STROBE_PEND + +#define LPDDR4__DENALI_PI_159__PI_TREFBW_THR_MASK 0x0001FF00U +#define LPDDR4__DENALI_PI_159__PI_TREFBW_THR_SHIFT 8U +#define LPDDR4__DENALI_PI_159__PI_TREFBW_THR_WIDTH 9U +#define LPDDR4__PI_TREFBW_THR__REG DENALI_PI_159 +#define LPDDR4__PI_TREFBW_THR__FLD LPDDR4__DENALI_PI_159__PI_TREFBW_THR + +#define LPDDR4__DENALI_PI_160_READ_MASK 0x0000001FU +#define LPDDR4__DENALI_PI_160_WRITE_MASK 0x0000001FU +#define LPDDR4__DENALI_PI_160__PI_FREQ_CHANGE_REG_COPY_MASK 0x0000001FU +#define LPDDR4__DENALI_PI_160__PI_FREQ_CHANGE_REG_COPY_SHIFT 0U +#define LPDDR4__DENALI_PI_160__PI_FREQ_CHANGE_REG_COPY_WIDTH 5U +#define LPDDR4__PI_FREQ_CHANGE_REG_COPY__REG DENALI_PI_160 +#define LPDDR4__PI_FREQ_CHANGE_REG_COPY__FLD LPDDR4__DENALI_PI_160__PI_FREQ_CHANGE_REG_COPY + +#define LPDDR4__DENALI_PI_161_READ_MASK 0x0F011F01U +#define LPDDR4__DENALI_PI_161_WRITE_MASK 0x0F011F01U +#define LPDDR4__DENALI_PI_161__PI_FREQ_SEL_FROM_REGIF_MASK 0x00000001U +#define LPDDR4__DENALI_PI_161__PI_FREQ_SEL_FROM_REGIF_SHIFT 0U +#define LPDDR4__DENALI_PI_161__PI_FREQ_SEL_FROM_REGIF_WIDTH 1U +#define LPDDR4__DENALI_PI_161__PI_FREQ_SEL_FROM_REGIF_WOCLR 0U +#define LPDDR4__DENALI_PI_161__PI_FREQ_SEL_FROM_REGIF_WOSET 0U +#define LPDDR4__PI_FREQ_SEL_FROM_REGIF__REG DENALI_PI_161 +#define LPDDR4__PI_FREQ_SEL_FROM_REGIF__FLD LPDDR4__DENALI_PI_161__PI_FREQ_SEL_FROM_REGIF + +#define LPDDR4__DENALI_PI_161__PI_RESERVED48_MASK 0x00001F00U +#define LPDDR4__DENALI_PI_161__PI_RESERVED48_SHIFT 8U +#define LPDDR4__DENALI_PI_161__PI_RESERVED48_WIDTH 5U +#define LPDDR4__PI_RESERVED48__REG DENALI_PI_161 +#define LPDDR4__PI_RESERVED48__FLD LPDDR4__DENALI_PI_161__PI_RESERVED48 + +#define LPDDR4__DENALI_PI_161__PI_PARALLEL_CALVL_EN_MASK 0x00010000U +#define LPDDR4__DENALI_PI_161__PI_PARALLEL_CALVL_EN_SHIFT 16U +#define LPDDR4__DENALI_PI_161__PI_PARALLEL_CALVL_EN_WIDTH 1U +#define LPDDR4__DENALI_PI_161__PI_PARALLEL_CALVL_EN_WOCLR 0U +#define LPDDR4__DENALI_PI_161__PI_PARALLEL_CALVL_EN_WOSET 0U +#define LPDDR4__PI_PARALLEL_CALVL_EN__REG DENALI_PI_161 +#define LPDDR4__PI_PARALLEL_CALVL_EN__FLD LPDDR4__DENALI_PI_161__PI_PARALLEL_CALVL_EN + +#define LPDDR4__DENALI_PI_161__PI_CATR_MASK 0x0F000000U +#define LPDDR4__DENALI_PI_161__PI_CATR_SHIFT 24U +#define LPDDR4__DENALI_PI_161__PI_CATR_WIDTH 4U +#define LPDDR4__PI_CATR__REG DENALI_PI_161 +#define LPDDR4__PI_CATR__FLD LPDDR4__DENALI_PI_161__PI_CATR + +#define LPDDR4__DENALI_PI_162_READ_MASK 0x01010101U +#define LPDDR4__DENALI_PI_162_WRITE_MASK 0x01010101U +#define LPDDR4__DENALI_PI_162__PI_NO_CATR_READ_MASK 0x00000001U +#define LPDDR4__DENALI_PI_162__PI_NO_CATR_READ_SHIFT 0U +#define LPDDR4__DENALI_PI_162__PI_NO_CATR_READ_WIDTH 1U +#define LPDDR4__DENALI_PI_162__PI_NO_CATR_READ_WOCLR 0U +#define LPDDR4__DENALI_PI_162__PI_NO_CATR_READ_WOSET 0U +#define LPDDR4__PI_NO_CATR_READ__REG DENALI_PI_162 +#define LPDDR4__PI_NO_CATR_READ__FLD LPDDR4__DENALI_PI_162__PI_NO_CATR_READ + +#define LPDDR4__DENALI_PI_162__PI_MASK_INIT_COMPLETE_MASK 0x00000100U +#define LPDDR4__DENALI_PI_162__PI_MASK_INIT_COMPLETE_SHIFT 8U +#define LPDDR4__DENALI_PI_162__PI_MASK_INIT_COMPLETE_WIDTH 1U +#define LPDDR4__DENALI_PI_162__PI_MASK_INIT_COMPLETE_WOCLR 0U +#define LPDDR4__DENALI_PI_162__PI_MASK_INIT_COMPLETE_WOSET 0U +#define LPDDR4__PI_MASK_INIT_COMPLETE__REG DENALI_PI_162 +#define LPDDR4__PI_MASK_INIT_COMPLETE__FLD LPDDR4__DENALI_PI_162__PI_MASK_INIT_COMPLETE + +#define LPDDR4__DENALI_PI_162__PI_DISCONNECT_MC_MASK 0x00010000U +#define LPDDR4__DENALI_PI_162__PI_DISCONNECT_MC_SHIFT 16U +#define LPDDR4__DENALI_PI_162__PI_DISCONNECT_MC_WIDTH 1U +#define LPDDR4__DENALI_PI_162__PI_DISCONNECT_MC_WOCLR 0U +#define LPDDR4__DENALI_PI_162__PI_DISCONNECT_MC_WOSET 0U +#define LPDDR4__PI_DISCONNECT_MC__REG DENALI_PI_162 +#define LPDDR4__PI_DISCONNECT_MC__FLD LPDDR4__DENALI_PI_162__PI_DISCONNECT_MC + +#define LPDDR4__DENALI_PI_162__PI_NOTCARE_MC_INIT_START_MASK 0x01000000U +#define LPDDR4__DENALI_PI_162__PI_NOTCARE_MC_INIT_START_SHIFT 24U +#define LPDDR4__DENALI_PI_162__PI_NOTCARE_MC_INIT_START_WIDTH 1U +#define LPDDR4__DENALI_PI_162__PI_NOTCARE_MC_INIT_START_WOCLR 0U +#define LPDDR4__DENALI_PI_162__PI_NOTCARE_MC_INIT_START_WOSET 0U +#define LPDDR4__PI_NOTCARE_MC_INIT_START__REG DENALI_PI_162 +#define LPDDR4__PI_NOTCARE_MC_INIT_START__FLD LPDDR4__DENALI_PI_162__PI_NOTCARE_MC_INIT_START + +#define LPDDR4__DENALI_PI_163_READ_MASK 0xFFFFFF01U +#define LPDDR4__DENALI_PI_163_WRITE_MASK 0xFFFFFF01U +#define LPDDR4__DENALI_PI_163__PI_TRACE_MC_MR13_MASK 0x00000001U +#define LPDDR4__DENALI_PI_163__PI_TRACE_MC_MR13_SHIFT 0U +#define LPDDR4__DENALI_PI_163__PI_TRACE_MC_MR13_WIDTH 1U +#define LPDDR4__DENALI_PI_163__PI_TRACE_MC_MR13_WOCLR 0U +#define LPDDR4__DENALI_PI_163__PI_TRACE_MC_MR13_WOSET 0U +#define LPDDR4__PI_TRACE_MC_MR13__REG DENALI_PI_163 +#define LPDDR4__PI_TRACE_MC_MR13__FLD LPDDR4__DENALI_PI_163__PI_TRACE_MC_MR13 + +#define LPDDR4__DENALI_PI_163__PI_TSDO_F0_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_163__PI_TSDO_F0_SHIFT 8U +#define LPDDR4__DENALI_PI_163__PI_TSDO_F0_WIDTH 8U +#define LPDDR4__PI_TSDO_F0__REG DENALI_PI_163 +#define LPDDR4__PI_TSDO_F0__FLD LPDDR4__DENALI_PI_163__PI_TSDO_F0 + +#define LPDDR4__DENALI_PI_163__PI_TSDO_F1_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_163__PI_TSDO_F1_SHIFT 16U +#define LPDDR4__DENALI_PI_163__PI_TSDO_F1_WIDTH 8U +#define LPDDR4__PI_TSDO_F1__REG DENALI_PI_163 +#define LPDDR4__PI_TSDO_F1__FLD LPDDR4__DENALI_PI_163__PI_TSDO_F1 + +#define LPDDR4__DENALI_PI_163__PI_TSDO_F2_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_163__PI_TSDO_F2_SHIFT 24U +#define LPDDR4__DENALI_PI_163__PI_TSDO_F2_WIDTH 8U +#define LPDDR4__PI_TSDO_F2__REG DENALI_PI_163 +#define LPDDR4__PI_TSDO_F2__FLD LPDDR4__DENALI_PI_163__PI_TSDO_F2 + +#define LPDDR4__DENALI_PI_164_READ_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_164_WRITE_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_164__PI_TDELAY_RDWR_2_BUS_IDLE_F0_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_164__PI_TDELAY_RDWR_2_BUS_IDLE_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_164__PI_TDELAY_RDWR_2_BUS_IDLE_F0_WIDTH 8U +#define LPDDR4__PI_TDELAY_RDWR_2_BUS_IDLE_F0__REG DENALI_PI_164 +#define LPDDR4__PI_TDELAY_RDWR_2_BUS_IDLE_F0__FLD LPDDR4__DENALI_PI_164__PI_TDELAY_RDWR_2_BUS_IDLE_F0 + +#define LPDDR4__DENALI_PI_165_READ_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_165_WRITE_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_165__PI_TDELAY_RDWR_2_BUS_IDLE_F1_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_165__PI_TDELAY_RDWR_2_BUS_IDLE_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_165__PI_TDELAY_RDWR_2_BUS_IDLE_F1_WIDTH 8U +#define LPDDR4__PI_TDELAY_RDWR_2_BUS_IDLE_F1__REG DENALI_PI_165 +#define LPDDR4__PI_TDELAY_RDWR_2_BUS_IDLE_F1__FLD LPDDR4__DENALI_PI_165__PI_TDELAY_RDWR_2_BUS_IDLE_F1 + +#define LPDDR4__DENALI_PI_166_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PI_166_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PI_166__PI_TDELAY_RDWR_2_BUS_IDLE_F2_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_166__PI_TDELAY_RDWR_2_BUS_IDLE_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_166__PI_TDELAY_RDWR_2_BUS_IDLE_F2_WIDTH 8U +#define LPDDR4__PI_TDELAY_RDWR_2_BUS_IDLE_F2__REG DENALI_PI_166 +#define LPDDR4__PI_TDELAY_RDWR_2_BUS_IDLE_F2__FLD LPDDR4__DENALI_PI_166__PI_TDELAY_RDWR_2_BUS_IDLE_F2 + +#define LPDDR4__DENALI_PI_166__PI_ZQINIT_F0_MASK 0x000FFF00U +#define LPDDR4__DENALI_PI_166__PI_ZQINIT_F0_SHIFT 8U +#define LPDDR4__DENALI_PI_166__PI_ZQINIT_F0_WIDTH 12U +#define LPDDR4__PI_ZQINIT_F0__REG DENALI_PI_166 +#define LPDDR4__PI_ZQINIT_F0__FLD LPDDR4__DENALI_PI_166__PI_ZQINIT_F0 + +#define LPDDR4__DENALI_PI_167_READ_MASK 0x0FFF0FFFU +#define LPDDR4__DENALI_PI_167_WRITE_MASK 0x0FFF0FFFU +#define LPDDR4__DENALI_PI_167__PI_ZQINIT_F1_MASK 0x00000FFFU +#define LPDDR4__DENALI_PI_167__PI_ZQINIT_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_167__PI_ZQINIT_F1_WIDTH 12U +#define LPDDR4__PI_ZQINIT_F1__REG DENALI_PI_167 +#define LPDDR4__PI_ZQINIT_F1__FLD LPDDR4__DENALI_PI_167__PI_ZQINIT_F1 + +#define LPDDR4__DENALI_PI_167__PI_ZQINIT_F2_MASK 0x0FFF0000U +#define LPDDR4__DENALI_PI_167__PI_ZQINIT_F2_SHIFT 16U +#define LPDDR4__DENALI_PI_167__PI_ZQINIT_F2_WIDTH 12U +#define LPDDR4__PI_ZQINIT_F2__REG DENALI_PI_167 +#define LPDDR4__PI_ZQINIT_F2__FLD LPDDR4__DENALI_PI_167__PI_ZQINIT_F2 + +#define LPDDR4__DENALI_PI_168_READ_MASK 0x7F7F7F7FU +#define LPDDR4__DENALI_PI_168_WRITE_MASK 0x7F7F7F7FU +#define LPDDR4__DENALI_PI_168__PI_WRLAT_F0_MASK 0x0000007FU +#define LPDDR4__DENALI_PI_168__PI_WRLAT_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_168__PI_WRLAT_F0_WIDTH 7U +#define LPDDR4__PI_WRLAT_F0__REG DENALI_PI_168 +#define LPDDR4__PI_WRLAT_F0__FLD LPDDR4__DENALI_PI_168__PI_WRLAT_F0 + +#define LPDDR4__DENALI_PI_168__PI_CASLAT_LIN_F0_MASK 0x00007F00U +#define LPDDR4__DENALI_PI_168__PI_CASLAT_LIN_F0_SHIFT 8U +#define LPDDR4__DENALI_PI_168__PI_CASLAT_LIN_F0_WIDTH 7U +#define LPDDR4__PI_CASLAT_LIN_F0__REG DENALI_PI_168 +#define LPDDR4__PI_CASLAT_LIN_F0__FLD LPDDR4__DENALI_PI_168__PI_CASLAT_LIN_F0 + +#define LPDDR4__DENALI_PI_168__PI_WRLAT_F1_MASK 0x007F0000U +#define LPDDR4__DENALI_PI_168__PI_WRLAT_F1_SHIFT 16U +#define LPDDR4__DENALI_PI_168__PI_WRLAT_F1_WIDTH 7U +#define LPDDR4__PI_WRLAT_F1__REG DENALI_PI_168 +#define LPDDR4__PI_WRLAT_F1__FLD LPDDR4__DENALI_PI_168__PI_WRLAT_F1 + +#define LPDDR4__DENALI_PI_168__PI_CASLAT_LIN_F1_MASK 0x7F000000U +#define LPDDR4__DENALI_PI_168__PI_CASLAT_LIN_F1_SHIFT 24U +#define LPDDR4__DENALI_PI_168__PI_CASLAT_LIN_F1_WIDTH 7U +#define LPDDR4__PI_CASLAT_LIN_F1__REG DENALI_PI_168 +#define LPDDR4__PI_CASLAT_LIN_F1__FLD LPDDR4__DENALI_PI_168__PI_CASLAT_LIN_F1 + +#define LPDDR4__DENALI_PI_169_READ_MASK 0x03FF7F7FU +#define LPDDR4__DENALI_PI_169_WRITE_MASK 0x03FF7F7FU +#define LPDDR4__DENALI_PI_169__PI_WRLAT_F2_MASK 0x0000007FU +#define LPDDR4__DENALI_PI_169__PI_WRLAT_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_169__PI_WRLAT_F2_WIDTH 7U +#define LPDDR4__PI_WRLAT_F2__REG DENALI_PI_169 +#define LPDDR4__PI_WRLAT_F2__FLD LPDDR4__DENALI_PI_169__PI_WRLAT_F2 + +#define LPDDR4__DENALI_PI_169__PI_CASLAT_LIN_F2_MASK 0x00007F00U +#define LPDDR4__DENALI_PI_169__PI_CASLAT_LIN_F2_SHIFT 8U +#define LPDDR4__DENALI_PI_169__PI_CASLAT_LIN_F2_WIDTH 7U +#define LPDDR4__PI_CASLAT_LIN_F2__REG DENALI_PI_169 +#define LPDDR4__PI_CASLAT_LIN_F2__FLD LPDDR4__DENALI_PI_169__PI_CASLAT_LIN_F2 + +#define LPDDR4__DENALI_PI_169__PI_TRFC_F0_MASK 0x03FF0000U +#define LPDDR4__DENALI_PI_169__PI_TRFC_F0_SHIFT 16U +#define LPDDR4__DENALI_PI_169__PI_TRFC_F0_WIDTH 10U +#define LPDDR4__PI_TRFC_F0__REG DENALI_PI_169 +#define LPDDR4__PI_TRFC_F0__FLD LPDDR4__DENALI_PI_169__PI_TRFC_F0 + +#define LPDDR4__DENALI_PI_170_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PI_170_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PI_170__PI_TREF_F0_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PI_170__PI_TREF_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_170__PI_TREF_F0_WIDTH 20U +#define LPDDR4__PI_TREF_F0__REG DENALI_PI_170 +#define LPDDR4__PI_TREF_F0__FLD LPDDR4__DENALI_PI_170__PI_TREF_F0 + +#define LPDDR4__DENALI_PI_171_READ_MASK 0x000003FFU +#define LPDDR4__DENALI_PI_171_WRITE_MASK 0x000003FFU +#define LPDDR4__DENALI_PI_171__PI_TRFC_F1_MASK 0x000003FFU +#define LPDDR4__DENALI_PI_171__PI_TRFC_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_171__PI_TRFC_F1_WIDTH 10U +#define LPDDR4__PI_TRFC_F1__REG DENALI_PI_171 +#define LPDDR4__PI_TRFC_F1__FLD LPDDR4__DENALI_PI_171__PI_TRFC_F1 + +#define LPDDR4__DENALI_PI_172_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PI_172_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PI_172__PI_TREF_F1_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PI_172__PI_TREF_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_172__PI_TREF_F1_WIDTH 20U +#define LPDDR4__PI_TREF_F1__REG DENALI_PI_172 +#define LPDDR4__PI_TREF_F1__FLD LPDDR4__DENALI_PI_172__PI_TREF_F1 + +#define LPDDR4__DENALI_PI_173_READ_MASK 0x000003FFU +#define LPDDR4__DENALI_PI_173_WRITE_MASK 0x000003FFU +#define LPDDR4__DENALI_PI_173__PI_TRFC_F2_MASK 0x000003FFU +#define LPDDR4__DENALI_PI_173__PI_TRFC_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_173__PI_TRFC_F2_WIDTH 10U +#define LPDDR4__PI_TRFC_F2__REG DENALI_PI_173 +#define LPDDR4__PI_TRFC_F2__FLD LPDDR4__DENALI_PI_173__PI_TRFC_F2 + +#define LPDDR4__DENALI_PI_174_READ_MASK 0x0F0FFFFFU +#define LPDDR4__DENALI_PI_174_WRITE_MASK 0x0F0FFFFFU +#define LPDDR4__DENALI_PI_174__PI_TREF_F2_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PI_174__PI_TREF_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_174__PI_TREF_F2_WIDTH 20U +#define LPDDR4__PI_TREF_F2__REG DENALI_PI_174 +#define LPDDR4__PI_TREF_F2__FLD LPDDR4__DENALI_PI_174__PI_TREF_F2 + +#define LPDDR4__DENALI_PI_174__PI_TDFI_CTRL_DELAY_F0_MASK 0x0F000000U +#define LPDDR4__DENALI_PI_174__PI_TDFI_CTRL_DELAY_F0_SHIFT 24U +#define LPDDR4__DENALI_PI_174__PI_TDFI_CTRL_DELAY_F0_WIDTH 4U +#define LPDDR4__PI_TDFI_CTRL_DELAY_F0__REG DENALI_PI_174 +#define LPDDR4__PI_TDFI_CTRL_DELAY_F0__FLD LPDDR4__DENALI_PI_174__PI_TDFI_CTRL_DELAY_F0 + +#define LPDDR4__DENALI_PI_175_READ_MASK 0x03030F0FU +#define LPDDR4__DENALI_PI_175_WRITE_MASK 0x03030F0FU +#define LPDDR4__DENALI_PI_175__PI_TDFI_CTRL_DELAY_F1_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_175__PI_TDFI_CTRL_DELAY_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_175__PI_TDFI_CTRL_DELAY_F1_WIDTH 4U +#define LPDDR4__PI_TDFI_CTRL_DELAY_F1__REG DENALI_PI_175 +#define LPDDR4__PI_TDFI_CTRL_DELAY_F1__FLD LPDDR4__DENALI_PI_175__PI_TDFI_CTRL_DELAY_F1 + +#define LPDDR4__DENALI_PI_175__PI_TDFI_CTRL_DELAY_F2_MASK 0x00000F00U +#define LPDDR4__DENALI_PI_175__PI_TDFI_CTRL_DELAY_F2_SHIFT 8U +#define LPDDR4__DENALI_PI_175__PI_TDFI_CTRL_DELAY_F2_WIDTH 4U +#define LPDDR4__PI_TDFI_CTRL_DELAY_F2__REG DENALI_PI_175 +#define LPDDR4__PI_TDFI_CTRL_DELAY_F2__FLD LPDDR4__DENALI_PI_175__PI_TDFI_CTRL_DELAY_F2 + +#define LPDDR4__DENALI_PI_175__PI_WRLVL_EN_F0_MASK 0x00030000U +#define LPDDR4__DENALI_PI_175__PI_WRLVL_EN_F0_SHIFT 16U +#define LPDDR4__DENALI_PI_175__PI_WRLVL_EN_F0_WIDTH 2U +#define LPDDR4__PI_WRLVL_EN_F0__REG DENALI_PI_175 +#define LPDDR4__PI_WRLVL_EN_F0__FLD LPDDR4__DENALI_PI_175__PI_WRLVL_EN_F0 + +#define LPDDR4__DENALI_PI_175__PI_WRLVL_EN_F1_MASK 0x03000000U +#define LPDDR4__DENALI_PI_175__PI_WRLVL_EN_F1_SHIFT 24U +#define LPDDR4__DENALI_PI_175__PI_WRLVL_EN_F1_WIDTH 2U +#define LPDDR4__PI_WRLVL_EN_F1__REG DENALI_PI_175 +#define LPDDR4__PI_WRLVL_EN_F1__FLD LPDDR4__DENALI_PI_175__PI_WRLVL_EN_F1 + +#define LPDDR4__DENALI_PI_176_READ_MASK 0x0003FF03U +#define LPDDR4__DENALI_PI_176_WRITE_MASK 0x0003FF03U +#define LPDDR4__DENALI_PI_176__PI_WRLVL_EN_F2_MASK 0x00000003U +#define LPDDR4__DENALI_PI_176__PI_WRLVL_EN_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_176__PI_WRLVL_EN_F2_WIDTH 2U +#define LPDDR4__PI_WRLVL_EN_F2__REG DENALI_PI_176 +#define LPDDR4__PI_WRLVL_EN_F2__FLD LPDDR4__DENALI_PI_176__PI_WRLVL_EN_F2 + +#define LPDDR4__DENALI_PI_176__PI_TDFI_WRLVL_WW_F0_MASK 0x0003FF00U +#define LPDDR4__DENALI_PI_176__PI_TDFI_WRLVL_WW_F0_SHIFT 8U +#define LPDDR4__DENALI_PI_176__PI_TDFI_WRLVL_WW_F0_WIDTH 10U +#define LPDDR4__PI_TDFI_WRLVL_WW_F0__REG DENALI_PI_176 +#define LPDDR4__PI_TDFI_WRLVL_WW_F0__FLD LPDDR4__DENALI_PI_176__PI_TDFI_WRLVL_WW_F0 + +#define LPDDR4__DENALI_PI_177_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PI_177_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PI_177__PI_TDFI_WRLVL_WW_F1_MASK 0x000003FFU +#define LPDDR4__DENALI_PI_177__PI_TDFI_WRLVL_WW_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_177__PI_TDFI_WRLVL_WW_F1_WIDTH 10U +#define LPDDR4__PI_TDFI_WRLVL_WW_F1__REG DENALI_PI_177 +#define LPDDR4__PI_TDFI_WRLVL_WW_F1__FLD LPDDR4__DENALI_PI_177__PI_TDFI_WRLVL_WW_F1 + +#define LPDDR4__DENALI_PI_177__PI_TDFI_WRLVL_WW_F2_MASK 0x03FF0000U +#define LPDDR4__DENALI_PI_177__PI_TDFI_WRLVL_WW_F2_SHIFT 16U +#define LPDDR4__DENALI_PI_177__PI_TDFI_WRLVL_WW_F2_WIDTH 10U +#define LPDDR4__PI_TDFI_WRLVL_WW_F2__REG DENALI_PI_177 +#define LPDDR4__PI_TDFI_WRLVL_WW_F2__FLD LPDDR4__DENALI_PI_177__PI_TDFI_WRLVL_WW_F2 + +#define LPDDR4__DENALI_PI_178_READ_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PI_178_WRITE_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PI_178__PI_TODTL_2CMD_F0_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_178__PI_TODTL_2CMD_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_178__PI_TODTL_2CMD_F0_WIDTH 8U +#define LPDDR4__PI_TODTL_2CMD_F0__REG DENALI_PI_178 +#define LPDDR4__PI_TODTL_2CMD_F0__FLD LPDDR4__DENALI_PI_178__PI_TODTL_2CMD_F0 + +#define LPDDR4__DENALI_PI_178__PI_ODT_EN_F0_MASK 0x00000100U +#define LPDDR4__DENALI_PI_178__PI_ODT_EN_F0_SHIFT 8U +#define LPDDR4__DENALI_PI_178__PI_ODT_EN_F0_WIDTH 1U +#define LPDDR4__DENALI_PI_178__PI_ODT_EN_F0_WOCLR 0U +#define LPDDR4__DENALI_PI_178__PI_ODT_EN_F0_WOSET 0U +#define LPDDR4__PI_ODT_EN_F0__REG DENALI_PI_178 +#define LPDDR4__PI_ODT_EN_F0__FLD LPDDR4__DENALI_PI_178__PI_ODT_EN_F0 + +#define LPDDR4__DENALI_PI_178__PI_TODTL_2CMD_F1_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_178__PI_TODTL_2CMD_F1_SHIFT 16U +#define LPDDR4__DENALI_PI_178__PI_TODTL_2CMD_F1_WIDTH 8U +#define LPDDR4__PI_TODTL_2CMD_F1__REG DENALI_PI_178 +#define LPDDR4__PI_TODTL_2CMD_F1__FLD LPDDR4__DENALI_PI_178__PI_TODTL_2CMD_F1 + +#define LPDDR4__DENALI_PI_178__PI_ODT_EN_F1_MASK 0x01000000U +#define LPDDR4__DENALI_PI_178__PI_ODT_EN_F1_SHIFT 24U +#define LPDDR4__DENALI_PI_178__PI_ODT_EN_F1_WIDTH 1U +#define LPDDR4__DENALI_PI_178__PI_ODT_EN_F1_WOCLR 0U +#define LPDDR4__DENALI_PI_178__PI_ODT_EN_F1_WOSET 0U +#define LPDDR4__PI_ODT_EN_F1__REG DENALI_PI_178 +#define LPDDR4__PI_ODT_EN_F1__FLD LPDDR4__DENALI_PI_178__PI_ODT_EN_F1 + +#define LPDDR4__DENALI_PI_179_READ_MASK 0x0F0F01FFU +#define LPDDR4__DENALI_PI_179_WRITE_MASK 0x0F0F01FFU +#define LPDDR4__DENALI_PI_179__PI_TODTL_2CMD_F2_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_179__PI_TODTL_2CMD_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_179__PI_TODTL_2CMD_F2_WIDTH 8U +#define LPDDR4__PI_TODTL_2CMD_F2__REG DENALI_PI_179 +#define LPDDR4__PI_TODTL_2CMD_F2__FLD LPDDR4__DENALI_PI_179__PI_TODTL_2CMD_F2 + +#define LPDDR4__DENALI_PI_179__PI_ODT_EN_F2_MASK 0x00000100U +#define LPDDR4__DENALI_PI_179__PI_ODT_EN_F2_SHIFT 8U +#define LPDDR4__DENALI_PI_179__PI_ODT_EN_F2_WIDTH 1U +#define LPDDR4__DENALI_PI_179__PI_ODT_EN_F2_WOCLR 0U +#define LPDDR4__DENALI_PI_179__PI_ODT_EN_F2_WOSET 0U +#define LPDDR4__PI_ODT_EN_F2__REG DENALI_PI_179 +#define LPDDR4__PI_ODT_EN_F2__FLD LPDDR4__DENALI_PI_179__PI_ODT_EN_F2 + +#define LPDDR4__DENALI_PI_179__PI_ODTLON_F0_MASK 0x000F0000U +#define LPDDR4__DENALI_PI_179__PI_ODTLON_F0_SHIFT 16U +#define LPDDR4__DENALI_PI_179__PI_ODTLON_F0_WIDTH 4U +#define LPDDR4__PI_ODTLON_F0__REG DENALI_PI_179 +#define LPDDR4__PI_ODTLON_F0__FLD LPDDR4__DENALI_PI_179__PI_ODTLON_F0 + +#define LPDDR4__DENALI_PI_179__PI_TODTON_MIN_F0_MASK 0x0F000000U +#define LPDDR4__DENALI_PI_179__PI_TODTON_MIN_F0_SHIFT 24U +#define LPDDR4__DENALI_PI_179__PI_TODTON_MIN_F0_WIDTH 4U +#define LPDDR4__PI_TODTON_MIN_F0__REG DENALI_PI_179 +#define LPDDR4__PI_TODTON_MIN_F0__FLD LPDDR4__DENALI_PI_179__PI_TODTON_MIN_F0 + +#define LPDDR4__DENALI_PI_180_READ_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_PI_180_WRITE_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_PI_180__PI_ODTLON_F1_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_180__PI_ODTLON_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_180__PI_ODTLON_F1_WIDTH 4U +#define LPDDR4__PI_ODTLON_F1__REG DENALI_PI_180 +#define LPDDR4__PI_ODTLON_F1__FLD LPDDR4__DENALI_PI_180__PI_ODTLON_F1 + +#define LPDDR4__DENALI_PI_180__PI_TODTON_MIN_F1_MASK 0x00000F00U +#define LPDDR4__DENALI_PI_180__PI_TODTON_MIN_F1_SHIFT 8U +#define LPDDR4__DENALI_PI_180__PI_TODTON_MIN_F1_WIDTH 4U +#define LPDDR4__PI_TODTON_MIN_F1__REG DENALI_PI_180 +#define LPDDR4__PI_TODTON_MIN_F1__FLD LPDDR4__DENALI_PI_180__PI_TODTON_MIN_F1 + +#define LPDDR4__DENALI_PI_180__PI_ODTLON_F2_MASK 0x000F0000U +#define LPDDR4__DENALI_PI_180__PI_ODTLON_F2_SHIFT 16U +#define LPDDR4__DENALI_PI_180__PI_ODTLON_F2_WIDTH 4U +#define LPDDR4__PI_ODTLON_F2__REG DENALI_PI_180 +#define LPDDR4__PI_ODTLON_F2__FLD LPDDR4__DENALI_PI_180__PI_ODTLON_F2 + +#define LPDDR4__DENALI_PI_180__PI_TODTON_MIN_F2_MASK 0x0F000000U +#define LPDDR4__DENALI_PI_180__PI_TODTON_MIN_F2_SHIFT 24U +#define LPDDR4__DENALI_PI_180__PI_TODTON_MIN_F2_WIDTH 4U +#define LPDDR4__PI_TODTON_MIN_F2__REG DENALI_PI_180 +#define LPDDR4__PI_TODTON_MIN_F2__FLD LPDDR4__DENALI_PI_180__PI_TODTON_MIN_F2 + +#define LPDDR4__DENALI_PI_181_READ_MASK 0x03030303U +#define LPDDR4__DENALI_PI_181_WRITE_MASK 0x03030303U +#define LPDDR4__DENALI_PI_181__PI_RDLVL_EN_F0_MASK 0x00000003U +#define LPDDR4__DENALI_PI_181__PI_RDLVL_EN_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_181__PI_RDLVL_EN_F0_WIDTH 2U +#define LPDDR4__PI_RDLVL_EN_F0__REG DENALI_PI_181 +#define LPDDR4__PI_RDLVL_EN_F0__FLD LPDDR4__DENALI_PI_181__PI_RDLVL_EN_F0 + +#define LPDDR4__DENALI_PI_181__PI_RDLVL_GATE_EN_F0_MASK 0x00000300U +#define LPDDR4__DENALI_PI_181__PI_RDLVL_GATE_EN_F0_SHIFT 8U +#define LPDDR4__DENALI_PI_181__PI_RDLVL_GATE_EN_F0_WIDTH 2U +#define LPDDR4__PI_RDLVL_GATE_EN_F0__REG DENALI_PI_181 +#define LPDDR4__PI_RDLVL_GATE_EN_F0__FLD LPDDR4__DENALI_PI_181__PI_RDLVL_GATE_EN_F0 + +#define LPDDR4__DENALI_PI_181__PI_RDLVL_EN_F1_MASK 0x00030000U +#define LPDDR4__DENALI_PI_181__PI_RDLVL_EN_F1_SHIFT 16U +#define LPDDR4__DENALI_PI_181__PI_RDLVL_EN_F1_WIDTH 2U +#define LPDDR4__PI_RDLVL_EN_F1__REG DENALI_PI_181 +#define LPDDR4__PI_RDLVL_EN_F1__FLD LPDDR4__DENALI_PI_181__PI_RDLVL_EN_F1 + +#define LPDDR4__DENALI_PI_181__PI_RDLVL_GATE_EN_F1_MASK 0x03000000U +#define LPDDR4__DENALI_PI_181__PI_RDLVL_GATE_EN_F1_SHIFT 24U +#define LPDDR4__DENALI_PI_181__PI_RDLVL_GATE_EN_F1_WIDTH 2U +#define LPDDR4__PI_RDLVL_GATE_EN_F1__REG DENALI_PI_181 +#define LPDDR4__PI_RDLVL_GATE_EN_F1__FLD LPDDR4__DENALI_PI_181__PI_RDLVL_GATE_EN_F1 + +#define LPDDR4__DENALI_PI_182_READ_MASK 0x03030303U +#define LPDDR4__DENALI_PI_182_WRITE_MASK 0x03030303U +#define LPDDR4__DENALI_PI_182__PI_RDLVL_EN_F2_MASK 0x00000003U +#define LPDDR4__DENALI_PI_182__PI_RDLVL_EN_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_182__PI_RDLVL_EN_F2_WIDTH 2U +#define LPDDR4__PI_RDLVL_EN_F2__REG DENALI_PI_182 +#define LPDDR4__PI_RDLVL_EN_F2__FLD LPDDR4__DENALI_PI_182__PI_RDLVL_EN_F2 + +#define LPDDR4__DENALI_PI_182__PI_RDLVL_GATE_EN_F2_MASK 0x00000300U +#define LPDDR4__DENALI_PI_182__PI_RDLVL_GATE_EN_F2_SHIFT 8U +#define LPDDR4__DENALI_PI_182__PI_RDLVL_GATE_EN_F2_WIDTH 2U +#define LPDDR4__PI_RDLVL_GATE_EN_F2__REG DENALI_PI_182 +#define LPDDR4__PI_RDLVL_GATE_EN_F2__FLD LPDDR4__DENALI_PI_182__PI_RDLVL_GATE_EN_F2 + +#define LPDDR4__DENALI_PI_182__PI_RDLVL_PAT0_EN_F0_MASK 0x00030000U +#define LPDDR4__DENALI_PI_182__PI_RDLVL_PAT0_EN_F0_SHIFT 16U +#define LPDDR4__DENALI_PI_182__PI_RDLVL_PAT0_EN_F0_WIDTH 2U +#define LPDDR4__PI_RDLVL_PAT0_EN_F0__REG DENALI_PI_182 +#define LPDDR4__PI_RDLVL_PAT0_EN_F0__FLD LPDDR4__DENALI_PI_182__PI_RDLVL_PAT0_EN_F0 + +#define LPDDR4__DENALI_PI_182__PI_RDLVL_RXCAL_EN_F0_MASK 0x03000000U +#define LPDDR4__DENALI_PI_182__PI_RDLVL_RXCAL_EN_F0_SHIFT 24U +#define LPDDR4__DENALI_PI_182__PI_RDLVL_RXCAL_EN_F0_WIDTH 2U +#define LPDDR4__PI_RDLVL_RXCAL_EN_F0__REG DENALI_PI_182 +#define LPDDR4__PI_RDLVL_RXCAL_EN_F0__FLD LPDDR4__DENALI_PI_182__PI_RDLVL_RXCAL_EN_F0 + +#define LPDDR4__DENALI_PI_183_READ_MASK 0x03030303U +#define LPDDR4__DENALI_PI_183_WRITE_MASK 0x03030303U +#define LPDDR4__DENALI_PI_183__PI_RDLVL_DFE_EN_F0_MASK 0x00000003U +#define LPDDR4__DENALI_PI_183__PI_RDLVL_DFE_EN_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_183__PI_RDLVL_DFE_EN_F0_WIDTH 2U +#define LPDDR4__PI_RDLVL_DFE_EN_F0__REG DENALI_PI_183 +#define LPDDR4__PI_RDLVL_DFE_EN_F0__FLD LPDDR4__DENALI_PI_183__PI_RDLVL_DFE_EN_F0 + +#define LPDDR4__DENALI_PI_183__PI_RDLVL_MULTI_EN_F0_MASK 0x00000300U +#define LPDDR4__DENALI_PI_183__PI_RDLVL_MULTI_EN_F0_SHIFT 8U +#define LPDDR4__DENALI_PI_183__PI_RDLVL_MULTI_EN_F0_WIDTH 2U +#define LPDDR4__PI_RDLVL_MULTI_EN_F0__REG DENALI_PI_183 +#define LPDDR4__PI_RDLVL_MULTI_EN_F0__FLD LPDDR4__DENALI_PI_183__PI_RDLVL_MULTI_EN_F0 + +#define LPDDR4__DENALI_PI_183__PI_RDLVL_PAT0_EN_F1_MASK 0x00030000U +#define LPDDR4__DENALI_PI_183__PI_RDLVL_PAT0_EN_F1_SHIFT 16U +#define LPDDR4__DENALI_PI_183__PI_RDLVL_PAT0_EN_F1_WIDTH 2U +#define LPDDR4__PI_RDLVL_PAT0_EN_F1__REG DENALI_PI_183 +#define LPDDR4__PI_RDLVL_PAT0_EN_F1__FLD LPDDR4__DENALI_PI_183__PI_RDLVL_PAT0_EN_F1 + +#define LPDDR4__DENALI_PI_183__PI_RDLVL_RXCAL_EN_F1_MASK 0x03000000U +#define LPDDR4__DENALI_PI_183__PI_RDLVL_RXCAL_EN_F1_SHIFT 24U +#define LPDDR4__DENALI_PI_183__PI_RDLVL_RXCAL_EN_F1_WIDTH 2U +#define LPDDR4__PI_RDLVL_RXCAL_EN_F1__REG DENALI_PI_183 +#define LPDDR4__PI_RDLVL_RXCAL_EN_F1__FLD LPDDR4__DENALI_PI_183__PI_RDLVL_RXCAL_EN_F1 + +#define LPDDR4__DENALI_PI_184_READ_MASK 0x03030303U +#define LPDDR4__DENALI_PI_184_WRITE_MASK 0x03030303U +#define LPDDR4__DENALI_PI_184__PI_RDLVL_DFE_EN_F1_MASK 0x00000003U +#define LPDDR4__DENALI_PI_184__PI_RDLVL_DFE_EN_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_184__PI_RDLVL_DFE_EN_F1_WIDTH 2U +#define LPDDR4__PI_RDLVL_DFE_EN_F1__REG DENALI_PI_184 +#define LPDDR4__PI_RDLVL_DFE_EN_F1__FLD LPDDR4__DENALI_PI_184__PI_RDLVL_DFE_EN_F1 + +#define LPDDR4__DENALI_PI_184__PI_RDLVL_MULTI_EN_F1_MASK 0x00000300U +#define LPDDR4__DENALI_PI_184__PI_RDLVL_MULTI_EN_F1_SHIFT 8U +#define LPDDR4__DENALI_PI_184__PI_RDLVL_MULTI_EN_F1_WIDTH 2U +#define LPDDR4__PI_RDLVL_MULTI_EN_F1__REG DENALI_PI_184 +#define LPDDR4__PI_RDLVL_MULTI_EN_F1__FLD LPDDR4__DENALI_PI_184__PI_RDLVL_MULTI_EN_F1 + +#define LPDDR4__DENALI_PI_184__PI_RDLVL_PAT0_EN_F2_MASK 0x00030000U +#define LPDDR4__DENALI_PI_184__PI_RDLVL_PAT0_EN_F2_SHIFT 16U +#define LPDDR4__DENALI_PI_184__PI_RDLVL_PAT0_EN_F2_WIDTH 2U +#define LPDDR4__PI_RDLVL_PAT0_EN_F2__REG DENALI_PI_184 +#define LPDDR4__PI_RDLVL_PAT0_EN_F2__FLD LPDDR4__DENALI_PI_184__PI_RDLVL_PAT0_EN_F2 + +#define LPDDR4__DENALI_PI_184__PI_RDLVL_RXCAL_EN_F2_MASK 0x03000000U +#define LPDDR4__DENALI_PI_184__PI_RDLVL_RXCAL_EN_F2_SHIFT 24U +#define LPDDR4__DENALI_PI_184__PI_RDLVL_RXCAL_EN_F2_WIDTH 2U +#define LPDDR4__PI_RDLVL_RXCAL_EN_F2__REG DENALI_PI_184 +#define LPDDR4__PI_RDLVL_RXCAL_EN_F2__FLD LPDDR4__DENALI_PI_184__PI_RDLVL_RXCAL_EN_F2 + +#define LPDDR4__DENALI_PI_185_READ_MASK 0x7F7F0303U +#define LPDDR4__DENALI_PI_185_WRITE_MASK 0x7F7F0303U +#define LPDDR4__DENALI_PI_185__PI_RDLVL_DFE_EN_F2_MASK 0x00000003U +#define LPDDR4__DENALI_PI_185__PI_RDLVL_DFE_EN_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_185__PI_RDLVL_DFE_EN_F2_WIDTH 2U +#define LPDDR4__PI_RDLVL_DFE_EN_F2__REG DENALI_PI_185 +#define LPDDR4__PI_RDLVL_DFE_EN_F2__FLD LPDDR4__DENALI_PI_185__PI_RDLVL_DFE_EN_F2 + +#define LPDDR4__DENALI_PI_185__PI_RDLVL_MULTI_EN_F2_MASK 0x00000300U +#define LPDDR4__DENALI_PI_185__PI_RDLVL_MULTI_EN_F2_SHIFT 8U +#define LPDDR4__DENALI_PI_185__PI_RDLVL_MULTI_EN_F2_WIDTH 2U +#define LPDDR4__PI_RDLVL_MULTI_EN_F2__REG DENALI_PI_185 +#define LPDDR4__PI_RDLVL_MULTI_EN_F2__FLD LPDDR4__DENALI_PI_185__PI_RDLVL_MULTI_EN_F2 + +#define LPDDR4__DENALI_PI_185__PI_RDLAT_ADJ_F0_MASK 0x007F0000U +#define LPDDR4__DENALI_PI_185__PI_RDLAT_ADJ_F0_SHIFT 16U +#define LPDDR4__DENALI_PI_185__PI_RDLAT_ADJ_F0_WIDTH 7U +#define LPDDR4__PI_RDLAT_ADJ_F0__REG DENALI_PI_185 +#define LPDDR4__PI_RDLAT_ADJ_F0__FLD LPDDR4__DENALI_PI_185__PI_RDLAT_ADJ_F0 + +#define LPDDR4__DENALI_PI_185__PI_RDLAT_ADJ_F1_MASK 0x7F000000U +#define LPDDR4__DENALI_PI_185__PI_RDLAT_ADJ_F1_SHIFT 24U +#define LPDDR4__DENALI_PI_185__PI_RDLAT_ADJ_F1_WIDTH 7U +#define LPDDR4__PI_RDLAT_ADJ_F1__REG DENALI_PI_185 +#define LPDDR4__PI_RDLAT_ADJ_F1__FLD LPDDR4__DENALI_PI_185__PI_RDLAT_ADJ_F1 + +#define LPDDR4__DENALI_PI_186_READ_MASK 0x7F7F7F7FU +#define LPDDR4__DENALI_PI_186_WRITE_MASK 0x7F7F7F7FU +#define LPDDR4__DENALI_PI_186__PI_RDLAT_ADJ_F2_MASK 0x0000007FU +#define LPDDR4__DENALI_PI_186__PI_RDLAT_ADJ_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_186__PI_RDLAT_ADJ_F2_WIDTH 7U +#define LPDDR4__PI_RDLAT_ADJ_F2__REG DENALI_PI_186 +#define LPDDR4__PI_RDLAT_ADJ_F2__FLD LPDDR4__DENALI_PI_186__PI_RDLAT_ADJ_F2 + +#define LPDDR4__DENALI_PI_186__PI_WRLAT_ADJ_F0_MASK 0x00007F00U +#define LPDDR4__DENALI_PI_186__PI_WRLAT_ADJ_F0_SHIFT 8U +#define LPDDR4__DENALI_PI_186__PI_WRLAT_ADJ_F0_WIDTH 7U +#define LPDDR4__PI_WRLAT_ADJ_F0__REG DENALI_PI_186 +#define LPDDR4__PI_WRLAT_ADJ_F0__FLD LPDDR4__DENALI_PI_186__PI_WRLAT_ADJ_F0 + +#define LPDDR4__DENALI_PI_186__PI_WRLAT_ADJ_F1_MASK 0x007F0000U +#define LPDDR4__DENALI_PI_186__PI_WRLAT_ADJ_F1_SHIFT 16U +#define LPDDR4__DENALI_PI_186__PI_WRLAT_ADJ_F1_WIDTH 7U +#define LPDDR4__PI_WRLAT_ADJ_F1__REG DENALI_PI_186 +#define LPDDR4__PI_WRLAT_ADJ_F1__FLD LPDDR4__DENALI_PI_186__PI_WRLAT_ADJ_F1 + +#define LPDDR4__DENALI_PI_186__PI_WRLAT_ADJ_F2_MASK 0x7F000000U +#define LPDDR4__DENALI_PI_186__PI_WRLAT_ADJ_F2_SHIFT 24U +#define LPDDR4__DENALI_PI_186__PI_WRLAT_ADJ_F2_WIDTH 7U +#define LPDDR4__PI_WRLAT_ADJ_F2__REG DENALI_PI_186 +#define LPDDR4__PI_WRLAT_ADJ_F2__FLD LPDDR4__DENALI_PI_186__PI_WRLAT_ADJ_F2 + +#define LPDDR4__DENALI_PI_187_READ_MASK 0x00070707U +#define LPDDR4__DENALI_PI_187_WRITE_MASK 0x00070707U +#define LPDDR4__DENALI_PI_187__PI_TDFI_PHY_WRDATA_F0_MASK 0x00000007U +#define LPDDR4__DENALI_PI_187__PI_TDFI_PHY_WRDATA_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_187__PI_TDFI_PHY_WRDATA_F0_WIDTH 3U +#define LPDDR4__PI_TDFI_PHY_WRDATA_F0__REG DENALI_PI_187 +#define LPDDR4__PI_TDFI_PHY_WRDATA_F0__FLD LPDDR4__DENALI_PI_187__PI_TDFI_PHY_WRDATA_F0 + +#define LPDDR4__DENALI_PI_187__PI_TDFI_PHY_WRDATA_F1_MASK 0x00000700U +#define LPDDR4__DENALI_PI_187__PI_TDFI_PHY_WRDATA_F1_SHIFT 8U +#define LPDDR4__DENALI_PI_187__PI_TDFI_PHY_WRDATA_F1_WIDTH 3U +#define LPDDR4__PI_TDFI_PHY_WRDATA_F1__REG DENALI_PI_187 +#define LPDDR4__PI_TDFI_PHY_WRDATA_F1__FLD LPDDR4__DENALI_PI_187__PI_TDFI_PHY_WRDATA_F1 + +#define LPDDR4__DENALI_PI_187__PI_TDFI_PHY_WRDATA_F2_MASK 0x00070000U +#define LPDDR4__DENALI_PI_187__PI_TDFI_PHY_WRDATA_F2_SHIFT 16U +#define LPDDR4__DENALI_PI_187__PI_TDFI_PHY_WRDATA_F2_WIDTH 3U +#define LPDDR4__PI_TDFI_PHY_WRDATA_F2__REG DENALI_PI_187 +#define LPDDR4__PI_TDFI_PHY_WRDATA_F2__FLD LPDDR4__DENALI_PI_187__PI_TDFI_PHY_WRDATA_F2 + +#define LPDDR4__DENALI_PI_188_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PI_188_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PI_188__PI_TDFI_CALVL_CC_F0_MASK 0x000003FFU +#define LPDDR4__DENALI_PI_188__PI_TDFI_CALVL_CC_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_188__PI_TDFI_CALVL_CC_F0_WIDTH 10U +#define LPDDR4__PI_TDFI_CALVL_CC_F0__REG DENALI_PI_188 +#define LPDDR4__PI_TDFI_CALVL_CC_F0__FLD LPDDR4__DENALI_PI_188__PI_TDFI_CALVL_CC_F0 + +#define LPDDR4__DENALI_PI_188__PI_TDFI_CALVL_CAPTURE_F0_MASK 0x03FF0000U +#define LPDDR4__DENALI_PI_188__PI_TDFI_CALVL_CAPTURE_F0_SHIFT 16U +#define LPDDR4__DENALI_PI_188__PI_TDFI_CALVL_CAPTURE_F0_WIDTH 10U +#define LPDDR4__PI_TDFI_CALVL_CAPTURE_F0__REG DENALI_PI_188 +#define LPDDR4__PI_TDFI_CALVL_CAPTURE_F0__FLD LPDDR4__DENALI_PI_188__PI_TDFI_CALVL_CAPTURE_F0 + +#define LPDDR4__DENALI_PI_189_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PI_189_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PI_189__PI_TDFI_CALVL_CC_F1_MASK 0x000003FFU +#define LPDDR4__DENALI_PI_189__PI_TDFI_CALVL_CC_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_189__PI_TDFI_CALVL_CC_F1_WIDTH 10U +#define LPDDR4__PI_TDFI_CALVL_CC_F1__REG DENALI_PI_189 +#define LPDDR4__PI_TDFI_CALVL_CC_F1__FLD LPDDR4__DENALI_PI_189__PI_TDFI_CALVL_CC_F1 + +#define LPDDR4__DENALI_PI_189__PI_TDFI_CALVL_CAPTURE_F1_MASK 0x03FF0000U +#define LPDDR4__DENALI_PI_189__PI_TDFI_CALVL_CAPTURE_F1_SHIFT 16U +#define LPDDR4__DENALI_PI_189__PI_TDFI_CALVL_CAPTURE_F1_WIDTH 10U +#define LPDDR4__PI_TDFI_CALVL_CAPTURE_F1__REG DENALI_PI_189 +#define LPDDR4__PI_TDFI_CALVL_CAPTURE_F1__FLD LPDDR4__DENALI_PI_189__PI_TDFI_CALVL_CAPTURE_F1 + +#define LPDDR4__DENALI_PI_190_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PI_190_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PI_190__PI_TDFI_CALVL_CC_F2_MASK 0x000003FFU +#define LPDDR4__DENALI_PI_190__PI_TDFI_CALVL_CC_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_190__PI_TDFI_CALVL_CC_F2_WIDTH 10U +#define LPDDR4__PI_TDFI_CALVL_CC_F2__REG DENALI_PI_190 +#define LPDDR4__PI_TDFI_CALVL_CC_F2__FLD LPDDR4__DENALI_PI_190__PI_TDFI_CALVL_CC_F2 + +#define LPDDR4__DENALI_PI_190__PI_TDFI_CALVL_CAPTURE_F2_MASK 0x03FF0000U +#define LPDDR4__DENALI_PI_190__PI_TDFI_CALVL_CAPTURE_F2_SHIFT 16U +#define LPDDR4__DENALI_PI_190__PI_TDFI_CALVL_CAPTURE_F2_WIDTH 10U +#define LPDDR4__PI_TDFI_CALVL_CAPTURE_F2__REG DENALI_PI_190 +#define LPDDR4__PI_TDFI_CALVL_CAPTURE_F2__FLD LPDDR4__DENALI_PI_190__PI_TDFI_CALVL_CAPTURE_F2 + +#define LPDDR4__DENALI_PI_191_READ_MASK 0x1F030303U +#define LPDDR4__DENALI_PI_191_WRITE_MASK 0x1F030303U +#define LPDDR4__DENALI_PI_191__PI_CALVL_EN_F0_MASK 0x00000003U +#define LPDDR4__DENALI_PI_191__PI_CALVL_EN_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_191__PI_CALVL_EN_F0_WIDTH 2U +#define LPDDR4__PI_CALVL_EN_F0__REG DENALI_PI_191 +#define LPDDR4__PI_CALVL_EN_F0__FLD LPDDR4__DENALI_PI_191__PI_CALVL_EN_F0 + +#define LPDDR4__DENALI_PI_191__PI_CALVL_EN_F1_MASK 0x00000300U +#define LPDDR4__DENALI_PI_191__PI_CALVL_EN_F1_SHIFT 8U +#define LPDDR4__DENALI_PI_191__PI_CALVL_EN_F1_WIDTH 2U +#define LPDDR4__PI_CALVL_EN_F1__REG DENALI_PI_191 +#define LPDDR4__PI_CALVL_EN_F1__FLD LPDDR4__DENALI_PI_191__PI_CALVL_EN_F1 + +#define LPDDR4__DENALI_PI_191__PI_CALVL_EN_F2_MASK 0x00030000U +#define LPDDR4__DENALI_PI_191__PI_CALVL_EN_F2_SHIFT 16U +#define LPDDR4__DENALI_PI_191__PI_CALVL_EN_F2_WIDTH 2U +#define LPDDR4__PI_CALVL_EN_F2__REG DENALI_PI_191 +#define LPDDR4__PI_CALVL_EN_F2__FLD LPDDR4__DENALI_PI_191__PI_CALVL_EN_F2 + +#define LPDDR4__DENALI_PI_191__PI_TMRZ_F0_MASK 0x1F000000U +#define LPDDR4__DENALI_PI_191__PI_TMRZ_F0_SHIFT 24U +#define LPDDR4__DENALI_PI_191__PI_TMRZ_F0_WIDTH 5U +#define LPDDR4__PI_TMRZ_F0__REG DENALI_PI_191 +#define LPDDR4__PI_TMRZ_F0__FLD LPDDR4__DENALI_PI_191__PI_TMRZ_F0 + +#define LPDDR4__DENALI_PI_192_READ_MASK 0x001F3FFFU +#define LPDDR4__DENALI_PI_192_WRITE_MASK 0x001F3FFFU +#define LPDDR4__DENALI_PI_192__PI_TCAENT_F0_MASK 0x00003FFFU +#define LPDDR4__DENALI_PI_192__PI_TCAENT_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_192__PI_TCAENT_F0_WIDTH 14U +#define LPDDR4__PI_TCAENT_F0__REG DENALI_PI_192 +#define LPDDR4__PI_TCAENT_F0__FLD LPDDR4__DENALI_PI_192__PI_TCAENT_F0 + +#define LPDDR4__DENALI_PI_192__PI_TMRZ_F1_MASK 0x001F0000U +#define LPDDR4__DENALI_PI_192__PI_TMRZ_F1_SHIFT 16U +#define LPDDR4__DENALI_PI_192__PI_TMRZ_F1_WIDTH 5U +#define LPDDR4__PI_TMRZ_F1__REG DENALI_PI_192 +#define LPDDR4__PI_TMRZ_F1__FLD LPDDR4__DENALI_PI_192__PI_TMRZ_F1 + +#define LPDDR4__DENALI_PI_193_READ_MASK 0x001F3FFFU +#define LPDDR4__DENALI_PI_193_WRITE_MASK 0x001F3FFFU +#define LPDDR4__DENALI_PI_193__PI_TCAENT_F1_MASK 0x00003FFFU +#define LPDDR4__DENALI_PI_193__PI_TCAENT_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_193__PI_TCAENT_F1_WIDTH 14U +#define LPDDR4__PI_TCAENT_F1__REG DENALI_PI_193 +#define LPDDR4__PI_TCAENT_F1__FLD LPDDR4__DENALI_PI_193__PI_TCAENT_F1 + +#define LPDDR4__DENALI_PI_193__PI_TMRZ_F2_MASK 0x001F0000U +#define LPDDR4__DENALI_PI_193__PI_TMRZ_F2_SHIFT 16U +#define LPDDR4__DENALI_PI_193__PI_TMRZ_F2_WIDTH 5U +#define LPDDR4__PI_TMRZ_F2__REG DENALI_PI_193 +#define LPDDR4__PI_TMRZ_F2__FLD LPDDR4__DENALI_PI_193__PI_TMRZ_F2 + +#define LPDDR4__DENALI_PI_194_READ_MASK 0x1F1F3FFFU +#define LPDDR4__DENALI_PI_194_WRITE_MASK 0x1F1F3FFFU +#define LPDDR4__DENALI_PI_194__PI_TCAENT_F2_MASK 0x00003FFFU +#define LPDDR4__DENALI_PI_194__PI_TCAENT_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_194__PI_TCAENT_F2_WIDTH 14U +#define LPDDR4__PI_TCAENT_F2__REG DENALI_PI_194 +#define LPDDR4__PI_TCAENT_F2__FLD LPDDR4__DENALI_PI_194__PI_TCAENT_F2 + +#define LPDDR4__DENALI_PI_194__PI_TDFI_CACSCA_F0_MASK 0x001F0000U +#define LPDDR4__DENALI_PI_194__PI_TDFI_CACSCA_F0_SHIFT 16U +#define LPDDR4__DENALI_PI_194__PI_TDFI_CACSCA_F0_WIDTH 5U +#define LPDDR4__PI_TDFI_CACSCA_F0__REG DENALI_PI_194 +#define LPDDR4__PI_TDFI_CACSCA_F0__FLD LPDDR4__DENALI_PI_194__PI_TDFI_CACSCA_F0 + +#define LPDDR4__DENALI_PI_194__PI_TDFI_CASEL_F0_MASK 0x1F000000U +#define LPDDR4__DENALI_PI_194__PI_TDFI_CASEL_F0_SHIFT 24U +#define LPDDR4__DENALI_PI_194__PI_TDFI_CASEL_F0_WIDTH 5U +#define LPDDR4__PI_TDFI_CASEL_F0__REG DENALI_PI_194 +#define LPDDR4__PI_TDFI_CASEL_F0__FLD LPDDR4__DENALI_PI_194__PI_TDFI_CASEL_F0 + +#define LPDDR4__DENALI_PI_195_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PI_195_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PI_195__PI_TVREF_SHORT_F0_MASK 0x000003FFU +#define LPDDR4__DENALI_PI_195__PI_TVREF_SHORT_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_195__PI_TVREF_SHORT_F0_WIDTH 10U +#define LPDDR4__PI_TVREF_SHORT_F0__REG DENALI_PI_195 +#define LPDDR4__PI_TVREF_SHORT_F0__FLD LPDDR4__DENALI_PI_195__PI_TVREF_SHORT_F0 + +#define LPDDR4__DENALI_PI_195__PI_TVREF_LONG_F0_MASK 0x03FF0000U +#define LPDDR4__DENALI_PI_195__PI_TVREF_LONG_F0_SHIFT 16U +#define LPDDR4__DENALI_PI_195__PI_TVREF_LONG_F0_WIDTH 10U +#define LPDDR4__PI_TVREF_LONG_F0__REG DENALI_PI_195 +#define LPDDR4__PI_TVREF_LONG_F0__FLD LPDDR4__DENALI_PI_195__PI_TVREF_LONG_F0 + +#define LPDDR4__DENALI_PI_196_READ_MASK 0x03FF1F1FU +#define LPDDR4__DENALI_PI_196_WRITE_MASK 0x03FF1F1FU +#define LPDDR4__DENALI_PI_196__PI_TDFI_CACSCA_F1_MASK 0x0000001FU +#define LPDDR4__DENALI_PI_196__PI_TDFI_CACSCA_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_196__PI_TDFI_CACSCA_F1_WIDTH 5U +#define LPDDR4__PI_TDFI_CACSCA_F1__REG DENALI_PI_196 +#define LPDDR4__PI_TDFI_CACSCA_F1__FLD LPDDR4__DENALI_PI_196__PI_TDFI_CACSCA_F1 + +#define LPDDR4__DENALI_PI_196__PI_TDFI_CASEL_F1_MASK 0x00001F00U +#define LPDDR4__DENALI_PI_196__PI_TDFI_CASEL_F1_SHIFT 8U +#define LPDDR4__DENALI_PI_196__PI_TDFI_CASEL_F1_WIDTH 5U +#define LPDDR4__PI_TDFI_CASEL_F1__REG DENALI_PI_196 +#define LPDDR4__PI_TDFI_CASEL_F1__FLD LPDDR4__DENALI_PI_196__PI_TDFI_CASEL_F1 + +#define LPDDR4__DENALI_PI_196__PI_TVREF_SHORT_F1_MASK 0x03FF0000U +#define LPDDR4__DENALI_PI_196__PI_TVREF_SHORT_F1_SHIFT 16U +#define LPDDR4__DENALI_PI_196__PI_TVREF_SHORT_F1_WIDTH 10U +#define LPDDR4__PI_TVREF_SHORT_F1__REG DENALI_PI_196 +#define LPDDR4__PI_TVREF_SHORT_F1__FLD LPDDR4__DENALI_PI_196__PI_TVREF_SHORT_F1 + +#define LPDDR4__DENALI_PI_197_READ_MASK 0x1F1F03FFU +#define LPDDR4__DENALI_PI_197_WRITE_MASK 0x1F1F03FFU +#define LPDDR4__DENALI_PI_197__PI_TVREF_LONG_F1_MASK 0x000003FFU +#define LPDDR4__DENALI_PI_197__PI_TVREF_LONG_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_197__PI_TVREF_LONG_F1_WIDTH 10U +#define LPDDR4__PI_TVREF_LONG_F1__REG DENALI_PI_197 +#define LPDDR4__PI_TVREF_LONG_F1__FLD LPDDR4__DENALI_PI_197__PI_TVREF_LONG_F1 + +#define LPDDR4__DENALI_PI_197__PI_TDFI_CACSCA_F2_MASK 0x001F0000U +#define LPDDR4__DENALI_PI_197__PI_TDFI_CACSCA_F2_SHIFT 16U +#define LPDDR4__DENALI_PI_197__PI_TDFI_CACSCA_F2_WIDTH 5U +#define LPDDR4__PI_TDFI_CACSCA_F2__REG DENALI_PI_197 +#define LPDDR4__PI_TDFI_CACSCA_F2__FLD LPDDR4__DENALI_PI_197__PI_TDFI_CACSCA_F2 + +#define LPDDR4__DENALI_PI_197__PI_TDFI_CASEL_F2_MASK 0x1F000000U +#define LPDDR4__DENALI_PI_197__PI_TDFI_CASEL_F2_SHIFT 24U +#define LPDDR4__DENALI_PI_197__PI_TDFI_CASEL_F2_WIDTH 5U +#define LPDDR4__PI_TDFI_CASEL_F2__REG DENALI_PI_197 +#define LPDDR4__PI_TDFI_CASEL_F2__FLD LPDDR4__DENALI_PI_197__PI_TDFI_CASEL_F2 + +#define LPDDR4__DENALI_PI_198_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PI_198_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PI_198__PI_TVREF_SHORT_F2_MASK 0x000003FFU +#define LPDDR4__DENALI_PI_198__PI_TVREF_SHORT_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_198__PI_TVREF_SHORT_F2_WIDTH 10U +#define LPDDR4__PI_TVREF_SHORT_F2__REG DENALI_PI_198 +#define LPDDR4__PI_TVREF_SHORT_F2__FLD LPDDR4__DENALI_PI_198__PI_TVREF_SHORT_F2 + +#define LPDDR4__DENALI_PI_198__PI_TVREF_LONG_F2_MASK 0x03FF0000U +#define LPDDR4__DENALI_PI_198__PI_TVREF_LONG_F2_SHIFT 16U +#define LPDDR4__DENALI_PI_198__PI_TVREF_LONG_F2_WIDTH 10U +#define LPDDR4__PI_TVREF_LONG_F2__REG DENALI_PI_198 +#define LPDDR4__PI_TVREF_LONG_F2__FLD LPDDR4__DENALI_PI_198__PI_TVREF_LONG_F2 + +#define LPDDR4__DENALI_PI_199_READ_MASK 0x7F7F7F7FU +#define LPDDR4__DENALI_PI_199_WRITE_MASK 0x7F7F7F7FU +#define LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_START_POINT_F0_MASK 0x0000007FU +#define LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_START_POINT_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_START_POINT_F0_WIDTH 7U +#define LPDDR4__PI_CALVL_VREF_INITIAL_START_POINT_F0__REG DENALI_PI_199 +#define LPDDR4__PI_CALVL_VREF_INITIAL_START_POINT_F0__FLD LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_START_POINT_F0 + +#define LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_STOP_POINT_F0_MASK 0x00007F00U +#define LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_STOP_POINT_F0_SHIFT 8U +#define LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_STOP_POINT_F0_WIDTH 7U +#define LPDDR4__PI_CALVL_VREF_INITIAL_STOP_POINT_F0__REG DENALI_PI_199 +#define LPDDR4__PI_CALVL_VREF_INITIAL_STOP_POINT_F0__FLD LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_STOP_POINT_F0 + +#define LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_START_POINT_F1_MASK 0x007F0000U +#define LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_START_POINT_F1_SHIFT 16U +#define LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_START_POINT_F1_WIDTH 7U +#define LPDDR4__PI_CALVL_VREF_INITIAL_START_POINT_F1__REG DENALI_PI_199 +#define LPDDR4__PI_CALVL_VREF_INITIAL_START_POINT_F1__FLD LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_START_POINT_F1 + +#define LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_STOP_POINT_F1_MASK 0x7F000000U +#define LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_STOP_POINT_F1_SHIFT 24U +#define LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_STOP_POINT_F1_WIDTH 7U +#define LPDDR4__PI_CALVL_VREF_INITIAL_STOP_POINT_F1__REG DENALI_PI_199 +#define LPDDR4__PI_CALVL_VREF_INITIAL_STOP_POINT_F1__FLD LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_STOP_POINT_F1 + +#define LPDDR4__DENALI_PI_200_READ_MASK 0x0F0F7F7FU +#define LPDDR4__DENALI_PI_200_WRITE_MASK 0x0F0F7F7FU +#define LPDDR4__DENALI_PI_200__PI_CALVL_VREF_INITIAL_START_POINT_F2_MASK 0x0000007FU +#define LPDDR4__DENALI_PI_200__PI_CALVL_VREF_INITIAL_START_POINT_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_200__PI_CALVL_VREF_INITIAL_START_POINT_F2_WIDTH 7U +#define LPDDR4__PI_CALVL_VREF_INITIAL_START_POINT_F2__REG DENALI_PI_200 +#define LPDDR4__PI_CALVL_VREF_INITIAL_START_POINT_F2__FLD LPDDR4__DENALI_PI_200__PI_CALVL_VREF_INITIAL_START_POINT_F2 + +#define LPDDR4__DENALI_PI_200__PI_CALVL_VREF_INITIAL_STOP_POINT_F2_MASK 0x00007F00U +#define LPDDR4__DENALI_PI_200__PI_CALVL_VREF_INITIAL_STOP_POINT_F2_SHIFT 8U +#define LPDDR4__DENALI_PI_200__PI_CALVL_VREF_INITIAL_STOP_POINT_F2_WIDTH 7U +#define LPDDR4__PI_CALVL_VREF_INITIAL_STOP_POINT_F2__REG DENALI_PI_200 +#define LPDDR4__PI_CALVL_VREF_INITIAL_STOP_POINT_F2__FLD LPDDR4__DENALI_PI_200__PI_CALVL_VREF_INITIAL_STOP_POINT_F2 + +#define LPDDR4__DENALI_PI_200__PI_CALVL_VREF_DELTA_F0_MASK 0x000F0000U +#define LPDDR4__DENALI_PI_200__PI_CALVL_VREF_DELTA_F0_SHIFT 16U +#define LPDDR4__DENALI_PI_200__PI_CALVL_VREF_DELTA_F0_WIDTH 4U +#define LPDDR4__PI_CALVL_VREF_DELTA_F0__REG DENALI_PI_200 +#define LPDDR4__PI_CALVL_VREF_DELTA_F0__FLD LPDDR4__DENALI_PI_200__PI_CALVL_VREF_DELTA_F0 + +#define LPDDR4__DENALI_PI_200__PI_CALVL_VREF_DELTA_F1_MASK 0x0F000000U +#define LPDDR4__DENALI_PI_200__PI_CALVL_VREF_DELTA_F1_SHIFT 24U +#define LPDDR4__DENALI_PI_200__PI_CALVL_VREF_DELTA_F1_WIDTH 4U +#define LPDDR4__PI_CALVL_VREF_DELTA_F1__REG DENALI_PI_200 +#define LPDDR4__PI_CALVL_VREF_DELTA_F1__FLD LPDDR4__DENALI_PI_200__PI_CALVL_VREF_DELTA_F1 + +#define LPDDR4__DENALI_PI_201_READ_MASK 0xFF1F0F0FU +#define LPDDR4__DENALI_PI_201_WRITE_MASK 0xFF1F0F0FU +#define LPDDR4__DENALI_PI_201__PI_CALVL_VREF_DELTA_F2_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_201__PI_CALVL_VREF_DELTA_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_201__PI_CALVL_VREF_DELTA_F2_WIDTH 4U +#define LPDDR4__PI_CALVL_VREF_DELTA_F2__REG DENALI_PI_201 +#define LPDDR4__PI_CALVL_VREF_DELTA_F2__FLD LPDDR4__DENALI_PI_201__PI_CALVL_VREF_DELTA_F2 + +#define LPDDR4__DENALI_PI_201__PI_TDFI_CALVL_STROBE_F0_MASK 0x00000F00U +#define LPDDR4__DENALI_PI_201__PI_TDFI_CALVL_STROBE_F0_SHIFT 8U +#define LPDDR4__DENALI_PI_201__PI_TDFI_CALVL_STROBE_F0_WIDTH 4U +#define LPDDR4__PI_TDFI_CALVL_STROBE_F0__REG DENALI_PI_201 +#define LPDDR4__PI_TDFI_CALVL_STROBE_F0__FLD LPDDR4__DENALI_PI_201__PI_TDFI_CALVL_STROBE_F0 + +#define LPDDR4__DENALI_PI_201__PI_TXP_F0_MASK 0x001F0000U +#define LPDDR4__DENALI_PI_201__PI_TXP_F0_SHIFT 16U +#define LPDDR4__DENALI_PI_201__PI_TXP_F0_WIDTH 5U +#define LPDDR4__PI_TXP_F0__REG DENALI_PI_201 +#define LPDDR4__PI_TXP_F0__FLD LPDDR4__DENALI_PI_201__PI_TXP_F0 + +#define LPDDR4__DENALI_PI_201__PI_TMRWCKEL_F0_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_201__PI_TMRWCKEL_F0_SHIFT 24U +#define LPDDR4__DENALI_PI_201__PI_TMRWCKEL_F0_WIDTH 8U +#define LPDDR4__PI_TMRWCKEL_F0__REG DENALI_PI_201 +#define LPDDR4__PI_TMRWCKEL_F0__FLD LPDDR4__DENALI_PI_201__PI_TMRWCKEL_F0 + +#define LPDDR4__DENALI_PI_202_READ_MASK 0xFF1F0F1FU +#define LPDDR4__DENALI_PI_202_WRITE_MASK 0xFF1F0F1FU +#define LPDDR4__DENALI_PI_202__PI_TCKELCK_F0_MASK 0x0000001FU +#define LPDDR4__DENALI_PI_202__PI_TCKELCK_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_202__PI_TCKELCK_F0_WIDTH 5U +#define LPDDR4__PI_TCKELCK_F0__REG DENALI_PI_202 +#define LPDDR4__PI_TCKELCK_F0__FLD LPDDR4__DENALI_PI_202__PI_TCKELCK_F0 + +#define LPDDR4__DENALI_PI_202__PI_TDFI_CALVL_STROBE_F1_MASK 0x00000F00U +#define LPDDR4__DENALI_PI_202__PI_TDFI_CALVL_STROBE_F1_SHIFT 8U +#define LPDDR4__DENALI_PI_202__PI_TDFI_CALVL_STROBE_F1_WIDTH 4U +#define LPDDR4__PI_TDFI_CALVL_STROBE_F1__REG DENALI_PI_202 +#define LPDDR4__PI_TDFI_CALVL_STROBE_F1__FLD LPDDR4__DENALI_PI_202__PI_TDFI_CALVL_STROBE_F1 + +#define LPDDR4__DENALI_PI_202__PI_TXP_F1_MASK 0x001F0000U +#define LPDDR4__DENALI_PI_202__PI_TXP_F1_SHIFT 16U +#define LPDDR4__DENALI_PI_202__PI_TXP_F1_WIDTH 5U +#define LPDDR4__PI_TXP_F1__REG DENALI_PI_202 +#define LPDDR4__PI_TXP_F1__FLD LPDDR4__DENALI_PI_202__PI_TXP_F1 + +#define LPDDR4__DENALI_PI_202__PI_TMRWCKEL_F1_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_202__PI_TMRWCKEL_F1_SHIFT 24U +#define LPDDR4__DENALI_PI_202__PI_TMRWCKEL_F1_WIDTH 8U +#define LPDDR4__PI_TMRWCKEL_F1__REG DENALI_PI_202 +#define LPDDR4__PI_TMRWCKEL_F1__FLD LPDDR4__DENALI_PI_202__PI_TMRWCKEL_F1 + +#define LPDDR4__DENALI_PI_203_READ_MASK 0xFF1F0F1FU +#define LPDDR4__DENALI_PI_203_WRITE_MASK 0xFF1F0F1FU +#define LPDDR4__DENALI_PI_203__PI_TCKELCK_F1_MASK 0x0000001FU +#define LPDDR4__DENALI_PI_203__PI_TCKELCK_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_203__PI_TCKELCK_F1_WIDTH 5U +#define LPDDR4__PI_TCKELCK_F1__REG DENALI_PI_203 +#define LPDDR4__PI_TCKELCK_F1__FLD LPDDR4__DENALI_PI_203__PI_TCKELCK_F1 + +#define LPDDR4__DENALI_PI_203__PI_TDFI_CALVL_STROBE_F2_MASK 0x00000F00U +#define LPDDR4__DENALI_PI_203__PI_TDFI_CALVL_STROBE_F2_SHIFT 8U +#define LPDDR4__DENALI_PI_203__PI_TDFI_CALVL_STROBE_F2_WIDTH 4U +#define LPDDR4__PI_TDFI_CALVL_STROBE_F2__REG DENALI_PI_203 +#define LPDDR4__PI_TDFI_CALVL_STROBE_F2__FLD LPDDR4__DENALI_PI_203__PI_TDFI_CALVL_STROBE_F2 + +#define LPDDR4__DENALI_PI_203__PI_TXP_F2_MASK 0x001F0000U +#define LPDDR4__DENALI_PI_203__PI_TXP_F2_SHIFT 16U +#define LPDDR4__DENALI_PI_203__PI_TXP_F2_WIDTH 5U +#define LPDDR4__PI_TXP_F2__REG DENALI_PI_203 +#define LPDDR4__PI_TXP_F2__FLD LPDDR4__DENALI_PI_203__PI_TXP_F2 + +#define LPDDR4__DENALI_PI_203__PI_TMRWCKEL_F2_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_203__PI_TMRWCKEL_F2_SHIFT 24U +#define LPDDR4__DENALI_PI_203__PI_TMRWCKEL_F2_WIDTH 8U +#define LPDDR4__PI_TMRWCKEL_F2__REG DENALI_PI_203 +#define LPDDR4__PI_TMRWCKEL_F2__FLD LPDDR4__DENALI_PI_203__PI_TMRWCKEL_F2 + +#define LPDDR4__DENALI_PI_204_READ_MASK 0x0003FF1FU +#define LPDDR4__DENALI_PI_204_WRITE_MASK 0x0003FF1FU +#define LPDDR4__DENALI_PI_204__PI_TCKELCK_F2_MASK 0x0000001FU +#define LPDDR4__DENALI_PI_204__PI_TCKELCK_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_204__PI_TCKELCK_F2_WIDTH 5U +#define LPDDR4__PI_TCKELCK_F2__REG DENALI_PI_204 +#define LPDDR4__PI_TCKELCK_F2__FLD LPDDR4__DENALI_PI_204__PI_TCKELCK_F2 + +#define LPDDR4__DENALI_PI_204__PI_TDFI_INIT_START_F0_MASK 0x0003FF00U +#define LPDDR4__DENALI_PI_204__PI_TDFI_INIT_START_F0_SHIFT 8U +#define LPDDR4__DENALI_PI_204__PI_TDFI_INIT_START_F0_WIDTH 10U +#define LPDDR4__PI_TDFI_INIT_START_F0__REG DENALI_PI_204 +#define LPDDR4__PI_TDFI_INIT_START_F0__FLD LPDDR4__DENALI_PI_204__PI_TDFI_INIT_START_F0 + +#define LPDDR4__DENALI_PI_205_READ_MASK 0x03FFFFFFU +#define LPDDR4__DENALI_PI_205_WRITE_MASK 0x03FFFFFFU +#define LPDDR4__DENALI_PI_205__PI_TDFI_INIT_COMPLETE_F0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PI_205__PI_TDFI_INIT_COMPLETE_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_205__PI_TDFI_INIT_COMPLETE_F0_WIDTH 16U +#define LPDDR4__PI_TDFI_INIT_COMPLETE_F0__REG DENALI_PI_205 +#define LPDDR4__PI_TDFI_INIT_COMPLETE_F0__FLD LPDDR4__DENALI_PI_205__PI_TDFI_INIT_COMPLETE_F0 + +#define LPDDR4__DENALI_PI_205__PI_TDFI_INIT_START_F1_MASK 0x03FF0000U +#define LPDDR4__DENALI_PI_205__PI_TDFI_INIT_START_F1_SHIFT 16U +#define LPDDR4__DENALI_PI_205__PI_TDFI_INIT_START_F1_WIDTH 10U +#define LPDDR4__PI_TDFI_INIT_START_F1__REG DENALI_PI_205 +#define LPDDR4__PI_TDFI_INIT_START_F1__FLD LPDDR4__DENALI_PI_205__PI_TDFI_INIT_START_F1 + +#define LPDDR4__DENALI_PI_206_READ_MASK 0x03FFFFFFU +#define LPDDR4__DENALI_PI_206_WRITE_MASK 0x03FFFFFFU +#define LPDDR4__DENALI_PI_206__PI_TDFI_INIT_COMPLETE_F1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PI_206__PI_TDFI_INIT_COMPLETE_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_206__PI_TDFI_INIT_COMPLETE_F1_WIDTH 16U +#define LPDDR4__PI_TDFI_INIT_COMPLETE_F1__REG DENALI_PI_206 +#define LPDDR4__PI_TDFI_INIT_COMPLETE_F1__FLD LPDDR4__DENALI_PI_206__PI_TDFI_INIT_COMPLETE_F1 + +#define LPDDR4__DENALI_PI_206__PI_TDFI_INIT_START_F2_MASK 0x03FF0000U +#define LPDDR4__DENALI_PI_206__PI_TDFI_INIT_START_F2_SHIFT 16U +#define LPDDR4__DENALI_PI_206__PI_TDFI_INIT_START_F2_WIDTH 10U +#define LPDDR4__PI_TDFI_INIT_START_F2__REG DENALI_PI_206 +#define LPDDR4__PI_TDFI_INIT_START_F2__FLD LPDDR4__DENALI_PI_206__PI_TDFI_INIT_START_F2 + +#define LPDDR4__DENALI_PI_207_READ_MASK 0x003FFFFFU +#define LPDDR4__DENALI_PI_207_WRITE_MASK 0x003FFFFFU +#define LPDDR4__DENALI_PI_207__PI_TDFI_INIT_COMPLETE_F2_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PI_207__PI_TDFI_INIT_COMPLETE_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_207__PI_TDFI_INIT_COMPLETE_F2_WIDTH 16U +#define LPDDR4__PI_TDFI_INIT_COMPLETE_F2__REG DENALI_PI_207 +#define LPDDR4__PI_TDFI_INIT_COMPLETE_F2__FLD LPDDR4__DENALI_PI_207__PI_TDFI_INIT_COMPLETE_F2 + +#define LPDDR4__DENALI_PI_207__PI_TCKEHDQS_F0_MASK 0x003F0000U +#define LPDDR4__DENALI_PI_207__PI_TCKEHDQS_F0_SHIFT 16U +#define LPDDR4__DENALI_PI_207__PI_TCKEHDQS_F0_WIDTH 6U +#define LPDDR4__PI_TCKEHDQS_F0__REG DENALI_PI_207 +#define LPDDR4__PI_TCKEHDQS_F0__FLD LPDDR4__DENALI_PI_207__PI_TCKEHDQS_F0 + +#define LPDDR4__DENALI_PI_208_READ_MASK 0x003F03FFU +#define LPDDR4__DENALI_PI_208_WRITE_MASK 0x003F03FFU +#define LPDDR4__DENALI_PI_208__PI_TFC_F0_MASK 0x000003FFU +#define LPDDR4__DENALI_PI_208__PI_TFC_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_208__PI_TFC_F0_WIDTH 10U +#define LPDDR4__PI_TFC_F0__REG DENALI_PI_208 +#define LPDDR4__PI_TFC_F0__FLD LPDDR4__DENALI_PI_208__PI_TFC_F0 + +#define LPDDR4__DENALI_PI_208__PI_TCKEHDQS_F1_MASK 0x003F0000U +#define LPDDR4__DENALI_PI_208__PI_TCKEHDQS_F1_SHIFT 16U +#define LPDDR4__DENALI_PI_208__PI_TCKEHDQS_F1_WIDTH 6U +#define LPDDR4__PI_TCKEHDQS_F1__REG DENALI_PI_208 +#define LPDDR4__PI_TCKEHDQS_F1__FLD LPDDR4__DENALI_PI_208__PI_TCKEHDQS_F1 + +#define LPDDR4__DENALI_PI_209_READ_MASK 0x003F03FFU +#define LPDDR4__DENALI_PI_209_WRITE_MASK 0x003F03FFU +#define LPDDR4__DENALI_PI_209__PI_TFC_F1_MASK 0x000003FFU +#define LPDDR4__DENALI_PI_209__PI_TFC_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_209__PI_TFC_F1_WIDTH 10U +#define LPDDR4__PI_TFC_F1__REG DENALI_PI_209 +#define LPDDR4__PI_TFC_F1__FLD LPDDR4__DENALI_PI_209__PI_TFC_F1 + +#define LPDDR4__DENALI_PI_209__PI_TCKEHDQS_F2_MASK 0x003F0000U +#define LPDDR4__DENALI_PI_209__PI_TCKEHDQS_F2_SHIFT 16U +#define LPDDR4__DENALI_PI_209__PI_TCKEHDQS_F2_WIDTH 6U +#define LPDDR4__PI_TCKEHDQS_F2__REG DENALI_PI_209 +#define LPDDR4__PI_TCKEHDQS_F2__FLD LPDDR4__DENALI_PI_209__PI_TCKEHDQS_F2 + +#define LPDDR4__DENALI_PI_210_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PI_210_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PI_210__PI_TFC_F2_MASK 0x000003FFU +#define LPDDR4__DENALI_PI_210__PI_TFC_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_210__PI_TFC_F2_WIDTH 10U +#define LPDDR4__PI_TFC_F2__REG DENALI_PI_210 +#define LPDDR4__PI_TFC_F2__FLD LPDDR4__DENALI_PI_210__PI_TFC_F2 + +#define LPDDR4__DENALI_PI_210__PI_TDFI_WDQLVL_WR_F0_MASK 0x03FF0000U +#define LPDDR4__DENALI_PI_210__PI_TDFI_WDQLVL_WR_F0_SHIFT 16U +#define LPDDR4__DENALI_PI_210__PI_TDFI_WDQLVL_WR_F0_WIDTH 10U +#define LPDDR4__PI_TDFI_WDQLVL_WR_F0__REG DENALI_PI_210 +#define LPDDR4__PI_TDFI_WDQLVL_WR_F0__FLD LPDDR4__DENALI_PI_210__PI_TDFI_WDQLVL_WR_F0 + +#define LPDDR4__DENALI_PI_211_READ_MASK 0x7F7F03FFU +#define LPDDR4__DENALI_PI_211_WRITE_MASK 0x7F7F03FFU +#define LPDDR4__DENALI_PI_211__PI_TDFI_WDQLVL_RW_F0_MASK 0x000003FFU +#define LPDDR4__DENALI_PI_211__PI_TDFI_WDQLVL_RW_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_211__PI_TDFI_WDQLVL_RW_F0_WIDTH 10U +#define LPDDR4__PI_TDFI_WDQLVL_RW_F0__REG DENALI_PI_211 +#define LPDDR4__PI_TDFI_WDQLVL_RW_F0__FLD LPDDR4__DENALI_PI_211__PI_TDFI_WDQLVL_RW_F0 + +#define LPDDR4__DENALI_PI_211__PI_WDQLVL_VREF_INITIAL_START_POINT_F0_MASK 0x007F0000U +#define LPDDR4__DENALI_PI_211__PI_WDQLVL_VREF_INITIAL_START_POINT_F0_SHIFT 16U +#define LPDDR4__DENALI_PI_211__PI_WDQLVL_VREF_INITIAL_START_POINT_F0_WIDTH 7U +#define LPDDR4__PI_WDQLVL_VREF_INITIAL_START_POINT_F0__REG DENALI_PI_211 +#define LPDDR4__PI_WDQLVL_VREF_INITIAL_START_POINT_F0__FLD LPDDR4__DENALI_PI_211__PI_WDQLVL_VREF_INITIAL_START_POINT_F0 + +#define LPDDR4__DENALI_PI_211__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0_MASK 0x7F000000U +#define LPDDR4__DENALI_PI_211__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0_SHIFT 24U +#define LPDDR4__DENALI_PI_211__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0_WIDTH 7U +#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0__REG DENALI_PI_211 +#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0__FLD LPDDR4__DENALI_PI_211__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0 + +#define LPDDR4__DENALI_PI_212_READ_MASK 0x0003030FU +#define LPDDR4__DENALI_PI_212_WRITE_MASK 0x0003030FU +#define LPDDR4__DENALI_PI_212__PI_WDQLVL_VREF_DELTA_F0_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_212__PI_WDQLVL_VREF_DELTA_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_212__PI_WDQLVL_VREF_DELTA_F0_WIDTH 4U +#define LPDDR4__PI_WDQLVL_VREF_DELTA_F0__REG DENALI_PI_212 +#define LPDDR4__PI_WDQLVL_VREF_DELTA_F0__FLD LPDDR4__DENALI_PI_212__PI_WDQLVL_VREF_DELTA_F0 + +#define LPDDR4__DENALI_PI_212__PI_WDQLVL_EN_F0_MASK 0x00000300U +#define LPDDR4__DENALI_PI_212__PI_WDQLVL_EN_F0_SHIFT 8U +#define LPDDR4__DENALI_PI_212__PI_WDQLVL_EN_F0_WIDTH 2U +#define LPDDR4__PI_WDQLVL_EN_F0__REG DENALI_PI_212 +#define LPDDR4__PI_WDQLVL_EN_F0__FLD LPDDR4__DENALI_PI_212__PI_WDQLVL_EN_F0 + +#define LPDDR4__DENALI_PI_212__PI_NTP_TRAIN_EN_F0_MASK 0x00030000U +#define LPDDR4__DENALI_PI_212__PI_NTP_TRAIN_EN_F0_SHIFT 16U +#define LPDDR4__DENALI_PI_212__PI_NTP_TRAIN_EN_F0_WIDTH 2U +#define LPDDR4__PI_NTP_TRAIN_EN_F0__REG DENALI_PI_212 +#define LPDDR4__PI_NTP_TRAIN_EN_F0__FLD LPDDR4__DENALI_PI_212__PI_NTP_TRAIN_EN_F0 + +#define LPDDR4__DENALI_PI_213_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PI_213_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PI_213__PI_TDFI_WDQLVL_WR_F1_MASK 0x000003FFU +#define LPDDR4__DENALI_PI_213__PI_TDFI_WDQLVL_WR_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_213__PI_TDFI_WDQLVL_WR_F1_WIDTH 10U +#define LPDDR4__PI_TDFI_WDQLVL_WR_F1__REG DENALI_PI_213 +#define LPDDR4__PI_TDFI_WDQLVL_WR_F1__FLD LPDDR4__DENALI_PI_213__PI_TDFI_WDQLVL_WR_F1 + +#define LPDDR4__DENALI_PI_213__PI_TDFI_WDQLVL_RW_F1_MASK 0x03FF0000U +#define LPDDR4__DENALI_PI_213__PI_TDFI_WDQLVL_RW_F1_SHIFT 16U +#define LPDDR4__DENALI_PI_213__PI_TDFI_WDQLVL_RW_F1_WIDTH 10U +#define LPDDR4__PI_TDFI_WDQLVL_RW_F1__REG DENALI_PI_213 +#define LPDDR4__PI_TDFI_WDQLVL_RW_F1__FLD LPDDR4__DENALI_PI_213__PI_TDFI_WDQLVL_RW_F1 + +#define LPDDR4__DENALI_PI_214_READ_MASK 0x030F7F7FU +#define LPDDR4__DENALI_PI_214_WRITE_MASK 0x030F7F7FU +#define LPDDR4__DENALI_PI_214__PI_WDQLVL_VREF_INITIAL_START_POINT_F1_MASK 0x0000007FU +#define LPDDR4__DENALI_PI_214__PI_WDQLVL_VREF_INITIAL_START_POINT_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_214__PI_WDQLVL_VREF_INITIAL_START_POINT_F1_WIDTH 7U +#define LPDDR4__PI_WDQLVL_VREF_INITIAL_START_POINT_F1__REG DENALI_PI_214 +#define LPDDR4__PI_WDQLVL_VREF_INITIAL_START_POINT_F1__FLD LPDDR4__DENALI_PI_214__PI_WDQLVL_VREF_INITIAL_START_POINT_F1 + +#define LPDDR4__DENALI_PI_214__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1_MASK 0x00007F00U +#define LPDDR4__DENALI_PI_214__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1_SHIFT 8U +#define LPDDR4__DENALI_PI_214__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1_WIDTH 7U +#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1__REG DENALI_PI_214 +#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1__FLD LPDDR4__DENALI_PI_214__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1 + +#define LPDDR4__DENALI_PI_214__PI_WDQLVL_VREF_DELTA_F1_MASK 0x000F0000U +#define LPDDR4__DENALI_PI_214__PI_WDQLVL_VREF_DELTA_F1_SHIFT 16U +#define LPDDR4__DENALI_PI_214__PI_WDQLVL_VREF_DELTA_F1_WIDTH 4U +#define LPDDR4__PI_WDQLVL_VREF_DELTA_F1__REG DENALI_PI_214 +#define LPDDR4__PI_WDQLVL_VREF_DELTA_F1__FLD LPDDR4__DENALI_PI_214__PI_WDQLVL_VREF_DELTA_F1 + +#define LPDDR4__DENALI_PI_214__PI_WDQLVL_EN_F1_MASK 0x03000000U +#define LPDDR4__DENALI_PI_214__PI_WDQLVL_EN_F1_SHIFT 24U +#define LPDDR4__DENALI_PI_214__PI_WDQLVL_EN_F1_WIDTH 2U +#define LPDDR4__PI_WDQLVL_EN_F1__REG DENALI_PI_214 +#define LPDDR4__PI_WDQLVL_EN_F1__FLD LPDDR4__DENALI_PI_214__PI_WDQLVL_EN_F1 + +#define LPDDR4__DENALI_PI_215_READ_MASK 0x0003FF03U +#define LPDDR4__DENALI_PI_215_WRITE_MASK 0x0003FF03U +#define LPDDR4__DENALI_PI_215__PI_NTP_TRAIN_EN_F1_MASK 0x00000003U +#define LPDDR4__DENALI_PI_215__PI_NTP_TRAIN_EN_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_215__PI_NTP_TRAIN_EN_F1_WIDTH 2U +#define LPDDR4__PI_NTP_TRAIN_EN_F1__REG DENALI_PI_215 +#define LPDDR4__PI_NTP_TRAIN_EN_F1__FLD LPDDR4__DENALI_PI_215__PI_NTP_TRAIN_EN_F1 + +#define LPDDR4__DENALI_PI_215__PI_TDFI_WDQLVL_WR_F2_MASK 0x0003FF00U +#define LPDDR4__DENALI_PI_215__PI_TDFI_WDQLVL_WR_F2_SHIFT 8U +#define LPDDR4__DENALI_PI_215__PI_TDFI_WDQLVL_WR_F2_WIDTH 10U +#define LPDDR4__PI_TDFI_WDQLVL_WR_F2__REG DENALI_PI_215 +#define LPDDR4__PI_TDFI_WDQLVL_WR_F2__FLD LPDDR4__DENALI_PI_215__PI_TDFI_WDQLVL_WR_F2 + +#define LPDDR4__DENALI_PI_216_READ_MASK 0x7F7F03FFU +#define LPDDR4__DENALI_PI_216_WRITE_MASK 0x7F7F03FFU +#define LPDDR4__DENALI_PI_216__PI_TDFI_WDQLVL_RW_F2_MASK 0x000003FFU +#define LPDDR4__DENALI_PI_216__PI_TDFI_WDQLVL_RW_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_216__PI_TDFI_WDQLVL_RW_F2_WIDTH 10U +#define LPDDR4__PI_TDFI_WDQLVL_RW_F2__REG DENALI_PI_216 +#define LPDDR4__PI_TDFI_WDQLVL_RW_F2__FLD LPDDR4__DENALI_PI_216__PI_TDFI_WDQLVL_RW_F2 + +#define LPDDR4__DENALI_PI_216__PI_WDQLVL_VREF_INITIAL_START_POINT_F2_MASK 0x007F0000U +#define LPDDR4__DENALI_PI_216__PI_WDQLVL_VREF_INITIAL_START_POINT_F2_SHIFT 16U +#define LPDDR4__DENALI_PI_216__PI_WDQLVL_VREF_INITIAL_START_POINT_F2_WIDTH 7U +#define LPDDR4__PI_WDQLVL_VREF_INITIAL_START_POINT_F2__REG DENALI_PI_216 +#define LPDDR4__PI_WDQLVL_VREF_INITIAL_START_POINT_F2__FLD LPDDR4__DENALI_PI_216__PI_WDQLVL_VREF_INITIAL_START_POINT_F2 + +#define LPDDR4__DENALI_PI_216__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2_MASK 0x7F000000U +#define LPDDR4__DENALI_PI_216__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2_SHIFT 24U +#define LPDDR4__DENALI_PI_216__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2_WIDTH 7U +#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2__REG DENALI_PI_216 +#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2__FLD LPDDR4__DENALI_PI_216__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2 + +#define LPDDR4__DENALI_PI_217_READ_MASK 0xFF03030FU +#define LPDDR4__DENALI_PI_217_WRITE_MASK 0xFF03030FU +#define LPDDR4__DENALI_PI_217__PI_WDQLVL_VREF_DELTA_F2_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_217__PI_WDQLVL_VREF_DELTA_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_217__PI_WDQLVL_VREF_DELTA_F2_WIDTH 4U +#define LPDDR4__PI_WDQLVL_VREF_DELTA_F2__REG DENALI_PI_217 +#define LPDDR4__PI_WDQLVL_VREF_DELTA_F2__FLD LPDDR4__DENALI_PI_217__PI_WDQLVL_VREF_DELTA_F2 + +#define LPDDR4__DENALI_PI_217__PI_WDQLVL_EN_F2_MASK 0x00000300U +#define LPDDR4__DENALI_PI_217__PI_WDQLVL_EN_F2_SHIFT 8U +#define LPDDR4__DENALI_PI_217__PI_WDQLVL_EN_F2_WIDTH 2U +#define LPDDR4__PI_WDQLVL_EN_F2__REG DENALI_PI_217 +#define LPDDR4__PI_WDQLVL_EN_F2__FLD LPDDR4__DENALI_PI_217__PI_WDQLVL_EN_F2 + +#define LPDDR4__DENALI_PI_217__PI_NTP_TRAIN_EN_F2_MASK 0x00030000U +#define LPDDR4__DENALI_PI_217__PI_NTP_TRAIN_EN_F2_SHIFT 16U +#define LPDDR4__DENALI_PI_217__PI_NTP_TRAIN_EN_F2_WIDTH 2U +#define LPDDR4__PI_NTP_TRAIN_EN_F2__REG DENALI_PI_217 +#define LPDDR4__PI_NTP_TRAIN_EN_F2__FLD LPDDR4__DENALI_PI_217__PI_NTP_TRAIN_EN_F2 + +#define LPDDR4__DENALI_PI_217__PI_TRTP_F0_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_217__PI_TRTP_F0_SHIFT 24U +#define LPDDR4__DENALI_PI_217__PI_TRTP_F0_WIDTH 8U +#define LPDDR4__PI_TRTP_F0__REG DENALI_PI_217 +#define LPDDR4__PI_TRTP_F0__FLD LPDDR4__DENALI_PI_217__PI_TRTP_F0 + +#define LPDDR4__DENALI_PI_218_READ_MASK 0xFF3FFFFFU +#define LPDDR4__DENALI_PI_218_WRITE_MASK 0xFF3FFFFFU +#define LPDDR4__DENALI_PI_218__PI_TRP_F0_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_218__PI_TRP_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_218__PI_TRP_F0_WIDTH 8U +#define LPDDR4__PI_TRP_F0__REG DENALI_PI_218 +#define LPDDR4__PI_TRP_F0__FLD LPDDR4__DENALI_PI_218__PI_TRP_F0 + +#define LPDDR4__DENALI_PI_218__PI_TRCD_F0_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_218__PI_TRCD_F0_SHIFT 8U +#define LPDDR4__DENALI_PI_218__PI_TRCD_F0_WIDTH 8U +#define LPDDR4__PI_TRCD_F0__REG DENALI_PI_218 +#define LPDDR4__PI_TRCD_F0__FLD LPDDR4__DENALI_PI_218__PI_TRCD_F0 + +#define LPDDR4__DENALI_PI_218__PI_TWTR_F0_MASK 0x003F0000U +#define LPDDR4__DENALI_PI_218__PI_TWTR_F0_SHIFT 16U +#define LPDDR4__DENALI_PI_218__PI_TWTR_F0_WIDTH 6U +#define LPDDR4__PI_TWTR_F0__REG DENALI_PI_218 +#define LPDDR4__PI_TWTR_F0__FLD LPDDR4__DENALI_PI_218__PI_TWTR_F0 + +#define LPDDR4__DENALI_PI_218__PI_TWR_F0_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_218__PI_TWR_F0_SHIFT 24U +#define LPDDR4__DENALI_PI_218__PI_TWR_F0_WIDTH 8U +#define LPDDR4__PI_TWR_F0__REG DENALI_PI_218 +#define LPDDR4__PI_TWR_F0__FLD LPDDR4__DENALI_PI_218__PI_TWR_F0 + +#define LPDDR4__DENALI_PI_219_READ_MASK 0xFF01FFFFU +#define LPDDR4__DENALI_PI_219_WRITE_MASK 0xFF01FFFFU +#define LPDDR4__DENALI_PI_219__PI_TRAS_MAX_F0_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_219__PI_TRAS_MAX_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_219__PI_TRAS_MAX_F0_WIDTH 17U +#define LPDDR4__PI_TRAS_MAX_F0__REG DENALI_PI_219 +#define LPDDR4__PI_TRAS_MAX_F0__FLD LPDDR4__DENALI_PI_219__PI_TRAS_MAX_F0 + +#define LPDDR4__DENALI_PI_219__PI_TRAS_MIN_F0_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_219__PI_TRAS_MIN_F0_SHIFT 24U +#define LPDDR4__DENALI_PI_219__PI_TRAS_MIN_F0_WIDTH 8U +#define LPDDR4__PI_TRAS_MIN_F0__REG DENALI_PI_219 +#define LPDDR4__PI_TRAS_MIN_F0__FLD LPDDR4__DENALI_PI_219__PI_TRAS_MIN_F0 + +#define LPDDR4__DENALI_PI_220_READ_MASK 0xFFFF3F0FU +#define LPDDR4__DENALI_PI_220_WRITE_MASK 0xFFFF3F0FU +#define LPDDR4__DENALI_PI_220__PI_TDQSCK_MAX_F0_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_220__PI_TDQSCK_MAX_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_220__PI_TDQSCK_MAX_F0_WIDTH 4U +#define LPDDR4__PI_TDQSCK_MAX_F0__REG DENALI_PI_220 +#define LPDDR4__PI_TDQSCK_MAX_F0__FLD LPDDR4__DENALI_PI_220__PI_TDQSCK_MAX_F0 + +#define LPDDR4__DENALI_PI_220__PI_TCCDMW_F0_MASK 0x00003F00U +#define LPDDR4__DENALI_PI_220__PI_TCCDMW_F0_SHIFT 8U +#define LPDDR4__DENALI_PI_220__PI_TCCDMW_F0_WIDTH 6U +#define LPDDR4__PI_TCCDMW_F0__REG DENALI_PI_220 +#define LPDDR4__PI_TCCDMW_F0__FLD LPDDR4__DENALI_PI_220__PI_TCCDMW_F0 + +#define LPDDR4__DENALI_PI_220__PI_TSR_F0_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_220__PI_TSR_F0_SHIFT 16U +#define LPDDR4__DENALI_PI_220__PI_TSR_F0_WIDTH 8U +#define LPDDR4__PI_TSR_F0__REG DENALI_PI_220 +#define LPDDR4__PI_TSR_F0__FLD LPDDR4__DENALI_PI_220__PI_TSR_F0 + +#define LPDDR4__DENALI_PI_220__PI_TMRD_F0_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_220__PI_TMRD_F0_SHIFT 24U +#define LPDDR4__DENALI_PI_220__PI_TMRD_F0_WIDTH 8U +#define LPDDR4__PI_TMRD_F0__REG DENALI_PI_220 +#define LPDDR4__PI_TMRD_F0__FLD LPDDR4__DENALI_PI_220__PI_TMRD_F0 + +#define LPDDR4__DENALI_PI_221_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_221_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_221__PI_TMRW_F0_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_221__PI_TMRW_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_221__PI_TMRW_F0_WIDTH 8U +#define LPDDR4__PI_TMRW_F0__REG DENALI_PI_221 +#define LPDDR4__PI_TMRW_F0__FLD LPDDR4__DENALI_PI_221__PI_TMRW_F0 + +#define LPDDR4__DENALI_PI_221__PI_TRTP_F1_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_221__PI_TRTP_F1_SHIFT 8U +#define LPDDR4__DENALI_PI_221__PI_TRTP_F1_WIDTH 8U +#define LPDDR4__PI_TRTP_F1__REG DENALI_PI_221 +#define LPDDR4__PI_TRTP_F1__FLD LPDDR4__DENALI_PI_221__PI_TRTP_F1 + +#define LPDDR4__DENALI_PI_221__PI_TRP_F1_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_221__PI_TRP_F1_SHIFT 16U +#define LPDDR4__DENALI_PI_221__PI_TRP_F1_WIDTH 8U +#define LPDDR4__PI_TRP_F1__REG DENALI_PI_221 +#define LPDDR4__PI_TRP_F1__FLD LPDDR4__DENALI_PI_221__PI_TRP_F1 + +#define LPDDR4__DENALI_PI_221__PI_TRCD_F1_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_221__PI_TRCD_F1_SHIFT 24U +#define LPDDR4__DENALI_PI_221__PI_TRCD_F1_WIDTH 8U +#define LPDDR4__PI_TRCD_F1__REG DENALI_PI_221 +#define LPDDR4__PI_TRCD_F1__FLD LPDDR4__DENALI_PI_221__PI_TRCD_F1 + +#define LPDDR4__DENALI_PI_222_READ_MASK 0x0000FF3FU +#define LPDDR4__DENALI_PI_222_WRITE_MASK 0x0000FF3FU +#define LPDDR4__DENALI_PI_222__PI_TWTR_F1_MASK 0x0000003FU +#define LPDDR4__DENALI_PI_222__PI_TWTR_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_222__PI_TWTR_F1_WIDTH 6U +#define LPDDR4__PI_TWTR_F1__REG DENALI_PI_222 +#define LPDDR4__PI_TWTR_F1__FLD LPDDR4__DENALI_PI_222__PI_TWTR_F1 + +#define LPDDR4__DENALI_PI_222__PI_TWR_F1_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_222__PI_TWR_F1_SHIFT 8U +#define LPDDR4__DENALI_PI_222__PI_TWR_F1_WIDTH 8U +#define LPDDR4__PI_TWR_F1__REG DENALI_PI_222 +#define LPDDR4__PI_TWR_F1__FLD LPDDR4__DENALI_PI_222__PI_TWR_F1 + +#define LPDDR4__DENALI_PI_223_READ_MASK 0xFF01FFFFU +#define LPDDR4__DENALI_PI_223_WRITE_MASK 0xFF01FFFFU +#define LPDDR4__DENALI_PI_223__PI_TRAS_MAX_F1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_223__PI_TRAS_MAX_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_223__PI_TRAS_MAX_F1_WIDTH 17U +#define LPDDR4__PI_TRAS_MAX_F1__REG DENALI_PI_223 +#define LPDDR4__PI_TRAS_MAX_F1__FLD LPDDR4__DENALI_PI_223__PI_TRAS_MAX_F1 + +#define LPDDR4__DENALI_PI_223__PI_TRAS_MIN_F1_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_223__PI_TRAS_MIN_F1_SHIFT 24U +#define LPDDR4__DENALI_PI_223__PI_TRAS_MIN_F1_WIDTH 8U +#define LPDDR4__PI_TRAS_MIN_F1__REG DENALI_PI_223 +#define LPDDR4__PI_TRAS_MIN_F1__FLD LPDDR4__DENALI_PI_223__PI_TRAS_MIN_F1 + +#define LPDDR4__DENALI_PI_224_READ_MASK 0xFFFF3F0FU +#define LPDDR4__DENALI_PI_224_WRITE_MASK 0xFFFF3F0FU +#define LPDDR4__DENALI_PI_224__PI_TDQSCK_MAX_F1_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_224__PI_TDQSCK_MAX_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_224__PI_TDQSCK_MAX_F1_WIDTH 4U +#define LPDDR4__PI_TDQSCK_MAX_F1__REG DENALI_PI_224 +#define LPDDR4__PI_TDQSCK_MAX_F1__FLD LPDDR4__DENALI_PI_224__PI_TDQSCK_MAX_F1 + +#define LPDDR4__DENALI_PI_224__PI_TCCDMW_F1_MASK 0x00003F00U +#define LPDDR4__DENALI_PI_224__PI_TCCDMW_F1_SHIFT 8U +#define LPDDR4__DENALI_PI_224__PI_TCCDMW_F1_WIDTH 6U +#define LPDDR4__PI_TCCDMW_F1__REG DENALI_PI_224 +#define LPDDR4__PI_TCCDMW_F1__FLD LPDDR4__DENALI_PI_224__PI_TCCDMW_F1 + +#define LPDDR4__DENALI_PI_224__PI_TSR_F1_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_224__PI_TSR_F1_SHIFT 16U +#define LPDDR4__DENALI_PI_224__PI_TSR_F1_WIDTH 8U +#define LPDDR4__PI_TSR_F1__REG DENALI_PI_224 +#define LPDDR4__PI_TSR_F1__FLD LPDDR4__DENALI_PI_224__PI_TSR_F1 + +#define LPDDR4__DENALI_PI_224__PI_TMRD_F1_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_224__PI_TMRD_F1_SHIFT 24U +#define LPDDR4__DENALI_PI_224__PI_TMRD_F1_WIDTH 8U +#define LPDDR4__PI_TMRD_F1__REG DENALI_PI_224 +#define LPDDR4__PI_TMRD_F1__FLD LPDDR4__DENALI_PI_224__PI_TMRD_F1 + +#define LPDDR4__DENALI_PI_225_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_225_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_225__PI_TMRW_F1_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_225__PI_TMRW_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_225__PI_TMRW_F1_WIDTH 8U +#define LPDDR4__PI_TMRW_F1__REG DENALI_PI_225 +#define LPDDR4__PI_TMRW_F1__FLD LPDDR4__DENALI_PI_225__PI_TMRW_F1 + +#define LPDDR4__DENALI_PI_225__PI_TRTP_F2_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_225__PI_TRTP_F2_SHIFT 8U +#define LPDDR4__DENALI_PI_225__PI_TRTP_F2_WIDTH 8U +#define LPDDR4__PI_TRTP_F2__REG DENALI_PI_225 +#define LPDDR4__PI_TRTP_F2__FLD LPDDR4__DENALI_PI_225__PI_TRTP_F2 + +#define LPDDR4__DENALI_PI_225__PI_TRP_F2_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_225__PI_TRP_F2_SHIFT 16U +#define LPDDR4__DENALI_PI_225__PI_TRP_F2_WIDTH 8U +#define LPDDR4__PI_TRP_F2__REG DENALI_PI_225 +#define LPDDR4__PI_TRP_F2__FLD LPDDR4__DENALI_PI_225__PI_TRP_F2 + +#define LPDDR4__DENALI_PI_225__PI_TRCD_F2_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_225__PI_TRCD_F2_SHIFT 24U +#define LPDDR4__DENALI_PI_225__PI_TRCD_F2_WIDTH 8U +#define LPDDR4__PI_TRCD_F2__REG DENALI_PI_225 +#define LPDDR4__PI_TRCD_F2__FLD LPDDR4__DENALI_PI_225__PI_TRCD_F2 + +#define LPDDR4__DENALI_PI_226_READ_MASK 0x0000FF3FU +#define LPDDR4__DENALI_PI_226_WRITE_MASK 0x0000FF3FU +#define LPDDR4__DENALI_PI_226__PI_TWTR_F2_MASK 0x0000003FU +#define LPDDR4__DENALI_PI_226__PI_TWTR_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_226__PI_TWTR_F2_WIDTH 6U +#define LPDDR4__PI_TWTR_F2__REG DENALI_PI_226 +#define LPDDR4__PI_TWTR_F2__FLD LPDDR4__DENALI_PI_226__PI_TWTR_F2 + +#define LPDDR4__DENALI_PI_226__PI_TWR_F2_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_226__PI_TWR_F2_SHIFT 8U +#define LPDDR4__DENALI_PI_226__PI_TWR_F2_WIDTH 8U +#define LPDDR4__PI_TWR_F2__REG DENALI_PI_226 +#define LPDDR4__PI_TWR_F2__FLD LPDDR4__DENALI_PI_226__PI_TWR_F2 + +#define LPDDR4__DENALI_PI_227_READ_MASK 0xFF01FFFFU +#define LPDDR4__DENALI_PI_227_WRITE_MASK 0xFF01FFFFU +#define LPDDR4__DENALI_PI_227__PI_TRAS_MAX_F2_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_227__PI_TRAS_MAX_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_227__PI_TRAS_MAX_F2_WIDTH 17U +#define LPDDR4__PI_TRAS_MAX_F2__REG DENALI_PI_227 +#define LPDDR4__PI_TRAS_MAX_F2__FLD LPDDR4__DENALI_PI_227__PI_TRAS_MAX_F2 + +#define LPDDR4__DENALI_PI_227__PI_TRAS_MIN_F2_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_227__PI_TRAS_MIN_F2_SHIFT 24U +#define LPDDR4__DENALI_PI_227__PI_TRAS_MIN_F2_WIDTH 8U +#define LPDDR4__PI_TRAS_MIN_F2__REG DENALI_PI_227 +#define LPDDR4__PI_TRAS_MIN_F2__FLD LPDDR4__DENALI_PI_227__PI_TRAS_MIN_F2 + +#define LPDDR4__DENALI_PI_228_READ_MASK 0xFFFF3F0FU +#define LPDDR4__DENALI_PI_228_WRITE_MASK 0xFFFF3F0FU +#define LPDDR4__DENALI_PI_228__PI_TDQSCK_MAX_F2_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_228__PI_TDQSCK_MAX_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_228__PI_TDQSCK_MAX_F2_WIDTH 4U +#define LPDDR4__PI_TDQSCK_MAX_F2__REG DENALI_PI_228 +#define LPDDR4__PI_TDQSCK_MAX_F2__FLD LPDDR4__DENALI_PI_228__PI_TDQSCK_MAX_F2 + +#define LPDDR4__DENALI_PI_228__PI_TCCDMW_F2_MASK 0x00003F00U +#define LPDDR4__DENALI_PI_228__PI_TCCDMW_F2_SHIFT 8U +#define LPDDR4__DENALI_PI_228__PI_TCCDMW_F2_WIDTH 6U +#define LPDDR4__PI_TCCDMW_F2__REG DENALI_PI_228 +#define LPDDR4__PI_TCCDMW_F2__FLD LPDDR4__DENALI_PI_228__PI_TCCDMW_F2 + +#define LPDDR4__DENALI_PI_228__PI_TSR_F2_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_228__PI_TSR_F2_SHIFT 16U +#define LPDDR4__DENALI_PI_228__PI_TSR_F2_WIDTH 8U +#define LPDDR4__PI_TSR_F2__REG DENALI_PI_228 +#define LPDDR4__PI_TSR_F2__FLD LPDDR4__DENALI_PI_228__PI_TSR_F2 + +#define LPDDR4__DENALI_PI_228__PI_TMRD_F2_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_228__PI_TMRD_F2_SHIFT 24U +#define LPDDR4__DENALI_PI_228__PI_TMRD_F2_WIDTH 8U +#define LPDDR4__PI_TMRD_F2__REG DENALI_PI_228 +#define LPDDR4__PI_TMRD_F2__FLD LPDDR4__DENALI_PI_228__PI_TMRD_F2 + +#define LPDDR4__DENALI_PI_229_READ_MASK 0x1FFFFFFFU +#define LPDDR4__DENALI_PI_229_WRITE_MASK 0x1FFFFFFFU +#define LPDDR4__DENALI_PI_229__PI_TMRW_F2_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_229__PI_TMRW_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_229__PI_TMRW_F2_WIDTH 8U +#define LPDDR4__PI_TMRW_F2__REG DENALI_PI_229 +#define LPDDR4__PI_TMRW_F2__FLD LPDDR4__DENALI_PI_229__PI_TMRW_F2 + +#define LPDDR4__DENALI_PI_229__PI_TDFI_CTRLUPD_MAX_F0_MASK 0x1FFFFF00U +#define LPDDR4__DENALI_PI_229__PI_TDFI_CTRLUPD_MAX_F0_SHIFT 8U +#define LPDDR4__DENALI_PI_229__PI_TDFI_CTRLUPD_MAX_F0_WIDTH 21U +#define LPDDR4__PI_TDFI_CTRLUPD_MAX_F0__REG DENALI_PI_229 +#define LPDDR4__PI_TDFI_CTRLUPD_MAX_F0__FLD LPDDR4__DENALI_PI_229__PI_TDFI_CTRLUPD_MAX_F0 + +#define LPDDR4__DENALI_PI_230_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_230_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_230__PI_TDFI_CTRLUPD_INTERVAL_F0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_230__PI_TDFI_CTRLUPD_INTERVAL_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_230__PI_TDFI_CTRLUPD_INTERVAL_F0_WIDTH 32U +#define LPDDR4__PI_TDFI_CTRLUPD_INTERVAL_F0__REG DENALI_PI_230 +#define LPDDR4__PI_TDFI_CTRLUPD_INTERVAL_F0__FLD LPDDR4__DENALI_PI_230__PI_TDFI_CTRLUPD_INTERVAL_F0 + +#define LPDDR4__DENALI_PI_231_READ_MASK 0x001FFFFFU +#define LPDDR4__DENALI_PI_231_WRITE_MASK 0x001FFFFFU +#define LPDDR4__DENALI_PI_231__PI_TDFI_CTRLUPD_MAX_F1_MASK 0x001FFFFFU +#define LPDDR4__DENALI_PI_231__PI_TDFI_CTRLUPD_MAX_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_231__PI_TDFI_CTRLUPD_MAX_F1_WIDTH 21U +#define LPDDR4__PI_TDFI_CTRLUPD_MAX_F1__REG DENALI_PI_231 +#define LPDDR4__PI_TDFI_CTRLUPD_MAX_F1__FLD LPDDR4__DENALI_PI_231__PI_TDFI_CTRLUPD_MAX_F1 + +#define LPDDR4__DENALI_PI_232_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_232_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_232__PI_TDFI_CTRLUPD_INTERVAL_F1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_232__PI_TDFI_CTRLUPD_INTERVAL_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_232__PI_TDFI_CTRLUPD_INTERVAL_F1_WIDTH 32U +#define LPDDR4__PI_TDFI_CTRLUPD_INTERVAL_F1__REG DENALI_PI_232 +#define LPDDR4__PI_TDFI_CTRLUPD_INTERVAL_F1__FLD LPDDR4__DENALI_PI_232__PI_TDFI_CTRLUPD_INTERVAL_F1 + +#define LPDDR4__DENALI_PI_233_READ_MASK 0x001FFFFFU +#define LPDDR4__DENALI_PI_233_WRITE_MASK 0x001FFFFFU +#define LPDDR4__DENALI_PI_233__PI_TDFI_CTRLUPD_MAX_F2_MASK 0x001FFFFFU +#define LPDDR4__DENALI_PI_233__PI_TDFI_CTRLUPD_MAX_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_233__PI_TDFI_CTRLUPD_MAX_F2_WIDTH 21U +#define LPDDR4__PI_TDFI_CTRLUPD_MAX_F2__REG DENALI_PI_233 +#define LPDDR4__PI_TDFI_CTRLUPD_MAX_F2__FLD LPDDR4__DENALI_PI_233__PI_TDFI_CTRLUPD_MAX_F2 + +#define LPDDR4__DENALI_PI_234_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_234_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_234__PI_TDFI_CTRLUPD_INTERVAL_F2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_234__PI_TDFI_CTRLUPD_INTERVAL_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_234__PI_TDFI_CTRLUPD_INTERVAL_F2_WIDTH 32U +#define LPDDR4__PI_TDFI_CTRLUPD_INTERVAL_F2__REG DENALI_PI_234 +#define LPDDR4__PI_TDFI_CTRLUPD_INTERVAL_F2__FLD LPDDR4__DENALI_PI_234__PI_TDFI_CTRLUPD_INTERVAL_F2 + +#define LPDDR4__DENALI_PI_235_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_235_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_235__PI_TXSR_F0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PI_235__PI_TXSR_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_235__PI_TXSR_F0_WIDTH 16U +#define LPDDR4__PI_TXSR_F0__REG DENALI_PI_235 +#define LPDDR4__PI_TXSR_F0__FLD LPDDR4__DENALI_PI_235__PI_TXSR_F0 + +#define LPDDR4__DENALI_PI_235__PI_TXSR_F1_MASK 0xFFFF0000U +#define LPDDR4__DENALI_PI_235__PI_TXSR_F1_SHIFT 16U +#define LPDDR4__DENALI_PI_235__PI_TXSR_F1_WIDTH 16U +#define LPDDR4__PI_TXSR_F1__REG DENALI_PI_235 +#define LPDDR4__PI_TXSR_F1__FLD LPDDR4__DENALI_PI_235__PI_TXSR_F1 + +#define LPDDR4__DENALI_PI_236_READ_MASK 0x3F3FFFFFU +#define LPDDR4__DENALI_PI_236_WRITE_MASK 0x3F3FFFFFU +#define LPDDR4__DENALI_PI_236__PI_TXSR_F2_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PI_236__PI_TXSR_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_236__PI_TXSR_F2_WIDTH 16U +#define LPDDR4__PI_TXSR_F2__REG DENALI_PI_236 +#define LPDDR4__PI_TXSR_F2__FLD LPDDR4__DENALI_PI_236__PI_TXSR_F2 + +#define LPDDR4__DENALI_PI_236__PI_TEXCKE_F0_MASK 0x003F0000U +#define LPDDR4__DENALI_PI_236__PI_TEXCKE_F0_SHIFT 16U +#define LPDDR4__DENALI_PI_236__PI_TEXCKE_F0_WIDTH 6U +#define LPDDR4__PI_TEXCKE_F0__REG DENALI_PI_236 +#define LPDDR4__PI_TEXCKE_F0__FLD LPDDR4__DENALI_PI_236__PI_TEXCKE_F0 + +#define LPDDR4__DENALI_PI_236__PI_TEXCKE_F1_MASK 0x3F000000U +#define LPDDR4__DENALI_PI_236__PI_TEXCKE_F1_SHIFT 24U +#define LPDDR4__DENALI_PI_236__PI_TEXCKE_F1_WIDTH 6U +#define LPDDR4__PI_TEXCKE_F1__REG DENALI_PI_236 +#define LPDDR4__PI_TEXCKE_F1__FLD LPDDR4__DENALI_PI_236__PI_TEXCKE_F1 + +#define LPDDR4__DENALI_PI_237_READ_MASK 0xFFFFFF3FU +#define LPDDR4__DENALI_PI_237_WRITE_MASK 0xFFFFFF3FU +#define LPDDR4__DENALI_PI_237__PI_TEXCKE_F2_MASK 0x0000003FU +#define LPDDR4__DENALI_PI_237__PI_TEXCKE_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_237__PI_TEXCKE_F2_WIDTH 6U +#define LPDDR4__PI_TEXCKE_F2__REG DENALI_PI_237 +#define LPDDR4__PI_TEXCKE_F2__FLD LPDDR4__DENALI_PI_237__PI_TEXCKE_F2 + +#define LPDDR4__DENALI_PI_237__PI_TINIT_F0_MASK 0xFFFFFF00U +#define LPDDR4__DENALI_PI_237__PI_TINIT_F0_SHIFT 8U +#define LPDDR4__DENALI_PI_237__PI_TINIT_F0_WIDTH 24U +#define LPDDR4__PI_TINIT_F0__REG DENALI_PI_237 +#define LPDDR4__PI_TINIT_F0__FLD LPDDR4__DENALI_PI_237__PI_TINIT_F0 + +#define LPDDR4__DENALI_PI_238_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_238_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_238__PI_TINIT3_F0_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_238__PI_TINIT3_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_238__PI_TINIT3_F0_WIDTH 24U +#define LPDDR4__PI_TINIT3_F0__REG DENALI_PI_238 +#define LPDDR4__PI_TINIT3_F0__FLD LPDDR4__DENALI_PI_238__PI_TINIT3_F0 + +#define LPDDR4__DENALI_PI_239_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_239_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_239__PI_TINIT4_F0_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_239__PI_TINIT4_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_239__PI_TINIT4_F0_WIDTH 24U +#define LPDDR4__PI_TINIT4_F0__REG DENALI_PI_239 +#define LPDDR4__PI_TINIT4_F0__FLD LPDDR4__DENALI_PI_239__PI_TINIT4_F0 + +#define LPDDR4__DENALI_PI_240_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_240_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_240__PI_TINIT5_F0_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_240__PI_TINIT5_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_240__PI_TINIT5_F0_WIDTH 24U +#define LPDDR4__PI_TINIT5_F0__REG DENALI_PI_240 +#define LPDDR4__PI_TINIT5_F0__FLD LPDDR4__DENALI_PI_240__PI_TINIT5_F0 + +#define LPDDR4__DENALI_PI_241_READ_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PI_241_WRITE_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PI_241__PI_TXSNR_F0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PI_241__PI_TXSNR_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_241__PI_TXSNR_F0_WIDTH 16U +#define LPDDR4__PI_TXSNR_F0__REG DENALI_PI_241 +#define LPDDR4__PI_TXSNR_F0__FLD LPDDR4__DENALI_PI_241__PI_TXSNR_F0 + +#define LPDDR4__DENALI_PI_242_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_242_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_242__PI_TINIT_F1_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_242__PI_TINIT_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_242__PI_TINIT_F1_WIDTH 24U +#define LPDDR4__PI_TINIT_F1__REG DENALI_PI_242 +#define LPDDR4__PI_TINIT_F1__FLD LPDDR4__DENALI_PI_242__PI_TINIT_F1 + +#define LPDDR4__DENALI_PI_243_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_243_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_243__PI_TINIT3_F1_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_243__PI_TINIT3_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_243__PI_TINIT3_F1_WIDTH 24U +#define LPDDR4__PI_TINIT3_F1__REG DENALI_PI_243 +#define LPDDR4__PI_TINIT3_F1__FLD LPDDR4__DENALI_PI_243__PI_TINIT3_F1 + +#define LPDDR4__DENALI_PI_244_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_244_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_244__PI_TINIT4_F1_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_244__PI_TINIT4_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_244__PI_TINIT4_F1_WIDTH 24U +#define LPDDR4__PI_TINIT4_F1__REG DENALI_PI_244 +#define LPDDR4__PI_TINIT4_F1__FLD LPDDR4__DENALI_PI_244__PI_TINIT4_F1 + +#define LPDDR4__DENALI_PI_245_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_245_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_245__PI_TINIT5_F1_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_245__PI_TINIT5_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_245__PI_TINIT5_F1_WIDTH 24U +#define LPDDR4__PI_TINIT5_F1__REG DENALI_PI_245 +#define LPDDR4__PI_TINIT5_F1__FLD LPDDR4__DENALI_PI_245__PI_TINIT5_F1 + +#define LPDDR4__DENALI_PI_246_READ_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PI_246_WRITE_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PI_246__PI_TXSNR_F1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PI_246__PI_TXSNR_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_246__PI_TXSNR_F1_WIDTH 16U +#define LPDDR4__PI_TXSNR_F1__REG DENALI_PI_246 +#define LPDDR4__PI_TXSNR_F1__FLD LPDDR4__DENALI_PI_246__PI_TXSNR_F1 + +#define LPDDR4__DENALI_PI_247_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_247_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_247__PI_TINIT_F2_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_247__PI_TINIT_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_247__PI_TINIT_F2_WIDTH 24U +#define LPDDR4__PI_TINIT_F2__REG DENALI_PI_247 +#define LPDDR4__PI_TINIT_F2__FLD LPDDR4__DENALI_PI_247__PI_TINIT_F2 + +#define LPDDR4__DENALI_PI_248_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_248_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_248__PI_TINIT3_F2_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_248__PI_TINIT3_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_248__PI_TINIT3_F2_WIDTH 24U +#define LPDDR4__PI_TINIT3_F2__REG DENALI_PI_248 +#define LPDDR4__PI_TINIT3_F2__FLD LPDDR4__DENALI_PI_248__PI_TINIT3_F2 + +#define LPDDR4__DENALI_PI_249_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_249_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_249__PI_TINIT4_F2_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_249__PI_TINIT4_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_249__PI_TINIT4_F2_WIDTH 24U +#define LPDDR4__PI_TINIT4_F2__REG DENALI_PI_249 +#define LPDDR4__PI_TINIT4_F2__FLD LPDDR4__DENALI_PI_249__PI_TINIT4_F2 + +#define LPDDR4__DENALI_PI_250_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_250_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_250__PI_TINIT5_F2_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_250__PI_TINIT5_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_250__PI_TINIT5_F2_WIDTH 24U +#define LPDDR4__PI_TINIT5_F2__REG DENALI_PI_250 +#define LPDDR4__PI_TINIT5_F2__FLD LPDDR4__DENALI_PI_250__PI_TINIT5_F2 + +#define LPDDR4__DENALI_PI_251_READ_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PI_251_WRITE_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PI_251__PI_TXSNR_F2_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PI_251__PI_TXSNR_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_251__PI_TXSNR_F2_WIDTH 16U +#define LPDDR4__PI_TXSNR_F2__REG DENALI_PI_251 +#define LPDDR4__PI_TXSNR_F2__FLD LPDDR4__DENALI_PI_251__PI_TXSNR_F2 + +#define LPDDR4__DENALI_PI_251__PI_RESERVED49_MASK 0x0FFF0000U +#define LPDDR4__DENALI_PI_251__PI_RESERVED49_SHIFT 16U +#define LPDDR4__DENALI_PI_251__PI_RESERVED49_WIDTH 12U +#define LPDDR4__PI_RESERVED49__REG DENALI_PI_251 +#define LPDDR4__PI_RESERVED49__FLD LPDDR4__DENALI_PI_251__PI_RESERVED49 + +#define LPDDR4__DENALI_PI_252_READ_MASK 0x0FFF0FFFU +#define LPDDR4__DENALI_PI_252_WRITE_MASK 0x0FFF0FFFU +#define LPDDR4__DENALI_PI_252__PI_RESERVED50_MASK 0x00000FFFU +#define LPDDR4__DENALI_PI_252__PI_RESERVED50_SHIFT 0U +#define LPDDR4__DENALI_PI_252__PI_RESERVED50_WIDTH 12U +#define LPDDR4__PI_RESERVED50__REG DENALI_PI_252 +#define LPDDR4__PI_RESERVED50__FLD LPDDR4__DENALI_PI_252__PI_RESERVED50 + +#define LPDDR4__DENALI_PI_252__PI_TZQCAL_F0_MASK 0x0FFF0000U +#define LPDDR4__DENALI_PI_252__PI_TZQCAL_F0_SHIFT 16U +#define LPDDR4__DENALI_PI_252__PI_TZQCAL_F0_WIDTH 12U +#define LPDDR4__PI_TZQCAL_F0__REG DENALI_PI_252 +#define LPDDR4__PI_TZQCAL_F0__FLD LPDDR4__DENALI_PI_252__PI_TZQCAL_F0 + +#define LPDDR4__DENALI_PI_253_READ_MASK 0x000FFF7FU +#define LPDDR4__DENALI_PI_253_WRITE_MASK 0x000FFF7FU +#define LPDDR4__DENALI_PI_253__PI_TZQLAT_F0_MASK 0x0000007FU +#define LPDDR4__DENALI_PI_253__PI_TZQLAT_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_253__PI_TZQLAT_F0_WIDTH 7U +#define LPDDR4__PI_TZQLAT_F0__REG DENALI_PI_253 +#define LPDDR4__PI_TZQLAT_F0__FLD LPDDR4__DENALI_PI_253__PI_TZQLAT_F0 + +#define LPDDR4__DENALI_PI_253__PI_RESERVED51_MASK 0x000FFF00U +#define LPDDR4__DENALI_PI_253__PI_RESERVED51_SHIFT 8U +#define LPDDR4__DENALI_PI_253__PI_RESERVED51_WIDTH 12U +#define LPDDR4__PI_RESERVED51__REG DENALI_PI_253 +#define LPDDR4__PI_RESERVED51__FLD LPDDR4__DENALI_PI_253__PI_RESERVED51 + +#define LPDDR4__DENALI_PI_254_READ_MASK 0x0FFF0FFFU +#define LPDDR4__DENALI_PI_254_WRITE_MASK 0x0FFF0FFFU +#define LPDDR4__DENALI_PI_254__PI_RESERVED52_MASK 0x00000FFFU +#define LPDDR4__DENALI_PI_254__PI_RESERVED52_SHIFT 0U +#define LPDDR4__DENALI_PI_254__PI_RESERVED52_WIDTH 12U +#define LPDDR4__PI_RESERVED52__REG DENALI_PI_254 +#define LPDDR4__PI_RESERVED52__FLD LPDDR4__DENALI_PI_254__PI_RESERVED52 + +#define LPDDR4__DENALI_PI_254__PI_TZQCAL_F1_MASK 0x0FFF0000U +#define LPDDR4__DENALI_PI_254__PI_TZQCAL_F1_SHIFT 16U +#define LPDDR4__DENALI_PI_254__PI_TZQCAL_F1_WIDTH 12U +#define LPDDR4__PI_TZQCAL_F1__REG DENALI_PI_254 +#define LPDDR4__PI_TZQCAL_F1__FLD LPDDR4__DENALI_PI_254__PI_TZQCAL_F1 + +#define LPDDR4__DENALI_PI_255_READ_MASK 0x000FFF7FU +#define LPDDR4__DENALI_PI_255_WRITE_MASK 0x000FFF7FU +#define LPDDR4__DENALI_PI_255__PI_TZQLAT_F1_MASK 0x0000007FU +#define LPDDR4__DENALI_PI_255__PI_TZQLAT_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_255__PI_TZQLAT_F1_WIDTH 7U +#define LPDDR4__PI_TZQLAT_F1__REG DENALI_PI_255 +#define LPDDR4__PI_TZQLAT_F1__FLD LPDDR4__DENALI_PI_255__PI_TZQLAT_F1 + +#define LPDDR4__DENALI_PI_255__PI_RESERVED53_MASK 0x000FFF00U +#define LPDDR4__DENALI_PI_255__PI_RESERVED53_SHIFT 8U +#define LPDDR4__DENALI_PI_255__PI_RESERVED53_WIDTH 12U +#define LPDDR4__PI_RESERVED53__REG DENALI_PI_255 +#define LPDDR4__PI_RESERVED53__FLD LPDDR4__DENALI_PI_255__PI_RESERVED53 + +#define LPDDR4__DENALI_PI_256_READ_MASK 0x0FFF0FFFU +#define LPDDR4__DENALI_PI_256_WRITE_MASK 0x0FFF0FFFU +#define LPDDR4__DENALI_PI_256__PI_RESERVED54_MASK 0x00000FFFU +#define LPDDR4__DENALI_PI_256__PI_RESERVED54_SHIFT 0U +#define LPDDR4__DENALI_PI_256__PI_RESERVED54_WIDTH 12U +#define LPDDR4__PI_RESERVED54__REG DENALI_PI_256 +#define LPDDR4__PI_RESERVED54__FLD LPDDR4__DENALI_PI_256__PI_RESERVED54 + +#define LPDDR4__DENALI_PI_256__PI_TZQCAL_F2_MASK 0x0FFF0000U +#define LPDDR4__DENALI_PI_256__PI_TZQCAL_F2_SHIFT 16U +#define LPDDR4__DENALI_PI_256__PI_TZQCAL_F2_WIDTH 12U +#define LPDDR4__PI_TZQCAL_F2__REG DENALI_PI_256 +#define LPDDR4__PI_TZQCAL_F2__FLD LPDDR4__DENALI_PI_256__PI_TZQCAL_F2 + +#define LPDDR4__DENALI_PI_257_READ_MASK 0x000FFF7FU +#define LPDDR4__DENALI_PI_257_WRITE_MASK 0x000FFF7FU +#define LPDDR4__DENALI_PI_257__PI_TZQLAT_F2_MASK 0x0000007FU +#define LPDDR4__DENALI_PI_257__PI_TZQLAT_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_257__PI_TZQLAT_F2_WIDTH 7U +#define LPDDR4__PI_TZQLAT_F2__REG DENALI_PI_257 +#define LPDDR4__PI_TZQLAT_F2__FLD LPDDR4__DENALI_PI_257__PI_TZQLAT_F2 + +#define LPDDR4__DENALI_PI_257__PI_RESERVED55_MASK 0x000FFF00U +#define LPDDR4__DENALI_PI_257__PI_RESERVED55_SHIFT 8U +#define LPDDR4__DENALI_PI_257__PI_RESERVED55_WIDTH 12U +#define LPDDR4__PI_RESERVED55__REG DENALI_PI_257 +#define LPDDR4__PI_RESERVED55__FLD LPDDR4__DENALI_PI_257__PI_RESERVED55 + +#define LPDDR4__DENALI_PI_258_READ_MASK 0x0FFF0FFFU +#define LPDDR4__DENALI_PI_258_WRITE_MASK 0x0FFF0FFFU +#define LPDDR4__DENALI_PI_258__PI_RESERVED56_MASK 0x00000FFFU +#define LPDDR4__DENALI_PI_258__PI_RESERVED56_SHIFT 0U +#define LPDDR4__DENALI_PI_258__PI_RESERVED56_WIDTH 12U +#define LPDDR4__PI_RESERVED56__REG DENALI_PI_258 +#define LPDDR4__PI_RESERVED56__FLD LPDDR4__DENALI_PI_258__PI_RESERVED56 + +#define LPDDR4__DENALI_PI_258__PI_RESERVED57_MASK 0x0FFF0000U +#define LPDDR4__DENALI_PI_258__PI_RESERVED57_SHIFT 16U +#define LPDDR4__DENALI_PI_258__PI_RESERVED57_WIDTH 12U +#define LPDDR4__PI_RESERVED57__REG DENALI_PI_258 +#define LPDDR4__PI_RESERVED57__FLD LPDDR4__DENALI_PI_258__PI_RESERVED57 + +#define LPDDR4__DENALI_PI_259_READ_MASK 0xFF0F0F0FU +#define LPDDR4__DENALI_PI_259_WRITE_MASK 0xFF0F0F0FU +#define LPDDR4__DENALI_PI_259__PI_WDQ_OSC_DELTA_INDEX_F0_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_259__PI_WDQ_OSC_DELTA_INDEX_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_259__PI_WDQ_OSC_DELTA_INDEX_F0_WIDTH 4U +#define LPDDR4__PI_WDQ_OSC_DELTA_INDEX_F0__REG DENALI_PI_259 +#define LPDDR4__PI_WDQ_OSC_DELTA_INDEX_F0__FLD LPDDR4__DENALI_PI_259__PI_WDQ_OSC_DELTA_INDEX_F0 + +#define LPDDR4__DENALI_PI_259__PI_WDQ_OSC_DELTA_INDEX_F1_MASK 0x00000F00U +#define LPDDR4__DENALI_PI_259__PI_WDQ_OSC_DELTA_INDEX_F1_SHIFT 8U +#define LPDDR4__DENALI_PI_259__PI_WDQ_OSC_DELTA_INDEX_F1_WIDTH 4U +#define LPDDR4__PI_WDQ_OSC_DELTA_INDEX_F1__REG DENALI_PI_259 +#define LPDDR4__PI_WDQ_OSC_DELTA_INDEX_F1__FLD LPDDR4__DENALI_PI_259__PI_WDQ_OSC_DELTA_INDEX_F1 + +#define LPDDR4__DENALI_PI_259__PI_WDQ_OSC_DELTA_INDEX_F2_MASK 0x000F0000U +#define LPDDR4__DENALI_PI_259__PI_WDQ_OSC_DELTA_INDEX_F2_SHIFT 16U +#define LPDDR4__DENALI_PI_259__PI_WDQ_OSC_DELTA_INDEX_F2_WIDTH 4U +#define LPDDR4__PI_WDQ_OSC_DELTA_INDEX_F2__REG DENALI_PI_259 +#define LPDDR4__PI_WDQ_OSC_DELTA_INDEX_F2__FLD LPDDR4__DENALI_PI_259__PI_WDQ_OSC_DELTA_INDEX_F2 + +#define LPDDR4__DENALI_PI_259__PI_MR13_DATA_0_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_259__PI_MR13_DATA_0_SHIFT 24U +#define LPDDR4__DENALI_PI_259__PI_MR13_DATA_0_WIDTH 8U +#define LPDDR4__PI_MR13_DATA_0__REG DENALI_PI_259 +#define LPDDR4__PI_MR13_DATA_0__FLD LPDDR4__DENALI_PI_259__PI_MR13_DATA_0 + +#define LPDDR4__DENALI_PI_260_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_260_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_260__PI_MR15_DATA_0_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_260__PI_MR15_DATA_0_SHIFT 0U +#define LPDDR4__DENALI_PI_260__PI_MR15_DATA_0_WIDTH 8U +#define LPDDR4__PI_MR15_DATA_0__REG DENALI_PI_260 +#define LPDDR4__PI_MR15_DATA_0__FLD LPDDR4__DENALI_PI_260__PI_MR15_DATA_0 + +#define LPDDR4__DENALI_PI_260__PI_MR16_DATA_0_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_260__PI_MR16_DATA_0_SHIFT 8U +#define LPDDR4__DENALI_PI_260__PI_MR16_DATA_0_WIDTH 8U +#define LPDDR4__PI_MR16_DATA_0__REG DENALI_PI_260 +#define LPDDR4__PI_MR16_DATA_0__FLD LPDDR4__DENALI_PI_260__PI_MR16_DATA_0 + +#define LPDDR4__DENALI_PI_260__PI_MR17_DATA_0_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_260__PI_MR17_DATA_0_SHIFT 16U +#define LPDDR4__DENALI_PI_260__PI_MR17_DATA_0_WIDTH 8U +#define LPDDR4__PI_MR17_DATA_0__REG DENALI_PI_260 +#define LPDDR4__PI_MR17_DATA_0__FLD LPDDR4__DENALI_PI_260__PI_MR17_DATA_0 + +#define LPDDR4__DENALI_PI_260__PI_MR20_DATA_0_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_260__PI_MR20_DATA_0_SHIFT 24U +#define LPDDR4__DENALI_PI_260__PI_MR20_DATA_0_WIDTH 8U +#define LPDDR4__PI_MR20_DATA_0__REG DENALI_PI_260 +#define LPDDR4__PI_MR20_DATA_0__FLD LPDDR4__DENALI_PI_260__PI_MR20_DATA_0 + +#define LPDDR4__DENALI_PI_261_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_261_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_261__PI_MR32_DATA_0_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_261__PI_MR32_DATA_0_SHIFT 0U +#define LPDDR4__DENALI_PI_261__PI_MR32_DATA_0_WIDTH 8U +#define LPDDR4__PI_MR32_DATA_0__REG DENALI_PI_261 +#define LPDDR4__PI_MR32_DATA_0__FLD LPDDR4__DENALI_PI_261__PI_MR32_DATA_0 + +#define LPDDR4__DENALI_PI_261__PI_MR40_DATA_0_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_261__PI_MR40_DATA_0_SHIFT 8U +#define LPDDR4__DENALI_PI_261__PI_MR40_DATA_0_WIDTH 8U +#define LPDDR4__PI_MR40_DATA_0__REG DENALI_PI_261 +#define LPDDR4__PI_MR40_DATA_0__FLD LPDDR4__DENALI_PI_261__PI_MR40_DATA_0 + +#define LPDDR4__DENALI_PI_261__PI_MR13_DATA_1_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_261__PI_MR13_DATA_1_SHIFT 16U +#define LPDDR4__DENALI_PI_261__PI_MR13_DATA_1_WIDTH 8U +#define LPDDR4__PI_MR13_DATA_1__REG DENALI_PI_261 +#define LPDDR4__PI_MR13_DATA_1__FLD LPDDR4__DENALI_PI_261__PI_MR13_DATA_1 + +#define LPDDR4__DENALI_PI_261__PI_MR15_DATA_1_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_261__PI_MR15_DATA_1_SHIFT 24U +#define LPDDR4__DENALI_PI_261__PI_MR15_DATA_1_WIDTH 8U +#define LPDDR4__PI_MR15_DATA_1__REG DENALI_PI_261 +#define LPDDR4__PI_MR15_DATA_1__FLD LPDDR4__DENALI_PI_261__PI_MR15_DATA_1 + +#define LPDDR4__DENALI_PI_262_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_262_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_262__PI_MR16_DATA_1_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_262__PI_MR16_DATA_1_SHIFT 0U +#define LPDDR4__DENALI_PI_262__PI_MR16_DATA_1_WIDTH 8U +#define LPDDR4__PI_MR16_DATA_1__REG DENALI_PI_262 +#define LPDDR4__PI_MR16_DATA_1__FLD LPDDR4__DENALI_PI_262__PI_MR16_DATA_1 + +#define LPDDR4__DENALI_PI_262__PI_MR17_DATA_1_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_262__PI_MR17_DATA_1_SHIFT 8U +#define LPDDR4__DENALI_PI_262__PI_MR17_DATA_1_WIDTH 8U +#define LPDDR4__PI_MR17_DATA_1__REG DENALI_PI_262 +#define LPDDR4__PI_MR17_DATA_1__FLD LPDDR4__DENALI_PI_262__PI_MR17_DATA_1 + +#define LPDDR4__DENALI_PI_262__PI_MR20_DATA_1_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_262__PI_MR20_DATA_1_SHIFT 16U +#define LPDDR4__DENALI_PI_262__PI_MR20_DATA_1_WIDTH 8U +#define LPDDR4__PI_MR20_DATA_1__REG DENALI_PI_262 +#define LPDDR4__PI_MR20_DATA_1__FLD LPDDR4__DENALI_PI_262__PI_MR20_DATA_1 + +#define LPDDR4__DENALI_PI_262__PI_MR32_DATA_1_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_262__PI_MR32_DATA_1_SHIFT 24U +#define LPDDR4__DENALI_PI_262__PI_MR32_DATA_1_WIDTH 8U +#define LPDDR4__PI_MR32_DATA_1__REG DENALI_PI_262 +#define LPDDR4__PI_MR32_DATA_1__FLD LPDDR4__DENALI_PI_262__PI_MR32_DATA_1 + +#define LPDDR4__DENALI_PI_263_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_263_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_263__PI_MR40_DATA_1_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_263__PI_MR40_DATA_1_SHIFT 0U +#define LPDDR4__DENALI_PI_263__PI_MR40_DATA_1_WIDTH 8U +#define LPDDR4__PI_MR40_DATA_1__REG DENALI_PI_263 +#define LPDDR4__PI_MR40_DATA_1__FLD LPDDR4__DENALI_PI_263__PI_MR40_DATA_1 + +#define LPDDR4__DENALI_PI_263__PI_MR13_DATA_2_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_263__PI_MR13_DATA_2_SHIFT 8U +#define LPDDR4__DENALI_PI_263__PI_MR13_DATA_2_WIDTH 8U +#define LPDDR4__PI_MR13_DATA_2__REG DENALI_PI_263 +#define LPDDR4__PI_MR13_DATA_2__FLD LPDDR4__DENALI_PI_263__PI_MR13_DATA_2 + +#define LPDDR4__DENALI_PI_263__PI_MR15_DATA_2_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_263__PI_MR15_DATA_2_SHIFT 16U +#define LPDDR4__DENALI_PI_263__PI_MR15_DATA_2_WIDTH 8U +#define LPDDR4__PI_MR15_DATA_2__REG DENALI_PI_263 +#define LPDDR4__PI_MR15_DATA_2__FLD LPDDR4__DENALI_PI_263__PI_MR15_DATA_2 + +#define LPDDR4__DENALI_PI_263__PI_MR16_DATA_2_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_263__PI_MR16_DATA_2_SHIFT 24U +#define LPDDR4__DENALI_PI_263__PI_MR16_DATA_2_WIDTH 8U +#define LPDDR4__PI_MR16_DATA_2__REG DENALI_PI_263 +#define LPDDR4__PI_MR16_DATA_2__FLD LPDDR4__DENALI_PI_263__PI_MR16_DATA_2 + +#define LPDDR4__DENALI_PI_264_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_264_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_264__PI_MR17_DATA_2_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_264__PI_MR17_DATA_2_SHIFT 0U +#define LPDDR4__DENALI_PI_264__PI_MR17_DATA_2_WIDTH 8U +#define LPDDR4__PI_MR17_DATA_2__REG DENALI_PI_264 +#define LPDDR4__PI_MR17_DATA_2__FLD LPDDR4__DENALI_PI_264__PI_MR17_DATA_2 + +#define LPDDR4__DENALI_PI_264__PI_MR20_DATA_2_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_264__PI_MR20_DATA_2_SHIFT 8U +#define LPDDR4__DENALI_PI_264__PI_MR20_DATA_2_WIDTH 8U +#define LPDDR4__PI_MR20_DATA_2__REG DENALI_PI_264 +#define LPDDR4__PI_MR20_DATA_2__FLD LPDDR4__DENALI_PI_264__PI_MR20_DATA_2 + +#define LPDDR4__DENALI_PI_264__PI_MR32_DATA_2_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_264__PI_MR32_DATA_2_SHIFT 16U +#define LPDDR4__DENALI_PI_264__PI_MR32_DATA_2_WIDTH 8U +#define LPDDR4__PI_MR32_DATA_2__REG DENALI_PI_264 +#define LPDDR4__PI_MR32_DATA_2__FLD LPDDR4__DENALI_PI_264__PI_MR32_DATA_2 + +#define LPDDR4__DENALI_PI_264__PI_MR40_DATA_2_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_264__PI_MR40_DATA_2_SHIFT 24U +#define LPDDR4__DENALI_PI_264__PI_MR40_DATA_2_WIDTH 8U +#define LPDDR4__PI_MR40_DATA_2__REG DENALI_PI_264 +#define LPDDR4__PI_MR40_DATA_2__FLD LPDDR4__DENALI_PI_264__PI_MR40_DATA_2 + +#define LPDDR4__DENALI_PI_265_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_265_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_265__PI_MR13_DATA_3_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_265__PI_MR13_DATA_3_SHIFT 0U +#define LPDDR4__DENALI_PI_265__PI_MR13_DATA_3_WIDTH 8U +#define LPDDR4__PI_MR13_DATA_3__REG DENALI_PI_265 +#define LPDDR4__PI_MR13_DATA_3__FLD LPDDR4__DENALI_PI_265__PI_MR13_DATA_3 + +#define LPDDR4__DENALI_PI_265__PI_MR15_DATA_3_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_265__PI_MR15_DATA_3_SHIFT 8U +#define LPDDR4__DENALI_PI_265__PI_MR15_DATA_3_WIDTH 8U +#define LPDDR4__PI_MR15_DATA_3__REG DENALI_PI_265 +#define LPDDR4__PI_MR15_DATA_3__FLD LPDDR4__DENALI_PI_265__PI_MR15_DATA_3 + +#define LPDDR4__DENALI_PI_265__PI_MR16_DATA_3_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_265__PI_MR16_DATA_3_SHIFT 16U +#define LPDDR4__DENALI_PI_265__PI_MR16_DATA_3_WIDTH 8U +#define LPDDR4__PI_MR16_DATA_3__REG DENALI_PI_265 +#define LPDDR4__PI_MR16_DATA_3__FLD LPDDR4__DENALI_PI_265__PI_MR16_DATA_3 + +#define LPDDR4__DENALI_PI_265__PI_MR17_DATA_3_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_265__PI_MR17_DATA_3_SHIFT 24U +#define LPDDR4__DENALI_PI_265__PI_MR17_DATA_3_WIDTH 8U +#define LPDDR4__PI_MR17_DATA_3__REG DENALI_PI_265 +#define LPDDR4__PI_MR17_DATA_3__FLD LPDDR4__DENALI_PI_265__PI_MR17_DATA_3 + +#define LPDDR4__DENALI_PI_266_READ_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PI_266_WRITE_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PI_266__PI_MR20_DATA_3_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_266__PI_MR20_DATA_3_SHIFT 0U +#define LPDDR4__DENALI_PI_266__PI_MR20_DATA_3_WIDTH 8U +#define LPDDR4__PI_MR20_DATA_3__REG DENALI_PI_266 +#define LPDDR4__PI_MR20_DATA_3__FLD LPDDR4__DENALI_PI_266__PI_MR20_DATA_3 + +#define LPDDR4__DENALI_PI_266__PI_MR32_DATA_3_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_266__PI_MR32_DATA_3_SHIFT 8U +#define LPDDR4__DENALI_PI_266__PI_MR32_DATA_3_WIDTH 8U +#define LPDDR4__PI_MR32_DATA_3__REG DENALI_PI_266 +#define LPDDR4__PI_MR32_DATA_3__FLD LPDDR4__DENALI_PI_266__PI_MR32_DATA_3 + +#define LPDDR4__DENALI_PI_266__PI_MR40_DATA_3_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_266__PI_MR40_DATA_3_SHIFT 16U +#define LPDDR4__DENALI_PI_266__PI_MR40_DATA_3_WIDTH 8U +#define LPDDR4__PI_MR40_DATA_3__REG DENALI_PI_266 +#define LPDDR4__PI_MR40_DATA_3__FLD LPDDR4__DENALI_PI_266__PI_MR40_DATA_3 + +#define LPDDR4__DENALI_PI_266__PI_CKE_MUX_0_MASK 0x0F000000U +#define LPDDR4__DENALI_PI_266__PI_CKE_MUX_0_SHIFT 24U +#define LPDDR4__DENALI_PI_266__PI_CKE_MUX_0_WIDTH 4U +#define LPDDR4__PI_CKE_MUX_0__REG DENALI_PI_266 +#define LPDDR4__PI_CKE_MUX_0__FLD LPDDR4__DENALI_PI_266__PI_CKE_MUX_0 + +#define LPDDR4__DENALI_PI_267_READ_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_PI_267_WRITE_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_PI_267__PI_CKE_MUX_1_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_267__PI_CKE_MUX_1_SHIFT 0U +#define LPDDR4__DENALI_PI_267__PI_CKE_MUX_1_WIDTH 4U +#define LPDDR4__PI_CKE_MUX_1__REG DENALI_PI_267 +#define LPDDR4__PI_CKE_MUX_1__FLD LPDDR4__DENALI_PI_267__PI_CKE_MUX_1 + +#define LPDDR4__DENALI_PI_267__PI_CKE_MUX_2_MASK 0x00000F00U +#define LPDDR4__DENALI_PI_267__PI_CKE_MUX_2_SHIFT 8U +#define LPDDR4__DENALI_PI_267__PI_CKE_MUX_2_WIDTH 4U +#define LPDDR4__PI_CKE_MUX_2__REG DENALI_PI_267 +#define LPDDR4__PI_CKE_MUX_2__FLD LPDDR4__DENALI_PI_267__PI_CKE_MUX_2 + +#define LPDDR4__DENALI_PI_267__PI_CKE_MUX_3_MASK 0x000F0000U +#define LPDDR4__DENALI_PI_267__PI_CKE_MUX_3_SHIFT 16U +#define LPDDR4__DENALI_PI_267__PI_CKE_MUX_3_WIDTH 4U +#define LPDDR4__PI_CKE_MUX_3__REG DENALI_PI_267 +#define LPDDR4__PI_CKE_MUX_3__FLD LPDDR4__DENALI_PI_267__PI_CKE_MUX_3 + +#define LPDDR4__DENALI_PI_267__PI_CS_MUX_0_MASK 0x0F000000U +#define LPDDR4__DENALI_PI_267__PI_CS_MUX_0_SHIFT 24U +#define LPDDR4__DENALI_PI_267__PI_CS_MUX_0_WIDTH 4U +#define LPDDR4__PI_CS_MUX_0__REG DENALI_PI_267 +#define LPDDR4__PI_CS_MUX_0__FLD LPDDR4__DENALI_PI_267__PI_CS_MUX_0 + +#define LPDDR4__DENALI_PI_268_READ_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_PI_268_WRITE_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_PI_268__PI_CS_MUX_1_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_268__PI_CS_MUX_1_SHIFT 0U +#define LPDDR4__DENALI_PI_268__PI_CS_MUX_1_WIDTH 4U +#define LPDDR4__PI_CS_MUX_1__REG DENALI_PI_268 +#define LPDDR4__PI_CS_MUX_1__FLD LPDDR4__DENALI_PI_268__PI_CS_MUX_1 + +#define LPDDR4__DENALI_PI_268__PI_CS_MUX_2_MASK 0x00000F00U +#define LPDDR4__DENALI_PI_268__PI_CS_MUX_2_SHIFT 8U +#define LPDDR4__DENALI_PI_268__PI_CS_MUX_2_WIDTH 4U +#define LPDDR4__PI_CS_MUX_2__REG DENALI_PI_268 +#define LPDDR4__PI_CS_MUX_2__FLD LPDDR4__DENALI_PI_268__PI_CS_MUX_2 + +#define LPDDR4__DENALI_PI_268__PI_CS_MUX_3_MASK 0x000F0000U +#define LPDDR4__DENALI_PI_268__PI_CS_MUX_3_SHIFT 16U +#define LPDDR4__DENALI_PI_268__PI_CS_MUX_3_WIDTH 4U +#define LPDDR4__PI_CS_MUX_3__REG DENALI_PI_268 +#define LPDDR4__PI_CS_MUX_3__FLD LPDDR4__DENALI_PI_268__PI_CS_MUX_3 + +#define LPDDR4__DENALI_PI_268__PI_RESET_N_MUX_0_MASK 0x0F000000U +#define LPDDR4__DENALI_PI_268__PI_RESET_N_MUX_0_SHIFT 24U +#define LPDDR4__DENALI_PI_268__PI_RESET_N_MUX_0_WIDTH 4U +#define LPDDR4__PI_RESET_N_MUX_0__REG DENALI_PI_268 +#define LPDDR4__PI_RESET_N_MUX_0__FLD LPDDR4__DENALI_PI_268__PI_RESET_N_MUX_0 + +#define LPDDR4__DENALI_PI_269_READ_MASK 0xFF0F0F0FU +#define LPDDR4__DENALI_PI_269_WRITE_MASK 0xFF0F0F0FU +#define LPDDR4__DENALI_PI_269__PI_RESET_N_MUX_1_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_269__PI_RESET_N_MUX_1_SHIFT 0U +#define LPDDR4__DENALI_PI_269__PI_RESET_N_MUX_1_WIDTH 4U +#define LPDDR4__PI_RESET_N_MUX_1__REG DENALI_PI_269 +#define LPDDR4__PI_RESET_N_MUX_1__FLD LPDDR4__DENALI_PI_269__PI_RESET_N_MUX_1 + +#define LPDDR4__DENALI_PI_269__PI_RESET_N_MUX_2_MASK 0x00000F00U +#define LPDDR4__DENALI_PI_269__PI_RESET_N_MUX_2_SHIFT 8U +#define LPDDR4__DENALI_PI_269__PI_RESET_N_MUX_2_WIDTH 4U +#define LPDDR4__PI_RESET_N_MUX_2__REG DENALI_PI_269 +#define LPDDR4__PI_RESET_N_MUX_2__FLD LPDDR4__DENALI_PI_269__PI_RESET_N_MUX_2 + +#define LPDDR4__DENALI_PI_269__PI_RESET_N_MUX_3_MASK 0x000F0000U +#define LPDDR4__DENALI_PI_269__PI_RESET_N_MUX_3_SHIFT 16U +#define LPDDR4__DENALI_PI_269__PI_RESET_N_MUX_3_WIDTH 4U +#define LPDDR4__PI_RESET_N_MUX_3__REG DENALI_PI_269 +#define LPDDR4__PI_RESET_N_MUX_3__FLD LPDDR4__DENALI_PI_269__PI_RESET_N_MUX_3 + +#define LPDDR4__DENALI_PI_269__PI_MRSINGLE_DATA_0_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_269__PI_MRSINGLE_DATA_0_SHIFT 24U +#define LPDDR4__DENALI_PI_269__PI_MRSINGLE_DATA_0_WIDTH 8U +#define LPDDR4__PI_MRSINGLE_DATA_0__REG DENALI_PI_269 +#define LPDDR4__PI_MRSINGLE_DATA_0__FLD LPDDR4__DENALI_PI_269__PI_MRSINGLE_DATA_0 + +#define LPDDR4__DENALI_PI_270_READ_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PI_270_WRITE_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PI_270__PI_MRSINGLE_DATA_1_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_270__PI_MRSINGLE_DATA_1_SHIFT 0U +#define LPDDR4__DENALI_PI_270__PI_MRSINGLE_DATA_1_WIDTH 8U +#define LPDDR4__PI_MRSINGLE_DATA_1__REG DENALI_PI_270 +#define LPDDR4__PI_MRSINGLE_DATA_1__FLD LPDDR4__DENALI_PI_270__PI_MRSINGLE_DATA_1 + +#define LPDDR4__DENALI_PI_270__PI_MRSINGLE_DATA_2_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_270__PI_MRSINGLE_DATA_2_SHIFT 8U +#define LPDDR4__DENALI_PI_270__PI_MRSINGLE_DATA_2_WIDTH 8U +#define LPDDR4__PI_MRSINGLE_DATA_2__REG DENALI_PI_270 +#define LPDDR4__PI_MRSINGLE_DATA_2__FLD LPDDR4__DENALI_PI_270__PI_MRSINGLE_DATA_2 + +#define LPDDR4__DENALI_PI_270__PI_MRSINGLE_DATA_3_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_270__PI_MRSINGLE_DATA_3_SHIFT 16U +#define LPDDR4__DENALI_PI_270__PI_MRSINGLE_DATA_3_WIDTH 8U +#define LPDDR4__PI_MRSINGLE_DATA_3__REG DENALI_PI_270 +#define LPDDR4__PI_MRSINGLE_DATA_3__FLD LPDDR4__DENALI_PI_270__PI_MRSINGLE_DATA_3 + +#define LPDDR4__DENALI_PI_270__PI_ZQ_CAL_START_MAP_0_MASK 0x0F000000U +#define LPDDR4__DENALI_PI_270__PI_ZQ_CAL_START_MAP_0_SHIFT 24U +#define LPDDR4__DENALI_PI_270__PI_ZQ_CAL_START_MAP_0_WIDTH 4U +#define LPDDR4__PI_ZQ_CAL_START_MAP_0__REG DENALI_PI_270 +#define LPDDR4__PI_ZQ_CAL_START_MAP_0__FLD LPDDR4__DENALI_PI_270__PI_ZQ_CAL_START_MAP_0 + +#define LPDDR4__DENALI_PI_271_READ_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_PI_271_WRITE_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_PI_271__PI_ZQ_CAL_LATCH_MAP_0_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_271__PI_ZQ_CAL_LATCH_MAP_0_SHIFT 0U +#define LPDDR4__DENALI_PI_271__PI_ZQ_CAL_LATCH_MAP_0_WIDTH 4U +#define LPDDR4__PI_ZQ_CAL_LATCH_MAP_0__REG DENALI_PI_271 +#define LPDDR4__PI_ZQ_CAL_LATCH_MAP_0__FLD LPDDR4__DENALI_PI_271__PI_ZQ_CAL_LATCH_MAP_0 + +#define LPDDR4__DENALI_PI_271__PI_ZQ_CAL_START_MAP_1_MASK 0x00000F00U +#define LPDDR4__DENALI_PI_271__PI_ZQ_CAL_START_MAP_1_SHIFT 8U +#define LPDDR4__DENALI_PI_271__PI_ZQ_CAL_START_MAP_1_WIDTH 4U +#define LPDDR4__PI_ZQ_CAL_START_MAP_1__REG DENALI_PI_271 +#define LPDDR4__PI_ZQ_CAL_START_MAP_1__FLD LPDDR4__DENALI_PI_271__PI_ZQ_CAL_START_MAP_1 + +#define LPDDR4__DENALI_PI_271__PI_ZQ_CAL_LATCH_MAP_1_MASK 0x000F0000U +#define LPDDR4__DENALI_PI_271__PI_ZQ_CAL_LATCH_MAP_1_SHIFT 16U +#define LPDDR4__DENALI_PI_271__PI_ZQ_CAL_LATCH_MAP_1_WIDTH 4U +#define LPDDR4__PI_ZQ_CAL_LATCH_MAP_1__REG DENALI_PI_271 +#define LPDDR4__PI_ZQ_CAL_LATCH_MAP_1__FLD LPDDR4__DENALI_PI_271__PI_ZQ_CAL_LATCH_MAP_1 + +#define LPDDR4__DENALI_PI_271__PI_ZQ_CAL_START_MAP_2_MASK 0x0F000000U +#define LPDDR4__DENALI_PI_271__PI_ZQ_CAL_START_MAP_2_SHIFT 24U +#define LPDDR4__DENALI_PI_271__PI_ZQ_CAL_START_MAP_2_WIDTH 4U +#define LPDDR4__PI_ZQ_CAL_START_MAP_2__REG DENALI_PI_271 +#define LPDDR4__PI_ZQ_CAL_START_MAP_2__FLD LPDDR4__DENALI_PI_271__PI_ZQ_CAL_START_MAP_2 + +#define LPDDR4__DENALI_PI_272_READ_MASK 0x000F0F0FU +#define LPDDR4__DENALI_PI_272_WRITE_MASK 0x000F0F0FU +#define LPDDR4__DENALI_PI_272__PI_ZQ_CAL_LATCH_MAP_2_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_272__PI_ZQ_CAL_LATCH_MAP_2_SHIFT 0U +#define LPDDR4__DENALI_PI_272__PI_ZQ_CAL_LATCH_MAP_2_WIDTH 4U +#define LPDDR4__PI_ZQ_CAL_LATCH_MAP_2__REG DENALI_PI_272 +#define LPDDR4__PI_ZQ_CAL_LATCH_MAP_2__FLD LPDDR4__DENALI_PI_272__PI_ZQ_CAL_LATCH_MAP_2 + +#define LPDDR4__DENALI_PI_272__PI_ZQ_CAL_START_MAP_3_MASK 0x00000F00U +#define LPDDR4__DENALI_PI_272__PI_ZQ_CAL_START_MAP_3_SHIFT 8U +#define LPDDR4__DENALI_PI_272__PI_ZQ_CAL_START_MAP_3_WIDTH 4U +#define LPDDR4__PI_ZQ_CAL_START_MAP_3__REG DENALI_PI_272 +#define LPDDR4__PI_ZQ_CAL_START_MAP_3__FLD LPDDR4__DENALI_PI_272__PI_ZQ_CAL_START_MAP_3 + +#define LPDDR4__DENALI_PI_272__PI_ZQ_CAL_LATCH_MAP_3_MASK 0x000F0000U +#define LPDDR4__DENALI_PI_272__PI_ZQ_CAL_LATCH_MAP_3_SHIFT 16U +#define LPDDR4__DENALI_PI_272__PI_ZQ_CAL_LATCH_MAP_3_WIDTH 4U +#define LPDDR4__PI_ZQ_CAL_LATCH_MAP_3__REG DENALI_PI_272 +#define LPDDR4__PI_ZQ_CAL_LATCH_MAP_3__FLD LPDDR4__DENALI_PI_272__PI_ZQ_CAL_LATCH_MAP_3 + +#define LPDDR4__DENALI_PI_273_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_273_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_273__PI_DQS_OSC_BASE_VALUE_0_0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PI_273__PI_DQS_OSC_BASE_VALUE_0_0_SHIFT 0U +#define LPDDR4__DENALI_PI_273__PI_DQS_OSC_BASE_VALUE_0_0_WIDTH 16U +#define LPDDR4__PI_DQS_OSC_BASE_VALUE_0_0__REG DENALI_PI_273 +#define LPDDR4__PI_DQS_OSC_BASE_VALUE_0_0__FLD LPDDR4__DENALI_PI_273__PI_DQS_OSC_BASE_VALUE_0_0 + +#define LPDDR4__DENALI_PI_273__PI_DQS_OSC_BASE_VALUE_1_0_MASK 0xFFFF0000U +#define LPDDR4__DENALI_PI_273__PI_DQS_OSC_BASE_VALUE_1_0_SHIFT 16U +#define LPDDR4__DENALI_PI_273__PI_DQS_OSC_BASE_VALUE_1_0_WIDTH 16U +#define LPDDR4__PI_DQS_OSC_BASE_VALUE_1_0__REG DENALI_PI_273 +#define LPDDR4__PI_DQS_OSC_BASE_VALUE_1_0__FLD LPDDR4__DENALI_PI_273__PI_DQS_OSC_BASE_VALUE_1_0 + +#define LPDDR4__DENALI_PI_274_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_274_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_274__PI_DQS_OSC_BASE_VALUE_0_1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PI_274__PI_DQS_OSC_BASE_VALUE_0_1_SHIFT 0U +#define LPDDR4__DENALI_PI_274__PI_DQS_OSC_BASE_VALUE_0_1_WIDTH 16U +#define LPDDR4__PI_DQS_OSC_BASE_VALUE_0_1__REG DENALI_PI_274 +#define LPDDR4__PI_DQS_OSC_BASE_VALUE_0_1__FLD LPDDR4__DENALI_PI_274__PI_DQS_OSC_BASE_VALUE_0_1 + +#define LPDDR4__DENALI_PI_274__PI_DQS_OSC_BASE_VALUE_1_1_MASK 0xFFFF0000U +#define LPDDR4__DENALI_PI_274__PI_DQS_OSC_BASE_VALUE_1_1_SHIFT 16U +#define LPDDR4__DENALI_PI_274__PI_DQS_OSC_BASE_VALUE_1_1_WIDTH 16U +#define LPDDR4__PI_DQS_OSC_BASE_VALUE_1_1__REG DENALI_PI_274 +#define LPDDR4__PI_DQS_OSC_BASE_VALUE_1_1__FLD LPDDR4__DENALI_PI_274__PI_DQS_OSC_BASE_VALUE_1_1 + +#define LPDDR4__DENALI_PI_275_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_275_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_275__PI_MR1_DATA_F0_0_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_275__PI_MR1_DATA_F0_0_SHIFT 0U +#define LPDDR4__DENALI_PI_275__PI_MR1_DATA_F0_0_WIDTH 8U +#define LPDDR4__PI_MR1_DATA_F0_0__REG DENALI_PI_275 +#define LPDDR4__PI_MR1_DATA_F0_0__FLD LPDDR4__DENALI_PI_275__PI_MR1_DATA_F0_0 + +#define LPDDR4__DENALI_PI_275__PI_MR2_DATA_F0_0_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_275__PI_MR2_DATA_F0_0_SHIFT 8U +#define LPDDR4__DENALI_PI_275__PI_MR2_DATA_F0_0_WIDTH 8U +#define LPDDR4__PI_MR2_DATA_F0_0__REG DENALI_PI_275 +#define LPDDR4__PI_MR2_DATA_F0_0__FLD LPDDR4__DENALI_PI_275__PI_MR2_DATA_F0_0 + +#define LPDDR4__DENALI_PI_275__PI_MR3_DATA_F0_0_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_275__PI_MR3_DATA_F0_0_SHIFT 16U +#define LPDDR4__DENALI_PI_275__PI_MR3_DATA_F0_0_WIDTH 8U +#define LPDDR4__PI_MR3_DATA_F0_0__REG DENALI_PI_275 +#define LPDDR4__PI_MR3_DATA_F0_0__FLD LPDDR4__DENALI_PI_275__PI_MR3_DATA_F0_0 + +#define LPDDR4__DENALI_PI_275__PI_MR11_DATA_F0_0_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_275__PI_MR11_DATA_F0_0_SHIFT 24U +#define LPDDR4__DENALI_PI_275__PI_MR11_DATA_F0_0_WIDTH 8U +#define LPDDR4__PI_MR11_DATA_F0_0__REG DENALI_PI_275 +#define LPDDR4__PI_MR11_DATA_F0_0__FLD LPDDR4__DENALI_PI_275__PI_MR11_DATA_F0_0 + +#define LPDDR4__DENALI_PI_276_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_276_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_276__PI_MR12_DATA_F0_0_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_276__PI_MR12_DATA_F0_0_SHIFT 0U +#define LPDDR4__DENALI_PI_276__PI_MR12_DATA_F0_0_WIDTH 8U +#define LPDDR4__PI_MR12_DATA_F0_0__REG DENALI_PI_276 +#define LPDDR4__PI_MR12_DATA_F0_0__FLD LPDDR4__DENALI_PI_276__PI_MR12_DATA_F0_0 + +#define LPDDR4__DENALI_PI_276__PI_MR14_DATA_F0_0_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_276__PI_MR14_DATA_F0_0_SHIFT 8U +#define LPDDR4__DENALI_PI_276__PI_MR14_DATA_F0_0_WIDTH 8U +#define LPDDR4__PI_MR14_DATA_F0_0__REG DENALI_PI_276 +#define LPDDR4__PI_MR14_DATA_F0_0__FLD LPDDR4__DENALI_PI_276__PI_MR14_DATA_F0_0 + +#define LPDDR4__DENALI_PI_276__PI_MR22_DATA_F0_0_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_276__PI_MR22_DATA_F0_0_SHIFT 16U +#define LPDDR4__DENALI_PI_276__PI_MR22_DATA_F0_0_WIDTH 8U +#define LPDDR4__PI_MR22_DATA_F0_0__REG DENALI_PI_276 +#define LPDDR4__PI_MR22_DATA_F0_0__FLD LPDDR4__DENALI_PI_276__PI_MR22_DATA_F0_0 + +#define LPDDR4__DENALI_PI_276__PI_MR23_DATA_F0_0_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_276__PI_MR23_DATA_F0_0_SHIFT 24U +#define LPDDR4__DENALI_PI_276__PI_MR23_DATA_F0_0_WIDTH 8U +#define LPDDR4__PI_MR23_DATA_F0_0__REG DENALI_PI_276 +#define LPDDR4__PI_MR23_DATA_F0_0__FLD LPDDR4__DENALI_PI_276__PI_MR23_DATA_F0_0 + +#define LPDDR4__DENALI_PI_277_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_277_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_277__PI_MR1_DATA_F1_0_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_277__PI_MR1_DATA_F1_0_SHIFT 0U +#define LPDDR4__DENALI_PI_277__PI_MR1_DATA_F1_0_WIDTH 8U +#define LPDDR4__PI_MR1_DATA_F1_0__REG DENALI_PI_277 +#define LPDDR4__PI_MR1_DATA_F1_0__FLD LPDDR4__DENALI_PI_277__PI_MR1_DATA_F1_0 + +#define LPDDR4__DENALI_PI_277__PI_MR2_DATA_F1_0_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_277__PI_MR2_DATA_F1_0_SHIFT 8U +#define LPDDR4__DENALI_PI_277__PI_MR2_DATA_F1_0_WIDTH 8U +#define LPDDR4__PI_MR2_DATA_F1_0__REG DENALI_PI_277 +#define LPDDR4__PI_MR2_DATA_F1_0__FLD LPDDR4__DENALI_PI_277__PI_MR2_DATA_F1_0 + +#define LPDDR4__DENALI_PI_277__PI_MR3_DATA_F1_0_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_277__PI_MR3_DATA_F1_0_SHIFT 16U +#define LPDDR4__DENALI_PI_277__PI_MR3_DATA_F1_0_WIDTH 8U +#define LPDDR4__PI_MR3_DATA_F1_0__REG DENALI_PI_277 +#define LPDDR4__PI_MR3_DATA_F1_0__FLD LPDDR4__DENALI_PI_277__PI_MR3_DATA_F1_0 + +#define LPDDR4__DENALI_PI_277__PI_MR11_DATA_F1_0_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_277__PI_MR11_DATA_F1_0_SHIFT 24U +#define LPDDR4__DENALI_PI_277__PI_MR11_DATA_F1_0_WIDTH 8U +#define LPDDR4__PI_MR11_DATA_F1_0__REG DENALI_PI_277 +#define LPDDR4__PI_MR11_DATA_F1_0__FLD LPDDR4__DENALI_PI_277__PI_MR11_DATA_F1_0 + +#define LPDDR4__DENALI_PI_278_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_278_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_278__PI_MR12_DATA_F1_0_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_278__PI_MR12_DATA_F1_0_SHIFT 0U +#define LPDDR4__DENALI_PI_278__PI_MR12_DATA_F1_0_WIDTH 8U +#define LPDDR4__PI_MR12_DATA_F1_0__REG DENALI_PI_278 +#define LPDDR4__PI_MR12_DATA_F1_0__FLD LPDDR4__DENALI_PI_278__PI_MR12_DATA_F1_0 + +#define LPDDR4__DENALI_PI_278__PI_MR14_DATA_F1_0_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_278__PI_MR14_DATA_F1_0_SHIFT 8U +#define LPDDR4__DENALI_PI_278__PI_MR14_DATA_F1_0_WIDTH 8U +#define LPDDR4__PI_MR14_DATA_F1_0__REG DENALI_PI_278 +#define LPDDR4__PI_MR14_DATA_F1_0__FLD LPDDR4__DENALI_PI_278__PI_MR14_DATA_F1_0 + +#define LPDDR4__DENALI_PI_278__PI_MR22_DATA_F1_0_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_278__PI_MR22_DATA_F1_0_SHIFT 16U +#define LPDDR4__DENALI_PI_278__PI_MR22_DATA_F1_0_WIDTH 8U +#define LPDDR4__PI_MR22_DATA_F1_0__REG DENALI_PI_278 +#define LPDDR4__PI_MR22_DATA_F1_0__FLD LPDDR4__DENALI_PI_278__PI_MR22_DATA_F1_0 + +#define LPDDR4__DENALI_PI_278__PI_MR23_DATA_F1_0_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_278__PI_MR23_DATA_F1_0_SHIFT 24U +#define LPDDR4__DENALI_PI_278__PI_MR23_DATA_F1_0_WIDTH 8U +#define LPDDR4__PI_MR23_DATA_F1_0__REG DENALI_PI_278 +#define LPDDR4__PI_MR23_DATA_F1_0__FLD LPDDR4__DENALI_PI_278__PI_MR23_DATA_F1_0 + +#define LPDDR4__DENALI_PI_279_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_279_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_279__PI_MR1_DATA_F2_0_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_279__PI_MR1_DATA_F2_0_SHIFT 0U +#define LPDDR4__DENALI_PI_279__PI_MR1_DATA_F2_0_WIDTH 8U +#define LPDDR4__PI_MR1_DATA_F2_0__REG DENALI_PI_279 +#define LPDDR4__PI_MR1_DATA_F2_0__FLD LPDDR4__DENALI_PI_279__PI_MR1_DATA_F2_0 + +#define LPDDR4__DENALI_PI_279__PI_MR2_DATA_F2_0_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_279__PI_MR2_DATA_F2_0_SHIFT 8U +#define LPDDR4__DENALI_PI_279__PI_MR2_DATA_F2_0_WIDTH 8U +#define LPDDR4__PI_MR2_DATA_F2_0__REG DENALI_PI_279 +#define LPDDR4__PI_MR2_DATA_F2_0__FLD LPDDR4__DENALI_PI_279__PI_MR2_DATA_F2_0 + +#define LPDDR4__DENALI_PI_279__PI_MR3_DATA_F2_0_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_279__PI_MR3_DATA_F2_0_SHIFT 16U +#define LPDDR4__DENALI_PI_279__PI_MR3_DATA_F2_0_WIDTH 8U +#define LPDDR4__PI_MR3_DATA_F2_0__REG DENALI_PI_279 +#define LPDDR4__PI_MR3_DATA_F2_0__FLD LPDDR4__DENALI_PI_279__PI_MR3_DATA_F2_0 + +#define LPDDR4__DENALI_PI_279__PI_MR11_DATA_F2_0_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_279__PI_MR11_DATA_F2_0_SHIFT 24U +#define LPDDR4__DENALI_PI_279__PI_MR11_DATA_F2_0_WIDTH 8U +#define LPDDR4__PI_MR11_DATA_F2_0__REG DENALI_PI_279 +#define LPDDR4__PI_MR11_DATA_F2_0__FLD LPDDR4__DENALI_PI_279__PI_MR11_DATA_F2_0 + +#define LPDDR4__DENALI_PI_280_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_280_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_280__PI_MR12_DATA_F2_0_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_280__PI_MR12_DATA_F2_0_SHIFT 0U +#define LPDDR4__DENALI_PI_280__PI_MR12_DATA_F2_0_WIDTH 8U +#define LPDDR4__PI_MR12_DATA_F2_0__REG DENALI_PI_280 +#define LPDDR4__PI_MR12_DATA_F2_0__FLD LPDDR4__DENALI_PI_280__PI_MR12_DATA_F2_0 + +#define LPDDR4__DENALI_PI_280__PI_MR14_DATA_F2_0_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_280__PI_MR14_DATA_F2_0_SHIFT 8U +#define LPDDR4__DENALI_PI_280__PI_MR14_DATA_F2_0_WIDTH 8U +#define LPDDR4__PI_MR14_DATA_F2_0__REG DENALI_PI_280 +#define LPDDR4__PI_MR14_DATA_F2_0__FLD LPDDR4__DENALI_PI_280__PI_MR14_DATA_F2_0 + +#define LPDDR4__DENALI_PI_280__PI_MR22_DATA_F2_0_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_280__PI_MR22_DATA_F2_0_SHIFT 16U +#define LPDDR4__DENALI_PI_280__PI_MR22_DATA_F2_0_WIDTH 8U +#define LPDDR4__PI_MR22_DATA_F2_0__REG DENALI_PI_280 +#define LPDDR4__PI_MR22_DATA_F2_0__FLD LPDDR4__DENALI_PI_280__PI_MR22_DATA_F2_0 + +#define LPDDR4__DENALI_PI_280__PI_MR23_DATA_F2_0_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_280__PI_MR23_DATA_F2_0_SHIFT 24U +#define LPDDR4__DENALI_PI_280__PI_MR23_DATA_F2_0_WIDTH 8U +#define LPDDR4__PI_MR23_DATA_F2_0__REG DENALI_PI_280 +#define LPDDR4__PI_MR23_DATA_F2_0__FLD LPDDR4__DENALI_PI_280__PI_MR23_DATA_F2_0 + +#define LPDDR4__DENALI_PI_281_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_281_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_281__PI_MR1_DATA_F0_1_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_281__PI_MR1_DATA_F0_1_SHIFT 0U +#define LPDDR4__DENALI_PI_281__PI_MR1_DATA_F0_1_WIDTH 8U +#define LPDDR4__PI_MR1_DATA_F0_1__REG DENALI_PI_281 +#define LPDDR4__PI_MR1_DATA_F0_1__FLD LPDDR4__DENALI_PI_281__PI_MR1_DATA_F0_1 + +#define LPDDR4__DENALI_PI_281__PI_MR2_DATA_F0_1_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_281__PI_MR2_DATA_F0_1_SHIFT 8U +#define LPDDR4__DENALI_PI_281__PI_MR2_DATA_F0_1_WIDTH 8U +#define LPDDR4__PI_MR2_DATA_F0_1__REG DENALI_PI_281 +#define LPDDR4__PI_MR2_DATA_F0_1__FLD LPDDR4__DENALI_PI_281__PI_MR2_DATA_F0_1 + +#define LPDDR4__DENALI_PI_281__PI_MR3_DATA_F0_1_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_281__PI_MR3_DATA_F0_1_SHIFT 16U +#define LPDDR4__DENALI_PI_281__PI_MR3_DATA_F0_1_WIDTH 8U +#define LPDDR4__PI_MR3_DATA_F0_1__REG DENALI_PI_281 +#define LPDDR4__PI_MR3_DATA_F0_1__FLD LPDDR4__DENALI_PI_281__PI_MR3_DATA_F0_1 + +#define LPDDR4__DENALI_PI_281__PI_MR11_DATA_F0_1_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_281__PI_MR11_DATA_F0_1_SHIFT 24U +#define LPDDR4__DENALI_PI_281__PI_MR11_DATA_F0_1_WIDTH 8U +#define LPDDR4__PI_MR11_DATA_F0_1__REG DENALI_PI_281 +#define LPDDR4__PI_MR11_DATA_F0_1__FLD LPDDR4__DENALI_PI_281__PI_MR11_DATA_F0_1 + +#define LPDDR4__DENALI_PI_282_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_282_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_282__PI_MR12_DATA_F0_1_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_282__PI_MR12_DATA_F0_1_SHIFT 0U +#define LPDDR4__DENALI_PI_282__PI_MR12_DATA_F0_1_WIDTH 8U +#define LPDDR4__PI_MR12_DATA_F0_1__REG DENALI_PI_282 +#define LPDDR4__PI_MR12_DATA_F0_1__FLD LPDDR4__DENALI_PI_282__PI_MR12_DATA_F0_1 + +#define LPDDR4__DENALI_PI_282__PI_MR14_DATA_F0_1_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_282__PI_MR14_DATA_F0_1_SHIFT 8U +#define LPDDR4__DENALI_PI_282__PI_MR14_DATA_F0_1_WIDTH 8U +#define LPDDR4__PI_MR14_DATA_F0_1__REG DENALI_PI_282 +#define LPDDR4__PI_MR14_DATA_F0_1__FLD LPDDR4__DENALI_PI_282__PI_MR14_DATA_F0_1 + +#define LPDDR4__DENALI_PI_282__PI_MR22_DATA_F0_1_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_282__PI_MR22_DATA_F0_1_SHIFT 16U +#define LPDDR4__DENALI_PI_282__PI_MR22_DATA_F0_1_WIDTH 8U +#define LPDDR4__PI_MR22_DATA_F0_1__REG DENALI_PI_282 +#define LPDDR4__PI_MR22_DATA_F0_1__FLD LPDDR4__DENALI_PI_282__PI_MR22_DATA_F0_1 + +#define LPDDR4__DENALI_PI_282__PI_MR23_DATA_F0_1_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_282__PI_MR23_DATA_F0_1_SHIFT 24U +#define LPDDR4__DENALI_PI_282__PI_MR23_DATA_F0_1_WIDTH 8U +#define LPDDR4__PI_MR23_DATA_F0_1__REG DENALI_PI_282 +#define LPDDR4__PI_MR23_DATA_F0_1__FLD LPDDR4__DENALI_PI_282__PI_MR23_DATA_F0_1 + +#define LPDDR4__DENALI_PI_283_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_283_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_283__PI_MR1_DATA_F1_1_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_283__PI_MR1_DATA_F1_1_SHIFT 0U +#define LPDDR4__DENALI_PI_283__PI_MR1_DATA_F1_1_WIDTH 8U +#define LPDDR4__PI_MR1_DATA_F1_1__REG DENALI_PI_283 +#define LPDDR4__PI_MR1_DATA_F1_1__FLD LPDDR4__DENALI_PI_283__PI_MR1_DATA_F1_1 + +#define LPDDR4__DENALI_PI_283__PI_MR2_DATA_F1_1_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_283__PI_MR2_DATA_F1_1_SHIFT 8U +#define LPDDR4__DENALI_PI_283__PI_MR2_DATA_F1_1_WIDTH 8U +#define LPDDR4__PI_MR2_DATA_F1_1__REG DENALI_PI_283 +#define LPDDR4__PI_MR2_DATA_F1_1__FLD LPDDR4__DENALI_PI_283__PI_MR2_DATA_F1_1 + +#define LPDDR4__DENALI_PI_283__PI_MR3_DATA_F1_1_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_283__PI_MR3_DATA_F1_1_SHIFT 16U +#define LPDDR4__DENALI_PI_283__PI_MR3_DATA_F1_1_WIDTH 8U +#define LPDDR4__PI_MR3_DATA_F1_1__REG DENALI_PI_283 +#define LPDDR4__PI_MR3_DATA_F1_1__FLD LPDDR4__DENALI_PI_283__PI_MR3_DATA_F1_1 + +#define LPDDR4__DENALI_PI_283__PI_MR11_DATA_F1_1_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_283__PI_MR11_DATA_F1_1_SHIFT 24U +#define LPDDR4__DENALI_PI_283__PI_MR11_DATA_F1_1_WIDTH 8U +#define LPDDR4__PI_MR11_DATA_F1_1__REG DENALI_PI_283 +#define LPDDR4__PI_MR11_DATA_F1_1__FLD LPDDR4__DENALI_PI_283__PI_MR11_DATA_F1_1 + +#define LPDDR4__DENALI_PI_284_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_284_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_284__PI_MR12_DATA_F1_1_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_284__PI_MR12_DATA_F1_1_SHIFT 0U +#define LPDDR4__DENALI_PI_284__PI_MR12_DATA_F1_1_WIDTH 8U +#define LPDDR4__PI_MR12_DATA_F1_1__REG DENALI_PI_284 +#define LPDDR4__PI_MR12_DATA_F1_1__FLD LPDDR4__DENALI_PI_284__PI_MR12_DATA_F1_1 + +#define LPDDR4__DENALI_PI_284__PI_MR14_DATA_F1_1_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_284__PI_MR14_DATA_F1_1_SHIFT 8U +#define LPDDR4__DENALI_PI_284__PI_MR14_DATA_F1_1_WIDTH 8U +#define LPDDR4__PI_MR14_DATA_F1_1__REG DENALI_PI_284 +#define LPDDR4__PI_MR14_DATA_F1_1__FLD LPDDR4__DENALI_PI_284__PI_MR14_DATA_F1_1 + +#define LPDDR4__DENALI_PI_284__PI_MR22_DATA_F1_1_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_284__PI_MR22_DATA_F1_1_SHIFT 16U +#define LPDDR4__DENALI_PI_284__PI_MR22_DATA_F1_1_WIDTH 8U +#define LPDDR4__PI_MR22_DATA_F1_1__REG DENALI_PI_284 +#define LPDDR4__PI_MR22_DATA_F1_1__FLD LPDDR4__DENALI_PI_284__PI_MR22_DATA_F1_1 + +#define LPDDR4__DENALI_PI_284__PI_MR23_DATA_F1_1_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_284__PI_MR23_DATA_F1_1_SHIFT 24U +#define LPDDR4__DENALI_PI_284__PI_MR23_DATA_F1_1_WIDTH 8U +#define LPDDR4__PI_MR23_DATA_F1_1__REG DENALI_PI_284 +#define LPDDR4__PI_MR23_DATA_F1_1__FLD LPDDR4__DENALI_PI_284__PI_MR23_DATA_F1_1 + +#define LPDDR4__DENALI_PI_285_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_285_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_285__PI_MR1_DATA_F2_1_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_285__PI_MR1_DATA_F2_1_SHIFT 0U +#define LPDDR4__DENALI_PI_285__PI_MR1_DATA_F2_1_WIDTH 8U +#define LPDDR4__PI_MR1_DATA_F2_1__REG DENALI_PI_285 +#define LPDDR4__PI_MR1_DATA_F2_1__FLD LPDDR4__DENALI_PI_285__PI_MR1_DATA_F2_1 + +#define LPDDR4__DENALI_PI_285__PI_MR2_DATA_F2_1_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_285__PI_MR2_DATA_F2_1_SHIFT 8U +#define LPDDR4__DENALI_PI_285__PI_MR2_DATA_F2_1_WIDTH 8U +#define LPDDR4__PI_MR2_DATA_F2_1__REG DENALI_PI_285 +#define LPDDR4__PI_MR2_DATA_F2_1__FLD LPDDR4__DENALI_PI_285__PI_MR2_DATA_F2_1 + +#define LPDDR4__DENALI_PI_285__PI_MR3_DATA_F2_1_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_285__PI_MR3_DATA_F2_1_SHIFT 16U +#define LPDDR4__DENALI_PI_285__PI_MR3_DATA_F2_1_WIDTH 8U +#define LPDDR4__PI_MR3_DATA_F2_1__REG DENALI_PI_285 +#define LPDDR4__PI_MR3_DATA_F2_1__FLD LPDDR4__DENALI_PI_285__PI_MR3_DATA_F2_1 + +#define LPDDR4__DENALI_PI_285__PI_MR11_DATA_F2_1_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_285__PI_MR11_DATA_F2_1_SHIFT 24U +#define LPDDR4__DENALI_PI_285__PI_MR11_DATA_F2_1_WIDTH 8U +#define LPDDR4__PI_MR11_DATA_F2_1__REG DENALI_PI_285 +#define LPDDR4__PI_MR11_DATA_F2_1__FLD LPDDR4__DENALI_PI_285__PI_MR11_DATA_F2_1 + +#define LPDDR4__DENALI_PI_286_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_286_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_286__PI_MR12_DATA_F2_1_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_286__PI_MR12_DATA_F2_1_SHIFT 0U +#define LPDDR4__DENALI_PI_286__PI_MR12_DATA_F2_1_WIDTH 8U +#define LPDDR4__PI_MR12_DATA_F2_1__REG DENALI_PI_286 +#define LPDDR4__PI_MR12_DATA_F2_1__FLD LPDDR4__DENALI_PI_286__PI_MR12_DATA_F2_1 + +#define LPDDR4__DENALI_PI_286__PI_MR14_DATA_F2_1_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_286__PI_MR14_DATA_F2_1_SHIFT 8U +#define LPDDR4__DENALI_PI_286__PI_MR14_DATA_F2_1_WIDTH 8U +#define LPDDR4__PI_MR14_DATA_F2_1__REG DENALI_PI_286 +#define LPDDR4__PI_MR14_DATA_F2_1__FLD LPDDR4__DENALI_PI_286__PI_MR14_DATA_F2_1 + +#define LPDDR4__DENALI_PI_286__PI_MR22_DATA_F2_1_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_286__PI_MR22_DATA_F2_1_SHIFT 16U +#define LPDDR4__DENALI_PI_286__PI_MR22_DATA_F2_1_WIDTH 8U +#define LPDDR4__PI_MR22_DATA_F2_1__REG DENALI_PI_286 +#define LPDDR4__PI_MR22_DATA_F2_1__FLD LPDDR4__DENALI_PI_286__PI_MR22_DATA_F2_1 + +#define LPDDR4__DENALI_PI_286__PI_MR23_DATA_F2_1_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_286__PI_MR23_DATA_F2_1_SHIFT 24U +#define LPDDR4__DENALI_PI_286__PI_MR23_DATA_F2_1_WIDTH 8U +#define LPDDR4__PI_MR23_DATA_F2_1__REG DENALI_PI_286 +#define LPDDR4__PI_MR23_DATA_F2_1__FLD LPDDR4__DENALI_PI_286__PI_MR23_DATA_F2_1 + +#define LPDDR4__DENALI_PI_287_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_287_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_287__PI_MR1_DATA_F0_2_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_287__PI_MR1_DATA_F0_2_SHIFT 0U +#define LPDDR4__DENALI_PI_287__PI_MR1_DATA_F0_2_WIDTH 8U +#define LPDDR4__PI_MR1_DATA_F0_2__REG DENALI_PI_287 +#define LPDDR4__PI_MR1_DATA_F0_2__FLD LPDDR4__DENALI_PI_287__PI_MR1_DATA_F0_2 + +#define LPDDR4__DENALI_PI_287__PI_MR2_DATA_F0_2_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_287__PI_MR2_DATA_F0_2_SHIFT 8U +#define LPDDR4__DENALI_PI_287__PI_MR2_DATA_F0_2_WIDTH 8U +#define LPDDR4__PI_MR2_DATA_F0_2__REG DENALI_PI_287 +#define LPDDR4__PI_MR2_DATA_F0_2__FLD LPDDR4__DENALI_PI_287__PI_MR2_DATA_F0_2 + +#define LPDDR4__DENALI_PI_287__PI_MR3_DATA_F0_2_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_287__PI_MR3_DATA_F0_2_SHIFT 16U +#define LPDDR4__DENALI_PI_287__PI_MR3_DATA_F0_2_WIDTH 8U +#define LPDDR4__PI_MR3_DATA_F0_2__REG DENALI_PI_287 +#define LPDDR4__PI_MR3_DATA_F0_2__FLD LPDDR4__DENALI_PI_287__PI_MR3_DATA_F0_2 + +#define LPDDR4__DENALI_PI_287__PI_MR11_DATA_F0_2_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_287__PI_MR11_DATA_F0_2_SHIFT 24U +#define LPDDR4__DENALI_PI_287__PI_MR11_DATA_F0_2_WIDTH 8U +#define LPDDR4__PI_MR11_DATA_F0_2__REG DENALI_PI_287 +#define LPDDR4__PI_MR11_DATA_F0_2__FLD LPDDR4__DENALI_PI_287__PI_MR11_DATA_F0_2 + +#define LPDDR4__DENALI_PI_288_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_288_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_288__PI_MR12_DATA_F0_2_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_288__PI_MR12_DATA_F0_2_SHIFT 0U +#define LPDDR4__DENALI_PI_288__PI_MR12_DATA_F0_2_WIDTH 8U +#define LPDDR4__PI_MR12_DATA_F0_2__REG DENALI_PI_288 +#define LPDDR4__PI_MR12_DATA_F0_2__FLD LPDDR4__DENALI_PI_288__PI_MR12_DATA_F0_2 + +#define LPDDR4__DENALI_PI_288__PI_MR14_DATA_F0_2_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_288__PI_MR14_DATA_F0_2_SHIFT 8U +#define LPDDR4__DENALI_PI_288__PI_MR14_DATA_F0_2_WIDTH 8U +#define LPDDR4__PI_MR14_DATA_F0_2__REG DENALI_PI_288 +#define LPDDR4__PI_MR14_DATA_F0_2__FLD LPDDR4__DENALI_PI_288__PI_MR14_DATA_F0_2 + +#define LPDDR4__DENALI_PI_288__PI_MR22_DATA_F0_2_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_288__PI_MR22_DATA_F0_2_SHIFT 16U +#define LPDDR4__DENALI_PI_288__PI_MR22_DATA_F0_2_WIDTH 8U +#define LPDDR4__PI_MR22_DATA_F0_2__REG DENALI_PI_288 +#define LPDDR4__PI_MR22_DATA_F0_2__FLD LPDDR4__DENALI_PI_288__PI_MR22_DATA_F0_2 + +#define LPDDR4__DENALI_PI_288__PI_MR23_DATA_F0_2_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_288__PI_MR23_DATA_F0_2_SHIFT 24U +#define LPDDR4__DENALI_PI_288__PI_MR23_DATA_F0_2_WIDTH 8U +#define LPDDR4__PI_MR23_DATA_F0_2__REG DENALI_PI_288 +#define LPDDR4__PI_MR23_DATA_F0_2__FLD LPDDR4__DENALI_PI_288__PI_MR23_DATA_F0_2 + +#define LPDDR4__DENALI_PI_289_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_289_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_289__PI_MR1_DATA_F1_2_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_289__PI_MR1_DATA_F1_2_SHIFT 0U +#define LPDDR4__DENALI_PI_289__PI_MR1_DATA_F1_2_WIDTH 8U +#define LPDDR4__PI_MR1_DATA_F1_2__REG DENALI_PI_289 +#define LPDDR4__PI_MR1_DATA_F1_2__FLD LPDDR4__DENALI_PI_289__PI_MR1_DATA_F1_2 + +#define LPDDR4__DENALI_PI_289__PI_MR2_DATA_F1_2_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_289__PI_MR2_DATA_F1_2_SHIFT 8U +#define LPDDR4__DENALI_PI_289__PI_MR2_DATA_F1_2_WIDTH 8U +#define LPDDR4__PI_MR2_DATA_F1_2__REG DENALI_PI_289 +#define LPDDR4__PI_MR2_DATA_F1_2__FLD LPDDR4__DENALI_PI_289__PI_MR2_DATA_F1_2 + +#define LPDDR4__DENALI_PI_289__PI_MR3_DATA_F1_2_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_289__PI_MR3_DATA_F1_2_SHIFT 16U +#define LPDDR4__DENALI_PI_289__PI_MR3_DATA_F1_2_WIDTH 8U +#define LPDDR4__PI_MR3_DATA_F1_2__REG DENALI_PI_289 +#define LPDDR4__PI_MR3_DATA_F1_2__FLD LPDDR4__DENALI_PI_289__PI_MR3_DATA_F1_2 + +#define LPDDR4__DENALI_PI_289__PI_MR11_DATA_F1_2_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_289__PI_MR11_DATA_F1_2_SHIFT 24U +#define LPDDR4__DENALI_PI_289__PI_MR11_DATA_F1_2_WIDTH 8U +#define LPDDR4__PI_MR11_DATA_F1_2__REG DENALI_PI_289 +#define LPDDR4__PI_MR11_DATA_F1_2__FLD LPDDR4__DENALI_PI_289__PI_MR11_DATA_F1_2 + +#define LPDDR4__DENALI_PI_290_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_290_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_290__PI_MR12_DATA_F1_2_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_290__PI_MR12_DATA_F1_2_SHIFT 0U +#define LPDDR4__DENALI_PI_290__PI_MR12_DATA_F1_2_WIDTH 8U +#define LPDDR4__PI_MR12_DATA_F1_2__REG DENALI_PI_290 +#define LPDDR4__PI_MR12_DATA_F1_2__FLD LPDDR4__DENALI_PI_290__PI_MR12_DATA_F1_2 + +#define LPDDR4__DENALI_PI_290__PI_MR14_DATA_F1_2_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_290__PI_MR14_DATA_F1_2_SHIFT 8U +#define LPDDR4__DENALI_PI_290__PI_MR14_DATA_F1_2_WIDTH 8U +#define LPDDR4__PI_MR14_DATA_F1_2__REG DENALI_PI_290 +#define LPDDR4__PI_MR14_DATA_F1_2__FLD LPDDR4__DENALI_PI_290__PI_MR14_DATA_F1_2 + +#define LPDDR4__DENALI_PI_290__PI_MR22_DATA_F1_2_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_290__PI_MR22_DATA_F1_2_SHIFT 16U +#define LPDDR4__DENALI_PI_290__PI_MR22_DATA_F1_2_WIDTH 8U +#define LPDDR4__PI_MR22_DATA_F1_2__REG DENALI_PI_290 +#define LPDDR4__PI_MR22_DATA_F1_2__FLD LPDDR4__DENALI_PI_290__PI_MR22_DATA_F1_2 + +#define LPDDR4__DENALI_PI_290__PI_MR23_DATA_F1_2_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_290__PI_MR23_DATA_F1_2_SHIFT 24U +#define LPDDR4__DENALI_PI_290__PI_MR23_DATA_F1_2_WIDTH 8U +#define LPDDR4__PI_MR23_DATA_F1_2__REG DENALI_PI_290 +#define LPDDR4__PI_MR23_DATA_F1_2__FLD LPDDR4__DENALI_PI_290__PI_MR23_DATA_F1_2 + +#define LPDDR4__DENALI_PI_291_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_291_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_291__PI_MR1_DATA_F2_2_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_291__PI_MR1_DATA_F2_2_SHIFT 0U +#define LPDDR4__DENALI_PI_291__PI_MR1_DATA_F2_2_WIDTH 8U +#define LPDDR4__PI_MR1_DATA_F2_2__REG DENALI_PI_291 +#define LPDDR4__PI_MR1_DATA_F2_2__FLD LPDDR4__DENALI_PI_291__PI_MR1_DATA_F2_2 + +#define LPDDR4__DENALI_PI_291__PI_MR2_DATA_F2_2_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_291__PI_MR2_DATA_F2_2_SHIFT 8U +#define LPDDR4__DENALI_PI_291__PI_MR2_DATA_F2_2_WIDTH 8U +#define LPDDR4__PI_MR2_DATA_F2_2__REG DENALI_PI_291 +#define LPDDR4__PI_MR2_DATA_F2_2__FLD LPDDR4__DENALI_PI_291__PI_MR2_DATA_F2_2 + +#define LPDDR4__DENALI_PI_291__PI_MR3_DATA_F2_2_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_291__PI_MR3_DATA_F2_2_SHIFT 16U +#define LPDDR4__DENALI_PI_291__PI_MR3_DATA_F2_2_WIDTH 8U +#define LPDDR4__PI_MR3_DATA_F2_2__REG DENALI_PI_291 +#define LPDDR4__PI_MR3_DATA_F2_2__FLD LPDDR4__DENALI_PI_291__PI_MR3_DATA_F2_2 + +#define LPDDR4__DENALI_PI_291__PI_MR11_DATA_F2_2_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_291__PI_MR11_DATA_F2_2_SHIFT 24U +#define LPDDR4__DENALI_PI_291__PI_MR11_DATA_F2_2_WIDTH 8U +#define LPDDR4__PI_MR11_DATA_F2_2__REG DENALI_PI_291 +#define LPDDR4__PI_MR11_DATA_F2_2__FLD LPDDR4__DENALI_PI_291__PI_MR11_DATA_F2_2 + +#define LPDDR4__DENALI_PI_292_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_292_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_292__PI_MR12_DATA_F2_2_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_292__PI_MR12_DATA_F2_2_SHIFT 0U +#define LPDDR4__DENALI_PI_292__PI_MR12_DATA_F2_2_WIDTH 8U +#define LPDDR4__PI_MR12_DATA_F2_2__REG DENALI_PI_292 +#define LPDDR4__PI_MR12_DATA_F2_2__FLD LPDDR4__DENALI_PI_292__PI_MR12_DATA_F2_2 + +#define LPDDR4__DENALI_PI_292__PI_MR14_DATA_F2_2_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_292__PI_MR14_DATA_F2_2_SHIFT 8U +#define LPDDR4__DENALI_PI_292__PI_MR14_DATA_F2_2_WIDTH 8U +#define LPDDR4__PI_MR14_DATA_F2_2__REG DENALI_PI_292 +#define LPDDR4__PI_MR14_DATA_F2_2__FLD LPDDR4__DENALI_PI_292__PI_MR14_DATA_F2_2 + +#define LPDDR4__DENALI_PI_292__PI_MR22_DATA_F2_2_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_292__PI_MR22_DATA_F2_2_SHIFT 16U +#define LPDDR4__DENALI_PI_292__PI_MR22_DATA_F2_2_WIDTH 8U +#define LPDDR4__PI_MR22_DATA_F2_2__REG DENALI_PI_292 +#define LPDDR4__PI_MR22_DATA_F2_2__FLD LPDDR4__DENALI_PI_292__PI_MR22_DATA_F2_2 + +#define LPDDR4__DENALI_PI_292__PI_MR23_DATA_F2_2_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_292__PI_MR23_DATA_F2_2_SHIFT 24U +#define LPDDR4__DENALI_PI_292__PI_MR23_DATA_F2_2_WIDTH 8U +#define LPDDR4__PI_MR23_DATA_F2_2__REG DENALI_PI_292 +#define LPDDR4__PI_MR23_DATA_F2_2__FLD LPDDR4__DENALI_PI_292__PI_MR23_DATA_F2_2 + +#define LPDDR4__DENALI_PI_293_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_293_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_293__PI_MR1_DATA_F0_3_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_293__PI_MR1_DATA_F0_3_SHIFT 0U +#define LPDDR4__DENALI_PI_293__PI_MR1_DATA_F0_3_WIDTH 8U +#define LPDDR4__PI_MR1_DATA_F0_3__REG DENALI_PI_293 +#define LPDDR4__PI_MR1_DATA_F0_3__FLD LPDDR4__DENALI_PI_293__PI_MR1_DATA_F0_3 + +#define LPDDR4__DENALI_PI_293__PI_MR2_DATA_F0_3_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_293__PI_MR2_DATA_F0_3_SHIFT 8U +#define LPDDR4__DENALI_PI_293__PI_MR2_DATA_F0_3_WIDTH 8U +#define LPDDR4__PI_MR2_DATA_F0_3__REG DENALI_PI_293 +#define LPDDR4__PI_MR2_DATA_F0_3__FLD LPDDR4__DENALI_PI_293__PI_MR2_DATA_F0_3 + +#define LPDDR4__DENALI_PI_293__PI_MR3_DATA_F0_3_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_293__PI_MR3_DATA_F0_3_SHIFT 16U +#define LPDDR4__DENALI_PI_293__PI_MR3_DATA_F0_3_WIDTH 8U +#define LPDDR4__PI_MR3_DATA_F0_3__REG DENALI_PI_293 +#define LPDDR4__PI_MR3_DATA_F0_3__FLD LPDDR4__DENALI_PI_293__PI_MR3_DATA_F0_3 + +#define LPDDR4__DENALI_PI_293__PI_MR11_DATA_F0_3_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_293__PI_MR11_DATA_F0_3_SHIFT 24U +#define LPDDR4__DENALI_PI_293__PI_MR11_DATA_F0_3_WIDTH 8U +#define LPDDR4__PI_MR11_DATA_F0_3__REG DENALI_PI_293 +#define LPDDR4__PI_MR11_DATA_F0_3__FLD LPDDR4__DENALI_PI_293__PI_MR11_DATA_F0_3 + +#define LPDDR4__DENALI_PI_294_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_294_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_294__PI_MR12_DATA_F0_3_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_294__PI_MR12_DATA_F0_3_SHIFT 0U +#define LPDDR4__DENALI_PI_294__PI_MR12_DATA_F0_3_WIDTH 8U +#define LPDDR4__PI_MR12_DATA_F0_3__REG DENALI_PI_294 +#define LPDDR4__PI_MR12_DATA_F0_3__FLD LPDDR4__DENALI_PI_294__PI_MR12_DATA_F0_3 + +#define LPDDR4__DENALI_PI_294__PI_MR14_DATA_F0_3_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_294__PI_MR14_DATA_F0_3_SHIFT 8U +#define LPDDR4__DENALI_PI_294__PI_MR14_DATA_F0_3_WIDTH 8U +#define LPDDR4__PI_MR14_DATA_F0_3__REG DENALI_PI_294 +#define LPDDR4__PI_MR14_DATA_F0_3__FLD LPDDR4__DENALI_PI_294__PI_MR14_DATA_F0_3 + +#define LPDDR4__DENALI_PI_294__PI_MR22_DATA_F0_3_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_294__PI_MR22_DATA_F0_3_SHIFT 16U +#define LPDDR4__DENALI_PI_294__PI_MR22_DATA_F0_3_WIDTH 8U +#define LPDDR4__PI_MR22_DATA_F0_3__REG DENALI_PI_294 +#define LPDDR4__PI_MR22_DATA_F0_3__FLD LPDDR4__DENALI_PI_294__PI_MR22_DATA_F0_3 + +#define LPDDR4__DENALI_PI_294__PI_MR23_DATA_F0_3_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_294__PI_MR23_DATA_F0_3_SHIFT 24U +#define LPDDR4__DENALI_PI_294__PI_MR23_DATA_F0_3_WIDTH 8U +#define LPDDR4__PI_MR23_DATA_F0_3__REG DENALI_PI_294 +#define LPDDR4__PI_MR23_DATA_F0_3__FLD LPDDR4__DENALI_PI_294__PI_MR23_DATA_F0_3 + +#define LPDDR4__DENALI_PI_295_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_295_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_295__PI_MR1_DATA_F1_3_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_295__PI_MR1_DATA_F1_3_SHIFT 0U +#define LPDDR4__DENALI_PI_295__PI_MR1_DATA_F1_3_WIDTH 8U +#define LPDDR4__PI_MR1_DATA_F1_3__REG DENALI_PI_295 +#define LPDDR4__PI_MR1_DATA_F1_3__FLD LPDDR4__DENALI_PI_295__PI_MR1_DATA_F1_3 + +#define LPDDR4__DENALI_PI_295__PI_MR2_DATA_F1_3_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_295__PI_MR2_DATA_F1_3_SHIFT 8U +#define LPDDR4__DENALI_PI_295__PI_MR2_DATA_F1_3_WIDTH 8U +#define LPDDR4__PI_MR2_DATA_F1_3__REG DENALI_PI_295 +#define LPDDR4__PI_MR2_DATA_F1_3__FLD LPDDR4__DENALI_PI_295__PI_MR2_DATA_F1_3 + +#define LPDDR4__DENALI_PI_295__PI_MR3_DATA_F1_3_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_295__PI_MR3_DATA_F1_3_SHIFT 16U +#define LPDDR4__DENALI_PI_295__PI_MR3_DATA_F1_3_WIDTH 8U +#define LPDDR4__PI_MR3_DATA_F1_3__REG DENALI_PI_295 +#define LPDDR4__PI_MR3_DATA_F1_3__FLD LPDDR4__DENALI_PI_295__PI_MR3_DATA_F1_3 + +#define LPDDR4__DENALI_PI_295__PI_MR11_DATA_F1_3_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_295__PI_MR11_DATA_F1_3_SHIFT 24U +#define LPDDR4__DENALI_PI_295__PI_MR11_DATA_F1_3_WIDTH 8U +#define LPDDR4__PI_MR11_DATA_F1_3__REG DENALI_PI_295 +#define LPDDR4__PI_MR11_DATA_F1_3__FLD LPDDR4__DENALI_PI_295__PI_MR11_DATA_F1_3 + +#define LPDDR4__DENALI_PI_296_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_296_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_296__PI_MR12_DATA_F1_3_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_296__PI_MR12_DATA_F1_3_SHIFT 0U +#define LPDDR4__DENALI_PI_296__PI_MR12_DATA_F1_3_WIDTH 8U +#define LPDDR4__PI_MR12_DATA_F1_3__REG DENALI_PI_296 +#define LPDDR4__PI_MR12_DATA_F1_3__FLD LPDDR4__DENALI_PI_296__PI_MR12_DATA_F1_3 + +#define LPDDR4__DENALI_PI_296__PI_MR14_DATA_F1_3_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_296__PI_MR14_DATA_F1_3_SHIFT 8U +#define LPDDR4__DENALI_PI_296__PI_MR14_DATA_F1_3_WIDTH 8U +#define LPDDR4__PI_MR14_DATA_F1_3__REG DENALI_PI_296 +#define LPDDR4__PI_MR14_DATA_F1_3__FLD LPDDR4__DENALI_PI_296__PI_MR14_DATA_F1_3 + +#define LPDDR4__DENALI_PI_296__PI_MR22_DATA_F1_3_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_296__PI_MR22_DATA_F1_3_SHIFT 16U +#define LPDDR4__DENALI_PI_296__PI_MR22_DATA_F1_3_WIDTH 8U +#define LPDDR4__PI_MR22_DATA_F1_3__REG DENALI_PI_296 +#define LPDDR4__PI_MR22_DATA_F1_3__FLD LPDDR4__DENALI_PI_296__PI_MR22_DATA_F1_3 + +#define LPDDR4__DENALI_PI_296__PI_MR23_DATA_F1_3_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_296__PI_MR23_DATA_F1_3_SHIFT 24U +#define LPDDR4__DENALI_PI_296__PI_MR23_DATA_F1_3_WIDTH 8U +#define LPDDR4__PI_MR23_DATA_F1_3__REG DENALI_PI_296 +#define LPDDR4__PI_MR23_DATA_F1_3__FLD LPDDR4__DENALI_PI_296__PI_MR23_DATA_F1_3 + +#define LPDDR4__DENALI_PI_297_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_297_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_297__PI_MR1_DATA_F2_3_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_297__PI_MR1_DATA_F2_3_SHIFT 0U +#define LPDDR4__DENALI_PI_297__PI_MR1_DATA_F2_3_WIDTH 8U +#define LPDDR4__PI_MR1_DATA_F2_3__REG DENALI_PI_297 +#define LPDDR4__PI_MR1_DATA_F2_3__FLD LPDDR4__DENALI_PI_297__PI_MR1_DATA_F2_3 + +#define LPDDR4__DENALI_PI_297__PI_MR2_DATA_F2_3_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_297__PI_MR2_DATA_F2_3_SHIFT 8U +#define LPDDR4__DENALI_PI_297__PI_MR2_DATA_F2_3_WIDTH 8U +#define LPDDR4__PI_MR2_DATA_F2_3__REG DENALI_PI_297 +#define LPDDR4__PI_MR2_DATA_F2_3__FLD LPDDR4__DENALI_PI_297__PI_MR2_DATA_F2_3 + +#define LPDDR4__DENALI_PI_297__PI_MR3_DATA_F2_3_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_297__PI_MR3_DATA_F2_3_SHIFT 16U +#define LPDDR4__DENALI_PI_297__PI_MR3_DATA_F2_3_WIDTH 8U +#define LPDDR4__PI_MR3_DATA_F2_3__REG DENALI_PI_297 +#define LPDDR4__PI_MR3_DATA_F2_3__FLD LPDDR4__DENALI_PI_297__PI_MR3_DATA_F2_3 + +#define LPDDR4__DENALI_PI_297__PI_MR11_DATA_F2_3_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_297__PI_MR11_DATA_F2_3_SHIFT 24U +#define LPDDR4__DENALI_PI_297__PI_MR11_DATA_F2_3_WIDTH 8U +#define LPDDR4__PI_MR11_DATA_F2_3__REG DENALI_PI_297 +#define LPDDR4__PI_MR11_DATA_F2_3__FLD LPDDR4__DENALI_PI_297__PI_MR11_DATA_F2_3 + +#define LPDDR4__DENALI_PI_298_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_298_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_298__PI_MR12_DATA_F2_3_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_298__PI_MR12_DATA_F2_3_SHIFT 0U +#define LPDDR4__DENALI_PI_298__PI_MR12_DATA_F2_3_WIDTH 8U +#define LPDDR4__PI_MR12_DATA_F2_3__REG DENALI_PI_298 +#define LPDDR4__PI_MR12_DATA_F2_3__FLD LPDDR4__DENALI_PI_298__PI_MR12_DATA_F2_3 + +#define LPDDR4__DENALI_PI_298__PI_MR14_DATA_F2_3_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_298__PI_MR14_DATA_F2_3_SHIFT 8U +#define LPDDR4__DENALI_PI_298__PI_MR14_DATA_F2_3_WIDTH 8U +#define LPDDR4__PI_MR14_DATA_F2_3__REG DENALI_PI_298 +#define LPDDR4__PI_MR14_DATA_F2_3__FLD LPDDR4__DENALI_PI_298__PI_MR14_DATA_F2_3 + +#define LPDDR4__DENALI_PI_298__PI_MR22_DATA_F2_3_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_298__PI_MR22_DATA_F2_3_SHIFT 16U +#define LPDDR4__DENALI_PI_298__PI_MR22_DATA_F2_3_WIDTH 8U +#define LPDDR4__PI_MR22_DATA_F2_3__REG DENALI_PI_298 +#define LPDDR4__PI_MR22_DATA_F2_3__FLD LPDDR4__DENALI_PI_298__PI_MR22_DATA_F2_3 + +#define LPDDR4__DENALI_PI_298__PI_MR23_DATA_F2_3_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_298__PI_MR23_DATA_F2_3_SHIFT 24U +#define LPDDR4__DENALI_PI_298__PI_MR23_DATA_F2_3_WIDTH 8U +#define LPDDR4__PI_MR23_DATA_F2_3__REG DENALI_PI_298 +#define LPDDR4__PI_MR23_DATA_F2_3__FLD LPDDR4__DENALI_PI_298__PI_MR23_DATA_F2_3 + +#define LPDDR4__DENALI_PI_299_READ_MASK 0x000007FFU +#define LPDDR4__DENALI_PI_299_WRITE_MASK 0x000007FFU +#define LPDDR4__DENALI_PI_299__PI_PARITY_ERROR_REGIF_MASK 0x000007FFU +#define LPDDR4__DENALI_PI_299__PI_PARITY_ERROR_REGIF_SHIFT 0U +#define LPDDR4__DENALI_PI_299__PI_PARITY_ERROR_REGIF_WIDTH 11U +#define LPDDR4__PI_PARITY_ERROR_REGIF__REG DENALI_PI_299 +#define LPDDR4__PI_PARITY_ERROR_REGIF__FLD LPDDR4__DENALI_PI_299__PI_PARITY_ERROR_REGIF + +#endif /* REG_LPDDR4_PI_MACROS_H_ */ diff --git a/drivers/ram/k3-j721e/lpddr4_private.h b/drivers/ram/k3-j721e/lpddr4_private.h new file mode 100644 index 0000000..42c9234 --- /dev/null +++ b/drivers/ram/k3-j721e/lpddr4_private.h @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/********************************************************************** + * Copyright (C) 2012-2018 Cadence Design Systems, Inc. + * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ + ********************************************************************** + * Cadence Core Driver for LPDDR4. + ********************************************************************** + */ + +#ifndef LPDDR4_PRIV_H +#define LPDDR4_PRIV_H + +#define PRODUCT_ID (0x1046U) +#define VERSION_0 (0x54d5da40U) +#define VERSION_1 (0xc1865a1U) + +#define BIT_MASK (0x1U) +#define BYTE_MASK (0xffU) +#define NIBBLE_MASK (0xfU) + +#define WORD_SHIFT (32U) +#define WORD_MASK (0xffffffffU) +#define SLICE_WIDTH (0x100) +/* Number of Data slices */ +#define DSLICE_NUM (4U) +/*Number of Address Slices */ +#define ASLICE_NUM (1U) + +/* Number of accessible registers in each slice */ +#define DSLICE0_REG_COUNT (140U) +#define DSLICE1_REG_COUNT (140U) +#define DSLICE2_REG_COUNT (140U) +#define DSLICE3_REG_COUNT (140U) +#define ASLICE0_REG_COUNT (52U) +#define PHY_CORE_REG_COUNT (140U) + +#define CTL_OFFSET 0 +#define PI_OFFSET (((uint32_t)1) << 11) +#define PHY_OFFSET (((uint32_t)1) << 12) + +/* BIT[17] on INT_MASK_1 register. */ +#define CTL_INT_MASK_ALL ((uint32_t)LPDDR4_LOR_BITS - WORD_SHIFT) + +/* Init Error information bits */ +#define PLL_READY (0x3U) +#define IO_CALIB_DONE ((uint32_t)0x1U << 23U) +#define IO_CALIB_FIELD ((uint32_t)NIBBLE_MASK << 28U) +#define IO_CALIB_STATE ((uint32_t)0xBU << 28U) +#define RX_CAL_DONE ((uint32_t)BIT_MASK << 4U) +#define CA_TRAIN_RL (((uint32_t)BIT_MASK << 5U) | ((uint32_t)BIT_MASK << 4U)) +#define WR_LVL_STATE (((uint32_t)NIBBLE_MASK) << 13U) +#define GATE_LVL_ERROR_FIELDS (((uint32_t)BIT_MASK << 7U) | ((uint32_t)BIT_MASK << 6U)) +#define READ_LVL_ERROR_FIELDS ((((uint32_t)NIBBLE_MASK) << 28U) | (((uint32_t)BYTE_MASK) << 16U)) +#define DQ_LVL_STATUS (((uint32_t)BIT_MASK << 26U) | (((uint32_t)BYTE_MASK) << 18U)) + +#endif /* LPDDR4_PRIV_H */ diff --git a/drivers/ram/k3-j721e/lpddr4_sanity.h b/drivers/ram/k3-j721e/lpddr4_sanity.h new file mode 100644 index 0000000..0f0fc27 --- /dev/null +++ b/drivers/ram/k3-j721e/lpddr4_sanity.h @@ -0,0 +1,1165 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/********************************************************************** + * Copyright (C) 2012-2019 Cadence Design Systems, Inc. + ********************************************************************** + * WARNING: This file is auto-generated using api-generator utility. + * api-generator: 12.02.13bb8d5 + * Do not edit it manually. + ********************************************************************** + * Cadence Core Driver for LPDDR4. + ********************************************************************** + */ + +/** + * This file contains sanity API functions. The purpose of sanity functions + * is to check input parameters validity. They take the same parameters as + * original API functions and return 0 on success or EINVAL on wrong parameter + * value(s). + */ + +#ifndef LPDDR4_SANITY_H +#define LPDDR4_SANITY_H + +#include <errno.h> +#include <linux/types.h> +#include "lpddr4_if.h" + +#define CDN_EOK 0U /* no error */ + +static inline uint32_t lpddr4_configsf(const lpddr4_config *obj); +static inline uint32_t lpddr4_privatedatasf(const lpddr4_privatedata *obj); +static inline uint32_t lpddr4_reginitdatasf(const lpddr4_reginitdata *obj); + +static inline uint32_t lpddr4_sanityfunction1(const lpddr4_config* config, const uint16_t* configsize); +static inline uint32_t lpddr4_sanityfunction2(const lpddr4_privatedata* pd, const lpddr4_config* cfg); +static inline uint32_t lpddr4_sanityfunction3(const lpddr4_privatedata* pd); +static inline uint32_t lpddr4_sanityfunction4(const lpddr4_privatedata* pd, const lpddr4_regblock cpp, const uint32_t* regvalue); +static inline uint32_t lpddr4_sanityfunction5(const lpddr4_privatedata* pd, const lpddr4_regblock cpp); +static inline uint32_t lpddr4_sanityfunction6(const lpddr4_privatedata* pd, const uint64_t* mmrvalue, const uint8_t* mmrstatus); +static inline uint32_t lpddr4_sanityfunction7(const lpddr4_privatedata* pd, const uint8_t* mrwstatus); +static inline uint32_t lpddr4_sanityfunction8(const lpddr4_privatedata* pd, const lpddr4_reginitdata* regvalues); +static inline uint32_t lpddr4_sanityfunction11(const lpddr4_privatedata* pd, const lpddr4_reginitdata* regvalues); +static inline uint32_t lpddr4_sanityfunction14(const lpddr4_privatedata* pd, const uint64_t* mask); +static inline uint32_t lpddr4_sanityfunction15(const lpddr4_privatedata* pd, const uint64_t* mask); +static inline uint32_t lpddr4_sanityfunction16(const lpddr4_privatedata* pd, const lpddr4_ctlinterrupt intr, const bool* irqstatus); +static inline uint32_t lpddr4_sanityfunction17(const lpddr4_privatedata* pd, const lpddr4_ctlinterrupt intr); +static inline uint32_t lpddr4_sanityfunction18(const lpddr4_privatedata* pd, const uint32_t* mask); +static inline uint32_t lpddr4_sanityfunction20(const lpddr4_privatedata* pd, const lpddr4_phyindepinterrupt intr, const bool* irqstatus); +static inline uint32_t lpddr4_sanityfunction21(const lpddr4_privatedata* pd, const lpddr4_phyindepinterrupt intr); +static inline uint32_t lpddr4_sanityfunction22(const lpddr4_privatedata* pd, const lpddr4_debuginfo* debuginfo); +static inline uint32_t lpddr4_sanityfunction23(const lpddr4_privatedata* pd, const lpddr4_lpiwakeupparam* lpiwakeupparam, const lpddr4_ctlfspnum* fspnum, const uint32_t* cycles); +static inline uint32_t lpddr4_sanityfunction25(const lpddr4_privatedata* pd, const lpddr4_eccenable* eccparam); +static inline uint32_t lpddr4_sanityfunction26(const lpddr4_privatedata* pd, const lpddr4_eccenable* eccparam); +static inline uint32_t lpddr4_sanityfunction27(const lpddr4_privatedata* pd, const lpddr4_reducmode* mode); +static inline uint32_t lpddr4_sanityfunction28(const lpddr4_privatedata* pd, const lpddr4_reducmode* mode); +static inline uint32_t lpddr4_sanityfunction29(const lpddr4_privatedata* pd, const bool* on_off); +static inline uint32_t lpddr4_sanityfunction31(const lpddr4_privatedata* pd, const lpddr4_dbimode* mode); +static inline uint32_t lpddr4_sanityfunction32(const lpddr4_privatedata* pd, const lpddr4_ctlfspnum* fspnum, const uint32_t* cycles); + +#define lpddr4_probesf lpddr4_sanityfunction1 +#define lpddr4_initsf lpddr4_sanityfunction2 +#define lpddr4_startsf lpddr4_sanityfunction3 +#define lpddr4_readregsf lpddr4_sanityfunction4 +#define lpddr4_writeregsf lpddr4_sanityfunction5 +#define lpddr4_getmmrregistersf lpddr4_sanityfunction6 +#define lpddr4_setmmrregistersf lpddr4_sanityfunction7 +#define lpddr4_writectlconfigsf lpddr4_sanityfunction8 +#define lpddr4_writephyconfigsf lpddr4_sanityfunction8 +#define lpddr4_writephyindepconfigsf lpddr4_sanityfunction8 +#define lpddr4_readctlconfigsf lpddr4_sanityfunction11 +#define lpddr4_readphyconfigsf lpddr4_sanityfunction11 +#define lpddr4_readphyindepconfigsf lpddr4_sanityfunction11 +#define lpddr4_getctlinterruptmasksf lpddr4_sanityfunction14 +#define lpddr4_setctlinterruptmasksf lpddr4_sanityfunction15 +#define lpddr4_checkctlinterruptsf lpddr4_sanityfunction16 +#define lpddr4_ackctlinterruptsf lpddr4_sanityfunction17 +#define lpddr4_getphyindepinterruptmsf lpddr4_sanityfunction18 +#define lpddr4_setphyindepinterruptmsf lpddr4_sanityfunction18 +#define lpddr4_checkphyindepinterrupsf lpddr4_sanityfunction20 +#define lpddr4_ackphyindepinterruptsf lpddr4_sanityfunction21 +#define lpddr4_getdebuginitinfosf lpddr4_sanityfunction22 +#define lpddr4_getlpiwakeuptimesf lpddr4_sanityfunction23 +#define lpddr4_setlpiwakeuptimesf lpddr4_sanityfunction23 +#define lpddr4_geteccenablesf lpddr4_sanityfunction25 +#define lpddr4_seteccenablesf lpddr4_sanityfunction26 +#define lpddr4_getreducmodesf lpddr4_sanityfunction27 +#define lpddr4_setreducmodesf lpddr4_sanityfunction28 +#define lpddr4_getdbireadmodesf lpddr4_sanityfunction29 +#define lpddr4_getdbiwritemodesf lpddr4_sanityfunction29 +#define lpddr4_setdbimodesf lpddr4_sanityfunction31 +#define lpddr4_getrefreshratesf lpddr4_sanityfunction32 +#define lpddr4_setrefreshratesf lpddr4_sanityfunction32 +#define lpddr4_refreshperchipselectsf lpddr4_sanityfunction3 + +/** + * Function to validate struct Config + * + * @param[in] obj pointer to struct to be verified + * @returns 0 for valid + * @returns EINVAL for invalid + */ +static inline uint32_t lpddr4_configsf(const lpddr4_config *obj) +{ + uint32_t ret = 0; + + if (obj == NULL) + { + ret = EINVAL; + } + + return ret; +} + +/** + * Function to validate struct PrivateData + * + * @param[in] obj pointer to struct to be verified + * @returns 0 for valid + * @returns EINVAL for invalid + */ +static inline uint32_t lpddr4_privatedatasf(const lpddr4_privatedata *obj) +{ + uint32_t ret = 0; + + if (obj == NULL) + { + ret = EINVAL; + } + + return ret; +} + +/** + * Function to validate struct RegInitData + * + * @param[in] obj pointer to struct to be verified + * @returns 0 for valid + * @returns EINVAL for invalid + */ +static inline uint32_t lpddr4_reginitdatasf(const lpddr4_reginitdata *obj) +{ + uint32_t ret = 0; + + if (obj == NULL) + { + ret = EINVAL; + } + + return ret; +} + +/** + * A common function to check the validity of API functions with + * following parameter types + * @param[in] config Driver/hardware configuration required. + * @param[out] configSize Size of memory allocations required. + * @return 0 success + * @return EINVAL invalid parameters + */ +static inline uint32_t lpddr4_sanityfunction1(const lpddr4_config* config, const uint16_t* configsize) +{ + /* Declaring return variable */ + uint32_t ret = 0; + + if (configsize == NULL) + { + ret = EINVAL; + } + else if (lpddr4_configsf(config) == EINVAL) + { + ret = EINVAL; + } + else + { + /* + * All 'if ... else if' constructs shall be terminated with an 'else' statement + * (MISRA2012-RULE-15_7-3) + */ + } + + return ret; +} + +/** + * A common function to check the validity of API functions with + * following parameter types + * @param[in] pD Driver state info specific to this instance. + * @param[in] cfg Specifies driver/hardware configuration. + * @return 0 success + * @return EINVAL invalid parameters + */ +static inline uint32_t lpddr4_sanityfunction2(const lpddr4_privatedata* pd, const lpddr4_config* cfg) +{ + /* Declaring return variable */ + uint32_t ret = 0; + + if (lpddr4_privatedatasf(pd) == EINVAL) + { + ret = EINVAL; + } + else if (lpddr4_configsf(cfg) == EINVAL) + { + ret = EINVAL; + } + else + { + /* + * All 'if ... else if' constructs shall be terminated with an 'else' statement + * (MISRA2012-RULE-15_7-3) + */ + } + + return ret; +} + +/** + * A common function to check the validity of API functions with + * following parameter types + * @param[in] pD Driver state info specific to this instance. + * @return 0 success + * @return EINVAL invalid parameters + */ +static inline uint32_t lpddr4_sanityfunction3(const lpddr4_privatedata* pd) +{ + /* Declaring return variable */ + uint32_t ret = 0; + + if (lpddr4_privatedatasf(pd) == EINVAL) + { + ret = EINVAL; + } + + return ret; +} + +/** + * A common function to check the validity of API functions with + * following parameter types + * @param[in] pD Driver state info specific to this instance. + * @param[in] cpp Indicates whether controller, PHY or PHY Independent Module register + * @param[out] regValue Register value read + * @return 0 success + * @return EINVAL invalid parameters + */ +static inline uint32_t lpddr4_sanityfunction4(const lpddr4_privatedata* pd, const lpddr4_regblock cpp, const uint32_t* regvalue) +{ + /* Declaring return variable */ + uint32_t ret = 0; + + if (regvalue == NULL) + { + ret = EINVAL; + } + else if (lpddr4_privatedatasf(pd) == EINVAL) + { + ret = EINVAL; + } + else if ( + (cpp != LPDDR4_CTL_REGS) && + (cpp != LPDDR4_PHY_REGS) && + (cpp != LPDDR4_PHY_INDEP_REGS) + ) + { + ret = EINVAL; + } + else + { + /* + * All 'if ... else if' constructs shall be terminated with an 'else' statement + * (MISRA2012-RULE-15_7-3) + */ + } + + return ret; +} + +/** + * A common function to check the validity of API functions with + * following parameter types + * @param[in] pD Driver state info specific to this instance. + * @param[in] cpp Indicates whether controller, PHY or PHY Independent Module register + * @return 0 success + * @return EINVAL invalid parameters + */ +static inline uint32_t lpddr4_sanityfunction5(const lpddr4_privatedata* pd, const lpddr4_regblock cpp) +{ + /* Declaring return variable */ + uint32_t ret = 0; + + if (lpddr4_privatedatasf(pd) == EINVAL) + { + ret = EINVAL; + } + else if ( + (cpp != LPDDR4_CTL_REGS) && + (cpp != LPDDR4_PHY_REGS) && + (cpp != LPDDR4_PHY_INDEP_REGS) + ) + { + ret = EINVAL; + } + else + { + /* + * All 'if ... else if' constructs shall be terminated with an 'else' statement + * (MISRA2012-RULE-15_7-3) + */ + } + + return ret; +} + +/** + * A common function to check the validity of API functions with + * following parameter types + * @param[in] pD Driver state info specific to this instance. + * @param[out] mmrValue Value which is read from memory mode register(mmr) for all devices. + * @param[out] mmrStatus Status of mode register read(mrr) instruction. + * @return 0 success + * @return EINVAL invalid parameters + */ +static inline uint32_t lpddr4_sanityfunction6(const lpddr4_privatedata* pd, const uint64_t* mmrvalue, const uint8_t* mmrstatus) +{ + /* Declaring return variable */ + uint32_t ret = 0; + + if (mmrvalue == NULL) + { + ret = EINVAL; + } + else if (mmrstatus == NULL) + { + ret = EINVAL; + } + else if (lpddr4_privatedatasf(pd) == EINVAL) + { + ret = EINVAL; + } + else + { + /* + * All 'if ... else if' constructs shall be terminated with an 'else' statement + * (MISRA2012-RULE-15_7-3) + */ + } + + return ret; +} + +/** + * A common function to check the validity of API functions with + * following parameter types + * @param[in] pD Driver state info specific to this instance. + * @param[out] mrwStatus Status of mode register write(mrw) instruction. + * @return 0 success + * @return EINVAL invalid parameters + */ +static inline uint32_t lpddr4_sanityfunction7(const lpddr4_privatedata* pd, const uint8_t* mrwstatus) +{ + /* Declaring return variable */ + uint32_t ret = 0; + + if (mrwstatus == NULL) + { + ret = EINVAL; + } + else if (lpddr4_privatedatasf(pd) == EINVAL) + { + ret = EINVAL; + } + else + { + /* + * All 'if ... else if' constructs shall be terminated with an 'else' statement + * (MISRA2012-RULE-15_7-3) + */ + } + + return ret; +} + +/** + * A common function to check the validity of API functions with + * following parameter types + * @param[in] pD Driver state info specific to this instance. + * @param[in] regValues Register values to be written + * @return 0 success + * @return EINVAL invalid parameters + */ +static inline uint32_t lpddr4_sanityfunction8(const lpddr4_privatedata* pd, const lpddr4_reginitdata* regvalues) +{ + /* Declaring return variable */ + uint32_t ret = 0; + + if (lpddr4_privatedatasf(pd) == EINVAL) + { + ret = EINVAL; + } + else if (lpddr4_reginitdatasf(regvalues) == EINVAL) + { + ret = EINVAL; + } + else + { + /* + * All 'if ... else if' constructs shall be terminated with an 'else' statement + * (MISRA2012-RULE-15_7-3) + */ + } + + return ret; +} + +/** + * A common function to check the validity of API functions with + * following parameter types + * @param[in] pD Driver state info specific to this instance. + * @param[out] regValues Register values which are read + * @return 0 success + * @return EINVAL invalid parameters + */ +static inline uint32_t lpddr4_sanityfunction11(const lpddr4_privatedata* pd, const lpddr4_reginitdata* regvalues) +{ + /* Declaring return variable */ + uint32_t ret = 0; + + if (regvalues == NULL) + { + ret = EINVAL; + } + else if (lpddr4_privatedatasf(pd) == EINVAL) + { + ret = EINVAL; + } + else + { + /* + * All 'if ... else if' constructs shall be terminated with an 'else' statement + * (MISRA2012-RULE-15_7-3) + */ + } + + return ret; +} + +/** + * A common function to check the validity of API functions with + * following parameter types + * @param[in] pD Driver state info specific to this instance. + * @param[out] mask Value of interrupt mask + * @return 0 success + * @return EINVAL invalid parameters + */ +static inline uint32_t lpddr4_sanityfunction14(const lpddr4_privatedata* pd, const uint64_t* mask) +{ + /* Declaring return variable */ + uint32_t ret = 0; + + if (mask == NULL) + { + ret = EINVAL; + } + else if (lpddr4_privatedatasf(pd) == EINVAL) + { + ret = EINVAL; + } + else + { + /* + * All 'if ... else if' constructs shall be terminated with an 'else' statement + * (MISRA2012-RULE-15_7-3) + */ + } + + return ret; +} + +/** + * A common function to check the validity of API functions with + * following parameter types + * @param[in] pD Driver state info specific to this instance. + * @param[in] mask Value of interrupt mask to be written + * @return 0 success + * @return EINVAL invalid parameters + */ +static inline uint32_t lpddr4_sanityfunction15(const lpddr4_privatedata* pd, const uint64_t* mask) +{ + /* Declaring return variable */ + uint32_t ret = 0; + + if (mask == NULL) + { + ret = EINVAL; + } + else if (lpddr4_privatedatasf(pd) == EINVAL) + { + ret = EINVAL; + } + else + { + /* + * All 'if ... else if' constructs shall be terminated with an 'else' statement + * (MISRA2012-RULE-15_7-3) + */ + } + + return ret; +} + +/** + * A common function to check the validity of API functions with + * following parameter types + * @param[in] pD Driver state info specific to this instance. + * @param[in] intr Interrupt to be checked + * @param[out] irqStatus Status of the interrupt, TRUE if active + * @return 0 success + * @return EINVAL invalid parameters + */ +static inline uint32_t lpddr4_sanityfunction16(const lpddr4_privatedata* pd, const lpddr4_ctlinterrupt intr, const bool* irqstatus) +{ + /* Declaring return variable */ + uint32_t ret = 0; + + if (irqstatus == NULL) + { + ret = EINVAL; + } + else if (lpddr4_privatedatasf(pd) == EINVAL) + { + ret = EINVAL; + } + else if ( + (intr != LPDDR4_RESET_DONE) && + (intr != LPDDR4_BUS_ACCESS_ERROR) && + (intr != LPDDR4_MULTIPLE_BUS_ACCESS_ERROR) && + (intr != LPDDR4_ECC_MULTIPLE_CORR_ERROR) && + (intr != LPDDR4_ECC_MULTIPLE_UNCORR_ERROR) && + (intr != LPDDR4_ECC_WRITEBACK_EXEC_ERROR) && + (intr != LPDDR4_ECC_SCRUB_DONE) && + (intr != LPDDR4_ECC_SCRUB_ERROR) && + (intr != LPDDR4_PORT_COMMAND_ERROR) && + (intr != LPDDR4_MC_INIT_DONE) && + (intr != LPDDR4_LP_DONE) && + (intr != LPDDR4_BIST_DONE) && + (intr != LPDDR4_WRAP_ERROR) && + (intr != LPDDR4_INVALID_BURST_ERROR) && + (intr != LPDDR4_RDLVL_ERROR) && + (intr != LPDDR4_RDLVL_GATE_ERROR) && + (intr != LPDDR4_WRLVL_ERROR) && + (intr != LPDDR4_CA_TRAINING_ERROR) && + (intr != LPDDR4_DFI_UPDATE_ERROR) && + (intr != LPDDR4_MRR_ERROR) && + (intr != LPDDR4_PHY_MASTER_ERROR) && + (intr != LPDDR4_WRLVL_REQ) && + (intr != LPDDR4_RDLVL_REQ) && + (intr != LPDDR4_RDLVL_GATE_REQ) && + (intr != LPDDR4_CA_TRAINING_REQ) && + (intr != LPDDR4_LEVELING_DONE) && + (intr != LPDDR4_PHY_ERROR) && + (intr != LPDDR4_MR_READ_DONE) && + (intr != LPDDR4_TEMP_CHANGE) && + (intr != LPDDR4_TEMP_ALERT) && + (intr != LPDDR4_SW_DQS_COMPLETE) && + (intr != LPDDR4_DQS_OSC_BV_UPDATED) && + (intr != LPDDR4_DQS_OSC_OVERFLOW) && + (intr != LPDDR4_DQS_OSC_VAR_OUT) && + (intr != LPDDR4_MR_WRITE_DONE) && + (intr != LPDDR4_INHIBIT_DRAM_DONE) && + (intr != LPDDR4_DFI_INIT_STATE) && + (intr != LPDDR4_DLL_RESYNC_DONE) && + (intr != LPDDR4_TDFI_TO) && + (intr != LPDDR4_DFS_DONE) && + (intr != LPDDR4_DFS_STATUS) && + (intr != LPDDR4_REFRESH_STATUS) && + (intr != LPDDR4_ZQ_STATUS) && + (intr != LPDDR4_SW_REQ_MODE) && + (intr != LPDDR4_LOR_BITS) + ) + { + ret = EINVAL; + } + else + { + /* + * All 'if ... else if' constructs shall be terminated with an 'else' statement + * (MISRA2012-RULE-15_7-3) + */ + } + + return ret; +} + +/** + * A common function to check the validity of API functions with + * following parameter types + * @param[in] pD Driver state info specific to this instance. + * @param[in] intr Interrupt to be acknowledged + * @return 0 success + * @return EINVAL invalid parameters + */ +static inline uint32_t lpddr4_sanityfunction17(const lpddr4_privatedata* pd, const lpddr4_ctlinterrupt intr) +{ + /* Declaring return variable */ + uint32_t ret = 0; + + if (lpddr4_privatedatasf(pd) == EINVAL) + { + ret = EINVAL; + } + else if ( + (intr != LPDDR4_RESET_DONE) && + (intr != LPDDR4_BUS_ACCESS_ERROR) && + (intr != LPDDR4_MULTIPLE_BUS_ACCESS_ERROR) && + (intr != LPDDR4_ECC_MULTIPLE_CORR_ERROR) && + (intr != LPDDR4_ECC_MULTIPLE_UNCORR_ERROR) && + (intr != LPDDR4_ECC_WRITEBACK_EXEC_ERROR) && + (intr != LPDDR4_ECC_SCRUB_DONE) && + (intr != LPDDR4_ECC_SCRUB_ERROR) && + (intr != LPDDR4_PORT_COMMAND_ERROR) && + (intr != LPDDR4_MC_INIT_DONE) && + (intr != LPDDR4_LP_DONE) && + (intr != LPDDR4_BIST_DONE) && + (intr != LPDDR4_WRAP_ERROR) && + (intr != LPDDR4_INVALID_BURST_ERROR) && + (intr != LPDDR4_RDLVL_ERROR) && + (intr != LPDDR4_RDLVL_GATE_ERROR) && + (intr != LPDDR4_WRLVL_ERROR) && + (intr != LPDDR4_CA_TRAINING_ERROR) && + (intr != LPDDR4_DFI_UPDATE_ERROR) && + (intr != LPDDR4_MRR_ERROR) && + (intr != LPDDR4_PHY_MASTER_ERROR) && + (intr != LPDDR4_WRLVL_REQ) && + (intr != LPDDR4_RDLVL_REQ) && + (intr != LPDDR4_RDLVL_GATE_REQ) && + (intr != LPDDR4_CA_TRAINING_REQ) && + (intr != LPDDR4_LEVELING_DONE) && + (intr != LPDDR4_PHY_ERROR) && + (intr != LPDDR4_MR_READ_DONE) && + (intr != LPDDR4_TEMP_CHANGE) && + (intr != LPDDR4_TEMP_ALERT) && + (intr != LPDDR4_SW_DQS_COMPLETE) && + (intr != LPDDR4_DQS_OSC_BV_UPDATED) && + (intr != LPDDR4_DQS_OSC_OVERFLOW) && + (intr != LPDDR4_DQS_OSC_VAR_OUT) && + (intr != LPDDR4_MR_WRITE_DONE) && + (intr != LPDDR4_INHIBIT_DRAM_DONE) && + (intr != LPDDR4_DFI_INIT_STATE) && + (intr != LPDDR4_DLL_RESYNC_DONE) && + (intr != LPDDR4_TDFI_TO) && + (intr != LPDDR4_DFS_DONE) && + (intr != LPDDR4_DFS_STATUS) && + (intr != LPDDR4_REFRESH_STATUS) && + (intr != LPDDR4_ZQ_STATUS) && + (intr != LPDDR4_SW_REQ_MODE) && + (intr != LPDDR4_LOR_BITS) + ) + { + ret = EINVAL; + } + else + { + /* + * All 'if ... else if' constructs shall be terminated with an 'else' statement + * (MISRA2012-RULE-15_7-3) + */ + } + + return ret; +} + +/** + * A common function to check the validity of API functions with + * following parameter types + * @param[in] pD Driver state info specific to this instance. + * @param[out] mask Value of interrupt mask + * @return 0 success + * @return EINVAL invalid parameters + */ +static inline uint32_t lpddr4_sanityfunction18(const lpddr4_privatedata* pd, const uint32_t* mask) +{ + /* Declaring return variable */ + uint32_t ret = 0; + + if (mask == NULL) + { + ret = EINVAL; + } + else if (lpddr4_privatedatasf(pd) == EINVAL) + { + ret = EINVAL; + } + else + { + /* + * All 'if ... else if' constructs shall be terminated with an 'else' statement + * (MISRA2012-RULE-15_7-3) + */ + } + + return ret; +} + +/** + * A common function to check the validity of API functions with + * following parameter types + * @param[in] pD Driver state info specific to this instance. + * @param[in] intr Interrupt to be checked + * @param[out] irqStatus Status of the interrupt, TRUE if active + * @return 0 success + * @return EINVAL invalid parameters + */ +static inline uint32_t lpddr4_sanityfunction20(const lpddr4_privatedata* pd, const lpddr4_phyindepinterrupt intr, const bool* irqstatus) +{ + /* Declaring return variable */ + uint32_t ret = 0; + + if (irqstatus == NULL) + { + ret = EINVAL; + } + else if (lpddr4_privatedatasf(pd) == EINVAL) + { + ret = EINVAL; + } + else if ( + (intr != LPDDR4_PHY_INDEP_INIT_DONE_BIT) && + (intr != LPDDR4_PHY_INDEP_CONTROL_ERROR_BIT) && + (intr != LPDDR4_PHY_INDEP_CA_PARITY_ERR_BIT) && + (intr != LPDDR4_PHY_INDEP_RDLVL_ERROR_BIT) && + (intr != LPDDR4_PHY_INDEP_RDLVL_GATE_ERROR_BIT) && + (intr != LPDDR4_PHY_INDEP_WRLVL_ERROR_BIT) && + (intr != LPDDR4_PHY_INDEP_CALVL_ERROR_BIT) && + (intr != LPDDR4_PHY_INDEP_WDQLVL_ERROR_BIT) && + (intr != LPDDR4_PHY_INDEP_UPDATE_ERROR_BIT) && + (intr != LPDDR4_PHY_INDEP_RDLVL_REQ_BIT) && + (intr != LPDDR4_PHY_INDEP_RDLVL_GATE_REQ_BIT) && + (intr != LPDDR4_PHY_INDEP_WRLVL_REQ_BIT) && + (intr != LPDDR4_PHY_INDEP_CALVL_REQ_BIT) && + (intr != LPDDR4_PHY_INDEP_WDQLVL_REQ_BIT) && + (intr != LPDDR4_PHY_INDEP_LVL_DONE_BIT) && + (intr != LPDDR4_PHY_INDEP_BIST_DONE_BIT) && + (intr != LPDDR4_PHY_INDEP_TDFI_INIT_TIME_OUT_BIT) && + (intr != LPDDR4_PHY_INDEP_DLL_LOCK_STATE_CHANGE_BIT) + ) + { + ret = EINVAL; + } + else + { + /* + * All 'if ... else if' constructs shall be terminated with an 'else' statement + * (MISRA2012-RULE-15_7-3) + */ + } + + return ret; +} + +/** + * A common function to check the validity of API functions with + * following parameter types + * @param[in] pD Driver state info specific to this instance. + * @param[in] intr Interrupt to be acknowledged + * @return 0 success + * @return EINVAL invalid parameters + */ +static inline uint32_t lpddr4_sanityfunction21(const lpddr4_privatedata* pd, const lpddr4_phyindepinterrupt intr) +{ + /* Declaring return variable */ + uint32_t ret = 0; + + if (lpddr4_privatedatasf(pd) == EINVAL) + { + ret = EINVAL; + } + else if ( + (intr != LPDDR4_PHY_INDEP_INIT_DONE_BIT) && + (intr != LPDDR4_PHY_INDEP_CONTROL_ERROR_BIT) && + (intr != LPDDR4_PHY_INDEP_CA_PARITY_ERR_BIT) && + (intr != LPDDR4_PHY_INDEP_RDLVL_ERROR_BIT) && + (intr != LPDDR4_PHY_INDEP_RDLVL_GATE_ERROR_BIT) && + (intr != LPDDR4_PHY_INDEP_WRLVL_ERROR_BIT) && + (intr != LPDDR4_PHY_INDEP_CALVL_ERROR_BIT) && + (intr != LPDDR4_PHY_INDEP_WDQLVL_ERROR_BIT) && + (intr != LPDDR4_PHY_INDEP_UPDATE_ERROR_BIT) && + (intr != LPDDR4_PHY_INDEP_RDLVL_REQ_BIT) && + (intr != LPDDR4_PHY_INDEP_RDLVL_GATE_REQ_BIT) && + (intr != LPDDR4_PHY_INDEP_WRLVL_REQ_BIT) && + (intr != LPDDR4_PHY_INDEP_CALVL_REQ_BIT) && + (intr != LPDDR4_PHY_INDEP_WDQLVL_REQ_BIT) && + (intr != LPDDR4_PHY_INDEP_LVL_DONE_BIT) && + (intr != LPDDR4_PHY_INDEP_BIST_DONE_BIT) && + (intr != LPDDR4_PHY_INDEP_TDFI_INIT_TIME_OUT_BIT) && + (intr != LPDDR4_PHY_INDEP_DLL_LOCK_STATE_CHANGE_BIT) + ) + { + ret = EINVAL; + } + else + { + /* + * All 'if ... else if' constructs shall be terminated with an 'else' statement + * (MISRA2012-RULE-15_7-3) + */ + } + + return ret; +} + +/** + * A common function to check the validity of API functions with + * following parameter types + * @param[in] pD Driver state info specific to this instance. + * @param[out] debugInfo status + * @return 0 success + * @return EINVAL invalid parameters + */ +static inline uint32_t lpddr4_sanityfunction22(const lpddr4_privatedata* pd, const lpddr4_debuginfo* debuginfo) +{ + /* Declaring return variable */ + uint32_t ret = 0; + + if (debuginfo == NULL) + { + ret = EINVAL; + } + else if (lpddr4_privatedatasf(pd) == EINVAL) + { + ret = EINVAL; + } + else + { + /* + * All 'if ... else if' constructs shall be terminated with an 'else' statement + * (MISRA2012-RULE-15_7-3) + */ + } + + return ret; +} + +/** + * A common function to check the validity of API functions with + * following parameter types + * @param[in] pD Driver state info specific to this instance. + * @param[in] lpiWakeUpParam LPI timing parameter + * @param[in] fspNum Frequency copy + * @param[out] cycles Timing value(in cycles) + * @return 0 success + * @return EINVAL invalid parameters + */ +static inline uint32_t lpddr4_sanityfunction23(const lpddr4_privatedata* pd, const lpddr4_lpiwakeupparam* lpiwakeupparam, const lpddr4_ctlfspnum* fspnum, const uint32_t* cycles) +{ + /* Declaring return variable */ + uint32_t ret = 0; + + if (lpiwakeupparam == NULL) + { + ret = EINVAL; + } + else if (fspnum == NULL) + { + ret = EINVAL; + } + else if (cycles == NULL) + { + ret = EINVAL; + } + else if (lpddr4_privatedatasf(pd) == EINVAL) + { + ret = EINVAL; + } + else if ( + (*lpiwakeupparam != LPDDR4_LPI_PD_WAKEUP_FN) && + (*lpiwakeupparam != LPDDR4_LPI_SR_SHORT_WAKEUP_FN) && + (*lpiwakeupparam != LPDDR4_LPI_SR_LONG_WAKEUP_FN) && + (*lpiwakeupparam != LPDDR4_LPI_SR_LONG_MCCLK_GATE_WAKEUP_FN) && + (*lpiwakeupparam != LPDDR4_LPI_SRPD_SHORT_WAKEUP_FN) && + (*lpiwakeupparam != LPDDR4_LPI_SRPD_LONG_WAKEUP_FN) && + (*lpiwakeupparam != LPDDR4_LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_FN) + ) + { + ret = EINVAL; + } + else if ( + (*fspnum != LPDDR4_FSP_0) && + (*fspnum != LPDDR4_FSP_1) && + (*fspnum != LPDDR4_FSP_2) + ) + { + ret = EINVAL; + } + else + { + /* + * All 'if ... else if' constructs shall be terminated with an 'else' statement + * (MISRA2012-RULE-15_7-3) + */ + } + + return ret; +} + +/** + * A common function to check the validity of API functions with + * following parameter types + * @param[in] pD Driver state info specific to this instance. + * @param[out] eccParam ECC parameter setting + * @return 0 success + * @return EINVAL invalid parameters + */ +static inline uint32_t lpddr4_sanityfunction25(const lpddr4_privatedata* pd, const lpddr4_eccenable* eccparam) +{ + /* Declaring return variable */ + uint32_t ret = 0; + + if (eccparam == NULL) + { + ret = EINVAL; + } + else if (lpddr4_privatedatasf(pd) == EINVAL) + { + ret = EINVAL; + } + else + { + /* + * All 'if ... else if' constructs shall be terminated with an 'else' statement + * (MISRA2012-RULE-15_7-3) + */ + } + + return ret; +} + +/** + * A common function to check the validity of API functions with + * following parameter types + * @param[in] pD Driver state info specific to this instance. + * @param[in] eccParam ECC control parameter setting + * @return 0 success + * @return EINVAL invalid parameters + */ +static inline uint32_t lpddr4_sanityfunction26(const lpddr4_privatedata* pd, const lpddr4_eccenable* eccparam) +{ + /* Declaring return variable */ + uint32_t ret = 0; + + if (eccparam == NULL) + { + ret = EINVAL; + } + else if (lpddr4_privatedatasf(pd) == EINVAL) + { + ret = EINVAL; + } + else if ( + (*eccparam != LPDDR4_ECC_DISABLED) && + (*eccparam != LPDDR4_ECC_ENABLED) && + (*eccparam != LPDDR4_ECC_ERR_DETECT) && + (*eccparam != LPDDR4_ECC_ERR_DETECT_CORRECT) + ) + { + ret = EINVAL; + } + else + { + /* + * All 'if ... else if' constructs shall be terminated with an 'else' statement + * (MISRA2012-RULE-15_7-3) + */ + } + + return ret; +} + +/** + * A common function to check the validity of API functions with + * following parameter types + * @param[in] pD Driver state info specific to this instance. + * @param[out] mode Half Datapath setting + * @return 0 success + * @return EINVAL invalid parameters + */ +static inline uint32_t lpddr4_sanityfunction27(const lpddr4_privatedata* pd, const lpddr4_reducmode* mode) +{ + /* Declaring return variable */ + uint32_t ret = 0; + + if (mode == NULL) + { + ret = EINVAL; + } + else if (lpddr4_privatedatasf(pd) == EINVAL) + { + ret = EINVAL; + } + else + { + /* + * All 'if ... else if' constructs shall be terminated with an 'else' statement + * (MISRA2012-RULE-15_7-3) + */ + } + + return ret; +} + +/** + * A common function to check the validity of API functions with + * following parameter types + * @param[in] pD Driver state info specific to this instance. + * @param[in] mode Half Datapath setting + * @return 0 success + * @return EINVAL invalid parameters + */ +static inline uint32_t lpddr4_sanityfunction28(const lpddr4_privatedata* pd, const lpddr4_reducmode* mode) +{ + /* Declaring return variable */ + uint32_t ret = 0; + + if (mode == NULL) + { + ret = EINVAL; + } + else if (lpddr4_privatedatasf(pd) == EINVAL) + { + ret = EINVAL; + } + else if ( + (*mode != LPDDR4_REDUC_ON) && + (*mode != LPDDR4_REDUC_OFF) + ) + { + ret = EINVAL; + } + else + { + /* + * All 'if ... else if' constructs shall be terminated with an 'else' statement + * (MISRA2012-RULE-15_7-3) + */ + } + + return ret; +} + +/** + * A common function to check the validity of API functions with + * following parameter types + * @param[in] pD Driver state info specific to this instance. + * @param[out] on_off DBI read value + * @return 0 success + * @return EINVAL invalid parameters + */ +static inline uint32_t lpddr4_sanityfunction29(const lpddr4_privatedata* pd, const bool* on_off) +{ + /* Declaring return variable */ + uint32_t ret = 0; + + if (on_off == NULL) + { + ret = EINVAL; + } + else if (lpddr4_privatedatasf(pd) == EINVAL) + { + ret = EINVAL; + } + else + { + /* + * All 'if ... else if' constructs shall be terminated with an 'else' statement + * (MISRA2012-RULE-15_7-3) + */ + } + + return ret; +} + +/** + * A common function to check the validity of API functions with + * following parameter types + * @param[in] pD Driver state info specific to this instance. + * @param[in] mode status + * @return 0 success + * @return EINVAL invalid parameters + */ +static inline uint32_t lpddr4_sanityfunction31(const lpddr4_privatedata* pd, const lpddr4_dbimode* mode) +{ + /* Declaring return variable */ + uint32_t ret = 0; + + if (mode == NULL) + { + ret = EINVAL; + } + else if (lpddr4_privatedatasf(pd) == EINVAL) + { + ret = EINVAL; + } + else if ( + (*mode != LPDDR4_DBI_RD_ON) && + (*mode != LPDDR4_DBI_RD_OFF) && + (*mode != LPDDR4_DBI_WR_ON) && + (*mode != LPDDR4_DBI_WR_OFF) + ) + { + ret = EINVAL; + } + else + { + /* + * All 'if ... else if' constructs shall be terminated with an 'else' statement + * (MISRA2012-RULE-15_7-3) + */ + } + + return ret; +} + +/** + * A common function to check the validity of API functions with + * following parameter types + * @param[in] pD Driver state info specific to this instance. + * @param[in] fspNum Frequency set number + * @param[out] cycles Refresh rate (in cycles) + * @return 0 success + * @return EINVAL invalid parameters + */ +static inline uint32_t lpddr4_sanityfunction32(const lpddr4_privatedata* pd, const lpddr4_ctlfspnum* fspnum, const uint32_t* cycles) +{ + /* Declaring return variable */ + uint32_t ret = 0; + + if (fspnum == NULL) + { + ret = EINVAL; + } + else if (cycles == NULL) + { + ret = EINVAL; + } + else if (lpddr4_privatedatasf(pd) == EINVAL) + { + ret = EINVAL; + } + else if ( + (*fspnum != LPDDR4_FSP_0) && + (*fspnum != LPDDR4_FSP_1) && + (*fspnum != LPDDR4_FSP_2) + ) + { + ret = EINVAL; + } + else + { + /* + * All 'if ... else if' constructs shall be terminated with an 'else' statement + * (MISRA2012-RULE-15_7-3) + */ + } + + return ret; +} + +#endif /* LPDDR4_SANITY_H */ diff --git a/drivers/ram/k3-j721e/lpddr4_structs_if.h b/drivers/ram/k3-j721e/lpddr4_structs_if.h new file mode 100644 index 0000000..dc6dd35 --- /dev/null +++ b/drivers/ram/k3-j721e/lpddr4_structs_if.h @@ -0,0 +1,121 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/********************************************************************** + * Copyright (C) 2012-2019 Cadence Design Systems, Inc. + ********************************************************************** + * WARNING: This file is auto-generated using api-generator utility. + * api-generator: 12.02.13bb8d5 + * Do not edit it manually. + ********************************************************************** + * Cadence Core Driver for LPDDR4. + ********************************************************************** + */ +#ifndef LPDDR4_STRUCTS_IF_H +#define LPDDR4_STRUCTS_IF_H + +#include <linux/types.h> +#include "lpddr4_if.h" + +/** @defgroup DataStructure Dynamic Data Structures + * This section defines the data structures used by the driver to provide + * hardware information, modification and dynamic operation of the driver. + * These data structures are defined in the header file of the core driver + * and utilized by the API. + * @{ + */ + +/********************************************************************** +* Structures and unions +**********************************************************************/ +/** + * Configuration of device. + * Object of this type is used for probe and init functions. + */ +struct lpddr4_config_s +{ + /** Base address of controller registers */ + struct lpddr4_ctlregs_s* ctlbase; + /** Information/warning handler */ + lpddr4_infocallback infohandler; + /** Controller interrupt handler */ + lpddr4_ctlcallback ctlinterrupthandler; + /** PHY Independent Module interrupt handler */ + lpddr4_phyindepcallback phyindepinterrupthandler; +}; + +/** + * Structure contains private data for Core Driver that should not be used by + * upper layers. This is not a part of API and manipulating of those data may cause + * unpredictable behavior of Core Driver. + */ +struct lpddr4_privatedata_s +{ + /** Base address of controller registers */ + struct lpddr4_ctlregs_s* ctlbase; + /** Information/warning handler */ + lpddr4_infocallback infohandler; + /** Controller interrupt handler */ + lpddr4_ctlcallback ctlinterrupthandler; + /** PHY Independent Module interrupt handler */ + lpddr4_phyindepcallback phyindepinterrupthandler; +}; + +/** Structure to contain debug information reported by the driver. */ +struct lpddr4_debuginfo_s +{ + /** PLL Lock error. */ + bool pllerror; + /** I/O calibration error. */ + bool iocaliberror; + /** RX offset error. */ + bool rxoffseterror; + /** CA training error. */ + bool catraingerror; + /** Write levelling error. */ + bool wrlvlerror; + /** Gate Level error. */ + bool gatelvlerror; + /** Read Level error. */ + bool readlvlerror; + /** Write DQ training error. */ + bool dqtrainingerror; +}; + +/** Frequency Set Point mode register values */ +struct lpddr4_fspmoderegs_s +{ + /** MR1 register data for the FSP. */ + uint8_t mr1data_fn[LPDDR4_MAX_CS]; + /** MR2 register data for the FSP. */ + uint8_t mr2data_fn[LPDDR4_MAX_CS]; + /** MR3 register data for the FSP. */ + uint8_t mr3data_fn[LPDDR4_MAX_CS]; + /** MR11 register data for the FSP. */ + uint8_t mr11data_fn[LPDDR4_MAX_CS]; + /** MR12 register data for the FSP. */ + uint8_t mr12data_fn[LPDDR4_MAX_CS]; + /** MR13 register data for the FSP. */ + uint8_t mr13data_fn[LPDDR4_MAX_CS]; + /** MR14 register data for the FSP. */ + uint8_t mr14data_fn[LPDDR4_MAX_CS]; + /** MR22 register data for the selected frequency. */ + uint8_t mr22data_fn[LPDDR4_MAX_CS]; +}; + +/** Structure to hold data set to initalise registers. */ +struct lpddr4_reginitdata_s +{ + /** Register initialisation data for the Controller. */ + uint32_t denalictlreg[LPDDR4_CTL_REG_COUNT]; + /** Should be set to true, if the corresponding denaliCtlReg element has been updated. */ + bool updatectlreg[LPDDR4_CTL_REG_COUNT]; + /** Register initialisation data for PHY independent module. */ + uint32_t denaliphyindepreg[LPDDR4_PHY_INDEP_REG_COUNT]; + /** Should be set to true, if the corresponding denaliPhyIndepReg element has been updated. */ + bool updatephyindepreg[LPDDR4_PHY_INDEP_REG_COUNT]; + /** Register initialisation data for the PHY. */ + uint32_t denaliphyreg[LPDDR4_PHY_REG_COUNT]; + /** Should be set to true, if the corresponding denaliPhyReg element has been updated. */ + bool updatephyreg[LPDDR4_PHY_REG_COUNT]; +}; + +#endif /* LPDDR4_STRUCTS_IF_H */ diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 976f3a7..cff0082 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -113,6 +113,13 @@ config RESET_MEDIATEK help Support for reset controller on MediaTek SoCs. +config RESET_MTMIPS + bool "Reset controller driver for MediaTek MIPS platform" + depends on DM_RESET && ARCH_MTMIPS + default y + help + Support for reset controller on MediaTek MIPS platform. + config RESET_SUNXI bool "RESET support for Allwinner SoCs" depends on DM_RESET && ARCH_SUNXI diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index f5875fc..8102d8d 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -18,6 +18,7 @@ obj-$(CONFIG_RESET_ROCKCHIP) += reset-rockchip.o obj-$(CONFIG_RESET_MESON) += reset-meson.o obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o obj-$(CONFIG_RESET_MEDIATEK) += reset-mediatek.o +obj-$(CONFIG_RESET_MTMIPS) += reset-mtmips.o obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o obj-$(CONFIG_RESET_HISILICON) += reset-hisilicon.o obj-$(CONFIG_RESET_IMX7) += reset-imx7.o diff --git a/drivers/reset/reset-mtmips.c b/drivers/reset/reset-mtmips.c new file mode 100644 index 0000000..5973456 --- /dev/null +++ b/drivers/reset/reset-mtmips.c @@ -0,0 +1,82 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 MediaTek Inc. All Rights Reserved. + * + * Author: Weijie Gao <weijie.gao@mediatek.com> + */ + +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <reset-uclass.h> +#include <linux/io.h> + +struct mtmips_reset_priv { + void __iomem *base; +}; + +static int mtmips_reset_request(struct reset_ctl *reset_ctl) +{ + return 0; +} + +static int mtmips_reset_free(struct reset_ctl *reset_ctl) +{ + return 0; +} + +static int mtmips_reset_assert(struct reset_ctl *reset_ctl) +{ + struct mtmips_reset_priv *priv = dev_get_priv(reset_ctl->dev); + + setbits_32(priv->base, BIT(reset_ctl->id)); + + return 0; +} + +static int mtmips_reset_deassert(struct reset_ctl *reset_ctl) +{ + struct mtmips_reset_priv *priv = dev_get_priv(reset_ctl->dev); + + clrbits_32(priv->base, BIT(reset_ctl->id)); + + return 0; +} + +static const struct reset_ops mtmips_reset_ops = { + .request = mtmips_reset_request, + .free = mtmips_reset_free, + .rst_assert = mtmips_reset_assert, + .rst_deassert = mtmips_reset_deassert, +}; + +static int mtmips_reset_probe(struct udevice *dev) +{ + return 0; +} + +static int mtmips_reset_ofdata_to_platdata(struct udevice *dev) +{ + struct mtmips_reset_priv *priv = dev_get_priv(dev); + + priv->base = (void __iomem *)dev_remap_addr_index(dev, 0); + if (!priv->base) + return -EINVAL; + + return 0; +} + +static const struct udevice_id mtmips_reset_ids[] = { + { .compatible = "mediatek,mtmips-reset" }, + { } +}; + +U_BOOT_DRIVER(mtmips_reset) = { + .name = "mtmips-reset", + .id = UCLASS_RESET, + .of_match = mtmips_reset_ids, + .ofdata_to_platdata = mtmips_reset_ofdata_to_platdata, + .probe = mtmips_reset_probe, + .priv_auto_alloc_size = sizeof(struct mtmips_reset_priv), + .ops = &mtmips_reset_ops, +}; diff --git a/drivers/scsi/scsi.c b/drivers/scsi/scsi.c index 48cb2a2..69de6a53 100644 --- a/drivers/scsi/scsi.c +++ b/drivers/scsi/scsi.c @@ -45,7 +45,7 @@ static struct blk_desc scsi_dev_desc[CONFIG_SYS_SCSI_MAX_DEVICE]; #endif /* almost the maximum amount of the scsi_ext command.. */ -#define SCSI_MAX_READ_BLK 0xFFFF +#define SCSI_MAX_BLK 0xFFFF #define SCSI_LBA48_READ 0xFFFFFFF static void scsi_print_error(struct scsi_cmd *pccb) @@ -83,6 +83,22 @@ void scsi_setup_read16(struct scsi_cmd *pccb, lbaint_t start, } #endif +static void scsi_setup_inquiry(struct scsi_cmd *pccb) +{ + pccb->cmd[0] = SCSI_INQUIRY; + pccb->cmd[1] = pccb->lun << 5; + pccb->cmd[2] = 0; + pccb->cmd[3] = 0; + if (pccb->datalen > 255) + pccb->cmd[4] = 255; + else + pccb->cmd[4] = (unsigned char)pccb->datalen; + pccb->cmd[5] = 0; + pccb->cmdlen = 6; + pccb->msgout[0] = SCSI_IDENTIFY; /* NOT USED */ +} + +#ifdef CONFIG_BLK static void scsi_setup_read_ext(struct scsi_cmd *pccb, lbaint_t start, unsigned short blocks) { @@ -126,36 +142,13 @@ static void scsi_setup_write_ext(struct scsi_cmd *pccb, lbaint_t start, pccb->cmd[7], pccb->cmd[8]); } -static void scsi_setup_inquiry(struct scsi_cmd *pccb) -{ - pccb->cmd[0] = SCSI_INQUIRY; - pccb->cmd[1] = pccb->lun << 5; - pccb->cmd[2] = 0; - pccb->cmd[3] = 0; - if (pccb->datalen > 255) - pccb->cmd[4] = 255; - else - pccb->cmd[4] = (unsigned char)pccb->datalen; - pccb->cmd[5] = 0; - pccb->cmdlen = 6; - pccb->msgout[0] = SCSI_IDENTIFY; /* NOT USED */ -} - -#ifdef CONFIG_BLK static ulong scsi_read(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt, void *buffer) -#else -static ulong scsi_read(struct blk_desc *block_dev, lbaint_t blknr, - lbaint_t blkcnt, void *buffer) -#endif { -#ifdef CONFIG_BLK struct blk_desc *block_dev = dev_get_uclass_platdata(dev); struct udevice *bdev = dev->parent; -#else - struct udevice *bdev = NULL; -#endif - lbaint_t start, blks; + struct scsi_platdata *uc_plat = dev_get_uclass_platdata(bdev); + lbaint_t start, blks, max_blks; uintptr_t buf_addr; unsigned short smallblks = 0; struct scsi_cmd *pccb = (struct scsi_cmd *)&tempccb; @@ -166,28 +159,33 @@ static ulong scsi_read(struct blk_desc *block_dev, lbaint_t blknr, buf_addr = (unsigned long)buffer; start = blknr; blks = blkcnt; + if (uc_plat->max_bytes_per_req) + max_blks = uc_plat->max_bytes_per_req / block_dev->blksz; + else + max_blks = SCSI_MAX_BLK; + debug("\nscsi_read: dev %d startblk " LBAF ", blccnt " LBAF " buffer %lx\n", block_dev->devnum, start, blks, (unsigned long)buffer); do { pccb->pdata = (unsigned char *)buf_addr; + pccb->dma_dir = DMA_FROM_DEVICE; #ifdef CONFIG_SYS_64BIT_LBA if (start > SCSI_LBA48_READ) { unsigned long blocks; - blocks = min_t(lbaint_t, blks, SCSI_MAX_READ_BLK); + blocks = min_t(lbaint_t, blks, max_blks); pccb->datalen = block_dev->blksz * blocks; scsi_setup_read16(pccb, start, blocks); start += blocks; blks -= blocks; } else #endif - if (blks > SCSI_MAX_READ_BLK) { - pccb->datalen = block_dev->blksz * - SCSI_MAX_READ_BLK; - smallblks = SCSI_MAX_READ_BLK; + if (blks > max_blks) { + pccb->datalen = block_dev->blksz * max_blks; + smallblks = max_blks; scsi_setup_read_ext(pccb, start, smallblks); - start += SCSI_MAX_READ_BLK; - blks -= SCSI_MAX_READ_BLK; + start += max_blks; + blks -= max_blks; } else { pccb->datalen = block_dev->blksz * blks; smallblks = (unsigned short)blks; @@ -214,24 +212,13 @@ static ulong scsi_read(struct blk_desc *block_dev, lbaint_t blknr, * scsi_write */ -/* Almost the maximum amount of the scsi_ext command.. */ -#define SCSI_MAX_WRITE_BLK 0xFFFF - -#ifdef CONFIG_BLK static ulong scsi_write(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt, const void *buffer) -#else -static ulong scsi_write(struct blk_desc *block_dev, lbaint_t blknr, - lbaint_t blkcnt, const void *buffer) -#endif { -#ifdef CONFIG_BLK struct blk_desc *block_dev = dev_get_uclass_platdata(dev); struct udevice *bdev = dev->parent; -#else - struct udevice *bdev = NULL; -#endif - lbaint_t start, blks; + struct scsi_platdata *uc_plat = dev_get_uclass_platdata(bdev); + lbaint_t start, blks, max_blks; uintptr_t buf_addr; unsigned short smallblks; struct scsi_cmd *pccb = (struct scsi_cmd *)&tempccb; @@ -242,17 +229,22 @@ static ulong scsi_write(struct blk_desc *block_dev, lbaint_t blknr, buf_addr = (unsigned long)buffer; start = blknr; blks = blkcnt; + if (uc_plat->max_bytes_per_req) + max_blks = uc_plat->max_bytes_per_req / block_dev->blksz; + else + max_blks = SCSI_MAX_BLK; + debug("\n%s: dev %d startblk " LBAF ", blccnt " LBAF " buffer %lx\n", __func__, block_dev->devnum, start, blks, (unsigned long)buffer); do { pccb->pdata = (unsigned char *)buf_addr; - if (blks > SCSI_MAX_WRITE_BLK) { - pccb->datalen = (block_dev->blksz * - SCSI_MAX_WRITE_BLK); - smallblks = SCSI_MAX_WRITE_BLK; + pccb->dma_dir = DMA_TO_DEVICE; + if (blks > max_blks) { + pccb->datalen = block_dev->blksz * max_blks; + smallblks = max_blks; scsi_setup_write_ext(pccb, start, smallblks); - start += SCSI_MAX_WRITE_BLK; - blks -= SCSI_MAX_WRITE_BLK; + start += max_blks; + blks -= max_blks; } else { pccb->datalen = block_dev->blksz * blks; smallblks = (unsigned short)blks; @@ -273,6 +265,7 @@ static ulong scsi_write(struct blk_desc *block_dev, lbaint_t blknr, __func__, start, smallblks, buf_addr); return blkcnt; } +#endif #if defined(CONFIG_PCI) && !defined(CONFIG_SCSI_AHCI_PLAT) && \ !defined(CONFIG_DM_SCSI) @@ -394,6 +387,7 @@ static int scsi_read_capacity(struct udevice *dev, struct scsi_cmd *pccb, pccb->msgout[0] = SCSI_IDENTIFY; /* NOT USED */ pccb->datalen = 16; + pccb->dma_dir = DMA_FROM_DEVICE; if (scsi_exec(dev, pccb)) return 1; @@ -450,10 +444,6 @@ static void scsi_init_dev_desc_priv(struct blk_desc *dev_desc) dev_desc->product[0] = 0; dev_desc->revision[0] = 0; dev_desc->removable = false; -#if !CONFIG_IS_ENABLED(BLK) - dev_desc->block_read = scsi_read; - dev_desc->block_write = scsi_write; -#endif } #if !defined(CONFIG_DM_SCSI) @@ -494,11 +484,13 @@ static int scsi_detect_dev(struct udevice *dev, int target, int lun, lbaint_t capacity; unsigned long blksz; struct scsi_cmd *pccb = (struct scsi_cmd *)&tempccb; + int count, err; pccb->target = target; pccb->lun = lun; pccb->pdata = (unsigned char *)&tempbuff; pccb->datalen = 512; + pccb->dma_dir = DMA_FROM_DEVICE; scsi_setup_inquiry(pccb); if (scsi_exec(dev, pccb)) { if (pccb->contr_stat == SCSI_SEL_TIME_OUT) { @@ -529,9 +521,14 @@ static int scsi_detect_dev(struct udevice *dev, int target, int lun, dev_desc->target = pccb->target; dev_desc->lun = pccb->lun; - pccb->datalen = 0; - scsi_setup_test_unit_ready(pccb); - if (scsi_exec(dev, pccb)) { + for (count = 0; count < 3; count++) { + pccb->datalen = 0; + scsi_setup_test_unit_ready(pccb); + err = scsi_exec(dev, pccb); + if (!err) + break; + } + if (err) { if (dev_desc->removable) { dev_desc->type = perq; goto removable; diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c index b907508..bf5f392 100644 --- a/drivers/serial/serial.c +++ b/drivers/serial/serial.c @@ -124,6 +124,7 @@ serial_initfunc(ns16550_serial_initialize); serial_initfunc(pl01x_serial_initialize); serial_initfunc(pxa_serial_initialize); serial_initfunc(sh_serial_initialize); +serial_initfunc(mtk_serial_initialize); /** * serial_register() - Register serial driver with serial driver core @@ -177,6 +178,7 @@ void serial_initialize(void) pl01x_serial_initialize(); pxa_serial_initialize(); sh_serial_initialize(); + mtk_serial_initialize(); serial_assign(default_serial_console()->name); } diff --git a/drivers/serial/serial_mtk.c b/drivers/serial/serial_mtk.c index bce1be8..18530a4 100644 --- a/drivers/serial/serial_mtk.c +++ b/drivers/serial/serial_mtk.c @@ -46,6 +46,22 @@ struct mtk_serial_regs { #define UART_LSR_DR 0x01 /* Data ready */ #define UART_LSR_THRE 0x20 /* Xmit holding register empty */ +#define UART_LSR_TEMT 0x40 /* Xmitter empty */ + +#define UART_MCR_DTR 0x01 /* DTR */ +#define UART_MCR_RTS 0x02 /* RTS */ + +#define UART_FCR_FIFO_EN 0x01 /* Fifo enable */ +#define UART_FCR_RXSR 0x02 /* Receiver soft reset */ +#define UART_FCR_TXSR 0x04 /* Transmitter soft reset */ + +#define UART_MCRVAL (UART_MCR_DTR | \ + UART_MCR_RTS) + +/* Clear & enable FIFOs */ +#define UART_FCRVAL (UART_FCR_FIFO_EN | \ + UART_FCR_RXSR | \ + UART_FCR_TXSR) /* the data is correct if the real baud is within 3%. */ #define BAUD_ALLOW_MAX(baud) ((baud) + (baud) * 3 / 100) @@ -124,6 +140,37 @@ static void _mtk_serial_setbrg(struct mtk_serial_priv *priv, int baud) } } +static int _mtk_serial_putc(struct mtk_serial_priv *priv, const char ch) +{ + if (!(readl(&priv->regs->lsr) & UART_LSR_THRE)) + return -EAGAIN; + + writel(ch, &priv->regs->thr); + + if (ch == '\n') + WATCHDOG_RESET(); + + return 0; +} + +static int _mtk_serial_getc(struct mtk_serial_priv *priv) +{ + if (!(readl(&priv->regs->lsr) & UART_LSR_DR)) + return -EAGAIN; + + return readl(&priv->regs->rbr); +} + +static int _mtk_serial_pending(struct mtk_serial_priv *priv, bool input) +{ + if (input) + return (readl(&priv->regs->lsr) & UART_LSR_DR) ? 1 : 0; + else + return (readl(&priv->regs->lsr) & UART_LSR_THRE) ? 0 : 1; +} + +#if defined(CONFIG_DM_SERIAL) && \ + (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_DM)) static int mtk_serial_setbrg(struct udevice *dev, int baudrate) { struct mtk_serial_priv *priv = dev_get_priv(dev); @@ -137,35 +184,21 @@ static int mtk_serial_putc(struct udevice *dev, const char ch) { struct mtk_serial_priv *priv = dev_get_priv(dev); - if (!(readl(&priv->regs->lsr) & UART_LSR_THRE)) - return -EAGAIN; - - writel(ch, &priv->regs->thr); - - if (ch == '\n') - WATCHDOG_RESET(); - - return 0; + return _mtk_serial_putc(priv, ch); } static int mtk_serial_getc(struct udevice *dev) { struct mtk_serial_priv *priv = dev_get_priv(dev); - if (!(readl(&priv->regs->lsr) & UART_LSR_DR)) - return -EAGAIN; - - return readl(&priv->regs->rbr); + return _mtk_serial_getc(priv); } static int mtk_serial_pending(struct udevice *dev, bool input) { struct mtk_serial_priv *priv = dev_get_priv(dev); - if (input) - return (readl(&priv->regs->lsr) & UART_LSR_DR) ? 1 : 0; - else - return (readl(&priv->regs->lsr) & UART_LSR_THRE) ? 0 : 1; + return _mtk_serial_pending(priv, input); } static int mtk_serial_probe(struct udevice *dev) @@ -175,6 +208,9 @@ static int mtk_serial_probe(struct udevice *dev) /* Disable interrupt */ writel(0, &priv->regs->ier); + writel(UART_MCRVAL, &priv->regs->mcr); + writel(UART_FCRVAL, &priv->regs->fcr); + return 0; } @@ -235,6 +271,157 @@ U_BOOT_DRIVER(serial_mtk) = { .ops = &mtk_serial_ops, .flags = DM_FLAG_PRE_RELOC, }; +#else + +DECLARE_GLOBAL_DATA_PTR; + +#define DECLARE_HSUART_PRIV(port) \ + static struct mtk_serial_priv mtk_hsuart##port = { \ + .regs = (struct mtk_serial_regs *)CONFIG_SYS_NS16550_COM##port, \ + .clock = CONFIG_SYS_NS16550_CLK \ +}; + +#define DECLARE_HSUART_FUNCTIONS(port) \ + static int mtk_serial##port##_init(void) \ + { \ + writel(0, &mtk_hsuart##port.regs->ier); \ + writel(UART_MCRVAL, &mtk_hsuart##port.regs->mcr); \ + writel(UART_FCRVAL, &mtk_hsuart##port.regs->fcr); \ + _mtk_serial_setbrg(&mtk_hsuart##port, gd->baudrate); \ + return 0 ; \ + } \ + static void mtk_serial##port##_setbrg(void) \ + { \ + _mtk_serial_setbrg(&mtk_hsuart##port, gd->baudrate); \ + } \ + static int mtk_serial##port##_getc(void) \ + { \ + int err; \ + do { \ + err = _mtk_serial_getc(&mtk_hsuart##port); \ + if (err == -EAGAIN) \ + WATCHDOG_RESET(); \ + } while (err == -EAGAIN); \ + return err >= 0 ? err : 0; \ + } \ + static int mtk_serial##port##_tstc(void) \ + { \ + return _mtk_serial_pending(&mtk_hsuart##port, true); \ + } \ + static void mtk_serial##port##_putc(const char c) \ + { \ + int err; \ + if (c == '\n') \ + mtk_serial##port##_putc('\r'); \ + do { \ + err = _mtk_serial_putc(&mtk_hsuart##port, c); \ + } while (err == -EAGAIN); \ + } \ + static void mtk_serial##port##_puts(const char *s) \ + { \ + while (*s) { \ + mtk_serial##port##_putc(*s++); \ + } \ + } + +/* Serial device descriptor */ +#define INIT_HSUART_STRUCTURE(port, __name) { \ + .name = __name, \ + .start = mtk_serial##port##_init, \ + .stop = NULL, \ + .setbrg = mtk_serial##port##_setbrg, \ + .getc = mtk_serial##port##_getc, \ + .tstc = mtk_serial##port##_tstc, \ + .putc = mtk_serial##port##_putc, \ + .puts = mtk_serial##port##_puts, \ +} + +#define DECLARE_HSUART(port, __name) \ + DECLARE_HSUART_PRIV(port); \ + DECLARE_HSUART_FUNCTIONS(port); \ + struct serial_device mtk_hsuart##port##_device = \ + INIT_HSUART_STRUCTURE(port, __name); + +#if !defined(CONFIG_CONS_INDEX) +#elif (CONFIG_CONS_INDEX < 1) || (CONFIG_CONS_INDEX > 6) +#error "Invalid console index value." +#endif + +#if CONFIG_CONS_INDEX == 1 && !defined(CONFIG_SYS_NS16550_COM1) +#error "Console port 1 defined but not configured." +#elif CONFIG_CONS_INDEX == 2 && !defined(CONFIG_SYS_NS16550_COM2) +#error "Console port 2 defined but not configured." +#elif CONFIG_CONS_INDEX == 3 && !defined(CONFIG_SYS_NS16550_COM3) +#error "Console port 3 defined but not configured." +#elif CONFIG_CONS_INDEX == 4 && !defined(CONFIG_SYS_NS16550_COM4) +#error "Console port 4 defined but not configured." +#elif CONFIG_CONS_INDEX == 5 && !defined(CONFIG_SYS_NS16550_COM5) +#error "Console port 5 defined but not configured." +#elif CONFIG_CONS_INDEX == 6 && !defined(CONFIG_SYS_NS16550_COM6) +#error "Console port 6 defined but not configured." +#endif + +#if defined(CONFIG_SYS_NS16550_COM1) +DECLARE_HSUART(1, "mtk-hsuart0"); +#endif +#if defined(CONFIG_SYS_NS16550_COM2) +DECLARE_HSUART(2, "mtk-hsuart1"); +#endif +#if defined(CONFIG_SYS_NS16550_COM3) +DECLARE_HSUART(3, "mtk-hsuart2"); +#endif +#if defined(CONFIG_SYS_NS16550_COM4) +DECLARE_HSUART(4, "mtk-hsuart3"); +#endif +#if defined(CONFIG_SYS_NS16550_COM5) +DECLARE_HSUART(5, "mtk-hsuart4"); +#endif +#if defined(CONFIG_SYS_NS16550_COM6) +DECLARE_HSUART(6, "mtk-hsuart5"); +#endif + +__weak struct serial_device *default_serial_console(void) +{ +#if CONFIG_CONS_INDEX == 1 + return &mtk_hsuart1_device; +#elif CONFIG_CONS_INDEX == 2 + return &mtk_hsuart2_device; +#elif CONFIG_CONS_INDEX == 3 + return &mtk_hsuart3_device; +#elif CONFIG_CONS_INDEX == 4 + return &mtk_hsuart4_device; +#elif CONFIG_CONS_INDEX == 5 + return &mtk_hsuart5_device; +#elif CONFIG_CONS_INDEX == 6 + return &mtk_hsuart6_device; +#else +#error "Bad CONFIG_CONS_INDEX." +#endif +} + +void mtk_serial_initialize(void) +{ +#if defined(CONFIG_SYS_NS16550_COM1) + serial_register(&mtk_hsuart1_device); +#endif +#if defined(CONFIG_SYS_NS16550_COM2) + serial_register(&mtk_hsuart2_device); +#endif +#if defined(CONFIG_SYS_NS16550_COM3) + serial_register(&mtk_hsuart3_device); +#endif +#if defined(CONFIG_SYS_NS16550_COM4) + serial_register(&mtk_hsuart4_device); +#endif +#if defined(CONFIG_SYS_NS16550_COM5) + serial_register(&mtk_hsuart5_device); +#endif +#if defined(CONFIG_SYS_NS16550_COM6) + serial_register(&mtk_hsuart6_device); +#endif +} + +#endif #ifdef CONFIG_DEBUG_UART_MTK @@ -248,6 +435,8 @@ static inline void _debug_uart_init(void) priv.clock = CONFIG_DEBUG_UART_CLOCK; writel(0, &priv.regs->ier); + writel(UART_MCRVAL, &priv.regs->mcr); + writel(UART_FCRVAL, &priv.regs->fcr); _mtk_serial_setbrg(&priv, CONFIG_BAUDRATE); } diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index b8ca2bd..7be867d 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -1,5 +1,22 @@ menuconfig SPI bool "SPI Support" + help + The "Serial Peripheral Interface" is a low level synchronous + protocol. Chips that support SPI can have data transfer rates + up to several tens of Mbit/sec. Chips are addressed with a + controller and a chipselect. Most SPI slaves don't support + dynamic device discovery; some are even write-only or read-only. + + SPI is widely used by microcontrollers to talk with sensors, + eeprom and flash memory, codecs and various other controller + chips, analog to digital (and d-to-a) converters, and more. + MMC and SD cards can be accessed using SPI protocol; and for + DataFlash cards used in MMC sockets, SPI must always be used. + + SPI is one of a family of similar protocols using a four wire + interface (select, clock, data in, data out) including Microwire + (half duplex), SSP, SSI, and PSP. This driver framework should + work with most such devices and controllers. if SPI @@ -243,6 +260,7 @@ config SPI_SIFIVE config SPI_SUNXI bool "Allwinner SoC SPI controllers" + default ARCH_SUNXI help Enable the Allwinner SoC SPi controller driver. diff --git a/drivers/spi/ath79_spi.c b/drivers/spi/ath79_spi.c index 4fd3c05..2070692 100644 --- a/drivers/spi/ath79_spi.c +++ b/drivers/spi/ath79_spi.c @@ -198,7 +198,7 @@ static int ath79_cs_info(struct udevice *bus, uint cs, { /* Always allow activity on CS 0/1/2 */ if (cs >= 3) - return -ENODEV; + return -EINVAL; return 0; } diff --git a/drivers/spi/bcm63xx_hsspi.c b/drivers/spi/bcm63xx_hsspi.c index e82b80c..529adfb 100644 --- a/drivers/spi/bcm63xx_hsspi.c +++ b/drivers/spi/bcm63xx_hsspi.c @@ -108,7 +108,7 @@ static int bcm63xx_hsspi_cs_info(struct udevice *bus, uint cs, if (cs >= priv->num_cs) { printf("no cs %u\n", cs); - return -ENODEV; + return -EINVAL; } return 0; diff --git a/drivers/spi/bcm63xx_spi.c b/drivers/spi/bcm63xx_spi.c index 4d19e03..69f88c9 100644 --- a/drivers/spi/bcm63xx_spi.c +++ b/drivers/spi/bcm63xx_spi.c @@ -130,7 +130,7 @@ static int bcm63xx_spi_cs_info(struct udevice *bus, uint cs, if (cs >= priv->num_cs) { printf("no cs %u\n", cs); - return -ENODEV; + return -EINVAL; } return 0; diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c index 7d58cfa..91e613e 100644 --- a/drivers/spi/designware_spi.c +++ b/drivers/spi/designware_spi.c @@ -518,8 +518,22 @@ static int dw_spi_set_mode(struct udevice *bus, uint mode) static int dw_spi_remove(struct udevice *bus) { struct dw_spi_priv *priv = dev_get_priv(bus); + int ret; + + ret = reset_release_bulk(&priv->resets); + if (ret) + return ret; - return reset_release_bulk(&priv->resets); +#if CONFIG_IS_ENABLED(CLK) + ret = clk_disable(&priv->clk); + if (ret) + return ret; + + ret = clk_free(&priv->clk); + if (ret) + return ret; +#endif + return 0; } static const struct dm_spi_ops dw_spi_ops = { diff --git a/drivers/spi/mt7621_spi.c b/drivers/spi/mt7621_spi.c index 107e58f..90e85c6 100644 --- a/drivers/spi/mt7621_spi.c +++ b/drivers/spi/mt7621_spi.c @@ -9,18 +9,22 @@ */ #include <common.h> +#include <clk.h> #include <dm.h> #include <spi.h> #include <wait_bit.h> #include <linux/io.h> -#define SPI_MSG_SIZE_MAX 32 /* SPI message chunk size */ -/* Enough for SPI NAND page read / write with page size 2048 bytes */ -#define SPI_MSG_SIZE_OVERALL (2048 + 16) +#define MT7621_RX_FIFO_LEN 32 +#define MT7621_TX_FIFO_LEN 36 #define MT7621_SPI_TRANS 0x00 #define MT7621_SPI_TRANS_START BIT(8) #define MT7621_SPI_TRANS_BUSY BIT(16) +#define TRANS_ADDR_SZ GENMASK(20, 19) +#define TRANS_ADDR_SZ_SHIFT 19 +#define TRANS_MOSI_BCNT GENMASK(3, 0) +#define TRANS_MOSI_BCNT_SHIFT 0 #define MT7621_SPI_OPCODE 0x04 #define MT7621_SPI_DATA0 0x08 @@ -38,27 +42,34 @@ #define MASTER_RS_CLK_SEL_SHIFT 16 #define MASTER_RS_SLAVE_SEL GENMASK(31, 29) +#define MOREBUF_CMD_CNT GENMASK(29, 24) +#define MOREBUF_CMD_CNT_SHIFT 24 +#define MOREBUF_MISO_CNT GENMASK(20, 12) +#define MOREBUF_MISO_CNT_SHIFT 12 +#define MOREBUF_MOSI_CNT GENMASK(8, 0) +#define MOREBUF_MOSI_CNT_SHIFT 0 + struct mt7621_spi { void __iomem *base; unsigned int sys_freq; - u32 data[(SPI_MSG_SIZE_OVERALL / 4) + 1]; - int tx_len; }; -static void mt7621_spi_reset(struct mt7621_spi *rs, int duplex) -{ - setbits_le32(rs->base + MT7621_SPI_MASTER, - MASTER_RS_SLAVE_SEL | MASTER_MORE_BUFMODE); -} - static void mt7621_spi_set_cs(struct mt7621_spi *rs, int cs, int enable) { - u32 val = 0; - debug("%s: cs#%d -> %s\n", __func__, cs, enable ? "enable" : "disable"); - if (enable) - val = BIT(cs); - iowrite32(val, rs->base + MT7621_SPI_POLAR); + + if (enable) { + setbits_le32(rs->base + MT7621_SPI_MASTER, + MASTER_RS_SLAVE_SEL | MASTER_MORE_BUFMODE); + iowrite32(BIT(cs), rs->base + MT7621_SPI_POLAR); + } else { + iowrite32(0, rs->base + MT7621_SPI_POLAR); + iowrite32((2 << TRANS_ADDR_SZ_SHIFT) | + (1 << TRANS_MOSI_BCNT_SHIFT), + rs->base + MT7621_SPI_TRANS); + clrbits_le32(rs->base + MT7621_SPI_MASTER, + MASTER_RS_SLAVE_SEL | MASTER_MORE_BUFMODE); + } } static int mt7621_spi_set_mode(struct udevice *bus, uint mode) @@ -128,20 +139,89 @@ static inline int mt7621_spi_wait_till_ready(struct mt7621_spi *rs) return ret; } +static int mt7621_spi_read(struct mt7621_spi *rs, u8 *buf, size_t len) +{ + size_t rx_len; + int i, ret; + u32 val = 0; + + while (len) { + rx_len = min_t(size_t, len, MT7621_RX_FIFO_LEN); + + iowrite32((rx_len * 8) << MOREBUF_MISO_CNT_SHIFT, + rs->base + MT7621_SPI_MOREBUF); + iowrite32(MT7621_SPI_TRANS_START, rs->base + MT7621_SPI_TRANS); + + ret = mt7621_spi_wait_till_ready(rs); + if (ret) + return ret; + + for (i = 0; i < rx_len; i++) { + if ((i % 4) == 0) + val = ioread32(rs->base + MT7621_SPI_DATA0 + i); + *buf++ = val & 0xff; + val >>= 8; + } + + len -= rx_len; + } + + return ret; +} + +static int mt7621_spi_write(struct mt7621_spi *rs, const u8 *buf, size_t len) +{ + size_t tx_len, opcode_len, dido_len; + int i, ret; + u32 val; + + while (len) { + tx_len = min_t(size_t, len, MT7621_TX_FIFO_LEN); + + opcode_len = min_t(size_t, tx_len, 4); + dido_len = tx_len - opcode_len; + + val = 0; + for (i = 0; i < opcode_len; i++) { + val <<= 8; + val |= *buf++; + } + + iowrite32(val, rs->base + MT7621_SPI_OPCODE); + + val = 0; + for (i = 0; i < dido_len; i++) { + val |= (*buf++) << ((i % 4) * 8); + + if ((i % 4 == 3) || (i == dido_len - 1)) { + iowrite32(val, rs->base + MT7621_SPI_DATA0 + + (i & ~3)); + val = 0; + } + } + + iowrite32(((opcode_len * 8) << MOREBUF_CMD_CNT_SHIFT) | + ((dido_len * 8) << MOREBUF_MOSI_CNT_SHIFT), + rs->base + MT7621_SPI_MOREBUF); + iowrite32(MT7621_SPI_TRANS_START, rs->base + MT7621_SPI_TRANS); + + ret = mt7621_spi_wait_till_ready(rs); + if (ret) + return ret; + + len -= tx_len; + } + + return 0; +} + static int mt7621_spi_xfer(struct udevice *dev, unsigned int bitlen, const void *dout, void *din, unsigned long flags) { struct udevice *bus = dev->parent; struct mt7621_spi *rs = dev_get_priv(bus); - const u8 *tx_buf = dout; - u8 *ptr = (u8 *)dout; - u8 *rx_buf = din; int total_size = bitlen >> 3; - int chunk_size; - int rx_len = 0; - u32 data[(SPI_MSG_SIZE_MAX / 4) + 1] = { 0 }; - u32 val; - int i; + int ret = 0; debug("%s: dout=%p, din=%p, len=%x, flags=%lx\n", __func__, dout, din, total_size, flags); @@ -155,13 +235,6 @@ static int mt7621_spi_xfer(struct udevice *dev, unsigned int bitlen, return -EIO; } - if (dout) { - debug("TX-DATA: "); - for (i = 0; i < total_size; i++) - debug("%02x ", *ptr++); - debug("\n"); - } - mt7621_spi_wait_till_ready(rs); /* @@ -171,119 +244,41 @@ static int mt7621_spi_xfer(struct udevice *dev, unsigned int bitlen, if (flags & SPI_XFER_BEGIN) mt7621_spi_set_cs(rs, spi_chip_select(dev), 1); - while (total_size > 0) { - /* Don't exceed the max xfer size */ - chunk_size = min_t(int, total_size, SPI_MSG_SIZE_MAX); - - /* - * We might have some TX data buffered from the last xfer - * message. Make sure, that this does not exceed the max - * xfer size - */ - if (rs->tx_len > 4) - chunk_size -= rs->tx_len; - if (din) - rx_len = chunk_size; - - if (tx_buf) { - /* Check if this message does not exceed the buffer */ - if ((chunk_size + rs->tx_len) > SPI_MSG_SIZE_OVERALL) { - printf("TX message size too big (%d)\n", - chunk_size + rs->tx_len); - return -EMSGSIZE; - } - - /* - * Write all TX data into internal buffer to collect - * all TX messages into one buffer (might be split into - * multiple calls to this function) - */ - for (i = 0; i < chunk_size; i++, rs->tx_len++) { - rs->data[rs->tx_len / 4] |= - tx_buf[i] << (8 * (rs->tx_len & 3)); - } - } - - if (flags & SPI_XFER_END) { - /* Write TX data into controller */ - if (rs->tx_len) { - rs->data[0] = swab32(rs->data[0]); - if (rs->tx_len < 4) - rs->data[0] >>= (4 - rs->tx_len) * 8; - - for (i = 0; i < rs->tx_len; i += 4) { - iowrite32(rs->data[i / 4], rs->base + - MT7621_SPI_OPCODE + i); - } - } + if (din) + ret = mt7621_spi_read(rs, din, total_size); + else if (dout) + ret = mt7621_spi_write(rs, dout, total_size); - /* Write length into controller */ - val = (min_t(int, rs->tx_len, 4) * 8) << 24; - if (rs->tx_len > 4) - val |= (rs->tx_len - 4) * 8; - val |= (rx_len * 8) << 12; - iowrite32(val, rs->base + MT7621_SPI_MOREBUF); - - /* Start the xfer */ - setbits_le32(rs->base + MT7621_SPI_TRANS, - MT7621_SPI_TRANS_START); - - /* Wait until xfer is finished on bus */ - mt7621_spi_wait_till_ready(rs); - - /* Reset TX length and TX buffer for next xfer */ - rs->tx_len = 0; - memset(rs->data, 0, sizeof(rs->data)); - } - - for (i = 0; i < rx_len; i += 4) - data[i / 4] = ioread32(rs->base + MT7621_SPI_DATA0 + i); - - if (rx_len) { - debug("RX-DATA: "); - for (i = 0; i < rx_len; i++) { - rx_buf[i] = data[i / 4] >> (8 * (i & 3)); - debug("%02x ", rx_buf[i]); - } - debug("\n"); - } - - if (tx_buf) - tx_buf += chunk_size; - if (rx_buf) - rx_buf += chunk_size; - total_size -= chunk_size; - } - - /* Wait until xfer is finished on bus and de-assert CS */ - mt7621_spi_wait_till_ready(rs); if (flags & SPI_XFER_END) mt7621_spi_set_cs(rs, spi_chip_select(dev), 0); - return 0; + return ret; } static int mt7621_spi_probe(struct udevice *dev) { struct mt7621_spi *rs = dev_get_priv(dev); + struct clk clk; + int ret; rs->base = dev_remap_addr(dev); if (!rs->base) return -EINVAL; - /* - * Read input clock via DT for now. At some point this should be - * replaced by implementing a clock driver for this SoC and getting - * the SPI frequency via this clock driver. - */ - rs->sys_freq = dev_read_u32_default(dev, "clock-frequency", 0); + ret = clk_get_by_index(dev, 0, &clk); + if (ret < 0) { + printf("Please provide a clock!\n"); + return ret; + } + + clk_enable(&clk); + + rs->sys_freq = clk_get_rate(&clk); if (!rs->sys_freq) { - printf("Please provide clock-frequency!\n"); + printf("Please provide a valid clock!\n"); return -EINVAL; } - mt7621_spi_reset(rs, 0); - return 0; } diff --git a/drivers/spi/sandbox_spi.c b/drivers/spi/sandbox_spi.c index 906401e..16473ec 100644 --- a/drivers/spi/sandbox_spi.c +++ b/drivers/spi/sandbox_spi.c @@ -117,7 +117,7 @@ static int sandbox_cs_info(struct udevice *bus, uint cs, { /* Always allow activity on CS 0 */ if (cs >= 1) - return -ENODEV; + return -EINVAL; return 0; } diff --git a/drivers/spi/spi-uclass.c b/drivers/spi/spi-uclass.c index a4d1b65..9475160 100644 --- a/drivers/spi/spi-uclass.c +++ b/drivers/spi/spi-uclass.c @@ -261,11 +261,10 @@ int spi_cs_info(struct udevice *bus, uint cs, struct spi_cs_info *info) return ops->cs_info(bus, cs, info); /* - * We could assume there is at least one valid chip select, but best - * to be sure and return an error in this case. The driver didn't - * care enough to tell us. + * We could assume there is at least one valid chip select. + * The driver didn't care enough to tell us. */ - return -ENODEV; + return 0; } int spi_find_bus_and_cs(int busnum, int cs, struct udevice **busp, diff --git a/drivers/spi/tegra20_sflash.c b/drivers/spi/tegra20_sflash.c index a54b10f..567e33f 100644 --- a/drivers/spi/tegra20_sflash.c +++ b/drivers/spi/tegra20_sflash.c @@ -78,7 +78,7 @@ int tegra20_sflash_cs_info(struct udevice *bus, unsigned int cs, { /* Tegra20 SPI-Flash - only 1 device ('bus/cs') */ if (cs != 0) - return -ENODEV; + return -EINVAL; else return 0; } diff --git a/drivers/spi/zynqmp_gqspi.c b/drivers/spi/zynqmp_gqspi.c index 04ea42c..c11f040 100644 --- a/drivers/spi/zynqmp_gqspi.c +++ b/drivers/spi/zynqmp_gqspi.c @@ -6,8 +6,6 @@ */ #include <common.h> -#include <asm/arch/clk.h> -#include <asm/arch/hardware.h> #include <asm/arch/sys_proto.h> #include <asm/io.h> #include <clk.h> diff --git a/drivers/ufs/Kconfig b/drivers/ufs/Kconfig new file mode 100644 index 0000000..c2aafd3 --- /dev/null +++ b/drivers/ufs/Kconfig @@ -0,0 +1,23 @@ +menu "UFS Host Controller Support" + +config UFS + bool "Support UFS controllers" + depends on DM_SCSI + help + This selects support for Universal Flash Subsystem (UFS). + Say Y here if you want UFS Support. + +config CADENCE_UFS + bool "Cadence platform driver for UFS" + depends on UFS + help + This selects the platform driver for the Cadence UFS host + controller present on present TI's J721e devices. + +config TI_J721E_UFS + bool "Glue Layer driver for UFS on TI J721E devices" + help + This selects the glue layer driver for Cadence controller + present on TI's J721E devices. + +endmenu diff --git a/drivers/ufs/Makefile b/drivers/ufs/Makefile new file mode 100644 index 0000000..62ed016 --- /dev/null +++ b/drivers/ufs/Makefile @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com +# + +obj-$(CONFIG_UFS) += ufs.o ufs-uclass.o +obj-$(CONFIG_CADENCE_UFS) += cdns-platform.o +obj-$(CONFIG_TI_J721E_UFS) += ti-j721e-ufs.o diff --git a/drivers/ufs/cdns-platform.c b/drivers/ufs/cdns-platform.c new file mode 100644 index 0000000..c80f425 --- /dev/null +++ b/drivers/ufs/cdns-platform.c @@ -0,0 +1,122 @@ +// SPDX-License-Identifier: GPL-2.0+ +/** + * cdns-platform.c - Platform driver for Cadence UFSHCI device + * + * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com + */ + +#include <clk.h> +#include <common.h> +#include <dm.h> +#include <ufs.h> + +#include "ufs.h" + +#define USEC_PER_SEC 1000000L + +#define CDNS_UFS_REG_HCLKDIV 0xFC +#define CDNS_UFS_REG_PHY_XCFGD1 0x113C + +static int cdns_ufs_link_startup_notify(struct ufs_hba *hba, + enum ufs_notify_change_status status) +{ + hba->quirks |= UFSHCD_QUIRK_BROKEN_LCC; + switch (status) { + case PRE_CHANGE: + return ufshcd_dme_set(hba, + UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE), + 0); + case POST_CHANGE: + ; + } + + return 0; +} + +static int cdns_ufs_set_hclkdiv(struct ufs_hba *hba) +{ + struct clk clk; + unsigned long core_clk_rate = 0; + u32 core_clk_div = 0; + int ret; + + ret = clk_get_by_name(hba->dev, "core_clk", &clk); + if (ret) { + dev_err(hba->dev, "failed to get core_clk clock\n"); + return ret; + } + + core_clk_rate = clk_get_rate(&clk); + if (IS_ERR_VALUE(core_clk_rate)) { + dev_err(hba->dev, "%s: unable to find core_clk rate\n", + __func__); + return core_clk_rate; + } + + core_clk_div = core_clk_rate / USEC_PER_SEC; + ufshcd_writel(hba, core_clk_div, CDNS_UFS_REG_HCLKDIV); + + return 0; +} + +static int cdns_ufs_hce_enable_notify(struct ufs_hba *hba, + enum ufs_notify_change_status status) +{ + switch (status) { + case PRE_CHANGE: + return cdns_ufs_set_hclkdiv(hba); + case POST_CHANGE: + ; + } + + return 0; +} + +static int cdns_ufs_init(struct ufs_hba *hba) +{ + u32 data; + + /* Increase RX_Advanced_Min_ActivateTime_Capability */ + data = ufshcd_readl(hba, CDNS_UFS_REG_PHY_XCFGD1); + data |= BIT(24); + ufshcd_writel(hba, data, CDNS_UFS_REG_PHY_XCFGD1); + + return 0; +} + +static struct ufs_hba_ops cdns_pltfm_hba_ops = { + .init = cdns_ufs_init, + .hce_enable_notify = cdns_ufs_hce_enable_notify, + .link_startup_notify = cdns_ufs_link_startup_notify, +}; + +static int cdns_ufs_pltfm_probe(struct udevice *dev) +{ + int err = ufshcd_probe(dev, &cdns_pltfm_hba_ops); + if (err) + dev_err(dev, "ufshcd_probe() failed %d\n", err); + + return err; +} + +static int cdns_ufs_pltfm_bind(struct udevice *dev) +{ + struct udevice *scsi_dev; + + return ufs_scsi_bind(dev, &scsi_dev); +} + +static const struct udevice_id cdns_ufs_pltfm_ids[] = { + { + .compatible = "cdns,ufshc-m31-16nm", + }, + {}, +}; + +U_BOOT_DRIVER(cdns_ufs_pltfm) = { + .name = "cdns-ufs-pltfm", + .id = UCLASS_UFS, + .of_match = cdns_ufs_pltfm_ids, + .probe = cdns_ufs_pltfm_probe, + .bind = cdns_ufs_pltfm_bind, +}; diff --git a/drivers/ufs/ti-j721e-ufs.c b/drivers/ufs/ti-j721e-ufs.c new file mode 100644 index 0000000..24ec3eb --- /dev/null +++ b/drivers/ufs/ti-j721e-ufs.c @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ + */ + +#include <asm/io.h> +#include <clk.h> +#include <common.h> +#include <dm.h> + +#define UFS_SS_CTRL 0x4 +#define UFS_SS_RST_N_PCS BIT(0) +#define UFS_SS_CLK_26MHZ BIT(4) + +static int ti_j721e_ufs_probe(struct udevice *dev) +{ + void __iomem *base; + unsigned int clock; + struct clk clk; + u32 reg = 0; + int ret; + + ret = clk_get_by_index(dev, 0, &clk); + if (ret) { + dev_err(dev, "failed to get M-PHY clock\n"); + return ret; + } + + clock = clk_get_rate(&clk); + if (IS_ERR_VALUE(clock)) { + dev_err(dev, "failed to get rate\n"); + return ret; + } + + base = dev_remap_addr_index(dev, 0); + + if (clock == 26000000) + reg |= UFS_SS_CLK_26MHZ; + /* Take UFS slave device out of reset */ + reg |= UFS_SS_RST_N_PCS; + writel(reg, base + UFS_SS_CTRL); + + return 0; +} + +static int ti_j721e_ufs_remove(struct udevice *dev) +{ + void __iomem *base = dev_remap_addr_index(dev, 0); + u32 reg = readl(base + UFS_SS_CTRL); + + reg &= ~UFS_SS_RST_N_PCS; + writel(reg, base + UFS_SS_CTRL); + + return 0; +} + +static const struct udevice_id ti_j721e_ufs_ids[] = { + { + .compatible = "ti,j721e-ufs", + }, + {}, +}; + +U_BOOT_DRIVER(ti_j721e_ufs) = { + .name = "ti-j721e-ufs", + .id = UCLASS_MISC, + .of_match = ti_j721e_ufs_ids, + .probe = ti_j721e_ufs_probe, + .remove = ti_j721e_ufs_remove, + .flags = DM_FLAG_OS_PREPARE, +}; diff --git a/drivers/ufs/ufs-uclass.c b/drivers/ufs/ufs-uclass.c new file mode 100644 index 0000000..920bfa6 --- /dev/null +++ b/drivers/ufs/ufs-uclass.c @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * ufs-uclass.c - Universal Flash Subsystem (UFS) Uclass driver + * + * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com + */ + +#include <common.h> +#include "ufs.h" +#include <dm.h> + +UCLASS_DRIVER(ufs) = { + .id = UCLASS_UFS, + .name = "ufs", + .per_device_auto_alloc_size = sizeof(struct ufs_hba), +}; diff --git a/drivers/ufs/ufs.c b/drivers/ufs/ufs.c new file mode 100644 index 0000000..2330686 --- /dev/null +++ b/drivers/ufs/ufs.c @@ -0,0 +1,1968 @@ +// SPDX-License-Identifier: GPL-2.0+ +/** + * ufs.c - Universal Flash Subsystem (UFS) driver + * + * Taken from Linux Kernel v5.2 (drivers/scsi/ufs/ufshcd.c) and ported + * to u-boot. + * + * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com + */ + +#include <charset.h> +#include <common.h> +#include <dm.h> +#include <dm/lists.h> +#include <dm/device-internal.h> +#include <malloc.h> +#include <hexdump.h> +#include <scsi.h> + +#include <asm/dma-mapping.h> + +#include "ufs.h" + +#define UFSHCD_ENABLE_INTRS (UTP_TRANSFER_REQ_COMPL |\ + UTP_TASK_REQ_COMPL |\ + UFSHCD_ERROR_MASK) +/* maximum number of link-startup retries */ +#define DME_LINKSTARTUP_RETRIES 3 + +/* maximum number of retries for a general UIC command */ +#define UFS_UIC_COMMAND_RETRIES 3 + +/* Query request retries */ +#define QUERY_REQ_RETRIES 3 +/* Query request timeout */ +#define QUERY_REQ_TIMEOUT 1500 /* 1.5 seconds */ + +/* maximum timeout in ms for a general UIC command */ +#define UFS_UIC_CMD_TIMEOUT 1000 +/* NOP OUT retries waiting for NOP IN response */ +#define NOP_OUT_RETRIES 10 +/* Timeout after 30 msecs if NOP OUT hangs without response */ +#define NOP_OUT_TIMEOUT 30 /* msecs */ + +/* Only use one Task Tag for all requests */ +#define TASK_TAG 0 + +/* Expose the flag value from utp_upiu_query.value */ +#define MASK_QUERY_UPIU_FLAG_LOC 0xFF + +#define MAX_PRDT_ENTRY 262144 + +/* maximum bytes per request */ +#define UFS_MAX_BYTES (128 * 256 * 1024) + +static inline bool ufshcd_is_hba_active(struct ufs_hba *hba); +static inline void ufshcd_hba_stop(struct ufs_hba *hba); +static int ufshcd_hba_enable(struct ufs_hba *hba); + +/* + * ufshcd_wait_for_register - wait for register value to change + */ +static int ufshcd_wait_for_register(struct ufs_hba *hba, u32 reg, u32 mask, + u32 val, unsigned long timeout_ms) +{ + int err = 0; + unsigned long start = get_timer(0); + + /* ignore bits that we don't intend to wait on */ + val = val & mask; + + while ((ufshcd_readl(hba, reg) & mask) != val) { + if (get_timer(start) > timeout_ms) { + if ((ufshcd_readl(hba, reg) & mask) != val) + err = -ETIMEDOUT; + break; + } + } + + return err; +} + +/** + * ufshcd_init_pwr_info - setting the POR (power on reset) + * values in hba power info + */ +static void ufshcd_init_pwr_info(struct ufs_hba *hba) +{ + hba->pwr_info.gear_rx = UFS_PWM_G1; + hba->pwr_info.gear_tx = UFS_PWM_G1; + hba->pwr_info.lane_rx = 1; + hba->pwr_info.lane_tx = 1; + hba->pwr_info.pwr_rx = SLOWAUTO_MODE; + hba->pwr_info.pwr_tx = SLOWAUTO_MODE; + hba->pwr_info.hs_rate = 0; +} + +/** + * ufshcd_print_pwr_info - print power params as saved in hba + * power info + */ +static void ufshcd_print_pwr_info(struct ufs_hba *hba) +{ + static const char * const names[] = { + "INVALID MODE", + "FAST MODE", + "SLOW_MODE", + "INVALID MODE", + "FASTAUTO_MODE", + "SLOWAUTO_MODE", + "INVALID MODE", + }; + + dev_err(hba->dev, "[RX, TX]: gear=[%d, %d], lane[%d, %d], pwr[%s, %s], rate = %d\n", + hba->pwr_info.gear_rx, hba->pwr_info.gear_tx, + hba->pwr_info.lane_rx, hba->pwr_info.lane_tx, + names[hba->pwr_info.pwr_rx], + names[hba->pwr_info.pwr_tx], + hba->pwr_info.hs_rate); +} + +/** + * ufshcd_ready_for_uic_cmd - Check if controller is ready + * to accept UIC commands + */ +static inline bool ufshcd_ready_for_uic_cmd(struct ufs_hba *hba) +{ + if (ufshcd_readl(hba, REG_CONTROLLER_STATUS) & UIC_COMMAND_READY) + return true; + else + return false; +} + +/** + * ufshcd_get_uic_cmd_result - Get the UIC command result + */ +static inline int ufshcd_get_uic_cmd_result(struct ufs_hba *hba) +{ + return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_2) & + MASK_UIC_COMMAND_RESULT; +} + +/** + * ufshcd_get_dme_attr_val - Get the value of attribute returned by UIC command + */ +static inline u32 ufshcd_get_dme_attr_val(struct ufs_hba *hba) +{ + return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_3); +} + +/** + * ufshcd_is_device_present - Check if any device connected to + * the host controller + */ +static inline bool ufshcd_is_device_present(struct ufs_hba *hba) +{ + return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) & + DEVICE_PRESENT) ? true : false; +} + +/** + * ufshcd_send_uic_cmd - UFS Interconnect layer command API + * + */ +static int ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd) +{ + unsigned long start = 0; + u32 intr_status; + u32 enabled_intr_status; + + if (!ufshcd_ready_for_uic_cmd(hba)) { + dev_err(hba->dev, + "Controller not ready to accept UIC commands\n"); + return -EIO; + } + + debug("sending uic command:%d\n", uic_cmd->command); + + /* Write Args */ + ufshcd_writel(hba, uic_cmd->argument1, REG_UIC_COMMAND_ARG_1); + ufshcd_writel(hba, uic_cmd->argument2, REG_UIC_COMMAND_ARG_2); + ufshcd_writel(hba, uic_cmd->argument3, REG_UIC_COMMAND_ARG_3); + + /* Write UIC Cmd */ + ufshcd_writel(hba, uic_cmd->command & COMMAND_OPCODE_MASK, + REG_UIC_COMMAND); + + start = get_timer(0); + do { + intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS); + enabled_intr_status = intr_status & hba->intr_mask; + ufshcd_writel(hba, intr_status, REG_INTERRUPT_STATUS); + + if (get_timer(start) > UFS_UIC_CMD_TIMEOUT) { + dev_err(hba->dev, + "Timedout waiting for UIC response\n"); + + return -ETIMEDOUT; + } + + if (enabled_intr_status & UFSHCD_ERROR_MASK) { + dev_err(hba->dev, "Error in status:%08x\n", + enabled_intr_status); + + return -1; + } + } while (!(enabled_intr_status & UFSHCD_UIC_MASK)); + + uic_cmd->argument2 = ufshcd_get_uic_cmd_result(hba); + uic_cmd->argument3 = ufshcd_get_dme_attr_val(hba); + + debug("Sent successfully\n"); + + return 0; +} + +/** + * ufshcd_dme_set_attr - UIC command for DME_SET, DME_PEER_SET + * + */ +int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel, u8 attr_set, + u32 mib_val, u8 peer) +{ + struct uic_command uic_cmd = {0}; + static const char *const action[] = { + "dme-set", + "dme-peer-set" + }; + const char *set = action[!!peer]; + int ret; + int retries = UFS_UIC_COMMAND_RETRIES; + + uic_cmd.command = peer ? + UIC_CMD_DME_PEER_SET : UIC_CMD_DME_SET; + uic_cmd.argument1 = attr_sel; + uic_cmd.argument2 = UIC_ARG_ATTR_TYPE(attr_set); + uic_cmd.argument3 = mib_val; + + do { + /* for peer attributes we retry upon failure */ + ret = ufshcd_send_uic_cmd(hba, &uic_cmd); + if (ret) + dev_dbg(hba->dev, "%s: attr-id 0x%x val 0x%x error code %d\n", + set, UIC_GET_ATTR_ID(attr_sel), mib_val, ret); + } while (ret && peer && --retries); + + if (ret) + dev_err(hba->dev, "%s: attr-id 0x%x val 0x%x failed %d retries\n", + set, UIC_GET_ATTR_ID(attr_sel), mib_val, + UFS_UIC_COMMAND_RETRIES - retries); + + return ret; +} + +/** + * ufshcd_dme_get_attr - UIC command for DME_GET, DME_PEER_GET + * + */ +int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel, + u32 *mib_val, u8 peer) +{ + struct uic_command uic_cmd = {0}; + static const char *const action[] = { + "dme-get", + "dme-peer-get" + }; + const char *get = action[!!peer]; + int ret; + int retries = UFS_UIC_COMMAND_RETRIES; + + uic_cmd.command = peer ? + UIC_CMD_DME_PEER_GET : UIC_CMD_DME_GET; + uic_cmd.argument1 = attr_sel; + + do { + /* for peer attributes we retry upon failure */ + ret = ufshcd_send_uic_cmd(hba, &uic_cmd); + if (ret) + dev_dbg(hba->dev, "%s: attr-id 0x%x error code %d\n", + get, UIC_GET_ATTR_ID(attr_sel), ret); + } while (ret && peer && --retries); + + if (ret) + dev_err(hba->dev, "%s: attr-id 0x%x failed %d retries\n", + get, UIC_GET_ATTR_ID(attr_sel), + UFS_UIC_COMMAND_RETRIES - retries); + + if (mib_val && !ret) + *mib_val = uic_cmd.argument3; + + return ret; +} + +static int ufshcd_disable_tx_lcc(struct ufs_hba *hba, bool peer) +{ + u32 tx_lanes, i, err = 0; + + if (!peer) + ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES), + &tx_lanes); + else + ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES), + &tx_lanes); + for (i = 0; i < tx_lanes; i++) { + if (!peer) + err = ufshcd_dme_set(hba, + UIC_ARG_MIB_SEL(TX_LCC_ENABLE, + UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)), + 0); + else + err = ufshcd_dme_peer_set(hba, + UIC_ARG_MIB_SEL(TX_LCC_ENABLE, + UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)), + 0); + if (err) { + dev_err(hba->dev, "%s: TX LCC Disable failed, peer = %d, lane = %d, err = %d", + __func__, peer, i, err); + break; + } + } + + return err; +} + +static inline int ufshcd_disable_device_tx_lcc(struct ufs_hba *hba) +{ + return ufshcd_disable_tx_lcc(hba, true); +} + +/** + * ufshcd_dme_link_startup - Notify Unipro to perform link startup + * + */ +static int ufshcd_dme_link_startup(struct ufs_hba *hba) +{ + struct uic_command uic_cmd = {0}; + int ret; + + uic_cmd.command = UIC_CMD_DME_LINK_STARTUP; + + ret = ufshcd_send_uic_cmd(hba, &uic_cmd); + if (ret) + dev_dbg(hba->dev, + "dme-link-startup: error code %d\n", ret); + return ret; +} + +/** + * ufshcd_disable_intr_aggr - Disables interrupt aggregation. + * + */ +static inline void ufshcd_disable_intr_aggr(struct ufs_hba *hba) +{ + ufshcd_writel(hba, 0, REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL); +} + +/** + * ufshcd_get_lists_status - Check UCRDY, UTRLRDY and UTMRLRDY + */ +static inline int ufshcd_get_lists_status(u32 reg) +{ + return !((reg & UFSHCD_STATUS_READY) == UFSHCD_STATUS_READY); +} + +/** + * ufshcd_enable_run_stop_reg - Enable run-stop registers, + * When run-stop registers are set to 1, it indicates the + * host controller that it can process the requests + */ +static void ufshcd_enable_run_stop_reg(struct ufs_hba *hba) +{ + ufshcd_writel(hba, UTP_TASK_REQ_LIST_RUN_STOP_BIT, + REG_UTP_TASK_REQ_LIST_RUN_STOP); + ufshcd_writel(hba, UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT, + REG_UTP_TRANSFER_REQ_LIST_RUN_STOP); +} + +/** + * ufshcd_enable_intr - enable interrupts + */ +static void ufshcd_enable_intr(struct ufs_hba *hba, u32 intrs) +{ + u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE); + u32 rw; + + if (hba->version == UFSHCI_VERSION_10) { + rw = set & INTERRUPT_MASK_RW_VER_10; + set = rw | ((set ^ intrs) & intrs); + } else { + set |= intrs; + } + + ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE); + + hba->intr_mask = set; +} + +/** + * ufshcd_make_hba_operational - Make UFS controller operational + * + * To bring UFS host controller to operational state, + * 1. Enable required interrupts + * 2. Configure interrupt aggregation + * 3. Program UTRL and UTMRL base address + * 4. Configure run-stop-registers + * + */ +static int ufshcd_make_hba_operational(struct ufs_hba *hba) +{ + int err = 0; + u32 reg; + + /* Enable required interrupts */ + ufshcd_enable_intr(hba, UFSHCD_ENABLE_INTRS); + + /* Disable interrupt aggregation */ + ufshcd_disable_intr_aggr(hba); + + /* Configure UTRL and UTMRL base address registers */ + ufshcd_writel(hba, lower_32_bits((dma_addr_t)hba->utrdl), + REG_UTP_TRANSFER_REQ_LIST_BASE_L); + ufshcd_writel(hba, upper_32_bits((dma_addr_t)hba->utrdl), + REG_UTP_TRANSFER_REQ_LIST_BASE_H); + ufshcd_writel(hba, lower_32_bits((dma_addr_t)hba->utmrdl), + REG_UTP_TASK_REQ_LIST_BASE_L); + ufshcd_writel(hba, upper_32_bits((dma_addr_t)hba->utmrdl), + REG_UTP_TASK_REQ_LIST_BASE_H); + + /* + * UCRDY, UTMRLDY and UTRLRDY bits must be 1 + */ + reg = ufshcd_readl(hba, REG_CONTROLLER_STATUS); + if (!(ufshcd_get_lists_status(reg))) { + ufshcd_enable_run_stop_reg(hba); + } else { + dev_err(hba->dev, + "Host controller not ready to process requests"); + err = -EIO; + goto out; + } + +out: + return err; +} + +/** + * ufshcd_link_startup - Initialize unipro link startup + */ +static int ufshcd_link_startup(struct ufs_hba *hba) +{ + int ret; + int retries = DME_LINKSTARTUP_RETRIES; + bool link_startup_again = true; + +link_startup: + do { + ufshcd_ops_link_startup_notify(hba, PRE_CHANGE); + + ret = ufshcd_dme_link_startup(hba); + + /* check if device is detected by inter-connect layer */ + if (!ret && !ufshcd_is_device_present(hba)) { + dev_err(hba->dev, "%s: Device not present\n", __func__); + ret = -ENXIO; + goto out; + } + + /* + * DME link lost indication is only received when link is up, + * but we can't be sure if the link is up until link startup + * succeeds. So reset the local Uni-Pro and try again. + */ + if (ret && ufshcd_hba_enable(hba)) + goto out; + } while (ret && retries--); + + if (ret) + /* failed to get the link up... retire */ + goto out; + + if (link_startup_again) { + link_startup_again = false; + retries = DME_LINKSTARTUP_RETRIES; + goto link_startup; + } + + /* Mark that link is up in PWM-G1, 1-lane, SLOW-AUTO mode */ + ufshcd_init_pwr_info(hba); + + if (hba->quirks & UFSHCD_QUIRK_BROKEN_LCC) { + ret = ufshcd_disable_device_tx_lcc(hba); + if (ret) + goto out; + } + + /* Include any host controller configuration via UIC commands */ + ret = ufshcd_ops_link_startup_notify(hba, POST_CHANGE); + if (ret) + goto out; + + ret = ufshcd_make_hba_operational(hba); +out: + if (ret) + dev_err(hba->dev, "link startup failed %d\n", ret); + + return ret; +} + +/** + * ufshcd_hba_stop - Send controller to reset state + */ +static inline void ufshcd_hba_stop(struct ufs_hba *hba) +{ + int err; + + ufshcd_writel(hba, CONTROLLER_DISABLE, REG_CONTROLLER_ENABLE); + err = ufshcd_wait_for_register(hba, REG_CONTROLLER_ENABLE, + CONTROLLER_ENABLE, CONTROLLER_DISABLE, + 10); + if (err) + dev_err(hba->dev, "%s: Controller disable failed\n", __func__); +} + +/** + * ufshcd_is_hba_active - Get controller state + */ +static inline bool ufshcd_is_hba_active(struct ufs_hba *hba) +{ + return (ufshcd_readl(hba, REG_CONTROLLER_ENABLE) & CONTROLLER_ENABLE) + ? false : true; +} + +/** + * ufshcd_hba_start - Start controller initialization sequence + */ +static inline void ufshcd_hba_start(struct ufs_hba *hba) +{ + ufshcd_writel(hba, CONTROLLER_ENABLE, REG_CONTROLLER_ENABLE); +} + +/** + * ufshcd_hba_enable - initialize the controller + */ +static int ufshcd_hba_enable(struct ufs_hba *hba) +{ + int retry; + + if (!ufshcd_is_hba_active(hba)) + /* change controller state to "reset state" */ + ufshcd_hba_stop(hba); + + ufshcd_ops_hce_enable_notify(hba, PRE_CHANGE); + + /* start controller initialization sequence */ + ufshcd_hba_start(hba); + + /* + * To initialize a UFS host controller HCE bit must be set to 1. + * During initialization the HCE bit value changes from 1->0->1. + * When the host controller completes initialization sequence + * it sets the value of HCE bit to 1. The same HCE bit is read back + * to check if the controller has completed initialization sequence. + * So without this delay the value HCE = 1, set in the previous + * instruction might be read back. + * This delay can be changed based on the controller. + */ + mdelay(1); + + /* wait for the host controller to complete initialization */ + retry = 10; + while (ufshcd_is_hba_active(hba)) { + if (retry) { + retry--; + } else { + dev_err(hba->dev, "Controller enable failed\n"); + return -EIO; + } + mdelay(5); + } + + /* enable UIC related interrupts */ + ufshcd_enable_intr(hba, UFSHCD_UIC_MASK); + + ufshcd_ops_hce_enable_notify(hba, POST_CHANGE); + + return 0; +} + +/** + * ufshcd_host_memory_configure - configure local reference block with + * memory offsets + */ +static void ufshcd_host_memory_configure(struct ufs_hba *hba) +{ + struct utp_transfer_req_desc *utrdlp; + dma_addr_t cmd_desc_dma_addr; + u16 response_offset; + u16 prdt_offset; + + utrdlp = hba->utrdl; + cmd_desc_dma_addr = (dma_addr_t)hba->ucdl; + + utrdlp->command_desc_base_addr_lo = + cpu_to_le32(lower_32_bits(cmd_desc_dma_addr)); + utrdlp->command_desc_base_addr_hi = + cpu_to_le32(upper_32_bits(cmd_desc_dma_addr)); + + response_offset = offsetof(struct utp_transfer_cmd_desc, response_upiu); + prdt_offset = offsetof(struct utp_transfer_cmd_desc, prd_table); + + utrdlp->response_upiu_offset = cpu_to_le16(response_offset >> 2); + utrdlp->prd_table_offset = cpu_to_le16(prdt_offset >> 2); + utrdlp->response_upiu_length = cpu_to_le16(ALIGNED_UPIU_SIZE >> 2); + + hba->ucd_req_ptr = (struct utp_upiu_req *)hba->ucdl; + hba->ucd_rsp_ptr = + (struct utp_upiu_rsp *)&hba->ucdl->response_upiu; + hba->ucd_prdt_ptr = + (struct ufshcd_sg_entry *)&hba->ucdl->prd_table; +} + +/** + * ufshcd_memory_alloc - allocate memory for host memory space data structures + */ +static int ufshcd_memory_alloc(struct ufs_hba *hba) +{ + /* Allocate one Transfer Request Descriptor + * Should be aligned to 1k boundary. + */ + hba->utrdl = memalign(1024, sizeof(struct utp_transfer_req_desc)); + if (!hba->utrdl) { + dev_err(hba->dev, "Transfer Descriptor memory allocation failed\n"); + return -ENOMEM; + } + + /* Allocate one Command Descriptor + * Should be aligned to 1k boundary. + */ + hba->ucdl = memalign(1024, sizeof(struct utp_transfer_cmd_desc)); + if (!hba->ucdl) { + dev_err(hba->dev, "Command descriptor memory allocation failed\n"); + return -ENOMEM; + } + + return 0; +} + +/** + * ufshcd_get_intr_mask - Get the interrupt bit mask + */ +static inline u32 ufshcd_get_intr_mask(struct ufs_hba *hba) +{ + u32 intr_mask = 0; + + switch (hba->version) { + case UFSHCI_VERSION_10: + intr_mask = INTERRUPT_MASK_ALL_VER_10; + break; + case UFSHCI_VERSION_11: + case UFSHCI_VERSION_20: + intr_mask = INTERRUPT_MASK_ALL_VER_11; + break; + case UFSHCI_VERSION_21: + default: + intr_mask = INTERRUPT_MASK_ALL_VER_21; + break; + } + + return intr_mask; +} + +/** + * ufshcd_get_ufs_version - Get the UFS version supported by the HBA + */ +static inline u32 ufshcd_get_ufs_version(struct ufs_hba *hba) +{ + return ufshcd_readl(hba, REG_UFS_VERSION); +} + +/** + * ufshcd_get_upmcrs - Get the power mode change request status + */ +static inline u8 ufshcd_get_upmcrs(struct ufs_hba *hba) +{ + return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) >> 8) & 0x7; +} + +/** + * ufshcd_prepare_req_desc_hdr() - Fills the requests header + * descriptor according to request + */ +static void ufshcd_prepare_req_desc_hdr(struct utp_transfer_req_desc *req_desc, + u32 *upiu_flags, + enum dma_data_direction cmd_dir) +{ + u32 data_direction; + u32 dword_0; + + if (cmd_dir == DMA_FROM_DEVICE) { + data_direction = UTP_DEVICE_TO_HOST; + *upiu_flags = UPIU_CMD_FLAGS_READ; + } else if (cmd_dir == DMA_TO_DEVICE) { + data_direction = UTP_HOST_TO_DEVICE; + *upiu_flags = UPIU_CMD_FLAGS_WRITE; + } else { + data_direction = UTP_NO_DATA_TRANSFER; + *upiu_flags = UPIU_CMD_FLAGS_NONE; + } + + dword_0 = data_direction | (0x1 << UPIU_COMMAND_TYPE_OFFSET); + + /* Enable Interrupt for command */ + dword_0 |= UTP_REQ_DESC_INT_CMD; + + /* Transfer request descriptor header fields */ + req_desc->header.dword_0 = cpu_to_le32(dword_0); + /* dword_1 is reserved, hence it is set to 0 */ + req_desc->header.dword_1 = 0; + /* + * assigning invalid value for command status. Controller + * updates OCS on command completion, with the command + * status + */ + req_desc->header.dword_2 = + cpu_to_le32(OCS_INVALID_COMMAND_STATUS); + /* dword_3 is reserved, hence it is set to 0 */ + req_desc->header.dword_3 = 0; + + req_desc->prd_table_length = 0; +} + +static void ufshcd_prepare_utp_query_req_upiu(struct ufs_hba *hba, + u32 upiu_flags) +{ + struct utp_upiu_req *ucd_req_ptr = hba->ucd_req_ptr; + struct ufs_query *query = &hba->dev_cmd.query; + u16 len = be16_to_cpu(query->request.upiu_req.length); + + /* Query request header */ + ucd_req_ptr->header.dword_0 = + UPIU_HEADER_DWORD(UPIU_TRANSACTION_QUERY_REQ, + upiu_flags, 0, TASK_TAG); + ucd_req_ptr->header.dword_1 = + UPIU_HEADER_DWORD(0, query->request.query_func, + 0, 0); + + /* Data segment length only need for WRITE_DESC */ + if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC) + ucd_req_ptr->header.dword_2 = + UPIU_HEADER_DWORD(0, 0, (len >> 8), (u8)len); + else + ucd_req_ptr->header.dword_2 = 0; + + /* Copy the Query Request buffer as is */ + memcpy(&ucd_req_ptr->qr, &query->request.upiu_req, QUERY_OSF_SIZE); + + /* Copy the Descriptor */ + if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC) + memcpy(ucd_req_ptr + 1, query->descriptor, len); + + memset(hba->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp)); +} + +static inline void ufshcd_prepare_utp_nop_upiu(struct ufs_hba *hba) +{ + struct utp_upiu_req *ucd_req_ptr = hba->ucd_req_ptr; + + memset(ucd_req_ptr, 0, sizeof(struct utp_upiu_req)); + + /* command descriptor fields */ + ucd_req_ptr->header.dword_0 = + UPIU_HEADER_DWORD(UPIU_TRANSACTION_NOP_OUT, 0, 0, 0x1f); + /* clear rest of the fields of basic header */ + ucd_req_ptr->header.dword_1 = 0; + ucd_req_ptr->header.dword_2 = 0; + + memset(hba->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp)); +} + +/** + * ufshcd_comp_devman_upiu - UFS Protocol Information Unit(UPIU) + * for Device Management Purposes + */ +static int ufshcd_comp_devman_upiu(struct ufs_hba *hba, + enum dev_cmd_type cmd_type) +{ + u32 upiu_flags; + int ret = 0; + struct utp_transfer_req_desc *req_desc = hba->utrdl; + + hba->dev_cmd.type = cmd_type; + + ufshcd_prepare_req_desc_hdr(req_desc, &upiu_flags, DMA_NONE); + switch (cmd_type) { + case DEV_CMD_TYPE_QUERY: + ufshcd_prepare_utp_query_req_upiu(hba, upiu_flags); + break; + case DEV_CMD_TYPE_NOP: + ufshcd_prepare_utp_nop_upiu(hba); + break; + default: + ret = -EINVAL; + } + + return ret; +} + +static int ufshcd_send_command(struct ufs_hba *hba, unsigned int task_tag) +{ + unsigned long start; + u32 intr_status; + u32 enabled_intr_status; + + ufshcd_writel(hba, 1 << task_tag, REG_UTP_TRANSFER_REQ_DOOR_BELL); + + start = get_timer(0); + do { + intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS); + enabled_intr_status = intr_status & hba->intr_mask; + ufshcd_writel(hba, intr_status, REG_INTERRUPT_STATUS); + + if (get_timer(start) > QUERY_REQ_TIMEOUT) { + dev_err(hba->dev, + "Timedout waiting for UTP response\n"); + + return -ETIMEDOUT; + } + + if (enabled_intr_status & UFSHCD_ERROR_MASK) { + dev_err(hba->dev, "Error in status:%08x\n", + enabled_intr_status); + + return -1; + } + } while (!(enabled_intr_status & UTP_TRANSFER_REQ_COMPL)); + + return 0; +} + +/** + * ufshcd_get_req_rsp - returns the TR response transaction type + */ +static inline int ufshcd_get_req_rsp(struct utp_upiu_rsp *ucd_rsp_ptr) +{ + return be32_to_cpu(ucd_rsp_ptr->header.dword_0) >> 24; +} + +/** + * ufshcd_get_tr_ocs - Get the UTRD Overall Command Status + * + */ +static inline int ufshcd_get_tr_ocs(struct ufs_hba *hba) +{ + return le32_to_cpu(hba->utrdl->header.dword_2) & MASK_OCS; +} + +static inline int ufshcd_get_rsp_upiu_result(struct utp_upiu_rsp *ucd_rsp_ptr) +{ + return be32_to_cpu(ucd_rsp_ptr->header.dword_1) & MASK_RSP_UPIU_RESULT; +} + +static int ufshcd_check_query_response(struct ufs_hba *hba) +{ + struct ufs_query_res *query_res = &hba->dev_cmd.query.response; + + /* Get the UPIU response */ + query_res->response = ufshcd_get_rsp_upiu_result(hba->ucd_rsp_ptr) >> + UPIU_RSP_CODE_OFFSET; + return query_res->response; +} + +/** + * ufshcd_copy_query_response() - Copy the Query Response and the data + * descriptor + */ +static int ufshcd_copy_query_response(struct ufs_hba *hba) +{ + struct ufs_query_res *query_res = &hba->dev_cmd.query.response; + + memcpy(&query_res->upiu_res, &hba->ucd_rsp_ptr->qr, QUERY_OSF_SIZE); + + /* Get the descriptor */ + if (hba->dev_cmd.query.descriptor && + hba->ucd_rsp_ptr->qr.opcode == UPIU_QUERY_OPCODE_READ_DESC) { + u8 *descp = (u8 *)hba->ucd_rsp_ptr + + GENERAL_UPIU_REQUEST_SIZE; + u16 resp_len; + u16 buf_len; + + /* data segment length */ + resp_len = be32_to_cpu(hba->ucd_rsp_ptr->header.dword_2) & + MASK_QUERY_DATA_SEG_LEN; + buf_len = + be16_to_cpu(hba->dev_cmd.query.request.upiu_req.length); + if (likely(buf_len >= resp_len)) { + memcpy(hba->dev_cmd.query.descriptor, descp, resp_len); + } else { + dev_warn(hba->dev, + "%s: Response size is bigger than buffer", + __func__); + return -EINVAL; + } + } + + return 0; +} + +/** + * ufshcd_exec_dev_cmd - API for sending device management requests + */ +static int ufshcd_exec_dev_cmd(struct ufs_hba *hba, enum dev_cmd_type cmd_type, + int timeout) +{ + int err; + int resp; + + err = ufshcd_comp_devman_upiu(hba, cmd_type); + if (err) + return err; + + err = ufshcd_send_command(hba, TASK_TAG); + if (err) + return err; + + err = ufshcd_get_tr_ocs(hba); + if (err) { + dev_err(hba->dev, "Error in OCS:%d\n", err); + return -EINVAL; + } + + resp = ufshcd_get_req_rsp(hba->ucd_rsp_ptr); + switch (resp) { + case UPIU_TRANSACTION_NOP_IN: + break; + case UPIU_TRANSACTION_QUERY_RSP: + err = ufshcd_check_query_response(hba); + if (!err) + err = ufshcd_copy_query_response(hba); + break; + case UPIU_TRANSACTION_REJECT_UPIU: + /* TODO: handle Reject UPIU Response */ + err = -EPERM; + dev_err(hba->dev, "%s: Reject UPIU not fully implemented\n", + __func__); + break; + default: + err = -EINVAL; + dev_err(hba->dev, "%s: Invalid device management cmd response: %x\n", + __func__, resp); + } + + return err; +} + +/** + * ufshcd_init_query() - init the query response and request parameters + */ +static inline void ufshcd_init_query(struct ufs_hba *hba, + struct ufs_query_req **request, + struct ufs_query_res **response, + enum query_opcode opcode, + u8 idn, u8 index, u8 selector) +{ + *request = &hba->dev_cmd.query.request; + *response = &hba->dev_cmd.query.response; + memset(*request, 0, sizeof(struct ufs_query_req)); + memset(*response, 0, sizeof(struct ufs_query_res)); + (*request)->upiu_req.opcode = opcode; + (*request)->upiu_req.idn = idn; + (*request)->upiu_req.index = index; + (*request)->upiu_req.selector = selector; +} + +/** + * ufshcd_query_flag() - API function for sending flag query requests + */ +int ufshcd_query_flag(struct ufs_hba *hba, enum query_opcode opcode, + enum flag_idn idn, bool *flag_res) +{ + struct ufs_query_req *request = NULL; + struct ufs_query_res *response = NULL; + int err, index = 0, selector = 0; + int timeout = QUERY_REQ_TIMEOUT; + + ufshcd_init_query(hba, &request, &response, opcode, idn, index, + selector); + + switch (opcode) { + case UPIU_QUERY_OPCODE_SET_FLAG: + case UPIU_QUERY_OPCODE_CLEAR_FLAG: + case UPIU_QUERY_OPCODE_TOGGLE_FLAG: + request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST; + break; + case UPIU_QUERY_OPCODE_READ_FLAG: + request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST; + if (!flag_res) { + /* No dummy reads */ + dev_err(hba->dev, "%s: Invalid argument for read request\n", + __func__); + err = -EINVAL; + goto out; + } + break; + default: + dev_err(hba->dev, + "%s: Expected query flag opcode but got = %d\n", + __func__, opcode); + err = -EINVAL; + goto out; + } + + err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, timeout); + + if (err) { + dev_err(hba->dev, + "%s: Sending flag query for idn %d failed, err = %d\n", + __func__, idn, err); + goto out; + } + + if (flag_res) + *flag_res = (be32_to_cpu(response->upiu_res.value) & + MASK_QUERY_UPIU_FLAG_LOC) & 0x1; + +out: + return err; +} + +static int ufshcd_query_flag_retry(struct ufs_hba *hba, + enum query_opcode opcode, + enum flag_idn idn, bool *flag_res) +{ + int ret; + int retries; + + for (retries = 0; retries < QUERY_REQ_RETRIES; retries++) { + ret = ufshcd_query_flag(hba, opcode, idn, flag_res); + if (ret) + dev_dbg(hba->dev, + "%s: failed with error %d, retries %d\n", + __func__, ret, retries); + else + break; + } + + if (ret) + dev_err(hba->dev, + "%s: query attribute, opcode %d, idn %d, failed with error %d after %d retires\n", + __func__, opcode, idn, ret, retries); + return ret; +} + +static int __ufshcd_query_descriptor(struct ufs_hba *hba, + enum query_opcode opcode, + enum desc_idn idn, u8 index, u8 selector, + u8 *desc_buf, int *buf_len) +{ + struct ufs_query_req *request = NULL; + struct ufs_query_res *response = NULL; + int err; + + if (!desc_buf) { + dev_err(hba->dev, "%s: descriptor buffer required for opcode 0x%x\n", + __func__, opcode); + err = -EINVAL; + goto out; + } + + if (*buf_len < QUERY_DESC_MIN_SIZE || *buf_len > QUERY_DESC_MAX_SIZE) { + dev_err(hba->dev, "%s: descriptor buffer size (%d) is out of range\n", + __func__, *buf_len); + err = -EINVAL; + goto out; + } + + ufshcd_init_query(hba, &request, &response, opcode, idn, index, + selector); + hba->dev_cmd.query.descriptor = desc_buf; + request->upiu_req.length = cpu_to_be16(*buf_len); + + switch (opcode) { + case UPIU_QUERY_OPCODE_WRITE_DESC: + request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST; + break; + case UPIU_QUERY_OPCODE_READ_DESC: + request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST; + break; + default: + dev_err(hba->dev, "%s: Expected query descriptor opcode but got = 0x%.2x\n", + __func__, opcode); + err = -EINVAL; + goto out; + } + + err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT); + + if (err) { + dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n", + __func__, opcode, idn, index, err); + goto out; + } + + hba->dev_cmd.query.descriptor = NULL; + *buf_len = be16_to_cpu(response->upiu_res.length); + +out: + return err; +} + +/** + * ufshcd_query_descriptor_retry - API function for sending descriptor requests + */ +int ufshcd_query_descriptor_retry(struct ufs_hba *hba, enum query_opcode opcode, + enum desc_idn idn, u8 index, u8 selector, + u8 *desc_buf, int *buf_len) +{ + int err; + int retries; + + for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) { + err = __ufshcd_query_descriptor(hba, opcode, idn, index, + selector, desc_buf, buf_len); + if (!err || err == -EINVAL) + break; + } + + return err; +} + +/** + * ufshcd_read_desc_length - read the specified descriptor length from header + */ +static int ufshcd_read_desc_length(struct ufs_hba *hba, enum desc_idn desc_id, + int desc_index, int *desc_length) +{ + int ret; + u8 header[QUERY_DESC_HDR_SIZE]; + int header_len = QUERY_DESC_HDR_SIZE; + + if (desc_id >= QUERY_DESC_IDN_MAX) + return -EINVAL; + + ret = ufshcd_query_descriptor_retry(hba, UPIU_QUERY_OPCODE_READ_DESC, + desc_id, desc_index, 0, header, + &header_len); + + if (ret) { + dev_err(hba->dev, "%s: Failed to get descriptor header id %d", + __func__, desc_id); + return ret; + } else if (desc_id != header[QUERY_DESC_DESC_TYPE_OFFSET]) { + dev_warn(hba->dev, "%s: descriptor header id %d and desc_id %d mismatch", + __func__, header[QUERY_DESC_DESC_TYPE_OFFSET], + desc_id); + ret = -EINVAL; + } + + *desc_length = header[QUERY_DESC_LENGTH_OFFSET]; + + return ret; +} + +static void ufshcd_init_desc_sizes(struct ufs_hba *hba) +{ + int err; + + err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_DEVICE, 0, + &hba->desc_size.dev_desc); + if (err) + hba->desc_size.dev_desc = QUERY_DESC_DEVICE_DEF_SIZE; + + err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_POWER, 0, + &hba->desc_size.pwr_desc); + if (err) + hba->desc_size.pwr_desc = QUERY_DESC_POWER_DEF_SIZE; + + err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_INTERCONNECT, 0, + &hba->desc_size.interc_desc); + if (err) + hba->desc_size.interc_desc = QUERY_DESC_INTERCONNECT_DEF_SIZE; + + err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_CONFIGURATION, 0, + &hba->desc_size.conf_desc); + if (err) + hba->desc_size.conf_desc = QUERY_DESC_CONFIGURATION_DEF_SIZE; + + err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_UNIT, 0, + &hba->desc_size.unit_desc); + if (err) + hba->desc_size.unit_desc = QUERY_DESC_UNIT_DEF_SIZE; + + err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_GEOMETRY, 0, + &hba->desc_size.geom_desc); + if (err) + hba->desc_size.geom_desc = QUERY_DESC_GEOMETRY_DEF_SIZE; + + err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_HEALTH, 0, + &hba->desc_size.hlth_desc); + if (err) + hba->desc_size.hlth_desc = QUERY_DESC_HEALTH_DEF_SIZE; +} + +/** + * ufshcd_map_desc_id_to_length - map descriptor IDN to its length + * + */ +int ufshcd_map_desc_id_to_length(struct ufs_hba *hba, enum desc_idn desc_id, + int *desc_len) +{ + switch (desc_id) { + case QUERY_DESC_IDN_DEVICE: + *desc_len = hba->desc_size.dev_desc; + break; + case QUERY_DESC_IDN_POWER: + *desc_len = hba->desc_size.pwr_desc; + break; + case QUERY_DESC_IDN_GEOMETRY: + *desc_len = hba->desc_size.geom_desc; + break; + case QUERY_DESC_IDN_CONFIGURATION: + *desc_len = hba->desc_size.conf_desc; + break; + case QUERY_DESC_IDN_UNIT: + *desc_len = hba->desc_size.unit_desc; + break; + case QUERY_DESC_IDN_INTERCONNECT: + *desc_len = hba->desc_size.interc_desc; + break; + case QUERY_DESC_IDN_STRING: + *desc_len = QUERY_DESC_MAX_SIZE; + break; + case QUERY_DESC_IDN_HEALTH: + *desc_len = hba->desc_size.hlth_desc; + break; + case QUERY_DESC_IDN_RFU_0: + case QUERY_DESC_IDN_RFU_1: + *desc_len = 0; + break; + default: + *desc_len = 0; + return -EINVAL; + } + return 0; +} +EXPORT_SYMBOL(ufshcd_map_desc_id_to_length); + +/** + * ufshcd_read_desc_param - read the specified descriptor parameter + * + */ +int ufshcd_read_desc_param(struct ufs_hba *hba, enum desc_idn desc_id, + int desc_index, u8 param_offset, u8 *param_read_buf, + u8 param_size) +{ + int ret; + u8 *desc_buf; + int buff_len; + bool is_kmalloc = true; + + /* Safety check */ + if (desc_id >= QUERY_DESC_IDN_MAX || !param_size) + return -EINVAL; + + /* Get the max length of descriptor from structure filled up at probe + * time. + */ + ret = ufshcd_map_desc_id_to_length(hba, desc_id, &buff_len); + + /* Sanity checks */ + if (ret || !buff_len) { + dev_err(hba->dev, "%s: Failed to get full descriptor length", + __func__); + return ret; + } + + /* Check whether we need temp memory */ + if (param_offset != 0 || param_size < buff_len) { + desc_buf = kmalloc(buff_len, GFP_KERNEL); + if (!desc_buf) + return -ENOMEM; + } else { + desc_buf = param_read_buf; + is_kmalloc = false; + } + + /* Request for full descriptor */ + ret = ufshcd_query_descriptor_retry(hba, UPIU_QUERY_OPCODE_READ_DESC, + desc_id, desc_index, 0, desc_buf, + &buff_len); + + if (ret) { + dev_err(hba->dev, "%s: Failed reading descriptor. desc_id %d, desc_index %d, param_offset %d, ret %d", + __func__, desc_id, desc_index, param_offset, ret); + goto out; + } + + /* Sanity check */ + if (desc_buf[QUERY_DESC_DESC_TYPE_OFFSET] != desc_id) { + dev_err(hba->dev, "%s: invalid desc_id %d in descriptor header", + __func__, desc_buf[QUERY_DESC_DESC_TYPE_OFFSET]); + ret = -EINVAL; + goto out; + } + + /* Check wherher we will not copy more data, than available */ + if (is_kmalloc && param_size > buff_len) + param_size = buff_len; + + if (is_kmalloc) + memcpy(param_read_buf, &desc_buf[param_offset], param_size); +out: + if (is_kmalloc) + kfree(desc_buf); + return ret; +} + +/* replace non-printable or non-ASCII characters with spaces */ +static inline void ufshcd_remove_non_printable(uint8_t *val) +{ + if (!val) + return; + + if (*val < 0x20 || *val > 0x7e) + *val = ' '; +} + +/** + * ufshcd_uic_pwr_ctrl - executes UIC commands (which affects the link power + * state) and waits for it to take effect. + * + */ +static int ufshcd_uic_pwr_ctrl(struct ufs_hba *hba, struct uic_command *cmd) +{ + unsigned long start = 0; + u8 status; + int ret; + + ret = ufshcd_send_uic_cmd(hba, cmd); + if (ret) { + dev_err(hba->dev, + "pwr ctrl cmd 0x%x with mode 0x%x uic error %d\n", + cmd->command, cmd->argument3, ret); + + return ret; + } + + start = get_timer(0); + do { + status = ufshcd_get_upmcrs(hba); + if (get_timer(start) > UFS_UIC_CMD_TIMEOUT) { + dev_err(hba->dev, + "pwr ctrl cmd 0x%x failed, host upmcrs:0x%x\n", + cmd->command, status); + ret = (status != PWR_OK) ? status : -1; + break; + } + } while (status != PWR_LOCAL); + + return ret; +} + +/** + * ufshcd_uic_change_pwr_mode - Perform the UIC power mode change + * using DME_SET primitives. + */ +static int ufshcd_uic_change_pwr_mode(struct ufs_hba *hba, u8 mode) +{ + struct uic_command uic_cmd = {0}; + int ret; + + uic_cmd.command = UIC_CMD_DME_SET; + uic_cmd.argument1 = UIC_ARG_MIB(PA_PWRMODE); + uic_cmd.argument3 = mode; + ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd); + + return ret; +} + +static +void ufshcd_prepare_utp_scsi_cmd_upiu(struct ufs_hba *hba, + struct scsi_cmd *pccb, u32 upiu_flags) +{ + struct utp_upiu_req *ucd_req_ptr = hba->ucd_req_ptr; + unsigned int cdb_len; + + /* command descriptor fields */ + ucd_req_ptr->header.dword_0 = + UPIU_HEADER_DWORD(UPIU_TRANSACTION_COMMAND, upiu_flags, + pccb->lun, TASK_TAG); + ucd_req_ptr->header.dword_1 = + UPIU_HEADER_DWORD(UPIU_COMMAND_SET_TYPE_SCSI, 0, 0, 0); + + /* Total EHS length and Data segment length will be zero */ + ucd_req_ptr->header.dword_2 = 0; + + ucd_req_ptr->sc.exp_data_transfer_len = cpu_to_be32(pccb->datalen); + + cdb_len = min_t(unsigned short, pccb->cmdlen, UFS_CDB_SIZE); + memset(ucd_req_ptr->sc.cdb, 0, UFS_CDB_SIZE); + memcpy(ucd_req_ptr->sc.cdb, pccb->cmd, cdb_len); + + memset(hba->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp)); +} + +static inline void prepare_prdt_desc(struct ufshcd_sg_entry *entry, + unsigned char *buf, ulong len) +{ + entry->size = cpu_to_le32(len) | GENMASK(1, 0); + entry->base_addr = cpu_to_le32(lower_32_bits((unsigned long)buf)); + entry->upper_addr = cpu_to_le32(upper_32_bits((unsigned long)buf)); +} + +static void prepare_prdt_table(struct ufs_hba *hba, struct scsi_cmd *pccb) +{ + struct utp_transfer_req_desc *req_desc = hba->utrdl; + struct ufshcd_sg_entry *prd_table = hba->ucd_prdt_ptr; + ulong datalen = pccb->datalen; + int table_length; + u8 *buf; + int i; + + if (!datalen) { + req_desc->prd_table_length = 0; + return; + } + + table_length = DIV_ROUND_UP(pccb->datalen, MAX_PRDT_ENTRY); + buf = pccb->pdata; + i = table_length; + while (--i) { + prepare_prdt_desc(&prd_table[table_length - i - 1], buf, + MAX_PRDT_ENTRY - 1); + buf += MAX_PRDT_ENTRY; + datalen -= MAX_PRDT_ENTRY; + } + + prepare_prdt_desc(&prd_table[table_length - i - 1], buf, datalen - 1); + + req_desc->prd_table_length = table_length; +} + +static int ufs_scsi_exec(struct udevice *scsi_dev, struct scsi_cmd *pccb) +{ + struct ufs_hba *hba = dev_get_uclass_priv(scsi_dev->parent); + struct utp_transfer_req_desc *req_desc = hba->utrdl; + u32 upiu_flags; + int ocs, result = 0; + u8 scsi_status; + + ufshcd_prepare_req_desc_hdr(req_desc, &upiu_flags, pccb->dma_dir); + ufshcd_prepare_utp_scsi_cmd_upiu(hba, pccb, upiu_flags); + prepare_prdt_table(hba, pccb); + + ufshcd_send_command(hba, TASK_TAG); + + ocs = ufshcd_get_tr_ocs(hba); + switch (ocs) { + case OCS_SUCCESS: + result = ufshcd_get_req_rsp(hba->ucd_rsp_ptr); + switch (result) { + case UPIU_TRANSACTION_RESPONSE: + result = ufshcd_get_rsp_upiu_result(hba->ucd_rsp_ptr); + + scsi_status = result & MASK_SCSI_STATUS; + if (scsi_status) + return -EINVAL; + + break; + case UPIU_TRANSACTION_REJECT_UPIU: + /* TODO: handle Reject UPIU Response */ + dev_err(hba->dev, + "Reject UPIU not fully implemented\n"); + return -EINVAL; + default: + dev_err(hba->dev, + "Unexpected request response code = %x\n", + result); + return -EINVAL; + } + break; + default: + dev_err(hba->dev, "OCS error from controller = %x\n", ocs); + return -EINVAL; + } + + return 0; +} + +static inline int ufshcd_read_desc(struct ufs_hba *hba, enum desc_idn desc_id, + int desc_index, u8 *buf, u32 size) +{ + return ufshcd_read_desc_param(hba, desc_id, desc_index, 0, buf, size); +} + +static int ufshcd_read_device_desc(struct ufs_hba *hba, u8 *buf, u32 size) +{ + return ufshcd_read_desc(hba, QUERY_DESC_IDN_DEVICE, 0, buf, size); +} + +/** + * ufshcd_read_string_desc - read string descriptor + * + */ +int ufshcd_read_string_desc(struct ufs_hba *hba, int desc_index, + u8 *buf, u32 size, bool ascii) +{ + int err = 0; + + err = ufshcd_read_desc(hba, QUERY_DESC_IDN_STRING, desc_index, buf, + size); + + if (err) { + dev_err(hba->dev, "%s: reading String Desc failed after %d retries. err = %d\n", + __func__, QUERY_REQ_RETRIES, err); + goto out; + } + + if (ascii) { + int desc_len; + int ascii_len; + int i; + u8 *buff_ascii; + + desc_len = buf[0]; + /* remove header and divide by 2 to move from UTF16 to UTF8 */ + ascii_len = (desc_len - QUERY_DESC_HDR_SIZE) / 2 + 1; + if (size < ascii_len + QUERY_DESC_HDR_SIZE) { + dev_err(hba->dev, "%s: buffer allocated size is too small\n", + __func__); + err = -ENOMEM; + goto out; + } + + buff_ascii = kmalloc(ascii_len, GFP_KERNEL); + if (!buff_ascii) { + err = -ENOMEM; + goto out; + } + + /* + * the descriptor contains string in UTF16 format + * we need to convert to utf-8 so it can be displayed + */ + utf16_to_utf8(buff_ascii, + (uint16_t *)&buf[QUERY_DESC_HDR_SIZE], ascii_len); + + /* replace non-printable or non-ASCII characters with spaces */ + for (i = 0; i < ascii_len; i++) + ufshcd_remove_non_printable(&buff_ascii[i]); + + memset(buf + QUERY_DESC_HDR_SIZE, 0, + size - QUERY_DESC_HDR_SIZE); + memcpy(buf + QUERY_DESC_HDR_SIZE, buff_ascii, ascii_len); + buf[QUERY_DESC_LENGTH_OFFSET] = ascii_len + QUERY_DESC_HDR_SIZE; + kfree(buff_ascii); + } +out: + return err; +} + +static int ufs_get_device_desc(struct ufs_hba *hba, + struct ufs_dev_desc *dev_desc) +{ + int err; + size_t buff_len; + u8 model_index; + u8 *desc_buf; + + buff_len = max_t(size_t, hba->desc_size.dev_desc, + QUERY_DESC_MAX_SIZE + 1); + desc_buf = kmalloc(buff_len, GFP_KERNEL); + if (!desc_buf) { + err = -ENOMEM; + goto out; + } + + err = ufshcd_read_device_desc(hba, desc_buf, hba->desc_size.dev_desc); + if (err) { + dev_err(hba->dev, "%s: Failed reading Device Desc. err = %d\n", + __func__, err); + goto out; + } + + /* + * getting vendor (manufacturerID) and Bank Index in big endian + * format + */ + dev_desc->wmanufacturerid = desc_buf[DEVICE_DESC_PARAM_MANF_ID] << 8 | + desc_buf[DEVICE_DESC_PARAM_MANF_ID + 1]; + + model_index = desc_buf[DEVICE_DESC_PARAM_PRDCT_NAME]; + + /* Zero-pad entire buffer for string termination. */ + memset(desc_buf, 0, buff_len); + + err = ufshcd_read_string_desc(hba, model_index, desc_buf, + QUERY_DESC_MAX_SIZE, true/*ASCII*/); + if (err) { + dev_err(hba->dev, "%s: Failed reading Product Name. err = %d\n", + __func__, err); + goto out; + } + + desc_buf[QUERY_DESC_MAX_SIZE] = '\0'; + strlcpy(dev_desc->model, (char *)(desc_buf + QUERY_DESC_HDR_SIZE), + min_t(u8, desc_buf[QUERY_DESC_LENGTH_OFFSET], + MAX_MODEL_LEN)); + + /* Null terminate the model string */ + dev_desc->model[MAX_MODEL_LEN] = '\0'; + +out: + kfree(desc_buf); + return err; +} + +/** + * ufshcd_get_max_pwr_mode - reads the max power mode negotiated with device + */ +static int ufshcd_get_max_pwr_mode(struct ufs_hba *hba) +{ + struct ufs_pa_layer_attr *pwr_info = &hba->max_pwr_info.info; + + if (hba->max_pwr_info.is_valid) + return 0; + + pwr_info->pwr_tx = FAST_MODE; + pwr_info->pwr_rx = FAST_MODE; + pwr_info->hs_rate = PA_HS_MODE_B; + + /* Get the connected lane count */ + ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDRXDATALANES), + &pwr_info->lane_rx); + ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES), + &pwr_info->lane_tx); + + if (!pwr_info->lane_rx || !pwr_info->lane_tx) { + dev_err(hba->dev, "%s: invalid connected lanes value. rx=%d, tx=%d\n", + __func__, pwr_info->lane_rx, pwr_info->lane_tx); + return -EINVAL; + } + + /* + * First, get the maximum gears of HS speed. + * If a zero value, it means there is no HSGEAR capability. + * Then, get the maximum gears of PWM speed. + */ + ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR), &pwr_info->gear_rx); + if (!pwr_info->gear_rx) { + ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR), + &pwr_info->gear_rx); + if (!pwr_info->gear_rx) { + dev_err(hba->dev, "%s: invalid max pwm rx gear read = %d\n", + __func__, pwr_info->gear_rx); + return -EINVAL; + } + pwr_info->pwr_rx = SLOW_MODE; + } + + ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR), + &pwr_info->gear_tx); + if (!pwr_info->gear_tx) { + ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR), + &pwr_info->gear_tx); + if (!pwr_info->gear_tx) { + dev_err(hba->dev, "%s: invalid max pwm tx gear read = %d\n", + __func__, pwr_info->gear_tx); + return -EINVAL; + } + pwr_info->pwr_tx = SLOW_MODE; + } + + hba->max_pwr_info.is_valid = true; + return 0; +} + +static int ufshcd_change_power_mode(struct ufs_hba *hba, + struct ufs_pa_layer_attr *pwr_mode) +{ + int ret; + + /* if already configured to the requested pwr_mode */ + if (pwr_mode->gear_rx == hba->pwr_info.gear_rx && + pwr_mode->gear_tx == hba->pwr_info.gear_tx && + pwr_mode->lane_rx == hba->pwr_info.lane_rx && + pwr_mode->lane_tx == hba->pwr_info.lane_tx && + pwr_mode->pwr_rx == hba->pwr_info.pwr_rx && + pwr_mode->pwr_tx == hba->pwr_info.pwr_tx && + pwr_mode->hs_rate == hba->pwr_info.hs_rate) { + dev_dbg(hba->dev, "%s: power already configured\n", __func__); + return 0; + } + + /* + * Configure attributes for power mode change with below. + * - PA_RXGEAR, PA_ACTIVERXDATALANES, PA_RXTERMINATION, + * - PA_TXGEAR, PA_ACTIVETXDATALANES, PA_TXTERMINATION, + * - PA_HSSERIES + */ + ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXGEAR), pwr_mode->gear_rx); + ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVERXDATALANES), + pwr_mode->lane_rx); + if (pwr_mode->pwr_rx == FASTAUTO_MODE || pwr_mode->pwr_rx == FAST_MODE) + ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), TRUE); + else + ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), FALSE); + + ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXGEAR), pwr_mode->gear_tx); + ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVETXDATALANES), + pwr_mode->lane_tx); + if (pwr_mode->pwr_tx == FASTAUTO_MODE || pwr_mode->pwr_tx == FAST_MODE) + ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), TRUE); + else + ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), FALSE); + + if (pwr_mode->pwr_rx == FASTAUTO_MODE || + pwr_mode->pwr_tx == FASTAUTO_MODE || + pwr_mode->pwr_rx == FAST_MODE || + pwr_mode->pwr_tx == FAST_MODE) + ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HSSERIES), + pwr_mode->hs_rate); + + ret = ufshcd_uic_change_pwr_mode(hba, pwr_mode->pwr_rx << 4 | + pwr_mode->pwr_tx); + + if (ret) { + dev_err(hba->dev, + "%s: power mode change failed %d\n", __func__, ret); + + return ret; + } + + /* Copy new Power Mode to power info */ + memcpy(&hba->pwr_info, pwr_mode, sizeof(struct ufs_pa_layer_attr)); + + return ret; +} + +/** + * ufshcd_verify_dev_init() - Verify device initialization + * + */ +static int ufshcd_verify_dev_init(struct ufs_hba *hba) +{ + int retries; + int err; + + for (retries = NOP_OUT_RETRIES; retries > 0; retries--) { + err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_NOP, + NOP_OUT_TIMEOUT); + if (!err || err == -ETIMEDOUT) + break; + + dev_dbg(hba->dev, "%s: error %d retrying\n", __func__, err); + } + + if (err) + dev_err(hba->dev, "%s: NOP OUT failed %d\n", __func__, err); + + return err; +} + +/** + * ufshcd_complete_dev_init() - checks device readiness + */ +static int ufshcd_complete_dev_init(struct ufs_hba *hba) +{ + int i; + int err; + bool flag_res = 1; + + err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG, + QUERY_FLAG_IDN_FDEVICEINIT, NULL); + if (err) { + dev_err(hba->dev, + "%s setting fDeviceInit flag failed with error %d\n", + __func__, err); + goto out; + } + + /* poll for max. 1000 iterations for fDeviceInit flag to clear */ + for (i = 0; i < 1000 && !err && flag_res; i++) + err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_READ_FLAG, + QUERY_FLAG_IDN_FDEVICEINIT, + &flag_res); + + if (err) + dev_err(hba->dev, + "%s reading fDeviceInit flag failed with error %d\n", + __func__, err); + else if (flag_res) + dev_err(hba->dev, + "%s fDeviceInit was not cleared by the device\n", + __func__); + +out: + return err; +} + +static void ufshcd_def_desc_sizes(struct ufs_hba *hba) +{ + hba->desc_size.dev_desc = QUERY_DESC_DEVICE_DEF_SIZE; + hba->desc_size.pwr_desc = QUERY_DESC_POWER_DEF_SIZE; + hba->desc_size.interc_desc = QUERY_DESC_INTERCONNECT_DEF_SIZE; + hba->desc_size.conf_desc = QUERY_DESC_CONFIGURATION_DEF_SIZE; + hba->desc_size.unit_desc = QUERY_DESC_UNIT_DEF_SIZE; + hba->desc_size.geom_desc = QUERY_DESC_GEOMETRY_DEF_SIZE; + hba->desc_size.hlth_desc = QUERY_DESC_HEALTH_DEF_SIZE; +} + +int ufs_start(struct ufs_hba *hba) +{ + struct ufs_dev_desc card = {0}; + int ret; + + ret = ufshcd_link_startup(hba); + if (ret) + return ret; + + ret = ufshcd_verify_dev_init(hba); + if (ret) + return ret; + + ret = ufshcd_complete_dev_init(hba); + if (ret) + return ret; + + /* Init check for device descriptor sizes */ + ufshcd_init_desc_sizes(hba); + + ret = ufs_get_device_desc(hba, &card); + if (ret) { + dev_err(hba->dev, "%s: Failed getting device info. err = %d\n", + __func__, ret); + + return ret; + } + + if (ufshcd_get_max_pwr_mode(hba)) { + dev_err(hba->dev, + "%s: Failed getting max supported power mode\n", + __func__); + } else { + ret = ufshcd_change_power_mode(hba, &hba->max_pwr_info.info); + if (ret) { + dev_err(hba->dev, "%s: Failed setting power mode, err = %d\n", + __func__, ret); + + return ret; + } + + printf("Device at %s up at:", hba->dev->name); + ufshcd_print_pwr_info(hba); + } + + return 0; +} + +int ufshcd_probe(struct udevice *ufs_dev, struct ufs_hba_ops *hba_ops) +{ + struct ufs_hba *hba = dev_get_uclass_priv(ufs_dev); + struct scsi_platdata *scsi_plat; + struct udevice *scsi_dev; + int err; + + device_find_first_child(ufs_dev, &scsi_dev); + if (!scsi_dev) + return -ENODEV; + + scsi_plat = dev_get_uclass_platdata(scsi_dev); + scsi_plat->max_id = UFSHCD_MAX_ID; + scsi_plat->max_lun = UFS_MAX_LUNS; + scsi_plat->max_bytes_per_req = UFS_MAX_BYTES; + + hba->dev = ufs_dev; + hba->ops = hba_ops; + hba->mmio_base = (void *)dev_read_addr(ufs_dev); + + /* Set descriptor lengths to specification defaults */ + ufshcd_def_desc_sizes(hba); + + ufshcd_ops_init(hba); + + /* Read capabilties registers */ + hba->capabilities = ufshcd_readl(hba, REG_CONTROLLER_CAPABILITIES); + + /* Get UFS version supported by the controller */ + hba->version = ufshcd_get_ufs_version(hba); + if (hba->version != UFSHCI_VERSION_10 && + hba->version != UFSHCI_VERSION_11 && + hba->version != UFSHCI_VERSION_20 && + hba->version != UFSHCI_VERSION_21) + dev_err(hba->dev, "invalid UFS version 0x%x\n", + hba->version); + + /* Get Interrupt bit mask per version */ + hba->intr_mask = ufshcd_get_intr_mask(hba); + + /* Allocate memory for host memory space */ + err = ufshcd_memory_alloc(hba); + if (err) { + dev_err(hba->dev, "Memory allocation failed\n"); + return err; + } + + /* Configure Local data structures */ + ufshcd_host_memory_configure(hba); + + /* + * In order to avoid any spurious interrupt immediately after + * registering UFS controller interrupt handler, clear any pending UFS + * interrupt status and disable all the UFS interrupts. + */ + ufshcd_writel(hba, ufshcd_readl(hba, REG_INTERRUPT_STATUS), + REG_INTERRUPT_STATUS); + ufshcd_writel(hba, 0, REG_INTERRUPT_ENABLE); + + err = ufshcd_hba_enable(hba); + if (err) { + dev_err(hba->dev, "Host controller enable failed\n"); + return err; + } + + err = ufs_start(hba); + if (err) + return err; + + return 0; +} + +int ufs_scsi_bind(struct udevice *ufs_dev, struct udevice **scsi_devp) +{ + int ret = device_bind_driver(ufs_dev, "ufs_scsi", "ufs_scsi", + scsi_devp); + + return ret; +} + +static struct scsi_ops ufs_ops = { + .exec = ufs_scsi_exec, +}; + +int ufs_probe_dev(int index) +{ + struct udevice *dev; + + return uclass_get_device(UCLASS_UFS, index, &dev); +} + +int ufs_probe(void) +{ + struct udevice *dev; + int ret, i; + + for (i = 0;; i++) { + ret = uclass_get_device(UCLASS_UFS, i, &dev); + if (ret == -ENODEV) + break; + } + + return 0; +} + +U_BOOT_DRIVER(ufs_scsi) = { + .id = UCLASS_SCSI, + .name = "ufs_scsi", + .ops = &ufs_ops, +}; diff --git a/drivers/ufs/ufs.h b/drivers/ufs/ufs.h new file mode 100644 index 0000000..e0bde93 --- /dev/null +++ b/drivers/ufs/ufs.h @@ -0,0 +1,918 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +#ifndef __UFS_H +#define __UFS_H + +#include <asm/io.h> +#include <dm.h> + +#include "unipro.h" + +#define UFS_CDB_SIZE 16 +#define UPIU_TRANSACTION_UIC_CMD 0x1F +#define UIC_CMD_SIZE (sizeof(u32) * 4) +#define RESPONSE_UPIU_SENSE_DATA_LENGTH 18 +#define UFS_MAX_LUNS 0x7F + +enum { + TASK_REQ_UPIU_SIZE_DWORDS = 8, + TASK_RSP_UPIU_SIZE_DWORDS = 8, + ALIGNED_UPIU_SIZE = 512, +}; + +/* UFS device power modes */ +enum ufs_dev_pwr_mode { + UFS_ACTIVE_PWR_MODE = 1, + UFS_SLEEP_PWR_MODE = 2, + UFS_POWERDOWN_PWR_MODE = 3, +}; + +enum ufs_notify_change_status { + PRE_CHANGE, + POST_CHANGE, +}; + +struct ufs_pa_layer_attr { + u32 gear_rx; + u32 gear_tx; + u32 lane_rx; + u32 lane_tx; + u32 pwr_rx; + u32 pwr_tx; + u32 hs_rate; +}; + +struct ufs_pwr_mode_info { + bool is_valid; + struct ufs_pa_layer_attr info; +}; + +enum ufs_desc_def_size { + QUERY_DESC_DEVICE_DEF_SIZE = 0x40, + QUERY_DESC_CONFIGURATION_DEF_SIZE = 0x90, + QUERY_DESC_UNIT_DEF_SIZE = 0x23, + QUERY_DESC_INTERCONNECT_DEF_SIZE = 0x06, + QUERY_DESC_GEOMETRY_DEF_SIZE = 0x48, + QUERY_DESC_POWER_DEF_SIZE = 0x62, + QUERY_DESC_HEALTH_DEF_SIZE = 0x25, +}; + +struct ufs_desc_size { + int dev_desc; + int pwr_desc; + int geom_desc; + int interc_desc; + int unit_desc; + int conf_desc; + int hlth_desc; +}; + +/* + * Request Descriptor Definitions + */ + +/* Transfer request command type */ +enum { + UTP_CMD_TYPE_SCSI = 0x0, + UTP_CMD_TYPE_UFS = 0x1, + UTP_CMD_TYPE_DEV_MANAGE = 0x2, +}; + +/* UTP Transfer Request Command Offset */ +#define UPIU_COMMAND_TYPE_OFFSET 28 + +/* Offset of the response code in the UPIU header */ +#define UPIU_RSP_CODE_OFFSET 8 + +/* To accommodate UFS2.0 required Command type */ +enum { + UTP_CMD_TYPE_UFS_STORAGE = 0x1, +}; + +enum { + UTP_SCSI_COMMAND = 0x00000000, + UTP_NATIVE_UFS_COMMAND = 0x10000000, + UTP_DEVICE_MANAGEMENT_FUNCTION = 0x20000000, + UTP_REQ_DESC_INT_CMD = 0x01000000, +}; + +/* UTP Transfer Request Data Direction (DD) */ +enum { + UTP_NO_DATA_TRANSFER = 0x00000000, + UTP_HOST_TO_DEVICE = 0x02000000, + UTP_DEVICE_TO_HOST = 0x04000000, +}; + +/* Overall command status values */ +enum { + OCS_SUCCESS = 0x0, + OCS_INVALID_CMD_TABLE_ATTR = 0x1, + OCS_INVALID_PRDT_ATTR = 0x2, + OCS_MISMATCH_DATA_BUF_SIZE = 0x3, + OCS_MISMATCH_RESP_UPIU_SIZE = 0x4, + OCS_PEER_COMM_FAILURE = 0x5, + OCS_ABORTED = 0x6, + OCS_FATAL_ERROR = 0x7, + OCS_INVALID_COMMAND_STATUS = 0x0F, + MASK_OCS = 0x0F, +}; + +/* The maximum length of the data byte count field in the PRDT is 256KB */ +#define PRDT_DATA_BYTE_COUNT_MAX (256 * 1024) +/* The granularity of the data byte count field in the PRDT is 32-bit */ +#define PRDT_DATA_BYTE_COUNT_PAD 4 + +#define GENERAL_UPIU_REQUEST_SIZE (sizeof(struct utp_upiu_req)) +#define QUERY_DESC_MAX_SIZE 255 +#define QUERY_DESC_MIN_SIZE 2 +#define QUERY_DESC_HDR_SIZE 2 +#define QUERY_OSF_SIZE (GENERAL_UPIU_REQUEST_SIZE - \ + (sizeof(struct utp_upiu_header))) +#define RESPONSE_UPIU_SENSE_DATA_LENGTH 18 +#define UPIU_HEADER_DWORD(byte3, byte2, byte1, byte0)\ + cpu_to_be32((byte3 << 24) | (byte2 << 16) |\ + (byte1 << 8) | (byte0)) +/* + * UFS Protocol Information Unit related definitions + */ + +/* Task management functions */ +enum { + UFS_ABORT_TASK = 0x01, + UFS_ABORT_TASK_SET = 0x02, + UFS_CLEAR_TASK_SET = 0x04, + UFS_LOGICAL_RESET = 0x08, + UFS_QUERY_TASK = 0x80, + UFS_QUERY_TASK_SET = 0x81, +}; + +/* UTP UPIU Transaction Codes Initiator to Target */ +enum { + UPIU_TRANSACTION_NOP_OUT = 0x00, + UPIU_TRANSACTION_COMMAND = 0x01, + UPIU_TRANSACTION_DATA_OUT = 0x02, + UPIU_TRANSACTION_TASK_REQ = 0x04, + UPIU_TRANSACTION_QUERY_REQ = 0x16, +}; + +/* UTP UPIU Transaction Codes Target to Initiator */ +enum { + UPIU_TRANSACTION_NOP_IN = 0x20, + UPIU_TRANSACTION_RESPONSE = 0x21, + UPIU_TRANSACTION_DATA_IN = 0x22, + UPIU_TRANSACTION_TASK_RSP = 0x24, + UPIU_TRANSACTION_READY_XFER = 0x31, + UPIU_TRANSACTION_QUERY_RSP = 0x36, + UPIU_TRANSACTION_REJECT_UPIU = 0x3F, +}; + +/* UPIU Read/Write flags */ +enum { + UPIU_CMD_FLAGS_NONE = 0x00, + UPIU_CMD_FLAGS_WRITE = 0x20, + UPIU_CMD_FLAGS_READ = 0x40, +}; + +/* UPIU Task Attributes */ +enum { + UPIU_TASK_ATTR_SIMPLE = 0x00, + UPIU_TASK_ATTR_ORDERED = 0x01, + UPIU_TASK_ATTR_HEADQ = 0x02, + UPIU_TASK_ATTR_ACA = 0x03, +}; + +/* UPIU Query request function */ +enum { + UPIU_QUERY_FUNC_STANDARD_READ_REQUEST = 0x01, + UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST = 0x81, +}; + +/* Offset of the response code in the UPIU header */ +#define UPIU_RSP_CODE_OFFSET 8 + +enum { + MASK_SCSI_STATUS = 0xFF, + MASK_TASK_RESPONSE = 0xFF00, + MASK_RSP_UPIU_RESULT = 0xFFFF, + MASK_QUERY_DATA_SEG_LEN = 0xFFFF, + MASK_RSP_UPIU_DATA_SEG_LEN = 0xFFFF, + MASK_RSP_EXCEPTION_EVENT = 0x10000, + MASK_TM_SERVICE_RESP = 0xFF, + MASK_TM_FUNC = 0xFF, +}; + +/* UTP QUERY Transaction Specific Fields OpCode */ +enum query_opcode { + UPIU_QUERY_OPCODE_NOP = 0x0, + UPIU_QUERY_OPCODE_READ_DESC = 0x1, + UPIU_QUERY_OPCODE_WRITE_DESC = 0x2, + UPIU_QUERY_OPCODE_READ_ATTR = 0x3, + UPIU_QUERY_OPCODE_WRITE_ATTR = 0x4, + UPIU_QUERY_OPCODE_READ_FLAG = 0x5, + UPIU_QUERY_OPCODE_SET_FLAG = 0x6, + UPIU_QUERY_OPCODE_CLEAR_FLAG = 0x7, + UPIU_QUERY_OPCODE_TOGGLE_FLAG = 0x8, +}; + +/* Query response result code */ +enum { + QUERY_RESULT_SUCCESS = 0x00, + QUERY_RESULT_NOT_READABLE = 0xF6, + QUERY_RESULT_NOT_WRITEABLE = 0xF7, + QUERY_RESULT_ALREADY_WRITTEN = 0xF8, + QUERY_RESULT_INVALID_LENGTH = 0xF9, + QUERY_RESULT_INVALID_VALUE = 0xFA, + QUERY_RESULT_INVALID_SELECTOR = 0xFB, + QUERY_RESULT_INVALID_INDEX = 0xFC, + QUERY_RESULT_INVALID_IDN = 0xFD, + QUERY_RESULT_INVALID_OPCODE = 0xFE, + QUERY_RESULT_GENERAL_FAILURE = 0xFF, +}; + +enum { + UPIU_COMMAND_SET_TYPE_SCSI = 0x0, + UPIU_COMMAND_SET_TYPE_UFS = 0x1, + UPIU_COMMAND_SET_TYPE_QUERY = 0x2, +}; + +/* Flag idn for Query Requests*/ +enum flag_idn { + QUERY_FLAG_IDN_FDEVICEINIT = 0x01, + QUERY_FLAG_IDN_PERMANENT_WPE = 0x02, + QUERY_FLAG_IDN_PWR_ON_WPE = 0x03, + QUERY_FLAG_IDN_BKOPS_EN = 0x04, + QUERY_FLAG_IDN_LIFE_SPAN_MODE_ENABLE = 0x05, + QUERY_FLAG_IDN_PURGE_ENABLE = 0x06, + QUERY_FLAG_IDN_RESERVED2 = 0x07, + QUERY_FLAG_IDN_FPHYRESOURCEREMOVAL = 0x08, + QUERY_FLAG_IDN_BUSY_RTC = 0x09, + QUERY_FLAG_IDN_RESERVED3 = 0x0A, + QUERY_FLAG_IDN_PERMANENTLY_DISABLE_FW_UPDATE = 0x0B, +}; + +/* Attribute idn for Query requests */ +enum attr_idn { + QUERY_ATTR_IDN_BOOT_LU_EN = 0x00, + QUERY_ATTR_IDN_RESERVED = 0x01, + QUERY_ATTR_IDN_POWER_MODE = 0x02, + QUERY_ATTR_IDN_ACTIVE_ICC_LVL = 0x03, + QUERY_ATTR_IDN_OOO_DATA_EN = 0x04, + QUERY_ATTR_IDN_BKOPS_STATUS = 0x05, + QUERY_ATTR_IDN_PURGE_STATUS = 0x06, + QUERY_ATTR_IDN_MAX_DATA_IN = 0x07, + QUERY_ATTR_IDN_MAX_DATA_OUT = 0x08, + QUERY_ATTR_IDN_DYN_CAP_NEEDED = 0x09, + QUERY_ATTR_IDN_REF_CLK_FREQ = 0x0A, + QUERY_ATTR_IDN_CONF_DESC_LOCK = 0x0B, + QUERY_ATTR_IDN_MAX_NUM_OF_RTT = 0x0C, + QUERY_ATTR_IDN_EE_CONTROL = 0x0D, + QUERY_ATTR_IDN_EE_STATUS = 0x0E, + QUERY_ATTR_IDN_SECONDS_PASSED = 0x0F, + QUERY_ATTR_IDN_CNTX_CONF = 0x10, + QUERY_ATTR_IDN_CORR_PRG_BLK_NUM = 0x11, + QUERY_ATTR_IDN_RESERVED2 = 0x12, + QUERY_ATTR_IDN_RESERVED3 = 0x13, + QUERY_ATTR_IDN_FFU_STATUS = 0x14, + QUERY_ATTR_IDN_PSA_STATE = 0x15, + QUERY_ATTR_IDN_PSA_DATA_SIZE = 0x16, +}; + +/* Descriptor idn for Query requests */ +enum desc_idn { + QUERY_DESC_IDN_DEVICE = 0x0, + QUERY_DESC_IDN_CONFIGURATION = 0x1, + QUERY_DESC_IDN_UNIT = 0x2, + QUERY_DESC_IDN_RFU_0 = 0x3, + QUERY_DESC_IDN_INTERCONNECT = 0x4, + QUERY_DESC_IDN_STRING = 0x5, + QUERY_DESC_IDN_RFU_1 = 0x6, + QUERY_DESC_IDN_GEOMETRY = 0x7, + QUERY_DESC_IDN_POWER = 0x8, + QUERY_DESC_IDN_HEALTH = 0x9, + QUERY_DESC_IDN_MAX, +}; + +enum desc_header_offset { + QUERY_DESC_LENGTH_OFFSET = 0x00, + QUERY_DESC_DESC_TYPE_OFFSET = 0x01, +}; + +struct ufshcd_sg_entry { + __le32 base_addr; + __le32 upper_addr; + __le32 reserved; + __le32 size; +}; + +#define MAX_BUFF 128 +/** + * struct utp_transfer_cmd_desc - UFS Command Descriptor structure + * @command_upiu: Command UPIU Frame address + * @response_upiu: Response UPIU Frame address + * @prd_table: Physical Region Descriptor + */ +struct utp_transfer_cmd_desc { + u8 command_upiu[ALIGNED_UPIU_SIZE]; + u8 response_upiu[ALIGNED_UPIU_SIZE]; + struct ufshcd_sg_entry prd_table[MAX_BUFF]; +}; + +/** + * struct request_desc_header - Descriptor Header common to both UTRD and UTMRD + * @dword0: Descriptor Header DW0 + * @dword1: Descriptor Header DW1 + * @dword2: Descriptor Header DW2 + * @dword3: Descriptor Header DW3 + */ +struct request_desc_header { + __le32 dword_0; + __le32 dword_1; + __le32 dword_2; + __le32 dword_3; +}; + +/** + * struct utp_transfer_req_desc - UTRD structure + * @header: UTRD header DW-0 to DW-3 + * @command_desc_base_addr_lo: UCD base address low DW-4 + * @command_desc_base_addr_hi: UCD base address high DW-5 + * @response_upiu_length: response UPIU length DW-6 + * @response_upiu_offset: response UPIU offset DW-6 + * @prd_table_length: Physical region descriptor length DW-7 + * @prd_table_offset: Physical region descriptor offset DW-7 + */ +struct utp_transfer_req_desc { + /* DW 0-3 */ + struct request_desc_header header; + + /* DW 4-5*/ + __le32 command_desc_base_addr_lo; + __le32 command_desc_base_addr_hi; + + /* DW 6 */ + __le16 response_upiu_length; + __le16 response_upiu_offset; + + /* DW 7 */ + __le16 prd_table_length; + __le16 prd_table_offset; +}; + +/** + * struct utp_upiu_header - UPIU header structure + * @dword_0: UPIU header DW-0 + * @dword_1: UPIU header DW-1 + * @dword_2: UPIU header DW-2 + */ +struct utp_upiu_header { + __be32 dword_0; + __be32 dword_1; + __be32 dword_2; +}; + +/** + * struct utp_upiu_query - upiu request buffer structure for + * query request. + * @opcode: command to perform B-0 + * @idn: a value that indicates the particular type of data B-1 + * @index: Index to further identify data B-2 + * @selector: Index to further identify data B-3 + * @reserved_osf: spec reserved field B-4,5 + * @length: number of descriptor bytes to read/write B-6,7 + * @value: Attribute value to be written DW-5 + * @reserved: spec reserved DW-6,7 + */ +struct utp_upiu_query { + __u8 opcode; + __u8 idn; + __u8 index; + __u8 selector; + __be16 reserved_osf; + __be16 length; + __be32 value; + __be32 reserved[2]; +}; + +/** + * struct utp_upiu_cmd - Command UPIU structure + * @data_transfer_len: Data Transfer Length DW-3 + * @cdb: Command Descriptor Block CDB DW-4 to DW-7 + */ +struct utp_upiu_cmd { + __be32 exp_data_transfer_len; + u8 cdb[UFS_CDB_SIZE]; +}; + +/* + * UTMRD structure. + */ +struct utp_task_req_desc { + /* DW 0-3 */ + struct request_desc_header header; + + /* DW 4-11 - Task request UPIU structure */ + struct utp_upiu_header req_header; + __be32 input_param1; + __be32 input_param2; + __be32 input_param3; + __be32 __reserved1[2]; + + /* DW 12-19 - Task Management Response UPIU structure */ + struct utp_upiu_header rsp_header; + __be32 output_param1; + __be32 output_param2; + __be32 __reserved2[3]; +}; + +/** + * struct utp_upiu_req - general upiu request structure + * @header:UPIU header structure DW-0 to DW-2 + * @sc: fields structure for scsi command DW-3 to DW-7 + * @qr: fields structure for query request DW-3 to DW-7 + */ +struct utp_upiu_req { + struct utp_upiu_header header; + union { + struct utp_upiu_cmd sc; + struct utp_upiu_query qr; + struct utp_upiu_query tr; + /* use utp_upiu_query to host the 4 dwords of uic command */ + struct utp_upiu_query uc; + }; +}; + +/** + * struct utp_cmd_rsp - Response UPIU structure + * @residual_transfer_count: Residual transfer count DW-3 + * @reserved: Reserved double words DW-4 to DW-7 + * @sense_data_len: Sense data length DW-8 U16 + * @sense_data: Sense data field DW-8 to DW-12 + */ +struct utp_cmd_rsp { + __be32 residual_transfer_count; + __be32 reserved[4]; + __be16 sense_data_len; + u8 sense_data[RESPONSE_UPIU_SENSE_DATA_LENGTH]; +}; + +/** + * struct utp_upiu_rsp - general upiu response structure + * @header: UPIU header structure DW-0 to DW-2 + * @sr: fields structure for scsi command DW-3 to DW-12 + * @qr: fields structure for query request DW-3 to DW-7 + */ +struct utp_upiu_rsp { + struct utp_upiu_header header; + union { + struct utp_cmd_rsp sr; + struct utp_upiu_query qr; + }; +}; + +#define MAX_MODEL_LEN 16 +/** + * ufs_dev_desc - ufs device details from the device descriptor + * + * @wmanufacturerid: card details + * @model: card model + */ +struct ufs_dev_desc { + u16 wmanufacturerid; + char model[MAX_MODEL_LEN + 1]; +}; + +/* Device descriptor parameters offsets in bytes*/ +enum device_desc_param { + DEVICE_DESC_PARAM_LEN = 0x0, + DEVICE_DESC_PARAM_TYPE = 0x1, + DEVICE_DESC_PARAM_DEVICE_TYPE = 0x2, + DEVICE_DESC_PARAM_DEVICE_CLASS = 0x3, + DEVICE_DESC_PARAM_DEVICE_SUB_CLASS = 0x4, + DEVICE_DESC_PARAM_PRTCL = 0x5, + DEVICE_DESC_PARAM_NUM_LU = 0x6, + DEVICE_DESC_PARAM_NUM_WLU = 0x7, + DEVICE_DESC_PARAM_BOOT_ENBL = 0x8, + DEVICE_DESC_PARAM_DESC_ACCSS_ENBL = 0x9, + DEVICE_DESC_PARAM_INIT_PWR_MODE = 0xA, + DEVICE_DESC_PARAM_HIGH_PR_LUN = 0xB, + DEVICE_DESC_PARAM_SEC_RMV_TYPE = 0xC, + DEVICE_DESC_PARAM_SEC_LU = 0xD, + DEVICE_DESC_PARAM_BKOP_TERM_LT = 0xE, + DEVICE_DESC_PARAM_ACTVE_ICC_LVL = 0xF, + DEVICE_DESC_PARAM_SPEC_VER = 0x10, + DEVICE_DESC_PARAM_MANF_DATE = 0x12, + DEVICE_DESC_PARAM_MANF_NAME = 0x14, + DEVICE_DESC_PARAM_PRDCT_NAME = 0x15, + DEVICE_DESC_PARAM_SN = 0x16, + DEVICE_DESC_PARAM_OEM_ID = 0x17, + DEVICE_DESC_PARAM_MANF_ID = 0x18, + DEVICE_DESC_PARAM_UD_OFFSET = 0x1A, + DEVICE_DESC_PARAM_UD_LEN = 0x1B, + DEVICE_DESC_PARAM_RTT_CAP = 0x1C, + DEVICE_DESC_PARAM_FRQ_RTC = 0x1D, + DEVICE_DESC_PARAM_UFS_FEAT = 0x1F, + DEVICE_DESC_PARAM_FFU_TMT = 0x20, + DEVICE_DESC_PARAM_Q_DPTH = 0x21, + DEVICE_DESC_PARAM_DEV_VER = 0x22, + DEVICE_DESC_PARAM_NUM_SEC_WPA = 0x24, + DEVICE_DESC_PARAM_PSA_MAX_DATA = 0x25, + DEVICE_DESC_PARAM_PSA_TMT = 0x29, + DEVICE_DESC_PARAM_PRDCT_REV = 0x2A, +}; + +struct ufs_hba; + +enum { + UFSHCD_MAX_CHANNEL = 0, + UFSHCD_MAX_ID = 1, +}; + +enum dev_cmd_type { + DEV_CMD_TYPE_NOP = 0x0, + DEV_CMD_TYPE_QUERY = 0x1, +}; + +/** + * struct uic_command - UIC command structure + * @command: UIC command + * @argument1: UIC command argument 1 + * @argument2: UIC command argument 2 + * @argument3: UIC command argument 3 + * @cmd_active: Indicate if UIC command is outstanding + * @result: UIC command result + * @done: UIC command completion + */ +struct uic_command { + u32 command; + u32 argument1; + u32 argument2; + u32 argument3; + int cmd_active; + int result; +}; + +/* GenSelectorIndex calculation macros for M-PHY attributes */ +#define UIC_ARG_MPHY_TX_GEN_SEL_INDEX(lane) (lane) +#define UIC_ARG_MPHY_RX_GEN_SEL_INDEX(lane) (PA_MAXDATALANES + (lane)) + +#define UIC_ARG_MIB_SEL(attr, sel) ((((attr) & 0xFFFF) << 16) |\ + ((sel) & 0xFFFF)) +#define UIC_ARG_MIB(attr) UIC_ARG_MIB_SEL(attr, 0) +#define UIC_ARG_ATTR_TYPE(t) (((t) & 0xFF) << 16) +#define UIC_GET_ATTR_ID(v) (((v) >> 16) & 0xFFFF) + +/* Link Status*/ +enum link_status { + UFSHCD_LINK_IS_DOWN = 1, + UFSHCD_LINK_IS_UP = 2, +}; + +#define UIC_ARG_MIB_SEL(attr, sel) ((((attr) & 0xFFFF) << 16) |\ + ((sel) & 0xFFFF)) +#define UIC_ARG_MIB(attr) UIC_ARG_MIB_SEL(attr, 0) +#define UIC_ARG_ATTR_TYPE(t) (((t) & 0xFF) << 16) +#define UIC_GET_ATTR_ID(v) (((v) >> 16) & 0xFFFF) + +/* UIC Commands */ +enum uic_cmd_dme { + UIC_CMD_DME_GET = 0x01, + UIC_CMD_DME_SET = 0x02, + UIC_CMD_DME_PEER_GET = 0x03, + UIC_CMD_DME_PEER_SET = 0x04, + UIC_CMD_DME_POWERON = 0x10, + UIC_CMD_DME_POWEROFF = 0x11, + UIC_CMD_DME_ENABLE = 0x12, + UIC_CMD_DME_RESET = 0x14, + UIC_CMD_DME_END_PT_RST = 0x15, + UIC_CMD_DME_LINK_STARTUP = 0x16, + UIC_CMD_DME_HIBER_ENTER = 0x17, + UIC_CMD_DME_HIBER_EXIT = 0x18, + UIC_CMD_DME_TEST_MODE = 0x1A, +}; + +/* UIC Config result code / Generic error code */ +enum { + UIC_CMD_RESULT_SUCCESS = 0x00, + UIC_CMD_RESULT_INVALID_ATTR = 0x01, + UIC_CMD_RESULT_FAILURE = 0x01, + UIC_CMD_RESULT_INVALID_ATTR_VALUE = 0x02, + UIC_CMD_RESULT_READ_ONLY_ATTR = 0x03, + UIC_CMD_RESULT_WRITE_ONLY_ATTR = 0x04, + UIC_CMD_RESULT_BAD_INDEX = 0x05, + UIC_CMD_RESULT_LOCKED_ATTR = 0x06, + UIC_CMD_RESULT_BAD_TEST_FEATURE_INDEX = 0x07, + UIC_CMD_RESULT_PEER_COMM_FAILURE = 0x08, + UIC_CMD_RESULT_BUSY = 0x09, + UIC_CMD_RESULT_DME_FAILURE = 0x0A, +}; + +#define MASK_UIC_COMMAND_RESULT 0xFF + +/* Host <-> Device UniPro Link state */ +enum uic_link_state { + UIC_LINK_OFF_STATE = 0, /* Link powered down or disabled */ + UIC_LINK_ACTIVE_STATE = 1, /* Link is in Fast/Slow/Sleep state */ + UIC_LINK_HIBERN8_STATE = 2, /* Link is in Hibernate state */ +}; + +/* UIC command interfaces for DME primitives */ +#define DME_LOCAL 0 +#define DME_PEER 1 +#define ATTR_SET_NOR 0 /* NORMAL */ +#define ATTR_SET_ST 1 /* STATIC */ + +int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel, + u8 attr_set, u32 mib_val, u8 peer); +int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel, + u32 *mib_val, u8 peer); + +static inline int ufshcd_dme_set(struct ufs_hba *hba, u32 attr_sel, + u32 mib_val) +{ + return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_NOR, + mib_val, DME_LOCAL); +} + +static inline int ufshcd_dme_get(struct ufs_hba *hba, + u32 attr_sel, u32 *mib_val) +{ + return ufshcd_dme_get_attr(hba, attr_sel, mib_val, DME_LOCAL); +} + +static inline int ufshcd_dme_peer_get(struct ufs_hba *hba, + u32 attr_sel, u32 *mib_val) +{ + return ufshcd_dme_get_attr(hba, attr_sel, mib_val, DME_PEER); +} + +static inline int ufshcd_dme_peer_set(struct ufs_hba *hba, u32 attr_sel, + u32 mib_val) +{ + return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_NOR, + mib_val, DME_PEER); +} + +/** + * struct ufs_query_req - parameters for building a query request + * @query_func: UPIU header query function + * @upiu_req: the query request data + */ +struct ufs_query_req { + u8 query_func; + struct utp_upiu_query upiu_req; +}; + +/** + * struct ufs_query_resp - UPIU QUERY + * @response: device response code + * @upiu_res: query response data + */ +struct ufs_query_res { + u8 response; + struct utp_upiu_query upiu_res; +}; + +/** + * struct ufs_query - holds relevant data structures for query request + * @request: request upiu and function + * @descriptor: buffer for sending/receiving descriptor + * @response: response upiu and response + */ +struct ufs_query { + struct ufs_query_req request; + u8 *descriptor; + struct ufs_query_res response; +}; + +/** + * struct ufs_dev_cmd - all assosiated fields with device management commands + * @type: device management command type - Query, NOP OUT + * @tag_wq: wait queue until free command slot is available + */ +struct ufs_dev_cmd { + enum dev_cmd_type type; + struct ufs_query query; +}; + +struct ufs_hba_ops { + int (*init)(struct ufs_hba *hba); + int (*hce_enable_notify)(struct ufs_hba *hba, + enum ufs_notify_change_status); + int (*link_startup_notify)(struct ufs_hba *hba, + enum ufs_notify_change_status); + int (*phy_initialization)(struct ufs_hba *hba); +}; + +struct ufs_hba { + struct udevice *dev; + void __iomem *mmio_base; + struct ufs_hba_ops *ops; + struct ufs_desc_size desc_size; + u32 capabilities; + u32 version; + u32 intr_mask; + u32 quirks; +/* + * If UFS host controller is having issue in processing LCC (Line + * Control Command) coming from device then enable this quirk. + * When this quirk is enabled, host controller driver should disable + * the LCC transmission on UFS device (by clearing TX_LCC_ENABLE + * attribute of device to 0). + */ +#define UFSHCD_QUIRK_BROKEN_LCC 0x1 + + /* Virtual memory reference */ + struct utp_transfer_cmd_desc *ucdl; + struct utp_transfer_req_desc *utrdl; + /* TODO: Add Task Manegement Support */ + struct utp_task_req_desc *utmrdl; + + struct utp_upiu_req *ucd_req_ptr; + struct utp_upiu_rsp *ucd_rsp_ptr; + struct ufshcd_sg_entry *ucd_prdt_ptr; + + /* Power Mode information */ + enum ufs_dev_pwr_mode curr_dev_pwr_mode; + struct ufs_pa_layer_attr pwr_info; + struct ufs_pwr_mode_info max_pwr_info; + + struct ufs_dev_cmd dev_cmd; +}; + +static inline int ufshcd_ops_init(struct ufs_hba *hba) +{ + if (hba->ops && hba->ops->init) + return hba->ops->init(hba); + + return 0; +} + +static inline int ufshcd_ops_hce_enable_notify(struct ufs_hba *hba, + bool status) +{ + if (hba->ops && hba->ops->hce_enable_notify) + return hba->ops->hce_enable_notify(hba, status); + + return 0; +} + +static inline int ufshcd_ops_link_startup_notify(struct ufs_hba *hba, + bool status) +{ + if (hba->ops && hba->ops->link_startup_notify) + return hba->ops->link_startup_notify(hba, status); + + return 0; +} + +/* Controller UFSHCI version */ +enum { + UFSHCI_VERSION_10 = 0x00010000, /* 1.0 */ + UFSHCI_VERSION_11 = 0x00010100, /* 1.1 */ + UFSHCI_VERSION_20 = 0x00000200, /* 2.0 */ + UFSHCI_VERSION_21 = 0x00000210, /* 2.1 */ +}; + +/* Interrupt disable masks */ +enum { + /* Interrupt disable mask for UFSHCI v1.0 */ + INTERRUPT_MASK_ALL_VER_10 = 0x30FFF, + INTERRUPT_MASK_RW_VER_10 = 0x30000, + + /* Interrupt disable mask for UFSHCI v1.1 */ + INTERRUPT_MASK_ALL_VER_11 = 0x31FFF, + + /* Interrupt disable mask for UFSHCI v2.1 */ + INTERRUPT_MASK_ALL_VER_21 = 0x71FFF, +}; + +/* UFSHCI Registers */ +enum { + REG_CONTROLLER_CAPABILITIES = 0x00, + REG_UFS_VERSION = 0x08, + REG_CONTROLLER_DEV_ID = 0x10, + REG_CONTROLLER_PROD_ID = 0x14, + REG_AUTO_HIBERNATE_IDLE_TIMER = 0x18, + REG_INTERRUPT_STATUS = 0x20, + REG_INTERRUPT_ENABLE = 0x24, + REG_CONTROLLER_STATUS = 0x30, + REG_CONTROLLER_ENABLE = 0x34, + REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER = 0x38, + REG_UIC_ERROR_CODE_DATA_LINK_LAYER = 0x3C, + REG_UIC_ERROR_CODE_NETWORK_LAYER = 0x40, + REG_UIC_ERROR_CODE_TRANSPORT_LAYER = 0x44, + REG_UIC_ERROR_CODE_DME = 0x48, + REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL = 0x4C, + REG_UTP_TRANSFER_REQ_LIST_BASE_L = 0x50, + REG_UTP_TRANSFER_REQ_LIST_BASE_H = 0x54, + REG_UTP_TRANSFER_REQ_DOOR_BELL = 0x58, + REG_UTP_TRANSFER_REQ_LIST_CLEAR = 0x5C, + REG_UTP_TRANSFER_REQ_LIST_RUN_STOP = 0x60, + REG_UTP_TASK_REQ_LIST_BASE_L = 0x70, + REG_UTP_TASK_REQ_LIST_BASE_H = 0x74, + REG_UTP_TASK_REQ_DOOR_BELL = 0x78, + REG_UTP_TASK_REQ_LIST_CLEAR = 0x7C, + REG_UTP_TASK_REQ_LIST_RUN_STOP = 0x80, + REG_UIC_COMMAND = 0x90, + REG_UIC_COMMAND_ARG_1 = 0x94, + REG_UIC_COMMAND_ARG_2 = 0x98, + REG_UIC_COMMAND_ARG_3 = 0x9C, + + UFSHCI_REG_SPACE_SIZE = 0xA0, + + REG_UFS_CCAP = 0x100, + REG_UFS_CRYPTOCAP = 0x104, + + UFSHCI_CRYPTO_REG_SPACE_SIZE = 0x400, +}; + +/* Controller capability masks */ +enum { + MASK_TRANSFER_REQUESTS_SLOTS = 0x0000001F, + MASK_TASK_MANAGEMENT_REQUEST_SLOTS = 0x00070000, + MASK_AUTO_HIBERN8_SUPPORT = 0x00800000, + MASK_64_ADDRESSING_SUPPORT = 0x01000000, + MASK_OUT_OF_ORDER_DATA_DELIVERY_SUPPORT = 0x02000000, + MASK_UIC_DME_TEST_MODE_SUPPORT = 0x04000000, +}; + +/* Interrupt Status 20h */ +#define UTP_TRANSFER_REQ_COMPL 0x1 +#define UIC_DME_END_PT_RESET 0x2 +#define UIC_ERROR 0x4 +#define UIC_TEST_MODE 0x8 +#define UIC_POWER_MODE 0x10 +#define UIC_HIBERNATE_EXIT 0x20 +#define UIC_HIBERNATE_ENTER 0x40 +#define UIC_LINK_LOST 0x80 +#define UIC_LINK_STARTUP 0x100 +#define UTP_TASK_REQ_COMPL 0x200 +#define UIC_COMMAND_COMPL 0x400 +#define DEVICE_FATAL_ERROR 0x800 +#define CONTROLLER_FATAL_ERROR 0x10000 +#define SYSTEM_BUS_FATAL_ERROR 0x20000 + +#define UFSHCD_UIC_PWR_MASK (UIC_HIBERNATE_ENTER |\ + UIC_HIBERNATE_EXIT |\ + UIC_POWER_MODE) + +#define UFSHCD_UIC_MASK (UIC_COMMAND_COMPL | UIC_POWER_MODE) + +#define UFSHCD_ERROR_MASK (UIC_ERROR |\ + DEVICE_FATAL_ERROR |\ + CONTROLLER_FATAL_ERROR |\ + SYSTEM_BUS_FATAL_ERROR) + +#define INT_FATAL_ERRORS (DEVICE_FATAL_ERROR |\ + CONTROLLER_FATAL_ERROR |\ + SYSTEM_BUS_FATAL_ERROR) + +/* Host Controller Enable 0x34h */ +#define CONTROLLER_ENABLE 0x1 +#define CONTROLLER_DISABLE 0x0 +/* HCS - Host Controller Status 30h */ +#define DEVICE_PRESENT 0x1 +#define UTP_TRANSFER_REQ_LIST_READY 0x2 +#define UTP_TASK_REQ_LIST_READY 0x4 +#define UIC_COMMAND_READY 0x8 +#define HOST_ERROR_INDICATOR 0x10 +#define DEVICE_ERROR_INDICATOR 0x20 +#define UIC_POWER_MODE_CHANGE_REQ_STATUS_MASK UFS_MASK(0x7, 8) + +#define UFSHCD_STATUS_READY (UTP_TRANSFER_REQ_LIST_READY |\ + UTP_TASK_REQ_LIST_READY |\ + UIC_COMMAND_READY) + +enum { + PWR_OK = 0x0, + PWR_LOCAL = 0x01, + PWR_REMOTE = 0x02, + PWR_BUSY = 0x03, + PWR_ERROR_CAP = 0x04, + PWR_FATAL_ERROR = 0x05, +}; + +/* UICCMD - UIC Command */ +#define COMMAND_OPCODE_MASK 0xFF +#define GEN_SELECTOR_INDEX_MASK 0xFFFF + +#define MIB_ATTRIBUTE_MASK UFS_MASK(0xFFFF, 16) +#define RESET_LEVEL 0xFF + +#define ATTR_SET_TYPE_MASK UFS_MASK(0xFF, 16) +#define CONFIG_RESULT_CODE_MASK 0xFF +#define GENERIC_ERROR_CODE_MASK 0xFF + +#define ufshcd_writel(hba, val, reg) \ + writel((val), (hba)->mmio_base + (reg)) +#define ufshcd_readl(hba, reg) \ + readl((hba)->mmio_base + (reg)) + +/* UTRLRSR - UTP Transfer Request Run-Stop Register 60h */ +#define UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT 0x1 + +/* UTMRLRSR - UTP Task Management Request Run-Stop Register 80h */ +#define UTP_TASK_REQ_LIST_RUN_STOP_BIT 0x1 + +int ufshcd_probe(struct udevice *dev, struct ufs_hba_ops *hba_ops); + +#endif diff --git a/drivers/ufs/unipro.h b/drivers/ufs/unipro.h new file mode 100644 index 0000000..b30b17f --- /dev/null +++ b/drivers/ufs/unipro.h @@ -0,0 +1,270 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +#ifndef _UNIPRO_H_ +#define _UNIPRO_H_ + +/* + * M-TX Configuration Attributes + */ +#define TX_HIBERN8TIME_CAPABILITY 0x000F +#define TX_MODE 0x0021 +#define TX_HSRATE_SERIES 0x0022 +#define TX_HSGEAR 0x0023 +#define TX_PWMGEAR 0x0024 +#define TX_AMPLITUDE 0x0025 +#define TX_HS_SLEWRATE 0x0026 +#define TX_SYNC_SOURCE 0x0027 +#define TX_HS_SYNC_LENGTH 0x0028 +#define TX_HS_PREPARE_LENGTH 0x0029 +#define TX_LS_PREPARE_LENGTH 0x002A +#define TX_HIBERN8_CONTROL 0x002B +#define TX_LCC_ENABLE 0x002C +#define TX_PWM_BURST_CLOSURE_EXTENSION 0x002D +#define TX_BYPASS_8B10B_ENABLE 0x002E +#define TX_DRIVER_POLARITY 0x002F +#define TX_HS_UNTERMINATED_LINE_DRIVE_ENABLE 0x0030 +#define TX_LS_TERMINATED_LINE_DRIVE_ENABLE 0x0031 +#define TX_LCC_SEQUENCER 0x0032 +#define TX_MIN_ACTIVATETIME 0x0033 +#define TX_PWM_G6_G7_SYNC_LENGTH 0x0034 +#define TX_REFCLKFREQ 0x00EB +#define TX_CFGCLKFREQVAL 0x00EC +#define CFGEXTRATTR 0x00F0 +#define DITHERCTRL2 0x00F1 + +/* + * M-RX Configuration Attributes + */ +#define RX_MODE 0x00A1 +#define RX_HSRATE_SERIES 0x00A2 +#define RX_HSGEAR 0x00A3 +#define RX_PWMGEAR 0x00A4 +#define RX_LS_TERMINATED_ENABLE 0x00A5 +#define RX_HS_UNTERMINATED_ENABLE 0x00A6 +#define RX_ENTER_HIBERN8 0x00A7 +#define RX_BYPASS_8B10B_ENABLE 0x00A8 +#define RX_TERMINATION_FORCE_ENABLE 0x0089 +#define RX_MIN_ACTIVATETIME_CAPABILITY 0x008F +#define RX_HIBERN8TIME_CAPABILITY 0x0092 +#define RX_REFCLKFREQ 0x00EB +#define RX_CFGCLKFREQVAL 0x00EC +#define CFGWIDEINLN 0x00F0 +#define CFGRXCDR8 0x00BA +#define ENARXDIRECTCFG4 0x00F2 +#define CFGRXOVR8 0x00BD +#define RXDIRECTCTRL2 0x00C7 +#define ENARXDIRECTCFG3 0x00F3 +#define RXCALCTRL 0x00B4 +#define ENARXDIRECTCFG2 0x00F4 +#define CFGRXOVR4 0x00E9 +#define RXSQCTRL 0x00B5 +#define CFGRXOVR6 0x00BF + +#define is_mphy_tx_attr(attr) (attr < RX_MODE) +#define RX_MIN_ACTIVATETIME_UNIT_US 100 +#define HIBERN8TIME_UNIT_US 100 + +/* + * Common Block Attributes + */ +#define TX_GLOBALHIBERNATE UNIPRO_CB_OFFSET(0x002B) +#define REFCLKMODE UNIPRO_CB_OFFSET(0x00BF) +#define DIRECTCTRL19 UNIPRO_CB_OFFSET(0x00CD) +#define DIRECTCTRL10 UNIPRO_CB_OFFSET(0x00E6) +#define CDIRECTCTRL6 UNIPRO_CB_OFFSET(0x00EA) +#define RTOBSERVESELECT UNIPRO_CB_OFFSET(0x00F0) +#define CBDIVFACTOR UNIPRO_CB_OFFSET(0x00F1) +#define CBDCOCTRL5 UNIPRO_CB_OFFSET(0x00F3) +#define CBPRGPLL2 UNIPRO_CB_OFFSET(0x00F8) +#define CBPRGTUNING UNIPRO_CB_OFFSET(0x00FB) + +#define UNIPRO_CB_OFFSET(x) (0x8000 | x) + +/* + * PHY Adpater attributes + */ +#define PA_ACTIVETXDATALANES 0x1560 +#define PA_ACTIVERXDATALANES 0x1580 +#define PA_TXTRAILINGCLOCKS 0x1564 +#define PA_PHY_TYPE 0x1500 +#define PA_AVAILTXDATALANES 0x1520 +#define PA_AVAILRXDATALANES 0x1540 +#define PA_MINRXTRAILINGCLOCKS 0x1543 +#define PA_TXPWRSTATUS 0x1567 +#define PA_RXPWRSTATUS 0x1582 +#define PA_TXFORCECLOCK 0x1562 +#define PA_TXPWRMODE 0x1563 +#define PA_LEGACYDPHYESCDL 0x1570 +#define PA_MAXTXSPEEDFAST 0x1521 +#define PA_MAXTXSPEEDSLOW 0x1522 +#define PA_MAXRXSPEEDFAST 0x1541 +#define PA_MAXRXSPEEDSLOW 0x1542 +#define PA_TXLINKSTARTUPHS 0x1544 +#define PA_LOCAL_TX_LCC_ENABLE 0x155E +#define PA_TXSPEEDFAST 0x1565 +#define PA_TXSPEEDSLOW 0x1566 +#define PA_REMOTEVERINFO 0x15A0 +#define PA_TXGEAR 0x1568 +#define PA_TXTERMINATION 0x1569 +#define PA_HSSERIES 0x156A +#define PA_PWRMODE 0x1571 +#define PA_RXGEAR 0x1583 +#define PA_RXTERMINATION 0x1584 +#define PA_MAXRXPWMGEAR 0x1586 +#define PA_MAXRXHSGEAR 0x1587 +#define PA_RXHSUNTERMCAP 0x15A5 +#define PA_RXLSTERMCAP 0x15A6 +#define PA_GRANULARITY 0x15AA +#define PA_PACPREQTIMEOUT 0x1590 +#define PA_PACPREQEOBTIMEOUT 0x1591 +#define PA_HIBERN8TIME 0x15A7 +#define PA_LOCALVERINFO 0x15A9 +#define PA_TACTIVATE 0x15A8 +#define PA_PACPFRAMECOUNT 0x15C0 +#define PA_PACPERRORCOUNT 0x15C1 +#define PA_PHYTESTCONTROL 0x15C2 +#define PA_PWRMODEUSERDATA0 0x15B0 +#define PA_PWRMODEUSERDATA1 0x15B1 +#define PA_PWRMODEUSERDATA2 0x15B2 +#define PA_PWRMODEUSERDATA3 0x15B3 +#define PA_PWRMODEUSERDATA4 0x15B4 +#define PA_PWRMODEUSERDATA5 0x15B5 +#define PA_PWRMODEUSERDATA6 0x15B6 +#define PA_PWRMODEUSERDATA7 0x15B7 +#define PA_PWRMODEUSERDATA8 0x15B8 +#define PA_PWRMODEUSERDATA9 0x15B9 +#define PA_PWRMODEUSERDATA10 0x15BA +#define PA_PWRMODEUSERDATA11 0x15BB +#define PA_CONNECTEDTXDATALANES 0x1561 +#define PA_CONNECTEDRXDATALANES 0x1581 +#define PA_LOGICALLANEMAP 0x15A1 +#define PA_SLEEPNOCONFIGTIME 0x15A2 +#define PA_STALLNOCONFIGTIME 0x15A3 +#define PA_SAVECONFIGTIME 0x15A4 + +#define PA_TACTIVATE_TIME_UNIT_US 10 +#define PA_HIBERN8_TIME_UNIT_US 100 + +/*Other attributes*/ +#define VS_MPHYCFGUPDT 0xD085 +#define VS_DEBUGOMC 0xD09E +#define VS_POWERSTATE 0xD083 + +#define PA_GRANULARITY_MIN_VAL 1 +#define PA_GRANULARITY_MAX_VAL 6 + +/* PHY Adapter Protocol Constants */ +#define PA_MAXDATALANES 4 + +/* PA power modes */ +enum { + FAST_MODE = 1, + SLOW_MODE = 2, + FASTAUTO_MODE = 4, + SLOWAUTO_MODE = 5, + UNCHANGED = 7, +}; + +/* PA TX/RX Frequency Series */ +enum { + PA_HS_MODE_A = 1, + PA_HS_MODE_B = 2, +}; + +enum ufs_pwm_gear_tag { + UFS_PWM_DONT_CHANGE, /* Don't change Gear */ + UFS_PWM_G1, /* PWM Gear 1 (default for reset) */ + UFS_PWM_G2, /* PWM Gear 2 */ + UFS_PWM_G3, /* PWM Gear 3 */ + UFS_PWM_G4, /* PWM Gear 4 */ + UFS_PWM_G5, /* PWM Gear 5 */ + UFS_PWM_G6, /* PWM Gear 6 */ + UFS_PWM_G7, /* PWM Gear 7 */ +}; + +enum ufs_hs_gear_tag { + UFS_HS_DONT_CHANGE, /* Don't change Gear */ + UFS_HS_G1, /* HS Gear 1 (default for reset) */ + UFS_HS_G2, /* HS Gear 2 */ + UFS_HS_G3, /* HS Gear 3 */ +}; + +enum ufs_unipro_ver { + UFS_UNIPRO_VER_RESERVED = 0, + UFS_UNIPRO_VER_1_40 = 1, /* UniPro version 1.40 */ + UFS_UNIPRO_VER_1_41 = 2, /* UniPro version 1.41 */ + UFS_UNIPRO_VER_1_6 = 3, /* UniPro version 1.6 */ + UFS_UNIPRO_VER_MAX = 4, /* UniPro unsupported version */ + /* UniPro version field mask in PA_LOCALVERINFO */ + UFS_UNIPRO_VER_MASK = 0xF, +}; + +/* + * Data Link Layer Attributes + */ +#define DL_TC0TXFCTHRESHOLD 0x2040 +#define DL_FC0PROTTIMEOUTVAL 0x2041 +#define DL_TC0REPLAYTIMEOUTVAL 0x2042 +#define DL_AFC0REQTIMEOUTVAL 0x2043 +#define DL_AFC0CREDITTHRESHOLD 0x2044 +#define DL_TC0OUTACKTHRESHOLD 0x2045 +#define DL_TC1TXFCTHRESHOLD 0x2060 +#define DL_FC1PROTTIMEOUTVAL 0x2061 +#define DL_TC1REPLAYTIMEOUTVAL 0x2062 +#define DL_AFC1REQTIMEOUTVAL 0x2063 +#define DL_AFC1CREDITTHRESHOLD 0x2064 +#define DL_TC1OUTACKTHRESHOLD 0x2065 +#define DL_TXPREEMPTIONCAP 0x2000 +#define DL_TC0TXMAXSDUSIZE 0x2001 +#define DL_TC0RXINITCREDITVAL 0x2002 +#define DL_TC0TXBUFFERSIZE 0x2005 +#define DL_PEERTC0PRESENT 0x2046 +#define DL_PEERTC0RXINITCREVAL 0x2047 +#define DL_TC1TXMAXSDUSIZE 0x2003 +#define DL_TC1RXINITCREDITVAL 0x2004 +#define DL_TC1TXBUFFERSIZE 0x2006 +#define DL_PEERTC1PRESENT 0x2066 +#define DL_PEERTC1RXINITCREVAL 0x2067 + +/* + * Network Layer Attributes + */ +#define N_DEVICEID 0x3000 +#define N_DEVICEID_VALID 0x3001 +#define N_TC0TXMAXSDUSIZE 0x3020 +#define N_TC1TXMAXSDUSIZE 0x3021 + +/* + * Transport Layer Attributes + */ +#define T_NUMCPORTS 0x4000 +#define T_NUMTESTFEATURES 0x4001 +#define T_CONNECTIONSTATE 0x4020 +#define T_PEERDEVICEID 0x4021 +#define T_PEERCPORTID 0x4022 +#define T_TRAFFICCLASS 0x4023 +#define T_PROTOCOLID 0x4024 +#define T_CPORTFLAGS 0x4025 +#define T_TXTOKENVALUE 0x4026 +#define T_RXTOKENVALUE 0x4027 +#define T_LOCALBUFFERSPACE 0x4028 +#define T_PEERBUFFERSPACE 0x4029 +#define T_CREDITSTOSEND 0x402A +#define T_CPORTMODE 0x402B +#define T_TC0TXMAXSDUSIZE 0x4060 +#define T_TC1TXMAXSDUSIZE 0x4061 + +#ifdef FALSE +#undef FALSE +#endif + +#ifdef TRUE +#undef TRUE +#endif + +/* Boolean attribute values */ +enum { + FALSE = 0, + TRUE, +}; + +#endif /* _UNIPRO_H_ */ diff --git a/drivers/usb/dwc3/Kconfig b/drivers/usb/dwc3/Kconfig index 25e1a38..c302486 100644 --- a/drivers/usb/dwc3/Kconfig +++ b/drivers/usb/dwc3/Kconfig @@ -7,25 +7,11 @@ config USB_DWC3 if USB_DWC3 -choice - bool "DWC3 Mode Selection" - -config USB_DWC3_HOST - bool "Host only mode" - depends on USB - help - Select this when you want to use DWC3 in host mode only, - thereby the gadget feature will be regressed. - config USB_DWC3_GADGET - bool "Gadget only mode" + bool "USB Gadget support for DWC3" + default y depends on USB_GADGET select USB_GADGET_DUALSPEED - help - Select this when you want to use DWC3 in gadget mode only, - thereby the host feature will be regressed. - -endchoice comment "Platform Glue Driver Support" diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index 2498f0e..23af60c 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -581,6 +581,12 @@ static int dwc3_core_init_mode(struct dwc3 *dwc) return 0; } +static void dwc3_gadget_run(struct dwc3 *dwc) +{ + dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_RUN_STOP); + mdelay(100); +} + static void dwc3_core_exit_mode(struct dwc3 *dwc) { switch (dwc->dr_mode) { @@ -598,6 +604,13 @@ static void dwc3_core_exit_mode(struct dwc3 *dwc) /* do nothing */ break; } + + /* + * switch back to peripheral mode + * This enables the phy to enter idle and then, if enabled, suspend. + */ + dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE); + dwc3_gadget_run(dwc); } #define DWC3_ALIGN_MASK (16 - 1) @@ -694,9 +707,9 @@ int dwc3_uboot_init(struct dwc3_device *dwc3_dev) return -ENOMEM; } - if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) + if (!IS_ENABLED(CONFIG_USB_DWC3_GADGET)) dwc->dr_mode = USB_DR_MODE_HOST; - else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) + else if (!IS_ENABLED(CONFIG_USB_HOST)) dwc->dr_mode = USB_DR_MODE_PERIPHERAL; if (dwc->dr_mode == USB_DR_MODE_UNKNOWN) @@ -874,7 +887,72 @@ int dwc3_shutdown_phy(struct udevice *dev, struct phy *usb_phys, int num_phys) } #endif -#if CONFIG_IS_ENABLED(DM_USB_GADGET) +#if CONFIG_IS_ENABLED(DM_USB) +void dwc3_of_parse(struct dwc3 *dwc) +{ + const u8 *tmp; + struct udevice *dev = dwc->dev; + u8 lpm_nyet_threshold; + u8 tx_de_emphasis; + u8 hird_threshold; + + /* default to highest possible threshold */ + lpm_nyet_threshold = 0xff; + + /* default to -3.5dB de-emphasis */ + tx_de_emphasis = 1; + + /* + * default to assert utmi_sleep_n and use maximum allowed HIRD + * threshold value of 0b1100 + */ + hird_threshold = 12; + + dwc->has_lpm_erratum = dev_read_bool(dev, + "snps,has-lpm-erratum"); + tmp = dev_read_u8_array_ptr(dev, "snps,lpm-nyet-threshold", 1); + if (tmp) + lpm_nyet_threshold = *tmp; + + dwc->is_utmi_l1_suspend = dev_read_bool(dev, + "snps,is-utmi-l1-suspend"); + tmp = dev_read_u8_array_ptr(dev, "snps,hird-threshold", 1); + if (tmp) + hird_threshold = *tmp; + + dwc->disable_scramble_quirk = dev_read_bool(dev, + "snps,disable_scramble_quirk"); + dwc->u2exit_lfps_quirk = dev_read_bool(dev, + "snps,u2exit_lfps_quirk"); + dwc->u2ss_inp3_quirk = dev_read_bool(dev, + "snps,u2ss_inp3_quirk"); + dwc->req_p1p2p3_quirk = dev_read_bool(dev, + "snps,req_p1p2p3_quirk"); + dwc->del_p1p2p3_quirk = dev_read_bool(dev, + "snps,del_p1p2p3_quirk"); + dwc->del_phy_power_chg_quirk = dev_read_bool(dev, + "snps,del_phy_power_chg_quirk"); + dwc->lfps_filter_quirk = dev_read_bool(dev, + "snps,lfps_filter_quirk"); + dwc->rx_detect_poll_quirk = dev_read_bool(dev, + "snps,rx_detect_poll_quirk"); + dwc->dis_u3_susphy_quirk = dev_read_bool(dev, + "snps,dis_u3_susphy_quirk"); + dwc->dis_u2_susphy_quirk = dev_read_bool(dev, + "snps,dis_u2_susphy_quirk"); + dwc->tx_de_emphasis_quirk = dev_read_bool(dev, + "snps,tx_de_emphasis_quirk"); + tmp = dev_read_u8_array_ptr(dev, "snps,tx_de_emphasis", 1); + if (tmp) + tx_de_emphasis = *tmp; + + dwc->lpm_nyet_threshold = lpm_nyet_threshold; + dwc->tx_de_emphasis = tx_de_emphasis; + + dwc->hird_threshold = hird_threshold + | (dwc->is_utmi_l1_suspend << 4); +} + int dwc3_init(struct dwc3 *dwc) { int ret; diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h index cfe2988..be96722 100644 --- a/drivers/usb/dwc3/core.h +++ b/drivers/usb/dwc3/core.h @@ -991,18 +991,14 @@ struct dwc3_gadget_ep_cmd_params { /* prototypes */ int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc); +void dwc3_of_parse(struct dwc3 *dwc); int dwc3_init(struct dwc3 *dwc); void dwc3_remove(struct dwc3 *dwc); -#ifdef CONFIG_USB_DWC3_HOST -int dwc3_host_init(struct dwc3 *dwc); -void dwc3_host_exit(struct dwc3 *dwc); -#else static inline int dwc3_host_init(struct dwc3 *dwc) { return 0; } static inline void dwc3_host_exit(struct dwc3 *dwc) { } -#endif #ifdef CONFIG_USB_DWC3_GADGET int dwc3_gadget_init(struct dwc3 *dwc); diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c index 406bf0b..023e953 100644 --- a/drivers/usb/dwc3/dwc3-generic.c +++ b/drivers/usb/dwc3/dwc3-generic.c @@ -21,51 +21,60 @@ #include "gadget.h" #include <reset.h> #include <clk.h> +#include <usb/xhci.h> -#if CONFIG_IS_ENABLED(DM_USB_GADGET) -struct dwc3_generic_peripheral { +struct dwc3_generic_plat { + fdt_addr_t base; + u32 maximum_speed; + enum usb_dr_mode dr_mode; +}; + +struct dwc3_generic_priv { + void *base; struct dwc3 dwc3; struct phy *phys; int num_phys; - fdt_addr_t base; }; -int dm_usb_gadget_handle_interrupts(struct udevice *dev) -{ - struct dwc3_generic_peripheral *priv = dev_get_priv(dev); - struct dwc3 *dwc3 = &priv->dwc3; - - dwc3_gadget_uboot_handle_interrupt(dwc3); - - return 0; -} +struct dwc3_generic_host_priv { + struct xhci_ctrl xhci_ctrl; + struct dwc3_generic_priv gen_priv; +}; -static int dwc3_generic_peripheral_probe(struct udevice *dev) +static int dwc3_generic_probe(struct udevice *dev, + struct dwc3_generic_priv *priv) { int rc; - struct dwc3_generic_peripheral *priv = dev_get_priv(dev); + struct dwc3_generic_plat *plat = dev_get_platdata(dev); struct dwc3 *dwc3 = &priv->dwc3; + dwc3->dev = dev; + dwc3->maximum_speed = plat->maximum_speed; + dwc3->dr_mode = plat->dr_mode; +#if CONFIG_IS_ENABLED(OF_CONTROL) + dwc3_of_parse(dwc3); +#endif + rc = dwc3_setup_phy(dev, &priv->phys, &priv->num_phys); if (rc) return rc; - dwc3->regs = map_physmem(priv->base, DWC3_OTG_REGS_END, MAP_NOCACHE); - dwc3->regs += DWC3_GLOBALS_REGS_START; - dwc3->dev = dev; + priv->base = map_physmem(plat->base, DWC3_OTG_REGS_END, MAP_NOCACHE); + dwc3->regs = priv->base + DWC3_GLOBALS_REGS_START; + rc = dwc3_init(dwc3); if (rc) { - unmap_physmem(dwc3->regs, MAP_NOCACHE); + unmap_physmem(priv->base, MAP_NOCACHE); return rc; } return 0; } -static int dwc3_generic_peripheral_remove(struct udevice *dev) +static int dwc3_generic_remove(struct udevice *dev, + struct dwc3_generic_priv *priv) { - struct dwc3_generic_peripheral *priv = dev_get_priv(dev); struct dwc3 *dwc3 = &priv->dwc3; dwc3_remove(dwc3); @@ -75,22 +84,21 @@ static int dwc3_generic_peripheral_remove(struct udevice *dev) return 0; } -static int dwc3_generic_peripheral_ofdata_to_platdata(struct udevice *dev) +static int dwc3_generic_ofdata_to_platdata(struct udevice *dev) { - struct dwc3_generic_peripheral *priv = dev_get_priv(dev); - struct dwc3 *dwc3 = &priv->dwc3; + struct dwc3_generic_plat *plat = dev_get_platdata(dev); int node = dev_of_offset(dev); - priv->base = devfdt_get_addr(dev); + plat->base = devfdt_get_addr(dev); - dwc3->maximum_speed = usb_get_maximum_speed(node); - if (dwc3->maximum_speed == USB_SPEED_UNKNOWN) { - pr_err("Invalid usb maximum speed\n"); - return -ENODEV; + plat->maximum_speed = usb_get_maximum_speed(node); + if (plat->maximum_speed == USB_SPEED_UNKNOWN) { + pr_info("No USB maximum speed specified. Using super speed\n"); + plat->maximum_speed = USB_SPEED_SUPER; } - dwc3->dr_mode = usb_get_dr_mode(node); - if (dwc3->dr_mode == USB_DR_MODE_UNKNOWN) { + plat->dr_mode = usb_get_dr_mode(node); + if (plat->dr_mode == USB_DR_MODE_UNKNOWN) { pr_err("Invalid usb mode setup\n"); return -ENODEV; } @@ -98,13 +106,83 @@ static int dwc3_generic_peripheral_ofdata_to_platdata(struct udevice *dev) return 0; } +#if CONFIG_IS_ENABLED(DM_USB_GADGET) +int dm_usb_gadget_handle_interrupts(struct udevice *dev) +{ + struct dwc3_generic_priv *priv = dev_get_priv(dev); + struct dwc3 *dwc3 = &priv->dwc3; + + dwc3_gadget_uboot_handle_interrupt(dwc3); + + return 0; +} + +static int dwc3_generic_peripheral_probe(struct udevice *dev) +{ + struct dwc3_generic_priv *priv = dev_get_priv(dev); + + return dwc3_generic_probe(dev, priv); +} + +static int dwc3_generic_peripheral_remove(struct udevice *dev) +{ + struct dwc3_generic_priv *priv = dev_get_priv(dev); + + return dwc3_generic_remove(dev, priv); +} + U_BOOT_DRIVER(dwc3_generic_peripheral) = { .name = "dwc3-generic-peripheral", .id = UCLASS_USB_GADGET_GENERIC, - .ofdata_to_platdata = dwc3_generic_peripheral_ofdata_to_platdata, + .ofdata_to_platdata = dwc3_generic_ofdata_to_platdata, .probe = dwc3_generic_peripheral_probe, .remove = dwc3_generic_peripheral_remove, - .priv_auto_alloc_size = sizeof(struct dwc3_generic_peripheral), + .priv_auto_alloc_size = sizeof(struct dwc3_generic_priv), + .platdata_auto_alloc_size = sizeof(struct dwc3_generic_plat), +}; +#endif + +#if defined(CONFIG_SPL_USB_HOST_SUPPORT) || !defined(CONFIG_SPL_BUILD) +static int dwc3_generic_host_probe(struct udevice *dev) +{ + struct xhci_hcor *hcor; + struct xhci_hccr *hccr; + struct dwc3_generic_host_priv *priv = dev_get_priv(dev); + int rc; + + rc = dwc3_generic_probe(dev, &priv->gen_priv); + if (rc) + return rc; + + hccr = (struct xhci_hccr *)priv->gen_priv.base; + hcor = (struct xhci_hcor *)(priv->gen_priv.base + + HC_LENGTH(xhci_readl(&(hccr)->cr_capbase))); + + return xhci_register(dev, hccr, hcor); +} + +static int dwc3_generic_host_remove(struct udevice *dev) +{ + struct dwc3_generic_host_priv *priv = dev_get_priv(dev); + int rc; + + rc = xhci_deregister(dev); + if (rc) + return rc; + + return dwc3_generic_remove(dev, &priv->gen_priv); +} + +U_BOOT_DRIVER(dwc3_generic_host) = { + .name = "dwc3-generic-host", + .id = UCLASS_USB, + .ofdata_to_platdata = dwc3_generic_ofdata_to_platdata, + .probe = dwc3_generic_host_probe, + .remove = dwc3_generic_host_remove, + .priv_auto_alloc_size = sizeof(struct dwc3_generic_host_priv), + .platdata_auto_alloc_size = sizeof(struct dwc3_generic_plat), + .ops = &xhci_usb_ops, + .flags = DM_FLAG_ALLOC_PRIV_DMA, }; #endif @@ -228,10 +306,12 @@ static int dwc3_glue_bind(struct udevice *parent) driver = "dwc3-generic-peripheral"; #endif break; +#if defined(CONFIG_SPL_USB_HOST_SUPPORT) || !defined(CONFIG_SPL_BUILD) case USB_DR_MODE_HOST: debug("%s: dr_mode: HOST\n", __func__); - driver = "xhci-dwc3"; + driver = "dwc3-generic-host"; break; +#endif default: debug("%s: unsupported dr_mode\n", __func__); return -ENODEV; diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index 30c6b69..0987ff2 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -73,13 +73,6 @@ config USB_XHCI_STI STiH407 family SoCs. This is a driver for the dwc3 to provide the glue logic to configure the controller. -config USB_XHCI_ZYNQMP - bool "Support for Xilinx ZynqMP on-chip xHCI USB controller" - depends on ARCH_ZYNQMP - depends on DM_USB - help - Enables support for the on-chip xHCI controller on Xilinx ZynqMP SoCs. - config USB_XHCI_DRA7XX_INDEX int "DRA7XX xHCI USB index" range 0 1 @@ -141,8 +134,8 @@ config USB_EHCI_MX5 Enables support for the on-chip EHCI controller on i.MX5 SoCs. config USB_EHCI_MX6 - bool "Support for i.MX6 on-chip EHCI USB controller" - depends on ARCH_MX6 + bool "Support for i.MX6/i.MX7ULP on-chip EHCI USB controller" + depends on ARCH_MX6 || ARCH_MX7ULP default y ---help--- Enables support for the on-chip EHCI controller on i.MX6 SoCs. @@ -169,7 +162,7 @@ config USB_EHCI_VF help Enables support for the on-chip EHCI controller on Vybrid SoCs. -if USB_EHCI_MX7 +if USB_EHCI_MX6 || USB_EHCI_MX7 config MXC_USB_OTG_HACTIVE bool "USB Power pin high active" diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile index dd13528..7feeff6 100644 --- a/drivers/usb/host/Makefile +++ b/drivers/usb/host/Makefile @@ -48,7 +48,6 @@ obj-$(CONFIG_USB_XHCI_HCD) += xhci.o xhci-mem.o xhci-ring.o obj-$(CONFIG_USB_XHCI_DWC3) += xhci-dwc3.o obj-$(CONFIG_USB_XHCI_DWC3_OF_SIMPLE) += dwc3-of-simple.o obj-$(CONFIG_USB_XHCI_ROCKCHIP) += xhci-rockchip.o -obj-$(CONFIG_USB_XHCI_ZYNQMP) += xhci-zynqmp.o obj-$(CONFIG_USB_XHCI_EXYNOS) += xhci-exynos5.o obj-$(CONFIG_USB_XHCI_FSL) += xhci-fsl.o obj-$(CONFIG_USB_XHCI_MVEBU) += xhci-mvebu.o diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c index e9e6ed5..1993ad6 100644 --- a/drivers/usb/host/ehci-mx6.c +++ b/drivers/usb/host/ehci-mx6.c @@ -64,10 +64,12 @@ DECLARE_GLOBAL_DATA_PTR; #define UCMD_RUN_STOP (1 << 0) /* controller run/stop */ #define UCMD_RESET (1 << 1) /* controller reset */ -#if defined(CONFIG_MX6) +#if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP) static const unsigned phy_bases[] = { USB_PHY0_BASE_ADDR, +#if defined(USB_PHY1_BASE_ADDR) USB_PHY1_BASE_ADDR, +#endif }; static void usb_internal_phy_clock_gate(int index, int on) @@ -84,6 +86,20 @@ static void usb_internal_phy_clock_gate(int index, int on) static void usb_power_config(int index) { +#if defined(CONFIG_MX7ULP) + struct usbphy_regs __iomem *usbphy = + (struct usbphy_regs __iomem *)USB_PHY0_BASE_ADDR; + + if (index > 0) + return; + + writel(ANADIG_USB2_CHRG_DETECT_EN_B | + ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B, + &usbphy->usb1_chrg_detect); + + scg_enable_usb_pll(true); + +#else struct anatop_regs __iomem *anatop = (struct anatop_regs __iomem *)ANATOP_BASE_ADDR; void __iomem *chrg_detect; @@ -123,6 +139,8 @@ static void usb_power_config(int index) ANADIG_USB2_PLL_480_CTRL_POWER | ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS, pll_480_ctrl_set); + +#endif } /* Return 0 : host node, <>0 : device mode */ @@ -185,6 +203,14 @@ int usb_phy_mode(int port) return USB_INIT_HOST; } +#if defined(CONFIG_MX7ULP) +struct usbnc_regs { + u32 ctrl1; + u32 ctrl2; + u32 reserve0[2]; + u32 hsic_ctrl; +}; +#else /* Base address for this IP block is 0x02184800 */ struct usbnc_regs { u32 ctrl[4]; /* otg/host1-3 */ @@ -193,6 +219,8 @@ struct usbnc_regs { u32 otg_phy_ctrl_0; u32 uh1_phy_ctrl_0; }; +#endif + #elif defined(CONFIG_MX7) struct usbnc_regs { u32 ctrl1; @@ -213,20 +241,12 @@ static void usb_power_config(int index) struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR + (0x10000 * index) + USBNC_OFFSET); void __iomem *phy_cfg2 = (void __iomem *)(&usbnc->phy_cfg2); - void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl1); /* * Clear the ACAENB to enable usb_otg_id detection, * otherwise it is the ACA detection enabled. */ clrbits_le32(phy_cfg2, USBNC_PHYCFG2_ACAENB); - - /* Set power polarity to high active */ -#ifdef CONFIG_MXC_USB_OTG_HACTIVE - setbits_le32(ctrl, UCTRL_PWR_POL); -#else - clrbits_le32(ctrl, UCTRL_PWR_POL); -#endif } int usb_phy_mode(int port) @@ -251,7 +271,7 @@ static void usb_oc_config(int index) struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET); void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl[index]); -#elif defined(CONFIG_MX7) +#elif defined(CONFIG_MX7) || defined(CONFIG_MX7ULP) struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR + (0x10000 * index) + USBNC_OFFSET); void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl1); @@ -265,6 +285,13 @@ static void usb_oc_config(int index) #endif setbits_le32(ctrl, UCTRL_OVER_CUR_DIS); + + /* Set power polarity to high active */ +#ifdef CONFIG_MXC_USB_OTG_HACTIVE + setbits_le32(ctrl, UCTRL_PWR_POL); +#else + clrbits_le32(ctrl, UCTRL_PWR_POL); +#endif } /** @@ -328,7 +355,7 @@ int ehci_mx6_common_init(struct usb_ehci *ehci, int index) usb_power_config(index); usb_oc_config(index); -#if defined(CONFIG_MX6) +#if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP) usb_internal_phy_clock_gate(index, 1); usb_phy_enable(index, ehci); #endif @@ -343,7 +370,7 @@ int ehci_hcd_init(int index, enum usb_init_type init, enum usb_init_type type; #if defined(CONFIG_MX6) u32 controller_spacing = 0x200; -#elif defined(CONFIG_MX7) +#elif defined(CONFIG_MX7) || defined(CONFIG_MX7ULP) u32 controller_spacing = 0x10000; #endif struct usb_ehci *ehci = (struct usb_ehci *)(USB_BASE_ADDR + @@ -446,7 +473,7 @@ static int ehci_usb_phy_mode(struct udevice *dev) * About fsl,usbphy, Refer to * Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt. */ - if (is_mx6()) { + if (is_mx6() || is_mx7ulp()) { phy_off = fdtdec_lookup_phandle(blob, offset, "fsl,usbphy"); @@ -513,10 +540,11 @@ static int ehci_usb_bind(struct udevice *dev) * from which it derives offsets in the PHY and ANATOP register sets. * * Here we attempt to calculate these indexes from DT information as - * well as we can. The USB controllers on all existing iMX6/iMX7 SoCs - * are placed next to each other, at addresses incremented by 0x200. - * Thus, the index is derived from the multiple of 0x200 offset from - * the first controller address. + * well as we can. The USB controllers on all existing iMX6 SoCs + * are placed next to each other, at addresses incremented by 0x200, + * and iMX7 their addresses are shifted by 0x10000. + * Thus, the index is derived from the multiple of 0x200 (0x10000 for + * iMX7) offset from the first controller address. * * However, to complete conversion of this driver to DT probing, the * following has to be done: @@ -531,10 +559,10 @@ static int ehci_usb_bind(struct udevice *dev) * With these changes in place, the ad-hoc indexing goes away and * the driver is fully converted to DT probing. */ - fdt_size_t size; - fdt_addr_t addr = devfdt_get_addr_size_index(dev, 0, &size); + u32 controller_spacing = is_mx7() ? 0x10000 : 0x200; + fdt_addr_t addr = devfdt_get_addr_index(dev, 0); - dev->req_seq = (addr - USB_BASE_ADDR) / size; + dev->req_seq = (addr - USB_BASE_ADDR) / controller_spacing; return 0; } diff --git a/drivers/usb/host/xhci-dwc3.c b/drivers/usb/host/xhci-dwc3.c index 55a1b22..c1c681c 100644 --- a/drivers/usb/host/xhci-dwc3.c +++ b/drivers/usb/host/xhci-dwc3.c @@ -14,7 +14,7 @@ #include <usb.h> #include <dwc3-uboot.h> -#include "xhci.h" +#include <usb/xhci.h> #include <asm/io.h> #include <linux/usb/dwc3.h> #include <linux/usb/otg.h> diff --git a/drivers/usb/host/xhci-exynos5.c b/drivers/usb/host/xhci-exynos5.c index c150f52..25c30c2 100644 --- a/drivers/usb/host/xhci-exynos5.c +++ b/drivers/usb/host/xhci-exynos5.c @@ -27,7 +27,7 @@ #include <linux/compat.h> #include <linux/usb/dwc3.h> -#include "xhci.h" +#include <usb/xhci.h> /* Declare global data pointer */ DECLARE_GLOBAL_DATA_PTR; diff --git a/drivers/usb/host/xhci-fsl.c b/drivers/usb/host/xhci-fsl.c index c0b98a8..9e0c1b7 100644 --- a/drivers/usb/host/xhci-fsl.c +++ b/drivers/usb/host/xhci-fsl.c @@ -13,7 +13,7 @@ #include <linux/compat.h> #include <linux/usb/xhci-fsl.h> #include <linux/usb/dwc3.h> -#include "xhci.h" +#include <usb/xhci.h> #include <fsl_errata.h> #include <fsl_usb.h> #include <dm.h> diff --git a/drivers/usb/host/xhci-mem.c b/drivers/usb/host/xhci-mem.c index 84c2c33..530e979 100644 --- a/drivers/usb/host/xhci-mem.c +++ b/drivers/usb/host/xhci-mem.c @@ -21,7 +21,7 @@ #include <asm/cache.h> #include <linux/errno.h> -#include "xhci.h" +#include <usb/xhci.h> #define CACHELINE_SIZE CONFIG_SYS_CACHELINE_SIZE /** diff --git a/drivers/usb/host/xhci-mvebu.c b/drivers/usb/host/xhci-mvebu.c index b6c6aaf..2b87104 100644 --- a/drivers/usb/host/xhci-mvebu.c +++ b/drivers/usb/host/xhci-mvebu.c @@ -12,7 +12,7 @@ #include <power/regulator.h> #include <asm/gpio.h> -#include "xhci.h" +#include <usb/xhci.h> struct mvebu_xhci_platdata { fdt_addr_t hcd_base; diff --git a/drivers/usb/host/xhci-omap.c b/drivers/usb/host/xhci-omap.c index db007af..25b195f 100644 --- a/drivers/usb/host/xhci-omap.c +++ b/drivers/usb/host/xhci-omap.c @@ -19,7 +19,7 @@ #include <linux/usb/dwc3.h> #include <linux/usb/xhci-omap.h> -#include "xhci.h" +#include <usb/xhci.h> /* Declare global data pointer */ static struct omap_xhci omap; diff --git a/drivers/usb/host/xhci-pci.c b/drivers/usb/host/xhci-pci.c index b995aef..c1f60da 100644 --- a/drivers/usb/host/xhci-pci.c +++ b/drivers/usb/host/xhci-pci.c @@ -9,7 +9,7 @@ #include <dm.h> #include <pci.h> #include <usb.h> -#include "xhci.h" +#include <usb/xhci.h> static void xhci_pci_init(struct udevice *dev, struct xhci_hccr **ret_hccr, struct xhci_hcor **ret_hcor) diff --git a/drivers/usb/host/xhci-rcar.c b/drivers/usb/host/xhci-rcar.c index f2e91ef..c4d8811 100644 --- a/drivers/usb/host/xhci-rcar.c +++ b/drivers/usb/host/xhci-rcar.c @@ -12,7 +12,7 @@ #include <usb.h> #include <wait_bit.h> -#include "xhci.h" +#include <usb/xhci.h> #include "xhci-rcar-r8a779x_usb3_v3.h" /* Register Offset */ diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c index b2cfd94..119b418 100644 --- a/drivers/usb/host/xhci-ring.c +++ b/drivers/usb/host/xhci-ring.c @@ -19,7 +19,7 @@ #include <asm/unaligned.h> #include <linux/errno.h> -#include "xhci.h" +#include <usb/xhci.h> /** * Is this TRB a link TRB or was the last TRB the last TRB in this event ring diff --git a/drivers/usb/host/xhci-rockchip.c b/drivers/usb/host/xhci-rockchip.c index e7b0dbc..b67722f 100644 --- a/drivers/usb/host/xhci-rockchip.c +++ b/drivers/usb/host/xhci-rockchip.c @@ -13,7 +13,7 @@ #include <linux/usb/dwc3.h> #include <power/regulator.h> -#include "xhci.h" +#include <usb/xhci.h> struct rockchip_xhci_platdata { fdt_addr_t hcd_base; diff --git a/drivers/usb/host/xhci-zynqmp.c b/drivers/usb/host/xhci-zynqmp.c deleted file mode 100644 index e44e1ae..0000000 --- a/drivers/usb/host/xhci-zynqmp.c +++ /dev/null @@ -1,146 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2015 Xilinx, Inc. - * - * Zynq USB HOST xHCI Controller - * - * Author: Siva Durga Prasad Paladugu<sivadur@xilinx.com> - * - * This file was reused from Freescale USB xHCI - */ - -#include <common.h> -#include <dm.h> -#include <usb.h> -#include <linux/errno.h> -#include <asm/arch/hardware.h> -#include <linux/compat.h> -#include <linux/usb/dwc3.h> -#include "xhci.h" - -/* Declare global data pointer */ -/* Default to the ZYNQMP XHCI defines */ -#define USB3_PWRCTL_CLK_CMD_MASK 0x3FE000 -#define USB3_PWRCTL_CLK_FREQ_MASK 0xFFC -#define USB3_PHY_PARTIAL_RX_POWERON BIT(6) -#define USB3_PHY_RX_POWERON BIT(14) -#define USB3_PHY_TX_POWERON BIT(15) -#define USB3_PHY_TX_RX_POWERON (USB3_PHY_RX_POWERON | USB3_PHY_TX_POWERON) -#define USB3_PWRCTL_CLK_CMD_SHIFT 14 -#define USB3_PWRCTL_CLK_FREQ_SHIFT 22 - -/* USBOTGSS_WRAPPER definitions */ -#define USBOTGSS_WRAPRESET BIT(17) -#define USBOTGSS_DMADISABLE BIT(16) -#define USBOTGSS_STANDBYMODE_NO_STANDBY BIT(4) -#define USBOTGSS_STANDBYMODE_SMRT BIT(5) -#define USBOTGSS_STANDBYMODE_SMRT_WKUP (0x3 << 4) -#define USBOTGSS_IDLEMODE_NOIDLE BIT(2) -#define USBOTGSS_IDLEMODE_SMRT BIT(3) -#define USBOTGSS_IDLEMODE_SMRT_WKUP (0x3 << 2) - -/* USBOTGSS_IRQENABLE_SET_0 bit */ -#define USBOTGSS_COREIRQ_EN BIT(1) - -/* USBOTGSS_IRQENABLE_SET_1 bits */ -#define USBOTGSS_IRQ_SET_1_IDPULLUP_FALL_EN BIT(1) -#define USBOTGSS_IRQ_SET_1_DISCHRGVBUS_FALL_EN BIT(3) -#define USBOTGSS_IRQ_SET_1_CHRGVBUS_FALL_EN BIT(4) -#define USBOTGSS_IRQ_SET_1_DRVVBUS_FALL_EN BIT(5) -#define USBOTGSS_IRQ_SET_1_IDPULLUP_RISE_EN BIT(8) -#define USBOTGSS_IRQ_SET_1_DISCHRGVBUS_RISE_EN BIT(11) -#define USBOTGSS_IRQ_SET_1_CHRGVBUS_RISE_EN BIT(12) -#define USBOTGSS_IRQ_SET_1_DRVVBUS_RISE_EN BIT(13) -#define USBOTGSS_IRQ_SET_1_OEVT_EN BIT(16) -#define USBOTGSS_IRQ_SET_1_DMADISABLECLR_EN BIT(17) - -struct zynqmp_xhci { - struct usb_platdata usb_plat; - struct xhci_ctrl ctrl; - struct xhci_hccr *hcd; - struct dwc3 *dwc3_reg; -}; - -struct zynqmp_xhci_platdata { - fdt_addr_t hcd_base; -}; - -static int zynqmp_xhci_core_init(struct zynqmp_xhci *zynqmp_xhci) -{ - int ret = 0; - - ret = dwc3_core_init(zynqmp_xhci->dwc3_reg); - if (ret) { - debug("%s:failed to initialize core\n", __func__); - return ret; - } - - /* We are hard-coding DWC3 core to Host Mode */ - dwc3_set_mode(zynqmp_xhci->dwc3_reg, DWC3_GCTL_PRTCAP_HOST); - - return ret; -} - -void xhci_hcd_stop(int index) -{ - /* - * Currently zynqmp socs do not support PHY shutdown from - * sw. But this support may be added in future socs. - */ - - return; -} - -static int xhci_usb_probe(struct udevice *dev) -{ - struct zynqmp_xhci_platdata *plat = dev_get_platdata(dev); - struct zynqmp_xhci *ctx = dev_get_priv(dev); - struct xhci_hcor *hcor; - int ret; - - ctx->hcd = (struct xhci_hccr *)plat->hcd_base; - ctx->dwc3_reg = (struct dwc3 *)((char *)(ctx->hcd) + DWC3_REG_OFFSET); - - ret = zynqmp_xhci_core_init(ctx); - if (ret) { - puts("XHCI: failed to initialize controller\n"); - return -EINVAL; - } - - hcor = (struct xhci_hcor *)((ulong)ctx->hcd + - HC_LENGTH(xhci_readl(&ctx->hcd->cr_capbase))); - - return xhci_register(dev, ctx->hcd, hcor); -} - -static int xhci_usb_remove(struct udevice *dev) -{ - return xhci_deregister(dev); -} - -static int xhci_usb_ofdata_to_platdata(struct udevice *dev) -{ - struct zynqmp_xhci_platdata *plat = dev_get_platdata(dev); - const void *blob = gd->fdt_blob; - - /* Get the base address for XHCI controller from the device node */ - plat->hcd_base = fdtdec_get_addr(blob, dev_of_offset(dev), "reg"); - if (plat->hcd_base == FDT_ADDR_T_NONE) { - debug("Can't get the XHCI register base address\n"); - return -ENXIO; - } - - return 0; -} - -U_BOOT_DRIVER(dwc3_generic_host) = { - .name = "dwc3-generic-host", - .id = UCLASS_USB, - .ofdata_to_platdata = xhci_usb_ofdata_to_platdata, - .probe = xhci_usb_probe, - .remove = xhci_usb_remove, - .ops = &xhci_usb_ops, - .platdata_auto_alloc_size = sizeof(struct zynqmp_xhci_platdata), - .priv_auto_alloc_size = sizeof(struct zynqmp_xhci), - .flags = DM_FLAG_ALLOC_PRIV_DMA, -}; diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c index b3e4dcd..abd23e2 100644 --- a/drivers/usb/host/xhci.c +++ b/drivers/usb/host/xhci.c @@ -28,7 +28,7 @@ #include <asm/cache.h> #include <asm/unaligned.h> #include <linux/errno.h> -#include "xhci.h" +#include <usb/xhci.h> #ifndef CONFIG_USB_MAX_CONTROLLER_COUNT #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 diff --git a/drivers/usb/phy/omap_usb_phy.c b/drivers/usb/phy/omap_usb_phy.c index 32e5bbb..897e6f1 100644 --- a/drivers/usb/phy/omap_usb_phy.c +++ b/drivers/usb/phy/omap_usb_phy.c @@ -19,7 +19,7 @@ #include <linux/usb/dwc3.h> #include <linux/usb/xhci-omap.h> -#include "../host/xhci.h" +#include <usb/xhci.h> #ifdef CONFIG_OMAP_USB3PHY1_HOST struct usb3_dpll_params { diff --git a/include/configs/aristainetos-common.h b/include/configs/aristainetos-common.h index e998d9b..b451c7e 100644 --- a/include/configs/aristainetos-common.h +++ b/include/configs/aristainetos-common.h @@ -30,7 +30,6 @@ #define CONFIG_ETHPRIME "FEC" #define CONFIG_FEC_MXC_PHYADDR 0 -#define CONFIG_SPI_FLASH_MTD #define CONFIG_SYS_SPI_ST_ENABLE_WP_PIN #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/bmips_bcm3380.h b/include/configs/bmips_bcm3380.h index e2f9e76..573ff3e 100644 --- a/include/configs/bmips_bcm3380.h +++ b/include/configs/bmips_bcm3380.h @@ -6,6 +6,8 @@ #ifndef __CONFIG_BMIPS_BCM3380_H #define __CONFIG_BMIPS_BCM3380_H +#include <linux/sizes.h> + /* CPU */ #define CONFIG_SYS_MIPS_TIMER_FREQ 166500000 @@ -13,11 +15,11 @@ #define CONFIG_SYS_SDRAM_BASE 0x80000000 /* U-Boot */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + 0x100000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_1M #if defined(CONFIG_BMIPS_BOOT_RAM) #define CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_SYS_INIT_SP_OFFSET 0x2000 +#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K #endif #endif /* __CONFIG_BMIPS_BCM3380_H */ diff --git a/include/configs/bmips_bcm6318.h b/include/configs/bmips_bcm6318.h index 476aa51..c7e7119 100644 --- a/include/configs/bmips_bcm6318.h +++ b/include/configs/bmips_bcm6318.h @@ -6,6 +6,8 @@ #ifndef __CONFIG_BMIPS_BCM6318_H #define __CONFIG_BMIPS_BCM6318_H +#include <linux/sizes.h> + /* CPU */ #define CONFIG_SYS_MIPS_TIMER_FREQ 166500000 @@ -20,11 +22,11 @@ #define CONFIG_USB_OHCI_NEW /* U-Boot */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + 0x100000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_1M #if defined(CONFIG_BMIPS_BOOT_RAM) #define CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_SYS_INIT_SP_OFFSET 0x2000 +#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K #endif #endif /* __CONFIG_BMIPS_BCM6318_H */ diff --git a/include/configs/bmips_bcm63268.h b/include/configs/bmips_bcm63268.h index 1456b0e..45f26bb 100644 --- a/include/configs/bmips_bcm63268.h +++ b/include/configs/bmips_bcm63268.h @@ -6,6 +6,8 @@ #ifndef __CONFIG_BMIPS_BCM63268_H #define __CONFIG_BMIPS_BCM63268_H +#include <linux/sizes.h> + /* CPU */ #define CONFIG_SYS_MIPS_TIMER_FREQ 200000000 @@ -20,11 +22,11 @@ #define CONFIG_USB_OHCI_NEW /* U-Boot */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + 0x100000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_1M #if defined(CONFIG_BMIPS_BOOT_RAM) #define CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_SYS_INIT_SP_OFFSET 0x2000 +#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K #endif #endif /* __CONFIG_BMIPS_BCM63268_H */ diff --git a/include/configs/bmips_bcm6328.h b/include/configs/bmips_bcm6328.h index faf9abc..8d59438 100644 --- a/include/configs/bmips_bcm6328.h +++ b/include/configs/bmips_bcm6328.h @@ -6,6 +6,8 @@ #ifndef __CONFIG_BMIPS_BCM6328_H #define __CONFIG_BMIPS_BCM6328_H +#include <linux/sizes.h> + /* CPU */ #define CONFIG_SYS_MIPS_TIMER_FREQ 160000000 @@ -20,11 +22,11 @@ #define CONFIG_USB_OHCI_NEW /* U-Boot */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + 0x100000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_1M #if defined(CONFIG_BMIPS_BOOT_RAM) #define CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_SYS_INIT_SP_OFFSET 0x2000 +#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K #endif #endif /* __CONFIG_BMIPS_BCM6328_H */ diff --git a/include/configs/bmips_bcm6338.h b/include/configs/bmips_bcm6338.h index 83050c9..38dd9e3 100644 --- a/include/configs/bmips_bcm6338.h +++ b/include/configs/bmips_bcm6338.h @@ -6,6 +6,8 @@ #ifndef __CONFIG_BMIPS_BCM6338_H #define __CONFIG_BMIPS_BCM6338_H +#include <linux/sizes.h> + /* CPU */ #define CONFIG_SYS_MIPS_TIMER_FREQ 120000000 @@ -13,11 +15,11 @@ #define CONFIG_SYS_SDRAM_BASE 0x80000000 /* U-Boot */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + 0x100000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_1M #if defined(CONFIG_BMIPS_BOOT_RAM) #define CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_SYS_INIT_SP_OFFSET 0x2000 +#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K #endif #define CONFIG_SYS_FLASH_BASE 0xbfc00000 diff --git a/include/configs/bmips_bcm6348.h b/include/configs/bmips_bcm6348.h index 5eb8b0f..061d6b2 100644 --- a/include/configs/bmips_bcm6348.h +++ b/include/configs/bmips_bcm6348.h @@ -6,6 +6,8 @@ #ifndef __CONFIG_BMIPS_BCM6348_H #define __CONFIG_BMIPS_BCM6348_H +#include <linux/sizes.h> + /* CPU */ #define CONFIG_SYS_MIPS_TIMER_FREQ 128000000 @@ -18,11 +20,11 @@ #define CONFIG_USB_OHCI_NEW /* U-Boot */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + 0x100000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_1M #if defined(CONFIG_BMIPS_BOOT_RAM) #define CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_SYS_INIT_SP_OFFSET 0x2000 +#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K #endif #define CONFIG_SYS_FLASH_BASE 0xbfc00000 diff --git a/include/configs/bmips_bcm6358.h b/include/configs/bmips_bcm6358.h index 7becf3f..583217d 100644 --- a/include/configs/bmips_bcm6358.h +++ b/include/configs/bmips_bcm6358.h @@ -6,6 +6,8 @@ #ifndef __CONFIG_BMIPS_BCM6358_H #define __CONFIG_BMIPS_BCM6358_H +#include <linux/sizes.h> + /* CPU */ #define CONFIG_SYS_MIPS_TIMER_FREQ 150000000 @@ -20,11 +22,11 @@ #define CONFIG_USB_OHCI_NEW /* U-Boot */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + 0x100000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_1M #if defined(CONFIG_BMIPS_BOOT_RAM) #define CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_SYS_INIT_SP_OFFSET 0x2000 +#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K #endif #define CONFIG_SYS_FLASH_BASE 0xbe000000 diff --git a/include/configs/bmips_bcm6362.h b/include/configs/bmips_bcm6362.h index 6077720..570bc3b 100644 --- a/include/configs/bmips_bcm6362.h +++ b/include/configs/bmips_bcm6362.h @@ -1,11 +1,13 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright (C) 2018 Ãlvaro Fernández Rojas <noltari@gmail.com> + * Copyright (C) 2018 Álvaro Fernández Rojas <noltari@gmail.com> */ #ifndef __CONFIG_BMIPS_BCM6362_H #define __CONFIG_BMIPS_BCM6362_H +#include <linux/sizes.h> + /* CPU */ #define CONFIG_SYS_MIPS_TIMER_FREQ 200000000 @@ -20,11 +22,11 @@ #define CONFIG_USB_OHCI_NEW /* U-Boot */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + 0x100000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_1M #if defined(CONFIG_BMIPS_BOOT_RAM) #define CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_SYS_INIT_SP_OFFSET 0x2000 +#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K #endif #endif /* __CONFIG_BMIPS_BCM6362_H */ diff --git a/include/configs/bmips_bcm6368.h b/include/configs/bmips_bcm6368.h index 1a57476..ab5bdac 100644 --- a/include/configs/bmips_bcm6368.h +++ b/include/configs/bmips_bcm6368.h @@ -6,6 +6,8 @@ #ifndef __CONFIG_BMIPS_BCM6368_H #define __CONFIG_BMIPS_BCM6368_H +#include <linux/sizes.h> + /* CPU */ #define CONFIG_SYS_MIPS_TIMER_FREQ 200000000 @@ -20,11 +22,11 @@ #define CONFIG_USB_OHCI_NEW /* U-Boot */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + 0x100000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_1M #if defined(CONFIG_BMIPS_BOOT_RAM) #define CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_SYS_INIT_SP_OFFSET 0x2000 +#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K #endif #define CONFIG_SYS_FLASH_BASE 0xb8000000 diff --git a/include/configs/bmips_bcm6838.h b/include/configs/bmips_bcm6838.h index d735c51..f1ff054 100644 --- a/include/configs/bmips_bcm6838.h +++ b/include/configs/bmips_bcm6838.h @@ -6,6 +6,8 @@ #ifndef __CONFIG_BMIPS_BCM6838_H #define __CONFIG_BMIPS_BCM6838_H +#include <linux/sizes.h> + /* CPU */ #define CONFIG_SYS_MIPS_TIMER_FREQ 160000000 @@ -13,11 +15,11 @@ #define CONFIG_SYS_SDRAM_BASE 0x80000000 /* U-Boot */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + 0x100000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_1M #if defined(CONFIG_BMIPS_BOOT_RAM) #define CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_SYS_INIT_SP_OFFSET 0x2000 +#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K #endif #endif /* __CONFIG_BMIPS_BCM6838_H */ diff --git a/include/configs/bmips_common.h b/include/configs/bmips_common.h index 788f4af..3cb2d40 100644 --- a/include/configs/bmips_common.h +++ b/include/configs/bmips_common.h @@ -6,6 +6,8 @@ #ifndef __CONFIG_BMIPS_COMMON_H #define __CONFIG_BMIPS_COMMON_H +#include <linux/sizes.h> + /* ETH */ #define CONFIG_PHY_RESET_DELAY 20 #define CONFIG_SYS_RX_ETH_BUFFER 6 @@ -14,15 +16,11 @@ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ 230400, 500000, 1500000 } -/* RAM */ -#define CONFIG_SYS_MEMTEST_START 0xa0000000 -#define CONFIG_SYS_MEMTEST_END 0xa2000000 - /* Memory usage */ #define CONFIG_SYS_MAXARGS 24 -#define CONFIG_SYS_MALLOC_LEN (2 * 1024 * 1024) -#define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024) -#define CONFIG_SYS_CBSIZE 512 +#define CONFIG_SYS_MALLOC_LEN SZ_2M +#define CONFIG_SYS_BOOTPARAMS_LEN SZ_128K +#define CONFIG_SYS_CBSIZE SZ_512 /* U-Boot */ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE diff --git a/include/configs/broadcom_bcm968380gerg.h b/include/configs/broadcom_bcm968380gerg.h index aa6ce67..b0e9337 100644 --- a/include/configs/broadcom_bcm968380gerg.h +++ b/include/configs/broadcom_bcm968380gerg.h @@ -6,7 +6,7 @@ #include <configs/bmips_common.h> #include <configs/bmips_bcm6838.h> -#define CONFIG_ENV_SIZE (8 * 1024) +#define CONFIG_ENV_SIZE SZ_8K #ifdef CONFIG_NAND #define CONFIG_SYS_MAX_NAND_DEVICE 1 diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h index b957e9c..c1a6625 100644 --- a/include/configs/cm_fx6.h +++ b/include/configs/cm_fx6.h @@ -38,13 +38,6 @@ #define CONFIG_MXC_UART_BASE UART4_BASE #define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200} -/* SPI flash */ - -/* MTD support */ -#ifndef CONFIG_SPL_BUILD -#define CONFIG_SPI_FLASH_MTD -#endif - /* Environment */ #define CONFIG_ENV_SECT_SIZE (64 * 1024) #define CONFIG_ENV_SIZE (8 * 1024) diff --git a/include/configs/comtrend_ar5315u.h b/include/configs/comtrend_ar5315u.h index a5eb3ae..1da96c1 100644 --- a/include/configs/comtrend_ar5315u.h +++ b/include/configs/comtrend_ar5315u.h @@ -8,5 +8,4 @@ #define CONFIG_REMAKE_ELF -#define CONFIG_ENV_SIZE (8 * 1024) - +#define CONFIG_ENV_SIZE SZ_8K diff --git a/include/configs/comtrend_ar5387un.h b/include/configs/comtrend_ar5387un.h index 71c5ba4..73e6a5d 100644 --- a/include/configs/comtrend_ar5387un.h +++ b/include/configs/comtrend_ar5387un.h @@ -8,5 +8,4 @@ #define CONFIG_REMAKE_ELF -#define CONFIG_ENV_SIZE (8 * 1024) - +#define CONFIG_ENV_SIZE SZ_8K diff --git a/include/configs/comtrend_ct5361.h b/include/configs/comtrend_ct5361.h index da70592..72f9ecb 100644 --- a/include/configs/comtrend_ct5361.h +++ b/include/configs/comtrend_ct5361.h @@ -8,5 +8,4 @@ #define CONFIG_REMAKE_ELF -#define CONFIG_ENV_SIZE (8 * 1024) - +#define CONFIG_ENV_SIZE SZ_8K diff --git a/include/configs/comtrend_vr3032u.h b/include/configs/comtrend_vr3032u.h index e183288..cb88805 100644 --- a/include/configs/comtrend_vr3032u.h +++ b/include/configs/comtrend_vr3032u.h @@ -8,5 +8,10 @@ #define CONFIG_REMAKE_ELF -#define CONFIG_ENV_SIZE (8 * 1024) +#define CONFIG_ENV_SIZE SZ_8K +#ifdef CONFIG_NAND +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_SELF_INIT +#define CONFIG_SYS_NAND_ONFI_DETECTION +#endif /* CONFIG_NAND */ diff --git a/include/configs/comtrend_wap5813n.h b/include/configs/comtrend_wap5813n.h index 7070a1c..b67f654 100644 --- a/include/configs/comtrend_wap5813n.h +++ b/include/configs/comtrend_wap5813n.h @@ -8,5 +8,4 @@ #define CONFIG_REMAKE_ELF -#define CONFIG_ENV_SIZE (8 * 1024) - +#define CONFIG_ENV_SIZE SZ_8K diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h index 41f0813..6876134 100644 --- a/include/configs/da850evm.h +++ b/include/configs/da850evm.h @@ -190,16 +190,11 @@ #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SZ #endif -#ifdef CONFIG_USE_SPIFLASH -#ifdef CONFIG_ENV_IS_IN_SPI_FLASH +#if defined(CONFIG_USE_SPIFLASH) && defined(CONFIG_ENV_IS_IN_SPI_FLASH) #define CONFIG_ENV_SIZE (64 << 10) #define CONFIG_ENV_OFFSET (512 << 10) #define CONFIG_ENV_SECT_SIZE (64 << 10) #endif -#ifdef CONFIG_SPL_BUILD -#undef CONFIG_SPI_FLASH_MTD -#endif -#endif /* * U-Boot general configuration diff --git a/include/configs/dh_imx6.h b/include/configs/dh_imx6.h index a854d0b..86c1192 100644 --- a/include/configs/dh_imx6.h +++ b/include/configs/dh_imx6.h @@ -59,7 +59,6 @@ #if defined(CONFIG_SPL_BUILD) #undef CONFIG_DM_SPI #undef CONFIG_DM_SPI_FLASH -#undef CONFIG_SPI_FLASH_MTD #endif /* UART */ diff --git a/include/configs/display5.h b/include/configs/display5.h index d806415..65dae1f 100644 --- a/include/configs/display5.h +++ b/include/configs/display5.h @@ -39,7 +39,6 @@ #if defined(CONFIG_SPL_BUILD) #undef CONFIG_DM_SPI #undef CONFIG_DM_SPI_FLASH -#undef CONFIG_SPI_FLASH_MTD #endif /* Below values are "dummy" - only to avoid build break */ diff --git a/include/configs/gardena-smart-gateway-mt7688.h b/include/configs/gardena-smart-gateway-mt7688.h index b3b89d2..e83a96a 100644 --- a/include/configs/gardena-smart-gateway-mt7688.h +++ b/include/configs/gardena-smart-gateway-mt7688.h @@ -22,7 +22,7 @@ /* UART */ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ - 230400, 500000, 1500000 } + 230400, 460800, 921600 } /* RAM */ #define CONFIG_SYS_MEMTEST_START 0x80100000 diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h index a27627e..e543061 100644 --- a/include/configs/gw_ventana.h +++ b/include/configs/gw_ventana.h @@ -47,15 +47,7 @@ #define CONFIG_MXC_UART #define CONFIG_MXC_UART_BASE UART2_BASE -#ifdef CONFIG_SPI_FLASH - -/* SPI */ -#ifdef CONFIG_CMD_SF - #define CONFIG_SPI_FLASH_MTD - /* GPIO 3-19 (21248) */ -#endif - -#elif defined(CONFIG_SPL_NAND_SUPPORT) +#if !defined(CONFIG_SPI_FLASH) && defined(CONFIG_SPL_NAND_SUPPORT) /* Enable NAND support */ #ifdef CONFIG_CMD_NAND #define CONFIG_SYS_MAX_NAND_DEVICE 1 diff --git a/include/configs/huawei_hg556a.h b/include/configs/huawei_hg556a.h index 1c9bee6..2aa5c66 100644 --- a/include/configs/huawei_hg556a.h +++ b/include/configs/huawei_hg556a.h @@ -8,5 +8,4 @@ #define CONFIG_REMAKE_ELF -#define CONFIG_ENV_SIZE (8 * 1024) - +#define CONFIG_ENV_SIZE SZ_8K diff --git a/include/configs/j721e_evm.h b/include/configs/j721e_evm.h index dbe226b..639d87a 100644 --- a/include/configs/j721e_evm.h +++ b/include/configs/j721e_evm.h @@ -13,6 +13,7 @@ #include <config_distro_bootcmd.h> #include <environment/ti/mmc.h> #include <environment/ti/k3_rproc.h> +#include <environment/ti/ufs.h> #define CONFIG_ENV_SIZE (128 << 10) @@ -56,6 +57,9 @@ #define CONFIG_SYS_BOOTM_LEN SZ_64M #define CONFIG_CQSPI_REF_CLK 133333333 +/* HyperFlash related configuration */ +#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1 + /* U-Boot general configuration */ #define EXTRA_ENV_J721E_BOARD_SETTINGS \ "default_device_tree=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \ @@ -103,7 +107,8 @@ DEFAULT_MMC_TI_ARGS \ EXTRA_ENV_J721E_BOARD_SETTINGS \ EXTRA_ENV_J721E_BOARD_SETTINGS_MMC \ - EXTRA_ENV_RPROC_SETTINGS + EXTRA_ENV_RPROC_SETTINGS \ + DEFAULT_UFS_TI_ARGS /* Now for the remaining common defines */ #include <configs/ti_armv7_common.h> diff --git a/include/configs/linkit-smart-7688.h b/include/configs/linkit-smart-7688.h index 2adf385..4d30d98 100644 --- a/include/configs/linkit-smart-7688.h +++ b/include/configs/linkit-smart-7688.h @@ -22,7 +22,7 @@ /* UART */ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ - 230400, 500000, 1500000 } + 230400, 460800, 921600 } /* RAM */ #define CONFIG_SYS_MEMTEST_START 0x80100000 diff --git a/include/configs/ls1012afrwy.h b/include/configs/ls1012afrwy.h index 77aa22b..1b0f156 100644 --- a/include/configs/ls1012afrwy.h +++ b/include/configs/ls1012afrwy.h @@ -23,6 +23,11 @@ #define CONFIG_SYS_MEMTEST_START 0x80000000 #define CONFIG_SYS_MEMTEST_END 0x9fffffff +/* ENV */ +#define CONFIG_SYS_FSL_QSPI_BASE 0x40000000 +#define CONFIG_ENV_ADDR (CONFIG_SYS_FSL_QSPI_BASE + \ + CONFIG_ENV_OFFSET) + #ifndef CONFIG_SPL_BUILD #undef BOOT_TARGET_DEVICES #define BOOT_TARGET_DEVICES(func) \ diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h index f6640fa..a5e2740 100644 --- a/include/configs/ls1012ardb.h +++ b/include/configs/ls1012ardb.h @@ -17,6 +17,10 @@ #define CONFIG_SYS_MEMTEST_END 0x9fffffff +/* ENV */ +#define CONFIG_SYS_FSL_QSPI_BASE 0x40000000 +#define CONFIG_ENV_ADDR (CONFIG_SYS_FSL_QSPI_BASE + \ + CONFIG_ENV_OFFSET) /* * I2C IO expander */ diff --git a/include/configs/netgear_cg3100d.h b/include/configs/netgear_cg3100d.h index d541e9c..e5a9601 100644 --- a/include/configs/netgear_cg3100d.h +++ b/include/configs/netgear_cg3100d.h @@ -6,5 +6,4 @@ #include <configs/bmips_common.h> #include <configs/bmips_bcm3380.h> -#define CONFIG_ENV_SIZE (8 * 1024) - +#define CONFIG_ENV_SIZE SZ_8K diff --git a/include/configs/netgear_dgnd3700v2.h b/include/configs/netgear_dgnd3700v2.h index 9edaec9..3baa17a 100644 --- a/include/configs/netgear_dgnd3700v2.h +++ b/include/configs/netgear_dgnd3700v2.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright (C) 2018 Ãlvaro Fernández Rojas <noltari@gmail.com> + * Copyright (C) 2018 Álvaro Fernández Rojas <noltari@gmail.com> */ #include <configs/bmips_common.h> @@ -8,5 +8,4 @@ #define CONFIG_REMAKE_ELF -#define CONFIG_ENV_SIZE (8 * 1024) - +#define CONFIG_ENV_SIZE SZ_8K diff --git a/include/configs/rcar-gen2-common.h b/include/configs/rcar-gen2-common.h index 71a5909..e940a8b 100644 --- a/include/configs/rcar-gen2-common.h +++ b/include/configs/rcar-gen2-common.h @@ -46,11 +46,9 @@ #define CONFIG_ENV_SIZE_REDUND (CONFIG_SYS_MONITOR_LEN) /* SF MTD */ -#if defined(CONFIG_SPI_FLASH_MTD) && !defined(CONFIG_SPL_BUILD) -#else +#ifdef CONFIG_SPL_BUILD #undef CONFIG_DM_SPI #undef CONFIG_DM_SPI_FLASH -#undef CONFIG_SPI_FLASH_MTD #endif /* Timer */ diff --git a/include/configs/sagem_f@st1704.h b/include/configs/sagem_f@st1704.h index 7171dc6..5a526d9 100644 --- a/include/configs/sagem_f@st1704.h +++ b/include/configs/sagem_f@st1704.h @@ -6,5 +6,4 @@ #include <configs/bmips_common.h> #include <configs/bmips_bcm6338.h> -#define CONFIG_ENV_SIZE (8 * 1024) - +#define CONFIG_ENV_SIZE SZ_8K diff --git a/include/configs/sfr_nb4_ser.h b/include/configs/sfr_nb4_ser.h index 1c9bee6..2aa5c66 100644 --- a/include/configs/sfr_nb4_ser.h +++ b/include/configs/sfr_nb4_ser.h @@ -8,5 +8,4 @@ #define CONFIG_REMAKE_ELF -#define CONFIG_ENV_SIZE (8 * 1024) - +#define CONFIG_ENV_SIZE SZ_8K diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 94268ed..baa2143 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -132,10 +132,6 @@ /* * QSPI support */ -/* Enable multiple SPI NOR flash manufacturers */ -#ifndef CONFIG_SPL_BUILD -#define CONFIG_SPI_FLASH_MTD -#endif /* QSPI reference clock */ #ifndef __ASSEMBLY__ unsigned int cm_get_qspi_controller_clk_hz(void); diff --git a/include/configs/stm32f746-disco.h b/include/configs/stm32f746-disco.h index a24127d..cc26f83 100644 --- a/include/configs/stm32f746-disco.h +++ b/include/configs/stm32f746-disco.h @@ -55,7 +55,7 @@ "pxefile_addr_r=0xC0008000\0" \ "fdt_high=0xffffffffffffffff\0" \ "initrd_high=0xffffffffffffffff\0" \ - "ramdisk_addr_r=0xD0900000\0" \ + "ramdisk_addr_r=0xC0600000\0" \ BOOTENV /* diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index b6c9f2c..274cc19 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -227,8 +227,6 @@ /* Boot FreeBSD/vxWorks from an ELF image */ #define CONFIG_SYS_MMC_MAX_DEVICE 1 -#undef CONFIG_BOOTM_NETBSD - /* MMC support */ #ifdef CONFIG_MMC_SDHCI_ZYNQ #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h index f7f3237..0c563d8 100644 --- a/include/dm/uclass-id.h +++ b/include/dm/uclass-id.h @@ -102,6 +102,7 @@ enum uclass_id { UCLASS_THERMAL, /* Thermal sensor */ UCLASS_TIMER, /* Timer device */ UCLASS_TPM, /* Trusted Platform Module TIS interface */ + UCLASS_UFS, /* Universal Flash Storage */ UCLASS_USB, /* USB bus */ UCLASS_USB_DEV_GENERIC, /* USB generic device */ UCLASS_USB_HUB, /* USB hub */ diff --git a/include/dt-bindings/clock/bcm6362-clock.h b/include/dt-bindings/clock/bcm6362-clock.h index fed04e6..d3770c5 100644 --- a/include/dt-bindings/clock/bcm6362-clock.h +++ b/include/dt-bindings/clock/bcm6362-clock.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright (C) 2018 Ãlvaro Fernández Rojas <noltari@gmail.com> + * Copyright (C) 2018 Álvaro Fernández Rojas <noltari@gmail.com> * * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h */ diff --git a/include/dt-bindings/clock/mt7628-clk.h b/include/dt-bindings/clock/mt7628-clk.h new file mode 100644 index 0000000..b5866fd --- /dev/null +++ b/include/dt-bindings/clock/mt7628-clk.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2019 MediaTek Inc. + * + * Author: Weijie Gao <weijie.gao@mediatek.com> + */ + +#ifndef _DT_BINDINGS_MT7628_CLK_H_ +#define _DT_BINDINGS_MT7628_CLK_H_ + +/* Base clocks */ +#define CLK_SYS 34 +#define CLK_CPU 33 +#define CLK_XTAL 32 + +/* Peripheral clocks */ +#define CLK_PWM 31 +#define CLK_SDXC 30 +#define CLK_CRYPTO 29 +#define CLK_MIPS_CNT 28 +#define CLK_PCIE 26 +#define CLK_UPHY 25 +#define CLK_ETH 23 +#define CLK_UART2 20 +#define CLK_UART1 19 +#define CLK_SPI 18 +#define CLK_I2S 17 +#define CLK_I2C 16 +#define CLK_GDMA 14 +#define CLK_PIO 13 +#define CLK_UART0 12 +#define CLK_PCM 11 +#define CLK_MC 10 +#define CLK_INTC 9 +#define CLK_TIMER 8 + +#endif /* _DT_BINDINGS_MT7628_CLK_H_ */ diff --git a/include/dt-bindings/clock/xlnx-zynqmp-clk.h b/include/dt-bindings/clock/xlnx-zynqmp-clk.h new file mode 100644 index 0000000..cdc4c0b --- /dev/null +++ b/include/dt-bindings/clock/xlnx-zynqmp-clk.h @@ -0,0 +1,126 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Xilinx Zynq MPSoC Firmware layer + * + * Copyright (C) 2014-2018 Xilinx, Inc. + * + */ + +#ifndef _DT_BINDINGS_CLK_ZYNQMP_H +#define _DT_BINDINGS_CLK_ZYNQMP_H + +#define IOPLL 0 +#define RPLL 1 +#define APLL 2 +#define DPLL 3 +#define VPLL 4 +#define IOPLL_TO_FPD 5 +#define RPLL_TO_FPD 6 +#define APLL_TO_LPD 7 +#define DPLL_TO_LPD 8 +#define VPLL_TO_LPD 9 +#define ACPU 10 +#define ACPU_HALF 11 +#define DBF_FPD 12 +#define DBF_LPD 13 +#define DBG_TRACE 14 +#define DBG_TSTMP 15 +#define DP_VIDEO_REF 16 +#define DP_AUDIO_REF 17 +#define DP_STC_REF 18 +#define GDMA_REF 19 +#define DPDMA_REF 20 +#define DDR_REF 21 +#define SATA_REF 22 +#define PCIE_REF 23 +#define GPU_REF 24 +#define GPU_PP0_REF 25 +#define GPU_PP1_REF 26 +#define TOPSW_MAIN 27 +#define TOPSW_LSBUS 28 +#define GTGREF0_REF 29 +#define LPD_SWITCH 30 +#define LPD_LSBUS 31 +#define USB0_BUS_REF 32 +#define USB1_BUS_REF 33 +#define USB3_DUAL_REF 34 +#define USB0 35 +#define USB1 36 +#define CPU_R5 37 +#define CPU_R5_CORE 38 +#define CSU_SPB 39 +#define CSU_PLL 40 +#define PCAP 41 +#define IOU_SWITCH 42 +#define GEM_TSU_REF 43 +#define GEM_TSU 44 +#define GEM0_TX 45 +#define GEM1_TX 46 +#define GEM2_TX 47 +#define GEM3_TX 48 +#define GEM0_RX 49 +#define GEM1_RX 50 +#define GEM2_RX 51 +#define GEM3_RX 52 +#define QSPI_REF 53 +#define SDIO0_REF 54 +#define SDIO1_REF 55 +#define UART0_REF 56 +#define UART1_REF 57 +#define SPI0_REF 58 +#define SPI1_REF 59 +#define NAND_REF 60 +#define I2C0_REF 61 +#define I2C1_REF 62 +#define CAN0_REF 63 +#define CAN1_REF 64 +#define CAN0 65 +#define CAN1 66 +#define DLL_REF 67 +#define ADMA_REF 68 +#define TIMESTAMP_REF 69 +#define AMS_REF 70 +#define PL0_REF 71 +#define PL1_REF 72 +#define PL2_REF 73 +#define PL3_REF 74 +#define WDT 75 +#define IOPLL_INT 76 +#define IOPLL_PRE_SRC 77 +#define IOPLL_HALF 78 +#define IOPLL_INT_MUX 79 +#define IOPLL_POST_SRC 80 +#define RPLL_INT 81 +#define RPLL_PRE_SRC 82 +#define RPLL_HALF 83 +#define RPLL_INT_MUX 84 +#define RPLL_POST_SRC 85 +#define APLL_INT 86 +#define APLL_PRE_SRC 87 +#define APLL_HALF 88 +#define APLL_INT_MUX 89 +#define APLL_POST_SRC 90 +#define DPLL_INT 91 +#define DPLL_PRE_SRC 92 +#define DPLL_HALF 93 +#define DPLL_INT_MUX 94 +#define DPLL_POST_SRC 95 +#define VPLL_INT 96 +#define VPLL_PRE_SRC 97 +#define VPLL_HALF 98 +#define VPLL_INT_MUX 99 +#define VPLL_POST_SRC 100 +#define CAN0_MIO 101 +#define CAN1_MIO 102 +#define ACPU_FULL 103 +#define GEM0_REF 104 +#define GEM1_REF 105 +#define GEM2_REF 106 +#define GEM3_REF 107 +#define GEM0_REF_UNG 108 +#define GEM1_REF_UNG 109 +#define GEM2_REF_UNG 110 +#define GEM3_REF_UNG 111 +#define LPD_WDT 112 + +#endif diff --git a/include/dt-bindings/power-domain/bcm6362-power-domain.h b/include/dt-bindings/power-domain/bcm6362-power-domain.h index ddc123e..1a708a9 100644 --- a/include/dt-bindings/power-domain/bcm6362-power-domain.h +++ b/include/dt-bindings/power-domain/bcm6362-power-domain.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright (C) 2018 Ãlvaro Fernández Rojas <noltari@gmail.com> + * Copyright (C) 2018 Álvaro Fernández Rojas <noltari@gmail.com> */ #ifndef __DT_BINDINGS_POWER_DOMAIN_BCM6362_H diff --git a/include/dt-bindings/power/xlnx-zynqmp-power.h b/include/dt-bindings/power/xlnx-zynqmp-power.h new file mode 100644 index 0000000..0d9a412 --- /dev/null +++ b/include/dt-bindings/power/xlnx-zynqmp-power.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2018 Xilinx, Inc. + */ + +#ifndef _DT_BINDINGS_ZYNQMP_POWER_H +#define _DT_BINDINGS_ZYNQMP_POWER_H + +#define PD_USB_0 22 +#define PD_USB_1 23 +#define PD_TTC_0 24 +#define PD_TTC_1 25 +#define PD_TTC_2 26 +#define PD_TTC_3 27 +#define PD_SATA 28 +#define PD_ETH_0 29 +#define PD_ETH_1 30 +#define PD_ETH_2 31 +#define PD_ETH_3 32 +#define PD_UART_0 33 +#define PD_UART_1 34 +#define PD_SPI_0 35 +#define PD_SPI_1 36 +#define PD_I2C_0 37 +#define PD_I2C_1 38 +#define PD_SD_0 39 +#define PD_SD_1 40 +#define PD_DP 41 +#define PD_GDMA 42 +#define PD_ADMA 43 +#define PD_NAND 44 +#define PD_QSPI 45 +#define PD_GPIO 46 +#define PD_CAN_0 47 +#define PD_CAN_1 48 +#define PD_GPU 58 +#define PD_PCIE 59 + +#endif diff --git a/include/dt-bindings/reset/bcm6362-reset.h b/include/dt-bindings/reset/bcm6362-reset.h index 6e257ce..8202e49 100644 --- a/include/dt-bindings/reset/bcm6362-reset.h +++ b/include/dt-bindings/reset/bcm6362-reset.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright (C) 2018 Ãlvaro Fernández Rojas <noltari@gmail.com> + * Copyright (C) 2018 Álvaro Fernández Rojas <noltari@gmail.com> * * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h */ diff --git a/include/dt-bindings/reset/mt7628-reset.h b/include/dt-bindings/reset/mt7628-reset.h new file mode 100644 index 0000000..2a674c1 --- /dev/null +++ b/include/dt-bindings/reset/mt7628-reset.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2019 MediaTek Inc. + * + * Author: Weijie Gao <weijie.gao@mediatek.com> + */ + +#ifndef _DT_BINDINGS_MT7628_RESET_H_ +#define _DT_BINDINGS_MT7628_RESET_H_ + +#define MT7628_PWM_RST 31 +#define MT7628_SDXC_RST 30 +#define MT7628_CRYPTO_RST 29 +#define MT7628_AUX_STCK_RST 28 +#define MT7628_PCIE_RST 26 +#define MT7628_EPHY_RST 24 +#define MT7628_ETH_RST 23 +#define MT7628_UPHY_RST 22 +#define MT7628_UART2_RST 20 +#define MT7628_UART1_RST 19 +#define MT7628_SPI_RST 18 +#define MT7628_I2S_RST 17 +#define MT7628_I2C_RST 16 +#define MT7628_GDMA_RST 14 +#define MT7628_PIO_RST 13 +#define MT7628_UART0_RST 12 +#define MT7628_PCM_RST 11 +#define MT7628_MC_RST 10 +#define MT7628_INT_RST 9 +#define MT7628_TIMER_RST 8 +#define MT7628_HIF_RST 5 +#define MT7628_WIFI_RST 4 +#define MT7628_SPIS_RST 3 +#define MT7628_SYS_RST 0 + +#endif /* _DT_BINDINGS_MT7628_RESET_H_ */ diff --git a/include/dt-bindings/reset/xlnx-zynqmp-resets.h b/include/dt-bindings/reset/xlnx-zynqmp-resets.h new file mode 100644 index 0000000..d44525b --- /dev/null +++ b/include/dt-bindings/reset/xlnx-zynqmp-resets.h @@ -0,0 +1,130 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2018 Xilinx, Inc. + */ + +#ifndef _DT_BINDINGS_ZYNQMP_RESETS_H +#define _DT_BINDINGS_ZYNQMP_RESETS_H + +#define ZYNQMP_RESET_PCIE_CFG 0 +#define ZYNQMP_RESET_PCIE_BRIDGE 1 +#define ZYNQMP_RESET_PCIE_CTRL 2 +#define ZYNQMP_RESET_DP 3 +#define ZYNQMP_RESET_SWDT_CRF 4 +#define ZYNQMP_RESET_AFI_FM5 5 +#define ZYNQMP_RESET_AFI_FM4 6 +#define ZYNQMP_RESET_AFI_FM3 7 +#define ZYNQMP_RESET_AFI_FM2 8 +#define ZYNQMP_RESET_AFI_FM1 9 +#define ZYNQMP_RESET_AFI_FM0 10 +#define ZYNQMP_RESET_GDMA 11 +#define ZYNQMP_RESET_GPU_PP1 12 +#define ZYNQMP_RESET_GPU_PP0 13 +#define ZYNQMP_RESET_GPU 14 +#define ZYNQMP_RESET_GT 15 +#define ZYNQMP_RESET_SATA 16 +#define ZYNQMP_RESET_ACPU3_PWRON 17 +#define ZYNQMP_RESET_ACPU2_PWRON 18 +#define ZYNQMP_RESET_ACPU1_PWRON 19 +#define ZYNQMP_RESET_ACPU0_PWRON 20 +#define ZYNQMP_RESET_APU_L2 21 +#define ZYNQMP_RESET_ACPU3 22 +#define ZYNQMP_RESET_ACPU2 23 +#define ZYNQMP_RESET_ACPU1 24 +#define ZYNQMP_RESET_ACPU0 25 +#define ZYNQMP_RESET_DDR 26 +#define ZYNQMP_RESET_APM_FPD 27 +#define ZYNQMP_RESET_SOFT 28 +#define ZYNQMP_RESET_GEM0 29 +#define ZYNQMP_RESET_GEM1 30 +#define ZYNQMP_RESET_GEM2 31 +#define ZYNQMP_RESET_GEM3 32 +#define ZYNQMP_RESET_QSPI 33 +#define ZYNQMP_RESET_UART0 34 +#define ZYNQMP_RESET_UART1 35 +#define ZYNQMP_RESET_SPI0 36 +#define ZYNQMP_RESET_SPI1 37 +#define ZYNQMP_RESET_SDIO0 38 +#define ZYNQMP_RESET_SDIO1 39 +#define ZYNQMP_RESET_CAN0 40 +#define ZYNQMP_RESET_CAN1 41 +#define ZYNQMP_RESET_I2C0 42 +#define ZYNQMP_RESET_I2C1 43 +#define ZYNQMP_RESET_TTC0 44 +#define ZYNQMP_RESET_TTC1 45 +#define ZYNQMP_RESET_TTC2 46 +#define ZYNQMP_RESET_TTC3 47 +#define ZYNQMP_RESET_SWDT_CRL 48 +#define ZYNQMP_RESET_NAND 49 +#define ZYNQMP_RESET_ADMA 50 +#define ZYNQMP_RESET_GPIO 51 +#define ZYNQMP_RESET_IOU_CC 52 +#define ZYNQMP_RESET_TIMESTAMP 53 +#define ZYNQMP_RESET_RPU_R50 54 +#define ZYNQMP_RESET_RPU_R51 55 +#define ZYNQMP_RESET_RPU_AMBA 56 +#define ZYNQMP_RESET_OCM 57 +#define ZYNQMP_RESET_RPU_PGE 58 +#define ZYNQMP_RESET_USB0_CORERESET 59 +#define ZYNQMP_RESET_USB1_CORERESET 60 +#define ZYNQMP_RESET_USB0_HIBERRESET 61 +#define ZYNQMP_RESET_USB1_HIBERRESET 62 +#define ZYNQMP_RESET_USB0_APB 63 +#define ZYNQMP_RESET_USB1_APB 64 +#define ZYNQMP_RESET_IPI 65 +#define ZYNQMP_RESET_APM_LPD 66 +#define ZYNQMP_RESET_RTC 67 +#define ZYNQMP_RESET_SYSMON 68 +#define ZYNQMP_RESET_AFI_FM6 69 +#define ZYNQMP_RESET_LPD_SWDT 70 +#define ZYNQMP_RESET_FPD 71 +#define ZYNQMP_RESET_RPU_DBG1 72 +#define ZYNQMP_RESET_RPU_DBG0 73 +#define ZYNQMP_RESET_DBG_LPD 74 +#define ZYNQMP_RESET_DBG_FPD 75 +#define ZYNQMP_RESET_APLL 76 +#define ZYNQMP_RESET_DPLL 77 +#define ZYNQMP_RESET_VPLL 78 +#define ZYNQMP_RESET_IOPLL 79 +#define ZYNQMP_RESET_RPLL 80 +#define ZYNQMP_RESET_GPO3_PL_0 81 +#define ZYNQMP_RESET_GPO3_PL_1 82 +#define ZYNQMP_RESET_GPO3_PL_2 83 +#define ZYNQMP_RESET_GPO3_PL_3 84 +#define ZYNQMP_RESET_GPO3_PL_4 85 +#define ZYNQMP_RESET_GPO3_PL_5 86 +#define ZYNQMP_RESET_GPO3_PL_6 87 +#define ZYNQMP_RESET_GPO3_PL_7 88 +#define ZYNQMP_RESET_GPO3_PL_8 89 +#define ZYNQMP_RESET_GPO3_PL_9 90 +#define ZYNQMP_RESET_GPO3_PL_10 91 +#define ZYNQMP_RESET_GPO3_PL_11 92 +#define ZYNQMP_RESET_GPO3_PL_12 93 +#define ZYNQMP_RESET_GPO3_PL_13 94 +#define ZYNQMP_RESET_GPO3_PL_14 95 +#define ZYNQMP_RESET_GPO3_PL_15 96 +#define ZYNQMP_RESET_GPO3_PL_16 97 +#define ZYNQMP_RESET_GPO3_PL_17 98 +#define ZYNQMP_RESET_GPO3_PL_18 99 +#define ZYNQMP_RESET_GPO3_PL_19 100 +#define ZYNQMP_RESET_GPO3_PL_20 101 +#define ZYNQMP_RESET_GPO3_PL_21 102 +#define ZYNQMP_RESET_GPO3_PL_22 103 +#define ZYNQMP_RESET_GPO3_PL_23 104 +#define ZYNQMP_RESET_GPO3_PL_24 105 +#define ZYNQMP_RESET_GPO3_PL_25 106 +#define ZYNQMP_RESET_GPO3_PL_26 107 +#define ZYNQMP_RESET_GPO3_PL_27 108 +#define ZYNQMP_RESET_GPO3_PL_28 109 +#define ZYNQMP_RESET_GPO3_PL_29 110 +#define ZYNQMP_RESET_GPO3_PL_30 111 +#define ZYNQMP_RESET_GPO3_PL_31 112 +#define ZYNQMP_RESET_RPU_LS 113 +#define ZYNQMP_RESET_PS_ONLY 114 +#define ZYNQMP_RESET_PL 115 +#define ZYNQMP_RESET_PS_PL0 116 +#define ZYNQMP_RESET_PS_PL1 117 +#define ZYNQMP_RESET_PS_PL2 118 +#define ZYNQMP_RESET_PS_PL3 119 + +#endif diff --git a/include/environment/ti/ufs.h b/include/environment/ti/ufs.h new file mode 100644 index 0000000..d457e20 --- /dev/null +++ b/include/environment/ti/ufs.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com + * + * Environment variable definitions for UFS on TI boards. + */ + +#ifndef __TI_UFS_H +#define __TI_UFS_H + +#define DEFAULT_UFS_TI_ARGS \ + "scsirootfstype=ext4 rootwait\0" \ + "ufs_finduuid=part uuid scsi ${bootpart} uuid\0" \ + "args_ufs=setenv devtype scsi;setenv bootpart 1:1;" \ + "run ufs_finduuid;setenv bootargs console = ${console} " \ + "${optargs}" \ + "root=PARTUUID=${uuid} rw " \ + "rootfstype=${scsirootfstype};" \ + "setenv devtype scsi;" \ + "setenv bootpart 1:1\0" \ + "init_ufs=ufs init; scsi scan; run args_ufs\0" \ + "get_kern_ufs=load ${devtype} ${bootpart} ${loadaddr} ${bootdir}/${name_kern}\0" \ + "get_fdt_ufs=load ${devtype} ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \ + "get_overlay_ufs=" \ + "fdt address ${fdtaddr};" \ + "fdt resize 0x100000;" \ + "for overlay in $name_overlays;" \ + "do;" \ + "load scsi ${bootpart} ${overlayaddr} ${bootdir}/${overlay} && " \ + "fdt apply ${overlayaddr};" \ + "done;\0" + +#endif diff --git a/include/image.h b/include/image.h index c1065c0..f4d2aaf 100644 --- a/include/image.h +++ b/include/image.h @@ -319,13 +319,13 @@ enum { * all data in network byte order (aka natural aka bigendian). */ typedef struct image_header { - __be32 ih_magic; /* Image Header Magic Number */ - __be32 ih_hcrc; /* Image Header CRC Checksum */ - __be32 ih_time; /* Image Creation Timestamp */ - __be32 ih_size; /* Image Data Size */ - __be32 ih_load; /* Data Load Address */ - __be32 ih_ep; /* Entry Point Address */ - __be32 ih_dcrc; /* Image Data CRC Checksum */ + uint32_t ih_magic; /* Image Header Magic Number */ + uint32_t ih_hcrc; /* Image Header CRC Checksum */ + uint32_t ih_time; /* Image Creation Timestamp */ + uint32_t ih_size; /* Image Data Size */ + uint32_t ih_load; /* Data Load Address */ + uint32_t ih_ep; /* Entry Point Address */ + uint32_t ih_dcrc; /* Image Data CRC Checksum */ uint8_t ih_os; /* Operating System */ uint8_t ih_arch; /* CPU architecture */ uint8_t ih_type; /* Image Type */ diff --git a/include/linux/types.h b/include/linux/types.h index cc6f7cb..51cb284 100644 --- a/include/linux/types.h +++ b/include/linux/types.h @@ -151,12 +151,14 @@ typedef __u32 __bitwise __wsum; typedef unsigned __bitwise__ gfp_t; +#ifdef __linux__ struct ustat { __kernel_daddr_t f_tfree; __kernel_ino_t f_tinode; char f_fname[6]; char f_fpack[6]; }; +#endif #define DECLARE_BITMAP(name, bits) \ unsigned long name[BITS_TO_LONGS(bits)] diff --git a/include/scsi.h b/include/scsi.h index 81ab43c..61da958 100644 --- a/include/scsi.h +++ b/include/scsi.h @@ -6,6 +6,8 @@ #ifndef _SCSI_H #define _SCSI_H +#include <linux/dma-direction.h> + struct scsi_cmd { unsigned char cmd[16]; /* command */ /* for request sense */ @@ -26,6 +28,7 @@ struct scsi_cmd { unsigned long trans_bytes; /* tranfered bytes */ unsigned int priv; + enum dma_data_direction dma_dir; }; /*----------------------------------------------------------- @@ -163,11 +166,13 @@ struct scsi_cmd { * @base: Controller base address * @max_lun: Maximum number of logical units * @max_id: Maximum number of target ids + * @max_bytes_per_req: Maximum number of bytes per read/write request */ struct scsi_platdata { unsigned long base; unsigned long max_lun; unsigned long max_id; + unsigned long max_bytes_per_req; }; /* Operations for SCSI */ diff --git a/include/spi.h b/include/spi.h index 5eec0c4..3f79168 100644 --- a/include/spi.h +++ b/include/spi.h @@ -458,7 +458,7 @@ struct dm_spi_ops { * @cs: The chip select (0..n-1) * @info: Returns information about the chip select, if valid. * On entry info->dev is NULL - * @return 0 if OK (and @info is set up), -ENODEV if the chip select + * @return 0 if OK (and @info is set up), -EINVAL if the chip select * is invalid, other -ve value on error */ int (*cs_info)(struct udevice *bus, uint cs, struct spi_cs_info *info); diff --git a/include/ufs.h b/include/ufs.h new file mode 100644 index 0000000..0592a76 --- /dev/null +++ b/include/ufs.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +#ifndef _UFS_H +#define _UFS_H +/** + * ufs_probe() - initialize all devices in the UFS uclass + * + * @return 0 if Ok, -ve on error + */ +int ufs_probe(void); + +/** + * ufs_probe_dev() - initialize a particular device in the UFS uclass + * + * @index: index in the uclass sequence + * + * @return 0 if successfully probed, -ve on error + */ +int ufs_probe_dev(int index); + +/* + * ufs_scsi_bind() - Create a new scsi device as a child of the UFS device and + * bind it to the ufs_scsi driver + * @ufs_dev: UFS device + * @scsi_devp: Pointer to scsi device + * + * @return 0 if Ok, -ve on error + */ +int ufs_scsi_bind(struct udevice *ufs_dev, struct udevice **scsi_devp); +#endif diff --git a/drivers/usb/host/xhci.h b/include/usb/xhci.h index 6017504..6017504 100644 --- a/drivers/usb/host/xhci.h +++ b/include/usb/xhci.h diff --git a/include/zynqmp_firmware.h b/include/zynqmp_firmware.h index a20cbcd..93d771e 100644 --- a/include/zynqmp_firmware.h +++ b/include/zynqmp_firmware.h @@ -11,12 +11,58 @@ enum pm_api_id { PM_GET_API_VERSION = 1, PM_SET_CONFIGURATION, - PM_SECURE_IMAGE = 45, + PM_GET_NODE_STATUS, + PM_GET_OPERATING_CHARACTERISTIC, + PM_REGISTER_NOTIFIER, + PM_REQUEST_SUSPEND, + PM_SELF_SUSPEND, + PM_FORCE_POWERDOWN, + PM_ABORT_SUSPEND, + PM_REQUEST_WAKEUP, + PM_SET_WAKEUP_SOURCE, + PM_SYSTEM_SHUTDOWN, + PM_REQUEST_NODE, + PM_RELEASE_NODE, + PM_SET_REQUIREMENT, + PM_SET_MAX_LATENCY, + PM_RESET_ASSERT, + PM_RESET_GET_STATUS, + PM_MMIO_WRITE, + PM_MMIO_READ, + PM_PM_INIT_FINALIZE, + PM_FPGA_LOAD, + PM_FPGA_GET_STATUS, + PM_GET_CHIPID, + PM_SECURE_SHA = 26, + PM_SECURE_RSA, + PM_PINCTRL_REQUEST, + PM_PINCTRL_RELEASE, + PM_PINCTRL_GET_FUNCTION, + PM_PINCTRL_SET_FUNCTION, + PM_PINCTRL_CONFIG_PARAM_GET, + PM_PINCTRL_CONFIG_PARAM_SET, + PM_IOCTL, + PM_QUERY_DATA, + PM_CLOCK_ENABLE, + PM_CLOCK_DISABLE, + PM_CLOCK_GETSTATE, + PM_CLOCK_SETDIVIDER, + PM_CLOCK_GETDIVIDER, + PM_CLOCK_SETRATE, + PM_CLOCK_GETRATE, + PM_CLOCK_SETPARENT, + PM_CLOCK_GETPARENT, + PM_SECURE_IMAGE, + PM_FPGA_READ = 46, + PM_SECURE_AES, + PM_CLOCK_PLL_GETPARAM = 49, + PM_REGISTER_ACCESS = 52, + PM_EFUSE_ACCESS, + PM_FEATURE_CHECK = 63, + PM_API_MAX, }; #define PM_SIP_SVC 0xc2000000 -#define ZYNQMP_SIP_SVC_PM_SECURE_IMG_LOAD \ - (PM_SIP_SVC + PM_SECURE_IMAGE) #define ZYNQMP_PM_VERSION_MAJOR 1 #define ZYNQMP_PM_VERSION_MINOR 0 @@ -33,5 +79,7 @@ enum pm_api_id { unsigned int zynqmp_firmware_version(void); void zynqmp_pmufw_load_config_object(const void *cfg_obj, size_t size); +int xilinx_pm_request(u32 api_id, u32 arg0, u32 arg1, u32 arg2, + u32 arg3, u32 *ret_payload); #endif /* _ZYNQMP_FIRMWARE_H_ */ diff --git a/tools/.gitignore b/tools/.gitignore index bd03d32..d0176a7 100644 --- a/tools/.gitignore +++ b/tools/.gitignore @@ -31,4 +31,5 @@ /spl_size_limit /sunxi-spl-image-builder /ubsha1 +/version.h /xway-swap-bytes diff --git a/tools/buildman/control.py b/tools/buildman/control.py index fcf531c..9787b86 100644 --- a/tools/buildman/control.py +++ b/tools/buildman/control.py @@ -201,14 +201,14 @@ def DoBuildman(options, args, toolchains=None, make_func=None, boards=None, # Work out what subset of the boards we are building if not boards: - board_file = os.path.join(options.git, 'boards.cfg') - status = subprocess.call([os.path.join(options.git, - 'tools/genboardscfg.py')]) + board_file = os.path.join(options.output_dir, 'boards.cfg') + genboardscfg = os.path.join(options.git, 'tools/genboardscfg.py') + status = subprocess.call([genboardscfg, '-o', board_file]) if status != 0: - sys.exit("Failed to generate boards.cfg") + sys.exit("Failed to generate boards.cfg") boards = board.Boards() - boards.ReadBoards(os.path.join(options.git, 'boards.cfg')) + boards.ReadBoards(board_file) exclude = [] if options.exclude: diff --git a/tools/buildman/test.py b/tools/buildman/test.py index de02f61..ed99b93 100644 --- a/tools/buildman/test.py +++ b/tools/buildman/test.py @@ -156,14 +156,6 @@ class TestBuild(unittest.TestCase): result.return_code = commit.return_code result.stderr = (''.join(commit.error_list) % {'basedir' : base_dir + '/.bm-work/00/'}) - if stage == 'build': - target_dir = None - for arg in args: - if arg.startswith('O='): - target_dir = arg[2:] - - if not os.path.isdir(target_dir): - os.mkdir(target_dir) result.combined = result.stdout + result.stderr return result diff --git a/tools/ifwitool.c b/tools/ifwitool.c index 2e020a8..543e9d4 100644 --- a/tools/ifwitool.c +++ b/tools/ifwitool.c @@ -10,7 +10,9 @@ #include <getopt.h> #include "os_support.h" +#ifndef __packed #define __packed __attribute__((packed)) +#endif #define KiB 1024 #define ALIGN(x, a) __ALIGN_MASK((x), (typeof(x))(a) - 1) #define __ALIGN_MASK(x, mask) (((x) + (mask)) & ~(mask)) diff --git a/tools/mtk_image.h b/tools/mtk_image.h index 0a9eab3..4e78b3d 100644 --- a/tools/mtk_image.h +++ b/tools/mtk_image.h @@ -9,14 +9,14 @@ #ifndef _MTK_IMAGE_H #define _MTK_IMAGE_H -/* Device header definitions */ +/* Device header definitions, all fields are little-endian */ /* Header for NOR/SD/eMMC */ union gen_boot_header { struct { char name[12]; - __le32 version; - __le32 size; + uint32_t version; + uint32_t size; }; uint8_t pad[0x200]; @@ -32,14 +32,14 @@ union nand_boot_header { char name[12]; char version[4]; char id[8]; - __le16 ioif; - __le16 pagesize; - __le16 addrcycles; - __le16 oobsize; - __le16 pages_of_block; - __le16 numblocks; - __le16 writesize_shift; - __le16 erasesize_shift; + uint16_t ioif; + uint16_t pagesize; + uint16_t addrcycles; + uint16_t oobsize; + uint16_t pages_of_block; + uint16_t numblocks; + uint16_t writesize_shift; + uint16_t erasesize_shift; uint8_t dummy[60]; uint8_t ecc_parity[28]; }; @@ -54,14 +54,14 @@ union nand_boot_header { /* BootROM layout header */ struct brom_layout_header { char name[8]; - __le32 version; - __le32 header_size; - __le32 total_size; - __le32 magic; - __le32 type; - __le32 header_size_2; - __le32 total_size_2; - __le32 unused; + uint32_t version; + uint32_t header_size; + uint32_t total_size; + uint32_t magic; + uint32_t type; + uint32_t header_size_2; + uint32_t total_size_2; + uint32_t unused; }; #define BRLYT_NAME "BRLYT" @@ -90,8 +90,8 @@ struct gen_device_header { struct gfh_common_header { uint8_t magic[3]; uint8_t version; - __le16 size; - __le16 type; + uint16_t size; + uint16_t type; }; #define GFH_HEADER_MAGIC "MMM" @@ -106,17 +106,17 @@ struct gfh_common_header { struct gfh_file_info { struct gfh_common_header gfh; char name[12]; - __le32 unused; - __le16 file_type; + uint32_t unused; + uint16_t file_type; uint8_t flash_type; uint8_t sig_type; - __le32 load_addr; - __le32 total_size; - __le32 max_size; - __le32 hdr_size; - __le32 sig_size; - __le32 jump_offset; - __le32 processed; + uint32_t load_addr; + uint32_t total_size; + uint32_t max_size; + uint32_t hdr_size; + uint32_t sig_size; + uint32_t jump_offset; + uint32_t processed; }; #define GFH_FILE_INFO_NAME "FILE_INFO" @@ -129,16 +129,16 @@ struct gfh_file_info { struct gfh_bl_info { struct gfh_common_header gfh; - __le32 attr; + uint32_t attr; }; struct gfh_brom_cfg { struct gfh_common_header gfh; - __le32 cfg_bits; - __le32 usbdl_by_auto_detect_timeout_ms; + uint32_t cfg_bits; + uint32_t usbdl_by_auto_detect_timeout_ms; uint8_t unused[0x48]; - __le32 usbdl_by_kcol0_timeout_ms; - __le32 usbdl_by_flag_timeout_ms; + uint32_t usbdl_by_kcol0_timeout_ms; + uint32_t usbdl_by_flag_timeout_ms; uint32_t pad; }; @@ -157,15 +157,15 @@ struct gfh_anti_clone { uint8_t ac_b2k; uint8_t ac_b2c; uint16_t pad; - __le32 ac_offset; - __le32 ac_len; + uint32_t ac_offset; + uint32_t ac_len; }; struct gfh_brom_sec_cfg { struct gfh_common_header gfh; - __le32 cfg_bits; + uint32_t cfg_bits; char customer_name[0x20]; - __le32 pad; + uint32_t pad; }; #define BROM_SEC_CFG_JTAG_EN 1 @@ -184,11 +184,11 @@ struct gfh_header { union lk_hdr { struct { - __le32 magic; - __le32 size; + uint32_t magic; + uint32_t size; char name[32]; - __le32 loadaddr; - __le32 mode; + uint32_t loadaddr; + uint32_t mode; }; uint8_t data[512]; diff --git a/tools/version.h b/tools/version.h deleted file mode 120000 index bb57607..0000000 --- a/tools/version.h +++ /dev/null @@ -1 +0,0 @@ -../include/version.h
\ No newline at end of file diff --git a/tools/zynqmp_psu_init_minimize.sh b/tools/zynqmp_psu_init_minimize.sh index 384bb56..4ee418f 100755 --- a/tools/zynqmp_psu_init_minimize.sh +++ b/tools/zynqmp_psu_init_minimize.sh @@ -64,7 +64,6 @@ psu_..._protection psu_init_xppu_aper_ram mask_delay(u32 mask_read(u32 -dpll_prog mask_poll(u32 mask_pollonvalue(u32 psu_ps_pl_reset_config_data diff --git a/tools/zynqmpbif.c b/tools/zynqmpbif.c index 8c47107..82ce0ac 100644 --- a/tools/zynqmpbif.c +++ b/tools/zynqmpbif.c @@ -517,7 +517,7 @@ static int bif_add_bit(struct bif_entry *bf) debug("Bitstream Length: 0x%x\n", bitlen); for (i = 0; i < bitlen; i += sizeof(uint32_t)) { uint32_t *bitbin32 = (uint32_t *)&bitbin[i]; - *bitbin32 = __swab32(*bitbin32); + *bitbin32 = __builtin_bswap32(*bitbin32); } if (!bf->dest_dev) |