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-rw-r--r--arch/arm/dts/Makefile5
-rw-r--r--arch/arm/dts/px30-engicam-common.dtsi90
-rw-r--r--arch/arm/dts/px30-engicam-ctouch2.dtsi22
-rw-r--r--arch/arm/dts/px30-engicam-edimm2.2.dtsi59
-rw-r--r--arch/arm/dts/px30-engicam-px30-core-ctouch2-of10.dts77
-rw-r--r--arch/arm/dts/px30-engicam-px30-core-ctouch2.dts (renamed from arch/arm/dts/px30-px30-core-ctouch2.dts)4
-rw-r--r--arch/arm/dts/px30-engicam-px30-core-edimm2.2.dts43
-rw-r--r--arch/arm/dts/px30-engicam-px30-core.dtsi (renamed from arch/arm/dts/px30-px30-core.dtsi)11
-rw-r--r--arch/arm/dts/px30-evb.dts143
-rw-r--r--arch/arm/dts/px30-px30-core-edimm2.2.dts21
-rw-r--r--arch/arm/dts/px30-u-boot.dtsi14
-rw-r--r--arch/arm/dts/px30.dtsi275
-rw-r--r--arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi18
-rw-r--r--arch/arm/dts/rk3326-odroid-go2.dts178
-rw-r--r--arch/arm/dts/rk3399-u-boot.dtsi4
-rw-r--r--arch/arm/dts/rk3568-u-boot.dtsi17
-rw-r--r--arch/arm/mach-rockchip/Kconfig2
-rw-r--r--arch/arm/mach-rockchip/boot_mode.c2
-rw-r--r--arch/arm/mach-rockchip/px30/Kconfig8
-rw-r--r--arch/arm/mach-rockchip/rk3568/rk3568.c27
-rw-r--r--board/amlogic/vim3/MAINTAINERS4
-rw-r--r--board/engicam/px30_core/MAINTAINERS6
-rw-r--r--board/theobroma-systems/puma_rk3399/README66
-rw-r--r--cmd/Kconfig7
-rw-r--r--cmd/Makefile1
-rw-r--r--cmd/kaslrseed.c81
-rw-r--r--configs/bananapi-m5_defconfig1
-rw-r--r--configs/beelink-gsking-x_defconfig1
-rw-r--r--configs/beelink-gtking_defconfig1
-rw-r--r--configs/beelink-gtkingpro_defconfig1
-rw-r--r--configs/evb-rk3568_defconfig25
-rw-r--r--configs/jethub_j80_defconfig1
-rw-r--r--configs/khadas-vim2_defconfig1
-rw-r--r--configs/khadas-vim3_android_ab_defconfig109
-rw-r--r--configs/khadas-vim3_android_defconfig107
-rw-r--r--configs/khadas-vim3_defconfig1
-rw-r--r--configs/khadas-vim3l_android_ab_defconfig109
-rw-r--r--configs/khadas-vim3l_android_defconfig107
-rw-r--r--configs/khadas-vim3l_defconfig1
-rw-r--r--configs/khadas-vim_defconfig1
-rw-r--r--configs/libretech-ac_defconfig1
-rw-r--r--configs/libretech-cc_defconfig1
-rw-r--r--configs/libretech-cc_v2_defconfig1
-rw-r--r--configs/libretech-s905d-pc_defconfig1
-rw-r--r--configs/libretech-s912-pc_defconfig1
-rw-r--r--configs/odroid-c4_defconfig1
-rw-r--r--configs/odroid-hc4_defconfig1
-rw-r--r--configs/odroid-n2_defconfig1
-rw-r--r--configs/p212_defconfig1
-rw-r--r--configs/px30-core-ctouch2-of10-px30_defconfig108
-rw-r--r--configs/px30-core-ctouch2-px30_defconfig4
-rw-r--r--configs/px30-core-edimm2.2-px30_defconfig4
-rw-r--r--configs/rock-pi-4-rk3399_defconfig1
-rw-r--r--configs/rock-pi-4c-rk3399_defconfig1
-rw-r--r--configs/s400_defconfig1
-rw-r--r--configs/sei510_defconfig1
-rw-r--r--configs/sei610_defconfig1
-rw-r--r--configs/u200_defconfig1
-rw-r--r--configs/wetek-core2_defconfig1
-rw-r--r--doc/README.rockchip27
-rw-r--r--doc/develop/uefi/uefi.rst6
-rw-r--r--drivers/mtd/spi/Kconfig6
-rw-r--r--drivers/mtd/spi/spi-nor-ids.c5
-rw-r--r--drivers/power/pmic/Kconfig14
-rw-r--r--drivers/power/pmic/Makefile2
-rw-r--r--drivers/spi/cadence_qspi_apb.c17
-rw-r--r--drivers/sysreset/sysreset_watchdog.c13
-rw-r--r--drivers/video/mxsfb.c4
-rw-r--r--include/configs/khadas-vim3_android.h50
-rw-r--r--include/configs/khadas-vim3l_android.h50
-rw-r--r--include/configs/meson64_android.h17
-rw-r--r--include/configs/rk3568_common.h6
-rw-r--r--lib/aes/aes-encrypt.c3
-rw-r--r--lib/ecdsa/ecdsa-libcrypto.c2
-rw-r--r--lib/rsa/rsa-sign.c2
-rw-r--r--tools/kwbimage.c8
-rw-r--r--tools/rkcommon.c226
77 files changed, 1827 insertions, 414 deletions
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 453e2fd..aeaec71 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -78,8 +78,9 @@ dtb-$(CONFIG_MACH_S700) += \
dtb-$(CONFIG_ROCKCHIP_PX30) += \
px30-evb.dtb \
px30-firefly.dtb \
- px30-px30-core-ctouch2.dtb \
- px30-px30-core-edimm2.2.dtb \
+ px30-engicam-px30-core-ctouch2.dtb \
+ px30-engicam-px30-core-ctouch2-of10.dtb \
+ px30-engicam-px30-core-edimm2.2.dtb \
rk3326-odroid-go2.dtb
dtb-$(CONFIG_ROCKCHIP_RK3036) += \
diff --git a/arch/arm/dts/px30-engicam-common.dtsi b/arch/arm/dts/px30-engicam-common.dtsi
index bd5bde9..3429e12 100644
--- a/arch/arm/dts/px30-engicam-common.dtsi
+++ b/arch/arm/dts/px30-engicam-common.dtsi
@@ -6,6 +6,11 @@
*/
/ {
+ aliases {
+ mmc1 = &sdmmc;
+ mmc2 = &sdio;
+ };
+
vcc5v0_sys: vcc5v0-sys {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_sys"; /* +5V */
@@ -14,6 +19,63 @@
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ clocks = <&xin32k>;
+ clock-names = "ext_clock";
+ post-power-on-delay-ms = <80>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&wifi_enable_h>;
+ };
+
+ vcc3v3_btreg: vcc3v3-btreg {
+ compatible = "regulator-gpio";
+ enable-active-high;
+ pinctrl-names = "default";
+ pinctrl-0 = <&bt_enable_h>;
+ regulator-name = "btreg-gpio-supply";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ states = <3300000 0x0>;
+ };
+
+ vcc3v3_rf_aux_mod: vcc3v3-rf-aux-mod {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_rf_aux_mod";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ xin32k: xin32k {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "xin32k";
+ };
+};
+
+&sdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ bus-width = <4>;
+ clock-frequency = <50000000>;
+ cap-sdio-irq;
+ cap-sd-highspeed;
+ keep-power-in-suspend;
+ mmc-pwrseq = <&sdio_pwrseq>;
+ non-removable;
+ sd-uhs-sdr104;
+ status = "okay";
+
+ brcmf: wifi@1 {
+ compatible = "brcm,bcm4329-fmac";
+ reg = <1>;
+ };
};
&gmac {
@@ -25,6 +87,10 @@
status = "okay";
};
+&pwm0 {
+ status = "okay";
+};
+
&sdmmc {
cap-sd-highspeed;
card-detect-delay = <800>;
@@ -33,7 +99,31 @@
status = "okay";
};
+&u2phy {
+ status = "okay";
+
+ u2phy_host: host-port {
+ status = "okay";
+ };
+
+ u2phy_otg: otg-port {
+ status = "okay";
+ };
+};
+
&uart2 {
pinctrl-0 = <&uart2m1_xfer>;
status = "okay";
};
+
+&usb20_otg {
+ status = "okay";
+};
+
+&usb_host0_ehci {
+ status = "okay";
+};
+
+&usb_host0_ohci {
+ status = "okay";
+};
diff --git a/arch/arm/dts/px30-engicam-ctouch2.dtsi b/arch/arm/dts/px30-engicam-ctouch2.dtsi
index 58425b1..bf10a3d 100644
--- a/arch/arm/dts/px30-engicam-ctouch2.dtsi
+++ b/arch/arm/dts/px30-engicam-ctouch2.dtsi
@@ -6,3 +6,25 @@
*/
#include "px30-engicam-common.dtsi"
+
+&pinctrl {
+ bt {
+ bt_enable_h: bt-enable-h {
+ rockchip,pins = <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ sdio-pwrseq {
+ wifi_enable_h: wifi-enable-h {
+ rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&sdio_pwrseq {
+ reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
+};
+
+&vcc3v3_btreg {
+ enable-gpio = <&gpio1 RK_PC3 GPIO_ACTIVE_HIGH>;
+};
diff --git a/arch/arm/dts/px30-engicam-edimm2.2.dtsi b/arch/arm/dts/px30-engicam-edimm2.2.dtsi
index cb00988..449b8eb 100644
--- a/arch/arm/dts/px30-engicam-edimm2.2.dtsi
+++ b/arch/arm/dts/px30-engicam-edimm2.2.dtsi
@@ -5,3 +5,62 @@
*/
#include "px30-engicam-common.dtsi"
+
+/ {
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ pwms = <&pwm0 0 25000 0>;
+ };
+
+ panel {
+ compatible = "yes-optoelectronics,ytc700tlag-05-201c";
+ backlight = <&backlight>;
+ data-mapping = "vesa-24";
+ power-supply = <&vcc3v3_lcd>;
+
+ port {
+ panel_in_lvds: endpoint {
+ remote-endpoint = <&lvds_out_panel>;
+ };
+ };
+ };
+};
+
+&display_subsystem {
+ status = "okay";
+};
+
+&dsi_dphy {
+ status = "okay";
+};
+
+/* LVDS_B(secondary) */
+&lvds {
+ status = "okay";
+
+ ports {
+ port@1 {
+ reg = <1>;
+
+ lvds_out_panel: endpoint {
+ remote-endpoint = <&panel_in_lvds>;
+ };
+ };
+ };
+};
+
+&vopb {
+ status = "okay";
+};
+
+&vopb_mmu {
+ status = "okay";
+};
+
+&vopl {
+ status = "okay";
+};
+
+&vopl_mmu {
+ status = "okay";
+};
diff --git a/arch/arm/dts/px30-engicam-px30-core-ctouch2-of10.dts b/arch/arm/dts/px30-engicam-px30-core-ctouch2-of10.dts
new file mode 100644
index 0000000..47aa305
--- /dev/null
+++ b/arch/arm/dts/px30-engicam-px30-core-ctouch2-of10.dts
@@ -0,0 +1,77 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd
+ * Copyright (c) 2020 Engicam srl
+ * Copyright (c) 2020 Amarula Solutions(India)
+ */
+
+/dts-v1/;
+#include "px30.dtsi"
+#include "px30-engicam-ctouch2.dtsi"
+#include "px30-engicam-px30-core.dtsi"
+
+/ {
+ model = "Engicam PX30.Core C.TOUCH 2.0 10.1\" Open Frame";
+ compatible = "engicam,px30-core-ctouch2-of10", "engicam,px30-core",
+ "rockchip,px30";
+
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ pwms = <&pwm0 0 25000 0>;
+ };
+
+ chosen {
+ stdout-path = "serial2:115200n8";
+ };
+
+ panel {
+ compatible = "ampire,am-1280800n3tzqw-t00h";
+ backlight = <&backlight>;
+ power-supply = <&vcc3v3_lcd>;
+ data-mapping = "vesa-24";
+
+ port {
+ panel_in_lvds: endpoint {
+ remote-endpoint = <&lvds_out_panel>;
+ };
+ };
+ };
+};
+
+&display_subsystem {
+ status = "okay";
+};
+
+&dsi_dphy {
+ status = "okay";
+};
+
+&lvds {
+ status = "okay";
+
+ ports {
+ port@1 {
+ reg = <1>;
+
+ lvds_out_panel: endpoint {
+ remote-endpoint = <&panel_in_lvds>;
+ };
+ };
+ };
+};
+
+&vopb {
+ status = "okay";
+};
+
+&vopb_mmu {
+ status = "okay";
+};
+
+&vopl {
+ status = "okay";
+};
+
+&vopl_mmu {
+ status = "okay";
+};
diff --git a/arch/arm/dts/px30-px30-core-ctouch2.dts b/arch/arm/dts/px30-engicam-px30-core-ctouch2.dts
index 2da0128..5a0ecb8 100644
--- a/arch/arm/dts/px30-px30-core-ctouch2.dts
+++ b/arch/arm/dts/px30-engicam-px30-core-ctouch2.dts
@@ -9,11 +9,11 @@
/dts-v1/;
#include "px30.dtsi"
#include "px30-engicam-ctouch2.dtsi"
-#include "px30-px30-core.dtsi"
+#include "px30-engicam-px30-core.dtsi"
/ {
model = "Engicam PX30.Core C.TOUCH 2.0";
- compatible = "engicam,px30-core-ctouch2", "engicam,px30-px30-core",
+ compatible = "engicam,px30-core-ctouch2", "engicam,px30-core",
"rockchip,px30";
chosen {
diff --git a/arch/arm/dts/px30-engicam-px30-core-edimm2.2.dts b/arch/arm/dts/px30-engicam-px30-core-edimm2.2.dts
new file mode 100644
index 0000000..d759478
--- /dev/null
+++ b/arch/arm/dts/px30-engicam-px30-core-edimm2.2.dts
@@ -0,0 +1,43 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd
+ * Copyright (c) 2020 Engicam srl
+ * Copyright (c) 2020 Amarula Solutions(India)
+ */
+
+/dts-v1/;
+#include "px30.dtsi"
+#include "px30-engicam-edimm2.2.dtsi"
+#include "px30-engicam-px30-core.dtsi"
+
+/ {
+ model = "Engicam PX30.Core EDIMM2.2 Starter Kit";
+ compatible = "engicam,px30-core-edimm2.2", "engicam,px30-core",
+ "rockchip,px30";
+
+ chosen {
+ stdout-path = "serial2:115200n8";
+ };
+};
+
+&pinctrl {
+ bt {
+ bt_enable_h: bt-enable-h {
+ rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ sdio-pwrseq {
+ wifi_enable_h: wifi-enable-h {
+ rockchip,pins = <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&sdio_pwrseq {
+ reset-gpios = <&gpio1 RK_PC3 GPIO_ACTIVE_LOW>;
+};
+
+&vcc3v3_btreg {
+ enable-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>;
+};
diff --git a/arch/arm/dts/px30-px30-core.dtsi b/arch/arm/dts/px30-engicam-px30-core.dtsi
index 16e6cf2..7249871 100644
--- a/arch/arm/dts/px30-px30-core.dtsi
+++ b/arch/arm/dts/px30-engicam-px30-core.dtsi
@@ -10,7 +10,11 @@
#include <dt-bindings/pinctrl/rockchip.h>
/ {
- compatible = "engicam,px30-px30-core", "rockchip,px30";
+ compatible = "engicam,px30-core", "rockchip,px30";
+
+ aliases {
+ mmc0 = &emmc;
+ };
};
&cpu0 {
@@ -192,6 +196,11 @@
};
};
+ vcc3v3_lcd: SWITCH_REG1 {
+ regulator-boot-on;
+ regulator-name = "vcc3v3_lcd";
+ };
+
vcc5v0_host: SWITCH_REG2 {
regulator-name = "vcc5v0_host";
regulator-always-on;
diff --git a/arch/arm/dts/px30-evb.dts b/arch/arm/dts/px30-evb.dts
index 4134e2e..848bc39 100644
--- a/arch/arm/dts/px30-evb.dts
+++ b/arch/arm/dts/px30-evb.dts
@@ -13,8 +13,14 @@
model = "Rockchip PX30 EVB";
compatible = "rockchip,px30-evb", "rockchip,px30";
+ aliases {
+ mmc0 = &sdmmc;
+ mmc1 = &sdio;
+ mmc2 = &emmc;
+ };
+
chosen {
- stdout-path = "serial2:115200n8";
+ stdout-path = "serial5:115200n8";
};
adc-keys {
@@ -108,6 +114,10 @@
cpu-supply = <&vdd_arm>;
};
+&csi_dphy {
+ status = "okay";
+};
+
&display_subsystem {
status = "okay";
};
@@ -126,22 +136,15 @@
};
panel@0 {
- compatible = "sitronix,st7703";
+ compatible = "xinpeng,xpp055c272";
reg = <0>;
backlight = <&backlight>;
iovcc-supply = <&vcc_1v8>;
vci-supply = <&vcc3v3_lcd>;
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
-
- mipi_in_panel: endpoint {
- remote-endpoint = <&mipi_out_panel>;
- };
+ port {
+ mipi_in_panel: endpoint {
+ remote-endpoint = <&mipi_out_panel>;
};
};
};
@@ -152,7 +155,6 @@
};
&emmc {
- bus-width = <8>;
cap-mmc-highspeed;
mmc-hs200-1_8v;
non-removable;
@@ -171,6 +173,11 @@
status = "okay";
};
+&gpu {
+ mali-supply = <&vdd_log>;
+ status = "okay";
+};
+
&i2c0 {
status = "okay";
@@ -388,6 +395,73 @@
};
};
+&i2c1 {
+ status = "okay";
+
+ sensor@d {
+ compatible = "asahi-kasei,ak8963";
+ reg = <0x0d>;
+ gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
+ vdd-supply = <&vcc3v0_pmu>;
+ mount-matrix = "1", /* x0 */
+ "0", /* y0 */
+ "0", /* z0 */
+ "0", /* x1 */
+ "1", /* y1 */
+ "0", /* z1 */
+ "0", /* x2 */
+ "0", /* y2 */
+ "1"; /* z2 */
+ };
+
+ touchscreen@14 {
+ compatible = "goodix,gt1151";
+ reg = <0x14>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PA5 IRQ_TYPE_LEVEL_LOW>;
+ irq-gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
+ reset-gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>;
+ VDDIO-supply = <&vcc3v3_lcd>;
+ };
+
+ sensor@4c {
+ compatible = "fsl,mma7660";
+ reg = <0x4c>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PB7 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+&i2c2 {
+ status = "okay";
+
+ clock-frequency = <100000>;
+
+ /* These are relatively safe rise/fall times; TODO: measure */
+ i2c-scl-falling-time-ns = <50>;
+ i2c-scl-rising-time-ns = <300>;
+
+ ov5695: ov5695@36 {
+ compatible = "ovti,ov5695";
+ reg = <0x36>;
+ avdd-supply = <&vcc2v8_dvp>;
+ clocks = <&cru SCLK_CIF_OUT>;
+ clock-names = "xvclk";
+ dvdd-supply = <&vcc1v5_dvp>;
+ dovdd-supply = <&vcc1v8_dvp>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&cif_clkout_m0>;
+ reset-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>;
+
+ port {
+ ucam_out: endpoint {
+ remote-endpoint = <&mipi_in_ucam>;
+ data-lanes = <1 2>;
+ };
+ };
+ };
+};
+
&i2s1_2ch {
status = "okay";
};
@@ -403,6 +477,24 @@
vccio6-supply = <&vccio_flash>;
};
+&isp {
+ status = "okay";
+
+ ports {
+ port@0 {
+ mipi_in_ucam: endpoint@0 {
+ reg = <0>;
+ data-lanes = <1 2>;
+ remote-endpoint = <&ucam_out>;
+ };
+ };
+ };
+};
+
+&isp_mmu {
+ status = "okay";
+};
+
&pinctrl {
headphone {
hp_det: hp-det {
@@ -464,7 +556,6 @@
};
&sdmmc {
- bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
card-detect-delay = <800>;
@@ -474,10 +565,10 @@
sd-uhs-sdr104;
vmmc-supply = <&vcc_sd>;
vqmmc-supply = <&vccio_sd>;
+ status = "okay";
};
&sdio {
- bus-width = <4>;
cap-sd-highspeed;
keep-power-in-suspend;
non-removable;
@@ -486,13 +577,27 @@
status = "okay";
};
-&uart1 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart1_xfer &uart1_cts>;
+&tsadc {
+ rockchip,hw-tshut-mode = <1>;
+ rockchip,hw-tshut-polarity = <1>;
status = "okay";
};
-&uart2 {
+&u2phy {
+ status = "okay";
+
+ u2phy_host: host-port {
+ status = "okay";
+ };
+
+ u2phy_otg: otg-port {
+ status = "okay";
+ };
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_xfer &uart1_cts>;
status = "okay";
};
diff --git a/arch/arm/dts/px30-px30-core-edimm2.2.dts b/arch/arm/dts/px30-px30-core-edimm2.2.dts
deleted file mode 100644
index c36280c..0000000
--- a/arch/arm/dts/px30-px30-core-edimm2.2.dts
+++ /dev/null
@@ -1,21 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd
- * Copyright (c) 2020 Engicam srl
- * Copyright (c) 2020 Amarula Solutions(India)
- */
-
-/dts-v1/;
-#include "px30.dtsi"
-#include "px30-engicam-edimm2.2.dtsi"
-#include "px30-px30-core.dtsi"
-
-/ {
- model = "Engicam PX30.Core EDIMM2.2 Starter Kit";
- compatible = "engicam,px30-core-edimm2.2", "engicam,px30-px30-core",
- "rockchip,px30";
-
- chosen {
- stdout-path = "serial2:115200n8";
- };
-};
diff --git a/arch/arm/dts/px30-u-boot.dtsi b/arch/arm/dts/px30-u-boot.dtsi
index 029c8fb..f102b2a 100644
--- a/arch/arm/dts/px30-u-boot.dtsi
+++ b/arch/arm/dts/px30-u-boot.dtsi
@@ -13,6 +13,12 @@
u-boot,spl-boot-order = &emmc, &sdmmc;
};
+ dmc {
+ u-boot,dm-pre-reloc;
+ compatible = "rockchip,px30-dmc", "syscon";
+ reg = <0x0 0xff2a0000 0x0 0x1000>;
+ };
+
rng: rng@ff0b0000 {
compatible = "rockchip,cryptov2-rng";
reg = <0x0 0xff0b0000 0x0 0x4000>;
@@ -20,10 +26,6 @@
};
};
-&dmc {
- u-boot,dm-pre-reloc;
-};
-
&uart2 {
clock-frequency = <24000000>;
u-boot,dm-pre-reloc;
@@ -62,10 +64,14 @@
&cru {
u-boot,dm-pre-reloc;
+ /delete-property/ assigned-clocks;
+ /delete-property/ assigned-clock-rates;
};
&pmucru {
u-boot,dm-pre-reloc;
+ /delete-property/ assigned-clocks;
+ /delete-property/ assigned-clock-rates;
};
&saradc {
diff --git a/arch/arm/dts/px30.dtsi b/arch/arm/dts/px30.dtsi
index ef70648..00f50b0 100644
--- a/arch/arm/dts/px30.dtsi
+++ b/arch/arm/dts/px30.dtsi
@@ -110,7 +110,7 @@
};
};
- cpu0_opp_table: cpu0-opp-table {
+ cpu0_opp_table: opp-table-0 {
compatible = "operating-points-v2";
opp-shared;
@@ -143,7 +143,7 @@
};
arm-pmu {
- compatible = "arm,cortex-a53-pmu";
+ compatible = "arm,cortex-a35-pmu";
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
@@ -151,11 +151,6 @@
interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
};
- dmc: dmc {
- compatible = "rockchip,px30-dmc", "syscon";
- reg = <0x0 0xff2a0000 0x0 0x1000>;
- };
-
display_subsystem: display-subsystem {
compatible = "rockchip,display-subsystem";
ports = <&vopb_out>, <&vopl_out>;
@@ -249,28 +244,31 @@
#size-cells = <0>;
/* These power domains are grouped by VD_LOGIC */
- pd_usb@PX30_PD_USB {
+ power-domain@PX30_PD_USB {
reg = <PX30_PD_USB>;
clocks = <&cru HCLK_HOST>,
<&cru HCLK_OTG>,
<&cru SCLK_OTG_ADP>;
pm_qos = <&qos_usb_host>, <&qos_usb_otg>;
+ #power-domain-cells = <0>;
};
- pd_sdcard@PX30_PD_SDCARD {
+ power-domain@PX30_PD_SDCARD {
reg = <PX30_PD_SDCARD>;
clocks = <&cru HCLK_SDMMC>,
<&cru SCLK_SDMMC>;
pm_qos = <&qos_sdmmc>;
+ #power-domain-cells = <0>;
};
- pd_gmac@PX30_PD_GMAC {
+ power-domain@PX30_PD_GMAC {
reg = <PX30_PD_GMAC>;
clocks = <&cru ACLK_GMAC>,
<&cru PCLK_GMAC>,
<&cru SCLK_MAC_REF>,
<&cru SCLK_GMAC_RX_TX>;
pm_qos = <&qos_gmac>;
+ #power-domain-cells = <0>;
};
- pd_mmc_nand@PX30_PD_MMC_NAND {
+ power-domain@PX30_PD_MMC_NAND {
reg = <PX30_PD_MMC_NAND>;
clocks = <&cru HCLK_NANDC>,
<&cru HCLK_EMMC>,
@@ -282,15 +280,17 @@
<&cru SCLK_SFC>;
pm_qos = <&qos_emmc>, <&qos_nand>,
<&qos_sdio>, <&qos_sfc>;
+ #power-domain-cells = <0>;
};
- pd_vpu@PX30_PD_VPU {
+ power-domain@PX30_PD_VPU {
reg = <PX30_PD_VPU>;
clocks = <&cru ACLK_VPU>,
<&cru HCLK_VPU>,
<&cru SCLK_CORE_VPU>;
pm_qos = <&qos_vpu>, <&qos_vpu_r128>;
+ #power-domain-cells = <0>;
};
- pd_vo@PX30_PD_VO {
+ power-domain@PX30_PD_VO {
reg = <PX30_PD_VO>;
clocks = <&cru ACLK_RGA>,
<&cru ACLK_VOPB>,
@@ -305,8 +305,9 @@
<&cru SCLK_VOPB_PWM>;
pm_qos = <&qos_rga_rd>, <&qos_rga_wr>,
<&qos_vop_m0>, <&qos_vop_m1>;
+ #power-domain-cells = <0>;
};
- pd_vi@PX30_PD_VI {
+ power-domain@PX30_PD_VI {
reg = <PX30_PD_VI>;
clocks = <&cru ACLK_CIF>,
<&cru ACLK_ISP>,
@@ -316,11 +317,13 @@
pm_qos = <&qos_isp_128>, <&qos_isp_rd>,
<&qos_isp_wr>, <&qos_isp_m1>,
<&qos_vip>;
+ #power-domain-cells = <0>;
};
- pd_gpu@PX30_PD_GPU {
+ power-domain@PX30_PD_GPU {
reg = <PX30_PD_GPU>;
clocks = <&cru SCLK_GPU>;
pm_qos = <&qos_gpu>;
+ #power-domain-cells = <0>;
};
};
};
@@ -605,7 +608,7 @@
};
wdt: watchdog@ff1e0000 {
- compatible = "snps,dw-wdt";
+ compatible = "rockchip,px30-wdt", "snps,dw-wdt";
reg = <0x0 0xff1e0000 0x0 0x100>;
clocks = <&cru PCLK_WDT_NS>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
@@ -708,21 +711,15 @@
clock-names = "pclk", "timer";
};
- amba {
- compatible = "simple-bus";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- dmac: dmac@ff240000 {
- compatible = "arm,pl330", "arm,primecell";
- reg = <0x0 0xff240000 0x0 0x4000>;
- interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru ACLK_DMAC>;
- clock-names = "apb_pclk";
- #dma-cells = <1>;
- };
+ dmac: dmac@ff240000 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0x0 0xff240000 0x0 0x4000>;
+ interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+ arm,pl330-periph-burst;
+ clocks = <&cru ACLK_DMAC>;
+ clock-names = "apb_pclk";
+ #dma-cells = <1>;
};
tsadc: tsadc@ff280000 {
@@ -738,9 +735,9 @@
rockchip,grf = <&grf>;
rockchip,hw-tshut-temp = <120000>;
pinctrl-names = "init", "default", "sleep";
- pinctrl-0 = <&tsadc_otp_gpio>;
+ pinctrl-0 = <&tsadc_otp_pin>;
pinctrl-1 = <&tsadc_otp_out>;
- pinctrl-2 = <&tsadc_otp_gpio>;
+ pinctrl-2 = <&tsadc_otp_pin>;
#thermal-sensor-cells = <1>;
status = "disabled";
};
@@ -789,6 +786,16 @@
rockchip,grf = <&grf>;
#clock-cells = <1>;
#reset-cells = <1>;
+
+ assigned-clocks = <&cru PLL_NPLL>,
+ <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
+ <&cru HCLK_BUS_PRE>, <&cru HCLK_PERI_PRE>,
+ <&cru PCLK_BUS_PRE>, <&cru SCLK_GPU>;
+
+ assigned-clock-rates = <1188000000>,
+ <200000000>, <200000000>,
+ <150000000>, <150000000>,
+ <100000000>, <200000000>;
};
pmucru: clock-controller@ff2bc000 {
@@ -799,6 +806,13 @@
rockchip,grf = <&grf>;
#clock-cells = <1>;
#reset-cells = <1>;
+
+ assigned-clocks =
+ <&pmucru PLL_GPLL>, <&pmucru PCLK_PMU_PRE>,
+ <&pmucru SCLK_WIFI_PMU>;
+ assigned-clock-rates =
+ <1200000000>, <100000000>,
+ <26000000>;
};
usb2phy_grf: syscon@ff2c0000 {
@@ -808,7 +822,7 @@
#address-cells = <1>;
#size-cells = <1>;
- u2phy: usb2-phy@100 {
+ u2phy: usb2phy@100 {
compatible = "rockchip,px30-usb2phy";
reg = <0x100 0x20>;
clocks = <&pmucru SCLK_USBPHY_REF>;
@@ -850,6 +864,19 @@
status = "disabled";
};
+ csi_dphy: phy@ff2f0000 {
+ compatible = "rockchip,px30-csi-dphy";
+ reg = <0x0 0xff2f0000 0x0 0x4000>;
+ clocks = <&cru PCLK_MIPICSIPHY>;
+ clock-names = "pclk";
+ #phy-cells = <0>;
+ power-domains = <&power PX30_PD_VI>;
+ resets = <&cru SRST_MIPICSIPHY_P>;
+ reset-names = "apb";
+ rockchip,grf = <&grf>;
+ status = "disabled";
+ };
+
usb20_otg: usb@ff300000 {
compatible = "rockchip,px30-usb", "rockchip,rk3066-usb",
"snps,dwc2";
@@ -861,7 +888,6 @@
g-np-tx-fifo-size = <16>;
g-rx-fifo-size = <280>;
g-tx-fifo-size = <256 128 128 64 32 16>;
- g-use-dma;
phys = <&u2phy_otg>;
phy-names = "usb2-phy";
power-domains = <&power PX30_PD_USB>;
@@ -873,7 +899,6 @@
reg = <0x0 0xff340000 0x0 0x10000>;
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_HOST>;
- clock-names = "usbhost";
phys = <&u2phy_host>;
phy-names = "usb";
power-domains = <&power PX30_PD_USB>;
@@ -885,7 +910,6 @@
reg = <0x0 0xff350000 0x0 0x10000>;
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_HOST>;
- clock-names = "usbhost";
phys = <&u2phy_host>;
phy-names = "usb";
power-domains = <&power PX30_PD_USB>;
@@ -915,13 +939,14 @@
status = "disabled";
};
- sdmmc: dwmmc@ff370000 {
+ sdmmc: mmc@ff370000 {
compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x0 0xff370000 0x0 0x4000>;
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
<&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
- clock-names = "biu", "ciu", "ciu-drv", "ciu-sample";
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+ bus-width = <4>;
fifo-depth = <0x100>;
max-frequency = <150000000>;
pinctrl-names = "default";
@@ -930,13 +955,14 @@
status = "disabled";
};
- sdio: dwmmc@ff380000 {
+ sdio: mmc@ff380000 {
compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x0 0xff380000 0x0 0x4000>;
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
<&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
- clock-names = "biu", "ciu", "ciu-drv", "ciu-sample";
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+ bus-width = <4>;
fifo-depth = <0x100>;
max-frequency = <150000000>;
pinctrl-names = "default";
@@ -945,13 +971,14 @@
status = "disabled";
};
- emmc: dwmmc@ff390000 {
+ emmc: mmc@ff390000 {
compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x0 0xff390000 0x0 0x4000>;
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
<&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
- clock-names = "biu", "ciu", "ciu-drv", "ciu-sample";
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+ bus-width = <8>;
fifo-depth = <0x100>;
max-frequency = <150000000>;
pinctrl-names = "default";
@@ -960,18 +987,54 @@
status = "disabled";
};
- sfc: sfc@ff3a0000 {
+ sfc: spi@ff3a0000 {
compatible = "rockchip,sfc";
reg = <0x0 0xff3a0000 0x0 0x4000>;
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
clock-names = "clk_sfc", "hclk_sfc";
- pinctrl-names = "default";
pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus4>;
+ pinctrl-names = "default";
+ power-domains = <&power PX30_PD_MMC_NAND>;
+ status = "disabled";
+ };
+
+ nfc: nand-controller@ff3b0000 {
+ compatible = "rockchip,px30-nfc";
+ reg = <0x0 0xff3b0000 0x0 0x4000>;
+ interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>;
+ clock-names = "ahb", "nfc";
+ assigned-clocks = <&cru SCLK_NANDC>;
+ assigned-clock-rates = <150000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_cs0
+ &flash_rdn &flash_rdy &flash_wrn &flash_dqs>;
power-domains = <&power PX30_PD_MMC_NAND>;
status = "disabled";
};
+ gpu_opp_table: opp-table-1 {
+ compatible = "operating-points-v2";
+
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ opp-microvolt = <950000>;
+ };
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ opp-microvolt = <975000>;
+ };
+ opp-400000000 {
+ opp-hz = /bits/ 64 <400000000>;
+ opp-microvolt = <1050000>;
+ };
+ opp-480000000 {
+ opp-hz = /bits/ 64 <480000000>;
+ opp-microvolt = <1125000>;
+ };
+ };
+
gpu: gpu@ff400000 {
compatible = "rockchip,px30-mali", "arm,mali-bifrost";
reg = <0x0 0xff400000 0x0 0x4000>;
@@ -982,9 +1045,32 @@
clocks = <&cru SCLK_GPU>;
#cooling-cells = <2>;
power-domains = <&power PX30_PD_GPU>;
+ operating-points-v2 = <&gpu_opp_table>;
status = "disabled";
};
+ vpu: video-codec@ff442000 {
+ compatible = "rockchip,px30-vpu";
+ reg = <0x0 0xff442000 0x0 0x800>;
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "vepu", "vdpu";
+ clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
+ clock-names = "aclk", "hclk";
+ iommus = <&vpu_mmu>;
+ power-domains = <&power PX30_PD_VPU>;
+ };
+
+ vpu_mmu: iommu@ff442800 {
+ compatible = "rockchip,iommu";
+ reg = <0x0 0xff442800 0x0 0x100>;
+ interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
+ clock-names = "aclk", "iface";
+ #iommu-cells = <0>;
+ power-domains = <&power PX30_PD_VPU>;
+ };
+
dsi: dsi@ff450000 {
compatible = "rockchip,px30-mipi-dsi";
reg = <0x0 0xff450000 0x0 0x10000>;
@@ -1034,7 +1120,6 @@
reset-names = "axi", "ahb", "dclk";
iommus = <&vopb_mmu>;
power-domains = <&power PX30_PD_VO>;
- rockchip,grf = <&grf>;
status = "disabled";
vopb_out: port {
@@ -1057,7 +1142,6 @@
compatible = "rockchip,iommu";
reg = <0x0 0xff460f00 0x0 0x100>;
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "vopb_mmu";
clocks = <&cru ACLK_VOPB>, <&cru HCLK_VOPB>;
clock-names = "aclk", "iface";
power-domains = <&power PX30_PD_VO>;
@@ -1076,7 +1160,6 @@
reset-names = "axi", "ahb", "dclk";
iommus = <&vopl_mmu>;
power-domains = <&power PX30_PD_VO>;
- rockchip,grf = <&grf>;
status = "disabled";
vopl_out: port {
@@ -1098,8 +1181,7 @@
vopl_mmu: iommu@ff470f00 {
compatible = "rockchip,iommu";
reg = <0x0 0xff470f00 0x0 0x100>;
- interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "vopl_mmu";
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru ACLK_VOPL>, <&cru HCLK_VOPL>;
clock-names = "aclk", "iface";
power-domains = <&power PX30_PD_VO>;
@@ -1107,103 +1189,144 @@
status = "disabled";
};
+ isp: isp@ff4a0000 {
+ compatible = "rockchip,px30-cif-isp"; /*rk3326-rkisp1*/
+ reg = <0x0 0xff4a0000 0x0 0x8000>;
+ interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "isp", "mi", "mipi";
+ clocks = <&cru SCLK_ISP>,
+ <&cru ACLK_ISP>,
+ <&cru HCLK_ISP>,
+ <&cru PCLK_ISP>;
+ clock-names = "isp", "aclk", "hclk", "pclk";
+ iommus = <&isp_mmu>;
+ phys = <&csi_dphy>;
+ phy-names = "dphy";
+ power-domains = <&power PX30_PD_VI>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+ };
+
+ isp_mmu: iommu@ff4a8000 {
+ compatible = "rockchip,iommu";
+ reg = <0x0 0xff4a8000 0x0 0x100>;
+ interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>;
+ clock-names = "aclk", "iface";
+ power-domains = <&power PX30_PD_VI>;
+ rockchip,disable-mmu-reset;
+ #iommu-cells = <0>;
+ };
+
qos_gmac: qos@ff518000 {
- compatible = "syscon";
+ compatible = "rockchip,px30-qos", "syscon";
reg = <0x0 0xff518000 0x0 0x20>;
};
qos_gpu: qos@ff520000 {
- compatible = "syscon";
+ compatible = "rockchip,px30-qos", "syscon";
reg = <0x0 0xff520000 0x0 0x20>;
};
qos_sdmmc: qos@ff52c000 {
- compatible = "syscon";
+ compatible = "rockchip,px30-qos", "syscon";
reg = <0x0 0xff52c000 0x0 0x20>;
};
qos_emmc: qos@ff538000 {
- compatible = "syscon";
+ compatible = "rockchip,px30-qos", "syscon";
reg = <0x0 0xff538000 0x0 0x20>;
};
qos_nand: qos@ff538080 {
- compatible = "syscon";
+ compatible = "rockchip,px30-qos", "syscon";
reg = <0x0 0xff538080 0x0 0x20>;
};
qos_sdio: qos@ff538100 {
- compatible = "syscon";
+ compatible = "rockchip,px30-qos", "syscon";
reg = <0x0 0xff538100 0x0 0x20>;
};
qos_sfc: qos@ff538180 {
- compatible = "syscon";
+ compatible = "rockchip,px30-qos", "syscon";
reg = <0x0 0xff538180 0x0 0x20>;
};
qos_usb_host: qos@ff540000 {
- compatible = "syscon";
+ compatible = "rockchip,px30-qos", "syscon";
reg = <0x0 0xff540000 0x0 0x20>;
};
qos_usb_otg: qos@ff540080 {
- compatible = "syscon";
+ compatible = "rockchip,px30-qos", "syscon";
reg = <0x0 0xff540080 0x0 0x20>;
};
qos_isp_128: qos@ff548000 {
- compatible = "syscon";
+ compatible = "rockchip,px30-qos", "syscon";
reg = <0x0 0xff548000 0x0 0x20>;
};
qos_isp_rd: qos@ff548080 {
- compatible = "syscon";
+ compatible = "rockchip,px30-qos", "syscon";
reg = <0x0 0xff548080 0x0 0x20>;
};
qos_isp_wr: qos@ff548100 {
- compatible = "syscon";
+ compatible = "rockchip,px30-qos", "syscon";
reg = <0x0 0xff548100 0x0 0x20>;
};
qos_isp_m1: qos@ff548180 {
- compatible = "syscon";
+ compatible = "rockchip,px30-qos", "syscon";
reg = <0x0 0xff548180 0x0 0x20>;
};
qos_vip: qos@ff548200 {
- compatible = "syscon";
+ compatible = "rockchip,px30-qos", "syscon";
reg = <0x0 0xff548200 0x0 0x20>;
};
qos_rga_rd: qos@ff550000 {
- compatible = "syscon";
+ compatible = "rockchip,px30-qos", "syscon";
reg = <0x0 0xff550000 0x0 0x20>;
};
qos_rga_wr: qos@ff550080 {
- compatible = "syscon";
+ compatible = "rockchip,px30-qos", "syscon";
reg = <0x0 0xff550080 0x0 0x20>;
};
qos_vop_m0: qos@ff550100 {
- compatible = "syscon";
+ compatible = "rockchip,px30-qos", "syscon";
reg = <0x0 0xff550100 0x0 0x20>;
};
qos_vop_m1: qos@ff550180 {
- compatible = "syscon";
+ compatible = "rockchip,px30-qos", "syscon";
reg = <0x0 0xff550180 0x0 0x20>;
};
qos_vpu: qos@ff558000 {
- compatible = "syscon";
+ compatible = "rockchip,px30-qos", "syscon";
reg = <0x0 0xff558000 0x0 0x20>;
};
qos_vpu_r128: qos@ff558080 {
- compatible = "syscon";
+ compatible = "rockchip,px30-qos", "syscon";
reg = <0x0 0xff558080 0x0 0x20>;
};
@@ -1215,7 +1338,7 @@
#size-cells = <2>;
ranges;
- gpio0: gpio0@ff040000 {
+ gpio0: gpio@ff040000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0xff040000 0x0 0x100>;
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
@@ -1227,7 +1350,7 @@
#interrupt-cells = <2>;
};
- gpio1: gpio1@ff250000 {
+ gpio1: gpio@ff250000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0xff250000 0x0 0x100>;
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
@@ -1239,7 +1362,7 @@
#interrupt-cells = <2>;
};
- gpio2: gpio2@ff260000 {
+ gpio2: gpio@ff260000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0xff260000 0x0 0x100>;
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
@@ -1251,7 +1374,7 @@
#interrupt-cells = <2>;
};
- gpio3: gpio3@ff270000 {
+ gpio3: gpio@ff270000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0xff270000 0x0 0x100>;
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
@@ -1375,7 +1498,7 @@
};
tsadc {
- tsadc_otp_gpio: tsadc-otp-gpio {
+ tsadc_otp_pin: tsadc-otp-pin {
rockchip,pins =
<0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
};
@@ -1938,7 +2061,7 @@
};
};
- serial_flash {
+ sfc {
sfc_bus4: sfc-bus4 {
rockchip,pins =
<1 RK_PA0 3 &pcfg_pull_none>,
diff --git a/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi b/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi
index bffaa3e..95f2652 100644
--- a/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi
+++ b/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi
@@ -16,6 +16,18 @@
serial2 = &uart2;
spi0 = &sfc;
};
+
+ dmc {
+ u-boot,dm-pre-reloc;
+ compatible = "rockchip,px30-dmc", "syscon";
+ reg = <0x0 0xff2a0000 0x0 0x1000>;
+ };
+
+ rng: rng@ff0b0000 {
+ compatible = "rockchip,cryptov2-rng";
+ reg = <0x0 0xff0b0000 0x0 0x4000>;
+ status = "okay";
+ };
};
/* U-Boot clk driver for px30 cannot set GPU_CLK */
@@ -32,10 +44,6 @@
<100000000>, <17000000>;
};
-&dmc {
- u-boot,dm-pre-reloc;
-};
-
&gpio0 {
u-boot,dm-pre-reloc;
};
@@ -80,7 +88,7 @@
u-boot,dm-pre-reloc;
};
-&{/sfc@ff3a0000/flash@0} {
+&{/spi@ff3a0000/flash@0} {
u-boot,dm-pre-reloc;
};
diff --git a/arch/arm/dts/rk3326-odroid-go2.dts b/arch/arm/dts/rk3326-odroid-go2.dts
index 4e3dcee..ea0695b 100644
--- a/arch/arm/dts/rk3326-odroid-go2.dts
+++ b/arch/arm/dts/rk3326-odroid-go2.dts
@@ -14,14 +14,12 @@
model = "ODROID-GO Advance";
compatible = "hardkernel,rk3326-odroid-go2", "rockchip,rk3326";
- chosen {
- stdout-path = "serial2:115200n8";
+ aliases {
+ mmc0 = &sdmmc;
};
- backlight: backlight {
- compatible = "pwm-backlight";
- power-supply = <&vcc_bl>;
- pwms = <&pwm1 0 25000 0>;
+ chosen {
+ stdout-path = "serial2:115200n8";
};
adc-joystick {
@@ -33,21 +31,27 @@
axis@0 {
reg = <0>;
- abs-range = <172 772>;
- abs-fuzz = <10>;
abs-flat = <10>;
+ abs-fuzz = <10>;
+ abs-range = <172 772>;
linux,code = <ABS_X>;
};
axis@1 {
reg = <1>;
- abs-range = <278 815>;
- abs-fuzz = <10>;
abs-flat = <10>;
+ abs-fuzz = <10>;
+ abs-range = <278 815>;
linux,code = <ABS_Y>;
};
};
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ power-supply = <&vcc_bl>;
+ pwms = <&pwm1 0 25000 0>;
+ };
+
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
@@ -163,25 +167,26 @@
rk817-sound {
compatible = "simple-audio-card";
+ simple-audio-card,name = "Analog";
simple-audio-card,format = "i2s";
- simple-audio-card,name = "rockchip,rk817-codec";
+ simple-audio-card,hp-det-gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>;
simple-audio-card,mclk-fs = <256>;
simple-audio-card,widgets =
"Microphone", "Mic Jack",
- "Headphone", "Headphone Jack";
+ "Headphone", "Headphones",
+ "Speaker", "Speaker";
simple-audio-card,routing =
- "MIC_IN", "Mic Jack",
- "Headphone Jack", "HPOL",
- "Headphone Jack", "HPOR";
- simple-audio-card,hp-det-gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_LOW>;
- simple-audio-card,codec-hp-det = <1>;
+ "MICL", "Mic Jack",
+ "Headphones", "HPOL",
+ "Headphones", "HPOR",
+ "Speaker", "SPKO";
- simple-audio-card,cpu {
- sound-dai = <&i2s1_2ch>;
+ simple-audio-card,codec {
+ sound-dai = <&rk817>;
};
- simple-audio-card,codec {
- sound-dai = <&rk817_codec>;
+ simple-audio-card,cpu {
+ sound-dai = <&i2s1_2ch>;
};
};
@@ -202,7 +207,8 @@
gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-always-on;
- vin-supply = <&vccsys>;
+ regulator-boot-on;
+ vin-supply = <&usb_midu>;
};
};
@@ -259,6 +265,7 @@
backlight = <&backlight>;
iovcc-supply = <&vcc_lcd>;
reset-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>;
+ rotation = <270>;
vdd-supply = <&vcc_lcd>;
port {
@@ -289,16 +296,14 @@
reg = <0x20>;
interrupt-parent = <&gpio0>;
interrupts = <RK_PB2 IRQ_TYPE_LEVEL_LOW>;
- pinctrl-names = "default", "pmic-sleep",
- "pmic-power-off", "pmic-reset";
- pinctrl-0 = <&pmic_int>;
- pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>;
- pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>;
- pinctrl-3 = <&soc_slppin_rst>, <&rk817_slppin_rst>;
- rockchip,system-power-controller;
+ clock-output-names = "rk808-clkout1", "xin32k";
+ clock-names = "mclk";
+ clocks = <&cru SCLK_I2S1_OUT>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int>, <&i2s1_2ch_mclk>;
wakeup-source;
#clock-cells = <1>;
- clock-output-names = "rk808-clkout1", "xin32k";
+ #sound-dai-cells = <0>;
vcc1-supply = <&vccsys>;
vcc2-supply = <&vccsys>;
@@ -307,53 +312,7 @@
vcc5-supply = <&vccsys>;
vcc6-supply = <&vccsys>;
vcc7-supply = <&vccsys>;
-
- pinctrl_rk8xx: pinctrl_rk8xx {
- gpio-controller;
- #gpio-cells = <2>;
-
- rk817_ts_gpio1: rk817_ts_gpio1 {
- pins = "gpio_ts";
- function = "pin_fun1";
- /* output-low; */
- /* input-enable; */
- };
-
- rk817_gt_gpio2: rk817_gt_gpio2 {
- pins = "gpio_gt";
- function = "pin_fun1";
- };
-
- rk817_pin_ts: rk817_pin_ts {
- pins = "gpio_ts";
- function = "pin_fun0";
- };
-
- rk817_pin_gt: rk817_pin_gt {
- pins = "gpio_gt";
- function = "pin_fun0";
- };
-
- rk817_slppin_null: rk817_slppin_null {
- pins = "gpio_slp";
- function = "pin_fun0";
- };
-
- rk817_slppin_slp: rk817_slppin_slp {
- pins = "gpio_slp";
- function = "pin_fun1";
- };
-
- rk817_slppin_pwrdn: rk817_slppin_pwrdn {
- pins = "gpio_slp";
- function = "pin_fun2";
- };
-
- rk817_slppin_rst: rk817_slppin_rst {
- pins = "gpio_slp";
- function = "pin_fun3";
- };
- };
+ vcc8-supply = <&vccsys>;
regulators {
vdd_logic: DCDC_REG1 {
@@ -503,66 +462,18 @@
regulator-suspend-microvolt = <3000000>;
};
};
- };
- battery {
- compatible = "rk817,battery";
- ocv_table = <3500 3625 3685 3697 3718 3735 3748
- 3760 3774 3788 3802 3816 3834 3853
- 3877 3908 3946 3975 4018 4071 4106>;
-
- /* KPL605475 Battery Spec */
- /*
- Capacity : 3.7V 3000mA
- Normal Voltage = 3.7V
- Cut-Off Voltage : 3.1V
- Internal Impedance : 180 mOhm
- Charging Voltage : 4.2V
- Charging Voltage Max : 4.25V
- Sample resister : 10 mohm
- */
- design_capacity = <3000>;
- design_qmax = <3000>;
- bat_res = <180>;
- sleep_enter_current = <300>;
- sleep_exit_current = <300>;
- sleep_filter_current = <100>;
- power_off_thresd = <3500>;
- zero_algorithm_vol = <3700>;
- max_soc_offset = <60>;
- monitor_sec = <5>;
- virtual_power = <0>;
- sample_res = <10>;
- };
-
- charger {
- compatible = "rk817,charger";
- min_input_voltage = <4500>;
- max_input_current = <1500>;
- max_chrg_current = <2000>;
- max_chrg_voltage = <4200>;
- chrg_term_mode = <0>;
- chrg_finish_cur = <300>;
- virtual_power = <0>;
- sample_res = <10>;
-
- /* P.C.B rev0.2 DC Detect & Charger Status LED GPIO */
- dc_det_gpio = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>;
- chg_led_gpio = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>;
-
- extcon = <&u2phy>;
+ usb_midu: BOOST {
+ regulator-name = "usb_midu";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5400000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
};
rk817_codec: codec {
- #sound-dai-cells = <0>;
- compatible = "rockchip,rk817-codec";
- clocks = <&cru SCLK_I2S1_OUT>;
- clock-names = "mclk";
- pinctrl-names = "default";
- pinctrl-0 = <&i2s1_2ch_mclk>;
- hp-volume = <20>;
- spk-volume = <3>;
- status = "okay";
+ rockchip,mic-in-differential;
};
};
};
@@ -604,7 +515,6 @@
};
&sdmmc {
- bus-width = <4>;
cap-sd-highspeed;
card-detect-delay = <200>;
cd-gpios = <&gpio0 RK_PA3 GPIO_ACTIVE_LOW>; /*[> CD GPIO <]*/
diff --git a/arch/arm/dts/rk3399-u-boot.dtsi b/arch/arm/dts/rk3399-u-boot.dtsi
index 73922c3..716b9a4 100644
--- a/arch/arm/dts/rk3399-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-u-boot.dtsi
@@ -88,6 +88,10 @@
u-boot,dm-pre-reloc;
};
+&emmc_phy {
+ u-boot,dm-pre-reloc;
+};
+
&grf {
u-boot,dm-pre-reloc;
};
diff --git a/arch/arm/dts/rk3568-u-boot.dtsi b/arch/arm/dts/rk3568-u-boot.dtsi
index 1570f13..5a80dda 100644
--- a/arch/arm/dts/rk3568-u-boot.dtsi
+++ b/arch/arm/dts/rk3568-u-boot.dtsi
@@ -9,6 +9,10 @@
mmc1 = &sdmmc0;
};
+ chosen {
+ u-boot,spl-boot-order = &sdhci, &sdmmc0;
+ };
+
dmc: dmc {
compatible = "rockchip,rk3568-dmc";
u-boot,dm-pre-reloc;
@@ -35,3 +39,16 @@
u-boot,dm-pre-reloc;
status = "okay";
};
+
+&sdmmc0 {
+ u-boot,dm-spl;
+ status = "okay";
+};
+
+&sdhci {
+ bus-width = <8>;
+ u-boot,dm-spl;
+ mmc-hs200-1_8v;
+ status = "okay";
+};
+
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index c4645a0..92f3530 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -255,6 +255,8 @@ config ROCKCHIP_RK3399
config ROCKCHIP_RK3568
bool "Support Rockchip RK3568"
select ARM64
+ select SUPPORT_SPL
+ select SPL
select CLK
select PINCTRL
select RAM
diff --git a/arch/arm/mach-rockchip/boot_mode.c b/arch/arm/mach-rockchip/boot_mode.c
index 2158934..1a1a887 100644
--- a/arch/arm/mach-rockchip/boot_mode.c
+++ b/arch/arm/mach-rockchip/boot_mode.c
@@ -95,7 +95,7 @@ int setup_boot_mode(void)
switch (boot_mode) {
case BOOT_FASTBOOT:
debug("%s: enter fastboot!\n", __func__);
- env_set("preboot", "setenv preboot; fastboot usb0");
+ env_set("preboot", "setenv preboot; fastboot usb 0");
break;
case BOOT_UMS:
debug("%s: enter UMS!\n", __func__);
diff --git a/arch/arm/mach-rockchip/px30/Kconfig b/arch/arm/mach-rockchip/px30/Kconfig
index aa5cc47..145bf35 100644
--- a/arch/arm/mach-rockchip/px30/Kconfig
+++ b/arch/arm/mach-rockchip/px30/Kconfig
@@ -27,6 +27,14 @@ config TARGET_PX30_CORE
* PX30.Core needs to mount on top of CTOUCH2.0 for creating complete
PX30.Core C.TOUCH Carrier board.
+ PX30.Core CTOUCH2-OF10:
+ * PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam.
+ * CTOUCH2.0 is a general purpose Carrier board with capacitive
+ touch interface support.
+ * 10.1" OF is a capacitive touch 10.1" Open Frame panel solutions.
+ * PX30.Core needs to mount on top of C.TOUCH 2.0 carrier with pluged
+ 10.1" OF for creating complete PX30.Core C.TOUCH 2.0 10.1" Open Frame.
+
config ROCKCHIP_BOOT_MODE_REG
default 0xff010200
diff --git a/arch/arm/mach-rockchip/rk3568/rk3568.c b/arch/arm/mach-rockchip/rk3568/rk3568.c
index 973b4f9..22eeb77 100644
--- a/arch/arm/mach-rockchip/rk3568/rk3568.c
+++ b/arch/arm/mach-rockchip/rk3568/rk3568.c
@@ -11,9 +11,18 @@
#include <asm/arch-rockchip/hardware.h>
#include <dt-bindings/clock/rk3568-cru.h>
-#define PMUGRF_BASE 0xfdc20000
-#define GRF_BASE 0xfdc60000
-
+#define PMUGRF_BASE 0xfdc20000
+#define GRF_BASE 0xfdc60000
+#define GRF_GPIO1B_DS_2 0x218
+#define GRF_GPIO1B_DS_3 0x21c
+#define GRF_GPIO1C_DS_0 0x220
+#define GRF_GPIO1C_DS_1 0x224
+#define GRF_GPIO1C_DS_2 0x228
+#define GRF_GPIO1C_DS_3 0x22c
+#define SGRF_BASE 0xFDD18000
+#define SGRF_SOC_CON4 0x10
+#define EMMC_HPROT_SECURE_CTRL 0x03
+#define SDMMC0_HPROT_SECURE_CTRL 0x01
/* PMU_GRF_GPIO0D_IOMUX_L */
enum {
GPIO0D1_SHIFT = 4,
@@ -81,5 +90,17 @@ void board_debug_uart_init(void)
int arch_cpu_init(void)
{
+#ifdef CONFIG_SPL_BUILD
+ /* Set the emmc sdmmc0 to secure */
+ rk_clrreg(SGRF_BASE + SGRF_SOC_CON4, (EMMC_HPROT_SECURE_CTRL << 11
+ | SDMMC0_HPROT_SECURE_CTRL << 4));
+ /* set the emmc driver strength to level 2 */
+ writel(0x3f3f0707, GRF_BASE + GRF_GPIO1B_DS_2);
+ writel(0x3f3f0707, GRF_BASE + GRF_GPIO1B_DS_3);
+ writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_0);
+ writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_1);
+ writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_2);
+ writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_3);
+#endif
return 0;
}
diff --git a/board/amlogic/vim3/MAINTAINERS b/board/amlogic/vim3/MAINTAINERS
index 92b426f..d884849 100644
--- a/board/amlogic/vim3/MAINTAINERS
+++ b/board/amlogic/vim3/MAINTAINERS
@@ -4,6 +4,10 @@ S: Maintained
L: u-boot-amlogic@groups.io
F: board/amlogic/vim3/
F: configs/khadas-vim3_defconfig
+F: configs/khadas-vim3_android_defconfig
+F: configs/khadas-vim3_android_ab_defconfig
F: configs/khadas-vim3l_defconfig
+F: configs/khadas-vim3l_android_defconfig
+F: configs/khadas-vim3l_android_ab_defconfig
F: doc/board/amlogic/khadas-vim3.rst
F: doc/board/amlogic/khadas-vim3l.rst
diff --git a/board/engicam/px30_core/MAINTAINERS b/board/engicam/px30_core/MAINTAINERS
index b87ca22..77f0c2d 100644
--- a/board/engicam/px30_core/MAINTAINERS
+++ b/board/engicam/px30_core/MAINTAINERS
@@ -4,6 +4,12 @@ M: Suniel Mahesh <sunil@amarulasolutions.com>
S: Maintained
F: configs/px30-core-ctouch2-px30_defconfig
+PX30-Core-CTOUCH2.0-OF10
+M: Jagan Teki <jagan@amarulasolutions.com>
+M: Suniel Mahesh <sunil@amarulasolutions.com>
+S: Maintained
+F: configs/px30-core-ctouch2-of10-px30_defconfig
+
PX30-Core-EDIMM2.2
M: Jagan Teki <jagan@amarulasolutions.com>
M: Suniel Mahesh <sunil@amarulasolutions.com>
diff --git a/board/theobroma-systems/puma_rk3399/README b/board/theobroma-systems/puma_rk3399/README
index 9b31b0b..254c3bb 100644
--- a/board/theobroma-systems/puma_rk3399/README
+++ b/board/theobroma-systems/puma_rk3399/README
@@ -26,25 +26,17 @@ RK3399-Q7 features:
Here is the step-by-step to boot to U-Boot on rk3399.
-Get the Source and build ATF/Cortex-M0 binaries
-===============================================
+Get the Source and build ATF binary
+===================================
- > git clone git://git.theobroma-systems.com/arm-trusted-firmware.git
- > git clone git://git.theobroma-systems.com/rk3399-cortex-m0.git
+ > git clone https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git
Compile the ATF
===============
- > cd arm-trusted-firmware
+ > cd trusted-firmware-a
> make CROSS_COMPILE=aarch64-linux-gnu- PLAT=rk3399 bl31
- > cp build/rk3399/release/bl31.bin ../u-boot/bl31-rk3399.bin
-
-Compile the M0 firmware
-=======================
-
- > cd ../rk3399-cortex-m0
- > make CROSS_COMPILE=arm-cortex_m0-eabi-
- > cp rk3399m0.bin ../u-boot
+ > cp build/rk3399/release/bl31/bl31.elf ../u-boot/bl31.elf
Compile the U-Boot
==================
@@ -55,23 +47,22 @@ Compile the U-Boot
Package the image
=================
-Creating a SPL image for SD-Card/eMMC
- > tools/mkimage -n rk3399 -T rksd -d spl/u-boot-spl.bin spl_mmc.img
-Creating a SPL image for SPI-NOR
- > tools/mkimage -n rk3399 -T rkspi -d spl/u-boot-spl.bin spl_nor.img
-Create the FIT image containing U-Boot proper, ATF, M0 Firmware, devicetree
- > make CROSS_COMPILE=aarch64-linux-gnu-
+The SPL image for SD-Card/eMMC is readily available in idbloader.img at the
+root of U-Boot after compilation.
+
+Creating an SPL image for SPI-NOR:
+ > tools/mkimage -n rk3399 -T rkspi -d spl/u-boot-spl.bin idbloader-spi.img
Flash the image
===============
Copy the SPL to offset 32k for SD/eMMC, offset 0 for NOR-Flash and the FIT
-image to offset 256k card.
+image to offset 256k.
SD-Card
-------
- > dd if=spl_mmc.img of=/dev/sdb seek=64
+ > dd if=idbloader.img of=/dev/sdb seek=64
> dd if=u-boot.itb of=/dev/sdb seek=512
eMMC
@@ -84,24 +75,27 @@ help of the Rockchip loader binary.
> cd rkdeveloptool
> autoreconf -i && ./configure && make
> git clone https://github.com/rockchip-linux/rkbin.git
- > ./rkdeveloptool db rkbin/rk33/rk3399_loader_v1.08.106.bin
- > ./rkdeveloptool wl 64 ../spl_mmc.img
+ > cd rkbin
+ > ./tools/boot_merger RKBOOT/RK3399MINIALL.ini
+ > cd ..
+ > ./rkdeveloptool db rkbin/rk3399_loader_v1.25.126.bin
+ > ./rkdeveloptool wl 64 ../idbloader.img
> ./rkdeveloptool wl 512 ../u-boot.itb
NOR-Flash
---------
-Writing the SPI NOR Flash requires a running U-Boot. For the sake of simplicity
-we assume you have a SD-Card with a partition containing the required files
-ready.
-
- > load mmc 1:1 ${kernel_addr_r} spl_nor.img
- > sf probe
- > sf erase 0 +$filesize
- > sf write $kernel_addr_r 0 ${filesize}
- > load mmc 1:1 ${kernel_addr_r} u-boot.itb
- > sf erase 0x40000 +$filesize
- > sf write $kernel_addr_r 0x40000 ${filesize}
-
+rkdeveloptool allows to flash the on-board SPI via the USB OTG interface with
+help of the Rockchip loader binary.
-Reboot the system and you should see a U-Boot console on UART0 (115200n8).
+ > git clone https://github.com/rockchip-linux/rkdeveloptool
+ > cd rkdeveloptool
+ > autoreconf -i && ./configure && make
+ > git clone https://github.com/rockchip-linux/rkbin.git
+ > cd rkbin
+ > ./tools/boot_merger RKBOOT/RK3399MINIALL_SPINOR.ini
+ > cd ..
+ > ./rkdeveloptool db rkbin/rk3399_loader_spinor_v1.25.114.bin
+ > ./rkdeveloptool ef
+ > ./rkdeveloptool wl 0 ../idbloader-spi.img
+ > ./rkdeveloptool wl 512 ../u-boot.itb
diff --git a/cmd/Kconfig b/cmd/Kconfig
index ef82f79..d70dbd4 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -1814,6 +1814,13 @@ config CMD_RNG
help
Print bytes from the hardware random number generator.
+config CMD_KASLRSEED
+ bool "kaslrseed"
+ depends on DM_RNG
+ help
+ Set the kaslr-seed in the chosen node with entropy provided by a
+ hardware random number generator.
+
config CMD_SLEEP
bool "sleep"
default y
diff --git a/cmd/Makefile b/cmd/Makefile
index 891819a..e31ac15 100644
--- a/cmd/Makefile
+++ b/cmd/Makefile
@@ -131,6 +131,7 @@ obj-$(CONFIG_CMD_REGINFO) += reginfo.o
obj-$(CONFIG_CMD_REISER) += reiser.o
obj-$(CONFIG_CMD_REMOTEPROC) += remoteproc.o
obj-$(CONFIG_CMD_RNG) += rng.o
+obj-$(CONFIG_CMD_KASLRSEED) += kaslrseed.o
obj-$(CONFIG_CMD_ROCKUSB) += rockusb.o
obj-$(CONFIG_CMD_RTC) += rtc.o
obj-$(CONFIG_SANDBOX) += host.o
diff --git a/cmd/kaslrseed.c b/cmd/kaslrseed.c
new file mode 100644
index 0000000..8a1d812
--- /dev/null
+++ b/cmd/kaslrseed.c
@@ -0,0 +1,81 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * The 'kaslrseed' command takes bytes from the hardware random number
+ * generator and uses them to set the kaslr-seed value in the chosen node.
+ *
+ * Copyright (c) 2021, Chris Morgan <macromorgan@hotmail.com>
+ */
+
+#include <common.h>
+#include <command.h>
+#include <dm.h>
+#include <hexdump.h>
+#include <malloc.h>
+#include <rng.h>
+#include <fdt_support.h>
+
+static int do_kaslr_seed(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+{
+ size_t n = 0x8;
+ struct udevice *dev;
+ u64 *buf;
+ int nodeoffset;
+ int ret = CMD_RET_SUCCESS;
+
+ if (uclass_get_device(UCLASS_RNG, 0, &dev) || !dev) {
+ printf("No RNG device\n");
+ return CMD_RET_FAILURE;
+ }
+
+ buf = malloc(n);
+ if (!buf) {
+ printf("Out of memory\n");
+ return CMD_RET_FAILURE;
+ }
+
+ if (dm_rng_read(dev, buf, n)) {
+ printf("Reading RNG failed\n");
+ return CMD_RET_FAILURE;
+ }
+
+ if (!working_fdt) {
+ printf("No FDT memory address configured. Please configure\n"
+ "the FDT address via \"fdt addr <address>\" command.\n"
+ "Aborting!\n");
+ return CMD_RET_FAILURE;
+ }
+
+ ret = fdt_check_header(working_fdt);
+ if (ret < 0) {
+ printf("fdt_chosen: %s\n", fdt_strerror(ret));
+ return CMD_RET_FAILURE;
+ }
+
+ nodeoffset = fdt_find_or_add_subnode(working_fdt, 0, "chosen");
+ if (nodeoffset < 0) {
+ printf("Reading chosen node failed\n");
+ return CMD_RET_FAILURE;
+ }
+
+ ret = fdt_setprop(working_fdt, nodeoffset, "kaslr-seed", buf, sizeof(buf));
+ if (ret < 0) {
+ printf("Unable to set kaslr-seed on chosen node: %s\n", fdt_strerror(ret));
+ return CMD_RET_FAILURE;
+ }
+
+ free(buf);
+
+ return ret;
+}
+
+#ifdef CONFIG_SYS_LONGHELP
+static char kaslrseed_help_text[] =
+ "[n]\n"
+ " - append random bytes to chosen kaslr-seed node\n";
+#endif
+
+U_BOOT_CMD(
+ kaslrseed, 1, 0, do_kaslr_seed,
+ "feed bytes from the hardware random number generator to the kaslr-seed",
+ kaslrseed_help_text
+);
diff --git a/configs/bananapi-m5_defconfig b/configs/bananapi-m5_defconfig
index 7ca14a5..4bf81b2 100644
--- a/configs/bananapi-m5_defconfig
+++ b/configs/bananapi-m5_defconfig
@@ -25,7 +25,6 @@ CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_REGULATOR=y
CONFIG_OF_CONTROL=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_ADC=y
CONFIG_SARADC_MESON=y
CONFIG_MMC_MESON_GX=y
diff --git a/configs/beelink-gsking-x_defconfig b/configs/beelink-gsking-x_defconfig
index 54ac1c9..e60e754 100644
--- a/configs/beelink-gsking-x_defconfig
+++ b/configs/beelink-gsking-x_defconfig
@@ -26,7 +26,6 @@ CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_REGULATOR=y
CONFIG_OF_CONTROL=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_MMC_MESON_GX=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
diff --git a/configs/beelink-gtking_defconfig b/configs/beelink-gtking_defconfig
index 7735c70..2ec3221 100644
--- a/configs/beelink-gtking_defconfig
+++ b/configs/beelink-gtking_defconfig
@@ -26,7 +26,6 @@ CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_REGULATOR=y
CONFIG_OF_CONTROL=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_MMC_MESON_GX=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
diff --git a/configs/beelink-gtkingpro_defconfig b/configs/beelink-gtkingpro_defconfig
index 93c5739..60d316d 100644
--- a/configs/beelink-gtkingpro_defconfig
+++ b/configs/beelink-gtkingpro_defconfig
@@ -26,7 +26,6 @@ CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_REGULATOR=y
CONFIG_OF_CONTROL=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_MMC_MESON_GX=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
diff --git a/configs/evb-rk3568_defconfig b/configs/evb-rk3568_defconfig
index 5975d25..b07bcf9 100644
--- a/configs/evb-rk3568_defconfig
+++ b/configs/evb-rk3568_defconfig
@@ -2,21 +2,43 @@ CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00a00000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
-CONFIG_DEFAULT_DEVICE_TREE="rk3568-evb"
CONFIG_ROCKCHIP_RK3568=y
+CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
+CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL_STACK_R_ADDR=0x600000
CONFIG_TARGET_EVB_RK3568=y
CONFIG_DEBUG_UART_BASE=0xFE660000
CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEFAULT_DEVICE_TREE="rk3568-evb"
CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-evb.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_CRC32_SUPPORT=y
+CONFIG_SPL_ATF=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
# CONFIG_CMD_SETEXPR is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIVE=y
CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_SYSCON=y
+CONFIG_SPL_CLK=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_MISC=y
@@ -31,6 +53,7 @@ CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
CONFIG_REGULATOR_PWM=y
CONFIG_PWM_ROCKCHIP=y
+CONFIG_SPL_RAM=y
CONFIG_DM_RESET=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
diff --git a/configs/jethub_j80_defconfig b/configs/jethub_j80_defconfig
index ad6bec0..eb1e4c4 100644
--- a/configs/jethub_j80_defconfig
+++ b/configs/jethub_j80_defconfig
@@ -33,7 +33,6 @@ CONFIG_CMD_REGULATOR=y
CONFIG_PARTITION_TYPE_GUID=y
CONFIG_OF_CONTROL=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SARADC_MESON=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_MESON=y
diff --git a/configs/khadas-vim2_defconfig b/configs/khadas-vim2_defconfig
index c852f7f..81cff3c 100644
--- a/configs/khadas-vim2_defconfig
+++ b/configs/khadas-vim2_defconfig
@@ -29,7 +29,6 @@ CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_REGULATOR=y
CONFIG_OF_CONTROL=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SARADC_MESON=y
CONFIG_MMC_MESON_GX=y
CONFIG_MTD=y
diff --git a/configs/khadas-vim3_android_ab_defconfig b/configs/khadas-vim3_android_ab_defconfig
new file mode 100644
index 0000000..88325c3
--- /dev/null
+++ b/configs/khadas-vim3_android_ab_defconfig
@@ -0,0 +1,109 @@
+CONFIG_ARM=y
+CONFIG_SYS_BOARD="vim3"
+CONFIG_SYS_CONFIG_NAME="khadas-vim3_android"
+CONFIG_ARCH_MESON=y
+CONFIG_SYS_TEXT_BASE=0x01000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x10000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="meson-g12b-a311d-khadas-vim3"
+CONFIG_MESON_G12A=y
+CONFIG_DEBUG_UART_BASE=0xff803000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_IDENT_STRING=" khadas-vim3"
+CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x1000000
+CONFIG_OF_BOARD_SETUP=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_MISC_INIT_R=y
+CONFIG_AVB_VERIFY=y
+CONFIG_ANDROID_AB=y
+# CONFIG_CMD_BDI is not set
+CONFIG_CMD_ADTIMG=y
+CONFIG_CMD_ABOOTIMG=y
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_BCB=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_SF_TEST=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_AB_SELECT=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_AVB=y
+CONFIG_OF_CONTROL=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_ADC=y
+CONFIG_SARADC_MESON=y
+CONFIG_BUTTON=y
+CONFIG_BUTTON_ADC=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x6000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=2
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MESON=y
+CONFIG_MMC_MESON_GX=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
+CONFIG_DM_MDIO_MUX=y
+CONFIG_ETH_DESIGNWARE_MESON8B=y
+CONFIG_MDIO_MUX_MESON_G12A=y
+CONFIG_NVME=y
+CONFIG_PCI=y
+CONFIG_PCIE_DW_MESON=y
+CONFIG_MESON_G12A_USB_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_MESON_G12A=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_MESON_EE_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_RESET=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_MESON_SERIAL=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_MESON_SPIFC=y
+CONFIG_SYSINFO=y
+CONFIG_SYSINFO_SMBIOS=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+# CONFIG_USB_DWC3_GADGET is not set
+CONFIG_USB_DWC3_MESON_G12A=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e
+CONFIG_USB_GADGET_PRODUCT_NUM=0xfada
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_GADGET_DWC2_OTG_PHY_BUS_WIDTH_8=y
+CONFIG_DM_VIDEO=y
+# CONFIG_VIDEO_BPP8 is not set
+# CONFIG_VIDEO_BPP16 is not set
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_MESON=y
+CONFIG_VIDEO_DT_SIMPLEFB=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_VIDEO_BMP_RLE8=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_LIBAVB=y
+CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/khadas-vim3_android_defconfig b/configs/khadas-vim3_android_defconfig
new file mode 100644
index 0000000..9305a54
--- /dev/null
+++ b/configs/khadas-vim3_android_defconfig
@@ -0,0 +1,107 @@
+CONFIG_ARM=y
+CONFIG_SYS_BOARD="vim3"
+CONFIG_SYS_CONFIG_NAME="khadas-vim3_android"
+CONFIG_ARCH_MESON=y
+CONFIG_SYS_TEXT_BASE=0x01000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x10000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="meson-g12b-a311d-khadas-vim3"
+CONFIG_MESON_G12A=y
+CONFIG_DEBUG_UART_BASE=0xff803000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_IDENT_STRING=" khadas-vim3"
+CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x1000000
+CONFIG_OF_BOARD_SETUP=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_MISC_INIT_R=y
+CONFIG_AVB_VERIFY=y
+# CONFIG_CMD_BDI is not set
+CONFIG_CMD_ADTIMG=y
+CONFIG_CMD_ABOOTIMG=y
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_BCB=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_SF_TEST=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_AVB=y
+CONFIG_OF_CONTROL=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_ADC=y
+CONFIG_SARADC_MESON=y
+CONFIG_BUTTON=y
+CONFIG_BUTTON_ADC=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x6000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=2
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MESON=y
+CONFIG_MMC_MESON_GX=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
+CONFIG_DM_MDIO_MUX=y
+CONFIG_ETH_DESIGNWARE_MESON8B=y
+CONFIG_MDIO_MUX_MESON_G12A=y
+CONFIG_NVME=y
+CONFIG_PCI=y
+CONFIG_PCIE_DW_MESON=y
+CONFIG_MESON_G12A_USB_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_MESON_G12A=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_MESON_EE_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_RESET=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_MESON_SERIAL=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_MESON_SPIFC=y
+CONFIG_SYSINFO=y
+CONFIG_SYSINFO_SMBIOS=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+# CONFIG_USB_DWC3_GADGET is not set
+CONFIG_USB_DWC3_MESON_G12A=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e
+CONFIG_USB_GADGET_PRODUCT_NUM=0xfada
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_GADGET_DWC2_OTG_PHY_BUS_WIDTH_8=y
+CONFIG_DM_VIDEO=y
+# CONFIG_VIDEO_BPP8 is not set
+# CONFIG_VIDEO_BPP16 is not set
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_MESON=y
+CONFIG_VIDEO_DT_SIMPLEFB=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_VIDEO_BMP_RLE8=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_LIBAVB=y
+CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/khadas-vim3_defconfig b/configs/khadas-vim3_defconfig
index a225a56..65050ef 100644
--- a/configs/khadas-vim3_defconfig
+++ b/configs/khadas-vim3_defconfig
@@ -30,7 +30,6 @@ CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_REGULATOR=y
CONFIG_OF_CONTROL=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_ADC=y
CONFIG_SARADC_MESON=y
CONFIG_BUTTON=y
diff --git a/configs/khadas-vim3l_android_ab_defconfig b/configs/khadas-vim3l_android_ab_defconfig
new file mode 100644
index 0000000..608b54d
--- /dev/null
+++ b/configs/khadas-vim3l_android_ab_defconfig
@@ -0,0 +1,109 @@
+CONFIG_ARM=y
+CONFIG_SYS_BOARD="vim3"
+CONFIG_SYS_CONFIG_NAME="khadas-vim3l_android"
+CONFIG_ARCH_MESON=y
+CONFIG_SYS_TEXT_BASE=0x01000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x10000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="meson-sm1-khadas-vim3l"
+CONFIG_MESON_G12A=y
+CONFIG_DEBUG_UART_BASE=0xff803000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_IDENT_STRING=" khadas-vim3l"
+CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x1000000
+CONFIG_OF_BOARD_SETUP=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_MISC_INIT_R=y
+CONFIG_AVB_VERIFY=y
+CONFIG_ANDROID_AB=y
+# CONFIG_CMD_BDI is not set
+CONFIG_CMD_ADTIMG=y
+CONFIG_CMD_ABOOTIMG=y
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_BCB=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_SF_TEST=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_AB_SELECT=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_AVB=y
+CONFIG_OF_CONTROL=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_ADC=y
+CONFIG_SARADC_MESON=y
+CONFIG_BUTTON=y
+CONFIG_BUTTON_ADC=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x6000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=2
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MESON=y
+CONFIG_MMC_MESON_GX=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
+CONFIG_DM_MDIO_MUX=y
+CONFIG_ETH_DESIGNWARE_MESON8B=y
+CONFIG_MDIO_MUX_MESON_G12A=y
+CONFIG_NVME=y
+CONFIG_PCI=y
+CONFIG_PCIE_DW_MESON=y
+CONFIG_MESON_G12A_USB_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_MESON_G12A=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_MESON_EE_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_RESET=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_MESON_SERIAL=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_MESON_SPIFC=y
+CONFIG_SYSINFO=y
+CONFIG_SYSINFO_SMBIOS=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+# CONFIG_USB_DWC3_GADGET is not set
+CONFIG_USB_DWC3_MESON_G12A=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e
+CONFIG_USB_GADGET_PRODUCT_NUM=0xfada
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_GADGET_DWC2_OTG_PHY_BUS_WIDTH_8=y
+CONFIG_DM_VIDEO=y
+# CONFIG_VIDEO_BPP8 is not set
+# CONFIG_VIDEO_BPP16 is not set
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_MESON=y
+CONFIG_VIDEO_DT_SIMPLEFB=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_VIDEO_BMP_RLE8=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_LIBAVB=y
+CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/khadas-vim3l_android_defconfig b/configs/khadas-vim3l_android_defconfig
new file mode 100644
index 0000000..5eed79b
--- /dev/null
+++ b/configs/khadas-vim3l_android_defconfig
@@ -0,0 +1,107 @@
+CONFIG_ARM=y
+CONFIG_SYS_BOARD="vim3"
+CONFIG_SYS_CONFIG_NAME="khadas-vim3l_android"
+CONFIG_ARCH_MESON=y
+CONFIG_SYS_TEXT_BASE=0x01000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x10000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="meson-sm1-khadas-vim3l"
+CONFIG_MESON_G12A=y
+CONFIG_DEBUG_UART_BASE=0xff803000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_IDENT_STRING=" khadas-vim3l"
+CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x1000000
+CONFIG_OF_BOARD_SETUP=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_MISC_INIT_R=y
+CONFIG_AVB_VERIFY=y
+# CONFIG_CMD_BDI is not set
+CONFIG_CMD_ADTIMG=y
+CONFIG_CMD_ABOOTIMG=y
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_BCB=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_SF_TEST=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_AVB=y
+CONFIG_OF_CONTROL=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_ADC=y
+CONFIG_SARADC_MESON=y
+CONFIG_BUTTON=y
+CONFIG_BUTTON_ADC=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x6000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=2
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MESON=y
+CONFIG_MMC_MESON_GX=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
+CONFIG_DM_MDIO_MUX=y
+CONFIG_ETH_DESIGNWARE_MESON8B=y
+CONFIG_MDIO_MUX_MESON_G12A=y
+CONFIG_NVME=y
+CONFIG_PCI=y
+CONFIG_PCIE_DW_MESON=y
+CONFIG_MESON_G12A_USB_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_MESON_G12A=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_MESON_EE_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_RESET=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_MESON_SERIAL=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_MESON_SPIFC=y
+CONFIG_SYSINFO=y
+CONFIG_SYSINFO_SMBIOS=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+# CONFIG_USB_DWC3_GADGET is not set
+CONFIG_USB_DWC3_MESON_G12A=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e
+CONFIG_USB_GADGET_PRODUCT_NUM=0xfada
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_GADGET_DWC2_OTG_PHY_BUS_WIDTH_8=y
+CONFIG_DM_VIDEO=y
+# CONFIG_VIDEO_BPP8 is not set
+# CONFIG_VIDEO_BPP16 is not set
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_MESON=y
+CONFIG_VIDEO_DT_SIMPLEFB=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_VIDEO_BMP_RLE8=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_LIBAVB=y
+CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/khadas-vim3l_defconfig b/configs/khadas-vim3l_defconfig
index 9d94c31..b9162c9 100644
--- a/configs/khadas-vim3l_defconfig
+++ b/configs/khadas-vim3l_defconfig
@@ -30,7 +30,6 @@ CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_REGULATOR=y
CONFIG_OF_CONTROL=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_ADC=y
CONFIG_SARADC_MESON=y
CONFIG_BUTTON=y
diff --git a/configs/khadas-vim_defconfig b/configs/khadas-vim_defconfig
index 5565635..81eeff4 100644
--- a/configs/khadas-vim_defconfig
+++ b/configs/khadas-vim_defconfig
@@ -27,7 +27,6 @@ CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_REGULATOR=y
CONFIG_OF_CONTROL=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SARADC_MESON=y
CONFIG_MMC_MESON_GX=y
CONFIG_PHY_MESON_GXL=y
diff --git a/configs/libretech-ac_defconfig b/configs/libretech-ac_defconfig
index 7cddd32..945521b 100644
--- a/configs/libretech-ac_defconfig
+++ b/configs/libretech-ac_defconfig
@@ -34,7 +34,6 @@ CONFIG_CMD_REGULATOR=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SARADC_MESON=y
CONFIG_MMC_MESON_GX=y
CONFIG_MTD=y
diff --git a/configs/libretech-cc_defconfig b/configs/libretech-cc_defconfig
index b729308..b4413ed 100644
--- a/configs/libretech-cc_defconfig
+++ b/configs/libretech-cc_defconfig
@@ -26,7 +26,6 @@ CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_REGULATOR=y
CONFIG_OF_CONTROL=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SARADC_MESON=y
CONFIG_MMC_MESON_GX=y
CONFIG_PHY_MESON_GXL=y
diff --git a/configs/libretech-cc_v2_defconfig b/configs/libretech-cc_v2_defconfig
index 6e08f99..0dae223 100644
--- a/configs/libretech-cc_v2_defconfig
+++ b/configs/libretech-cc_v2_defconfig
@@ -30,7 +30,6 @@ CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SARADC_MESON=y
CONFIG_MMC_MESON_GX=y
CONFIG_MTD=y
diff --git a/configs/libretech-s905d-pc_defconfig b/configs/libretech-s905d-pc_defconfig
index 052b173..ca96191 100644
--- a/configs/libretech-s905d-pc_defconfig
+++ b/configs/libretech-s905d-pc_defconfig
@@ -32,7 +32,6 @@ CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_REGULATOR=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SARADC_MESON=y
CONFIG_MMC_MESON_GX=y
CONFIG_MTD=y
diff --git a/configs/libretech-s912-pc_defconfig b/configs/libretech-s912-pc_defconfig
index ee86ec9..02626cb 100644
--- a/configs/libretech-s912-pc_defconfig
+++ b/configs/libretech-s912-pc_defconfig
@@ -31,7 +31,6 @@ CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_REGULATOR=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SARADC_MESON=y
CONFIG_MMC_MESON_GX=y
CONFIG_MTD=y
diff --git a/configs/odroid-c4_defconfig b/configs/odroid-c4_defconfig
index bc778a6..1ea003f 100644
--- a/configs/odroid-c4_defconfig
+++ b/configs/odroid-c4_defconfig
@@ -26,7 +26,6 @@ CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_REGULATOR=y
CONFIG_OF_CONTROL=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_ADC=y
CONFIG_SARADC_MESON=y
CONFIG_MMC_MESON_GX=y
diff --git a/configs/odroid-hc4_defconfig b/configs/odroid-hc4_defconfig
index 2fe761e..d632670 100644
--- a/configs/odroid-hc4_defconfig
+++ b/configs/odroid-hc4_defconfig
@@ -29,7 +29,6 @@ CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_REGULATOR=y
CONFIG_OF_CONTROL=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_ADC=y
CONFIG_SARADC_MESON=y
CONFIG_SATA=y
diff --git a/configs/odroid-n2_defconfig b/configs/odroid-n2_defconfig
index 8e9e8f8..7f87504 100644
--- a/configs/odroid-n2_defconfig
+++ b/configs/odroid-n2_defconfig
@@ -26,7 +26,6 @@ CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_REGULATOR=y
CONFIG_OF_CONTROL=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_ADC=y
CONFIG_SARADC_MESON=y
CONFIG_MMC_MESON_GX=y
diff --git a/configs/p212_defconfig b/configs/p212_defconfig
index b1d2ca8..bca0fa8 100644
--- a/configs/p212_defconfig
+++ b/configs/p212_defconfig
@@ -25,7 +25,6 @@ CONFIG_CMD_USB=y
CONFIG_CMD_REGULATOR=y
CONFIG_OF_CONTROL=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_MMC_MESON_GX=y
CONFIG_PHY_MESON_GXL=y
CONFIG_DM_ETH=y
diff --git a/configs/px30-core-ctouch2-of10-px30_defconfig b/configs/px30-core-ctouch2-of10-px30_defconfig
new file mode 100644
index 0000000..664c977
--- /dev/null
+++ b/configs/px30-core-ctouch2-of10-px30_defconfig
@@ -0,0 +1,108 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SYS_TEXT_BASE=0x00200000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_DEFAULT_DEVICE_TREE="px30-engicam-px30-core-ctouch2-of10"
+CONFIG_SPL_TEXT_BASE=0x00000000
+CONFIG_ROCKCHIP_PX30=y
+CONFIG_TARGET_PX30_CORE=y
+CONFIG_DEBUG_UART_CHANNEL=1
+CONFIG_TPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_STACK_R_ADDR=0x600000
+CONFIG_DEBUG_UART_BASE=0xFF160000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART=y
+CONFIG_TPL_SYS_MALLOC_F_LEN=0x600
+CONFIG_SYS_LOAD_ADDR=0x800800
+# CONFIG_ANDROID_BOOT_IMAGE is not set
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/px30-engicam-px30-core-ctouch2-of10.dtb"
+# CONFIG_CONSOLE_MUX is not set
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_MISC_INIT_R=y
+CONFIG_SPL_BOOTROM_SUPPORT=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_STACK_R=y
+# CONFIG_TPL_BANNER_PRINT is not set
+CONFIG_SPL_ATF=y
+# CONFIG_TPL_FRAMEWORK is not set
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_LZMADEC is not set
+# CONFIG_CMD_UNZIP is not set
+CONFIG_CMD_GPT=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_ISO_PARTITION is not set
+CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIVE=y
+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_SYSCON=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_FASTBOOT_BUF_ADDR=0x800800
+CONFIG_FASTBOOT_BUF_SIZE=0x04000000
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MISC=y
+CONFIG_ROCKCHIP_OTP=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PINCTRL=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_RAM=y
+CONFIG_SPL_RAM=y
+CONFIG_TPL_RAM=y
+CONFIG_ROCKCHIP_SDRAM_COMMON=y
+CONFIG_DM_RESET=y
+CONFIG_DM_RNG=y
+CONFIG_RNG_ROCKCHIP=y
+# CONFIG_SPECIFY_CONSOLE_INDEX is not set
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_SOUND=y
+CONFIG_SYSRESET=y
+CONFIG_DM_THERMAL=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_DM_VIDEO=y
+CONFIG_DISPLAY=y
+CONFIG_LCD=y
+CONFIG_SPL_TINY_MEMSET=y
+CONFIG_TPL_TINY_MEMSET=y
+CONFIG_LZO=y
+CONFIG_ERRNO_STR=y
diff --git a/configs/px30-core-ctouch2-px30_defconfig b/configs/px30-core-ctouch2-px30_defconfig
index a5dbbd7..7d19204 100644
--- a/configs/px30-core-ctouch2-px30_defconfig
+++ b/configs/px30-core-ctouch2-px30_defconfig
@@ -6,7 +6,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
-CONFIG_DEFAULT_DEVICE_TREE="px30-px30-core-ctouch2"
+CONFIG_DEFAULT_DEVICE_TREE="px30-engicam-px30-core-ctouch2"
CONFIG_SPL_TEXT_BASE=0x00000000
CONFIG_ROCKCHIP_PX30=y
CONFIG_TARGET_PX30_CORE=y
@@ -23,7 +23,7 @@ CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
-CONFIG_DEFAULT_FDT_FILE="rockchip/px30-px30-core-ctouch2.dtb"
+CONFIG_DEFAULT_FDT_FILE="rockchip/px30-engicam-px30-core-ctouch2.dtb"
# CONFIG_CONSOLE_MUX is not set
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
diff --git a/configs/px30-core-edimm2.2-px30_defconfig b/configs/px30-core-edimm2.2-px30_defconfig
index 1e138d6..84c5733 100644
--- a/configs/px30-core-edimm2.2-px30_defconfig
+++ b/configs/px30-core-edimm2.2-px30_defconfig
@@ -6,7 +6,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
-CONFIG_DEFAULT_DEVICE_TREE="px30-px30-core-edimm2.2"
+CONFIG_DEFAULT_DEVICE_TREE="px30-engicam-px30-core-edimm2.2"
CONFIG_SPL_TEXT_BASE=0x00000000
CONFIG_ROCKCHIP_PX30=y
CONFIG_TARGET_PX30_CORE=y
@@ -23,7 +23,7 @@ CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
-CONFIG_DEFAULT_FDT_FILE="rockchip/px30-px30-core-edimm2.2.dtb"
+CONFIG_DEFAULT_FDT_FILE="rockchip/px30-engicam-px30-core-edimm2.2.dtb"
# CONFIG_CONSOLE_MUX is not set
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
diff --git a/configs/rock-pi-4-rk3399_defconfig b/configs/rock-pi-4-rk3399_defconfig
index 9366eba..032b908 100644
--- a/configs/rock-pi-4-rk3399_defconfig
+++ b/configs/rock-pi-4-rk3399_defconfig
@@ -31,6 +31,7 @@ CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ROCKCHIP_GPIO=y
+CONFIG_ROCKCHIP_EFUSE=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_MISC=y
CONFIG_MMC_DW=y
diff --git a/configs/rock-pi-4c-rk3399_defconfig b/configs/rock-pi-4c-rk3399_defconfig
index ac045d1..6f5e866 100644
--- a/configs/rock-pi-4c-rk3399_defconfig
+++ b/configs/rock-pi-4c-rk3399_defconfig
@@ -31,6 +31,7 @@ CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ROCKCHIP_GPIO=y
+CONFIG_ROCKCHIP_EFUSE=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_MISC=y
CONFIG_MMC_DW=y
diff --git a/configs/s400_defconfig b/configs/s400_defconfig
index 4467e66..8483694 100644
--- a/configs/s400_defconfig
+++ b/configs/s400_defconfig
@@ -25,7 +25,6 @@ CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_REGULATOR=y
CONFIG_OF_CONTROL=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_MMC_MESON_GX=y
CONFIG_PHY_REALTEK=y
CONFIG_DM_ETH=y
diff --git a/configs/sei510_defconfig b/configs/sei510_defconfig
index 690a0ca..5e2496e 100644
--- a/configs/sei510_defconfig
+++ b/configs/sei510_defconfig
@@ -43,7 +43,6 @@ CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_DEV=2
CONFIG_SYS_MMC_ENV_PART=1
-CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x6000000
CONFIG_FASTBOOT_FLASH=y
diff --git a/configs/sei610_defconfig b/configs/sei610_defconfig
index 63080ae..df53c91 100644
--- a/configs/sei610_defconfig
+++ b/configs/sei610_defconfig
@@ -43,7 +43,6 @@ CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_DEV=2
CONFIG_SYS_MMC_ENV_PART=1
-CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x6000000
CONFIG_FASTBOOT_FLASH=y
diff --git a/configs/u200_defconfig b/configs/u200_defconfig
index 144c394..7f46dcf 100644
--- a/configs/u200_defconfig
+++ b/configs/u200_defconfig
@@ -25,7 +25,6 @@ CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_REGULATOR=y
CONFIG_OF_CONTROL=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_MMC_MESON_GX=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
diff --git a/configs/wetek-core2_defconfig b/configs/wetek-core2_defconfig
index ce947b5..006cebc 100644
--- a/configs/wetek-core2_defconfig
+++ b/configs/wetek-core2_defconfig
@@ -26,7 +26,6 @@ CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_REGULATOR=y
CONFIG_OF_CONTROL=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SARADC_MESON=y
CONFIG_MMC_MESON_GX=y
CONFIG_MTD=y
diff --git a/doc/README.rockchip b/doc/README.rockchip
index 154166e..52b5140 100644
--- a/doc/README.rockchip
+++ b/doc/README.rockchip
@@ -81,30 +81,19 @@ Building
- Compile ATF
- For Puma board.
+ => git clone https://github.com/ARM-software/arm-trusted-firmware.git
+ => cd arm-trusted-firmware
- => git clone git://git.theobroma-systems.com/arm-trusted-firmware.git
- => cd arm-trusted-firmware
- => make CROSS_COMPILE=aarch64-linux-gnu- PLAT=rk3399 bl31
+ (export cross compiler path for Cortex-M0 MCU likely arm-none-eabi-)
+ => make realclean
+ => make CROSS_COMPILE=aarch64-linux-gnu- PLAT=rk3399
- (export bl31.bin)
- => export BL31=/path/to/arm-trusted-firmware/build/rk3399/release/bl31/bl31.bin
-
- For rest of rk3399 boards.
-
- => git clone https://github.com/ARM-software/arm-trusted-firmware.git
- => cd arm-trusted-firmware
-
- (export cross compiler path for Cortex-M0 MCU likely arm-none-eabi-)
- => make realclean
- => make CROSS_COMPILE=aarch64-linux-gnu- PLAT=rk3399
-
- (export bl31.elf)
- => export BL31=/path/to/arm-trusted-firmware/build/rk3399/release/bl31/bl31.elf
+ (export bl31.elf)
+ => export BL31=/path/to/arm-trusted-firmware/build/rk3399/release/bl31/bl31.elf
- Compile PMU M0 firmware
- This is optional for most of the rk3399 boards and required only for Puma board.
+ This is optional for most of the rk3399 boards.
=> git clone git://git.theobroma-systems.com/rk3399-cortex-m0.git
=> cd rk3399-cortex-m0
diff --git a/doc/develop/uefi/uefi.rst b/doc/develop/uefi/uefi.rst
index a3e2656..43fb10f 100644
--- a/doc/develop/uefi/uefi.rst
+++ b/doc/develop/uefi/uefi.rst
@@ -248,9 +248,9 @@ OP-TEE Build instructions
$ export ARCH=arm
$ CROSS_COMPILE32=arm-linux-gnueabihf- make -j32 CFG_ARM64_core=y \
PLATFORM=<myboard> CFG_STMM_PATH=BL32_AP_MM.fd CFG_RPMB_FS=y \
- CFG_RPMB_FS_DEV_ID=0 CFG_CORE_HEAP_SIZE=524288 CFG_RPMB_WRITE_KEY=1 \
- CFG_CORE_HEAP_SIZE=524288 CFG_CORE_DYN_SHM=y CFG_RPMB_TESTKEY=y \
- CFG_REE_FS=n CFG_CORE_ARM64_PA_BITS=48 CFG_TEE_CORE_LOG_LEVEL=1 \
+ CFG_RPMB_FS_DEV_ID=0 CFG_CORE_HEAP_SIZE=524288 CFG_RPMB_WRITE_KEY=y \
+ CFG_CORE_DYN_SHM=y CFG_RPMB_TESTKEY=y CFG_REE_FS=n \
+ CFG_CORE_ARM64_PA_BITS=48 CFG_TEE_CORE_LOG_LEVEL=1 \
CFG_TEE_TA_LOG_LEVEL=1 CFG_SCTLR_ALIGNMENT_CHECK=n
U-Boot Build instructions
diff --git a/drivers/mtd/spi/Kconfig b/drivers/mtd/spi/Kconfig
index 0969c03..f350c7e 100644
--- a/drivers/mtd/spi/Kconfig
+++ b/drivers/mtd/spi/Kconfig
@@ -129,12 +129,6 @@ config SPI_FLASH_UNLOCK_ALL
For legacy reasons, this option default to y. But if you intend to
actually use the software protection bits you should say n here.
-config SF_DUAL_FLASH
- bool "SPI DUAL flash memory support"
- help
- Enable this option to support two flash memories connected to a single
- controller. Currently Xilinx Zynq qspi supports this.
-
config SPI_FLASH_ATMEL
bool "Atmel SPI flash support"
help
diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
index 3ae7bb1..b551ebd 100644
--- a/drivers/mtd/spi/spi-nor-ids.c
+++ b/drivers/mtd/spi/spi-nor-ids.c
@@ -355,6 +355,11 @@ const struct flash_info spi_nor_ids[] = {
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
},
+ {
+ INFO("w25q01jv", 0xef4021, 0, 64 * 1024, 2048,
+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
+ SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
+ },
{ INFO("w25q80", 0xef5014, 0, 64 * 1024, 16, SECT_4K) },
{ INFO("w25q80bl", 0xef4014, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ INFO("w25q16cl", 0xef4015, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
diff --git a/drivers/power/pmic/Kconfig b/drivers/power/pmic/Kconfig
index b9fda42..ce0adb1 100644
--- a/drivers/power/pmic/Kconfig
+++ b/drivers/power/pmic/Kconfig
@@ -128,6 +128,20 @@ config DM_PMIC_FAN53555
The driver implements read/write operations for use with the FAN53555
regulator driver and binds the regulator driver to its node.
+config SPL_DM_PMIC_FAN53555
+ bool "Enable support for OnSemi FAN53555 in SPL"
+ depends on SPL_DM_REGULATOR && SPL_DM_I2C
+ select SPL_DM_REGULATOR_FAN53555
+ help
+ This config enables implementation of driver-model PMIC
+ uclass features for the FAN53555 regulator. The FAN53555 is
+ a (family of) single-output regulators that supports
+ transitioning between two different output voltages based on
+ an voltage selection pin.
+
+ The driver implements read/write operations for use with the FAN53555
+ regulator driver and binds the regulator driver to its node.
+
config DM_PMIC_MP5416
bool "Enable Driver Model for PMIC MP5416"
help
diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile
index e1922df..401cde3 100644
--- a/drivers/power/pmic/Makefile
+++ b/drivers/power/pmic/Makefile
@@ -4,7 +4,7 @@
# Lukasz Majewski <l.majewski@samsung.com>
obj-$(CONFIG_$(SPL_TPL_)DM_PMIC) += pmic-uclass.o
-obj-$(CONFIG_DM_PMIC_FAN53555) += fan53555.o
+obj-$(CONFIG_$(SPL_)DM_PMIC_FAN53555) += fan53555.o
obj-$(CONFIG_$(SPL_)DM_PMIC_DA9063) += da9063.o
obj-$(CONFIG_DM_PMIC_MAX77686) += max77686.o
obj-$(CONFIG_DM_PMIC_MAX8998) += max8998.o
diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
index 429ee33..2cdf4c9 100644
--- a/drivers/spi/cadence_qspi_apb.c
+++ b/drivers/spi/cadence_qspi_apb.c
@@ -858,6 +858,14 @@ cadence_qspi_apb_indirect_read_execute(struct cadence_spi_plat *plat,
writel(CQSPI_REG_INDIRECTRD_DONE,
plat->regbase + CQSPI_REG_INDIRECTRD);
+ /* Check indirect done status */
+ ret = wait_for_bit_le32(plat->regbase + CQSPI_REG_INDIRECTRD,
+ CQSPI_REG_INDIRECTRD_DONE, 0, 10, 0);
+ if (ret) {
+ printf("Indirect read clear completion error (%i)\n", ret);
+ goto failrd;
+ }
+
return 0;
failrd:
@@ -1012,6 +1020,15 @@ cadence_qspi_apb_indirect_write_execute(struct cadence_spi_plat *plat,
/* Clear indirect completion status */
writel(CQSPI_REG_INDIRECTWR_DONE,
plat->regbase + CQSPI_REG_INDIRECTWR);
+
+ /* Check indirect done status */
+ ret = wait_for_bit_le32(plat->regbase + CQSPI_REG_INDIRECTWR,
+ CQSPI_REG_INDIRECTWR_DONE, 0, 10, 0);
+ if (ret) {
+ printf("Indirect write clear completion error (%i)\n", ret);
+ goto failwr;
+ }
+
if (bounce_buf)
free(bounce_buf);
return 0;
diff --git a/drivers/sysreset/sysreset_watchdog.c b/drivers/sysreset/sysreset_watchdog.c
index 35efcac..8a659ee 100644
--- a/drivers/sysreset/sysreset_watchdog.c
+++ b/drivers/sysreset/sysreset_watchdog.c
@@ -20,9 +20,16 @@ static int wdt_reboot_request(struct udevice *dev, enum sysreset_t type)
struct wdt_reboot_plat *plat = dev_get_plat(dev);
int ret;
- ret = wdt_expire_now(plat->wdt, 0);
- if (ret)
- return ret;
+ switch (type) {
+ case SYSRESET_COLD:
+ case SYSRESET_WARM:
+ ret = wdt_expire_now(plat->wdt, 0);
+ if (ret)
+ return ret;
+ break;
+ default:
+ return -ENOSYS;
+ }
return -EINPROGRESS;
}
diff --git a/drivers/video/mxsfb.c b/drivers/video/mxsfb.c
index 98d2965..5f85c0c 100644
--- a/drivers/video/mxsfb.c
+++ b/drivers/video/mxsfb.c
@@ -89,7 +89,7 @@ static void mxs_lcd_init(struct udevice *dev, u32 fb_addr,
}
ret = clk_get_by_name(dev, "axi", &clk);
- if (!ret) {
+ if (ret < 0) {
debug("%s: Failed to get mxs axi clk: %d\n", __func__, ret);
} else {
ret = clk_enable(&clk);
@@ -100,7 +100,7 @@ static void mxs_lcd_init(struct udevice *dev, u32 fb_addr,
}
ret = clk_get_by_name(dev, "disp_axi", &clk);
- if (!ret) {
+ if (ret < 0) {
debug("%s: Failed to get mxs disp_axi clk: %d\n", __func__, ret);
} else {
ret = clk_enable(&clk);
diff --git a/include/configs/khadas-vim3_android.h b/include/configs/khadas-vim3_android.h
new file mode 100644
index 0000000..da6adf6
--- /dev/null
+++ b/include/configs/khadas-vim3_android.h
@@ -0,0 +1,50 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuration for the khadas VIM3 Android
+ *
+ * Copyright (C) 2021 Baylibre, SAS
+ * Author: Guillaume LA ROQUE <glaroque@baylibre.com>
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define LOGO_UUID "43a3305d-150f-4cc9-bd3b-38fca8693846;"
+#define ROOT_UUID "ddb8c3f6-d94d-4394-b633-3134139cc2e0;"
+
+#if defined(CONFIG_CMD_AB_SELECT)
+#define PARTS_DEFAULT \
+ "uuid_disk=${uuid_gpt_disk};" \
+ "name=logo,start=512K,size=2M,uuid=" LOGO_UUID \
+ "name=misc,size=512K,uuid=${uuid_gpt_misc};" \
+ "name=dtbo_a,size=8M,uuid=${uuid_gpt_dtbo_a};" \
+ "name=dtbo_b,size=8M,uuid=${uuid_gpt_dtbo_b};" \
+ "name=vbmeta_a,size=512K,uuid=${uuid_gpt_vbmeta_a};" \
+ "name=vbmeta_b,size=512K,uuid=${uuid_gpt_vbmeta_b};" \
+ "name=boot_a,size=32M,bootable,uuid=${uuid_gpt_boot_a};" \
+ "name=boot_b,size=32M,bootable,uuid=${uuid_gpt_boot_b};" \
+ "name=super,size=3072M,uuid=${uuid_gpt_super};" \
+ "name=userdata,size=11282M,uuid=${uuid_gpt_userdata};" \
+ "name=rootfs,size=-,uuid=" ROOT_UUID
+#else
+#define PARTS_DEFAULT \
+ "uuid_disk=${uuid_gpt_disk};" \
+ "name=logo,start=512K,size=2M,uuid=" LOGO_UUID \
+ "name=misc,size=512K,uuid=${uuid_gpt_misc};" \
+ "name=dtbo,size=8M,uuid=${uuid_gpt_dtbo};" \
+ "name=vbmeta,size=512K,uuid=${uuid_gpt_vbmeta};" \
+ "name=boot,size=32M,bootable,uuid=${uuid_gpt_boot};" \
+ "name=recovery,size=32M,uuid=${uuid_gpt_recovery};" \
+ "name=cache,size=256M,uuid=${uuid_gpt_cache};" \
+ "name=super,size=1792M,uuid=${uuid_gpt_super};" \
+ "name=userdata,size=12786M,uuid=${uuid_gpt_userdata};" \
+ "name=rootfs,size=-,uuid=" ROOT_UUID
+#endif
+
+#define EXTRA_ANDROID_ENV_SETTINGS \
+ "board=vim3\0" \
+ "board_name=vim3\0" \
+
+#include <configs/meson64_android.h>
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/khadas-vim3l_android.h b/include/configs/khadas-vim3l_android.h
new file mode 100644
index 0000000..b1768e2
--- /dev/null
+++ b/include/configs/khadas-vim3l_android.h
@@ -0,0 +1,50 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuration for the khadas VIM3L Android
+ *
+ * Copyright (C) 2021 Baylibre, SAS
+ * Author: Guillaume LA ROQUE <glaroque@baylibre.com>
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define LOGO_UUID "43a3305d-150f-4cc9-bd3b-38fca8693846;"
+#define ROOT_UUID "ddb8c3f6-d94d-4394-b633-3134139cc2e0;"
+
+#if defined(CONFIG_CMD_AB_SELECT)
+#define PARTS_DEFAULT \
+ "uuid_disk=${uuid_gpt_disk};" \
+ "name=logo,start=512K,size=2M,uuid=" LOGO_UUID \
+ "name=misc,size=512K,uuid=${uuid_gpt_misc};" \
+ "name=dtbo_a,size=8M,uuid=${uuid_gpt_dtbo_a};" \
+ "name=dtbo_b,size=8M,uuid=${uuid_gpt_dtbo_b};" \
+ "name=vbmeta_a,size=512K,uuid=${uuid_gpt_vbmeta_a};" \
+ "name=vbmeta_b,size=512K,uuid=${uuid_gpt_vbmeta_b};" \
+ "name=boot_a,size=32M,bootable,uuid=${uuid_gpt_boot_a};" \
+ "name=boot_b,size=32M,bootable,uuid=${uuid_gpt_boot_b};" \
+ "name=super,size=3072M,uuid=${uuid_gpt_super};" \
+ "name=userdata,size=11282M,uuid=${uuid_gpt_userdata};" \
+ "name=rootfs,size=-,uuid=" ROOT_UUID
+#else
+#define PARTS_DEFAULT \
+ "uuid_disk=${uuid_gpt_disk};" \
+ "name=logo,start=512K,size=2M,uuid=" LOGO_UUID \
+ "name=misc,size=512K,uuid=${uuid_gpt_misc};" \
+ "name=dtbo,size=8M,uuid=${uuid_gpt_dtbo};" \
+ "name=vbmeta,size=512K,uuid=${uuid_gpt_vbmeta};" \
+ "name=boot,size=32M,bootable,uuid=${uuid_gpt_boot};" \
+ "name=recovery,size=32M,uuid=${uuid_gpt_recovery};" \
+ "name=cache,size=256M,uuid=${uuid_gpt_cache};" \
+ "name=super,size=1792M,uuid=${uuid_gpt_super};" \
+ "name=userdata,size=12786M,uuid=${uuid_gpt_userdata};" \
+ "name=rootfs,size=-,uuid=" ROOT_UUID
+#endif
+
+#define EXTRA_ANDROID_ENV_SETTINGS \
+ "board=vim3l\0" \
+ "board_name=vim3l\0" \
+
+#include <configs/meson64_android.h>
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/meson64_android.h b/include/configs/meson64_android.h
index 7cd1ab0..0303d18 100644
--- a/include/configs/meson64_android.h
+++ b/include/configs/meson64_android.h
@@ -23,6 +23,10 @@
#define CONTROL_PARTITION "misc"
#endif
+#ifndef EXTRA_ANDROID_ENV_SETTINGS
+#define EXTRA_ANDROID_ENV_SETTINGS ""
+#endif
+
#if defined(CONFIG_CMD_AVB)
#define AVB_VERIFY_CHECK \
"if test \"${force_avb}\" -eq 1; then " \
@@ -100,6 +104,12 @@
"elif test $board_name = sei610; then " \
"echo \" Reading DTB for sei610...\"; " \
"setenv dtb_index 1;" \
+ "elif test $board_name = vim3l; then " \
+ "echo \" Reading DTB for vim3l...\"; " \
+ "setenv dtb_index 2;" \
+ "elif test $board_name = vim3; then " \
+ "echo \" Reading DTB for vim3...\"; " \
+ "setenv dtb_index 3;" \
"else " \
"echo Error: Android boot is not supported for $board_name; " \
"exit; " \
@@ -113,6 +123,12 @@
"elif test $board_name = sei610; then " \
"echo \" Reading DTBO for sei610...\"; " \
"setenv dtbo_index 1;" \
+ "elif test $board_name = vim3l; then " \
+ "echo \" Reading DTBO for vim3l...\"; " \
+ "setenv dtbo_index 2;" \
+ "elif test $board_name = vim3; then " \
+ "echo \" Reading DTBO for vim3...\"; " \
+ "setenv dtbo_index 3;" \
"else " \
"echo Error: Android boot is not supported for $board_name; " \
"exit; " \
@@ -264,6 +280,7 @@
"fi;"
#define CONFIG_EXTRA_ENV_SETTINGS \
+ EXTRA_ANDROID_ENV_SETTINGS \
"partitions=" PARTS_DEFAULT "\0" \
"mmcdev=2\0" \
ANDROIDBOOT_GET_CURRENT_SLOT_CMD \
diff --git a/include/configs/rk3568_common.h b/include/configs/rk3568_common.h
index afe5050..25d7c5c 100644
--- a/include/configs/rk3568_common.h
+++ b/include/configs/rk3568_common.h
@@ -16,6 +16,12 @@
#define CONFIG_IRAM_BASE 0xfdcc0000
#define CONFIG_SYS_INIT_SP_ADDR 0x00c00000
+
+#define CONFIG_SPL_STACK 0x00400000
+#define CONFIG_SPL_MAX_SIZE 0x20000
+#define CONFIG_SPL_BSS_START_ADDR 0x4000000
+#define CONFIG_SPL_BSS_MAX_SIZE 0x4000
+
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */
#define CONFIG_SYS_SDRAM_BASE 0
diff --git a/lib/aes/aes-encrypt.c b/lib/aes/aes-encrypt.c
index a6d1720..e74e35e 100644
--- a/lib/aes/aes-encrypt.c
+++ b/lib/aes/aes-encrypt.c
@@ -2,6 +2,9 @@
/*
* Copyright (c) 2019,Softathome
*/
+
+#define OPENSSL_API_COMPAT 0x10101000L
+
#include "mkimage.h"
#include <stdio.h>
#include <string.h>
diff --git a/lib/ecdsa/ecdsa-libcrypto.c b/lib/ecdsa/ecdsa-libcrypto.c
index 1757a14..ae6dfa0 100644
--- a/lib/ecdsa/ecdsa-libcrypto.c
+++ b/lib/ecdsa/ecdsa-libcrypto.c
@@ -18,6 +18,8 @@
* Copyright (c) 2020,2021, Alexandru Gagniuc <mr.nuke.me@gmail.com>
*/
+#define OPENSSL_API_COMPAT 0x10101000L
+
#include <u-boot/ecdsa.h>
#include <u-boot/fdt-libcrypto.h>
#include <openssl/ssl.h>
diff --git a/lib/rsa/rsa-sign.c b/lib/rsa/rsa-sign.c
index 0579e52..44f2141 100644
--- a/lib/rsa/rsa-sign.c
+++ b/lib/rsa/rsa-sign.c
@@ -3,6 +3,8 @@
* Copyright (c) 2013, Google Inc.
*/
+#define OPENSSL_API_COMPAT 0x10101000L
+
#include "mkimage.h"
#include <stdlib.h>
#include <stdio.h>
diff --git a/tools/kwbimage.c b/tools/kwbimage.c
index 875f636..224d815 100644
--- a/tools/kwbimage.c
+++ b/tools/kwbimage.c
@@ -8,6 +8,8 @@
* <thomas.petazzoni@free-electrons.com>
*/
+#define OPENSSL_API_COMPAT 0x10101000L
+
#include "imagetool.h"
#include <limits.h>
#include <image.h>
@@ -1398,9 +1400,6 @@ static void *image_create_v1(size_t *imagesz, struct image_tool_params *params,
headersz, image, secure_hdr))
return NULL;
- /* Calculate and set the header checksum */
- main_hdr->checksum = image_checksum8(main_hdr, headersz);
-
*imagesz = headersz;
/* Fill the real header size without padding into the main header */
@@ -1410,6 +1409,9 @@ static void *image_create_v1(size_t *imagesz, struct image_tool_params *params,
main_hdr->headersz_lsb = cpu_to_le16(headersz & 0xFFFF);
main_hdr->headersz_msb = (headersz & 0xFFFF0000) >> 16;
+ /* Calculate and set the header checksum */
+ main_hdr->checksum = image_checksum8(main_hdr, headersz);
+
return image;
}
diff --git a/tools/rkcommon.c b/tools/rkcommon.c
index d55cd2c..29f2676 100644
--- a/tools/rkcommon.c
+++ b/tools/rkcommon.c
@@ -10,12 +10,67 @@
#include "imagetool.h"
#include <image.h>
+#include <u-boot/sha256.h>
#include <rc4.h>
#include "mkimage.h"
#include "rkcommon.h"
enum {
- RK_SIGNATURE = 0x0ff0aa55,
+ RK_MAGIC = 0x0ff0aa55,
+ RK_MAGIC_V2 = 0x534E4B52,
+};
+
+enum {
+ RK_HEADER_V1 = 1,
+ RK_HEADER_V2 = 2,
+};
+
+enum hash_type {
+ HASH_NONE = 0,
+ HASH_SHA256 = 1,
+ HASH_SHA512 = 2,
+};
+
+/**
+ * struct image_entry
+ *
+ * @size_and_off: [31:16]image size;[15:0]image offset
+ * @address: default as 0xFFFFFFFF
+ * @flag: no use
+ * @counter: no use
+ * @hash: hash of image
+ *
+ */
+struct image_entry {
+ uint32_t size_and_off;
+ uint32_t address;
+ uint32_t flag;
+ uint32_t counter;
+ uint8_t reserved[8];
+ uint8_t hash[64];
+};
+
+/**
+ * struct header0_info_v2 - v2 header block for rockchip BootRom
+ *
+ * This is stored at SD card block 64 (where each block is 512 bytes)
+ *
+ * @magic: Magic (must be RK_MAGIC_V2)
+ * @size_and_nimage: [31:16]number of images;[15:0]
+ * offset to hash field of header(unit as 4Byte)
+ * @boot_flag: [3:0]hash type(0:none,1:sha256,2:sha512)
+ * @signature: hash or signature for header info
+ *
+ */
+struct header0_info_v2 {
+ uint32_t magic;
+ uint8_t reserved[4];
+ uint32_t size_and_nimage;
+ uint32_t boot_flag;
+ uint8_t reserved1[104];
+ struct image_entry images[4];
+ uint8_t reserved2[1064];
+ uint8_t hash[512];
};
/**
@@ -24,14 +79,14 @@ enum {
* This is stored at SD card block 64 (where each block is 512 bytes, or at
* the start of SPI flash. It is encoded with RC4.
*
- * @signature: Signature (must be RKSD_SIGNATURE)
+ * @magic: Magic (must be RK_MAGIC)
* @disable_rc4: 0 to use rc4 for boot image, 1 to use plain binary
* @init_offset: Offset in blocks of the SPL code from this header
* block. E.g. 4 means 2KB after the start of this header.
* Other fields are not used by U-Boot
*/
struct header0_info {
- uint32_t signature;
+ uint32_t magic;
uint8_t reserved[4];
uint32_t disable_rc4;
uint16_t init_offset;
@@ -55,27 +110,29 @@ struct header1_info {
* @spl_hdr: Boot ROM requires a 4-bytes spl header
* @spl_size: Spl size(include extra 4-bytes spl header)
* @spl_rc4: RC4 encode the SPL binary (same key as header)
+ * @header_ver: header block version
*/
-
struct spl_info {
const char *imagename;
const char *spl_hdr;
const uint32_t spl_size;
const bool spl_rc4;
+ const uint32_t header_ver;
};
static struct spl_info spl_infos[] = {
- { "px30", "RK33", 0x2800, false },
- { "rk3036", "RK30", 0x1000, false },
- { "rk3128", "RK31", 0x1800, false },
- { "rk3188", "RK31", 0x8000 - 0x800, true },
- { "rk322x", "RK32", 0x8000 - 0x1000, false },
- { "rk3288", "RK32", 0x8000, false },
- { "rk3308", "RK33", 0x40000 - 0x1000, false},
- { "rk3328", "RK32", 0x8000 - 0x1000, false },
- { "rk3368", "RK33", 0x8000 - 0x1000, false },
- { "rk3399", "RK33", 0x30000 - 0x2000, false },
- { "rv1108", "RK11", 0x1800, false },
+ { "px30", "RK33", 0x2800, false, RK_HEADER_V1 },
+ { "rk3036", "RK30", 0x1000, false, RK_HEADER_V1 },
+ { "rk3128", "RK31", 0x1800, false, RK_HEADER_V1 },
+ { "rk3188", "RK31", 0x8000 - 0x800, true, RK_HEADER_V1 },
+ { "rk322x", "RK32", 0x8000 - 0x1000, false, RK_HEADER_V1 },
+ { "rk3288", "RK32", 0x8000, false, RK_HEADER_V1 },
+ { "rk3308", "RK33", 0x40000 - 0x1000, false, RK_HEADER_V1 },
+ { "rk3328", "RK32", 0x8000 - 0x1000, false, RK_HEADER_V1 },
+ { "rk3368", "RK33", 0x8000 - 0x1000, false, RK_HEADER_V1 },
+ { "rk3399", "RK33", 0x30000 - 0x2000, false, RK_HEADER_V1 },
+ { "rv1108", "RK11", 0x1800, false, RK_HEADER_V1 },
+ { "rk3568", "RK35", 0x14000 - 0x1000, false, RK_HEADER_V2 },
};
/**
@@ -197,7 +254,6 @@ const char *rkcommon_get_spl_hdr(struct image_tool_params *params)
return info->spl_hdr;
}
-
int rkcommon_get_spl_size(struct image_tool_params *params)
{
struct spl_info *info = rkcommon_get_spl_info(params->imagename);
@@ -218,13 +274,29 @@ bool rkcommon_need_rc4_spl(struct image_tool_params *params)
return info->spl_rc4;
}
+bool rkcommon_is_header_v2(struct image_tool_params *params)
+{
+ struct spl_info *info = rkcommon_get_spl_info(params->imagename);
+
+ return (info->header_ver == RK_HEADER_V2);
+}
+
+static void do_sha256_hash(uint8_t *buf, uint32_t size, uint8_t *out)
+{
+ sha256_context ctx;
+
+ sha256_starts(&ctx);
+ sha256_update(&ctx, buf, size);
+ sha256_finish(&ctx, out);
+}
+
static void rkcommon_set_header0(void *buf, struct image_tool_params *params)
{
struct header0_info *hdr = buf;
uint32_t init_boot_size;
memset(buf, '\0', RK_INIT_OFFSET * RK_BLK_SIZE);
- hdr->signature = cpu_to_le32(RK_SIGNATURE);
+ hdr->magic = cpu_to_le32(RK_MAGIC);
hdr->disable_rc4 = cpu_to_le32(!rkcommon_need_rc4_spl(params));
hdr->init_offset = cpu_to_le16(RK_INIT_OFFSET);
hdr->init_size = cpu_to_le16(spl_params.init_size / RK_BLK_SIZE);
@@ -246,29 +318,67 @@ static void rkcommon_set_header0(void *buf, struct image_tool_params *params)
rc4_encode(buf, RK_BLK_SIZE, rc4_key);
}
+static void rkcommon_set_header0_v2(void *buf, struct image_tool_params *params)
+{
+ struct header0_info_v2 *hdr = buf;
+ uint32_t sector_offset, image_sector_count;
+ uint32_t image_size_array[2];
+ uint8_t *image_ptr = NULL;
+ int i;
+
+ printf("Image Type: Rockchip %s boot image\n",
+ rkcommon_get_spl_hdr(params));
+ memset(buf, '\0', RK_INIT_OFFSET * RK_BLK_SIZE);
+ hdr->magic = cpu_to_le32(RK_MAGIC_V2);
+ hdr->size_and_nimage = cpu_to_le32((2 << 16) + 384);
+ hdr->boot_flag = cpu_to_le32(HASH_SHA256);
+ sector_offset = 4;
+ image_size_array[0] = spl_params.init_size;
+ image_size_array[1] = spl_params.boot_size;
+
+ for (i = 0; i < 2; i++) {
+ image_sector_count = image_size_array[i] / RK_BLK_SIZE;
+ hdr->images[i].size_and_off = cpu_to_le32((image_sector_count
+ << 16) + sector_offset);
+ hdr->images[i].address = 0xFFFFFFFF;
+ hdr->images[i].counter = cpu_to_le32(i + 1);
+ image_ptr = buf + sector_offset * RK_BLK_SIZE;
+ do_sha256_hash(image_ptr, image_size_array[i],
+ hdr->images[i].hash);
+ sector_offset = sector_offset + image_sector_count;
+ }
+
+ do_sha256_hash(buf, (void *)hdr->hash - buf, hdr->hash);
+}
+
void rkcommon_set_header(void *buf, struct stat *sbuf, int ifd,
struct image_tool_params *params)
{
struct header1_info *hdr = buf + RK_SPL_HDR_START;
- rkcommon_set_header0(buf, params);
-
- /* Set up the SPL name (i.e. copy spl_hdr over) */
- memcpy(&hdr->magic, rkcommon_get_spl_hdr(params), RK_SPL_HDR_SIZE);
+ if (rkcommon_is_header_v2(params)) {
+ rkcommon_set_header0_v2(buf, params);
+ } else {
+ rkcommon_set_header0(buf, params);
- if (rkcommon_need_rc4_spl(params))
- rkcommon_rc4_encode_spl(buf, RK_SPL_HDR_START,
- spl_params.init_size);
+ /* Set up the SPL name (i.e. copy spl_hdr over) */
+ if (memcmp(&hdr->magic, "RSAK", 4))
+ memcpy(&hdr->magic, rkcommon_get_spl_hdr(params), RK_SPL_HDR_SIZE);
- if (spl_params.boot_file) {
if (rkcommon_need_rc4_spl(params))
- rkcommon_rc4_encode_spl(buf + RK_SPL_HDR_START,
- spl_params.init_size,
- spl_params.boot_size);
+ rkcommon_rc4_encode_spl(buf, RK_SPL_HDR_START,
+ spl_params.init_size);
+
+ if (spl_params.boot_file) {
+ if (rkcommon_need_rc4_spl(params))
+ rkcommon_rc4_encode_spl(buf + RK_SPL_HDR_START,
+ spl_params.init_size,
+ spl_params.boot_size);
+ }
}
}
-static inline unsigned rkcommon_offset_to_spi(unsigned offset)
+static inline unsigned int rkcommon_offset_to_spi(unsigned int offset)
{
/*
* While SD/MMC images use a flat addressing, SPI images are padded
@@ -280,7 +390,7 @@ static inline unsigned rkcommon_offset_to_spi(unsigned offset)
static int rkcommon_parse_header(const void *buf, struct header0_info *header0,
struct spl_info **spl_info)
{
- unsigned hdr1_offset;
+ unsigned int hdr1_offset;
struct header1_info *hdr1_sdmmc, *hdr1_spi;
int i;
@@ -294,7 +404,7 @@ static int rkcommon_parse_header(const void *buf, struct header0_info *header0,
memcpy((void *)header0, buf, sizeof(struct header0_info));
rc4_encode((void *)header0, sizeof(struct header0_info), rc4_key);
- if (le32_to_cpu(header0->signature) != RK_SIGNATURE)
+ if (le32_to_cpu(header0->magic) != RK_MAGIC)
return -EPROTO;
/* We don't support RC4 encoded image payloads here, yet... */
@@ -323,6 +433,16 @@ static int rkcommon_parse_header(const void *buf, struct header0_info *header0,
return -1;
}
+static int rkcommon_parse_header_v2(const void *buf, struct header0_info_v2 *header)
+{
+ memcpy((void *)header, buf, sizeof(struct header0_info_v2));
+
+ if (le32_to_cpu(header->magic) != RK_MAGIC_V2)
+ return -EPROTO;
+
+ return 0;
+}
+
int rkcommon_verify_header(unsigned char *buf, int size,
struct image_tool_params *params)
{
@@ -357,30 +477,46 @@ int rkcommon_verify_header(unsigned char *buf, int size,
void rkcommon_print_header(const void *buf)
{
struct header0_info header0;
+ struct header0_info_v2 header0_v2;
struct spl_info *spl_info;
uint8_t image_type;
int ret, boot_size, init_size;
- ret = rkcommon_parse_header(buf, &header0, &spl_info);
+ if ((*(uint32_t *)buf) == RK_MAGIC_V2) {
+ ret = rkcommon_parse_header_v2(buf, &header0_v2);
- /* If this is the (unimplemented) RC4 case, then fail silently */
- if (ret == -ENOSYS)
- return;
+ if (ret < 0) {
+ fprintf(stderr, "Error: image verification failed\n");
+ return;
+ }
- if (ret < 0) {
- fprintf(stderr, "Error: image verification failed\n");
- return;
- }
+ init_size = header0_v2.images[0].size_and_off >> 16;
+ init_size = init_size * RK_BLK_SIZE;
+ boot_size = header0_v2.images[1].size_and_off >> 16;
+ boot_size = boot_size * RK_BLK_SIZE;
+ } else {
+ ret = rkcommon_parse_header(buf, &header0, &spl_info);
- image_type = ret;
+ /* If this is the (unimplemented) RC4 case, then fail silently */
+ if (ret == -ENOSYS)
+ return;
+
+ if (ret < 0) {
+ fprintf(stderr, "Error: image verification failed\n");
+ return;
+ }
+
+ image_type = ret;
+ init_size = header0.init_size * RK_BLK_SIZE;
+ boot_size = header0.init_boot_size * RK_BLK_SIZE - init_size;
+
+ printf("Image Type: Rockchip %s (%s) boot image\n",
+ spl_info->spl_hdr,
+ (image_type == IH_TYPE_RKSD) ? "SD/MMC" : "SPI");
+ }
- printf("Image Type: Rockchip %s (%s) boot image\n",
- spl_info->spl_hdr,
- (image_type == IH_TYPE_RKSD) ? "SD/MMC" : "SPI");
- init_size = le16_to_cpu(header0.init_size) * RK_BLK_SIZE;
printf("Init Data Size: %d bytes\n", init_size);
- boot_size = le16_to_cpu(header0.init_boot_size) * RK_BLK_SIZE - init_size;
if (boot_size != RK_MAX_BOOT_SIZE)
printf("Boot Data Size: %d bytes\n", boot_size);
}