diff options
| -rw-r--r-- | drivers/clk/sunxi/Kconfig | 7 | ||||
| -rw-r--r-- | drivers/clk/sunxi/Makefile | 1 | ||||
| -rw-r--r-- | drivers/clk/sunxi/clk_r40.c | 70 |
3 files changed, 78 insertions, 0 deletions
diff --git a/drivers/clk/sunxi/Kconfig b/drivers/clk/sunxi/Kconfig index 90af70d..c45a4ba 100644 --- a/drivers/clk/sunxi/Kconfig +++ b/drivers/clk/sunxi/Kconfig @@ -44,6 +44,13 @@ config CLK_SUN8I_A83T This enables common clock driver support for platforms based on Allwinner A83T SoC. +config CLK_SUN8I_R40 + bool "Clock driver for Allwinner R40" + default MACH_SUN8I_R40 + help + This enables common clock driver support for platforms based + on Allwinner R40 SoC. + config CLK_SUN8I_H3 bool "Clock driver for Allwinner H3/H5" default MACH_SUNXI_H3_H5 diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile index 4a254c8..61f8b87 100644 --- a/drivers/clk/sunxi/Makefile +++ b/drivers/clk/sunxi/Makefile @@ -11,5 +11,6 @@ obj-$(CONFIG_CLK_SUN5I_A10S) += clk_a10s.o obj-$(CONFIG_CLK_SUN6I_A31) += clk_a31.o obj-$(CONFIG_CLK_SUN8I_A23) += clk_a23.o obj-$(CONFIG_CLK_SUN8I_A83T) += clk_a83t.o +obj-$(CONFIG_CLK_SUN8I_R40) += clk_r40.o obj-$(CONFIG_CLK_SUN8I_H3) += clk_h3.o obj-$(CONFIG_CLK_SUN50I_A64) += clk_a64.o diff --git a/drivers/clk/sunxi/clk_r40.c b/drivers/clk/sunxi/clk_r40.c new file mode 100644 index 0000000..cdf54da --- /dev/null +++ b/drivers/clk/sunxi/clk_r40.c @@ -0,0 +1,70 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2018 Amarula Solutions. + * Author: Jagan Teki <jagan@amarulasolutions.com> + */ + +#include <common.h> +#include <clk-uclass.h> +#include <dm.h> +#include <errno.h> +#include <asm/arch/ccu.h> +#include <dt-bindings/clock/sun8i-r40-ccu.h> +#include <dt-bindings/reset/sun8i-r40-ccu.h> + +static struct ccu_clk_gate r40_gates[] = { + [CLK_BUS_OTG] = GATE(0x060, BIT(25)), + [CLK_BUS_EHCI0] = GATE(0x060, BIT(26)), + [CLK_BUS_EHCI1] = GATE(0x060, BIT(27)), + [CLK_BUS_EHCI2] = GATE(0x060, BIT(28)), + [CLK_BUS_OHCI0] = GATE(0x060, BIT(29)), + [CLK_BUS_OHCI1] = GATE(0x060, BIT(30)), + [CLK_BUS_OHCI2] = GATE(0x060, BIT(31)), + + [CLK_USB_PHY0] = GATE(0x0cc, BIT(8)), + [CLK_USB_PHY1] = GATE(0x0cc, BIT(9)), + [CLK_USB_PHY2] = GATE(0x0cc, BIT(10)), + [CLK_USB_OHCI0] = GATE(0x0cc, BIT(16)), + [CLK_USB_OHCI1] = GATE(0x0cc, BIT(17)), + [CLK_USB_OHCI2] = GATE(0x0cc, BIT(18)), +}; + +static struct ccu_reset r40_resets[] = { + [RST_USB_PHY0] = RESET(0x0cc, BIT(0)), + [RST_USB_PHY1] = RESET(0x0cc, BIT(1)), + [RST_USB_PHY2] = RESET(0x0cc, BIT(2)), + + [RST_BUS_OTG] = RESET(0x2c0, BIT(25)), + [RST_BUS_EHCI0] = RESET(0x2c0, BIT(26)), + [RST_BUS_EHCI1] = RESET(0x2c0, BIT(27)), + [RST_BUS_EHCI2] = RESET(0x2c0, BIT(28)), + [RST_BUS_OHCI0] = RESET(0x2c0, BIT(29)), + [RST_BUS_OHCI1] = RESET(0x2c0, BIT(30)), + [RST_BUS_OHCI2] = RESET(0x2c0, BIT(31)), +}; + +static const struct ccu_desc r40_ccu_desc = { + .gates = r40_gates, + .resets = r40_resets, +}; + +static int r40_clk_bind(struct udevice *dev) +{ + return sunxi_reset_bind(dev, ARRAY_SIZE(r40_resets)); +} + +static const struct udevice_id r40_clk_ids[] = { + { .compatible = "allwinner,sun8i-r40-ccu", + .data = (ulong)&r40_ccu_desc }, + { } +}; + +U_BOOT_DRIVER(clk_sun8i_r40) = { + .name = "sun8i_r40_ccu", + .id = UCLASS_CLK, + .of_match = r40_clk_ids, + .priv_auto_alloc_size = sizeof(struct ccu_priv), + .ops = &sunxi_clk_ops, + .probe = sunxi_clk_probe, + .bind = r40_clk_bind, +}; |