diff options
45 files changed, 1002 insertions, 214 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index abd7c6c..59e4d4d 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1160,14 +1160,14 @@ config ARCH_SUNXI select SPL_SEPARATE_BSS if SPL select SPL_STACK_R if SPL select SPL_SYS_MALLOC_SIMPLE if SPL - select SPL_SYS_THUMB_BUILD if !ARM64 + select SPL_SYS_THUMB_BUILD if SPL && !ARM64 select SUNXI_GPIO select SYS_NS16550 select SYS_THUMB_BUILD if !ARM64 select USB if DISTRO_DEFAULTS select USB_KEYBOARD if DISTRO_DEFAULTS && USB_HOST select USB_STORAGE if DISTRO_DEFAULTS && USB_HOST - select SPL_USE_TINY_PRINTF + select SPL_USE_TINY_PRINTF if SPL select USE_PREBOOT select SYS_RELOC_GD_ENV_ADDR imply BOARD_LATE_INIT diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index b5c588c..50f35e3 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -838,6 +838,7 @@ dtb-$(CONFIG_MACH_SUN50I_H6) += \ dtb-$(CONFIG_MACH_SUN50I_H616) += \ sun50i-h616-orangepi-zero2.dtb \ sun50i-h618-orangepi-zero3.dtb \ + sun50i-h618-transpeed-8k618-t.dtb \ sun50i-h616-x96-mate.dtb dtb-$(CONFIG_MACH_SUN50I) += \ sun50i-a64-amarula-relic.dtb \ diff --git a/arch/arm/dts/sun50i-h616-bigtreetech-cb1-manta.dts b/arch/arm/dts/sun50i-h616-bigtreetech-cb1-manta.dts new file mode 100644 index 0000000..dbce61b --- /dev/null +++ b/arch/arm/dts/sun50i-h616-bigtreetech-cb1-manta.dts @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +/* + * Copyright (C) 2023 Martin Botka <martin.botka@somainline.org>. + */ + +/dts-v1/; + +#include "sun50i-h616-bigtreetech-cb1.dtsi" + +/ { + model = "BigTreeTech CB1"; + compatible = "bigtreetech,cb1-manta", "bigtreetech,cb1", "allwinner,sun50i-h616"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&ehci1 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_ph_pins>; + status = "okay"; +}; diff --git a/arch/arm/dts/sun50i-h616-bigtreetech-cb1.dtsi b/arch/arm/dts/sun50i-h616-bigtreetech-cb1.dtsi new file mode 100644 index 0000000..1fed2b4 --- /dev/null +++ b/arch/arm/dts/sun50i-h616-bigtreetech-cb1.dtsi @@ -0,0 +1,138 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +/* + * Copyright (C) 2023 Martin Botka <martin.botka@somainline.org>. + */ + +/dts-v1/; + +#include "sun50i-h616.dtsi" + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/leds/common.h> + +/ { + aliases { + ethernet0 = &rtl8189ftv; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + function = LED_FUNCTION_STATUS; + color = <LED_COLOR_ID_GREEN>; + gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ + }; + }; + + reg_vcc5v: regulator-vcc5v { + /* board wide 5V supply from carrier boards */ + compatible = "regulator-fixed"; + regulator-name = "vcc-5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + reg_vcc33_wifi: vcc33-wifi { + compatible = "regulator-fixed"; + regulator-name = "vcc33-wifi"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + vin-supply = <®_vcc5v>; + }; + + reg_vcc_wifi_io: vcc-wifi-io { + compatible = "regulator-fixed"; + regulator-name = "vcc-wifi-io"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + vin-supply = <®_vcc33_wifi>; + }; + + wifi_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rtc 1>; + clock-names = "ext_clock"; + reset-gpios = <&pio 6 18 GPIO_ACTIVE_LOW>; /* PG18 */ + post-power-on-delay-ms = <200>; + }; +}; + +&mmc0 { + vmmc-supply = <®_dldo1>; + /* Card detection pin is not connected */ + broken-cd; + bus-width = <4>; + status = "okay"; +}; + +&mmc1 { + vmmc-supply = <®_vcc33_wifi>; + vqmmc-supply = <®_vcc_wifi_io>; + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + non-removable; + mmc-ddr-1_8v; + status = "okay"; + + rtl8189ftv: wifi@1 { + reg = <1>; + }; +}; + +&r_i2c { + status = "okay"; + + axp313a: pmic@36 { + compatible = "x-powers,axp313a"; + reg = <0x36>; + interrupt-controller; + #interrupt-cells = <1>; + + regulators{ + reg_dcdc1: dcdc1 { + regulator-name = "vdd-gpu-sys"; + regulator-min-microvolt = <810000>; + regulator-max-microvolt = <990000>; + regulator-always-on; + }; + + reg_dcdc2: dcdc2 { + regulator-name = "vdd-cpu"; + regulator-min-microvolt = <810000>; + regulator-max-microvolt = <1100000>; + regulator-ramp-delay = <200>; + regulator-always-on; + }; + + reg_dcdc3: dcdc3 { + regulator-name = "vcc-dram"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + }; + + reg_aldo1: aldo1 { + regulator-name = "vcc-1v8-pll"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reg_dldo1: dldo1 { + regulator-name = "vcc-3v3-io"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; +}; + +&usbphy { + status = "okay"; +}; diff --git a/arch/arm/dts/sun50i-h616-bigtreetech-pi.dts b/arch/arm/dts/sun50i-h616-bigtreetech-pi.dts new file mode 100644 index 0000000..832f08b --- /dev/null +++ b/arch/arm/dts/sun50i-h616-bigtreetech-pi.dts @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +/* + * Copyright (C) 2023 Martin Botka <martin@biqu3d.com>. + */ + +/dts-v1/; + +#include "sun50i-h616-bigtreetech-cb1.dtsi" + +/ { + model = "BigTreeTech Pi"; + compatible = "bigtreetech,pi", "allwinner,sun50i-h616"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&ehci2 { + status = "okay"; +}; + +&ehci3 { + status = "okay"; +}; + +&ir { + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&ohci2 { + status = "okay"; +}; + +&ohci3 { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_ph_pins>; + status = "okay"; +}; diff --git a/arch/arm/dts/sun50i-h616.dtsi b/arch/arm/dts/sun50i-h616.dtsi index 74aed0d..d549d27 100644 --- a/arch/arm/dts/sun50i-h616.dtsi +++ b/arch/arm/dts/sun50i-h616.dtsi @@ -133,6 +133,13 @@ #reset-cells = <1>; }; + sid: efuse@3006000 { + compatible = "allwinner,sun50i-h616-sid", "allwinner,sun50i-a64-sid"; + reg = <0x03006000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + }; + watchdog: watchdog@30090a0 { compatible = "allwinner,sun50i-h616-wdt", "allwinner,sun6i-a31-wdt"; diff --git a/arch/arm/dts/sun50i-h618-orangepi-zero2w.dts b/arch/arm/dts/sun50i-h618-orangepi-zero2w.dts new file mode 100644 index 0000000..21ca197 --- /dev/null +++ b/arch/arm/dts/sun50i-h618-orangepi-zero2w.dts @@ -0,0 +1,176 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2023 Arm Ltd. + */ + +/dts-v1/; + +#include "sun50i-h616.dtsi" + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/leds/common.h> + +/ { + model = "OrangePi Zero 2W"; + compatible = "xunlong,orangepi-zero2w", "allwinner,sun50i-h618"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + function = LED_FUNCTION_STATUS; + color = <LED_COLOR_ID_GREEN>; + gpios = <&pio 2 13 GPIO_ACTIVE_HIGH>; /* PC13 */ + }; + }; + + reg_vcc5v: vcc5v { + /* board wide 5V supply directly from the USB-C socket */ + compatible = "regulator-fixed"; + regulator-name = "vcc-5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + reg_vcc3v3: vcc3v3 { + /* SY8089 DC/DC converter */ + compatible = "regulator-fixed"; + regulator-name = "vcc-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <®_vcc5v>; + regulator-always-on; + }; +}; + +&ehci1 { + status = "okay"; +}; + +/* USB 2 & 3 are on the FPC connector (or the exansion board) */ + +&mmc0 { + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ + bus-width = <4>; + vmmc-supply = <®_vcc3v3>; + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&pio { + vcc-pc-supply = <®_dldo1>; + vcc-pf-supply = <®_dldo1>; /* internally via VCC-IO */ + vcc-pg-supply = <®_aldo1>; + vcc-ph-supply = <®_dldo1>; /* internally via VCC-IO */ + vcc-pi-supply = <®_dldo1>; +}; + +&r_i2c { + status = "okay"; + + axp313: pmic@36 { + compatible = "x-powers,axp313a"; + reg = <0x36>; + #interrupt-cells = <1>; + interrupt-controller; + interrupt-parent = <&pio>; + interrupts = <2 9 IRQ_TYPE_LEVEL_LOW>; /* PC9 */ + + vin1-supply = <®_vcc5v>; + vin2-supply = <®_vcc5v>; + vin3-supply = <®_vcc5v>; + + regulators { + /* Supplies VCC-PLL and DRAM */ + reg_aldo1: aldo1 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc1v8"; + }; + + /* Supplies VCC-IO, so needs to be always on. */ + reg_dldo1: dldo1 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3"; + }; + + reg_dcdc1: dcdc1 { + regulator-always-on; + regulator-min-microvolt = <810000>; + regulator-max-microvolt = <990000>; + regulator-name = "vdd-gpu-sys"; + }; + + reg_dcdc2: dcdc2 { + regulator-always-on; + regulator-min-microvolt = <810000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-cpu"; + }; + + reg_dcdc3: dcdc3 { + regulator-always-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-dram"; + }; + }; + }; +}; + +&spi0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins>, <&spi0_cs0_pin>; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <40000000>; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_ph_pins>; + status = "okay"; +}; + +&usbotg { + /* + * PHY0 pins are connected to a USB-C socket, but a role switch + * is not implemented: both CC pins are pulled to GND. + * The VBUS pins power the device, so a fixed peripheral mode + * is the best choice. + * The board can be powered via GPIOs, in this case port0 *can* + * act as a host (with a cable/adapter ignoring CC), as VBUS is + * then provided by the GPIOs. Any user of this setup would + * need to adjust the DT accordingly: dr_mode set to "host", + * enabling OHCI0 and EHCI0. + */ + dr_mode = "peripheral"; + status = "okay"; +}; + +&usbphy { + usb1_vbus-supply = <®_vcc5v>; + status = "okay"; +}; diff --git a/arch/arm/dts/sun50i-h618-transpeed-8k618-t.dts b/arch/arm/dts/sun50i-h618-transpeed-8k618-t.dts new file mode 100644 index 0000000..8ea1fd4 --- /dev/null +++ b/arch/arm/dts/sun50i-h618-transpeed-8k618-t.dts @@ -0,0 +1,161 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2023 Arm Ltd. + */ + +/dts-v1/; + +#include "sun50i-h616.dtsi" + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + model = "Transpeed 8K618-T"; + compatible = "transpeed,8k618-t", "allwinner,sun50i-h618"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + reg_vcc5v: vcc5v { + /* board wide 5V supply directly from the DC input */ + compatible = "regulator-fixed"; + regulator-name = "vcc-5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + reg_vcc3v3: vcc3v3 { + /* discrete 3.3V regulator */ + compatible = "regulator-fixed"; + regulator-name = "vcc-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&ir { + status = "okay"; +}; + +&mmc0 { + vmmc-supply = <®_dldo1>; + cd-gpios = <&pio 8 16 GPIO_ACTIVE_LOW>; /* PI16 */ + bus-width = <4>; + status = "okay"; +}; + +&mmc2 { + vmmc-supply = <®_dldo1>; + vqmmc-supply = <®_aldo1>; + bus-width = <8>; + non-removable; + cap-mmc-hw-reset; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&r_i2c { + status = "okay"; + + axp313: pmic@36 { + compatible = "x-powers,axp313a"; + reg = <0x36>; + #interrupt-cells = <1>; + interrupt-controller; + + vin1-supply = <®_vcc5v>; + vin2-supply = <®_vcc5v>; + vin3-supply = <®_vcc5v>; + + regulators { + reg_aldo1: aldo1 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-1v8-pll"; + }; + + reg_dldo1: dldo1 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-3v3-io-mmc"; + }; + + reg_dcdc1: dcdc1 { + regulator-always-on; + regulator-min-microvolt = <810000>; + regulator-max-microvolt = <990000>; + regulator-name = "vdd-gpu-sys"; + }; + + reg_dcdc2: dcdc2 { + regulator-always-on; + regulator-min-microvolt = <810000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-cpu"; + }; + + reg_dcdc3: dcdc3 { + regulator-always-on; + regulator-min-microvolt = <1360000>; + regulator-max-microvolt = <1360000>; + regulator-name = "vdd-dram"; + }; + }; + }; +}; + +&pio { + vcc-pc-supply = <®_aldo1>; + vcc-pg-supply = <®_dldo1>; + vcc-ph-supply = <®_dldo1>; + vcc-pi-supply = <®_dldo1>; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_ph_pins>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; + uart-has-rtscts; + status = "okay"; +}; + +&usbotg { + dr_mode = "host"; /* USB A type receptable */ + status = "okay"; +}; + +&usbphy { + status = "okay"; +}; diff --git a/arch/arm/dts/sun8i-r40.dtsi b/arch/arm/dts/sun8i-r40.dtsi index 4ef26d8..a5b1f1e 100644 --- a/arch/arm/dts/sun8i-r40.dtsi +++ b/arch/arm/dts/sun8i-r40.dtsi @@ -338,6 +338,8 @@ resets = <&ccu RST_BUS_VE>; interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; allwinner,sram = <&ve_sram 1>; + interconnects = <&mbus 4>; + interconnect-names = "dma-mem"; }; mmc0: mmc@1c0f000 { diff --git a/arch/arm/dts/sun8i-v3s-anbernic-rg-nano.dts b/arch/arm/dts/sun8i-v3s-anbernic-rg-nano.dts new file mode 100644 index 0000000..f34dfdf --- /dev/null +++ b/arch/arm/dts/sun8i-v3s-anbernic-rg-nano.dts @@ -0,0 +1,276 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; +#include <dt-bindings/input/linux-event-codes.h> +#include "sun8i-v3s.dtsi" +#include "sunxi-common-regulators.dtsi" + +/ { + model = "Anbernic RG Nano"; + compatible = "anbernic,rg-nano", "allwinner,sun8i-v3s"; + + aliases { + rtc0 = &pcf8563; + rtc1 = &rtc; + serial0 = &uart0; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + brightness-levels = <0 1 2 3 8 14 21 32 46 60 80 100>; + default-brightness-level = <11>; + power-supply = <®_vcc5v0>; + pwms = <&pwm 0 40000 1>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio_keys: gpio-keys { + compatible = "gpio-keys"; + + button-a { + gpios = <&gpio_expander 12 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + label = "BTN-A"; + linux,code = <BTN_EAST>; + }; + + button-b { + gpios = <&gpio_expander 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + label = "BTN-B"; + linux,code = <BTN_SOUTH>; + }; + + button-down { + gpios = <&gpio_expander 1 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + label = "DPAD-DOWN"; + linux,code = <BTN_DPAD_DOWN>; + }; + + button-left { + gpios = <&gpio_expander 4 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + label = "DPAD-LEFT"; + linux,code = <BTN_DPAD_LEFT>; + }; + + button-right { + gpios = <&gpio_expander 0 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + label = "DPAD-RIGHT"; + linux,code = <BTN_DPAD_RIGHT>; + }; + + button-se { + gpios = <&gpio_expander 7 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + label = "BTN-SELECT"; + linux,code = <BTN_SELECT>; + }; + + button-st { + gpios = <&gpio_expander 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + label = "BTN-START"; + linux,code = <BTN_START>; + }; + + button-tl { + gpios = <&gpio_expander 2 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + label = "BTN-L"; + linux,code = <BTN_TL>; + }; + + button-tr { + gpios = <&gpio_expander 15 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + label = "BTN-R"; + linux,code = <BTN_TR>; + }; + + button-up { + gpios = <&gpio_expander 3 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + label = "DPAD-UP"; + linux,code = <BTN_DPAD_UP>; + }; + + button-x { + gpios = <&gpio_expander 11 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + label = "BTN-X"; + linux,code = <BTN_NORTH>; + }; + + button-y { + gpios = <&gpio_expander 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + label = "BTN-Y"; + linux,code = <BTN_WEST>; + }; + }; +}; + +&codec { + allwinner,audio-routing = "Speaker", "HP", + "MIC1", "Mic", + "Mic", "HBIAS"; + allwinner,pa-gpios = <&pio 5 6 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PF6 */ + status = "okay"; +}; + +&ehci { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + gpio_expander: gpio@20 { + compatible = "nxp,pcal6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + interrupt-controller; + interrupt-parent = <&pio>; + interrupts = <1 3 IRQ_TYPE_EDGE_BOTH>; /* PB3/EINT3 */ + vcc-supply = <®_vcc3v3>; + }; + + axp209: pmic@34 { + reg = <0x34>; + interrupt-parent = <&pio>; + interrupts = <1 5 IRQ_TYPE_EDGE_FALLING>; /* PB5/EINT5 */ + }; + + pcf8563: rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; +}; + +#include "axp209.dtsi" + +&battery_power_supply { + status = "okay"; +}; + +&mmc0 { + broken-cd; + bus-width = <4>; + disable-wp; + vmmc-supply = <®_vcc3v3>; + vqmmc-supply = <®_vcc3v3>; + status = "okay"; +}; + +&ohci { + status = "okay"; +}; + +&pio { + vcc-pb-supply = <®_vcc3v3>; + vcc-pc-supply = <®_vcc3v3>; + vcc-pf-supply = <®_vcc3v3>; + vcc-pg-supply = <®_vcc3v3>; + + spi0_no_miso_pins: spi0-no-miso-pins { + pins = "PC1", "PC2", "PC3"; + function = "spi0"; + }; +}; + +&pwm { + pinctrl-0 = <&pwm0_pin>; + pinctrl-names = "default"; + status = "okay"; +}; + +/* DCDC2 wired into vdd-cpu, vdd-sys, and vdd-ephy. */ +®_dcdc2 { + regulator-always-on; + regulator-max-microvolt = <1250000>; + regulator-min-microvolt = <1250000>; + regulator-name = "vdd-cpu"; +}; + +/* DCDC3 wired into every 3.3v input that isn't the RTC. */ +®_dcdc3 { + regulator-always-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "vcc-io"; +}; + +/* LDO1 wired into RTC, voltage is hard-wired at 3.3v. */ +®_ldo1 { + regulator-always-on; + regulator-name = "vcc-rtc"; +}; + +/* LDO2 wired into VCC-PLL and audio codec. */ +®_ldo2 { + regulator-always-on; + regulator-max-microvolt = <3000000>; + regulator-min-microvolt = <3000000>; + regulator-name = "vcc-pll"; +}; + +/* LDO3, LDO4, and LDO5 unused. */ +®_ldo3 { + status = "disabled"; +}; + +®_ldo4 { + status = "disabled"; +}; + +/* RTC uses internal oscillator */ +&rtc { + /delete-property/ clocks; +}; + +&spi0 { + pinctrl-0 = <&spi0_no_miso_pins>; + pinctrl-names = "default"; + status = "okay"; + + display@0 { + compatible = "saef,sftc154b", "panel-mipi-dbi-spi"; + reg = <0>; + backlight = <&backlight>; + dc-gpios = <&pio 2 0 GPIO_ACTIVE_HIGH>; /* PC0 */ + reset-gpios = <&pio 1 2 GPIO_ACTIVE_HIGH>; /* PB2 */ + spi-max-frequency = <100000000>; + + height-mm = <39>; + width-mm = <39>; + + /* Set hb-porch to compensate for non-visible area */ + panel-timing { + hactive = <240>; + vactive = <240>; + hback-porch = <80>; + vback-porch = <0>; + clock-frequency = <0>; + hfront-porch = <0>; + hsync-len = <0>; + vfront-porch = <0>; + vsync-len = <0>; + }; + }; +}; + +&uart0 { + pinctrl-0 = <&uart0_pb_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usb_power_supply { + status = "okay"; +}; + +&usbphy { + usb0_id_det-gpios = <&pio 6 5 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PG5 */ + status = "okay"; +}; diff --git a/arch/arm/dts/sun8i-v3s.dtsi b/arch/arm/dts/sun8i-v3s.dtsi index 3b9a282..e8a0447 100644 --- a/arch/arm/dts/sun8i-v3s.dtsi +++ b/arch/arm/dts/sun8i-v3s.dtsi @@ -319,6 +319,29 @@ #phy-cells = <1>; }; + ehci: usb@1c1a000 { + compatible = "allwinner,sun8i-v3s-ehci", "generic-ehci"; + reg = <0x01c1a000 0x100>; + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>; + resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>; + phys = <&usbphy 0>; + phy-names = "usb"; + status = "disabled"; + }; + + ohci: usb@1c1a400 { + compatible = "allwinner,sun8i-v3s-ohci", "generic-ohci"; + reg = <0x01c1a400 0x100>; + interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>, + <&ccu CLK_USB_OHCI0>; + resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>; + phys = <&usbphy 0>; + phy-names = "usb"; + status = "disabled"; + }; + ccu: clock@1c20000 { compatible = "allwinner,sun8i-v3s-ccu"; reg = <0x01c20000 0x400>; @@ -414,6 +437,18 @@ bias-pull-up; }; + /omit-if-no-ref/ + pwm0_pin: pwm0-pin { + pins = "PB4"; + function = "pwm0"; + }; + + /omit-if-no-ref/ + pwm1_pin: pwm1-pin { + pins = "PB5"; + function = "pwm1"; + }; + spi0_pins: spi0-pins { pins = "PC0", "PC1", "PC2", "PC3"; function = "spi0"; diff --git a/arch/arm/dts/sunxi-u-boot.dtsi b/arch/arm/dts/sunxi-u-boot.dtsi index a0c8abb..0909a67 100644 --- a/arch/arm/dts/sunxi-u-boot.dtsi +++ b/arch/arm/dts/sunxi-u-boot.dtsi @@ -1,13 +1,9 @@ #include <config.h> -#ifdef CONFIG_MACH_SUN50I_H6 -#define BL31_ADDR 0x104000 -#define SCP_ADDR 0x114000 -#elif defined(CONFIG_MACH_SUN50I_H616) -#define BL31_ADDR 0x40000000 +#ifdef CONFIG_ARM64 +#define ARCH "arm64" #else -#define BL31_ADDR 0x44000 -#define SCP_ADDR 0x50000 +#define ARCH "arm" #endif / { @@ -44,47 +40,52 @@ filename = "spl/sunxi-spl.bin"; }; -#ifdef CONFIG_ARM64 +#ifdef CONFIG_SPL_LOAD_FIT fit { - description = "Configuration to load ATF before U-Boot"; + description = "Configuration to load U-Boot and firmware"; #address-cells = <1>; fit,fdt-list = "of-list"; images { uboot { - description = "U-Boot (64-bit)"; + description = "U-Boot"; type = "standalone"; os = "u-boot"; - arch = "arm64"; + arch = ARCH; compression = "none"; load = <CONFIG_TEXT_BASE>; +#if CONFIG_SUNXI_BL31_BASE == 0 + entry = <CONFIG_TEXT_BASE>; +#endif u-boot-nodtb { }; }; +#if CONFIG_SUNXI_BL31_BASE atf { description = "ARM Trusted Firmware"; type = "firmware"; os = "arm-trusted-firmware"; - arch = "arm64"; + arch = ARCH; compression = "none"; - load = <BL31_ADDR>; - entry = <BL31_ADDR>; + load = <CONFIG_SUNXI_BL31_BASE>; + entry = <CONFIG_SUNXI_BL31_BASE>; atf-bl31 { filename = "bl31.bin"; missing-msg = "atf-bl31-sunxi"; }; }; +#endif -#ifdef SCP_ADDR +#if CONFIG_SUNXI_SCP_BASE scp { description = "SCP firmware"; type = "firmware"; arch = "or1k"; compression = "none"; - load = <SCP_ADDR>; + load = <CONFIG_SUNXI_SCP_BASE>; scp { filename = "scp.bin"; @@ -105,11 +106,15 @@ @config-SEQ { description = "NAME"; +#if CONFIG_SUNXI_BL31_BASE firmware = "atf"; -#ifndef SCP_ADDR - loadables = "uboot"; #else + firmware = "uboot"; +#endif +#if CONFIG_SUNXI_SCP_BASE loadables = "scp", "uboot"; +#else + loadables = "uboot"; #endif fdt = "fdt-SEQ"; }; diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h index 3daee2f..f023a4c 100644 --- a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h +++ b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h @@ -36,58 +36,20 @@ #define SUNXI_SRAMC_BASE 0x01c00000 #define SUNXI_DRAMC_BASE 0x01c01000 -#define SUNXI_DMA_BASE 0x01c02000 #define SUNXI_NFC_BASE 0x01c03000 -#define SUNXI_TS_BASE 0x01c04000 -#define SUNXI_SPI0_BASE 0x01c05000 -#define SUNXI_SPI1_BASE 0x01c06000 -#define SUNXI_MS_BASE 0x01c07000 -#define SUNXI_TVD_BASE 0x01c08000 -#define SUNXI_CSI0_BASE 0x01c09000 #ifndef CONFIG_MACH_SUNXI_H3_H5 #define SUNXI_TVE0_BASE 0x01c0a000 #endif -#define SUNXI_EMAC_BASE 0x01c0b000 #define SUNXI_LCD0_BASE 0x01c0C000 #define SUNXI_LCD1_BASE 0x01c0d000 -#define SUNXI_VE_BASE 0x01c0e000 #define SUNXI_MMC0_BASE 0x01c0f000 #define SUNXI_MMC1_BASE 0x01c10000 #define SUNXI_MMC2_BASE 0x01c11000 #define SUNXI_MMC3_BASE 0x01c12000 -#ifdef CONFIG_SUNXI_GEN_SUN4I -#define SUNXI_USB0_BASE 0x01c13000 -#define SUNXI_USB1_BASE 0x01c14000 -#endif #define SUNXI_SS_BASE 0x01c15000 #if !defined(CONFIG_MACH_SUNXI_H3_H5) && !defined(CONFIG_MACH_SUN50I) #define SUNXI_HDMI_BASE 0x01c16000 #endif -#define SUNXI_SPI2_BASE 0x01c17000 -#define SUNXI_SATA_BASE 0x01c18000 -#ifdef CONFIG_SUNXI_GEN_SUN4I -#define SUNXI_PATA_BASE 0x01c19000 -#define SUNXI_ACE_BASE 0x01c1a000 -#define SUNXI_TVE1_BASE 0x01c1b000 -#define SUNXI_USB2_BASE 0x01c1c000 -#endif -#ifdef CONFIG_SUNXI_GEN_SUN6I -#if defined(CONFIG_MACH_SUNXI_H3_H5) || defined(CONFIG_MACH_SUN50I) -#define SUNXI_USBPHY_BASE 0x01c19000 -#define SUNXI_USB0_BASE SUNXI_USBPHY_BASE -#define SUNXI_USB1_BASE 0x01c1a000 -#define SUNXI_USB2_BASE 0x01c1b000 -#define SUNXI_USB3_BASE 0x01c1c000 -#define SUNXI_USB4_BASE 0x01c1d000 -#else -#define SUNXI_USB0_BASE 0x01c19000 -#define SUNXI_USB1_BASE 0x01c1a000 -#define SUNXI_USB2_BASE 0x01c1b000 -#endif -#endif -#define SUNXI_CSI1_BASE 0x01c1d000 -#define SUNXI_TZASC_BASE 0x01c1e000 -#define SUNXI_SPI3_BASE 0x01c1f000 #define SUNXI_CCM_BASE 0x01c20000 #define SUNXI_INTC_BASE 0x01c20400 @@ -177,8 +139,6 @@ defined(CONFIG_MACH_SUN50I) #else #define SUNXI_TVE0_BASE 0x01e40000 #endif -#define SUNXI_MP_BASE 0x01e80000 -#define SUNXI_AVG_BASE 0x01ea0000 #if defined(CONFIG_MACH_SUNXI_H3_H5) || defined(CONFIG_MACH_SUN50I) #define SUNXI_HDMI_BASE 0x01ee0000 @@ -197,13 +157,6 @@ defined(CONFIG_MACH_SUN50I) #define SUN6I_P2WI_BASE 0x01f03400 #define SUNXI_RSB_BASE 0x01f03400 -/* CoreSight Debug Module */ -#define SUNXI_CSDM_BASE 0x3f500000 - -#define SUNXI_DDRII_DDRIII_BASE 0x40000000 /* 2 GiB */ - -#define SUNXI_BROM_BASE 0xffff0000 /* 32 kiB */ - #define SUNXI_CPU_CFG (SUNXI_TIMER_BASE + 0x13c) /* SS bonding ids used for cpu identification */ diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h b/arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h index 15ee092..8a3f465 100644 --- a/arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h +++ b/arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h @@ -7,25 +7,14 @@ #ifndef _SUNXI_CPU_SUN50I_H6_H #define _SUNXI_CPU_SUN50I_H6_H -#define SUNXI_SRAM_A1_BASE CONFIG_SUNXI_SRAM_ADDRESS -#define SUNXI_SRAM_C_BASE 0x00028000 -#define SUNXI_SRAM_A2_BASE 0x00100000 - -#define SUNXI_DE3_BASE 0x01000000 -#define SUNXI_SS_BASE 0x01904000 -#define SUNXI_EMCE_BASE 0x01905000 - #define SUNXI_SRAMC_BASE 0x03000000 #define SUNXI_CCM_BASE 0x03001000 -#define SUNXI_DMA_BASE 0x03002000 /* SID address space starts at 0x03006000, but e-fuse is at offset 0x200 */ #define SUNXI_SIDC_BASE 0x03006000 #define SUNXI_SID_BASE 0x03006200 #define SUNXI_TIMER_BASE 0x03009000 -#define SUNXI_PSI_BASE 0x0300C000 #define SUNXI_GIC400_BASE 0x03020000 -#define SUNXI_IOMMU_BASE 0x030F0000 #ifdef CONFIG_MACH_SUN50I_H6 #define SUNXI_DRAM_COM_BASE 0x04002000 @@ -46,18 +35,8 @@ #define SUNXI_TWI1_BASE 0x05002400 #define SUNXI_TWI2_BASE 0x05002800 #define SUNXI_TWI3_BASE 0x05002C00 -#define SUNXI_SPI0_BASE 0x05010000 -#define SUNXI_SPI1_BASE 0x05011000 -#define SUNXI_GMAC_BASE 0x05020000 -#define SUNXI_USB0_BASE 0x05100000 -#define SUNXI_XHCI_BASE 0x05200000 -#define SUNXI_USB3_BASE 0x05311000 -#define SUNXI_PCIE_BASE 0x05400000 #define SUNXI_HDMI_BASE 0x06000000 -#define SUNXI_TCON_TOP_BASE 0x06510000 -#define SUNXI_TCON_LCD0_BASE 0x06511000 -#define SUNXI_TCON_TV0_BASE 0x06515000 #define SUNXI_RTC_BASE 0x07000000 #define SUNXI_R_CPUCFG_BASE 0x07000400 diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h index 2bf2675..73de470 100644 --- a/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h +++ b/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h @@ -20,7 +20,6 @@ /* AHB0 Module */ #define SUNXI_NFC_BASE (REGS_AHB0_BASE + 0x3000) -#define SUNXI_TSC_BASE (REGS_AHB0_BASE + 0x4000) #define SUNXI_GTBUS_BASE (REGS_AHB0_BASE + 0x9000) /* SID address space starts at 0x01ce000, but e-fuse is at offset 0x200 */ @@ -32,14 +31,7 @@ #define SUNXI_MMC3_BASE (REGS_AHB0_BASE + 0x12000) #define SUNXI_MMC_COMMON_BASE (REGS_AHB0_BASE + 0x13000) -#define SUNXI_SPI0_BASE (REGS_AHB0_BASE + 0x1A000) -#define SUNXI_SPI1_BASE (REGS_AHB0_BASE + 0x1B000) -#define SUNXI_SPI2_BASE (REGS_AHB0_BASE + 0x1C000) -#define SUNXI_SPI3_BASE (REGS_AHB0_BASE + 0x1D000) - #define SUNXI_GIC400_BASE (REGS_AHB0_BASE + 0x40000) -#define SUNXI_ARMA9_GIC_BASE (REGS_AHB0_BASE + 0x41000) -#define SUNXI_ARMA9_CPUIF_BASE (REGS_AHB0_BASE + 0x42000) #define SUNXI_DRAM_COM_BASE (REGS_AHB0_BASE + 0x62000) #define SUNXI_DRAM_CTL0_BASE (REGS_AHB0_BASE + 0x63000) @@ -47,59 +39,26 @@ #define SUNXI_DRAM_PHY0_BASE (REGS_AHB0_BASE + 0x65000) #define SUNXI_DRAM_PHY1_BASE (REGS_AHB0_BASE + 0x66000) -/* AHB1 Module */ -#define SUNXI_DMA_BASE (REGS_AHB1_BASE + 0x002000) -#define SUNXI_USBOTG_BASE (REGS_AHB1_BASE + 0x100000) -#define SUNXI_USBEHCI0_BASE (REGS_AHB1_BASE + 0x200000) -#define SUNXI_USBEHCI1_BASE (REGS_AHB1_BASE + 0x201000) -#define SUNXI_USBEHCI2_BASE (REGS_AHB1_BASE + 0x202000) - -/* AHB2 Module */ -#define SUNXI_DE_SYS_BASE (REGS_AHB2_BASE + 0x000000) -#define SUNXI_DISP_SYS_BASE (REGS_AHB2_BASE + 0x010000) #define SUNXI_DE_FE0_BASE (REGS_AHB2_BASE + 0x100000) -#define SUNXI_DE_FE1_BASE (REGS_AHB2_BASE + 0x140000) -#define SUNXI_DE_FE2_BASE (REGS_AHB2_BASE + 0x180000) - #define SUNXI_DE_BE0_BASE (REGS_AHB2_BASE + 0x200000) -#define SUNXI_DE_BE1_BASE (REGS_AHB2_BASE + 0x240000) -#define SUNXI_DE_BE2_BASE (REGS_AHB2_BASE + 0x280000) - -#define SUNXI_DE_DEU0_BASE (REGS_AHB2_BASE + 0x300000) -#define SUNXI_DE_DEU1_BASE (REGS_AHB2_BASE + 0x340000) -#define SUNXI_DE_DRC0_BASE (REGS_AHB2_BASE + 0x400000) -#define SUNXI_DE_DRC1_BASE (REGS_AHB2_BASE + 0x440000) - #define SUNXI_LCD0_BASE (REGS_AHB2_BASE + 0xC00000) #define SUNXI_LCD1_BASE (REGS_AHB2_BASE + 0xC10000) #define SUNXI_LCD2_BASE (REGS_AHB2_BASE + 0xC20000) -#define SUNXI_MIPI_DSI0_BASE (REGS_AHB2_BASE + 0xC40000) -/* Also seen as SUNXI_MIPI_DSI0_DPHY_BASE 0x01ca1000 */ -#define SUNXI_MIPI_DSI0_DPHY_BASE (REGS_AHB2_BASE + 0xC40100) #define SUNXI_HDMI_BASE (REGS_AHB2_BASE + 0xD00000) /* APB0 Module */ #define SUNXI_CCM_BASE (REGS_APB0_BASE + 0x0000) -#define SUNXI_CCMMODULE_BASE (REGS_APB0_BASE + 0x0400) #define SUNXI_TIMER_BASE (REGS_APB0_BASE + 0x0C00) #define SUNXI_PWM_BASE (REGS_APB0_BASE + 0x1400) -#define SUNXI_LRADC_BASE (REGS_APB0_BASE + 0x1800) /* APB1 Module */ #define SUNXI_TWI0_BASE (REGS_APB1_BASE + 0x2800) #define SUNXI_TWI1_BASE (REGS_APB1_BASE + 0x2C00) -#define SUNXI_TWI2_BASE (REGS_APB1_BASE + 0x3000) -#define SUNXI_TWI3_BASE (REGS_APB1_BASE + 0x3400) -#define SUNXI_TWI4_BASE (REGS_APB1_BASE + 0x3800) /* RCPUS Module */ #define SUNXI_PRCM_BASE (REGS_RCPUS_BASE + 0x1400) #define SUNXI_RSB_BASE (REGS_RCPUS_BASE + 0x3400) -/* Misc. */ -#define SUNXI_BROM_BASE 0xFFFF0000 /* 32K */ -#define SUNXI_CPU_CFG (SUNXI_TIMER_BASE + 0x13c) - #ifndef __ASSEMBLY__ void sunxi_board_init(void); void sunxi_reset(void); diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index a4a8d8e..fe89aec 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -161,6 +161,23 @@ config SUNXI_RVBAR_ALTERNATIVE for all other SoCs, so the content of the SRAM_VER_REG becomes irrelevant there, and we can use the same code. +config SUNXI_BL31_BASE + hex + default 0x00044000 if MACH_SUN50I || MACH_SUN50I_H5 + default 0x00104000 if MACH_SUN50I_H6 + default 0x40000000 if MACH_SUN50I_H616 + default 0x0 + help + Address where BL31 (TF-A) is loaded, or zero if BL31 is not used. + +config SUNXI_SCP_BASE + hex + default 0x00050000 if MACH_SUN50I || MACH_SUN50I_H5 + default 0x00114000 if MACH_SUN50I_H6 + default 0x0 + help + Address where SCP firmware is loaded, or zero if it is not used. + config SUNXI_A64_TIMER_ERRATUM bool @@ -182,7 +199,7 @@ config SUNXI_GEN_SUN6I config SUN50I_GEN_H6 bool select FIT - select SPL_LOAD_FIT + select SPL_LOAD_FIT if SPL select MMC_SUNXI_HAS_NEW_MODE select SUPPORT_SPL ---help--- @@ -272,7 +289,7 @@ config MACH_SUN6I select ARCH_SUPPORT_PSCI select SPL_ARMV7_SET_CORTEX_SMPEN select DRAM_SUN6I - select SPL_I2C + select SPL_I2C if SPL select SUN6I_PRCM select SUNXI_GEN_SUN6I select SUPPORT_SPL @@ -300,7 +317,7 @@ config MACH_SUN8I_A23 select CPU_V7_HAS_VIRT select ARCH_SUPPORT_PSCI select DRAM_SUN8I_A23 - select SPL_I2C + select SPL_I2C if SPL select SUNXI_GEN_SUN6I select SUPPORT_SPL select SYS_I2C_SUN8I_RSB @@ -313,7 +330,7 @@ config MACH_SUN8I_A33 select CPU_V7_HAS_VIRT select ARCH_SUPPORT_PSCI select DRAM_SUN8I_A33 - select SPL_I2C + select SPL_I2C if SPL select SUNXI_GEN_SUN6I select SUPPORT_SPL select SYS_I2C_SUN8I_RSB @@ -323,7 +340,7 @@ config MACH_SUN8I_A83T bool "sun8i (Allwinner A83T)" select CPU_V7A select DRAM_SUN8I_A83T - select SPL_I2C + select SPL_I2C if SPL select SUNXI_GEN_SUN6I select MMC_SUNXI_HAS_NEW_MODE select MMC_SUNXI_HAS_MODE_SWITCH @@ -382,7 +399,7 @@ config MACH_SUN9I select CPU_V7A select SPL_ARMV7_SET_CORTEX_SMPEN select DRAM_SUN9I - select SPL_I2C + select SPL_I2C if SPL select SUN6I_PRCM select SUNXI_GEN_SUN6I select SUPPORT_SPL @@ -398,7 +415,7 @@ config MACH_SUN50I select SUNXI_DRAM_DW select SUNXI_DRAM_DW_32BIT select FIT - select SPL_LOAD_FIT + select SPL_LOAD_FIT if SPL select SUNXI_A64_TIMER_ERRATUM config MACH_SUN50I_H5 @@ -407,7 +424,7 @@ config MACH_SUN50I_H5 select MACH_SUNXI_H3_H5 select MMC_SUNXI_HAS_NEW_MODE select FIT - select SPL_LOAD_FIT + select SPL_LOAD_FIT if SPL config MACH_SUN50I_H6 bool "sun50i (Allwinner H6)" diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c index 11a4941..f4dbb2a 100644 --- a/arch/arm/mach-sunxi/board.c +++ b/arch/arm/mach-sunxi/board.c @@ -9,7 +9,6 @@ * Some init for sunxi platform. */ -#include <common.h> #include <cpu_func.h> #include <init.h> #include <log.h> diff --git a/arch/arm/mach-sunxi/clock.c b/arch/arm/mach-sunxi/clock.c index da3a0eb..b6c68c9 100644 --- a/arch/arm/mach-sunxi/clock.c +++ b/arch/arm/mach-sunxi/clock.c @@ -7,7 +7,6 @@ * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net> */ -#include <common.h> #include <asm/io.h> #include <asm/arch/clock.h> #include <asm/arch/prcm.h> diff --git a/arch/arm/mach-sunxi/clock_sun4i.c b/arch/arm/mach-sunxi/clock_sun4i.c index 4716097..8f1d1b6 100644 --- a/arch/arm/mach-sunxi/clock_sun4i.c +++ b/arch/arm/mach-sunxi/clock_sun4i.c @@ -9,7 +9,6 @@ * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net> */ -#include <common.h> #include <asm/io.h> #include <asm/arch/clock.h> #include <asm/arch/sys_proto.h> diff --git a/arch/arm/mach-sunxi/clock_sun50i_h6.c b/arch/arm/mach-sunxi/clock_sun50i_h6.c index bea91c7..dac3663 100644 --- a/arch/arm/mach-sunxi/clock_sun50i_h6.c +++ b/arch/arm/mach-sunxi/clock_sun50i_h6.c @@ -1,4 +1,3 @@ -#include <common.h> #include <asm/io.h> #include <asm/arch/cpu.h> #include <asm/arch/clock.h> diff --git a/arch/arm/mach-sunxi/clock_sun6i.c b/arch/arm/mach-sunxi/clock_sun6i.c index 6bd75a1..aad9df2 100644 --- a/arch/arm/mach-sunxi/clock_sun6i.c +++ b/arch/arm/mach-sunxi/clock_sun6i.c @@ -9,7 +9,6 @@ * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net> */ -#include <common.h> #include <asm/io.h> #include <asm/arch/clock.h> #include <asm/arch/prcm.h> diff --git a/arch/arm/mach-sunxi/clock_sun8i_a83t.c b/arch/arm/mach-sunxi/clock_sun8i_a83t.c index 31e4281..198fe9d 100644 --- a/arch/arm/mach-sunxi/clock_sun8i_a83t.c +++ b/arch/arm/mach-sunxi/clock_sun8i_a83t.c @@ -9,7 +9,6 @@ * (C) Copyright 2015 Vishnu Patekar <vishnupatekar0510@gmail.com> */ -#include <common.h> #include <asm/io.h> #include <asm/arch/clock.h> #include <asm/arch/prcm.h> diff --git a/arch/arm/mach-sunxi/clock_sun9i.c b/arch/arm/mach-sunxi/clock_sun9i.c index 8ba4802..edaff9a 100644 --- a/arch/arm/mach-sunxi/clock_sun9i.c +++ b/arch/arm/mach-sunxi/clock_sun9i.c @@ -9,7 +9,6 @@ * Philipp Tomsich <philipp.tomsich@theobroma-systems.com> */ -#include <common.h> #include <asm/io.h> #include <asm/arch/clock.h> #include <asm/arch/prcm.h> diff --git a/arch/arm/mach-sunxi/cpu_info.c b/arch/arm/mach-sunxi/cpu_info.c index 7fecc3b..310dca0 100644 --- a/arch/arm/mach-sunxi/cpu_info.c +++ b/arch/arm/mach-sunxi/cpu_info.c @@ -5,7 +5,6 @@ * Tom Cubie <tangliang@allwinnertech.com> */ -#include <common.h> #include <init.h> #include <asm/io.h> #include <asm/arch/cpu.h> diff --git a/arch/arm/mach-sunxi/dram_helpers.c b/arch/arm/mach-sunxi/dram_helpers.c index cdf2750..4a867df 100644 --- a/arch/arm/mach-sunxi/dram_helpers.c +++ b/arch/arm/mach-sunxi/dram_helpers.c @@ -5,8 +5,9 @@ * (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com> */ -#include <common.h> +#include <config.h> #include <time.h> +#include <vsprintf.h> #include <asm/barriers.h> #include <asm/io.h> #include <asm/arch/dram.h> diff --git a/arch/arm/mach-sunxi/dram_sun4i.c b/arch/arm/mach-sunxi/dram_sun4i.c index 80a6c4b..2cce381 100644 --- a/arch/arm/mach-sunxi/dram_sun4i.c +++ b/arch/arm/mach-sunxi/dram_sun4i.c @@ -20,7 +20,6 @@ * rather undocumented and full of magic. */ -#include <common.h> #include <init.h> #include <asm/io.h> #include <asm/arch/clock.h> diff --git a/arch/arm/mach-sunxi/dram_sun50i_h6.c b/arch/arm/mach-sunxi/dram_sun50i_h6.c index 62bc2a0..e7862bd 100644 --- a/arch/arm/mach-sunxi/dram_sun50i_h6.c +++ b/arch/arm/mach-sunxi/dram_sun50i_h6.c @@ -5,7 +5,6 @@ * (C) Copyright 2017 Icenowy Zheng <icenowy@aosc.io> * */ -#include <common.h> #include <init.h> #include <log.h> #include <asm/io.h> diff --git a/arch/arm/mach-sunxi/dram_sun50i_h616.c b/arch/arm/mach-sunxi/dram_sun50i_h616.c index e62d571..37c139e 100644 --- a/arch/arm/mach-sunxi/dram_sun50i_h616.c +++ b/arch/arm/mach-sunxi/dram_sun50i_h616.c @@ -12,7 +12,6 @@ * (C) Copyright 2020 Jernej Skrabec <jernej.skrabec@siol.net> * */ -#include <common.h> #include <init.h> #include <log.h> #include <asm/io.h> diff --git a/arch/arm/mach-sunxi/dram_sun6i.c b/arch/arm/mach-sunxi/dram_sun6i.c index 0590110..c023845 100644 --- a/arch/arm/mach-sunxi/dram_sun6i.c +++ b/arch/arm/mach-sunxi/dram_sun6i.c @@ -9,7 +9,6 @@ * * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com> */ -#include <common.h> #include <errno.h> #include <init.h> #include <asm/io.h> diff --git a/arch/arm/mach-sunxi/dram_sun8i_a23.c b/arch/arm/mach-sunxi/dram_sun8i_a23.c index 056cb03..1c3c6d8 100644 --- a/arch/arm/mach-sunxi/dram_sun8i_a23.c +++ b/arch/arm/mach-sunxi/dram_sun8i_a23.c @@ -19,7 +19,6 @@ * This may be used as a (possible) reference for future work / cleanups. */ -#include <common.h> #include <errno.h> #include <init.h> #include <asm/io.h> diff --git a/arch/arm/mach-sunxi/dram_sun8i_a33.c b/arch/arm/mach-sunxi/dram_sun8i_a33.c index 367b740..0d08b6a 100644 --- a/arch/arm/mach-sunxi/dram_sun8i_a33.c +++ b/arch/arm/mach-sunxi/dram_sun8i_a33.c @@ -7,7 +7,6 @@ * (C) Copyright 2015 Vishnu Patekar <vishnupatekar0510@gmail.com> * (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com> */ -#include <common.h> #include <errno.h> #include <init.h> #include <asm/io.h> diff --git a/arch/arm/mach-sunxi/dram_sun8i_a83t.c b/arch/arm/mach-sunxi/dram_sun8i_a83t.c index a3f833d..ef83332 100644 --- a/arch/arm/mach-sunxi/dram_sun8i_a83t.c +++ b/arch/arm/mach-sunxi/dram_sun8i_a83t.c @@ -7,7 +7,6 @@ * (C) Copyright 2015 Vishnu Patekar <vishnupatekar0510@gmail.com> * (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com> */ -#include <common.h> #include <errno.h> #include <init.h> #include <asm/io.h> diff --git a/arch/arm/mach-sunxi/dram_sun9i.c b/arch/arm/mach-sunxi/dram_sun9i.c index 14be212..002b6df 100644 --- a/arch/arm/mach-sunxi/dram_sun9i.c +++ b/arch/arm/mach-sunxi/dram_sun9i.c @@ -10,7 +10,6 @@ * Philipp Tomsich <philipp.tomsich@theobroma-systems.com> */ -#include <common.h> #include <dm.h> #include <errno.h> #include <init.h> diff --git a/arch/arm/mach-sunxi/dram_suniv.c b/arch/arm/mach-sunxi/dram_suniv.c index 9e583e1..640f872 100644 --- a/arch/arm/mach-sunxi/dram_suniv.c +++ b/arch/arm/mach-sunxi/dram_suniv.c @@ -9,7 +9,7 @@ * Copyright(c) 2007-2018 Jianjun Jiang <8192542@qq.com> */ -#include <common.h> +#include <config.h> #include <asm/io.h> #include <asm/arch/clock.h> #include <asm/arch/dram.h> diff --git a/arch/arm/mach-sunxi/dram_sunxi_dw.c b/arch/arm/mach-sunxi/dram_sunxi_dw.c index daef051..3bfcc63 100644 --- a/arch/arm/mach-sunxi/dram_sunxi_dw.c +++ b/arch/arm/mach-sunxi/dram_sunxi_dw.c @@ -8,7 +8,6 @@ * (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com> * (C) Copyright 2015 Jens Kuske <jenskuske@gmail.com> */ -#include <common.h> #include <init.h> #include <log.h> #include <asm/io.h> diff --git a/arch/arm/mach-sunxi/gtbus_sun9i.c b/arch/arm/mach-sunxi/gtbus_sun9i.c index 5624621..a058fea 100644 --- a/arch/arm/mach-sunxi/gtbus_sun9i.c +++ b/arch/arm/mach-sunxi/gtbus_sun9i.c @@ -6,7 +6,6 @@ * Philipp Tomsich <philipp.tomsich@theobroma-systems.com> */ -#include <common.h> #include <asm/io.h> #include <asm/arch/cpu.h> #include <asm/arch/gtbus_sun9i.h> diff --git a/arch/arm/mach-sunxi/pmic_bus.c b/arch/arm/mach-sunxi/pmic_bus.c index 8e7625f..87df312 100644 --- a/arch/arm/mach-sunxi/pmic_bus.c +++ b/arch/arm/mach-sunxi/pmic_bus.c @@ -9,7 +9,6 @@ */ #include <axp_pmic.h> -#include <common.h> #include <dm.h> #include <asm/arch/p2wi.h> #include <asm/arch/rsb.h> diff --git a/arch/arm/mach-sunxi/prcm.c b/arch/arm/mach-sunxi/prcm.c index 71a2e44..ef7c46e 100644 --- a/arch/arm/mach-sunxi/prcm.c +++ b/arch/arm/mach-sunxi/prcm.c @@ -13,7 +13,6 @@ * Tom Cubie <tangliang@allwinnertech.com> */ -#include <common.h> #include <errno.h> #include <asm/io.h> #include <asm/arch/cpu.h> diff --git a/arch/arm/mach-sunxi/spl_spi_sunxi.c b/arch/arm/mach-sunxi/spl_spi_sunxi.c index 267cb0b..72faa71 100644 --- a/arch/arm/mach-sunxi/spl_spi_sunxi.c +++ b/arch/arm/mach-sunxi/spl_spi_sunxi.c @@ -3,7 +3,6 @@ * Copyright (C) 2016 Siarhei Siamashka <siarhei.siamashka@gmail.com> */ -#include <common.h> #include <image.h> #include <log.h> #include <spl.h> diff --git a/arch/arm/mach-sunxi/timer.c b/arch/arm/mach-sunxi/timer.c index 9a6f6c0..1bbfad5 100644 --- a/arch/arm/mach-sunxi/timer.c +++ b/arch/arm/mach-sunxi/timer.c @@ -5,7 +5,6 @@ * Tom Cubie <tangliang@allwinnertech.com> */ -#include <common.h> #include <init.h> #include <time.h> #include <asm/global_data.h> diff --git a/common/spl/Kconfig b/common/spl/Kconfig index e7b84fc..6a4772e 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -97,8 +97,7 @@ config SPL_PAD_TO default 0x31000 if ARCH_MX6 && MX6_OCRAM_256KB default 0x11000 if ARCH_MX7 || (ARCH_MX6 && !MX6_OCRAM_256KB) default 0x10000 if ARCH_KEYSTONE - default 0x8000 if ARCH_SUNXI && !MACH_SUN50I_H616 - default 0x0 if ARCH_MTMIPS + default 0x0 if ARCH_MTMIPS || ARCH_SUNXI default TPL_MAX_SIZE if TPL_MAX_SIZE > SPL_MAX_SIZE default SPL_MAX_SIZE help @@ -585,8 +584,7 @@ config SYS_MMCSD_RAW_MODE_EMMC_BOOT_PARTITION config SPL_FIT_IMAGE_TINY bool "Remove functionality from SPL FIT loading to reduce size" depends on SPL_FIT - default y if MACH_SUN50I || MACH_SUN50I_H5 || SUN50I_GEN_H6 - default y if ARCH_IMX8M || ARCH_IMX9 + default y if ARCH_IMX8M || ARCH_IMX9 || ARCH_SUNXI help Enable this to reduce the size of the FIT image loading code in SPL, if space for the SPL binary is very tight. diff --git a/configs/nanopi_duo2_defconfig b/configs/nanopi_duo2_defconfig new file mode 100644 index 0000000..beb2f92 --- /dev/null +++ b/configs/nanopi_duo2_defconfig @@ -0,0 +1,12 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-nanopi-duo2" +CONFIG_SPL=y +CONFIG_MACH_SUN8I_H3=y +CONFIG_DRAM_CLK=408 +# CONFIG_VIDEO_DE2 is not set +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_CONSOLE_MUX=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_MUSB_GADGET=y diff --git a/configs/transpeed-8k618-t_defconfig b/configs/transpeed-8k618-t_defconfig new file mode 100644 index 0000000..020d397 --- /dev/null +++ b/configs/transpeed-8k618-t_defconfig @@ -0,0 +1,27 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_DEFAULT_DEVICE_TREE="sun50i-h618-transpeed-8k618-t" +CONFIG_SPL=y +CONFIG_DRAM_SUN50I_H616_DX_ODT=0x03030303 +CONFIG_DRAM_SUN50I_H616_DX_DRI=0x0e0e0e0e +CONFIG_DRAM_SUN50I_H616_CA_DRI=0x1f12 +CONFIG_DRAM_SUN50I_H616_TPR0=0xc0001002 +CONFIG_DRAM_SUN50I_H616_TPR10=0x2f1107 +CONFIG_DRAM_SUN50I_H616_TPR11=0xddddcccc +CONFIG_DRAM_SUN50I_H616_TPR12=0xeddc7665 +CONFIG_MACH_SUN50I_H616=y +CONFIG_SUNXI_DRAM_H616_DDR3_1333=y +CONFIG_DRAM_CLK=648 +CONFIG_MMC_SUNXI_SLOT_EXTRA=2 +CONFIG_R_I2C_ENABLE=y +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_SYS_I2C_SLAVE=0x7f +CONFIG_SYS_I2C_SPEED=400000 +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_AXP313_POWER=y +CONFIG_AXP_DCDC3_VOLT=1360 +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_OHCI_HCD=y diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c index a12f7e3..8bff4fe 100644 --- a/drivers/net/sun8i_emac.c +++ b/drivers/net/sun8i_emac.c @@ -833,11 +833,8 @@ static int sun8i_emac_eth_of_to_plat(struct udevice *dev) priv->use_internal_phy = false; offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "phy-handle"); - if (offset < 0) { - debug("%s: Cannot find PHY address\n", __func__); - return -EINVAL; - } - priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1); + if (offset >= 0) + priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1); pdata->phy_interface = dev_read_phy_mode(dev); debug("phy interface %d\n", pdata->phy_interface); diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index b8ca77d..b29a25d 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -14,8 +14,9 @@ #include <linux/stringify.h> -/* Serial & console */ -/* ns16550 reg in the low bits of cpu reg */ +/**************************************************************************** + * base addresses for the SPL UART driver * + ****************************************************************************/ #ifdef CONFIG_MACH_SUNIV /* suniv doesn't have apb2 and uart is connected to apb1 */ #define CFG_SYS_NS16550_CLK 100000000 @@ -31,8 +32,9 @@ # define CFG_SYS_NS16550_COM5 SUNXI_R_UART_BASE #endif -/* CPU */ - +/**************************************************************************** + * DRAM base address * + ****************************************************************************/ /* * The DRAM Base differs between some models. We cannot use macros for the * CONFIG_FOO defines which contain the DRAM base address since they end @@ -52,16 +54,6 @@ /* V3s do not have enough memory to place code at 0x4a000000 */ #endif -/* - * The A80's A1 sram starts at 0x00010000 rather then at 0x00000000 and is - * slightly bigger. Note that it is possible to map the first 32 KiB of the - * A1 at 0x00000000 like with older SoCs by writing 0x16aa0001 to the - * undocumented 0x008000e0 SYS_CTRL register. Where the 16aa is a key and - * the 1 actually activates the mapping of the first 32 KiB to 0x00000000. - * A64 and H5 also has SRAM A1 at 0x00010000, but no magic remap register - * is known yet. - * H6 has SRAM A1 at 0x00020000. - */ #define CFG_SYS_INIT_RAM_ADDR CONFIG_SUNXI_SRAM_ADDRESS /* FIXME: this may be larger on some SoCs */ #define CFG_SYS_INIT_RAM_SIZE 0x8000 /* 32 KiB */ @@ -69,36 +61,13 @@ #define PHYS_SDRAM_0 CFG_SYS_SDRAM_BASE #define PHYS_SDRAM_0_SIZE 0x80000000 /* 2 GiB */ -/* - * Miscellaneous configurable options - */ - -/* FLASH and environment organization */ - +/**************************************************************************** + * environment variables holding default load addresses * + ****************************************************************************/ /* * We cannot use expressions here, because expressions won't be evaluated in * autoconf.mk. */ -#if CONFIG_SUNXI_SRAM_ADDRESS == 0x10000 -#ifdef CONFIG_ARM64 -/* end of SRAM A2 for now, as SRAM A1 is pretty tight for an ARM64 build */ -#define LOW_LEVEL_SRAM_STACK 0x00054000 -#else -#define LOW_LEVEL_SRAM_STACK 0x00018000 -#endif /* !CONFIG_ARM64 */ -#elif CONFIG_SUNXI_SRAM_ADDRESS == 0x20000 -#ifdef CONFIG_MACH_SUN50I_H616 -#define LOW_LEVEL_SRAM_STACK 0x52a00 /* below FEL buffers */ -#else -/* end of SRAM A2 on H6 for now */ -#define LOW_LEVEL_SRAM_STACK 0x00118000 -#endif -#else -#define LOW_LEVEL_SRAM_STACK 0x00008000 /* End of sram */ -#endif - -/* Ethernet support */ - #ifdef CONFIG_ARM64 /* * Boards seem to come with at least 512MB of DRAM. @@ -174,15 +143,11 @@ "ramdisk_addr_r=" RAMDISK_ADDR_R "\0" #ifdef CONFIG_ARM64 - #define MEM_LAYOUT_ENV_EXTRA_SETTINGS \ "kernel_comp_addr_r=" KERNEL_COMP_ADDR_R "\0" \ "kernel_comp_size=" KERNEL_COMP_SIZE "\0" - #else - #define MEM_LAYOUT_ENV_EXTRA_SETTINGS "" - #endif #define DFU_ALT_INFO_RAM \ @@ -191,6 +156,9 @@ "fdt ram " FDT_ADDR_R " 0x100000;" \ "ramdisk ram " RAMDISK_ADDR_R " 0x4000000\0" +/**************************************************************************** + * definitions for the distro boot system * + ****************************************************************************/ #ifdef CONFIG_MMC #if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1 #define BOOTENV_DEV_MMC_AUTO(devtypeu, devtypel, instance) \ |