diff options
| -rw-r--r-- | arch/x86/cpu/baytrail/valleyview.c | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/arch/x86/cpu/baytrail/valleyview.c b/arch/x86/cpu/baytrail/valleyview.c index c58f6a8..9af1bda 100644 --- a/arch/x86/cpu/baytrail/valleyview.c +++ b/arch/x86/cpu/baytrail/valleyview.c @@ -10,6 +10,13 @@ #include <asm/irq.h> #include <asm/mrccache.h> #include <asm/post.h> +#include <asm/arch/iomap.h> + +/* GPIO SUS */ +#define GPIO_SUS_PAD_BASE (IO_BASE_ADDRESS + IO_BASE_OFFSET_GPSSUS) +#define GPIO_SUS_DFX5_CONF0 0x150 +#define BYT_TRIG_LVL BIT(24) +#define BYT_TRIG_POS BIT(25) #ifndef CONFIG_EFI_APP int arch_cpu_init(void) @@ -33,6 +40,21 @@ int arch_misc_init(void) mrccache_save(); #endif + /* + * For some unknown reason, FSP (gold4) for BayTrail configures + * the GPIO DFX5 PAD to enable level interrupt (bit 24 and 25). + * This does not cause any issue when Linux kernel runs w/ or w/o + * the pinctrl driver for BayTrail. However this causes unstable + * S3 resume if the pinctrl driver is included in the kernel build. + * As this pin keeps generating interrupts during an S3 resume, + * and there is no IRQ requester in the kernel to handle it, the + * kernel seems to hang and does not continue resuming. + * + * Clear the mysterious interrupt bits for this pin. + */ + clrbits_le32(GPIO_SUS_PAD_BASE + GPIO_SUS_DFX5_CONF0, + BYT_TRIG_LVL | BYT_TRIG_POS); + return 0; } |