diff options
| -rw-r--r-- | arch/arm/cpu/armv7/sunxi/psci.c | 2 | ||||
| -rw-r--r-- | arch/arm/include/asm/system.h | 15 | ||||
| -rw-r--r-- | arch/arm/mach-imx/mx7/psci-mx7.c | 2 | ||||
| -rw-r--r-- | arch/arm/mach-stm32mp/psci.c | 18 | ||||
| -rw-r--r-- | arch/arm/mach-uniphier/arm32/psci.c | 4 |
5 files changed, 28 insertions, 13 deletions
diff --git a/arch/arm/cpu/armv7/sunxi/psci.c b/arch/arm/cpu/armv7/sunxi/psci.c index f3e8f99..2c5d99e 100644 --- a/arch/arm/cpu/armv7/sunxi/psci.c +++ b/arch/arm/cpu/armv7/sunxi/psci.c @@ -276,7 +276,7 @@ int __secure psci_cpu_on(u32 __always_unused unused, u32 mpidr, u32 pc, return ARM_PSCI_RET_SUCCESS; } -void __secure psci_cpu_off(void) +s32 __secure psci_cpu_off(void) { psci_cpu_off_common(); diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index aed2e3c..a1a5e35 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -516,6 +516,21 @@ enum { */ void mmu_page_table_flush(unsigned long start, unsigned long stop); +#ifdef CONFIG_ARMV7_PSCI +void psci_arch_cpu_entry(void); +u32 psci_version(void); +s32 psci_features(u32 function_id, u32 psci_fid); +s32 psci_cpu_off(void); +s32 psci_cpu_on(u32 function_id, u32 target_cpu, u32 pc, + u32 context_id); +s32 psci_affinity_info(u32 function_id, u32 target_affinity, + u32 lowest_affinity_level); +u32 psci_migrate_info_type(void); +void psci_system_off(void); +void psci_system_reset(void); +s32 psci_features(u32 function_id, u32 psci_fid); +#endif + #endif /* __ASSEMBLY__ */ #define arch_align_stack(x) (x) diff --git a/arch/arm/mach-imx/mx7/psci-mx7.c b/arch/arm/mach-imx/mx7/psci-mx7.c index 34ba0a9..c98d2e9 100644 --- a/arch/arm/mach-imx/mx7/psci-mx7.c +++ b/arch/arm/mach-imx/mx7/psci-mx7.c @@ -298,7 +298,7 @@ __secure s32 psci_affinity_info(u32 __always_unused function_id, return psci_state[cpu]; } -__secure s32 psci_migrate_info_type(u32 function_id) +__secure u32 psci_migrate_info_type(void) { /* Trusted OS is either not present or does not require migration */ return 2; diff --git a/arch/arm/mach-stm32mp/psci.c b/arch/arm/mach-stm32mp/psci.c index 139bb09..1d91b2d 100644 --- a/arch/arm/mach-stm32mp/psci.c +++ b/arch/arm/mach-stm32mp/psci.c @@ -30,7 +30,7 @@ u8 psci_state[STM32MP1_PSCI_NR_CPUS] __secure_data = { PSCI_AFFINITY_LEVEL_ON, PSCI_AFFINITY_LEVEL_OFF}; -void __secure psci_set_state(int cpu, u8 state) +static inline void psci_set_state(int cpu, u8 state) { psci_state[cpu] = state; dsb(); @@ -67,7 +67,7 @@ void __secure psci_arch_cpu_entry(void) writel(0xFFFFFFFF, TAMP_BACKUP_MAGIC_NUMBER); } -int __secure psci_features(u32 function_id, u32 psci_fid) +s32 __secure psci_features(u32 function_id, u32 psci_fid) { switch (psci_fid) { case ARM_PSCI_0_2_FN_PSCI_VERSION: @@ -82,12 +82,12 @@ int __secure psci_features(u32 function_id, u32 psci_fid) return ARM_PSCI_RET_NI; } -unsigned int __secure psci_version(u32 function_id) +u32 __secure psci_version(void) { return ARM_PSCI_VER_1_0; } -int __secure psci_affinity_info(u32 function_id, u32 target_affinity, +s32 __secure psci_affinity_info(u32 function_id, u32 target_affinity, u32 lowest_affinity_level) { u32 cpu = target_affinity & MPIDR_AFF0; @@ -104,7 +104,7 @@ int __secure psci_affinity_info(u32 function_id, u32 target_affinity, return psci_state[cpu]; } -int __secure psci_migrate_info_type(u32 function_id) +u32 __secure psci_migrate_info_type(void) { /* * in Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf @@ -116,7 +116,7 @@ int __secure psci_migrate_info_type(u32 function_id) return 2; } -int __secure psci_cpu_on(u32 function_id, u32 target_cpu, u32 pc, +s32 __secure psci_cpu_on(u32 function_id, u32 target_cpu, u32 pc, u32 context_id) { u32 cpu = target_cpu & MPIDR_AFF0; @@ -161,7 +161,7 @@ int __secure psci_cpu_on(u32 function_id, u32 target_cpu, u32 pc, return ARM_PSCI_RET_SUCCESS; } -int __secure psci_cpu_off(u32 function_id) +s32 __secure psci_cpu_off(void) { u32 cpu; @@ -181,7 +181,7 @@ int __secure psci_cpu_off(u32 function_id) wfi(); } -void __secure psci_system_reset(u32 function_id) +void __secure psci_system_reset(void) { /* System reset */ writel(RCC_MP_GRSTCSETR_MPSYSRST, RCC_MP_GRSTCSETR); @@ -190,7 +190,7 @@ void __secure psci_system_reset(u32 function_id) wfi(); } -void __secure psci_system_off(u32 function_id) +void __secure psci_system_off(void) { /* System Off is not managed, waiting user power off * TODO: handle I2C write in PMIC Main Control register bit 0 = SWOFF diff --git a/arch/arm/mach-uniphier/arm32/psci.c b/arch/arm/mach-uniphier/arm32/psci.c index 3f67edf..ef35923 100644 --- a/arch/arm/mach-uniphier/arm32/psci.c +++ b/arch/arm/mach-uniphier/arm32/psci.c @@ -130,7 +130,7 @@ void psci_arch_init(void) u32 uniphier_psci_holding_pen_release __secure_data = 0xffffffff; -int __secure psci_cpu_on(u32 function_id, u32 cpuid, u32 entry_point, +s32 __secure psci_cpu_on(u32 function_id, u32 cpuid, u32 entry_point, u32 context_id) { u32 cpu = cpuid & 0xff; @@ -155,7 +155,7 @@ int __secure psci_cpu_on(u32 function_id, u32 cpuid, u32 entry_point, return PSCI_RET_SUCCESS; } -void __secure psci_system_reset(u32 function_id) +void __secure psci_system_reset(void) { reset_cpu(0); } |