diff options
| -rw-r--r-- | arch/arm/mach-rockchip/Kconfig | 2 | ||||
| -rw-r--r-- | arch/arm/mach-rockchip/Makefile | 1 | ||||
| -rw-r--r-- | arch/arm/mach-rockchip/rk3188-board-spl.c | 10 | ||||
| -rw-r--r-- | arch/arm/mach-rockchip/rk3188-board-tpl.c | 86 | ||||
| -rw-r--r-- | doc/README.rockchip | 10 | ||||
| -rw-r--r-- | include/configs/rk3188_common.h | 12 |
6 files changed, 9 insertions, 112 deletions
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index d59a1d5..09f2c45 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -18,7 +18,7 @@ config ROCKCHIP_RK3188 select SUPPORT_SPL select SUPPORT_TPL select SPL - select TPL + select SPL_ROCKCHIP_EARLYRETURN_TO_BROM select BOARD_LATE_INIT select ROCKCHIP_BROM_HELPER help diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile index b875dfc..c15e9bf 100644 --- a/arch/arm/mach-rockchip/Makefile +++ b/arch/arm/mach-rockchip/Makefile @@ -11,7 +11,6 @@ obj-spl-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o obj-tpl-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o -obj-tpl-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-tpl.o obj-tpl-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-tpl.o obj-tpl-$(CONFIG_ROCKCHIP_RK3368) += rk3368-board-tpl.o diff --git a/arch/arm/mach-rockchip/rk3188-board-spl.c b/arch/arm/mach-rockchip/rk3188-board-spl.c index 406207e..05d4ae6 100644 --- a/arch/arm/mach-rockchip/rk3188-board-spl.c +++ b/arch/arm/mach-rockchip/rk3188-board-spl.c @@ -101,7 +101,6 @@ static int setup_arm_clock(void) void board_init_f(ulong dummy) { struct udevice *pinctrl, *dev; - struct rk3188_pmu *pmu; int ret; /* Example code showing how to enable the debug UART on RK3188 */ @@ -145,15 +144,6 @@ void board_init_f(ulong dummy) return; } - /* - * Recover the bootrom's stackpointer. - * For whatever reason needs to run after rockchip_get_clk. - */ - pmu = syscon_get_first_range(ROCKCHIP_SYSCON_PMU); - if (IS_ERR(pmu)) - pr_err("pmu syscon returned %ld\n", PTR_ERR(pmu)); - SAVE_SP_ADDR = readl(&pmu->sys_reg[2]); - ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); if (ret) { debug("Pinctrl init failed: %d\n", ret); diff --git a/arch/arm/mach-rockchip/rk3188-board-tpl.c b/arch/arm/mach-rockchip/rk3188-board-tpl.c deleted file mode 100644 index b458ef6..0000000 --- a/arch/arm/mach-rockchip/rk3188-board-tpl.c +++ /dev/null @@ -1,86 +0,0 @@ -/* - * (C) Copyright 2015 Google, Inc - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <debug_uart.h> -#include <spl.h> -#include <asm/io.h> -#include <asm/arch/bootrom.h> -#include <asm/arch/pmu_rk3188.h> - -DECLARE_GLOBAL_DATA_PTR; - -/* track how often we were entered */ -static int rk3188_num_entries __attribute__ ((section(".data"))); - -#define PMU_BASE 0x20004000 -#define SPL_ENTRY 0x10080C00 - -static void jump_to_spl(void) -{ - typedef void __noreturn (*image_entry_noargs_t)(void); - - struct rk3188_pmu * const pmu = (void *)PMU_BASE; - image_entry_noargs_t tpl_entry = - (image_entry_noargs_t)(unsigned long)SPL_ENTRY; - - /* Store the SAVE_SP_ADDR in a location shared with SPL. */ - writel(SAVE_SP_ADDR, &pmu->sys_reg[2]); - tpl_entry(); -} - -void board_init_f(ulong dummy) -{ - /* Example code showing how to enable the debug UART on RK3188 */ -#ifdef EARLY_UART -#include <asm/arch/grf_rk3188.h> - /* Enable early UART on the RK3188 */ -#define GRF_BASE 0x20008000 - struct rk3188_grf * const grf = (void *)GRF_BASE; - - rk_clrsetreg(&grf->gpio1b_iomux, - GPIO1B1_MASK << GPIO1B1_SHIFT | - GPIO1B0_MASK << GPIO1B0_SHIFT, - GPIO1B1_UART2_SOUT << GPIO1B1_SHIFT | - GPIO1B0_UART2_SIN << GPIO1B0_SHIFT); - /* - * Debug UART can be used from here if required: - * - * debug_uart_init(); - * printch('a'); - * printhex8(0x1234); - * printascii("string"); - */ - debug_uart_init(); - - printch('t'); - printch('p'); - printch('l'); - printch('-'); - printch(rk3188_num_entries + 1 + '0'); - printch('\n'); -#endif - - rk3188_num_entries++; - - if (rk3188_num_entries == 1) { - /* - * The original loader did some very basic integrity - * checking at this point, but the remaining few bytes - * could be used for any improvement making sense - * really early on. - */ - - back_to_bootrom(); - } else { - /* - * TPL part of the loader should now wait for us - * at offset 0xC00 in the sram. Should never return - * from there. - */ - jump_to_spl(); - } -} diff --git a/doc/README.rockchip b/doc/README.rockchip index da99f30..597f068 100644 --- a/doc/README.rockchip +++ b/doc/README.rockchip @@ -176,17 +176,17 @@ described above, but the image creation needs a bit more care. The bootrom of rk3188 expects to find a small 1kb loader which returns control to the bootrom, after which it will load the real loader, which -can then be up to 29kb in size and does the regular ddr init. +can then be up to 29kb in size and does the regular ddr init. This is +handled by a single image (built as the SPL stage) that tests whether +it is handled for the first or second time via code executed from the +boot0-hook. Additionally the rk3188 requires everything the bootrom loads to be rc4-encrypted. Except for the very first stage the bootrom always reads and decodes 2kb pages, so files should be sized accordingly. # copy tpl, pad to 1020 bytes and append spl -cat tpl/u-boot-tpl.bin > tplspl.bin -truncate -s 1020 tplspl.bin -cat spl/u-boot-spl.bin >> tplspl.bin -tools/mkimage -n rk3188 -T rksd -d tplspl.bin out +tools/mkimage -n rk3188 -T rksd -d spl/u-boot-spl.bin out # truncate, encode and append u-boot.bin truncate -s %2048 u-boot.bin diff --git a/include/configs/rk3188_common.h b/include/configs/rk3188_common.h index cfa5364..68a42a9 100644 --- a/include/configs/rk3188_common.h +++ b/include/configs/rk3188_common.h @@ -36,14 +36,9 @@ #define CONFIG_ROCKCHIP_MAX_INIT_SIZE (0x8000 - 0x800) #define CONFIG_ROCKCHIP_CHIP_TAG "RK31" -#ifdef CONFIG_TPL_BUILD -#define CONFIG_SPL_TEXT_BASE 0x10080804 -/* tpl size 1kb - 4byte RK31 header */ -#define CONFIG_SPL_MAX_SIZE (0x400 - 0x4) -#elif defined(CONFIG_SPL_BUILD) -/* spl size 32kb sram - 2kb bootrom - 1kb spl */ -#define CONFIG_SPL_MAX_SIZE (0x8000 - 0xC00) -#define CONFIG_SPL_TEXT_BASE 0x10080C00 +#define CONFIG_SPL_TEXT_BASE 0x10080800 +/* spl size 32kb sram - 2kb bootrom */ +#define CONFIG_SPL_MAX_SIZE (0x8000 - 0x800) #define CONFIG_SPL_FRAMEWORK 1 #define CONFIG_SPL_CLK 1 #define CONFIG_SPL_PINCTRL 1 @@ -52,7 +47,6 @@ #define CONFIG_SPL_RAM 1 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT 1 #define CONFIG_ROCKCHIP_SERIAL 1 -#endif #define CONFIG_SPL_STACK 0x10087fff |