diff options
| -rw-r--r-- | arch/arm/mach-omap2/emif-common.c | 34 |
1 files changed, 21 insertions, 13 deletions
diff --git a/arch/arm/mach-omap2/emif-common.c b/arch/arm/mach-omap2/emif-common.c index 9bdaa38..290f9dc 100644 --- a/arch/arm/mach-omap2/emif-common.c +++ b/arch/arm/mach-omap2/emif-common.c @@ -348,7 +348,7 @@ static void dra7_reset_ddr_data(u32 base, u32 size) static void dra7_enable_ecc(u32 base, const struct emif_regs *regs) { struct emif_reg_struct *emif = (struct emif_reg_struct *)base; - u32 rgn, rgn_start, size; + u32 rgn, rgn_start, size, ctrl_reg; /* ECC available only on dra76x EMIF1 */ if ((base != EMIF1_BASE) || !is_dra76x()) @@ -358,11 +358,28 @@ static void dra7_enable_ecc(u32 base, const struct emif_regs *regs) /* Disable high-order interleaving */ clrbits_le32(MA_PRIORITY, MA_HIMEM_INTERLEAVE_UN_MASK); +#ifdef CONFIG_DRA7XX + /* Clear the status flags and other history */ + writel(readl(&emif->emif_1b_ecc_err_cnt), + &emif->emif_1b_ecc_err_cnt); + writel(0xffffffff, &emif->emif_1b_ecc_err_dist_1); + writel(0x2, &emif->emif_1b_ecc_err_addr_log); + writel(0x1, &emif->emif_2b_ecc_err_addr_log); + writel(EMIF_INT_WR_ECC_ERR_SYS_MASK | + EMIF_INT_TWOBIT_ECC_ERR_SYS_MASK | + EMIF_INT_ONEBIT_ECC_ERR_SYS_MASK, + &emif->emif_irqstatus_sys); +#endif writel(regs->emif_ecc_address_range_1, &emif->emif_ecc_address_range_1); writel(regs->emif_ecc_address_range_2, &emif->emif_ecc_address_range_2); - writel(regs->emif_ecc_ctrl_reg, &emif->emif_ecc_ctrl_reg); + + /* Disable RMW and ECC verification for read accesses */ + ctrl_reg = (regs->emif_ecc_ctrl_reg & + ~EMIF_ECC_REG_RMW_EN_MASK) | + EMIF_ECC_CTRL_REG_ECC_VERIFY_DIS_MASK; + writel(ctrl_reg, &emif->emif_ecc_ctrl_reg); /* Set region1 memory with 0 */ rgn_start = (regs->emif_ecc_address_range_1 & @@ -386,17 +403,8 @@ static void dra7_enable_ecc(u32 base, const struct emif_regs *regs) EMIF_ECC_REG_ECC_ADDR_RGN_2_EN_MASK) dra7_reset_ddr_data(rgn, size); -#ifdef CONFIG_DRA7XX - /* Clear the status flags and other history */ - writel(readl(&emif->emif_1b_ecc_err_cnt), - &emif->emif_1b_ecc_err_cnt); - writel(0xffffffff, &emif->emif_1b_ecc_err_dist_1); - writel(0x1, &emif->emif_2b_ecc_err_addr_log); - writel(EMIF_INT_WR_ECC_ERR_SYS_MASK | - EMIF_INT_TWOBIT_ECC_ERR_SYS_MASK | - EMIF_INT_ONEBIT_ECC_ERR_SYS_MASK, - &emif->emif_irqstatus_sys); -#endif + /* Default value enables RMW and ECC verification */ + writel(regs->emif_ecc_ctrl_reg, &emif->emif_ecc_ctrl_reg); } } |