diff options
192 files changed, 2162 insertions, 462 deletions
diff --git a/.azure-pipelines.yml b/.azure-pipelines.yml index 06c46b6..b7dc7e8 100644 --- a/.azure-pipelines.yml +++ b/.azure-pipelines.yml @@ -2,7 +2,7 @@ variables: windows_vm: windows-2019 ubuntu_vm: ubuntu-22.04 macos_vm: macOS-12 - ci_runner_image: trini/u-boot-gitlab-ci-runner:jammy-20230308-04Apr2023 + ci_runner_image: trini/u-boot-gitlab-ci-runner:jammy-20230624-20Jul2023 # Add '-u 0' options for Azure pipelines, otherwise we get "permission # denied" error when it tries to "useradd -m -u 1001 vsts_azpcontainer", # since our $(ci_runner_image) user is not root. @@ -194,7 +194,7 @@ stages: ln -s /opt/nokia/libc6_2.5.1-1eglibc27+0m5_armel.deb nokia_rx51_tmp/ ln -s /opt/nokia/busybox_1.10.2.legal-1osso30+0m5_armel.deb nokia_rx51_tmp/ ln -s /opt/nokia/qemu-system-arm nokia_rx51_tmp/ - export PATH=/opt/gcc-12.2.0-nolibc/arm-linux-gnueabi/bin:$PATH + export PATH=/opt/gcc-13.1.0-nolibc/arm-linux-gnueabi/bin:$PATH test/nokia_rx51_test.sh - job: pylint @@ -460,6 +460,7 @@ stages: fi # Some tests using libguestfs-tools need the fuse device to run docker run "$@" --device /dev/fuse:/dev/fuse -v $PWD:$(work_dir) $(ci_runner_image) /bin/bash $(work_dir)/test.sh + retryCountOnTaskFailure: 2 # QEMU may be too slow, etc. - stage: world_build jobs: @@ -506,7 +507,7 @@ stages: imx: BUILDMAN: "mx -x mx6,imx8,freescale,technexion,toradex" imx8_imx9: - BUILDMAN: "imx8 imx9" + BUILDMAN: "imx8 imx9 -x engicam,technexion,toradex" keymile: BUILDMAN: "keymile" keystone2_keystone3: @@ -563,10 +564,10 @@ stages: BUILDMAN: "uniphier" aarch64_catch_all: BUILDMAN: "aarch64 -x amlogic,bcm,imx8,imx9,k3,tegra,ls1,ls2,lx216,mvebu,uniphier,renesas,sunxi,samsung,socfpga,rk,versal,zynq" - rockchip_32bit: - BUILDMAN: "rk -x aarch64" - rockchip_64bit: - BUILDMAN: "rk&aarch64" + rk_rv_non_rockchip: + BUILDMAN: "rk|rv -x rockchip" + rk_rv_and_rockchip: + BUILDMAN: "(rk|rv)&rockchip" renesas: BUILDMAN: "renesas" zynq: diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index cfd5851..98195c7 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -10,7 +10,7 @@ default: # Grab our configured image. The source for this is found # in the u-boot tree at tools/docker/Dockerfile -image: ${MIRROR_DOCKER}/trini/u-boot-gitlab-ci-runner:jammy-20230308-04Apr2023 +image: ${MIRROR_DOCKER}/trini/u-boot-gitlab-ci-runner:jammy-20230624-20Jul2023 # We run some tests in different order, to catch some failures quicker. stages: @@ -20,6 +20,7 @@ stages: .buildman_and_testpy_template: &buildman_and_testpy_dfn stage: test.py + retry: 2 # QEMU may be too slow, etc. before_script: # Clone uboot-test-hooks - git config --global --add safe.directory "${CI_PROJECT_DIR}" @@ -231,7 +232,7 @@ Run tests for Nokia RX-51 (aka N900): ln -s /opt/nokia/libc6_2.5.1-1eglibc27+0m5_armel.deb nokia_rx51_tmp/; ln -s /opt/nokia/busybox_1.10.2.legal-1osso30+0m5_armel.deb nokia_rx51_tmp/; ln -s /opt/nokia/qemu-system-arm nokia_rx51_tmp/; - export PATH=/opt/gcc-12.2.0-nolibc/arm-linux-gnueabi/bin:$PATH; + export PATH=/opt/gcc-13.1.0-nolibc/arm-linux-gnueabi/bin:$PATH; test/nokia_rx51_test.sh # Check for any pylint regressions diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 07b26df..b13b26b 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -416,6 +416,9 @@ dtb-$(CONFIG_ARCH_VERSAL) += \ xilinx-versal-virt.dtb dtb-$(CONFIG_ARCH_VERSAL_NET) += \ versal-net-mini.dtb \ + versal-net-mini-emmc.dtb \ + versal-net-mini-ospi-single.dtb \ + versal-net-mini-qspi-single.dtb \ xilinx-versal-net-virt.dtb dtb-$(CONFIG_ARCH_ZYNQMP_R5) += \ zynqmp-r5.dtb diff --git a/arch/arm/dts/avnet-ultra96-rev1.dts b/arch/arm/dts/avnet-ultra96-rev1.dts index ddb8feb..96a6403 100644 --- a/arch/arm/dts/avnet-ultra96-rev1.dts +++ b/arch/arm/dts/avnet-ultra96-rev1.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2018 - 2020, Xilinx, Inc. * - * Michal Simek <michal.simek@xilinx.com> + * Michal Simek <michal.simek@amd.com> */ /dts-v1/; diff --git a/arch/arm/dts/stm32mp15-u-boot.dtsi b/arch/arm/dts/stm32mp15-u-boot.dtsi index d872c6f..573dd4d 100644 --- a/arch/arm/dts/stm32mp15-u-boot.dtsi +++ b/arch/arm/dts/stm32mp15-u-boot.dtsi @@ -226,6 +226,7 @@ mkimage { args = "-T stm32image -a 0x2ffc2500 -e 0x2ffc2500"; u-boot-spl { + no-write-symbols; }; }; }; diff --git a/arch/arm/dts/versal-mini-emmc0.dts b/arch/arm/dts/versal-mini-emmc0.dts index 1863d29..bd685dd 100644 --- a/arch/arm/dts/versal-mini-emmc0.dts +++ b/arch/arm/dts/versal-mini-emmc0.dts @@ -4,8 +4,8 @@ * * (C) Copyright 2018-2019, Xilinx, Inc. * - * Siva Durga Prasad <siva.durga.paladugu@xilinx.com> - * Michal Simek <michal.simek@xilinx.com> + * Siva Durga Prasad <siva.durga.prasad.paladugu@amd.com>> + * Michal Simek <michal.simek@amd.com> */ /dts-v1/; diff --git a/arch/arm/dts/versal-mini-emmc1.dts b/arch/arm/dts/versal-mini-emmc1.dts index 8701c3b..fbdcf5d 100644 --- a/arch/arm/dts/versal-mini-emmc1.dts +++ b/arch/arm/dts/versal-mini-emmc1.dts @@ -4,8 +4,8 @@ * * (C) Copyright 2018-2019, Xilinx, Inc. * - * Siva Durga Prasad <siva.durga.paladugu@xilinx.com> - * Michal Simek <michal.simek@xilinx.com> + * Siva Durga Prasad <siva.durga.prasad.paladugu@amd.com>> + * Michal Simek <michal.simek@amd.com> */ /dts-v1/; diff --git a/arch/arm/dts/versal-mini-ospi.dtsi b/arch/arm/dts/versal-mini-ospi.dtsi index 2d04521..19caea7 100644 --- a/arch/arm/dts/versal-mini-ospi.dtsi +++ b/arch/arm/dts/versal-mini-ospi.dtsi @@ -4,8 +4,8 @@ * * (C) Copyright 2018-2019, Xilinx, Inc. * - * Siva Durga Prasad <siva.durga.paladugu@xilinx.com> - * Michal Simek <michal.simek@xilinx.com> + * Siva Durga Prasad <siva.durga.prasad.paladugu@amd.com>> + * Michal Simek <michal.simek@amd.com> */ /dts-v1/; diff --git a/arch/arm/dts/versal-mini-qspi.dtsi b/arch/arm/dts/versal-mini-qspi.dtsi index bb8819d..2fec92c 100644 --- a/arch/arm/dts/versal-mini-qspi.dtsi +++ b/arch/arm/dts/versal-mini-qspi.dtsi @@ -4,8 +4,8 @@ * * (C) Copyright 2018-2019, Xilinx, Inc. * - * Siva Durga Prasad <siva.durga.paladugu@xilinx.com> - * Michal Simek <michal.simek@xilinx.com> + * Siva Durga Prasad <siva.durga.prasad.paladugu@amd.com>> + * Michal Simek <michal.simek@amd.com> */ /dts-v1/; diff --git a/arch/arm/dts/versal-mini.dts b/arch/arm/dts/versal-mini.dts index 769eb9e..a213b74 100644 --- a/arch/arm/dts/versal-mini.dts +++ b/arch/arm/dts/versal-mini.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2019, Xilinx, Inc. * - * Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> + * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>> */ /dts-v1/; diff --git a/arch/arm/dts/versal-net-mini-emmc.dts b/arch/arm/dts/versal-net-mini-emmc.dts new file mode 100644 index 0000000..8a864ba --- /dev/null +++ b/arch/arm/dts/versal-net-mini-emmc.dts @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for Xilinx Versal NET Mini eMMC Configuration + * + * (C) Copyright 2023, Advanced Micro Devices, Inc. + * + * Michal Simek <michal.simek@amd.com> + * Ashok Reddy Soma <ashok.reddy.soma@amd.com> + */ + +/dts-v1/; + +/ { + compatible = "xlnx,versal-net-mini"; + #address-cells = <2>; + #size-cells = <2>; + model = "Xilinx Versal NET MINI eMMC"; + + aliases { + serial0 = &dcc; + mmc0 = &sdhci1; + }; + + chosen { + stdout-path = "serial0:115200"; + }; + + memory@0 { + device_type = "memory"; + reg = <0 0 0 0x20000000>; + }; + + clk200: clk200 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; + + dcc: dcc { + compatible = "arm,dcc"; + status = "okay"; + bootph-all; + }; + + amba: amba { + bootph-all; + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + sdhci1: sdhci@f1050000 { + compatible = "xlnx,versal-net-emmc"; + status = "okay"; + non-removable; + disable-wp; + bus-width = <8>; + reg = <0 0xf1050000 0 0x10000>; + clock-names = "clk_xin", "clk_ahb"; + clocks = <&clk200>, <&clk200>; + xlnx,mio-bank = <0>; + }; + }; +}; diff --git a/arch/arm/dts/versal-net-mini-ospi-single.dts b/arch/arm/dts/versal-net-mini-ospi-single.dts new file mode 100644 index 0000000..11a8e8b --- /dev/null +++ b/arch/arm/dts/versal-net-mini-ospi-single.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Xilinx Versal NET OSPI single DTS + * + * (C) Copyright 2023, Advanced Micro Devices, Inc. + * + * Michal Simek <michal.simek@amd.com> + * Ashok Reddy Soma <ashok.reddy.soma@amd.com> + */ + +#include "versal-net-mini-ospi.dtsi" + +/ { + model = "Xilinx Versal NET MINI OSPI SINGLE"; +}; + +&flash0 { + spi-rx-bus-width = <8>; +}; diff --git a/arch/arm/dts/versal-net-mini-ospi.dtsi b/arch/arm/dts/versal-net-mini-ospi.dtsi new file mode 100644 index 0000000..ce8e215 --- /dev/null +++ b/arch/arm/dts/versal-net-mini-ospi.dtsi @@ -0,0 +1,78 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for Xilinx Versal NET Mini OSPI Configuration + * + * (C) Copyright 2023, Advanced Micro Devices, Inc. + * + * Michal Simek <michal.simek@amd.com> + * Ashok Reddy Soma <ashok.reddy.soma@amd.com> + */ + +/dts-v1/; + +/ { + compatible = "xlnx,versal-net-mini"; + #address-cells = <2>; + #size-cells = <2>; + model = "Xilinx Versal NET MINI OSPI"; + + aliases { + serial0 = &dcc; + spi0 = &ospi; + }; + + chosen { + stdout-path = "serial0:115200"; + }; + + memory@bbf00000 { + device_type = "memory"; + reg = <0 0xBBF00000 0 0x100000>; + }; + + clk125: clk125 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + }; + + dcc: dcc { + compatible = "arm,dcc"; + status = "okay"; + bootph-all; + }; + + amba: amba { + bootph-all; + compatible = "simple-bus"; + #address-cells = <0x2>; + #size-cells = <0x2>; + ranges; + + ospi: spi@f1010000 { + compatible = "cadence,qspi", "cdns,qspi-nor"; + status = "okay"; + reg = <0 0xf1010000 0 0x10000>, <0 0xc0000000 0 0x20000000>; + clock-names = "ref_clk", "pclk"; + clocks = <&clk125>, <&clk125>; + bus-num = <2>; + num-cs = <1>; + cdns,fifo-depth = <256>; + cdns,fifo-width = <4>; + cdns,is-dma = <1>; + cdns,is-stig-pgm = <1>; + cdns,trigger-address = <0xc0000000>; + #address-cells = <1>; + #size-cells = <0>; + + flash0: flash@0 { + compatible = "mt35xu02g", "micron,m25p80", + "jedec,spi-nor"; + reg = <0>; + spi-tx-bus-width = <8>; + spi-rx-bus-width = <8>; + spi-max-frequency = <20000000>; + }; + }; + }; +}; diff --git a/arch/arm/dts/versal-net-mini-qspi-single.dts b/arch/arm/dts/versal-net-mini-qspi-single.dts new file mode 100644 index 0000000..fec1b51 --- /dev/null +++ b/arch/arm/dts/versal-net-mini-qspi-single.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Xilinx Versal NET QSPI single DTS + * + * (C) Copyright 2023, Advanced Micro Devices, Inc. + */ + +#include "versal-net-mini-qspi.dtsi" + +/ { + model = "Xilinx Versal NET MINI QSPI SINGLE"; +}; + +&flash0 { + spi-rx-bus-width = <4>; +}; diff --git a/arch/arm/dts/versal-net-mini-qspi.dtsi b/arch/arm/dts/versal-net-mini-qspi.dtsi new file mode 100644 index 0000000..097b58c --- /dev/null +++ b/arch/arm/dts/versal-net-mini-qspi.dtsi @@ -0,0 +1,72 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for Xilinx Versal NET Mini QSPI Configuration + * + * (C) Copyright 2023, Advanced Micro Devices, Inc. + * + * Michal Simek <michal.simek@amd.com> + * Ashok Reddy Soma <ashok.reddy.soma@amd.com> + */ + +/dts-v1/; + +/ { + compatible = "xlnx,versal-net-mini"; + #address-cells = <2>; + #size-cells = <2>; + model = "Xilinx Versal NET MINI QSPI"; + + aliases { + serial0 = &dcc; + spi0 = &qspi; + }; + + chosen { + stdout-path = "serial0:115200"; + }; + + memory@bbf00000 { + device_type = "memory"; + reg = <0 0xbbf00000 0 0x100000>; + }; + + clk150: clk150 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <150000000>; + }; + + dcc: dcc { + compatible = "arm,dcc"; + status = "okay"; + bootph-all; + }; + + amba: amba { + bootph-all; + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + qspi: spi@f1030000 { + compatible = "xlnx,versal-qspi-1.0"; + status = "okay"; + clock-names = "ref_clk", "pclk"; + num-cs = <1>; + reg = <0 0xf1030000 0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk150>, <&clk150>; + + flash0: flash@0 { + compatible = "n25q512a", "micron,m25p80", + "jedec,spi-nor"; + reg = <0>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + spi-max-frequency = <20000000>; + }; + }; + }; +}; diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi index 97a9e49..8c6eafe 100644 --- a/arch/arm/dts/zynq-7000.dtsi +++ b/arch/arm/dts/zynq-7000.dtsi @@ -153,6 +153,7 @@ clocks = <&clkc 38>; interrupt-parent = <&intc>; interrupts = <0 25 4>; + clock-frequency = <400000>; reg = <0xe0004000 0x1000>; #address-cells = <1>; #size-cells = <0>; @@ -164,6 +165,7 @@ clocks = <&clkc 39>; interrupt-parent = <&intc>; interrupts = <0 48 4>; + clock-frequency = <400000>; reg = <0xe0005000 0x1000>; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/dts/zynq-dlc20-rev1.0.dts b/arch/arm/dts/zynq-dlc20-rev1.0.dts index cfe0710..d06838c 100644 --- a/arch/arm/dts/zynq-dlc20-rev1.0.dts +++ b/arch/arm/dts/zynq-dlc20-rev1.0.dts @@ -2,7 +2,7 @@ /* * Copyright (C) 2018 Xilinx, Inc. * - * Michal Simek <michal.simek@xilinx.com> + * Michal Simek <michal.simek@amd.com> */ /dts-v1/; #include "zynq-7000.dtsi" diff --git a/arch/arm/dts/zynq-minized.dts b/arch/arm/dts/zynq-minized.dts index 38365d1..3214ee4 100644 --- a/arch/arm/dts/zynq-minized.dts +++ b/arch/arm/dts/zynq-minized.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2017 - 2018, Xilinx, Inc. * - * Ibai Erkiaga <ibai.erkiaga-elorza@xilinx.com> + * Ibai Erkiaga <ibai.erkiaga-elorza@amd.com> */ /dts-v1/; diff --git a/arch/arm/dts/zynq-zc702.dts b/arch/arm/dts/zynq-zc702.dts index 27fb194..8d47f24 100644 --- a/arch/arm/dts/zynq-zc702.dts +++ b/arch/arm/dts/zynq-zc702.dts @@ -5,6 +5,7 @@ */ /dts-v1/; #include "zynq-7000.dtsi" +#include <dt-bindings/gpio/gpio.h> / { model = "Xilinx ZC702 board"; @@ -102,8 +103,8 @@ pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; - scl-gpios = <&gpio0 50 0>; - sda-gpios = <&gpio0 51 0>; + scl-gpios = <&gpio0 50 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio0 51 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; i2c-mux@74 { compatible = "nxp,pca9548"; diff --git a/arch/arm/dts/zynqmp-a2197-revA.dts b/arch/arm/dts/zynqmp-a2197-revA.dts index 04f9f02..8416705 100644 --- a/arch/arm/dts/zynqmp-a2197-revA.dts +++ b/arch/arm/dts/zynqmp-a2197-revA.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2019, Xilinx, Inc. * - * Michal Simek <michal.simek@xilinx.com> + * Michal Simek <michal.simek@amd.com> */ /dts-v1/; diff --git a/arch/arm/dts/zynqmp-clk-ccf.dtsi b/arch/arm/dts/zynqmp-clk-ccf.dtsi index 38dc9cd..1ae8ea2 100644 --- a/arch/arm/dts/zynqmp-clk-ccf.dtsi +++ b/arch/arm/dts/zynqmp-clk-ccf.dtsi @@ -4,7 +4,7 @@ * * (C) Copyright 2017 - 2021, Xilinx, Inc. * - * Michal Simek <michal.simek@xilinx.com> + * Michal Simek <michal.simek@amd.com> */ #include <dt-bindings/clock/xlnx-zynqmp-clk.h> @@ -126,7 +126,7 @@ }; &gpu { - clocks = <&zynqmp_clk GPU_REF>, <&zynqmp_clk GPU_PP0_REF>, <&zynqmp_clk GPU_PP1_REF>; + clocks = <&zynqmp_clk GPU_REF>, <&zynqmp_clk GPU_PP0_REF>; }; &lpd_dma_chan1 { @@ -169,24 +169,28 @@ clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM0_REF>, <&zynqmp_clk GEM0_TX>, <&zynqmp_clk GEM0_RX>, <&zynqmp_clk GEM_TSU>; + assigned-clocks = <&zynqmp_clk GEM_TSU>; }; &gem1 { clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM1_REF>, <&zynqmp_clk GEM1_TX>, <&zynqmp_clk GEM1_RX>, <&zynqmp_clk GEM_TSU>; + assigned-clocks = <&zynqmp_clk GEM_TSU>; }; &gem2 { clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM2_REF>, <&zynqmp_clk GEM2_TX>, <&zynqmp_clk GEM2_RX>, <&zynqmp_clk GEM_TSU>; + assigned-clocks = <&zynqmp_clk GEM_TSU>; }; &gem3 { clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM3_REF>, <&zynqmp_clk GEM3_TX>, <&zynqmp_clk GEM3_RX>, <&zynqmp_clk GEM_TSU>; + assigned-clocks = <&zynqmp_clk GEM_TSU>; }; &gpio { @@ -285,10 +289,6 @@ clocks = <&zynqmp_clk AMS_REF>; }; -&zynqmp_pcap { - clocks = <&zynqmp_clk PCAP>; -}; - &zynqmp_dpdma { clocks = <&zynqmp_clk DPDMA_REF>; assigned-clocks = <&zynqmp_clk DPDMA_REF>; /* apll */ diff --git a/arch/arm/dts/zynqmp-dlc21-revA.dts b/arch/arm/dts/zynqmp-dlc21-revA.dts index 7460e4a..1b247bf 100644 --- a/arch/arm/dts/zynqmp-dlc21-revA.dts +++ b/arch/arm/dts/zynqmp-dlc21-revA.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2019 - 2021, Xilinx, Inc. * - * Michal Simek <michal.simek@xilinx.com> + * Michal Simek <michal.simek@amd.com> */ /dts-v1/; @@ -131,7 +131,7 @@ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ - "", "", "", ""; /* 170 - 174 */ + "", "", "", ""; /* 170 - 173 */ }; &i2c0 { /* MIO34/35 */ diff --git a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts index 3fa18f5..bf6ffb7 100644 --- a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts +++ b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2019 - 2021, Xilinx, Inc. * - * Michal Simek <michal.simek@xilinx.com> + * Michal Simek <michal.simek@amd.com> */ /dts-v1/; @@ -201,7 +201,7 @@ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ - "", "", "", ""; /* 170 - 174 */ + "", "", "", ""; /* 170 - 173 */ }; &i2c0 { /* MIO 34-35 - can't stay here */ diff --git a/arch/arm/dts/zynqmp-g-a2197-00-revA.dts b/arch/arm/dts/zynqmp-g-a2197-00-revA.dts index 02d2427..d5cfc61 100644 --- a/arch/arm/dts/zynqmp-g-a2197-00-revA.dts +++ b/arch/arm/dts/zynqmp-g-a2197-00-revA.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2019, Xilinx, Inc. * - * Michal Simek <michal.simek@xilinx.com> + * Michal Simek <michal.simek@amd.com> */ /dts-v1/; @@ -125,14 +125,14 @@ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ - "", "", "", ""; /* 170 - 174 */ + "", "", "", ""; /* 170 - 173 */ }; &i2c0 { /* MIO 34-35 - can't stay here */ status = "okay"; clock-frequency = <400000>; - scl-gpios = <&gpio 34 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio 34 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 35 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; i2c-mux@74 { /* u94 */ compatible = "nxp,pca9548"; #address-cells = <1>; diff --git a/arch/arm/dts/zynqmp-m-a2197-01-revA.dts b/arch/arm/dts/zynqmp-m-a2197-01-revA.dts index 2d7fe59..97500b1 100644 --- a/arch/arm/dts/zynqmp-m-a2197-01-revA.dts +++ b/arch/arm/dts/zynqmp-m-a2197-01-revA.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2019, Xilinx, Inc. * - * Michal Simek <michal.simek@xilinx.com> + * Michal Simek <michal.simek@amd.com> */ /dts-v1/; @@ -154,7 +154,7 @@ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ - "", "", "", ""; /* 170 - 174 */ + "", "", "", ""; /* 170 - 173 */ }; &i2c0 { /* MIO 34-35 - can't stay here */ diff --git a/arch/arm/dts/zynqmp-m-a2197-02-revA.dts b/arch/arm/dts/zynqmp-m-a2197-02-revA.dts index e46748d..3bdcf05 100644 --- a/arch/arm/dts/zynqmp-m-a2197-02-revA.dts +++ b/arch/arm/dts/zynqmp-m-a2197-02-revA.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2019, Xilinx, Inc. * - * Michal Simek <michal.simek@xilinx.com> + * Michal Simek <michal.simek@amd.com> */ /dts-v1/; @@ -149,7 +149,7 @@ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ - "", "", "", ""; /* 170 - 174 */ + "", "", "", ""; /* 170 - 173 */ }; &i2c0 { /* MIO 34-35 - can't stay here */ diff --git a/arch/arm/dts/zynqmp-m-a2197-03-revA.dts b/arch/arm/dts/zynqmp-m-a2197-03-revA.dts index f564817..9a693a5 100644 --- a/arch/arm/dts/zynqmp-m-a2197-03-revA.dts +++ b/arch/arm/dts/zynqmp-m-a2197-03-revA.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2019, Xilinx, Inc. * - * Michal Simek <michal.simek@xilinx.com> + * Michal Simek <michal.simek@amd.com> */ /dts-v1/; @@ -149,7 +149,7 @@ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ - "", "", "", ""; /* 170 - 174 */ + "", "", "", ""; /* 170 - 173 */ }; &i2c0 { /* MIO 34-35 - can't stay here */ diff --git a/arch/arm/dts/zynqmp-mini-emmc0.dts b/arch/arm/dts/zynqmp-mini-emmc0.dts index d1e58eb..08ec2f7 100644 --- a/arch/arm/dts/zynqmp-mini-emmc0.dts +++ b/arch/arm/dts/zynqmp-mini-emmc0.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2018, Xilinx, Inc. * - * Siva Durga Prasad <siva.durga.paladugu@xilinx.com> + * Siva Durga Prasad <siva.durga.prasad.paladugu@amd.com>> */ /dts-v1/; diff --git a/arch/arm/dts/zynqmp-mini-emmc1.dts b/arch/arm/dts/zynqmp-mini-emmc1.dts index 0c139f8..905de08 100644 --- a/arch/arm/dts/zynqmp-mini-emmc1.dts +++ b/arch/arm/dts/zynqmp-mini-emmc1.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2018, Xilinx, Inc. * - * Siva Durga Prasad <siva.durga.paladugu@xilinx.com> + * Siva Durga Prasad <siva.durga.prasad.paladugu@amd.com>> */ /dts-v1/; diff --git a/arch/arm/dts/zynqmp-mini-nand.dts b/arch/arm/dts/zynqmp-mini-nand.dts index 8fae01b..e5688fd 100644 --- a/arch/arm/dts/zynqmp-mini-nand.dts +++ b/arch/arm/dts/zynqmp-mini-nand.dts @@ -4,8 +4,8 @@ * * (C) Copyright 2018, Xilinx, Inc. * - * Siva Durga Prasad <siva.durga.paladugu@xilinx.com> - * Michal Simek <michal.simek@xilinx.com> + * Siva Durga Prasad <siva.durga.prasad.paladugu@amd.com>> + * Michal Simek <michal.simek@amd.com> */ /dts-v1/; diff --git a/arch/arm/dts/zynqmp-mini-qspi.dts b/arch/arm/dts/zynqmp-mini-qspi.dts index a7cf4ef..fc0a2e8 100644 --- a/arch/arm/dts/zynqmp-mini-qspi.dts +++ b/arch/arm/dts/zynqmp-mini-qspi.dts @@ -4,8 +4,8 @@ * * (C) Copyright 2015 - 2020, Xilinx, Inc. * - * Siva Durga Prasad <siva.durga.paladugu@xilinx.com> - * Michal Simek <michal.simek@xilinx.com> + * Siva Durga Prasad <siva.durga.prasad.paladugu@amd.com>> + * Michal Simek <michal.simek@amd.com> */ /dts-v1/; diff --git a/arch/arm/dts/zynqmp-mini.dts b/arch/arm/dts/zynqmp-mini.dts index 15bee16..b9a24f0 100644 --- a/arch/arm/dts/zynqmp-mini.dts +++ b/arch/arm/dts/zynqmp-mini.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2017, Xilinx, Inc. * - * Michal Simek <michal.simek@xilinx.com> + * Michal Simek <michal.simek@amd.com> */ /dts-v1/; diff --git a/arch/arm/dts/zynqmp-p-a2197-00-revA.dts b/arch/arm/dts/zynqmp-p-a2197-00-revA.dts index d63deb8..16691a8 100644 --- a/arch/arm/dts/zynqmp-p-a2197-00-revA.dts +++ b/arch/arm/dts/zynqmp-p-a2197-00-revA.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2019, Xilinx, Inc. * - * Michal Simek <michal.simek@xilinx.com> + * Michal Simek <michal.simek@amd.com> */ /dts-v1/; @@ -134,7 +134,7 @@ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ - "", "", "", ""; /* 170 - 174 */ + "", "", "", ""; /* 170 - 173 */ }; &i2c0 { /* MIO 34-35 - can't stay here */ diff --git a/arch/arm/dts/zynqmp-r5.dts b/arch/arm/dts/zynqmp-r5.dts index 9789d71..77b15fe 100644 --- a/arch/arm/dts/zynqmp-r5.dts +++ b/arch/arm/dts/zynqmp-r5.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2018, Xilinx, Inc. * - * Michal Simek <michal.simek@xilinx.com> + * Michal Simek <michal.simek@amd.com> */ /dts-v1/; diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revA.dts b/arch/arm/dts/zynqmp-sck-kr-g-revA.dts index c82e1df..d318773 100644 --- a/arch/arm/dts/zynqmp-sck-kr-g-revA.dts +++ b/arch/arm/dts/zynqmp-sck-kr-g-revA.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2021, Xilinx, Inc. * - * Michal Simek <michal.simek@xilinx.com> + * Michal Simek <michal.simek@amd.com> */ #include <dt-bindings/gpio/gpio.h> @@ -68,8 +68,8 @@ pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; u14: ina260@40 { /* u14 */ compatible = "ti,ina260"; @@ -188,6 +188,7 @@ phy-handle = <&phy0>; phy-mode = "sgmii"; is-internal-pcspma; + assigned-clock-rates = <250000000>; }; &gem1 { /* mdio mio50/51, gem mio38 - mio49 */ @@ -196,6 +197,7 @@ pinctrl-0 = <&pinctrl_gem1_default>; phy-handle = <&phy1>; phy-mode = "rgmii-id"; + assigned-clock-rates = <250000000>; mdio: mdio { #address-cells = <1>; @@ -208,7 +210,7 @@ ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>; ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; ti,dp83867-rxctrl-strap-quirk; - reset-assert-us = <100>; + reset-assert-us = <300>; reset-deassert-us = <280>; reset-gpios = <&slg7xl45106 5 GPIO_ACTIVE_LOW>; }; diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revB.dts b/arch/arm/dts/zynqmp-sck-kr-g-revB.dts index 9dd160c..69dba07 100644 --- a/arch/arm/dts/zynqmp-sck-kr-g-revB.dts +++ b/arch/arm/dts/zynqmp-sck-kr-g-revB.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2021 - 2022, Xilinx, Inc. * - * Michal Simek <michal.simek@xilinx.com> + * Michal Simek <michal.simek@amd.com> */ #include <dt-bindings/gpio/gpio.h> @@ -68,8 +68,8 @@ pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; u14: ina260@40 { /* u14 */ compatible = "ti,ina260"; @@ -188,6 +188,7 @@ phy-handle = <&phy0>; phy-mode = "sgmii"; is-internal-pcspma; + assigned-clock-rates = <250000000>; }; &gem1 { /* mdio mio50/51, gem mio38 - mio49 */ @@ -196,6 +197,7 @@ pinctrl-0 = <&pinctrl_gem1_default>; phy-handle = <&phy1>; phy-mode = "rgmii-id"; + assigned-clock-rates = <250000000>; mdio: mdio { #address-cells = <1>; @@ -208,7 +210,7 @@ ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>; ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; ti,dp83867-rxctrl-strap-quirk; - reset-assert-us = <100>; + reset-assert-us = <300>; reset-deassert-us = <280>; reset-gpios = <&slg7xl45106 5 GPIO_ACTIVE_LOW>; }; diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revA.dts b/arch/arm/dts/zynqmp-sck-kv-g-revA.dts index 6f5a426..a81b3f6 100644 --- a/arch/arm/dts/zynqmp-sck-kv-g-revA.dts +++ b/arch/arm/dts/zynqmp-sck-kv-g-revA.dts @@ -9,7 +9,7 @@ * "Y" – A01 board modified with legacy interposer (Nexperia) * "Z" – A01 board modified with Diode interposer * - * Michal Simek <michal.simek@xilinx.com> + * Michal Simek <michal.simek@amd.com> */ #include <dt-bindings/gpio/gpio.h> @@ -34,8 +34,8 @@ pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; u14: ina260@40 { /* u14 */ compatible = "ti,ina260"; @@ -165,6 +165,7 @@ pinctrl-0 = <&pinctrl_gem3_default>; phy-handle = <&phy0>; phy-mode = "rgmii-id"; + assigned-clock-rates = <250000000>; mdio: mdio { #address-cells = <1>; diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revB.dts b/arch/arm/dts/zynqmp-sck-kv-g-revB.dts index 7764adf..f935f25 100644 --- a/arch/arm/dts/zynqmp-sck-kv-g-revB.dts +++ b/arch/arm/dts/zynqmp-sck-kv-g-revB.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2020 - 2021, Xilinx, Inc. * - * Michal Simek <michal.simek@xilinx.com> + * Michal Simek <michal.simek@amd.com> */ #include <dt-bindings/gpio/gpio.h> @@ -16,7 +16,8 @@ /plugin/; &{/} { - compatible = "xlnx,zynqmp-sk-kv260-rev1", + compatible = "xlnx,zynqmp-sk-kv260-rev2", + "xlnx,zynqmp-sk-kv260-rev1", "xlnx,zynqmp-sk-kv260-revB", "xlnx,zynqmp-sk-kv260", "xlnx,zynqmp"; model = "ZynqMP KV260 revB"; @@ -28,8 +29,8 @@ pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; u14: ina260@40 { /* u14 */ compatible = "ti,ina260"; @@ -152,6 +153,7 @@ pinctrl-0 = <&pinctrl_gem3_default>; phy-handle = <&phy0>; phy-mode = "rgmii-id"; + assigned-clock-rates = <250000000>; mdio: mdio { #address-cells = <1>; diff --git a/arch/arm/dts/zynqmp-sm-k24-revA.dts b/arch/arm/dts/zynqmp-sm-k24-revA.dts index 2451440..653bd93 100644 --- a/arch/arm/dts/zynqmp-sm-k24-revA.dts +++ b/arch/arm/dts/zynqmp-sm-k24-revA.dts @@ -11,8 +11,9 @@ #include "zynqmp-sm-k26-revA.dts" / { - model = "ZynqMP SM-K24 RevA"; - compatible = "xlnx,zynqmp-sm-k24-revA", "xlnx,zynqmp-sm-k24", + model = "ZynqMP SM-K24 RevA/B/1"; + compatible = "xlnx,zynqmp-sm-k24-rev1", "xlnx,zynqmp-sm-k24-revB", + "xlnx,zynqmp-sm-k24-revA", "xlnx,zynqmp-sm-k24", "xlnx,zynqmp"; memory@0 { diff --git a/arch/arm/dts/zynqmp-sm-k26-revA.dts b/arch/arm/dts/zynqmp-sm-k26-revA.dts index f6ed047..d718fec 100644 --- a/arch/arm/dts/zynqmp-sm-k26-revA.dts +++ b/arch/arm/dts/zynqmp-sm-k26-revA.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2020 - 2021, Xilinx, Inc. * - * Michal Simek <michal.simek@xilinx.com> + * Michal Simek <michal.simek@amd.com> */ /dts-v1/; @@ -50,6 +50,17 @@ reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + pmu_region: pmu@7ff00000 { + reg = <0x0 0x7ff00000 0x0 0x100000>; + no-map; + }; + }; + gpio-keys { compatible = "gpio-keys"; autorepeat; @@ -256,8 +267,8 @@ status = "okay"; bootph-all; clock-frequency = <400000>; - scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; eeprom: eeprom@50 { /* u46 - also at address 0x58 */ bootph-all; @@ -352,7 +363,7 @@ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ - "", "", "", ""; /* 170 - 174 */ + "", "", "", ""; /* 170 - 173 */ }; &xilinx_ams { diff --git a/arch/arm/dts/zynqmp-smk-k26-revA.dts b/arch/arm/dts/zynqmp-smk-k26-revA.dts index c70966c..85b0d16 100644 --- a/arch/arm/dts/zynqmp-smk-k26-revA.dts +++ b/arch/arm/dts/zynqmp-smk-k26-revA.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2020 - 2021, Xilinx, Inc. * - * Michal Simek <michal.simek@xilinx.com> + * Michal Simek <michal.simek@amd.com> */ #include "zynqmp-sm-k26-revA.dts" diff --git a/arch/arm/dts/zynqmp-zc1232-revA.dts b/arch/arm/dts/zynqmp-zc1232-revA.dts index 63c553f..a288029 100644 --- a/arch/arm/dts/zynqmp-zc1232-revA.dts +++ b/arch/arm/dts/zynqmp-zc1232-revA.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2017 - 2021, Xilinx, Inc. * - * Michal Simek <michal.simek@xilinx.com> + * Michal Simek <michal.simek@amd.com> */ /dts-v1/; diff --git a/arch/arm/dts/zynqmp-zc1254-revA.dts b/arch/arm/dts/zynqmp-zc1254-revA.dts index 343033c..5c4acd17 100644 --- a/arch/arm/dts/zynqmp-zc1254-revA.dts +++ b/arch/arm/dts/zynqmp-zc1254-revA.dts @@ -4,8 +4,8 @@ * * (C) Copyright 2015 - 2020, Xilinx, Inc. * - * Michal Simek <michal.simek@xilinx.com> - * Siva Durga Prasad Paladugu <sivadur@xilinx.com> + * Michal Simek <michal.simek@amd.com> + * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>> */ /dts-v1/; diff --git a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts index 7ea2a1c..cffad44 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2015 - 2021, Xilinx, Inc. * - * Michal Simek <michal.simek@xilinx.com> + * Michal Simek <michal.simek@amd.com> */ /dts-v1/; @@ -118,8 +118,8 @@ pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio 36 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio 37 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio 36 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 37 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; eeprom: eeprom@55 { compatible = "atmel,24c64"; /* 24AA64 */ diff --git a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts index b6bc2f5..bb04778 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2015 - 2021, Xilinx, Inc. * - * Michal Simek <michal.simek@xilinx.com> + * Michal Simek <michal.simek@amd.com> */ /dts-v1/; @@ -109,8 +109,8 @@ pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; - scl-gpios = <&gpio 6 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio 7 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; tca6416_u26: gpio@20 { compatible = "ti,tca6416"; diff --git a/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts b/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts index 6021f8b..69ad580 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2016 - 2021, Xilinx, Inc. * - * Michal Simek <michal.simek@xilinx.com> + * Michal Simek <michal.simek@amd.com> */ /dts-v1/; diff --git a/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts b/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts index e153a64..3017c9b 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2015 - 2021, Xilinx, Inc. * - * Michal Simek <michal.simek@xilinx.com> + * Michal Simek <michal.simek@amd.com> */ /dts-v1/; diff --git a/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts b/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts index ae2d03d..74a5b02 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts @@ -4,8 +4,8 @@ * * (C) Copyright 2015 - 2021, Xilinx, Inc. * - * Siva Durga Prasad <siva.durga.paladugu@xilinx.com> - * Michal Simek <michal.simek@xilinx.com> + * Siva Durga Prasad <siva.durga.prasad.paladugu@amd.com>> + * Michal Simek <michal.simek@amd.com> */ /dts-v1/; @@ -91,8 +91,8 @@ pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; - scl-gpios = <&gpio 74 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio 75 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio 74 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 75 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; }; &i2c1 { @@ -100,8 +100,8 @@ pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio 76 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio 77 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio 76 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 77 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; }; diff --git a/arch/arm/dts/zynqmp-zcu100-revC.dts b/arch/arm/dts/zynqmp-zcu100-revC.dts index 742a539..a84cd86 100644 --- a/arch/arm/dts/zynqmp-zcu100-revC.dts +++ b/arch/arm/dts/zynqmp-zcu100-revC.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2016 - 2021, Xilinx, Inc. * - * Michal Simek <michal.simek@xilinx.com> + * Michal Simek <michal.simek@amd.com> * Nathalie Chan King Choy */ @@ -188,8 +188,8 @@ pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio 4 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; clock-frequency = <100000>; i2c-mux@75 { /* u11 */ compatible = "nxp,pca9548"; @@ -569,6 +569,7 @@ pinctrl-0 = <&pinctrl_usb0_default>; phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 0>; + /delete-property/ reset-gpios; }; &dwc3_0 { @@ -584,6 +585,7 @@ pinctrl-0 = <&pinctrl_usb1_default>; phy-names = "usb3-phy"; phys = <&psgtr 3 PHY_TYPE_USB3 1 0>; + reset-gpios = <&modepin_gpio 1 GPIO_ACTIVE_LOW>; }; &dwc3_1 { diff --git a/arch/arm/dts/zynqmp-zcu102-rev1.0.dts b/arch/arm/dts/zynqmp-zcu102-rev1.0.dts index d508f33..c0a4d91 100644 --- a/arch/arm/dts/zynqmp-zcu102-rev1.0.dts +++ b/arch/arm/dts/zynqmp-zcu102-rev1.0.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2016 - 2020, Xilinx, Inc. * - * Michal Simek <michal.simek@xilinx.com> + * Michal Simek <michal.simek@amd.com> */ #include "zynqmp-zcu102-revB.dts" diff --git a/arch/arm/dts/zynqmp-zcu102-rev1.1.dts b/arch/arm/dts/zynqmp-zcu102-rev1.1.dts index b679839..70536976 100644 --- a/arch/arm/dts/zynqmp-zcu102-rev1.1.dts +++ b/arch/arm/dts/zynqmp-zcu102-rev1.1.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2016 - 2020, Xilinx, Inc. * - * Michal Simek <michal.simek@xilinx.com> + * Michal Simek <michal.simek@amd.com> */ #include "zynqmp-zcu102-rev1.0.dts" diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts b/arch/arm/dts/zynqmp-zcu102-revA.dts index d78bfb8..79d67c4 100644 --- a/arch/arm/dts/zynqmp-zcu102-revA.dts +++ b/arch/arm/dts/zynqmp-zcu102-revA.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2015 - 2021, Xilinx, Inc. * - * Michal Simek <michal.simek@xilinx.com> + * Michal Simek <michal.simek@amd.com> */ /dts-v1/; @@ -232,8 +232,8 @@ pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; - scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; tca6416_u97: gpio@20 { compatible = "ti,tca6416"; @@ -496,8 +496,8 @@ pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; /* PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ diff --git a/arch/arm/dts/zynqmp-zcu102-revB.dts b/arch/arm/dts/zynqmp-zcu102-revB.dts index de3b5ab..ce0a6e5 100644 --- a/arch/arm/dts/zynqmp-zcu102-revB.dts +++ b/arch/arm/dts/zynqmp-zcu102-revB.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2016 - 2020, Xilinx, Inc. * - * Michal Simek <michal.simek@xilinx.com> + * Michal Simek <michal.simek@amd.com> */ #include "zynqmp-zcu102-revA.dts" diff --git a/arch/arm/dts/zynqmp-zcu104-revA.dts b/arch/arm/dts/zynqmp-zcu104-revA.dts index b9d82af..90fbfca 100644 --- a/arch/arm/dts/zynqmp-zcu104-revA.dts +++ b/arch/arm/dts/zynqmp-zcu104-revA.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2017 - 2021, Xilinx, Inc. * - * Michal Simek <michal.simek@xilinx.com> + * Michal Simek <michal.simek@amd.com> */ /dts-v1/; @@ -139,8 +139,8 @@ pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; /* Another connection to this bus via PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ diff --git a/arch/arm/dts/zynqmp-zcu104-revC.dts b/arch/arm/dts/zynqmp-zcu104-revC.dts index 6f24e33..69470f8 100644 --- a/arch/arm/dts/zynqmp-zcu104-revC.dts +++ b/arch/arm/dts/zynqmp-zcu104-revC.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2017 - 2021, Xilinx, Inc. * - * Michal Simek <michal.simek@xilinx.com> + * Michal Simek <michal.simek@amd.com> */ /dts-v1/; @@ -144,8 +144,8 @@ pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; tca6416_u97: gpio@20 { compatible = "ti,tca6416"; diff --git a/arch/arm/dts/zynqmp-zcu106-rev1.0.dts b/arch/arm/dts/zynqmp-zcu106-rev1.0.dts index f43c477..a9b5826 100644 --- a/arch/arm/dts/zynqmp-zcu106-rev1.0.dts +++ b/arch/arm/dts/zynqmp-zcu106-rev1.0.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2016 - 2022, Xilinx, Inc. * - * Michal Simek <michal.simek@xilinx.com> + * Michal Simek <michal.simek@amd.com> */ #include "zynqmp-zcu106-revA.dts" diff --git a/arch/arm/dts/zynqmp-zcu106-revA.dts b/arch/arm/dts/zynqmp-zcu106-revA.dts index 266c24e..7a8094a 100644 --- a/arch/arm/dts/zynqmp-zcu106-revA.dts +++ b/arch/arm/dts/zynqmp-zcu106-revA.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2016 - 2021, Xilinx, Inc. * - * Michal Simek <michal.simek@xilinx.com> + * Michal Simek <michal.simek@amd.com> */ /dts-v1/; @@ -232,8 +232,8 @@ pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; - scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; tca6416_u97: gpio@20 { compatible = "ti,tca6416"; @@ -495,8 +495,8 @@ pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; /* PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ diff --git a/arch/arm/dts/zynqmp-zcu111-revA.dts b/arch/arm/dts/zynqmp-zcu111-revA.dts index 8535cc0..c9ff99f 100644 --- a/arch/arm/dts/zynqmp-zcu111-revA.dts +++ b/arch/arm/dts/zynqmp-zcu111-revA.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2017 - 2021, Xilinx, Inc. * - * Michal Simek <michal.simek@xilinx.com> + * Michal Simek <michal.simek@amd.com> */ /dts-v1/; @@ -204,8 +204,8 @@ pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; - scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; tca6416_u22: gpio@20 { compatible = "ti,tca6416"; @@ -384,8 +384,8 @@ pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; i2c-mux@74 { /* u26 */ compatible = "nxp,pca9548"; diff --git a/arch/arm/dts/zynqmp-zcu1275-revA.dts b/arch/arm/dts/zynqmp-zcu1275-revA.dts index e88fc23..9404c13 100644 --- a/arch/arm/dts/zynqmp-zcu1275-revA.dts +++ b/arch/arm/dts/zynqmp-zcu1275-revA.dts @@ -4,8 +4,8 @@ * * (C) Copyright 2017 - 2021, Xilinx, Inc. * - * Michal Simek <michal.simek@xilinx.com> - * Siva Durga Prasad Paladugu <sivadur@xilinx.com> + * Michal Simek <michal.simek@amd.com> + * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>> */ /dts-v1/; diff --git a/arch/arm/dts/zynqmp-zcu1275-revB.dts b/arch/arm/dts/zynqmp-zcu1275-revB.dts index 97ae1b2..c06d262 100644 --- a/arch/arm/dts/zynqmp-zcu1275-revB.dts +++ b/arch/arm/dts/zynqmp-zcu1275-revB.dts @@ -4,8 +4,8 @@ * * (C) Copyright 2018 - 2021, Xilinx, Inc. * - * Michal Simek <michal.simek@xilinx.com> - * Siva Durga Prasad Paladugu <sivadur@xilinx.com> + * Michal Simek <michal.simek@amd.com> + * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>> */ /dts-v1/; diff --git a/arch/arm/dts/zynqmp-zcu1285-revA.dts b/arch/arm/dts/zynqmp-zcu1285-revA.dts index eaf99a9..99ea143 100644 --- a/arch/arm/dts/zynqmp-zcu1285-revA.dts +++ b/arch/arm/dts/zynqmp-zcu1285-revA.dts @@ -4,8 +4,8 @@ * * (C) Copyright 2018 - 2021, Xilinx, Inc. * - * Michal Simek <michal.simek@xilinx.com> - * Siva Durga Prasad Paladugu <sivadur@xilinx.com> + * Michal Simek <michal.simek@amd.com> + * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>> */ /dts-v1/; diff --git a/arch/arm/dts/zynqmp-zcu208-revA.dts b/arch/arm/dts/zynqmp-zcu208-revA.dts index 7e7e157..9b3ae67 100644 --- a/arch/arm/dts/zynqmp-zcu208-revA.dts +++ b/arch/arm/dts/zynqmp-zcu208-revA.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2017 - 2021, Xilinx, Inc. * - * Michal Simek <michal.simek@xilinx.com> + * Michal Simek <michal.simek@amd.com> */ /dts-v1/; @@ -222,7 +222,7 @@ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ - "", "", "", ""; /* 170 - 174 */ + "", "", "", ""; /* 170 - 173 */ }; &i2c0 { @@ -231,8 +231,8 @@ pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; - scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; tca6416_u15: gpio@20 { /* u15 */ compatible = "ti,tca6416"; @@ -397,8 +397,8 @@ pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; i2c-mux@74 { compatible = "nxp,pca9548"; /* u20 */ diff --git a/arch/arm/dts/zynqmp-zcu216-revA.dts b/arch/arm/dts/zynqmp-zcu216-revA.dts index 35a3097..43eeaec 100644 --- a/arch/arm/dts/zynqmp-zcu216-revA.dts +++ b/arch/arm/dts/zynqmp-zcu216-revA.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2017 - 2021, Xilinx, Inc. * - * Michal Simek <michal.simek@xilinx.com> + * Michal Simek <michal.simek@amd.com> */ /dts-v1/; @@ -228,7 +228,7 @@ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ - "", "", "", ""; /* 170 - 174 */ + "", "", "", ""; /* 170 - 173 */ }; &gpu { @@ -241,8 +241,8 @@ pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; - scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; tca6416_u15: gpio@20 { /* u15 */ compatible = "ti,tca6416"; @@ -407,8 +407,8 @@ pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; i2c-mux@74 { compatible = "nxp,pca9548"; /* u20 */ diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 6a16638..1632be8 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -4,7 +4,7 @@ * * (C) Copyright 2014 - 2021, Xilinx, Inc. * - * Michal Simek <michal.simek@xilinx.com> + * Michal Simek <michal.simek@amd.com> * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -33,6 +33,7 @@ operating-points-v2 = <&cpu_opp_table>; reg = <0x0>; cpu-idle-states = <&CPU_SLEEP_0>; + next-level-cache = <&L2>; }; cpu1: cpu@1 { @@ -42,6 +43,7 @@ reg = <0x1>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; + next-level-cache = <&L2>; }; cpu2: cpu@2 { @@ -51,6 +53,7 @@ reg = <0x2>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; + next-level-cache = <&L2>; }; cpu3: cpu@3 { @@ -60,6 +63,13 @@ reg = <0x3>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; + next-level-cache = <&L2>; + }; + + L2: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; }; idle-states { @@ -111,7 +121,7 @@ #size-cells = <2>; ranges; - ipi_mailbox_pmu1: mailbox@ff990400 { + ipi_mailbox_pmu1: mailbox@ff9905c0 { bootph-all; reg = <0x0 0xff9905c0 0x0 0x20>, <0x0 0xff9905e0 0x0 0x20>, @@ -139,6 +149,10 @@ <0 144 4>, <0 145 4>, <0 146 4>; + interrupt-affinity = <&cpu0>, + <&cpu1>, + <&cpu2>, + <&cpu3>; }; psci { @@ -179,7 +193,6 @@ zynqmp_pcap: pcap { compatible = "xlnx,zynqmp-pcap-fpga"; - clock-names = "ref_clk"; }; xlnx_aes: zynqmp-aes { @@ -396,12 +409,12 @@ gpu: gpu@fd4b0000 { status = "disabled"; - compatible = "arm,mali-400", "arm,mali-utgard"; + compatible = "xlnx,zynqmp-mali", "arm,mali-400"; reg = <0x0 0xfd4b0000 0x0 0x10000>; interrupt-parent = <&gic>; interrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>; - interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP0", "IRQPPMMU0", "IRQPP1", "IRQPPMMU1"; - clock-names = "gpu", "gpu_pp0", "gpu_pp1"; + interrupt-names = "gp", "gpmmu", "pp0", "ppmmu0", "pp1", "ppmmu1"; + clock-names = "bus", "core"; power-domains = <&zynqmp_firmware PD_GPU>; }; @@ -611,6 +624,7 @@ status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 17 4>; + clock-frequency = <400000>; reg = <0x0 0xff020000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; @@ -622,6 +636,7 @@ status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 18 4>; + clock-frequency = <400000>; reg = <0x0 0xff030000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; @@ -876,7 +891,6 @@ iommus = <&smmu 0x860>; snps,quirk-frame-length-adjustment = <0x20>; clock-names = "ref"; - snps,enable_guctl1_resume_quirk; snps,enable_guctl1_ipd_quirk; snps,xhci-stream-quirk; snps,resume-hs-terminations; @@ -908,7 +922,6 @@ iommus = <&smmu 0x861>; snps,quirk-frame-length-adjustment = <0x20>; clock-names = "ref"; - snps,enable_guctl1_resume_quirk; snps,enable_guctl1_ipd_quirk; snps,xhci-stream-quirk; snps,resume-hs-terminations; @@ -940,21 +953,19 @@ status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 56 4>; - interrupt-names = "ams-irq"; reg = <0x0 0xffa50000 0x0 0x800>; - reg-names = "ams-base"; #address-cells = <1>; #size-cells = <1>; #io-channel-cells = <1>; ranges = <0 0 0xffa50800 0x800>; - ams_ps: ams_ps@0 { + ams_ps: ams-ps@0 { compatible = "xlnx,zynqmp-ams-ps"; status = "disabled"; reg = <0x0 0x400>; }; - ams_pl: ams_pl@400 { + ams_pl: ams-pl@400 { compatible = "xlnx,zynqmp-ams-pl"; status = "disabled"; reg = <0x400 0x400>; diff --git a/arch/arm/include/asm/arch-mx5/clock.h b/arch/arm/include/asm/arch-mx5/clock.h index 63a5104..d585b5c 100644 --- a/arch/arm/include/asm/arch-mx5/clock.h +++ b/arch/arm/include/asm/arch-mx5/clock.h @@ -42,7 +42,7 @@ enum mxc_clock { u32 imx_get_uartclk(void); u32 imx_get_fecclk(void); unsigned int mxc_get_clock(enum mxc_clock clk); -int mxc_set_clock(u32 ref, u32 freq, u32 clk_type); +int mxc_set_clock(u32 ref, u32 freq, enum mxc_clock clk); void set_usb_phy_clk(void); void enable_usb_phy1_clk(bool enable); void enable_usb_phy2_clk(bool enable); diff --git a/arch/arm/mach-tegra/arm64-mmu.c b/arch/arm/mach-tegra/arm64-mmu.c index d45b1fa..ea4eac3 100644 --- a/arch/arm/mach-tegra/arm64-mmu.c +++ b/arch/arm/mach-tegra/arm64-mmu.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * (C) Copyright 2014 - 2015 Xilinx, Inc. - * Michal Simek <michal.simek@xilinx.com> + * Michal Simek <michal.simek@amd.com> * (This file derived from arch/arm/mach-zynqmp/cpu.c) * * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. diff --git a/arch/arm/mach-versal-net/include/mach/hardware.h b/arch/arm/mach-versal-net/include/mach/hardware.h index 3f04104..9bddb8b 100644 --- a/arch/arm/mach-versal-net/include/mach/hardware.h +++ b/arch/arm/mach-versal-net/include/mach/hardware.h @@ -81,3 +81,14 @@ enum versal_net_platform { #define VERSAL_SLCR_BASEADDR 0xF1060000 #define VERSAL_AXI_MUX_SEL (VERSAL_SLCR_BASEADDR + 0x504) #define VERSAL_OSPI_LINEAR_MODE BIT(1) + +#define FLASH_RESET_GPIO 0xc +#define WPROT_CRP 0xF126001C +#define RST_GPIO 0xF1260318 +#define WPROT_LPD_MIO 0xFF080728 +#define WPROT_PMC_MIO 0xF1060828 +#define BOOT_MODE_DIR 0xF1020204 +#define BOOT_MODE_OUT 0xF1020208 +#define MIO_PIN_12 0xF1060030 +#define BANK0_OUTPUT 0xF1020040 +#define BANK0_TRI 0xF1060200 diff --git a/arch/arm/mach-versal-net/include/mach/sys_proto.h b/arch/arm/mach-versal-net/include/mach/sys_proto.h index a20cf02..23374d1 100644 --- a/arch/arm/mach-versal-net/include/mach/sys_proto.h +++ b/arch/arm/mach-versal-net/include/mach/sys_proto.h @@ -7,5 +7,3 @@ #include <linux/build_bug.h> void mem_map_fill(void); - -int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value); diff --git a/arch/arm/mach-versal/Makefile b/arch/arm/mach-versal/Makefile index ca12e29..864b305 100644 --- a/arch/arm/mach-versal/Makefile +++ b/arch/arm/mach-versal/Makefile @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0+ # # (C) Copyright 2016 - 2018 Xilinx, Inc. -# Michal Simek <michal.simek@xilinx.com> +# Michal Simek <michal.simek@amd.com> # obj-y += clk.o diff --git a/arch/arm/mach-versal/clk.c b/arch/arm/mach-versal/clk.c index 249e050..5e3f44c7 100644 --- a/arch/arm/mach-versal/clk.c +++ b/arch/arm/mach-versal/clk.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * (C) Copyright 2016 - 2018 Xilinx, Inc. - * Michal Simek <michal.simek@xilinx.com> + * Michal Simek <michal.simek@amd.com> */ #include <common.h> diff --git a/arch/arm/mach-versal/cpu.c b/arch/arm/mach-versal/cpu.c index 9dc308b..e4dc305 100644 --- a/arch/arm/mach-versal/cpu.c +++ b/arch/arm/mach-versal/cpu.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * (C) Copyright 2016 - 2018 Xilinx, Inc. - * Michal Simek <michal.simek@xilinx.com> + * Michal Simek <michal.simek@amd.com> */ #include <common.h> diff --git a/arch/arm/mach-versal/include/mach/sys_proto.h b/arch/arm/mach-versal/include/mach/sys_proto.h index 433f9ba..757bd87 100644 --- a/arch/arm/mach-versal/include/mach/sys_proto.h +++ b/arch/arm/mach-versal/include/mach/sys_proto.h @@ -13,5 +13,3 @@ enum { void initialize_tcm(bool mode); void tcm_init(u8 mode); void mem_map_fill(void); - -int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value); diff --git a/arch/arm/mach-versal/mp.c b/arch/arm/mach-versal/mp.c index 5b850f3..7bd3928 100644 --- a/arch/arm/mach-versal/mp.c +++ b/arch/arm/mach-versal/mp.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* * (C) Copyright 2019 Xilinx, Inc. - * Siva Durga Prasad <siva.durga.paladugu@xilinx.com> + * Siva Durga Prasad <siva.durga.prasad.paladugu@amd.com>> */ #include <common.h> diff --git a/arch/arm/mach-zynqmp/Makefile b/arch/arm/mach-zynqmp/Makefile index bb1830c..3f25554 100644 --- a/arch/arm/mach-zynqmp/Makefile +++ b/arch/arm/mach-zynqmp/Makefile @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0+ # # (C) Copyright 2014 - 2015 Xilinx, Inc. -# Michal Simek <michal.simek@xilinx.com> +# Michal Simek <michal.simek@amd.com> obj-y += clk.o obj-y += cpu.o diff --git a/arch/arm/mach-zynqmp/clk.c b/arch/arm/mach-zynqmp/clk.c index 1e6e726..3b05f84 100644 --- a/arch/arm/mach-zynqmp/clk.c +++ b/arch/arm/mach-zynqmp/clk.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * (C) Copyright 2014 - 2015 Xilinx, Inc. - * Michal Simek <michal.simek@xilinx.com> + * Michal Simek <michal.simek@amd.com> */ #include <common.h> diff --git a/arch/arm/mach-zynqmp/cpu.c b/arch/arm/mach-zynqmp/cpu.c index 26e285c..6ae2789 100644 --- a/arch/arm/mach-zynqmp/cpu.c +++ b/arch/arm/mach-zynqmp/cpu.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * (C) Copyright 2014 - 2015 Xilinx, Inc. - * Michal Simek <michal.simek@xilinx.com> + * Michal Simek <michal.simek@amd.com> */ #include <common.h> diff --git a/arch/arm/mach-zynqmp/handoff.c b/arch/arm/mach-zynqmp/handoff.c index 511b241..dce9243 100644 --- a/arch/arm/mach-zynqmp/handoff.c +++ b/arch/arm/mach-zynqmp/handoff.c @@ -2,7 +2,7 @@ /* * Copyright 2016 - 2017 Xilinx, Inc. * - * Michal Simek <michal.simek@xilinx.com> + * Michal Simek <michal.simek@amd.com> */ #include <common.h> diff --git a/arch/arm/mach-zynqmp/include/mach/clk.h b/arch/arm/mach-zynqmp/include/mach/clk.h index cfd44c8..9918d46 100644 --- a/arch/arm/mach-zynqmp/include/mach/clk.h +++ b/arch/arm/mach-zynqmp/include/mach/clk.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * (C) Copyright 2014 - 2015 Xilinx, Inc. - * Michal Simek <michal.simek@xilinx.com> + * Michal Simek <michal.simek@amd.com> */ #ifndef _ASM_ARCH_CLK_H_ diff --git a/arch/arm/mach-zynqmp/include/mach/hardware.h b/arch/arm/mach-zynqmp/include/mach/hardware.h index 70221e0..634bf16 100644 --- a/arch/arm/mach-zynqmp/include/mach/hardware.h +++ b/arch/arm/mach-zynqmp/include/mach/hardware.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * (C) Copyright 2014 - 2015 Xilinx, Inc. - * Michal Simek <michal.simek@xilinx.com> + * Michal Simek <michal.simek@amd.com> */ #ifndef _ASM_ARCH_HARDWARE_H diff --git a/arch/arm/mach-zynqmp/include/mach/sys_proto.h b/arch/arm/mach-zynqmp/include/mach/sys_proto.h index c6733ed..15b69e7 100644 --- a/arch/arm/mach-zynqmp/include/mach/sys_proto.h +++ b/arch/arm/mach-zynqmp/include/mach/sys_proto.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * (C) Copyright 2014 - 2015 Xilinx, Inc. - * Michal Simek <michal.simek@xilinx.com> + * Michal Simek <michal.simek@amd.com> */ #ifndef _ASM_ARCH_SYS_PROTO_H @@ -48,9 +48,6 @@ enum { unsigned int zynqmp_get_silicon_version(void); -int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value); -int zynqmp_mmio_read(const u32 address, u32 *value); - void initialize_tcm(bool mode); void mem_map_fill(void); #if defined(CONFIG_SYS_MEM_RSVD_FOR_MMU) || defined(CONFIG_DEFINE_TCM_OCM_MMAP) diff --git a/arch/arm/mach-zynqmp/mp.c b/arch/arm/mach-zynqmp/mp.c index b06c867..aff9054 100644 --- a/arch/arm/mach-zynqmp/mp.c +++ b/arch/arm/mach-zynqmp/mp.c @@ -1,12 +1,13 @@ // SPDX-License-Identifier: GPL-2.0+ /* * (C) Copyright 2014 - 2015 Xilinx, Inc. - * Michal Simek <michal.simek@xilinx.com> + * Michal Simek <michal.simek@amd.com> */ #include <common.h> #include <cpu_func.h> #include <log.h> +#include <zynqmp_firmware.h> #include <asm/arch/hardware.h> #include <asm/arch/sys_proto.h> #include <asm/io.h> diff --git a/arch/arm/mach-zynqmp/psu_spl_init.c b/arch/arm/mach-zynqmp/psu_spl_init.c index 5c5c7d1..b4d7f44 100644 --- a/arch/arm/mach-zynqmp/psu_spl_init.c +++ b/arch/arm/mach-zynqmp/psu_spl_init.c @@ -2,7 +2,7 @@ /* * Copyright 2018 Xilinx, Inc. * - * Michal Simek <michal.simek@xilinx.com> + * Michal Simek <michal.simek@amd.com> */ #include <common.h> #include <asm/io.h> diff --git a/arch/arm/mach-zynqmp/spl.c b/arch/arm/mach-zynqmp/spl.c index b428fd5..a0f35f3 100644 --- a/arch/arm/mach-zynqmp/spl.c +++ b/arch/arm/mach-zynqmp/spl.c @@ -2,7 +2,7 @@ /* * Copyright 2015 - 2016 Xilinx, Inc. * - * Michal Simek <michal.simek@xilinx.com> + * Michal Simek <michal.simek@amd.com> */ #include <common.h> diff --git a/arch/microblaze/cpu/spl.c b/arch/microblaze/cpu/spl.c index eaa095b..c21beaf 100644 --- a/arch/microblaze/cpu/spl.c +++ b/arch/microblaze/cpu/spl.c @@ -2,7 +2,7 @@ /* * (C) Copyright 2013 - 2014 Xilinx, Inc * - * Michal Simek <michal.simek@xilinx.com> + * Michal Simek <michal.simek@amd.com> */ #include <common.h> diff --git a/arch/microblaze/cpu/u-boot-spl.lds b/arch/microblaze/cpu/u-boot-spl.lds index 5970951..09abbea 100644 --- a/arch/microblaze/cpu/u-boot-spl.lds +++ b/arch/microblaze/cpu/u-boot-spl.lds @@ -2,7 +2,7 @@ /* * (C) Copyright 2013 - 2014 Xilinx, Inc * - * Michal Simek <michal.simek@xilinx.com> + * Michal Simek <michal.simek@amd.com> */ #include <asm-offsets.h> diff --git a/arch/microblaze/include/asm/spl.h b/arch/microblaze/include/asm/spl.h index 350d283..7557dc2 100644 --- a/arch/microblaze/include/asm/spl.h +++ b/arch/microblaze/include/asm/spl.h @@ -2,7 +2,7 @@ /* * (C) Copyright 2013 - 2014 Xilinx, Inc * - * Michal Simek <michal.simek@xilinx.com> + * Michal Simek <michal.simek@amd.com> */ #ifndef _ASM_MICROBLAZE_SPL_H_ diff --git a/arch/mips/mach-octeon/cvmx-pko3-queue.c b/arch/mips/mach-octeon/cvmx-pko3-queue.c index e28afdf..53f2e4d 100644 --- a/arch/mips/mach-octeon/cvmx-pko3-queue.c +++ b/arch/mips/mach-octeon/cvmx-pko3-queue.c @@ -761,7 +761,7 @@ int cvmx_pko3_pq_config(unsigned int node, unsigned int mac_num, * The Scheduler Queues in Levels 3 to 5 and Descriptor Queues are * configured one-to-one or many-to-one to a single parent Scheduler * Queues. The level of the parent SQ is specified in an argument, - * as well as the number of childer to attach to the specific parent. + * as well as the number of children to attach to the specific parent. * The children can have fair round-robin or priority-based scheduling * when multiple children are assigned a single parent. * diff --git a/arch/mips/mach-octeon/include/mach/cvmx-pko3-queue.h b/arch/mips/mach-octeon/include/mach/cvmx-pko3-queue.h index b3f61d7..3931191 100644 --- a/arch/mips/mach-octeon/include/mach/cvmx-pko3-queue.h +++ b/arch/mips/mach-octeon/include/mach/cvmx-pko3-queue.h @@ -6,6 +6,8 @@ #ifndef __CVMX_PKO3_QUEUE_H__ #define __CVMX_PKO3_QUEUE_H__ +enum cvmx_pko3_level_e; + /** * @INTERNAL * @@ -46,11 +48,10 @@ int cvmx_pko3_get_port_queue(int xiface, int index); * The children can have fair round-robin or priority-based scheduling * when multiple children are assigned a single parent. * - * @param node is the OCI node location for the queues to be configured - * @param parent_level is the level of the parent queue, 2 to 5. + * @param node on which to operate + * @param child_level is the level of the child queue * @param parent_queue is the number of the parent Scheduler Queue * @param child_base is the number of the first child SQ or DQ to assign to - * @param parent * @param child_count is the number of consecutive children to assign * @param stat_prio_count is the priority setting for the children L2 SQs * @@ -65,8 +66,10 @@ int cvmx_pko3_get_port_queue(int xiface, int index); * * Note: this function supports the configuration of node-local unit. */ -int cvmx_pko3_sq_config_children(unsigned int node, unsigned int parent_level, - unsigned int parent_queue, unsigned int child_base, +int cvmx_pko3_sq_config_children(unsigned int node, + enum cvmx_pko3_level_e child_level, + unsigned int parent_queue, + unsigned int child_base, unsigned int child_count, int stat_prio_count); /* diff --git a/arch/sandbox/include/asm/sdl.h b/arch/sandbox/include/asm/sdl.h index 56dcb84..ee4991f 100644 --- a/arch/sandbox/include/asm/sdl.h +++ b/arch/sandbox/include/asm/sdl.h @@ -7,6 +7,7 @@ #define __SANDBOX_SDL_H #include <errno.h> +#include <video.h> #ifdef CONFIG_SANDBOX_SDL @@ -87,6 +88,22 @@ int sandbox_sdl_sound_stop(void); */ int sandbox_sdl_sound_init(int rate, int channels); +/** + * sandbox_sdl_set_bpp() - Set the depth of the sandbox display + * + * The device must not be active when this function is called. It activiates it + * before returning. + * + * This updates the depth value and adjusts a few other settings accordingly. + * It must be called before the display is probed. + * + * @dev: Device to adjust + * @l2bpp: depth to set + * Return: 0 if the device was already active, other error if it fails to probe + * after the change + */ +int sandbox_sdl_set_bpp(struct udevice *dev, enum video_log2_bpp l2bpp); + #else static inline int sandbox_sdl_init_display(int width, int height, int log2_bpp, bool double_size) @@ -134,6 +151,12 @@ static inline int sandbox_sdl_sound_init(int rate, int channels) return -ENODEV; } +static inline int sandbox_sdl_set_bpp(struct udevice *dev, + enum video_log2_bpp l2bpp) +{ + return -ENOSYS; +} + #endif #endif diff --git a/arch/sandbox/include/asm/test.h b/arch/sandbox/include/asm/test.h index e482271..17159f8 100644 --- a/arch/sandbox/include/asm/test.h +++ b/arch/sandbox/include/asm/test.h @@ -8,7 +8,6 @@ #ifndef __ASM_TEST_H #define __ASM_TEST_H -#include <video.h> #include <pci_ids.h> struct unit_test_state; @@ -300,30 +299,6 @@ void sandbox_cros_ec_set_test_flags(struct udevice *dev, uint flags); */ int sandbox_cros_ec_get_pwm_duty(struct udevice *dev, uint index, uint *duty); -#if IS_ENABLED(CONFIG_SANDBOX_SDL) -/** - * sandbox_sdl_set_bpp() - Set the depth of the sandbox display - * - * The device must not be active when this function is called. It activiates it - * before returning. - * - * This updates the depth value and adjusts a few other settings accordingly. - * It must be called before the display is probed. - * - * @dev: Device to adjust - * @l2bpp: depth to set - * Return: 0 if the device was already active, other error if it fails to probe - * after the change - */ -int sandbox_sdl_set_bpp(struct udevice *dev, enum video_log2_bpp l2bpp); -#else -static inline int sandbox_sdl_set_bpp(struct udevice *dev, - enum video_log2_bpp l2bpp) -{ - return -ENOSYS; -} -#endif - /** * sandbox_set_fake_efi_mgr_dev() - Control EFI bootmgr producing valid bootflow * diff --git a/board/xilinx/common/Makefile b/board/xilinx/common/Makefile index cdc3c96..d563290 100644 --- a/board/xilinx/common/Makefile +++ b/board/xilinx/common/Makefile @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 # # (C) Copyright 2020 Xilinx, Inc. -# Michal Simek <michal.simek@xilinx.com> +# Michal Simek <michal.simek@amd.com> # obj-y += board.o diff --git a/board/xilinx/common/board.h b/board/xilinx/common/board.h index 922c9d5..64d6576 100644 --- a/board/xilinx/common/board.h +++ b/board/xilinx/common/board.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* * (C) Copyright 2020 Xilinx, Inc. - * Michal Simek <michal.simek@xilinx.com> + * Michal Simek <michal.simek@amd.com> */ #ifndef _BOARD_XILINX_COMMON_BOARD_H diff --git a/board/xilinx/common/cpu-info.c b/board/xilinx/common/cpu-info.c index 4eccc7a..bfe7f5b 100644 --- a/board/xilinx/common/cpu-info.c +++ b/board/xilinx/common/cpu-info.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * (C) Copyright 2014 - 2020 Xilinx, Inc. - * Michal Simek <michal.simek@xilinx.com> + * Michal Simek <michal.simek@amd.com> */ #include <common.h> diff --git a/board/xilinx/common/fru.h b/board/xilinx/common/fru.h index 586c41b..2b3fa05 100644 --- a/board/xilinx/common/fru.h +++ b/board/xilinx/common/fru.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * (C) Copyright 2019 Xilinx, Inc. - * Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> + * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>> */ #ifndef __FRU_H diff --git a/board/xilinx/versal-net/board.c b/board/xilinx/versal-net/board.c index a68b608..f0d2224 100644 --- a/board/xilinx/versal-net/board.c +++ b/board/xilinx/versal-net/board.c @@ -227,15 +227,33 @@ int board_late_init(void) break; case QSPI_MODE_24BIT: puts("QSPI_MODE_24\n"); - mode = "xspi0"; + if (uclass_get_device_by_name(UCLASS_SPI, + "spi@f1030000", &dev)) { + puts("Boot from QSPI but without QSPI enabled!\n"); + return -1; + } + mode = "xspi"; + bootseq = dev_seq(dev); break; case QSPI_MODE_32BIT: puts("QSPI_MODE_32\n"); - mode = "xspi0"; + if (uclass_get_device_by_name(UCLASS_SPI, + "spi@f1030000", &dev)) { + puts("Boot from QSPI but without QSPI enabled!\n"); + return -1; + } + mode = "xspi"; + bootseq = dev_seq(dev); break; case OSPI_MODE: puts("OSPI_MODE\n"); - mode = "xspi0"; + if (uclass_get_device_by_name(UCLASS_SPI, + "spi@f1010000", &dev)) { + puts("Boot from OSPI but without OSPI enabled!\n"); + return -1; + } + mode = "xspi"; + bootseq = dev_seq(dev); break; case EMMC_MODE: puts("EMMC_MODE\n"); diff --git a/board/xilinx/versal/Makefile b/board/xilinx/versal/Makefile index 4a46ca0..d912f2e 100644 --- a/board/xilinx/versal/Makefile +++ b/board/xilinx/versal/Makefile @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0+ # # (C) Copyright 2016 - 2018 Xilinx, Inc. -# Michal Simek <michal.simek@xilinx.com> +# Michal Simek <michal.simek@amd.com> # obj-y := board.o diff --git a/board/xilinx/versal/board.c b/board/xilinx/versal/board.c index 81e1b69..60bf37d 100644 --- a/board/xilinx/versal/board.c +++ b/board/xilinx/versal/board.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * (C) Copyright 2014 - 2018 Xilinx, Inc. - * Michal Simek <michal.simek@xilinx.com> + * Michal Simek <michal.simek@amd.com> */ #include <command.h> diff --git a/board/xilinx/versal/cmds.c b/board/xilinx/versal/cmds.c index 797c1a5..148fa51 100644 --- a/board/xilinx/versal/cmds.c +++ b/board/xilinx/versal/cmds.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* * (C) Copyright 2020 Xilinx, Inc. - * Michal Simek <michal.simek@xilinx.com> + * Michal Simek <michal.simek@amd.com> */ #include <cpu_func.h> diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c index 9a59445..3b6581e 100644 --- a/board/xilinx/zynq/board.c +++ b/board/xilinx/zynq/board.c @@ -5,6 +5,8 @@ */ #include <common.h> +#include <debug_uart.h> +#include <dfu.h> #include <init.h> #include <log.h> #include <dm/uclass.h> diff --git a/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.c b/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.c index c2a6f91..602a789 100644 --- a/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.c +++ b/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.c @@ -12408,7 +12408,7 @@ unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0; unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0; int -ps7_post_config() +ps7_post_config(void) { // Get the PS_VERSION on run time unsigned long si_ver = ps7GetSiliconVersion (); @@ -12427,7 +12427,7 @@ ps7_post_config() } int -ps7_init() +ps7_init(void) { // Get the PS_VERSION on run time unsigned long si_ver = ps7GetSiliconVersion (); diff --git a/board/xilinx/zynq/zynq-zc702/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zc702/ps7_init_gpl.c index fd102a3..9343683 100644 --- a/board/xilinx/zynq/zynq-zc702/ps7_init_gpl.c +++ b/board/xilinx/zynq/zynq-zc702/ps7_init_gpl.c @@ -12741,7 +12741,7 @@ unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0; unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0; int -ps7_post_config() +ps7_post_config(void) { // Get the PS_VERSION on run time unsigned long si_ver = ps7GetSiliconVersion (); @@ -12760,7 +12760,7 @@ ps7_post_config() } int -ps7_init() +ps7_init(void) { // Get the PS_VERSION on run time unsigned long si_ver = ps7GetSiliconVersion (); diff --git a/board/xilinx/zynq/zynq-zc706/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zc706/ps7_init_gpl.c index 796e5b0..6b153aa 100644 --- a/board/xilinx/zynq/zynq-zc706/ps7_init_gpl.c +++ b/board/xilinx/zynq/zynq-zc706/ps7_init_gpl.c @@ -12648,7 +12648,7 @@ unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0; unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0; int -ps7_post_config() +ps7_post_config(void) { // Get the PS_VERSION on run time unsigned long si_ver = ps7GetSiliconVersion (); @@ -12667,7 +12667,7 @@ ps7_post_config() } int -ps7_init() +ps7_init(void) { // Get the PS_VERSION on run time unsigned long si_ver = ps7GetSiliconVersion (); diff --git a/board/xilinx/zynq/zynq-zed/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zed/ps7_init_gpl.c index baf89a5..6f2edf1 100644 --- a/board/xilinx/zynq/zynq-zed/ps7_init_gpl.c +++ b/board/xilinx/zynq/zynq-zed/ps7_init_gpl.c @@ -12306,7 +12306,7 @@ unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0; unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0; int -ps7_post_config() +ps7_post_config(void) { // Get the PS_VERSION on run time unsigned long si_ver = ps7GetSiliconVersion (); @@ -12325,7 +12325,7 @@ ps7_post_config() } int -ps7_init() +ps7_init(void) { // Get the PS_VERSION on run time unsigned long si_ver = ps7GetSiliconVersion (); diff --git a/board/xilinx/zynqmp/Makefile b/board/xilinx/zynqmp/Makefile index 732f909..204e4fa 100644 --- a/board/xilinx/zynqmp/Makefile +++ b/board/xilinx/zynqmp/Makefile @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0+ # # (C) Copyright 2014 - 2016 Xilinx, Inc. -# Michal Simek <michal.simek@xilinx.com> +# Michal Simek <michal.simek@amd.com> obj-y := zynqmp.o diff --git a/board/xilinx/zynqmp/cmds.c b/board/xilinx/zynqmp/cmds.c index dd1ad66..ea404d5 100644 --- a/board/xilinx/zynqmp/cmds.c +++ b/board/xilinx/zynqmp/cmds.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* * (C) Copyright 2018 Xilinx, Inc. - * Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> + * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>> */ #include <common.h> diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index 39da96b..309f24a 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * (C) Copyright 2014 - 2015 Xilinx, Inc. - * Michal Simek <michal.simek@xilinx.com> + * Michal Simek <michal.simek@amd.com> */ #include <common.h> diff --git a/boot/bootmeth_script.c b/boot/bootmeth_script.c index 225eb18..a4050c3 100644 --- a/boot/bootmeth_script.c +++ b/boot/bootmeth_script.c @@ -190,7 +190,10 @@ static int script_boot(struct udevice *dev, struct bootflow *bflow) ulong addr; int ret; - ret = env_set("devtype", blk_get_devtype(bflow->blk)); + if (desc->uclass_id == UCLASS_USB) + ret = env_set("devtype", "usb"); + else + ret = env_set("devtype", blk_get_devtype(bflow->blk)); if (!ret) ret = env_set_hex("devnum", desc->devnum); if (!ret) @@ -181,13 +181,17 @@ static ulong load_serial(long offset) } else #endif { + void *dst; + ret = lmb_reserve(&lmb, store_addr, binlen); if (ret) { printf("\nCannot overwrite reserved area (%08lx..%08lx)\n", store_addr, store_addr + binlen); return ret; } - memcpy((char *)(store_addr), binbuf, binlen); + dst = map_sysmem(store_addr, binlen); + memcpy(dst, binbuf, binlen); + unmap_sysmem(dst); lmb_free(&lmb, store_addr, binlen); } if ((store_addr) < start_addr) @@ -350,15 +354,19 @@ static int save_serial(ulong address, ulong count) if(write_record(SREC3_START)) /* write the header */ return (-1); do { - if(count) { /* collect hex data in the buffer */ - c = *(volatile uchar*)(address + reclen); /* get one byte */ - checksum += c; /* accumulate checksum */ + volatile uchar *src; + + src = map_sysmem(address, count); + if (count) { /* collect hex data in the buffer */ + c = src[reclen]; /* get one byte */ + checksum += c; /* accumulate checksum */ data[2*reclen] = hex[(c>>4)&0x0f]; data[2*reclen+1] = hex[c & 0x0f]; data[2*reclen+2] = '\0'; ++reclen; --count; } + unmap_sysmem((void *)src); if(reclen == SREC_BYTES_PER_RECORD || count == 0) { /* enough data collected for one record: dump it */ if(reclen) { /* build & write a data record: */ diff --git a/common/event.c b/common/event.c index 164c95f..20720c5 100644 --- a/common/event.c +++ b/common/event.c @@ -36,6 +36,9 @@ const char *const type_name[] = { /* init hooks */ "misc_init_f", + /* Fpga load hook */ + "fpga_load", + /* fdt hooks */ "ft_fixup", diff --git a/common/spl/spl_ram.c b/common/spl/spl_ram.c index 8139a20..93cf420 100644 --- a/common/spl/spl_ram.c +++ b/common/spl/spl_ram.c @@ -6,7 +6,7 @@ * (C) Copyright 2016 * Toradex AG * - * Michal Simek <michal.simek@xilinx.com> + * Michal Simek <michal.simek@amd.com> * Stefan Agner <stefan.agner@toradex.com> */ #include <common.h> diff --git a/configs/xilinx_versal_net_mini_emmc_defconfig b/configs/xilinx_versal_net_mini_emmc_defconfig new file mode 100644 index 0000000..6d5affc --- /dev/null +++ b/configs/xilinx_versal_net_mini_emmc_defconfig @@ -0,0 +1,63 @@ +CONFIG_ARM=y +CONFIG_SYS_CONFIG_NAME="xilinx_versal_net_mini" +CONFIG_COUNTER_FREQUENCY=100000000 +CONFIG_ARCH_VERSAL_NET=y +CONFIG_TEXT_BASE=0x10000 +CONFIG_SYS_MALLOC_LEN=0x80000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x10000 +CONFIG_ENV_SIZE=0x80 +CONFIG_DEFAULT_DEVICE_TREE="versal-net-mini-emmc" +CONFIG_SYS_PROMPT="Versal NET> " +# CONFIG_PSCI_RESET is not set +CONFIG_SYS_LOAD_ADDR=0x8000000 +# CONFIG_EXPERT is not set +CONFIG_REMAKE_ELF=y +# CONFIG_AUTOBOOT is not set +CONFIG_SYS_CONSOLE_INFO_QUIET=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_BOARD_EARLY_INIT_R=y +# CONFIG_BOARD_LATE_INIT is not set +# CONFIG_CMDLINE_EDITING is not set +# CONFIG_AUTO_COMPLETE is not set +# CONFIG_SYS_LONGHELP is not set +# CONFIG_CMD_BDI is not set +# CONFIG_CMD_CONSOLE is not set +# CONFIG_CMD_BOOTD is not set +# CONFIG_CMD_BOOTM is not set +# CONFIG_CMD_BOOTI is not set +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_FDT is not set +# CONFIG_CMD_GO is not set +# CONFIG_CMD_RUN is not set +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_EDITENV is not set +# CONFIG_CMD_SAVEENV is not set +# CONFIG_CMD_ENV_EXISTS is not set +# CONFIG_CMD_CRC32 is not set +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +# CONFIG_CMD_ECHO is not set +# CONFIG_CMD_ITEST is not set +# CONFIG_CMD_SOURCE is not set +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_EMBED=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +# CONFIG_NET is not set +# CONFIG_DM_WARN is not set +# CONFIG_DM_DEVICE_REMOVE is not set +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ZYNQ=y +CONFIG_ARM_DCC=y +CONFIG_FAT_WRITE=y +# CONFIG_GZIP is not set +# CONFIG_EFI_LOADER is not set +# CONFIG_LMB is not set diff --git a/configs/xilinx_versal_net_mini_ospi_defconfig b/configs/xilinx_versal_net_mini_ospi_defconfig new file mode 100644 index 0000000..d11e180 --- /dev/null +++ b/configs/xilinx_versal_net_mini_ospi_defconfig @@ -0,0 +1,71 @@ +CONFIG_ARM=y +CONFIG_SYS_CONFIG_NAME="xilinx_versal_net_mini" +CONFIG_COUNTER_FREQUENCY=100000000 +CONFIG_ARCH_VERSAL_NET=y +CONFIG_TEXT_BASE=0xBBF00000 +CONFIG_SYS_MALLOC_LEN=0x2000 +CONFIG_SYS_MALLOC_F_LEN=0x500 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xBBF20000 +CONFIG_SF_DEFAULT_SPEED=30000000 +CONFIG_ENV_SIZE=0x80 +# CONFIG_DM_GPIO is not set +CONFIG_DEFAULT_DEVICE_TREE="versal-net-mini-ospi-single" +CONFIG_SYS_PROMPT="Versal NET> " +CONFIG_SYS_MEM_RSVD_FOR_MMU=y +# CONFIG_PSCI_RESET is not set +CONFIG_SYS_LOAD_ADDR=0xBBF80000 +# CONFIG_EXPERT is not set +CONFIG_REMAKE_ELF=y +# CONFIG_AUTOBOOT is not set +CONFIG_SYS_CONSOLE_INFO_QUIET=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_BOARD_EARLY_INIT_R=y +# CONFIG_BOARD_LATE_INIT is not set +# CONFIG_CMDLINE_EDITING is not set +# CONFIG_AUTO_COMPLETE is not set +# CONFIG_SYS_LONGHELP is not set +# CONFIG_CMD_BDI is not set +# CONFIG_CMD_CONSOLE is not set +# CONFIG_CMD_BOOTD is not set +# CONFIG_CMD_BOOTM is not set +# CONFIG_CMD_BOOTI is not set +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_FDT is not set +# CONFIG_CMD_GO is not set +# CONFIG_CMD_RUN is not set +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_EDITENV is not set +# CONFIG_CMD_SAVEENV is not set +# CONFIG_CMD_ENV_EXISTS is not set +# CONFIG_CMD_CRC32 is not set +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +# CONFIG_CMD_ECHO is not set +# CONFIG_CMD_ITEST is not set +# CONFIG_CMD_SOURCE is not set +# CONFIG_CMD_SETEXPR is not set +# CONFIG_NET is not set +# CONFIG_DM_WARN is not set +# CONFIG_DM_DEVICE_REMOVE is not set +# CONFIG_MMC is not set +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_SOFT_RESET=y +CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_ISSI=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_MT35XU=y +CONFIG_ARM_DCC=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_CADENCE_QSPI=y +CONFIG_HAS_CQSPI_REF_CLK=y +CONFIG_CQSPI_REF_CLK=200000000 +CONFIG_CADENCE_OSPI_VERSAL=y +# CONFIG_LMB is not set diff --git a/configs/xilinx_versal_net_mini_qspi_defconfig b/configs/xilinx_versal_net_mini_qspi_defconfig new file mode 100644 index 0000000..a7ebc38 --- /dev/null +++ b/configs/xilinx_versal_net_mini_qspi_defconfig @@ -0,0 +1,75 @@ +CONFIG_ARM=y +CONFIG_SYS_CONFIG_NAME="xilinx_versal_net_mini" +CONFIG_COUNTER_FREQUENCY=100000000 +CONFIG_ARCH_VERSAL_NET=y +CONFIG_TEXT_BASE=0xBBF00000 +CONFIG_SYS_MALLOC_LEN=0x2000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xBBF20000 +CONFIG_SF_DEFAULT_SPEED=30000000 +CONFIG_ENV_SIZE=0x80 +CONFIG_DEFAULT_DEVICE_TREE="versal-net-mini-qspi-single" +CONFIG_SYS_PROMPT="Versal NET> " +CONFIG_SYS_MEM_RSVD_FOR_MMU=y +# CONFIG_PSCI_RESET is not set +CONFIG_SYS_LOAD_ADDR=0xBBF80000 +# CONFIG_EXPERT is not set +CONFIG_REMAKE_ELF=y +# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set +# CONFIG_AUTOBOOT is not set +CONFIG_LOGLEVEL=0 +CONFIG_SYS_CONSOLE_INFO_QUIET=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_BOARD_EARLY_INIT_R=y +# CONFIG_BOARD_LATE_INIT is not set +# CONFIG_CMDLINE_EDITING is not set +# CONFIG_AUTO_COMPLETE is not set +# CONFIG_SYS_LONGHELP is not set +# CONFIG_SYS_XTRACE is not set +# CONFIG_CMD_BDI is not set +# CONFIG_CMD_CONSOLE is not set +# CONFIG_CMD_BOOTD is not set +# CONFIG_CMD_BOOTM is not set +# CONFIG_CMD_BOOTI is not set +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_FDT is not set +# CONFIG_CMD_GO is not set +# CONFIG_CMD_RUN is not set +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_EDITENV is not set +# CONFIG_CMD_SAVEENV is not set +# CONFIG_CMD_ENV_EXISTS is not set +# CONFIG_CMD_CRC32 is not set +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +# CONFIG_CMD_ECHO is not set +# CONFIG_CMD_ITEST is not set +# CONFIG_CMD_SOURCE is not set +# CONFIG_CMD_SETEXPR is not set +# CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG is not set +# CONFIG_NET is not set +# CONFIG_DM_WARN is not set +# CONFIG_DM_DEVICE_REMOVE is not set +# CONFIG_GPIO is not set +# CONFIG_I2C is not set +# CONFIG_INPUT is not set +# CONFIG_MMC is not set +CONFIG_DM_SPI_FLASH=y +# CONFIG_SPI_FLASH_SMART_HWCAPS is not set +# CONFIG_SPI_FLASH_UNLOCK_ALL is not set +CONFIG_SPI_FLASH_ISSI=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +# CONFIG_POWER is not set +CONFIG_ARM_DCC=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_ZYNQMP_GQSPI=y +# CONFIG_LMB is not set diff --git a/configs/xilinx_zynq_virt_defconfig b/configs/xilinx_zynq_virt_defconfig index 474abc7..9900577 100644 --- a/configs/xilinx_zynq_virt_defconfig +++ b/configs/xilinx_zynq_virt_defconfig @@ -7,6 +7,7 @@ CONFIG_SF_DEFAULT_SPEED=30000000 CONFIG_ENV_OFFSET=0xE00000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="zynq-zc706" +CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_SPL_STACK_R_ADDR=0x200000 CONFIG_SPL_STACK=0xfffffe00 CONFIG_SPL=y diff --git a/drivers/ata/sata_ceva.c b/drivers/ata/sata_ceva.c index 43bcc59..4736643 100644 --- a/drivers/ata/sata_ceva.c +++ b/drivers/ata/sata_ceva.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * (C) Copyright 2015 - 2016 Xilinx, Inc. - * Michal Simek <michal.simek@xilinx.com> + * Michal Simek <michal.simek@amd.com> */ #include <common.h> #include <dm.h> diff --git a/drivers/clk/clk_versal.c b/drivers/clk/clk_versal.c index faebbab..b3b3333 100644 --- a/drivers/clk/clk_versal.c +++ b/drivers/clk/clk_versal.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * (C) Copyright 2019 Xilinx, Inc. - * Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> + * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>> */ #include <common.h> diff --git a/drivers/clk/clk_zynqmp.c b/drivers/clk/clk_zynqmp.c index be0ee50..1cfe0e2 100644 --- a/drivers/clk/clk_zynqmp.c +++ b/drivers/clk/clk_zynqmp.c @@ -12,6 +12,7 @@ #include <linux/bitops.h> #include <clk-uclass.h> #include <clk.h> +#include <zynqmp_firmware.h> #include <asm/arch/sys_proto.h> #include <dm.h> #include <linux/err.h> @@ -269,17 +270,22 @@ static u32 zynqmp_clk_get_register(enum zynqmp_clk id) case usb3_dual_ref: return CRL_APB_USB3_DUAL_REF_CTRL; case gem_tsu_ref: + case gem_tsu: return CRL_APB_GEM_TSU_REF_CTRL; case gem0_tx: + case gem0_rx: case gem0_ref: return CRL_APB_GEM0_REF_CTRL; case gem1_tx: + case gem1_rx: case gem1_ref: return CRL_APB_GEM1_REF_CTRL; case gem2_tx: + case gem2_rx: case gem2_ref: return CRL_APB_GEM2_REF_CTRL; case gem3_tx: + case gem3_rx: case gem3_ref: return CRL_APB_GEM3_REF_CTRL; case usb0_bus_ref: @@ -718,6 +724,8 @@ static ulong zynqmp_clk_set_rate(struct clk *clk, ulong rate) switch (id) { case gem0_ref ... gem3_ref: case gem0_tx ... gem3_tx: + case gem0_rx ... gem3_rx: + case gem_tsu: case qspi_ref ... can1_ref: case usb0_bus_ref ... usb3_dual_ref: return zynqmp_clk_set_peripheral_rate(priv, id, diff --git a/drivers/core/of_access.c b/drivers/core/of_access.c index 81a3079..57f1044 100644 --- a/drivers/core/of_access.c +++ b/drivers/core/of_access.c @@ -593,11 +593,14 @@ int of_read_u64(const struct device_node *np, const char *propname, u64 *outp) int of_property_match_string(const struct device_node *np, const char *propname, const char *string) { - const struct property *prop = of_find_property(np, propname, NULL); + int len = 0; + const struct property *prop = of_find_property(np, propname, &len); size_t l; int i; const char *p, *end; + if (!prop && len == -FDT_ERR_NOTFOUND) + return -ENOENT; if (!prop) return -EINVAL; if (!prop->value) diff --git a/drivers/core/read.c b/drivers/core/read.c index 0289a2e..5749473 100644 --- a/drivers/core/read.c +++ b/drivers/core/read.c @@ -211,10 +211,9 @@ void *dev_remap_addr(const struct udevice *dev) return dev_remap_addr_index(dev, 0); } -fdt_addr_t dev_read_addr_size(const struct udevice *dev, const char *property, - fdt_size_t *sizep) +fdt_addr_t dev_read_addr_size(const struct udevice *dev, fdt_size_t *sizep) { - return ofnode_get_addr_size(dev_ofnode(dev), property, sizep); + return dev_read_addr_size_index(dev, 0, sizep); } const char *dev_read_name(const struct udevice *dev) diff --git a/drivers/fpga/fpga.c b/drivers/fpga/fpga.c index 7f6b6bc..81e6d8f 100644 --- a/drivers/fpga/fpga.c +++ b/drivers/fpga/fpga.c @@ -244,6 +244,21 @@ int fpga_loads(int devnum, const void *buf, size_t size, } #endif +static int fpga_load_event_notify(const void *buf, size_t bsize, int result) +{ + if (CONFIG_IS_ENABLED(EVENT)) { + struct event_fpga_load load = { + .buf = buf, + .bsize = bsize, + .result = result + }; + + return event_notify(EVT_FPGA_LOAD, &load, sizeof(load)); + } + + return 0; +} + /* * Generic multiplexing code */ @@ -251,6 +266,7 @@ int fpga_load(int devnum, const void *buf, size_t bsize, bitstream_type bstype, int flags) { int ret_val = FPGA_FAIL; /* assume failure */ + int ret_notify; const fpga_desc *desc = fpga_validate(devnum, buf, bsize, (char *)__func__); @@ -284,6 +300,10 @@ int fpga_load(int devnum, const void *buf, size_t bsize, bitstream_type bstype, } } + ret_notify = fpga_load_event_notify(buf, bsize, ret_val); + if (ret_notify) + return ret_notify; + return ret_val; } diff --git a/drivers/fpga/versalpl.c b/drivers/fpga/versalpl.c index d3876a8..be58db5 100644 --- a/drivers/fpga/versalpl.c +++ b/drivers/fpga/versalpl.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* * (C) Copyright 2019, Xilinx, Inc, - * Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> + * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>> */ #include <common.h> diff --git a/drivers/fpga/zynqmppl.c b/drivers/fpga/zynqmppl.c index 7b5128f..b1f201f 100644 --- a/drivers/fpga/zynqmppl.c +++ b/drivers/fpga/zynqmppl.c @@ -1,8 +1,8 @@ // SPDX-License-Identifier: GPL-2.0 /* * (C) Copyright 2015 - 2016, Xilinx, Inc, - * Michal Simek <michal.simek@xilinx.com> - * Siva Durga Prasad <siva.durga.paladugu@xilinx.com> + * Michal Simek <michal.simek@amd.com> + * Siva Durga Prasad <siva.durga.prasad.paladugu@amd.com>> */ #include <console.h> diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c index e779251..935540d 100644 --- a/drivers/mmc/zynq_sdhci.c +++ b/drivers/mmc/zynq_sdhci.c @@ -422,7 +422,8 @@ static int arasan_sdhci_execute_tuning(struct mmc *mmc, u8 opcode) mdelay(1); - arasan_zynqmp_dll_reset(host, priv->node_id); + if (device_is_compatible(mmc->dev, "xlnx,zynqmp-8.9a")) + arasan_zynqmp_dll_reset(host, priv->node_id); sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE); sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE); @@ -468,7 +469,9 @@ static int arasan_sdhci_execute_tuning(struct mmc *mmc, u8 opcode) } udelay(1); - arasan_zynqmp_dll_reset(host, priv->node_id); + + if (device_is_compatible(mmc->dev, "xlnx,zynqmp-8.9a")) + arasan_zynqmp_dll_reset(host, priv->node_id); /* Enable only interrupts served by the SD controller */ sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK, diff --git a/drivers/mtd/Kconfig b/drivers/mtd/Kconfig index 5fa88da..c56840c 100644 --- a/drivers/mtd/Kconfig +++ b/drivers/mtd/Kconfig @@ -128,7 +128,7 @@ config FLASH_SPANSION_S29WS_N config FLASH_CFI_MTD bool "Enable CFI MTD driver" - depends on FLASH_CFI_DRIVER + depends on FLASH_CFI_DRIVER && MTD help This option enables the building of the cfi_mtd driver in the drivers directory. The driver exports CFI flash diff --git a/drivers/mtd/nand/raw/zynq_nand.c b/drivers/mtd/nand/raw/zynq_nand.c index 9e3ee74..545fdd7 100644 --- a/drivers/mtd/nand/raw/zynq_nand.c +++ b/drivers/mtd/nand/raw/zynq_nand.c @@ -285,7 +285,7 @@ static int zynq_nand_init_nand_flash(struct mtd_info *mtd, int option) { struct nand_chip *nand_chip = mtd_to_nand(mtd); struct nand_drv *smc = nand_get_controller_data(nand_chip); - u32 status; + int status; /* disable interrupts */ writel(ZYNQ_NAND_CLR_CONFIG, &smc->reg->cfr); @@ -332,7 +332,7 @@ static int zynq_nand_calculate_hwecc(struct mtd_info *mtd, const u8 *data, struct nand_drv *smc = nand_get_controller_data(nand_chip); u32 ecc_value = 0; u8 ecc_reg, ecc_byte; - u32 ecc_status; + int ecc_status; /* Wait till the ECC operation is complete */ ecc_status = zynq_nand_waitfor_ecc_completion(mtd); diff --git a/drivers/net/xilinx_axi_emac.c b/drivers/net/xilinx_axi_emac.c index 3e99199..39cb3cc 100644 --- a/drivers/net/xilinx_axi_emac.c +++ b/drivers/net/xilinx_axi_emac.c @@ -748,7 +748,7 @@ static int axiemac_recv(struct udevice *dev, int flags, uchar **packetp) /* Wait for an incoming packet */ if (!isrxready(priv)) - return -1; + return -EAGAIN; debug("axiemac: RX data ready\n"); diff --git a/drivers/net/xilinx_axi_mrmac.c b/drivers/net/xilinx_axi_mrmac.c index 6d15386..410fb25 100644 --- a/drivers/net/xilinx_axi_mrmac.c +++ b/drivers/net/xilinx_axi_mrmac.c @@ -3,7 +3,7 @@ * Xilinx Multirate Ethernet MAC(MRMAC) driver * * Author(s): Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> - * Michal Simek <michal.simek@xilinx.com> + * Michal Simek <michal.simek@amd.com> * * Copyright (C) 2021 Xilinx, Inc. All rights reserved. */ diff --git a/drivers/net/xilinx_axi_mrmac.h b/drivers/net/xilinx_axi_mrmac.h index 4f87585..e2c2105 100644 --- a/drivers/net/xilinx_axi_mrmac.h +++ b/drivers/net/xilinx_axi_mrmac.h @@ -3,7 +3,7 @@ * Xilinx Multirate Ethernet MAC(MRMAC) driver * * Author(s): Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> - * Michal Simek <michal.simek@xilinx.com> + * Michal Simek <michal.simek@amd.com> * * Copyright (C) 2021 Xilinx, Inc. All rights reserved. */ diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index 211b2c6..f3cdfb0 100644 --- a/drivers/net/zynq_gem.c +++ b/drivers/net/zynq_gem.c @@ -30,6 +30,7 @@ #include <asm/arch/hardware.h> #include <asm/arch/sys_proto.h> #include <dm/device_compat.h> +#include <linux/bitfield.h> #include <linux/bitops.h> #include <linux/err.h> #include <linux/errno.h> @@ -67,11 +68,6 @@ #define ZYNQ_GEM_NWCFG_FSREM 0x00020000 /* FCS removal */ #define ZYNQ_GEM_NWCFG_SGMII_ENBL 0x08000000 /* SGMII Enable */ #define ZYNQ_GEM_NWCFG_PCS_SEL 0x00000800 /* PCS select */ -#ifdef CONFIG_ARM64 -#define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x00100000 /* Div pclk by 64, max 160MHz */ -#else -#define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x000c0000 /* Div pclk by 48, max 120MHz */ -#endif #ifdef CONFIG_ARM64 # define ZYNQ_GEM_DBUS_WIDTH (1 << 21) /* 64 bit bus */ @@ -81,8 +77,7 @@ #define ZYNQ_GEM_NWCFG_INIT (ZYNQ_GEM_DBUS_WIDTH | \ ZYNQ_GEM_NWCFG_FDEN | \ - ZYNQ_GEM_NWCFG_FSREM | \ - ZYNQ_GEM_NWCFG_MDCCLKDIV) + ZYNQ_GEM_NWCFG_FSREM) #define ZYNQ_GEM_NWSR_MDIOIDLE_MASK 0x00000004 /* PHY management idle */ @@ -141,6 +136,18 @@ #define RXCLK_EN BIT(0) +/* GEM specific constants for CLK. */ +#define GEM_CLK_DIV8 0 +#define GEM_CLK_DIV16 1 +#define GEM_CLK_DIV32 2 +#define GEM_CLK_DIV48 3 +#define GEM_CLK_DIV64 4 +#define GEM_CLK_DIV96 5 +#define GEM_CLK_DIV128 6 +#define GEM_CLK_DIV224 7 + +#define GEM_MDC_SET(val) FIELD_PREP(GENMASK(20, 18), val) + /* Device registers */ struct zynq_gem_regs { u32 nwctrl; /* 0x0 - Network Control reg */ @@ -220,6 +227,7 @@ struct zynq_gem_priv { struct mii_dev *bus; struct clk rx_clk; struct clk tx_clk; + struct clk pclk; u32 max_speed; bool int_pcs; bool dma_64bit; @@ -352,6 +360,32 @@ static int zynq_phy_init(struct udevice *dev) return phy_config(priv->phydev); } +static u32 gem_mdc_clk_div(struct zynq_gem_priv *priv) +{ + u32 config; + unsigned long pclk_hz; + + pclk_hz = clk_get_rate(&priv->pclk); + if (pclk_hz <= 20000000) + config = GEM_MDC_SET(GEM_CLK_DIV8); + else if (pclk_hz <= 40000000) + config = GEM_MDC_SET(GEM_CLK_DIV16); + else if (pclk_hz <= 80000000) + config = GEM_MDC_SET(GEM_CLK_DIV32); + else if (pclk_hz <= 120000000) + config = GEM_MDC_SET(GEM_CLK_DIV48); + else if (pclk_hz <= 160000000) + config = GEM_MDC_SET(GEM_CLK_DIV64); + else if (pclk_hz <= 240000000) + config = GEM_MDC_SET(GEM_CLK_DIV96); + else if (pclk_hz <= 320000000) + config = GEM_MDC_SET(GEM_CLK_DIV128); + else + config = GEM_MDC_SET(GEM_CLK_DIV224); + + return config; +} + static int zynq_gem_init(struct udevice *dev) { u32 i, nwconfig; @@ -460,7 +494,8 @@ static int zynq_gem_init(struct udevice *dev) return -1; } - nwconfig = ZYNQ_GEM_NWCFG_INIT; + nwconfig = gem_mdc_clk_div(priv); + nwconfig |= ZYNQ_GEM_NWCFG_INIT; /* * Set SGMII enable PCS selection only if internal PCS/PMA @@ -828,6 +863,12 @@ static int zynq_gem_probe(struct udevice *dev) } } + ret = clk_get_by_name(dev, "pclk", &priv->pclk); + if (ret < 0) { + dev_err(dev, "failed to get pclk clock\n"); + goto err2; + } + if (IS_ENABLED(CONFIG_DM_ETH_PHY)) priv->bus = eth_phy_get_mdio_bus(dev); diff --git a/drivers/pinctrl/pinctrl-zynqmp.c b/drivers/pinctrl/pinctrl-zynqmp.c index ee6529b..02626a7 100644 --- a/drivers/pinctrl/pinctrl-zynqmp.c +++ b/drivers/pinctrl/pinctrl-zynqmp.c @@ -3,7 +3,7 @@ * Xilinx pinctrl driver for ZynqMP * * Author(s): Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> - * Michal Simek <michal.simek@xilinx.com> + * Michal Simek <michal.simek@amd.com> * * Copyright (C) 2021 Xilinx, Inc. All rights reserved. */ diff --git a/drivers/reset/reset-rockchip.c b/drivers/reset/reset-rockchip.c index 2ebe338..6cabaa1 100644 --- a/drivers/reset/reset-rockchip.c +++ b/drivers/reset/reset-rockchip.c @@ -97,7 +97,7 @@ static int rockchip_reset_probe(struct udevice *dev) fdt_addr_t addr; fdt_size_t size; - addr = dev_read_addr_size(dev, "reg", &size); + addr = dev_read_addr_size(dev, &size); if (addr == FDT_ADDR_T_NONE) return -EINVAL; diff --git a/drivers/soc/soc_xilinx_zynqmp.c b/drivers/soc/soc_xilinx_zynqmp.c index afa277f..d9a5944 100644 --- a/drivers/soc/soc_xilinx_zynqmp.c +++ b/drivers/soc/soc_xilinx_zynqmp.c @@ -3,7 +3,7 @@ * Xilinx ZynqMP SOC driver * * Copyright (C) 2021 Xilinx, Inc. - * Michal Simek <michal.simek@xilinx.com> + * Michal Simek <michal.simek@amd.com> * * Copyright (C) 2022 Weidmüller Interface GmbH & Co. KG * Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com> diff --git a/drivers/spi/cadence_ospi_versal.c b/drivers/spi/cadence_ospi_versal.c index 434c603..a7685a2 100644 --- a/drivers/spi/cadence_ospi_versal.c +++ b/drivers/spi/cadence_ospi_versal.c @@ -130,7 +130,6 @@ int cadence_qspi_apb_wait_for_dma_cmplt(struct cadence_spi_priv *priv) #if defined(CONFIG_DM_GPIO) int cadence_qspi_versal_flash_reset(struct udevice *dev) { -#ifndef CONFIG_ARCH_VERSAL_NET struct gpio_desc gpio; u32 reset_gpio; int ret; @@ -166,7 +165,7 @@ int cadence_qspi_versal_flash_reset(struct udevice *dev) /* Set value 1 to pin */ dm_gpio_set_value(&gpio, 1); udelay(1); -#endif + return 0; } #else diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c index 2d715e4..cc3a54f 100644 --- a/drivers/spi/cadence_qspi.c +++ b/drivers/spi/cadence_qspi.c @@ -249,17 +249,14 @@ static int cadence_spi_probe(struct udevice *bus) priv->wr_delay = 50 * DIV_ROUND_UP(NSEC_PER_SEC, priv->ref_clk_hz); - if (IS_ENABLED(CONFIG_ARCH_VERSAL)) { - /* Versal platform uses spi calibration to set read delay */ + /* Versal and Versal-NET use spi calibration to set read delay */ + if (CONFIG_IS_ENABLED(ARCH_VERSAL) || + CONFIG_IS_ENABLED(ARCH_VERSAL_NET)) if (priv->read_delay >= 0) priv->read_delay = -1; - /* Reset ospi flash device */ - ret = cadence_qspi_versal_flash_reset(bus); - if (ret) - return ret; - } - return 0; + /* Reset ospi flash device */ + return cadence_qspi_versal_flash_reset(bus); } static int cadence_spi_remove(struct udevice *dev) diff --git a/drivers/spi/xilinx_spi.c b/drivers/spi/xilinx_spi.c index 33575fe..b58a3f6 100644 --- a/drivers/spi/xilinx_spi.c +++ b/drivers/spi/xilinx_spi.c @@ -363,8 +363,8 @@ static int xilinx_qspi_check_buswidth(struct spi_slave *slave, u8 width) return -EOPNOTSUPP; } -bool xilinx_qspi_mem_exec_op(struct spi_slave *slave, - const struct spi_mem_op *op) +static bool xilinx_qspi_mem_exec_op(struct spi_slave *slave, + const struct spi_mem_op *op) { if (xilinx_qspi_check_buswidth(slave, op->cmd.buswidth)) return false; diff --git a/drivers/spi/zynq_qspi.c b/drivers/spi/zynq_qspi.c index d1d4048..cb52c0f 100644 --- a/drivers/spi/zynq_qspi.c +++ b/drivers/spi/zynq_qspi.c @@ -747,8 +747,8 @@ static int zynq_qspi_check_buswidth(struct spi_slave *slave, u8 width) return -EOPNOTSUPP; } -bool zynq_qspi_mem_exec_op(struct spi_slave *slave, - const struct spi_mem_op *op) +static bool zynq_qspi_mem_exec_op(struct spi_slave *slave, + const struct spi_mem_op *op) { if (zynq_qspi_check_buswidth(slave, op->cmd.buswidth)) return false; diff --git a/drivers/watchdog/xilinx_tb_wdt.c b/drivers/watchdog/xilinx_tb_wdt.c index 0f9fb02..b38c400 100644 --- a/drivers/watchdog/xilinx_tb_wdt.c +++ b/drivers/watchdog/xilinx_tb_wdt.c @@ -2,7 +2,7 @@ /* * Xilinx AXI platforms watchdog timer driver. * - * Author(s): Michal Simek <michal.simek@xilinx.com> + * Author(s): Michal Simek <michal.simek@amd.com> * Shreenidhi Shedi <yesshedi@gmail.com> * * Copyright (c) 2011-2018 Xilinx Inc. diff --git a/drivers/watchdog/xilinx_wwdt.c b/drivers/watchdog/xilinx_wwdt.c index d582e3c..963ab22 100644 --- a/drivers/watchdog/xilinx_wwdt.c +++ b/drivers/watchdog/xilinx_wwdt.c @@ -2,7 +2,7 @@ /* * Xilinx window watchdog timer driver. * - * Author(s): Michal Simek <michal.simek@xilinx.com> + * Author(s): Michal Simek <michal.simek@amd.com> * Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> * * Copyright (c) 2020, Xilinx Inc. @@ -191,7 +191,8 @@ static const struct wdt_ops xlnx_wwdt_ops = { }; static const struct udevice_id xlnx_wwdt_ids[] = { - { .compatible = "xlnx,versal-wwdt-1.0", }, + { .compatible = "xlnx,versal-wwdt", }, + { .compatible = "xlnx,versal-wwdt-1.0", }, /* deprecated */ {}, }; diff --git a/include/configs/xilinx_versal.h b/include/configs/xilinx_versal.h index e70acd9..a403999 100644 --- a/include/configs/xilinx_versal.h +++ b/include/configs/xilinx_versal.h @@ -2,7 +2,7 @@ /* * Configuration for Xilinx Versal * (C) Copyright 2016 - 2018 Xilinx, Inc. - * Michal Simek <michal.simek@xilinx.com> + * Michal Simek <michal.simek@amd.com> * * Based on Configuration for Xilinx ZynqMP */ diff --git a/include/configs/xilinx_versal_mini.h b/include/configs/xilinx_versal_mini.h index 23655a4..628fd80 100644 --- a/include/configs/xilinx_versal_mini.h +++ b/include/configs/xilinx_versal_mini.h @@ -3,8 +3,8 @@ * Configuration for Xilinx Versal MINI configuration * * (C) Copyright 2018-2019 Xilinx, Inc. - * Michal Simek <michal.simek@xilinx.com> - * Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> + * Michal Simek <michal.simek@amd.com> + * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>> */ #ifndef __CONFIG_VERSAL_MINI_H diff --git a/include/configs/xilinx_versal_net.h b/include/configs/xilinx_versal_net.h index 424ead0..613cce4 100644 --- a/include/configs/xilinx_versal_net.h +++ b/include/configs/xilinx_versal_net.h @@ -76,20 +76,24 @@ # define BOOT_TARGET_DEVICES_DHCP(func) #endif -#if defined(CONFIG_ZYNQMP_GQSPI) || defined(CONFIG_CADENCE_OSPI_VERSAL_NET) -# define BOOT_TARGET_DEVICES_XSPI(func) func(XSPI, xspi, 0) +#if defined(CONFIG_ZYNQMP_GQSPI) || defined(CONFIG_CADENCE_OSPI_VERSAL) +# define BOOT_TARGET_DEVICES_XSPI(func) func(XSPI, xspi, 0) func(XSPI, xspi, 1) +# define BOOTENV_DEV_SHARED_XSPI \ + "xspi_boot=sf probe $devnum_xspi:0 0 0 && " \ + "sf read $scriptaddr $script_offset_f $script_size_f && " \ + "echo XSPI: Trying to boot script at ${scriptaddr} && " \ + "source ${scriptaddr}; echo XSPI: SCRIPT FAILED: continuing...;\0" #else # define BOOT_TARGET_DEVICES_XSPI(func) +# define BOOTENV_DEV_SHARED_XSPI #endif #define BOOTENV_DEV_XSPI(devtypeu, devtypel, instance) \ - "bootcmd_xspi0=sf probe 0 0 0 && " \ - "sf read $scriptaddr $script_offset_f $script_size_f && " \ - "echo XSPI: Trying to boot script at ${scriptaddr} && " \ - "source ${scriptaddr}; echo XSPI: SCRIPT FAILED: continuing...;\0" + "bootcmd_" #devtypel #instance "=" \ + "devnum_xspi=" #instance "; run " #devtypel "_boot\0" \ #define BOOTENV_DEV_NAME_XSPI(devtypeu, devtypel, instance) \ - "xspi0 " + "" #define BOOT_TARGET_DEVICES_JTAG(func) func(JTAG, jtag, na) @@ -127,6 +131,7 @@ #define CFG_EXTRA_ENV_SETTINGS \ ENV_MEM_LAYOUT_SETTINGS \ BOOTENV \ + BOOTENV_DEV_SHARED_XSPI \ DFU_ALT_INFO #endif diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index 995427d..74264b7 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -2,7 +2,7 @@ /* * Configuration for Xilinx ZynqMP * (C) Copyright 2014 - 2015 Xilinx, Inc. - * Michal Simek <michal.simek@xilinx.com> + * Michal Simek <michal.simek@amd.com> * * Based on Configuration for Versatile Express */ diff --git a/include/configs/xilinx_zynqmp_mini.h b/include/configs/xilinx_zynqmp_mini.h index 9af0545..8afccb7 100644 --- a/include/configs/xilinx_zynqmp_mini.h +++ b/include/configs/xilinx_zynqmp_mini.h @@ -3,8 +3,8 @@ * Configuration for Xilinx ZynqMP Flash utility * * (C) Copyright 2018 Xilinx, Inc. - * Michal Simek <michal.simek@xilinx.com> - * Siva Durga Prasad Paladugu <sivadur@xilinx.com> + * Michal Simek <michal.simek@amd.com> + * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>> */ #ifndef __CONFIG_ZYNQMP_MINI_H diff --git a/include/configs/xilinx_zynqmp_mini_nand.h b/include/configs/xilinx_zynqmp_mini_nand.h index 1b6e26e..cf3747a 100644 --- a/include/configs/xilinx_zynqmp_mini_nand.h +++ b/include/configs/xilinx_zynqmp_mini_nand.h @@ -3,8 +3,8 @@ * Configuration for Xilinx ZynqMP Nand Flash utility * * (C) Copyright 2018 Xilinx, Inc. - * Michal Simek <michal.simek@xilinx.com> - * Siva Durga Prasad Paladugu <sivadur@xilinx.com> + * Michal Simek <michal.simek@amd.com> + * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>> */ #ifndef __CONFIG_ZYNQMP_MINI_NAND_H diff --git a/include/dm/read.h b/include/dm/read.h index 56ac076..137f2a5 100644 --- a/include/dm/read.h +++ b/include/dm/read.h @@ -347,18 +347,13 @@ fdt_addr_t dev_read_addr_pci(const struct udevice *dev); void *dev_remap_addr(const struct udevice *dev); /** - * dev_read_addr_size() - get address and size from a device property - * - * This does no address translation. It simply reads an property that contains - * an address and a size value, one after the other. + * dev_read_addr_size() - Get the reg property of a device * * @dev: Device to read from - * @propname: property to read * @sizep: place to put size value (on success) * Return: address value, or FDT_ADDR_T_NONE on error */ -fdt_addr_t dev_read_addr_size(const struct udevice *dev, const char *propname, - fdt_size_t *sizep); +fdt_addr_t dev_read_addr_size(const struct udevice *dev, fdt_size_t *sizep); /** * dev_read_name() - get the name of a device's node @@ -1002,10 +997,9 @@ static inline void *dev_remap_addr_name(const struct udevice *dev, } static inline fdt_addr_t dev_read_addr_size(const struct udevice *dev, - const char *propname, fdt_size_t *sizep) { - return ofnode_get_addr_size(dev_ofnode(dev), propname, sizep); + return dev_read_addr_size_index(dev, 0, sizep); } static inline const char *dev_read_name(const struct udevice *dev) diff --git a/include/event.h b/include/event.h index fe41080..daf44bf 100644 --- a/include/event.h +++ b/include/event.h @@ -11,6 +11,7 @@ #define __event_h #include <dm/ofnode_decl.h> +#include <linux/types.h> /** * enum event_t - Types of events supported by U-Boot @@ -31,6 +32,9 @@ enum event_t { /* Init hooks */ EVT_MISC_INIT_F, + /* Fpga load hook */ + EVT_FPGA_LOAD, + /* Device tree fixups before booting */ EVT_FT_FIXUP, @@ -60,6 +64,19 @@ union event_data { } dm; /** + * struct event_fpga_load - fpga load event + * + * @buf: The buffer that was loaded into the fpga + * @bsize: The size of the buffer that was loaded into the fpga + * @result: Result of the load operation + */ + struct event_fpga_load { + const void *buf; + size_t bsize; + int result; + } fpga_load; + + /** * struct event_ft_fixup - FDT fixup before booting * * @tree: tree to update diff --git a/include/spl.h b/include/spl.h index 658d364..92bcaa9 100644 --- a/include/spl.h +++ b/include/spl.h @@ -31,6 +31,7 @@ struct legacy_img_hdr; struct blk_desc; struct legacy_img_hdr; struct spl_boot_device; +enum boot_device; /* * u_boot_first_phase() - check if this is the first U-Boot phase @@ -525,7 +526,7 @@ void spl_board_prepare_for_linux(void); void spl_board_prepare_for_optee(void *fdt); void spl_board_prepare_for_boot(void); int spl_board_ubi_load_image(u32 boot_device); -int spl_board_boot_device(u32 boot_device); +int spl_board_boot_device(enum boot_device boot_dev_spl); /** * spl_board_loader_name() - Return a name for the loader diff --git a/include/versalpl.h b/include/versalpl.h index 0cc101b..7dae56b 100644 --- a/include/versalpl.h +++ b/include/versalpl.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* * (C) Copyright 2019 Xilinx, Inc, - * Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> + * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>> */ #ifndef _VERSALPL_H_ diff --git a/include/zynqmp_firmware.h b/include/zynqmp_firmware.h index 1192d59..18a87d2 100644 --- a/include/zynqmp_firmware.h +++ b/include/zynqmp_firmware.h @@ -454,6 +454,8 @@ int zynqmp_pm_set_sd_config(u32 node, enum pm_sd_config_type config, u32 value); int zynqmp_pm_set_gem_config(u32 node, enum pm_gem_config_type config, u32 value); int zynqmp_pm_is_function_supported(const u32 api_id, const u32 id); +int zynqmp_mmio_read(const u32 address, u32 *value); +int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value); /* Type of Config Object */ #define PM_CONFIG_OBJECT_TYPE_BASE 0x1U diff --git a/include/zynqmppl.h b/include/zynqmppl.h index acf75a8..3fd334a 100644 --- a/include/zynqmppl.h +++ b/include/zynqmppl.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* * (C) Copyright 2015 Xilinx, Inc, - * Michal Simek <michal.simek@xilinx.com> + * Michal Simek <michal.simek@amd.com> */ #ifndef _ZYNQMPPL_H_ diff --git a/test/dm/video.c b/test/dm/video.c index 0534ee9..d907f68 100644 --- a/test/dm/video.c +++ b/test/dm/video.c @@ -15,6 +15,7 @@ #include <video.h> #include <video_console.h> #include <asm/test.h> +#include <asm/sdl.h> #include <dm/test.h> #include <dm/uclass-internal.h> #include <test/test.h> diff --git a/tools/binman/binman.rst b/tools/binman/binman.rst index 23cbb99..8f57b6c 100644 --- a/tools/binman/binman.rst +++ b/tools/binman/binman.rst @@ -727,6 +727,13 @@ optional: Note that missing, optional blobs do not produce a non-zero exit code from binman, although it does show a warning about the missing external blob. +insert-template: + This is not strictly speaking an entry property, since it is processed early + in Binman before the entries are read. It is a list of phandles of nodes to + include in the current (target) node. For each node, its subnodes and their + properties are brought into the target node. See Templates_ below for + more information. + The attributes supported for images and sections are described below. Several are similar to those for entries. @@ -831,6 +838,13 @@ write-symbols: binman. This is automatic for certain entry types, e.g. `u-boot-spl`. See binman_syms_ for more information. +no-write-symbols: + Disables symbol writing for this entry. This can be used in entry types + where symbol writing is automatic. For example, if `u-boot-spl` refers to + the `u_boot_any_image_pos` symbol but U-Boot is not available in the image + containing SPL, this can be used to disable the writing. Quite likely this + indicates a bug in your setup. + elf-filename: Sets the file name of a blob's associated ELF file. For example, if the blob is `zephyr.bin` then the ELF file may be `zephyr.elf`. This allows @@ -1165,6 +1179,86 @@ If you are having trouble figuring out what is going on, you can use arch/arm/dts/u-boot.dtsi ... found: "arch/arm/dts/juno-r2-u-boot.dtsi" +Templates +========= + +Sometimes multiple images need to be created which have all have a common +part. For example, a board may generate SPI and eMMC images which both include +a FIT. Since the FIT includes many entries, it is tedious to repeat them twice +in the image description. + +Templates provide a simple way to handle this:: + + binman { + multiple-images; + common_part: template-1 { + some-property; + fit { + ... lots of entries in here + }; + + text { + text = "base image"; + }; + }; + + spi-image { + filename = "image-spi.bin"; + insert-template = <&fit>; + + /* things specific to SPI follow */ + footer { + ]; + + text { + text = "SPI image"; + }; + }; + + mmc-image { + filename = "image-mmc.bin"; + insert-template = <&fit>; + + /* things specific to MMC follow */ + footer { + ]; + + text { + text = "MMC image"; + }; + }; + }; + +The template node name must start with 'template', so it is not considered to be +an image itself. + +The mechanism is very simple. For each phandle in the 'insert-templates' +property, the source node is looked up. Then the subnodes of that source node +are copied into the target node, i.e. the one containing the `insert-template` +property. + +If the target node has a node with the same name as a template, its properties +override corresponding properties in the template. This allows the template to +be uses as a base, with the node providing updates to the properties as needed. +The overriding happens recursively. + +Template nodes appear first in each node that they are inserted into and +ordering of template nodes is preserved. Other nodes come afterwards. If a +template node also appears in the target node, then the template node sets the +order. Thus the template can be used to set the ordering, even if the target +node provides all the properties. In the above example, `fit` and `text` appear +first in the `spi-image` and `mmc-image` images, followed by `footer`. + +Where there are multiple template nodes, they are inserted in that order. so +the first template node appears first, then the second. + +Properties in the template node are inserted into the destination node if they +do not exist there. In the example above, `some-property` is added to each of +`spi-image` and `mmc-image`. + +Note that template nodes are not removed from the binman description at present. + + Updating an ELF file ==================== diff --git a/tools/binman/bintool.py b/tools/binman/bintool.py index 8162968..0b0f56d 100644 --- a/tools/binman/bintool.py +++ b/tools/binman/bintool.py @@ -288,7 +288,7 @@ class Bintool: name = os.path.expanduser(self.name) # Expand paths containing ~ all_args = (name,) + args env = tools.get_env_with_path() - tout.detail(f"bintool: {' '.join(all_args)}") + tout.debug(f"bintool: {' '.join(all_args)}") result = command.run_pipe( [all_args], capture=True, capture_stderr=True, env=env, raise_on_error=False, binary=binary) diff --git a/tools/binman/control.py b/tools/binman/control.py index 7e2dd35..25e6681 100644 --- a/tools/binman/control.py +++ b/tools/binman/control.py @@ -22,6 +22,7 @@ from binman import bintool from binman import cbfs_util from binman import elf from binman import entry +from dtoc import fdt_util from u_boot_pylib import command from u_boot_pylib import tools from u_boot_pylib import tout @@ -56,8 +57,9 @@ def _ReadImageDesc(binman_node, use_expanded): images = OrderedDict() if 'multiple-images' in binman_node.props: for node in binman_node.subnodes: - images[node.name] = Image(node.name, node, - use_expanded=use_expanded) + if 'template' not in node.name: + images[node.name] = Image(node.name, node, + use_expanded=use_expanded) else: images['image'] = Image('image', binman_node, use_expanded=use_expanded) return images @@ -478,6 +480,30 @@ def SignEntries(image_fname, input_fname, privatekey_fname, algo, entry_paths, AfterReplace(image, allow_resize=True, write_map=write_map) +def _ProcessTemplates(parent): + """Handle any templates in the binman description + + Args: + parent: Binman node to process (typically /binman) + + Search though each target node looking for those with an 'insert-template' + property. Use that as a list of references to template nodes to use to + adjust the target node. + + Processing involves copying each subnode of the template node into the + target node. + + This is done recursively, so templates can be at any level of the binman + image, e.g. inside a section. + + See 'Templates' in the Binman documnentation for details. + """ + for node in parent.subnodes: + tmpl = fdt_util.GetPhandleList(node, 'insert-template') + if tmpl: + node.copy_subnodes_from_phandles(tmpl) + _ProcessTemplates(node) + def PrepareImagesAndDtbs(dtb_fname, select_images, update_fdt, use_expanded): """Prepare the images to be processed and select the device tree @@ -520,6 +546,8 @@ def PrepareImagesAndDtbs(dtb_fname, select_images, update_fdt, use_expanded): raise ValueError("Device tree '%s' does not have a 'binman' " "node" % dtb_fname) + _ProcessTemplates(node) + images = _ReadImageDesc(node, use_expanded) if select_images: diff --git a/tools/binman/elf.py b/tools/binman/elf.py index 5816284..4219001 100644 --- a/tools/binman/elf.py +++ b/tools/binman/elf.py @@ -248,6 +248,9 @@ def LookupAndWriteSymbols(elf_fname, entry, section, is_elf=False, entry: Entry to process section: Section which can be used to lookup symbol values base_sym: Base symbol marking the start of the image + + Returns: + int: Number of symbols written """ if not base_sym: base_sym = '__image_copy_start' @@ -269,12 +272,13 @@ def LookupAndWriteSymbols(elf_fname, entry, section, is_elf=False, if not syms: tout.debug('LookupAndWriteSymbols: no syms') - return + return 0 base = syms.get(base_sym) if not base and not is_elf: tout.debug('LookupAndWriteSymbols: no base') - return + return 0 base_addr = 0 if is_elf else base.address + count = 0 for name, sym in syms.items(): if name.startswith('_binman'): msg = ("Section '%s': Symbol '%s'\n in entry '%s'" % @@ -307,6 +311,11 @@ def LookupAndWriteSymbols(elf_fname, entry, section, is_elf=False, (msg, name, offset, value, len(value_bytes))) entry.data = (entry.data[:offset] + value_bytes + entry.data[offset + sym.size:]) + count += 1 + if count: + tout.detail( + f"Section '{section.GetPath()}': entry '{entry.GetPath()}' : {count} symbols") + return count def GetSymbolValue(sym, data, msg): """Get the value of a symbol diff --git a/tools/binman/elf_test.py b/tools/binman/elf_test.py index c980839..cc95b42 100644 --- a/tools/binman/elf_test.py +++ b/tools/binman/elf_test.py @@ -141,7 +141,8 @@ class TestElf(unittest.TestCase): entry = FakeEntry(10) section = FakeSection() elf_fname = self.ElfTestFile('u_boot_binman_syms_bad') - elf.LookupAndWriteSymbols(elf_fname, entry, section) + count = elf.LookupAndWriteSymbols(elf_fname, entry, section) + self.assertEqual(0, count) def testBadSymbolSize(self): """Test that an attempt to use an 8-bit symbol are detected @@ -162,7 +163,7 @@ class TestElf(unittest.TestCase): def testNoValue(self): """Test the case where we have no value for the symbol - This should produce -1 values for all thress symbols, taking up the + This should produce -1 values for all three symbols, taking up the first 16 bytes of the image. """ if not elf.ELF_TOOLS: @@ -170,7 +171,8 @@ class TestElf(unittest.TestCase): entry = FakeEntry(28) section = FakeSection(sym_value=None) elf_fname = self.ElfTestFile('u_boot_binman_syms') - elf.LookupAndWriteSymbols(elf_fname, entry, section) + count = elf.LookupAndWriteSymbols(elf_fname, entry, section) + self.assertEqual(5, count) expected = (struct.pack('<L', elf.BINMAN_SYM_MAGIC_VALUE) + tools.get_bytes(255, 20) + tools.get_bytes(ord('a'), 4)) @@ -369,6 +371,11 @@ class TestElf(unittest.TestCase): elf.GetSymbolOffset(fname, 'embed') self.assertIn('__image_copy_start', str(e.exception)) + def test_get_symbol_address(self): + fname = self.ElfTestFile('embed_data') + addr = elf.GetSymbolAddress(fname, 'region_size') + self.assertEqual(0, addr) + if __name__ == '__main__': unittest.main() diff --git a/tools/binman/entries.rst b/tools/binman/entries.rst index b71af80..b55f424 100644 --- a/tools/binman/entries.rst +++ b/tools/binman/entries.rst @@ -615,6 +615,12 @@ The top-level 'fit' node supports the following special properties: `of-list` meaning that `-a of-list="dtb1 dtb2..."` should be passed to binman. + fit,fdt-list-val + As an alternative to fit,fdt-list the list of device tree files + can be provided in this property as a string list, e.g.:: + + fit,fdt-list-val = "dtb1", "dtb2"; + Substitutions ~~~~~~~~~~~~~ diff --git a/tools/binman/entry.py b/tools/binman/entry.py index 3945690..42e0b7b 100644 --- a/tools/binman/entry.py +++ b/tools/binman/entry.py @@ -158,6 +158,7 @@ class Entry(object): self.offset_from_elf = None self.preserve = False self.build_done = False + self.no_write_symbols = False @staticmethod def FindEntryClass(etype, expanded): @@ -321,6 +322,7 @@ class Entry(object): 'offset-from-elf') self.preserve = fdt_util.GetBool(self._node, 'preserve') + self.no_write_symbols = fdt_util.GetBool(self._node, 'no-write-symbols') def GetDefaultFilename(self): return None @@ -472,6 +474,9 @@ class Entry(object): def ObtainContents(self, skip_entry=None, fake_size=0): """Figure out the contents of an entry. + For missing blobs (where allow-missing is enabled), the contents are set + to b'' and self.missing is set to True. + Args: skip_entry (Entry): Entry to skip when obtaining section contents fake_size (int): Size of fake file to create if needed @@ -695,7 +700,7 @@ class Entry(object): Args: section: Section containing the entry """ - if self.auto_write_symbols: + if self.auto_write_symbols and not self.no_write_symbols: # Check if we are writing symbols into an ELF file is_elf = self.GetDefaultFilename() == self.elf_fname elf.LookupAndWriteSymbols(self.elf_fname, self, section.GetImage(), @@ -1309,10 +1314,6 @@ features to produce new behaviours. """ data = b'' for entry in entries: - # First get the input data and put it in a file. If not available, - # try later. - if not entry.ObtainContents(fake_size=fake_size): - return None, None, None data += entry.GetData() uniq = self.GetUniqueName() fname = tools.get_output_filename(f'{prefix}.{uniq}') diff --git a/tools/binman/etype/blob_phase.py b/tools/binman/etype/blob_phase.py index b937158..951d993 100644 --- a/tools/binman/etype/blob_phase.py +++ b/tools/binman/etype/blob_phase.py @@ -52,3 +52,8 @@ class Entry_blob_phase(Entry_section): # Read entries again, now that we have some self.ReadEntries() + + # Propagate the no-write-symbols property + if self.no_write_symbols: + for entry in self._entries.values(): + entry.no_write_symbols = True diff --git a/tools/binman/etype/fit.py b/tools/binman/etype/fit.py index c395706..ef4d066 100644 --- a/tools/binman/etype/fit.py +++ b/tools/binman/etype/fit.py @@ -81,6 +81,12 @@ class Entry_fit(Entry_section): `of-list` meaning that `-a of-list="dtb1 dtb2..."` should be passed to binman. + fit,fdt-list-val + As an alternative to fit,fdt-list the list of device tree files + can be provided in this property as a string list, e.g.:: + + fit,fdt-list-val = "dtb1", "dtb2"; + Substitutions ~~~~~~~~~~~~~ @@ -361,6 +367,9 @@ class Entry_fit(Entry_section): [EntryArg(self._fit_list_prop.value, str)]) if fdts is not None: self._fdts = fdts.split() + else: + self._fdts = fdt_util.GetStringList(self._node, 'fit,fdt-list-val') + self._fit_default_dt = self.GetEntryArgsOrProps([EntryArg('default-dt', str)])[0] diff --git a/tools/binman/etype/mkimage.py b/tools/binman/etype/mkimage.py index e028c44..6ae5d0c 100644 --- a/tools/binman/etype/mkimage.py +++ b/tools/binman/etype/mkimage.py @@ -8,10 +8,11 @@ from collections import OrderedDict from binman.entry import Entry +from binman.etype.section import Entry_section from dtoc import fdt_util from u_boot_pylib import tools -class Entry_mkimage(Entry): +class Entry_mkimage(Entry_section): """Binary produced by mkimage Properties / Entry arguments: @@ -121,54 +122,67 @@ class Entry_mkimage(Entry): """ def __init__(self, section, etype, node): super().__init__(section, etype, node) - self._multiple_data_files = fdt_util.GetBool(self._node, 'multiple-data-files') - self._mkimage_entries = OrderedDict() self._imagename = None - self._filename = fdt_util.GetString(self._node, 'filename') - self.align_default = None + self._multiple_data_files = False def ReadNode(self): super().ReadNode() + self._multiple_data_files = fdt_util.GetBool(self._node, + 'multiple-data-files') self._args = fdt_util.GetArgs(self._node, 'args') self._data_to_imagename = fdt_util.GetBool(self._node, 'data-to-imagename') if self._data_to_imagename and self._node.FindNode('imagename'): self.Raise('Cannot use both imagename node and data-to-imagename') - self.ReadEntries() def ReadEntries(self): """Read the subnodes to find out what should go in this image""" for node in self._node.subnodes: - entry = Entry.Create(self, node) + if self.IsSpecialSubnode(node): + continue + entry = Entry.Create(self, node, + expanded=self.GetImage().use_expanded, + missing_etype=self.GetImage().missing_etype) entry.ReadNode() + entry.SetPrefix(self._name_prefix) if entry.name == 'imagename': self._imagename = entry else: - self._mkimage_entries[entry.name] = entry + self._entries[entry.name] = entry - def ObtainContents(self): + def BuildSectionData(self, required): + """Build mkimage entry contents + + Runs mkimage to build the entry contents + + Args: + required (bool): True if the data must be present, False if it is OK + to return None + + Returns: + bytes: Contents of the section + """ # Use a non-zero size for any fake files to keep mkimage happy # Note that testMkimageImagename() relies on this 'mkimage' parameter fake_size = 1024 if self._multiple_data_files: fnames = [] uniq = self.GetUniqueName() - for entry in self._mkimage_entries.values(): - if not entry.ObtainContents(fake_size=fake_size): - return False - if entry._pathname: - fnames.append(entry._pathname) + for entry in self._entries.values(): + # Put the contents in a temporary file + ename = f'mkimage-in-{uniq}-{entry.name}' + fname = tools.get_output_filename(ename) + data = entry.GetData(required) + tools.write_file(fname, data) + fnames.append(fname) input_fname = ":".join(fnames) + data = b'' else: data, input_fname, uniq = self.collect_contents_to_file( - self._mkimage_entries.values(), 'mkimage', fake_size) - if data is None: - return False + self._entries.values(), 'mkimage', fake_size) if self._imagename: image_data, imagename_fname, _ = self.collect_contents_to_file( [self._imagename], 'mkimage-n', 1024) - if image_data is None: - return False outfile = self._filename if self._filename else 'mkimage-out.%s' % uniq output_fname = tools.get_output_filename(outfile) @@ -176,8 +190,7 @@ class Entry_mkimage(Entry): self.CheckMissing(missing_list) self.missing = bool(missing_list) if self.missing: - self.SetContents(b'') - return self.allow_missing + return b'' args = ['-d', input_fname] if self._data_to_imagename: @@ -186,71 +199,58 @@ class Entry_mkimage(Entry): args += ['-n', imagename_fname] args += self._args + [output_fname] if self.mkimage.run_cmd(*args) is not None: - self.SetContents(tools.read_file(output_fname)) + return tools.read_file(output_fname) else: # Bintool is missing; just use the input data as the output self.record_missing_bintool(self.mkimage) - self.SetContents(data) - - return True + return data def GetEntries(self): # Make a copy so we don't change the original - entries = OrderedDict(self._mkimage_entries) + entries = OrderedDict(self._entries) if self._imagename: entries['imagename'] = self._imagename return entries - def SetAllowMissing(self, allow_missing): - """Set whether a section allows missing external blobs + def AddBintools(self, btools): + super().AddBintools(btools) + self.mkimage = self.AddBintool(btools, 'mkimage') - Args: - allow_missing: True if allowed, False if not allowed - """ - self.allow_missing = allow_missing - for entry in self._mkimage_entries.values(): - entry.SetAllowMissing(allow_missing) - if self._imagename: - self._imagename.SetAllowMissing(allow_missing) + def CheckEntries(self): + pass - def SetAllowFakeBlob(self, allow_fake): - """Set whether the sub nodes allows to create a fake blob + def ProcessContents(self): + # The blob may have changed due to WriteSymbols() + ok = super().ProcessContents() + data = self.BuildSectionData(True) + ok2 = self.ProcessContentsUpdate(data) + return ok and ok2 - Args: - allow_fake: True if allowed, False if not allowed - """ - for entry in self._mkimage_entries.values(): - entry.SetAllowFakeBlob(allow_fake) - if self._imagename: - self._imagename.SetAllowFakeBlob(allow_fake) + def SetImagePos(self, image_pos): + """Set the position in the image - def CheckMissing(self, missing_list): - """Check if any entries in this section have missing external blobs + This sets each subentry's offsets, sizes and positions-in-image + according to where they ended up in the packed mkimage file. - If there are missing (non-optional) blobs, the entries are added to the - list + NOTE: This assumes a legacy mkimage and assumes that the images are + written to the output in order. SoC-specific mkimage handling may not + conform to this, in which case these values may be wrong. Args: - missing_list: List of Entry objects to be added to + image_pos (int): Position of this entry in the image """ - for entry in self._mkimage_entries.values(): - entry.CheckMissing(missing_list) - if self._imagename: - self._imagename.CheckMissing(missing_list) + # The mkimage header consists of 0x40 bytes, following by a table of + # offsets for each file + upto = 0x40 - def CheckFakedBlobs(self, faked_blobs_list): - """Check if any entries in this section have faked external blobs + # Skip the 0-terminated list of offsets (assume a single image) + upto += 4 + 4 + for entry in self.GetEntries().values(): + entry.SetOffsetSize(upto, None) - If there are faked blobs, the entries are added to the list + # Give up if any entries lack a size + if entry.size is None: + return + upto += entry.size - Args: - faked_blobs_list: List of Entry objects to be added to - """ - for entry in self._mkimage_entries.values(): - entry.CheckFakedBlobs(faked_blobs_list) - if self._imagename: - self._imagename.CheckFakedBlobs(faked_blobs_list) - - def AddBintools(self, btools): - super().AddBintools(btools) - self.mkimage = self.AddBintool(btools, 'mkimage') + super().SetImagePos(image_pos) diff --git a/tools/binman/etype/section.py b/tools/binman/etype/section.py index c36edd1..7c4d312 100644 --- a/tools/binman/etype/section.py +++ b/tools/binman/etype/section.py @@ -168,6 +168,7 @@ class Entry_section(Entry): self._end_4gb = False self._ignore_missing = False self._filename = None + self.align_default = 0 def IsSpecialSubnode(self, node): """Check if a node is a special one used by the section itself @@ -178,7 +179,8 @@ class Entry_section(Entry): Returns: bool: True if the node is a special one, else False """ - return node.name.startswith('hash') or node.name.startswith('signature') + start_list = ('hash', 'signature', 'template') + return any(node.name.startswith(name) for name in start_list) def ReadNode(self): """Read properties from the section node""" @@ -315,12 +317,15 @@ class Entry_section(Entry): This should be overridden by subclasses which want to build their own data structure for the section. + Missing entries will have be given empty (or fake) data, so are + processed normally here. + Args: required: True if the data must be present, False if it is OK to return None Returns: - Contents of the section (bytes) + Contents of the section (bytes), None if not available """ section_data = bytearray() @@ -710,6 +715,33 @@ class Entry_section(Entry): def GetEntryContents(self, skip_entry=None): """Call ObtainContents() for each entry in the section + The overall goal of this function is to read in any available data in + this entry and any subentries. This includes reading in blobs, setting + up objects which have predefined contents, etc. + + Since entry types which contain entries call ObtainContents() on all + those entries too, the result is that ObtainContents() is called + recursively for the whole tree below this one. + + Entries with subentries are generally not *themselves& processed here, + i.e. their ObtainContents() implementation simply obtains contents of + their subentries, skipping their own contents. For example, the + implementation here (for entry_Section) does not attempt to pack the + entries into a final result. That is handled later. + + Generally, calling this results in SetContents() being called for each + entry, so that the 'data' and 'contents_size; properties are set, and + subsequent calls to GetData() will return value data. + + Where 'allow_missing' is set, this can result in the 'missing' property + being set to True if there is no data. This is handled by setting the + data to b''. This function will still return success. Future calls to + GetData() for this entry will return b'', or in the case where the data + is faked, GetData() will return that fake data. + + Args: + skip_entry: (single) Entry to skip, or None to process all entries + Note that this may set entry.absent to True if the entry is not actually needed """ @@ -719,7 +751,7 @@ class Entry_section(Entry): next_todo.append(entry) return entry - todo = self._entries.values() + todo = self.GetEntries().values() for passnum in range(3): threads = state.GetThreads() next_todo = [] @@ -892,7 +924,7 @@ class Entry_section(Entry): allow_missing: True if allowed, False if not allowed """ self.allow_missing = allow_missing - for entry in self._entries.values(): + for entry in self.GetEntries().values(): entry.SetAllowMissing(allow_missing) def SetAllowFakeBlob(self, allow_fake): @@ -902,7 +934,7 @@ class Entry_section(Entry): allow_fake: True if allowed, False if not allowed """ super().SetAllowFakeBlob(allow_fake) - for entry in self._entries.values(): + for entry in self.GetEntries().values(): entry.SetAllowFakeBlob(allow_fake) def CheckMissing(self, missing_list): @@ -914,7 +946,7 @@ class Entry_section(Entry): Args: missing_list: List of Entry objects to be added to """ - for entry in self._entries.values(): + for entry in self.GetEntries().values(): entry.CheckMissing(missing_list) def CheckFakedBlobs(self, faked_blobs_list): @@ -925,7 +957,7 @@ class Entry_section(Entry): Args: faked_blobs_list: List of Entry objects to be added to """ - for entry in self._entries.values(): + for entry in self.GetEntries().values(): entry.CheckFakedBlobs(faked_blobs_list) def CheckOptional(self, optional_list): @@ -936,7 +968,7 @@ class Entry_section(Entry): Args: optional_list (list): List of Entry objects to be added to """ - for entry in self._entries.values(): + for entry in self.GetEntries().values(): entry.CheckOptional(optional_list) def check_missing_bintools(self, missing_list): @@ -948,7 +980,7 @@ class Entry_section(Entry): missing_list: List of Bintool objects to be added to """ super().check_missing_bintools(missing_list) - for entry in self._entries.values(): + for entry in self.GetEntries().values(): entry.check_missing_bintools(missing_list) def _CollectEntries(self, entries, entries_by_name, add_entry): @@ -998,12 +1030,12 @@ class Entry_section(Entry): entry.Raise(f'Missing required properties/entry args: {missing}') def CheckAltFormats(self, alt_formats): - for entry in self._entries.values(): + for entry in self.GetEntries().values(): entry.CheckAltFormats(alt_formats) def AddBintools(self, btools): super().AddBintools(btools) - for entry in self._entries.values(): + for entry in self.GetEntries().values(): entry.AddBintools(btools) def read_elf_segments(self): diff --git a/tools/binman/etype/u_boot_spl_bss_pad.py b/tools/binman/etype/u_boot_spl_bss_pad.py index 1ffeb39..4af4045 100644 --- a/tools/binman/etype/u_boot_spl_bss_pad.py +++ b/tools/binman/etype/u_boot_spl_bss_pad.py @@ -38,7 +38,7 @@ class Entry_u_boot_spl_bss_pad(Entry_blob): def ObtainContents(self): fname = tools.get_input_filename('spl/u-boot-spl') bss_size = elf.GetSymbolAddress(fname, '__bss_size') - if not bss_size: + if bss_size is None: self.Raise('Expected __bss_size symbol in spl/u-boot-spl') self.SetContents(tools.get_bytes(0, bss_size)) return True diff --git a/tools/binman/etype/u_boot_tpl_bss_pad.py b/tools/binman/etype/u_boot_tpl_bss_pad.py index 29c6a95..46d2cd5 100644 --- a/tools/binman/etype/u_boot_tpl_bss_pad.py +++ b/tools/binman/etype/u_boot_tpl_bss_pad.py @@ -38,7 +38,7 @@ class Entry_u_boot_tpl_bss_pad(Entry_blob): def ObtainContents(self): fname = tools.get_input_filename('tpl/u-boot-tpl') bss_size = elf.GetSymbolAddress(fname, '__bss_size') - if not bss_size: + if bss_size is None: self.Raise('Expected __bss_size symbol in tpl/u-boot-tpl') self.SetContents(tools.get_bytes(0, bss_size)) return True diff --git a/tools/binman/etype/u_boot_vpl_bss_pad.py b/tools/binman/etype/u_boot_vpl_bss_pad.py index bba38cc..12b286a 100644 --- a/tools/binman/etype/u_boot_vpl_bss_pad.py +++ b/tools/binman/etype/u_boot_vpl_bss_pad.py @@ -38,7 +38,7 @@ class Entry_u_boot_vpl_bss_pad(Entry_blob): def ObtainContents(self): fname = tools.get_input_filename('vpl/u-boot-vpl') bss_size = elf.GetSymbolAddress(fname, '__bss_size') - if not bss_size: + if bss_size is None: self.Raise('Expected __bss_size symbol in vpl/u-boot-vpl') self.SetContents(tools.get_bytes(0, bss_size)) return True diff --git a/tools/binman/ftest.py b/tools/binman/ftest.py index 43b4f85..e53181a 100644 --- a/tools/binman/ftest.py +++ b/tools/binman/ftest.py @@ -1103,6 +1103,7 @@ class TestFunctional(unittest.TestCase): def testPackZeroOffset(self): """Test that an entry at offset 0 is not given a new offset""" + self._SetupSplElf() with self.assertRaises(ValueError) as e: self._DoTestFile('025_pack_zero_size.dts') self.assertIn("Node '/binman/u-boot-spl': Offset 0x0 (0) overlaps " @@ -1116,6 +1117,7 @@ class TestFunctional(unittest.TestCase): def testPackX86RomNoSize(self): """Test that the end-at-4gb property requires a size property""" + self._SetupSplElf() with self.assertRaises(ValueError) as e: self._DoTestFile('027_pack_4gb_no_size.dts') self.assertIn("Image '/binman': Section size must be provided when " @@ -1124,6 +1126,7 @@ class TestFunctional(unittest.TestCase): def test4gbAndSkipAtStartTogether(self): """Test that the end-at-4gb and skip-at-size property can't be used together""" + self._SetupSplElf() with self.assertRaises(ValueError) as e: self._DoTestFile('098_4gb_and_skip_at_start_together.dts') self.assertIn("Image '/binman': Provide either 'end-at-4gb' or " @@ -1131,6 +1134,7 @@ class TestFunctional(unittest.TestCase): def testPackX86RomOutside(self): """Test that the end-at-4gb property checks for offset boundaries""" + self._SetupSplElf() with self.assertRaises(ValueError) as e: self._DoTestFile('028_pack_4gb_outside.dts') self.assertIn("Node '/binman/u-boot': Offset 0x0 (0) size 0x4 (4) " @@ -1423,6 +1427,7 @@ class TestFunctional(unittest.TestCase): def testPackUbootSplMicrocode(self): """Test that x86 microcode can be handled correctly in SPL""" + self._SetupSplElf() self._PackUbootSplMicrocode('049_x86_ucode_spl.dts') def testPackUbootSplMicrocodeReorder(self): @@ -1442,6 +1447,7 @@ class TestFunctional(unittest.TestCase): def testSplDtb(self): """Test that an image with spl/u-boot-spl.dtb can be created""" + self._SetupSplElf() data = self._DoReadFile('051_u_boot_spl_dtb.dts') self.assertEqual(U_BOOT_SPL_DTB_DATA, data[:len(U_BOOT_SPL_DTB_DATA)]) @@ -1452,7 +1458,7 @@ class TestFunctional(unittest.TestCase): self.assertEqual(U_BOOT_SPL_NODTB_DATA, data[:len(U_BOOT_SPL_NODTB_DATA)]) def checkSymbols(self, dts, base_data, u_boot_offset, entry_args=None, - use_expanded=False): + use_expanded=False, no_write_symbols=False): """Check the image contains the expected symbol values Args: @@ -1481,9 +1487,14 @@ class TestFunctional(unittest.TestCase): sym_values = struct.pack('<LLQLL', elf.BINMAN_SYM_MAGIC_VALUE, 0x00, u_boot_offset + len(U_BOOT_DATA), 0x10 + u_boot_offset, 0x04) - expected = (sym_values + base_data[24:] + - tools.get_bytes(0xff, 1) + U_BOOT_DATA + sym_values + - base_data[24:]) + if no_write_symbols: + expected = (base_data + + tools.get_bytes(0xff, 0x38 - len(base_data)) + + U_BOOT_DATA + base_data) + else: + expected = (sym_values + base_data[24:] + + tools.get_bytes(0xff, 1) + U_BOOT_DATA + sym_values + + base_data[24:]) self.assertEqual(expected, data) def testSymbols(self): @@ -1957,6 +1968,8 @@ class TestFunctional(unittest.TestCase): def testUpdateFdtAll(self): """Test that all device trees are updated with offset/size info""" + self._SetupSplElf() + self._SetupTplElf() data = self._DoReadFileRealDtb('082_fdt_update_all.dts') base_expected = { @@ -3279,6 +3292,8 @@ class TestFunctional(unittest.TestCase): def testUpdateFdtAllRepack(self): """Test that all device trees are updated with offset/size info""" + self._SetupSplElf() + self._SetupTplElf() data = self._DoReadFileRealDtb('134_fdt_update_all_repack.dts') SECTION_SIZE = 0x300 DTB_SIZE = 602 @@ -3732,6 +3747,7 @@ class TestFunctional(unittest.TestCase): def testMkimage(self): """Test using mkimage to build an image""" + self._SetupSplElf() data = self._DoReadFile('156_mkimage.dts') # Just check that the data appears in the file somewhere @@ -3739,6 +3755,7 @@ class TestFunctional(unittest.TestCase): def testMkimageMissing(self): """Test that binman still produces an image if mkimage is missing""" + self._SetupSplElf() with test_util.capture_sys_output() as (_, stderr): self._DoTestFile('156_mkimage.dts', force_missing_bintools='mkimage') @@ -3851,6 +3868,7 @@ class TestFunctional(unittest.TestCase): def testSimpleFit(self): """Test an image with a FIT inside""" + self._SetupSplElf() data = self._DoReadFile('161_fit.dts') self.assertEqual(U_BOOT_DATA, data[:len(U_BOOT_DATA)]) self.assertEqual(U_BOOT_NODTB_DATA, data[-len(U_BOOT_NODTB_DATA):]) @@ -5370,6 +5388,7 @@ fdt fdtmap Extract the devicetree blob from the fdtmap def testFitSubentryHashSubnode(self): """Test an image with a FIT inside""" + self._SetupSplElf() data, _, _, out_dtb_name = self._DoReadFileDtb( '221_fit_subentry_hash.dts', use_real_dtb=True, update_dtb=True) @@ -5888,6 +5907,7 @@ fdt fdtmap Extract the devicetree blob from the fdtmap def testMkimageImagename(self): """Test using mkimage with -n holding the data too""" + self._SetupSplElf() data = self._DoReadFile('242_mkimage_name.dts') # Check that the data appears in the file somewhere @@ -5905,6 +5925,7 @@ fdt fdtmap Extract the devicetree blob from the fdtmap def testMkimageImage(self): """Test using mkimage with -n holding the data too""" + self._SetupSplElf() data = self._DoReadFile('243_mkimage_image.dts') # Check that the data appears in the file somewhere @@ -5925,6 +5946,7 @@ fdt fdtmap Extract the devicetree blob from the fdtmap def testMkimageImageNoContent(self): """Test using mkimage with -n and no data""" + self._SetupSplElf() with self.assertRaises(ValueError) as exc: self._DoReadFile('244_mkimage_image_no_content.dts') self.assertIn('Could not complete processing of contents', @@ -5932,6 +5954,7 @@ fdt fdtmap Extract the devicetree blob from the fdtmap def testMkimageImageBad(self): """Test using mkimage with imagename node and data-to-imagename""" + self._SetupSplElf() with self.assertRaises(ValueError) as exc: self._DoReadFile('245_mkimage_image_bad.dts') self.assertIn('Cannot use both imagename node and data-to-imagename', @@ -5947,6 +5970,7 @@ fdt fdtmap Extract the devicetree blob from the fdtmap def testMkimageCollection(self): """Test using a collection referring to an entry in a mkimage entry""" + self._SetupSplElf() data = self._DoReadFile('247_mkimage_coll.dts') expect = U_BOOT_SPL_DATA + U_BOOT_DATA self.assertEqual(expect, data[:len(expect)]) @@ -6032,6 +6056,8 @@ fdt fdtmap Extract the devicetree blob from the fdtmap def testMkimageMultipleDataFiles(self): """Test passing multiple files to mkimage in a mkimage entry""" + self._SetupSplElf() + self._SetupTplElf() data = self._DoReadFile('252_mkimage_mult_data.dts') # Size of files are packed in their 4B big-endian format expect = struct.pack('>I', len(U_BOOT_TPL_DATA)) @@ -6046,8 +6072,42 @@ fdt fdtmap Extract the devicetree blob from the fdtmap expect += U_BOOT_SPL_DATA self.assertEqual(expect, data[-len(expect):]) + def testMkimageMultipleExpanded(self): + """Test passing multiple files to mkimage in a mkimage entry""" + self._SetupSplElf() + self._SetupTplElf() + entry_args = { + 'spl-bss-pad': 'y', + 'spl-dtb': 'y', + } + data = self._DoReadFileDtb('252_mkimage_mult_data.dts', + use_expanded=True, entry_args=entry_args)[0] + pad_len = 10 + tpl_expect = U_BOOT_TPL_DATA + spl_expect = U_BOOT_SPL_NODTB_DATA + tools.get_bytes(0, pad_len) + spl_expect += U_BOOT_SPL_DTB_DATA + + content = data[0x40:] + lens = struct.unpack('>III', content[:12]) + + # Size of files are packed in their 4B big-endian format + # Size info is always followed by a 4B zero value. + self.assertEqual(len(tpl_expect), lens[0]) + self.assertEqual(len(spl_expect), lens[1]) + self.assertEqual(0, lens[2]) + + rest = content[12:] + self.assertEqual(tpl_expect, rest[:len(tpl_expect)]) + + rest = rest[len(tpl_expect):] + align_pad = len(tpl_expect) % 4 + self.assertEqual(tools.get_bytes(0, align_pad), rest[:align_pad]) + rest = rest[align_pad:] + self.assertEqual(spl_expect, rest) + def testMkimageMultipleNoContent(self): """Test passing multiple data files to mkimage with one data file having no content""" + self._SetupSplElf() with self.assertRaises(ValueError) as exc: self._DoReadFile('253_mkimage_mult_no_content.dts') self.assertIn('Could not complete processing of contents', @@ -6055,6 +6115,7 @@ fdt fdtmap Extract the devicetree blob from the fdtmap def testMkimageFilename(self): """Test using mkimage to build a binary with a filename""" + self._SetupSplElf() retcode = self._DoTestFile('254_mkimage_filename.dts') self.assertEqual(0, retcode) fname = tools.get_output_filename('mkimage-test.bin') @@ -6529,6 +6590,7 @@ fdt fdtmap Extract the devicetree blob from the fdtmap def testReplaceFitSibling(self): """Test an image with a FIT inside where we replace its sibling""" + self._SetupSplElf() fname = TestFunctional._MakeInputFile('once', b'available once') self._DoReadFileRealDtb('277_replace_fit_sibling.dts') os.remove(fname) @@ -6603,7 +6665,7 @@ fdt fdtmap Extract the devicetree blob from the fdtmap Private key DTB """ - + self._SetupSplElf() data = self._DoReadFileRealDtb(dts) updated_fname = tools.get_output_filename('image-updated.bin') tools.write_file(updated_fname, data) @@ -6676,6 +6738,152 @@ fdt fdtmap Extract the devicetree blob from the fdtmap ['fit']) self.assertIn("Node '/fit': Missing tool: 'mkimage'", str(e.exception)) + def testSymbolNoWrite(self): + """Test disabling of symbol writing""" + self._SetupSplElf() + self.checkSymbols('282_symbols_disable.dts', U_BOOT_SPL_DATA, 0x1c, + no_write_symbols=True) + + def testSymbolNoWriteExpanded(self): + """Test disabling of symbol writing in expanded entries""" + entry_args = { + 'spl-dtb': '1', + } + self.checkSymbols('282_symbols_disable.dts', U_BOOT_SPL_NODTB_DATA + + U_BOOT_SPL_DTB_DATA, 0x38, + entry_args=entry_args, use_expanded=True, + no_write_symbols=True) + + def testMkimageSpecial(self): + """Test mkimage ignores special hash-1 node""" + data = self._DoReadFile('283_mkimage_special.dts') + + # Just check that the data appears in the file somewhere + self.assertIn(U_BOOT_DATA, data) + + def testFitFdtList(self): + """Test an image with an FIT with the fit,fdt-list-val option""" + entry_args = { + 'default-dt': 'test-fdt2', + } + data = self._DoReadFileDtb( + '284_fit_fdt_list.dts', + entry_args=entry_args, + extra_indirs=[os.path.join(self._indir, TEST_FDT_SUBDIR)])[0] + self.assertEqual(U_BOOT_NODTB_DATA, data[-len(U_BOOT_NODTB_DATA):]) + fit_data = data[len(U_BOOT_DATA):-len(U_BOOT_NODTB_DATA)] + + def testSplEmptyBss(self): + """Test an expanded SPL with a zero-size BSS""" + # ELF file with a '__bss_size' symbol + self._SetupSplElf(src_fname='bss_data_zero') + + entry_args = { + 'spl-bss-pad': 'y', + 'spl-dtb': 'y', + } + data = self._DoReadFileDtb('285_spl_expand.dts', + use_expanded=True, entry_args=entry_args)[0] + + def testTemplate(self): + """Test using a template""" + TestFunctional._MakeInputFile('vga2.bin', b'#' + VGA_DATA) + data = self._DoReadFile('286_template.dts') + first = U_BOOT_DATA + VGA_DATA + U_BOOT_DTB_DATA + second = U_BOOT_DATA + b'#' + VGA_DATA + U_BOOT_DTB_DATA + self.assertEqual(U_BOOT_IMG_DATA + first + second, data) + + def testTemplateBlobMulti(self): + """Test using a template with 'multiple-images' enabled""" + TestFunctional._MakeInputFile('my-blob.bin', b'blob') + TestFunctional._MakeInputFile('my-blob2.bin', b'other') + retcode = self._DoTestFile('287_template_multi.dts') + + self.assertEqual(0, retcode) + image = control.images['image'] + image_fname = tools.get_output_filename('my-image.bin') + data = tools.read_file(image_fname) + self.assertEqual(b'blob@@@@other', data) + + def testTemplateFit(self): + """Test using a template in a FIT""" + fit_data = self._DoReadFile('288_template_fit.dts') + fname = os.path.join(self._indir, 'fit_data.fit') + tools.write_file(fname, fit_data) + out = tools.run('dumpimage', '-l', fname) + + def testTemplateSection(self): + """Test using a template in a section (not at top level)""" + TestFunctional._MakeInputFile('vga2.bin', b'#' + VGA_DATA) + data = self._DoReadFile('289_template_section.dts') + first = U_BOOT_DATA + VGA_DATA + U_BOOT_DTB_DATA + second = U_BOOT_DATA + b'#' + VGA_DATA + U_BOOT_DTB_DATA + self.assertEqual(U_BOOT_IMG_DATA + first + second + first, data) + + def testMkimageSymbols(self): + """Test using mkimage to build an image with symbols in it""" + self._SetupSplElf('u_boot_binman_syms') + data = self._DoReadFile('290_mkimage_sym.dts') + + image = control.images['image'] + entries = image.GetEntries() + self.assertIn('u-boot', entries) + u_boot = entries['u-boot'] + + mkim = entries['mkimage'] + mkim_entries = mkim.GetEntries() + self.assertIn('u-boot-spl', mkim_entries) + spl = mkim_entries['u-boot-spl'] + self.assertIn('u-boot-spl2', mkim_entries) + spl2 = mkim_entries['u-boot-spl2'] + + # skip the mkimage header and the area sizes + mk_data = data[mkim.offset + 0x40:] + size, term = struct.unpack('>LL', mk_data[:8]) + + # There should be only one image, so check that the zero terminator is + # present + self.assertEqual(0, term) + + content = mk_data[8:8 + size] + + # The image should contain the symbols from u_boot_binman_syms.c + # Note that image_pos is adjusted by the base address of the image, + # which is 0x10 in our test image + spl_data = content[:0x18] + content = content[0x1b:] + + # After the header is a table of offsets for each image. There should + # only be one image, then a 0 terminator, so figure out the real start + # of the image data + base = 0x40 + 8 + + # Check symbols in both u-boot-spl and u-boot-spl2 + for i in range(2): + vals = struct.unpack('<LLQLL', spl_data) + + # The image should contain the symbols from u_boot_binman_syms.c + # Note that image_pos is adjusted by the base address of the image, + # which is 0x10 in our 'u_boot_binman_syms' test image + self.assertEqual(elf.BINMAN_SYM_MAGIC_VALUE, vals[0]) + self.assertEqual(base, vals[1]) + self.assertEqual(spl2.offset, vals[2]) + # figure out the internal positions of its components + self.assertEqual(0x10 + u_boot.image_pos, vals[3]) + + # Check that spl and spl2 are actually at the indicated positions + self.assertEqual( + elf.BINMAN_SYM_MAGIC_VALUE, + struct.unpack('<I', data[spl.image_pos:spl.image_pos + 4])[0]) + self.assertEqual( + elf.BINMAN_SYM_MAGIC_VALUE, + struct.unpack('<I', data[spl2.image_pos:spl2.image_pos + 4])[0]) + + self.assertEqual(len(U_BOOT_DATA), vals[4]) + + # Move to next + spl_data = content[:0x18] + if __name__ == "__main__": unittest.main() diff --git a/tools/binman/state.py b/tools/binman/state.py index 3e78cf3..45bae40 100644 --- a/tools/binman/state.py +++ b/tools/binman/state.py @@ -385,8 +385,8 @@ def SetInt(node, prop, value, for_repack=False): for_repack: True is this property is only needed for repacking """ for n in GetUpdateNodes(node, for_repack): - tout.detail("File %s: Update node '%s' prop '%s' to %#x" % - (n.GetFdt().name, n.path, prop, value)) + tout.debug("File %s: Update node '%s' prop '%s' to %#x" % + (n.GetFdt().name, n.path, prop, value)) n.SetInt(prop, value) def CheckAddHashProp(node): diff --git a/tools/binman/test/282_symbols_disable.dts b/tools/binman/test/282_symbols_disable.dts new file mode 100644 index 0000000..6efa933 --- /dev/null +++ b/tools/binman/test/282_symbols_disable.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/dts-v1/; + +/ { + #address-cells = <1>; + #size-cells = <1>; + + binman { + pad-byte = <0xff>; + u-boot-spl { + no-write-symbols; + }; + + u-boot { + offset = <0x38>; + no-expanded; + }; + + u-boot-spl2 { + type = "u-boot-spl"; + no-write-symbols; + }; + }; +}; diff --git a/tools/binman/test/283_mkimage_special.dts b/tools/binman/test/283_mkimage_special.dts new file mode 100644 index 0000000..c234093 --- /dev/null +++ b/tools/binman/test/283_mkimage_special.dts @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/dts-v1/; + +/ { + #address-cells = <1>; + #size-cells = <1>; + + binman { + mkimage { + args = "-T script"; + + u-boot { + }; + + hash { + }; + + imagename { + type = "u-boot"; + }; + }; + }; +}; diff --git a/tools/binman/test/284_fit_fdt_list.dts b/tools/binman/test/284_fit_fdt_list.dts new file mode 100644 index 0000000..8885313 --- /dev/null +++ b/tools/binman/test/284_fit_fdt_list.dts @@ -0,0 +1,58 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/dts-v1/; + +/ { + #address-cells = <1>; + #size-cells = <1>; + + binman { + u-boot { + }; + fit { + description = "test-desc"; + #address-cells = <1>; + fit,fdt-list-val = "test-fdt1", "test-fdt2"; + + images { + kernel { + description = "Vanilla Linux kernel"; + type = "kernel"; + arch = "ppc"; + os = "linux"; + compression = "gzip"; + load = <00000000>; + entry = <00000000>; + hash-1 { + algo = "crc32"; + }; + hash-2 { + algo = "sha1"; + }; + u-boot { + }; + }; + @fdt-SEQ { + description = "fdt-NAME.dtb"; + type = "flat_dt"; + compression = "none"; + hash { + algo = "sha256"; + }; + }; + }; + + configurations { + default = "@config-DEFAULT-SEQ"; + @config-SEQ { + description = "conf-NAME.dtb"; + firmware = "uboot"; + loadables = "atf"; + fdt = "fdt-SEQ"; + }; + }; + }; + u-boot-nodtb { + }; + }; +}; diff --git a/tools/binman/test/285_spl_expand.dts b/tools/binman/test/285_spl_expand.dts new file mode 100644 index 0000000..9c88ccb --- /dev/null +++ b/tools/binman/test/285_spl_expand.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/dts-v1/; + +/ { + #address-cells = <1>; + #size-cells = <1>; + + binman { + u-boot-spl { + }; + }; +}; diff --git a/tools/binman/test/286_template.dts b/tools/binman/test/286_template.dts new file mode 100644 index 0000000..6980dbf --- /dev/null +++ b/tools/binman/test/286_template.dts @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/dts-v1/; + +/ { + #address-cells = <1>; + #size-cells = <1>; + + binman { + u-boot-img { + }; + + common_part: template { + u-boot { + }; + + intel-vga { + filename = "vga.bin"; + }; + }; + + first { + type = "section"; + insert-template = <&common_part>; + + u-boot-dtb { + }; + }; + + second { + type = "section"; + insert-template = <&common_part>; + + u-boot-dtb { + }; + + intel-vga { + filename = "vga2.bin"; + }; + }; + }; +}; diff --git a/tools/binman/test/287_template_multi.dts b/tools/binman/test/287_template_multi.dts new file mode 100644 index 0000000..122bfcc --- /dev/null +++ b/tools/binman/test/287_template_multi.dts @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/dts-v1/; +/ { + binman: binman { + multiple-images; + + my_template: template { + blob-ext@0 { + filename = "my-blob.bin"; + offset = <0>; + }; + blob-ext@8 { + offset = <8>; + }; + }; + + image { + pad-byte = <0x40>; + filename = "my-image.bin"; + insert-template = <&my_template>; + blob-ext@8 { + filename = "my-blob2.bin"; + }; + }; + }; +}; diff --git a/tools/binman/test/288_template_fit.dts b/tools/binman/test/288_template_fit.dts new file mode 100644 index 0000000..d84dca4 --- /dev/null +++ b/tools/binman/test/288_template_fit.dts @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/dts-v1/; + +/ { + binman: binman { + multiple-images; + + my_template: template { + fit@0 { + images { + kernel-1 { + }; + kernel-2 { + }; + }; + }; + }; + + image { + filename = "image.bin"; + insert-template = <&my_template>; + + fit@0 { + description = "desc"; + configurations { + }; + images { + kernel-3 { + }; + kernel-4 { + }; + }; + }; + }; + }; +}; diff --git a/tools/binman/test/289_template_section.dts b/tools/binman/test/289_template_section.dts new file mode 100644 index 0000000..8a744a0 --- /dev/null +++ b/tools/binman/test/289_template_section.dts @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/dts-v1/; + +/ { + #address-cells = <1>; + #size-cells = <1>; + + binman { + u-boot-img { + }; + + common_part: template { + u-boot { + }; + + intel-vga { + filename = "vga.bin"; + }; + }; + + first { + type = "section"; + insert-template = <&common_part>; + + u-boot-dtb { + }; + }; + + section { + second { + type = "section"; + insert-template = <&common_part>; + + u-boot-dtb { + }; + + intel-vga { + filename = "vga2.bin"; + }; + }; + }; + + second { + type = "section"; + insert-template = <&common_part>; + + u-boot-dtb { + }; + }; + }; +}; diff --git a/tools/binman/test/290_mkimage_sym.dts b/tools/binman/test/290_mkimage_sym.dts new file mode 100644 index 0000000..2dfd286 --- /dev/null +++ b/tools/binman/test/290_mkimage_sym.dts @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/dts-v1/; + +/ { + #address-cells = <1>; + #size-cells = <1>; + + binman { + u-boot-dtb { + }; + + mkimage { + args = "-n test -T script"; + + u-boot-spl { + }; + + u-boot-spl2 { + type = "u-boot-spl"; + }; + }; + + u-boot { + }; + }; +}; diff --git a/tools/binman/test/Makefile b/tools/binman/test/Makefile index cd66a30..4d152ee 100644 --- a/tools/binman/test/Makefile +++ b/tools/binman/test/Makefile @@ -32,7 +32,7 @@ LDS_BINMAN_EMBED := -T $(SRC)u_boot_binman_embed.lds LDS_EFL_SECTIONS := -T $(SRC)elf_sections.lds LDS_BLOB := -T $(SRC)blob_syms.lds -TARGETS = u_boot_ucode_ptr u_boot_no_ucode_ptr bss_data \ +TARGETS = u_boot_ucode_ptr u_boot_no_ucode_ptr bss_data bss_data_zero \ u_boot_binman_syms u_boot_binman_syms.bin u_boot_binman_syms_bad \ u_boot_binman_syms_size u_boot_binman_syms_x86 embed_data \ u_boot_binman_embed u_boot_binman_embed_sm elf_sections blob_syms.bin @@ -48,6 +48,9 @@ u_boot_ucode_ptr: u_boot_ucode_ptr.c bss_data: CFLAGS += $(SRC)bss_data.lds bss_data: bss_data.c +bss_data_zero: CFLAGS += $(SRC)bss_data_zero.lds +bss_data_zero: bss_data_zero.c + embed_data: CFLAGS += $(SRC)embed_data.lds embed_data: embed_data.c diff --git a/tools/binman/test/bss_data.c b/tools/binman/test/bss_data.c index 4f9b64c..7047a3b 100644 --- a/tools/binman/test/bss_data.c +++ b/tools/binman/test/bss_data.c @@ -7,9 +7,8 @@ */ int bss_data[10]; -int __bss_size = sizeof(bss_data); -int main() +int main(void) { bss_data[2] = 2; diff --git a/tools/binman/test/bss_data_zero.c b/tools/binman/test/bss_data_zero.c new file mode 100644 index 0000000..7047a3b --- /dev/null +++ b/tools/binman/test/bss_data_zero.c @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2016 Google, Inc + * + * Simple program to create a bss_data region so the symbol can be read + * by binutils. This is used by binman tests. + */ + +int bss_data[10]; + +int main(void) +{ + bss_data[2] = 2; + + return 0; +} diff --git a/tools/binman/test/bss_data_zero.lds b/tools/binman/test/bss_data_zero.lds new file mode 100644 index 0000000..8fa0210 --- /dev/null +++ b/tools/binman/test/bss_data_zero.lds @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2016 Google, Inc + */ + +OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386") +OUTPUT_ARCH(i386) +ENTRY(_start) + +SECTIONS +{ + . = 0xfffffdf0; + _start = .; + __bss_size = 0; +} diff --git a/tools/binman/test/embed_data.lds b/tools/binman/test/embed_data.lds index 908bf66..d416cb2 100644 --- a/tools/binman/test/embed_data.lds +++ b/tools/binman/test/embed_data.lds @@ -17,6 +17,7 @@ SECTIONS embed_start = .; *(.embed*) embed_end = .; + region_size = 0; . = ALIGN(32); *(.data*) } diff --git a/tools/buildman/bsettings.py b/tools/buildman/bsettings.py index 0eb894a..029c401 100644 --- a/tools/buildman/bsettings.py +++ b/tools/buildman/bsettings.py @@ -91,7 +91,6 @@ other = / [toolchain-prefix] # name = path to prefix # e.g. x86 = /opt/gcc-4.6.3-nolibc/x86_64-linux/bin/x86_64-linux- -# arc = /opt/arc/arc_gnu_2021.03_prebuilt_elf32_le_linux_install/bin/arc-elf32- [toolchain-alias] # arch = alias diff --git a/tools/buildman/buildman.rst b/tools/buildman/buildman.rst index c8b0db3..6808727 100644 --- a/tools/buildman/buildman.rst +++ b/tools/buildman/buildman.rst @@ -475,10 +475,6 @@ Setting up sudo mkdir -p /toolchains sudo mv ~/.buildman-toolchains/*/* /toolchains/ - For those not available from kernel.org, download from the following links: - - - `Arc Toolchain`_ - Buildman should now be set up to use your new toolchain. At the time of writing, U-Boot has these architectures: @@ -1342,8 +1338,6 @@ Thanks to Grant Grundler <grundler@chromium.org> for his ideas for improving the build speed by building all commits for a board instead of the other way around. -.. _`Arc Toolchain`: https://github.com/foss-for-synopsys-dwc-arc-processors/toolchain/releases/download/arc-2021.03-release/arc_gnu_2021.03_prebuilt_elf32_le_linux_install.tar.gz - .. sectionauthor:: Simon Glass .. sectionauthor:: Copyright (c) 2013 The Chromium OS Authors. .. sectionauthor:: sjg@chromium.org diff --git a/tools/buildman/toolchain.py b/tools/buildman/toolchain.py index 0ecd845..1001b61 100644 --- a/tools/buildman/toolchain.py +++ b/tools/buildman/toolchain.py @@ -499,7 +499,7 @@ class Toolchains: if arch == 'aarch64': arch = 'arm64' base = 'https://www.kernel.org/pub/tools/crosstool/files/bin' - versions = ['12.2.0', '11.1.0'] + versions = ['13.1.0', '12.2.0'] links = [] for version in versions: url = '%s/%s/%s/' % (base, arch, version) diff --git a/tools/docker/Dockerfile b/tools/docker/Dockerfile index 9804b55..3d2b64a 100644 --- a/tools/docker/Dockerfile +++ b/tools/docker/Dockerfile @@ -2,7 +2,7 @@ # This Dockerfile is used to build an image containing basic stuff to be used # to build U-Boot and run our test suites. -FROM ubuntu:jammy-20230308 +FROM ubuntu:jammy-20230624 MAINTAINER Tom Rini <trini@konsulko.com> LABEL Description=" This image is for building U-Boot inside a container" @@ -14,22 +14,22 @@ RUN apt-get update && apt-get install -y gnupg2 wget xz-utils && rm -rf /var/lib RUN wget -O - https://apt.llvm.org/llvm-snapshot.gpg.key | apt-key add - RUN echo deb http://apt.llvm.org/jammy/ llvm-toolchain-jammy-16 main | tee /etc/apt/sources.list.d/llvm.list -# Manually install the kernel.org "Crosstool" based toolchains for gcc-12.2.0 -RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/12.2.0/x86_64-gcc-12.2.0-nolibc-aarch64-linux.tar.xz | tar -C /opt -xJ -RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/12.2.0/x86_64-gcc-12.2.0-nolibc-arm-linux-gnueabi.tar.xz | tar -C /opt -xJ -RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/12.2.0/x86_64-gcc-12.2.0-nolibc-i386-linux.tar.xz | tar -C /opt -xJ -RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/12.2.0/x86_64-gcc-12.2.0-nolibc-m68k-linux.tar.xz | tar -C /opt -xJ -RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/12.2.0/x86_64-gcc-12.2.0-nolibc-mips-linux.tar.xz | tar -C /opt -xJ -RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/12.2.0/x86_64-gcc-12.2.0-nolibc-microblaze-linux.tar.xz | tar -C /opt -xJ -RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/12.2.0/x86_64-gcc-12.2.0-nolibc-nios2-linux.tar.xz | tar -C /opt -xJ -RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/12.2.0/x86_64-gcc-12.2.0-nolibc-powerpc-linux.tar.xz | tar -C /opt -xJ -RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/12.2.0/x86_64-gcc-12.2.0-nolibc-riscv64-linux.tar.xz | tar -C /opt -xJ -RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/12.2.0/x86_64-gcc-12.2.0-nolibc-riscv32-linux.tar.xz | tar -C /opt -xJ -RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/12.2.0/x86_64-gcc-12.2.0-nolibc-sh2-linux.tar.xz | tar -C /opt -xJ +# Manually install the kernel.org "Crosstool" based toolchains for gcc-13.1.0 +RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/13.1.0/x86_64-gcc-13.1.0-nolibc-aarch64-linux.tar.xz | tar -C /opt -xJ +RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/13.1.0/x86_64-gcc-13.1.0-nolibc-arc-linux.tar.xz | tar -C /opt -xJ +RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/13.1.0/x86_64-gcc-13.1.0-nolibc-arm-linux-gnueabi.tar.xz | tar -C /opt -xJ +RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/13.1.0/x86_64-gcc-13.1.0-nolibc-i386-linux.tar.xz | tar -C /opt -xJ +RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/13.1.0/x86_64-gcc-13.1.0-nolibc-m68k-linux.tar.xz | tar -C /opt -xJ +RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/13.1.0/x86_64-gcc-13.1.0-nolibc-mips-linux.tar.xz | tar -C /opt -xJ +RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/13.1.0/x86_64-gcc-13.1.0-nolibc-microblaze-linux.tar.xz | tar -C /opt -xJ +RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/13.1.0/x86_64-gcc-13.1.0-nolibc-nios2-linux.tar.xz | tar -C /opt -xJ +RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/13.1.0/x86_64-gcc-13.1.0-nolibc-powerpc-linux.tar.xz | tar -C /opt -xJ +RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/13.1.0/x86_64-gcc-13.1.0-nolibc-riscv64-linux.tar.xz | tar -C /opt -xJ +RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/13.1.0/x86_64-gcc-13.1.0-nolibc-riscv32-linux.tar.xz | tar -C /opt -xJ +RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/13.1.0/x86_64-gcc-13.1.0-nolibc-sh2-linux.tar.xz | tar -C /opt -xJ # Manually install other toolchains RUN wget -O - https://github.com/foss-xtensa/toolchain/releases/download/2020.07/x86_64-2020.07-xtensa-dc233c-elf.tar.gz | tar -C /opt -xz -RUN wget -O - https://github.com/foss-for-synopsys-dwc-arc-processors/toolchain/releases/download/arc-2021.03-release/arc_gnu_2021.03_prebuilt_uclibc_le_archs_linux_install.tar.gz | tar --no-same-owner -C /opt -xz # Update and install things from apt now RUN apt-get update && apt-get install -y \ @@ -77,6 +77,7 @@ RUN apt-get update && apt-get install -y \ libsdl1.2-dev \ libsdl2-dev \ libseccomp-dev \ + libslirp-dev \ libssl-dev \ libtool \ libudev-dev \ @@ -128,15 +129,16 @@ RUN git clone git://git.savannah.gnu.org/grub.git /tmp/grub && \ git config --global user.name "GitLab CI Runner" && \ git config --global user.email trini@konsulko.com && \ git cherry-pick 049efdd72eb7baa7b2bf8884391ee7fe650da5a0 && \ + git cherry-pick 403d6540cd608b2706cfa0cb4713f7e4b490ff45 && \ ./bootstrap && \ mkdir -p /opt/grub && \ ./configure --target=aarch64 --with-platform=efi \ CC=gcc \ - TARGET_CC=/opt/gcc-12.2.0-nolibc/aarch64-linux/bin/aarch64-linux-gcc \ - TARGET_OBJCOPY=/opt/gcc-12.2.0-nolibc/aarch64-linux/bin/aarch64-linux-objcopy \ - TARGET_STRIP=/opt/gcc-12.2.0-nolibc/aarch64-linux/bin/aarch64-linux-strip \ - TARGET_NM=/opt/gcc-12.2.0-nolibc/aarch64-linux/bin/aarch64-linux-nm \ - TARGET_RANLIB=/opt/gcc-12.2.0-nolibc/aarch64-linux/bin/aarch64-linux-ranlib && \ + TARGET_CC=/opt/gcc-13.1.0-nolibc/aarch64-linux/bin/aarch64-linux-gcc \ + TARGET_OBJCOPY=/opt/gcc-13.1.0-nolibc/aarch64-linux/bin/aarch64-linux-objcopy \ + TARGET_STRIP=/opt/gcc-13.1.0-nolibc/aarch64-linux/bin/aarch64-linux-strip \ + TARGET_NM=/opt/gcc-13.1.0-nolibc/aarch64-linux/bin/aarch64-linux-nm \ + TARGET_RANLIB=/opt/gcc-13.1.0-nolibc/aarch64-linux/bin/aarch64-linux-ranlib && \ make && \ ./grub-mkimage -O arm64-efi -o /opt/grub/grubaa64.efi --prefix= -d \ grub-core cat chain configfile echo efinet ext2 fat halt help linux \ @@ -146,11 +148,11 @@ RUN git clone git://git.savannah.gnu.org/grub.git /tmp/grub && \ make clean && \ ./configure --target=arm --with-platform=efi \ CC=gcc \ - TARGET_CC=/opt/gcc-12.2.0-nolibc/arm-linux-gnueabi/bin/arm-linux-gnueabi-gcc \ - TARGET_OBJCOPY=/opt/gcc-12.2.0-nolibc/arm-linux-gnueabi/bin/arm-linux-gnueabi-objcopy \ - TARGET_STRIP=/opt/gcc-12.2.0-nolibc/arm-linux-gnueabi/bin/arm-linux-gnueabi-strip \ - TARGET_NM=/opt/gcc-12.2.0-nolibc/arm-linux-gnueabi/bin/arm-linux-gnueabi-nm \ - TARGET_RANLIB=/opt/gcc-12.2.0-nolibc/arm-linux-gnueabi/bin/arm-linux-gnueabi-ranlib && \ + TARGET_CC=/opt/gcc-13.1.0-nolibc/arm-linux-gnueabi/bin/arm-linux-gnueabi-gcc \ + TARGET_OBJCOPY=/opt/gcc-13.1.0-nolibc/arm-linux-gnueabi/bin/arm-linux-gnueabi-objcopy \ + TARGET_STRIP=/opt/gcc-13.1.0-nolibc/arm-linux-gnueabi/bin/arm-linux-gnueabi-strip \ + TARGET_NM=/opt/gcc-13.1.0-nolibc/arm-linux-gnueabi/bin/arm-linux-gnueabi-nm \ + TARGET_RANLIB=/opt/gcc-13.1.0-nolibc/arm-linux-gnueabi/bin/arm-linux-gnueabi-ranlib && \ make && \ ./grub-mkimage -O arm-efi -o /opt/grub/grubarm.efi --prefix= -d \ grub-core cat chain configfile echo efinet ext2 fat halt help linux \ @@ -160,11 +162,11 @@ RUN git clone git://git.savannah.gnu.org/grub.git /tmp/grub && \ make clean && \ ./configure --target=riscv64 --with-platform=efi \ CC=gcc \ - TARGET_CC=/opt/gcc-12.2.0-nolibc/riscv64-linux/bin/riscv64-linux-gcc \ - TARGET_OBJCOPY=/opt/gcc-12.2.0-nolibc/riscv64-linux/bin/riscv64-linux-objcopy \ - TARGET_STRIP=/opt/gcc-12.2.0-nolibc/riscv64-linux/bin/riscv64-linux-strip \ - TARGET_NM=/opt/gcc-12.2.0-nolibc/riscv64-linux/bin/riscv64-linux-nm \ - TARGET_RANLIB=/opt/gcc-12.2.0-nolibc/riscv64-linux/bin/riscv64-linux-ranlib && \ + TARGET_CC=/opt/gcc-13.1.0-nolibc/riscv64-linux/bin/riscv64-linux-gcc \ + TARGET_OBJCOPY=/opt/gcc-13.1.0-nolibc/riscv64-linux/bin/riscv64-linux-objcopy \ + TARGET_STRIP=/opt/gcc-13.1.0-nolibc/riscv64-linux/bin/riscv64-linux-strip \ + TARGET_NM=/opt/gcc-13.1.0-nolibc/riscv64-linux/bin/riscv64-linux-nm \ + TARGET_RANLIB=/opt/gcc-13.1.0-nolibc/riscv64-linux/bin/riscv64-linux-ranlib && \ make && \ ./grub-mkimage -O riscv64-efi -o /opt/grub/grubriscv64.efi --prefix= -d \ grub-core cat chain configfile echo efinet ext2 fat halt help linux \ @@ -175,13 +177,10 @@ RUN git clone git://git.savannah.gnu.org/grub.git /tmp/grub && \ RUN git clone https://gitlab.com/qemu-project/qemu.git /tmp/qemu && \ cd /tmp/qemu && \ - git submodule update --init dtc && \ - git checkout v6.1.0 && \ + git checkout v8.0.3 && \ # config user.name and user.email to make 'git am' happy git config user.name u-boot && \ git config user.email u-boot@denx.de && \ - # manually apply the bug fix for QEMU 6.1.0 Xilinx Zynq UART emulation codes - wget -O - http://patchwork.ozlabs.org/project/qemu-devel/patch/20210823020813.25192-2-bmeng.cn@gmail.com/mbox/ | git am && \ ./configure --prefix=/opt/qemu --target-list="aarch64-softmmu,arm-softmmu,i386-softmmu,m68k-softmmu,mips-softmmu,mips64-softmmu,mips64el-softmmu,mipsel-softmmu,ppc-softmmu,riscv32-softmmu,riscv64-softmmu,sh4-softmmu,x86_64-softmmu,xtensa-softmmu" && \ make -j$(nproc) all install && \ rm -rf /tmp/qemu @@ -278,8 +277,7 @@ RUN virtualenv -p /usr/bin/python3 /tmp/venv && \ # Create the buildman config file RUN /bin/echo -e "[toolchain]\nroot = /usr" > ~/.buildman -RUN /bin/echo -e "kernelorg = /opt/gcc-12.2.0-nolibc/*" >> ~/.buildman -RUN /bin/echo -e "arc = /opt/arc_gnu_2021.03_prebuilt_uclibc_le_archs_linux_install" >> ~/.buildman +RUN /bin/echo -e "kernelorg = /opt/gcc-13.1.0-nolibc/*" >> ~/.buildman RUN /bin/echo -e "\n[toolchain-prefix]\nxtensa = /opt/2020.07/xtensa-dc233c-elf/bin/xtensa-dc233c-elf-" >> ~/.buildman; RUN /bin/echo -e "\n[toolchain-alias]\nsh = sh2" >> ~/.buildman RUN /bin/echo -e "\nsandbox = x86_64" >> ~/.buildman diff --git a/tools/dtoc/fdt.py b/tools/dtoc/fdt.py index a8e0534..fd0f3e9 100644 --- a/tools/dtoc/fdt.py +++ b/tools/dtoc/fdt.py @@ -13,6 +13,7 @@ from dtoc import fdt_util import libfdt from libfdt import QUIET_NOTFOUND from u_boot_pylib import tools +from u_boot_pylib import tout # This deals with a device tree, presenting it as an assortment of Node and # Prop objects, representing nodes and properties, respectively. This file @@ -264,6 +265,13 @@ class Prop: fdt_obj.setprop(node.Offset(), self.name, self.bytes) self.dirty = False + def purge(self): + """Set a property offset to None + + The property remains in the tree structure and will be recreated when + the FDT is synced + """ + self._offset = None class Node: """A device tree node @@ -534,8 +542,8 @@ class Node: """ return self.AddData(prop_name, struct.pack('>I', val)) - def AddSubnode(self, name): - """Add a new subnode to the node + def Subnode(self, name): + """Create new subnode for the node Args: name: name of node to add @@ -544,10 +552,72 @@ class Node: New subnode that was created """ path = self.path + '/' + name - subnode = Node(self._fdt, self, None, name, path) + return Node(self._fdt, self, None, name, path) + + def AddSubnode(self, name): + """Add a new subnode to the node, after all other subnodes + + Args: + name: name of node to add + + Returns: + New subnode that was created + """ + subnode = self.Subnode(name) self.subnodes.append(subnode) return subnode + def insert_subnode(self, name): + """Add a new subnode to the node, before all other subnodes + + This deletes other subnodes and sets their offset to None, so that they + will be recreated after this one. + + Args: + name: name of node to add + + Returns: + New subnode that was created + """ + # Deleting a node invalidates the offsets of all following nodes, so + # process in reverse order so that the offset of each node remains valid + # until deletion. + for subnode in reversed(self.subnodes): + subnode.purge(True) + subnode = self.Subnode(name) + self.subnodes.insert(0, subnode) + return subnode + + def purge(self, delete_it=False): + """Purge this node, setting offset to None and deleting from FDT""" + if self._offset is not None: + if delete_it: + CheckErr(self._fdt._fdt_obj.del_node(self.Offset()), + "Node '%s': delete" % self.path) + self._offset = None + self._fdt.Invalidate() + + for prop in self.props.values(): + prop.purge() + + for subnode in self.subnodes: + subnode.purge(False) + + def move_to_first(self): + """Move the current node to first in its parent's node list""" + parent = self.parent + if parent.subnodes and parent.subnodes[0] == self: + return + for subnode in reversed(parent.subnodes): + subnode.purge(True) + + new_subnodes = [self] + for subnode in parent.subnodes: + #subnode.purge(False) + if subnode != self: + new_subnodes.append(subnode) + parent.subnodes = new_subnodes + def Delete(self): """Delete a node @@ -635,6 +705,71 @@ class Node: prop.Sync(auto_resize) return added + def merge_props(self, src): + """Copy missing properties (except 'phandle') from another node + + Args: + src (Node): Node containing properties to copy + + Adds properties which are present in src but not in this node. Any + 'phandle' property is not copied since this might result in two nodes + with the same phandle, thus making phandle references ambiguous. + """ + for name, src_prop in src.props.items(): + if name != 'phandle' and name not in self.props: + self.props[name] = Prop(self, None, name, src_prop.bytes) + + def copy_node(self, src): + """Copy a node and all its subnodes into this node + + Args: + src (Node): Node to copy + + Returns: + Node: Resulting destination node + + This works recursively. + + The new node is put before all other nodes. If the node already + exists, just its subnodes and properties are copied, placing them before + any existing subnodes. Properties which exist in the destination node + already are not copied. + """ + dst = self.FindNode(src.name) + if dst: + dst.move_to_first() + else: + dst = self.insert_subnode(src.name) + dst.merge_props(src) + + # Process in reverse order so that they appear correctly in the result, + # since copy_node() puts the node first in the list + for node in reversed(src.subnodes): + dst.copy_node(node) + return dst + + def copy_subnodes_from_phandles(self, phandle_list): + """Copy subnodes of a list of nodes into another node + + Args: + phandle_list (list of int): List of phandles of nodes to copy + + For each node in the phandle list, its subnodes and their properties are + copied recursively. Note that it does not copy the node itself, nor its + properties. + """ + # Process in reverse order, since new nodes are inserted at the start of + # the destination's node list. We want them to appear in order of the + # phandle list + for phandle in phandle_list.__reversed__(): + parent = self.GetFdt().LookupPhandle(phandle) + tout.debug(f'adding template {parent.path} to node {self.path}') + for node in parent.subnodes.__reversed__(): + dst = self.copy_node(node) + + tout.debug(f'merge props from {parent.path} to {dst.path}') + self.merge_props(parent) + class Fdt: """Provides simple access to a flat device tree blob using libfdts. diff --git a/tools/dtoc/test/dtoc_test_copy.dts b/tools/dtoc/test/dtoc_test_copy.dts new file mode 100644 index 0000000..36faa9b --- /dev/null +++ b/tools/dtoc/test/dtoc_test_copy.dts @@ -0,0 +1,88 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Test device tree file for dtoc + * + * Copyright 2017 Google, Inc + */ + +/dts-v1/; + +/ { + #address-cells = <1>; + #size-cells = <1>; + reference = <&over>; /* nake sure that the 'over' phandle exists */ + copy-list = <&another &base>; + + dest { + bootph-all; + compatible = "sandbox,spl-test"; + stringarray = "one"; + longbytearray = [09 0a 0b 0c 0d 0e 0f 10]; + maybe-empty-int = <1>; + + first@0 { + a-prop = <456>; + b-prop = <1>; + }; + + existing { + }; + + base { + second { + second3 { + }; + + second2 { + new-prop; + }; + + second1 { + new-prop; + }; + + second4 { + }; + }; + }; + }; + + base: base { + compatible = "sandbox,i2c"; + bootph-all; + #address-cells = <1>; + #size-cells = <0>; + over: over { + compatible = "sandbox,pmic"; + bootph-all; + reg = <9>; + low-power; + }; + + first@0 { + reg = <0>; + a-prop = <123>; + }; + + second: second { + second1 { + some-prop; + }; + + second2 { + some-prop; + }; + }; + }; + + another: another { + new-prop = "hello"; + earlier { + wibble = <2>; + }; + + later { + fibble = <3>; + }; + }; +}; diff --git a/tools/dtoc/test_fdt.py b/tools/dtoc/test_fdt.py index 4fe8d12..3e54694 100755 --- a/tools/dtoc/test_fdt.py +++ b/tools/dtoc/test_fdt.py @@ -306,6 +306,119 @@ class TestNode(unittest.TestCase): self.assertIn("Internal error, node '/spl-test' name mismatch 'i2c@0'", str(exc.exception)) + def test_copy_node(self): + """Test copy_node() function""" + def do_copy_checks(dtb, dst, expect_none): + self.assertEqual( + ['/dest/base', '/dest/first@0', '/dest/existing'], + [n.path for n in dst.subnodes]) + + chk = dtb.GetNode('/dest/base') + self.assertTrue(chk) + self.assertEqual( + {'compatible', 'bootph-all', '#address-cells', '#size-cells'}, + chk.props.keys()) + + # Check the first property + prop = chk.props['bootph-all'] + self.assertEqual('bootph-all', prop.name) + self.assertEqual(True, prop.value) + self.assertEqual(chk.path, prop._node.path) + + # Check the second property + prop2 = chk.props['compatible'] + self.assertEqual('compatible', prop2.name) + self.assertEqual('sandbox,i2c', prop2.value) + self.assertEqual(chk.path, prop2._node.path) + + base = chk.FindNode('base') + self.assertTrue(chk) + + first = dtb.GetNode('/dest/base/first@0') + self.assertTrue(first) + over = dtb.GetNode('/dest/base/over') + self.assertTrue(over) + + # Make sure that the phandle for 'over' is not copied + self.assertNotIn('phandle', over.props.keys()) + + second = dtb.GetNode('/dest/base/second') + self.assertTrue(second) + self.assertEqual([over.name, first.name, second.name], + [n.name for n in chk.subnodes]) + self.assertEqual(chk, over.parent) + self.assertEqual( + {'bootph-all', 'compatible', 'reg', 'low-power'}, + over.props.keys()) + + if expect_none: + self.assertIsNone(prop._offset) + self.assertIsNone(prop2._offset) + self.assertIsNone(over._offset) + else: + self.assertTrue(prop._offset) + self.assertTrue(prop2._offset) + self.assertTrue(over._offset) + + # Now check ordering of the subnodes + self.assertEqual( + ['second1', 'second2', 'second3', 'second4'], + [n.name for n in second.subnodes]) + + dtb = fdt.FdtScan(find_dtb_file('dtoc_test_copy.dts')) + tmpl = dtb.GetNode('/base') + dst = dtb.GetNode('/dest') + dst.copy_node(tmpl) + + do_copy_checks(dtb, dst, expect_none=True) + + dtb.Sync(auto_resize=True) + + # Now check that the FDT looks correct + new_dtb = fdt.Fdt.FromData(dtb.GetContents()) + new_dtb.Scan() + dst = new_dtb.GetNode('/dest') + do_copy_checks(new_dtb, dst, expect_none=False) + + def test_copy_subnodes_from_phandles(self): + """Test copy_node() function""" + dtb = fdt.FdtScan(find_dtb_file('dtoc_test_copy.dts')) + + orig = dtb.GetNode('/') + node_list = fdt_util.GetPhandleList(orig, 'copy-list') + + dst = dtb.GetNode('/dest') + dst.copy_subnodes_from_phandles(node_list) + + pmic = dtb.GetNode('/dest/over') + self.assertTrue(pmic) + + subn = dtb.GetNode('/dest/first@0') + self.assertTrue(subn) + self.assertEqual({'a-prop', 'b-prop', 'reg'}, subn.props.keys()) + + self.assertEqual( + ['/dest/earlier', '/dest/later', '/dest/over', '/dest/first@0', + '/dest/second', '/dest/existing', '/dest/base'], + [n.path for n in dst.subnodes]) + + # Make sure that the phandle for 'over' is not copied + over = dst.FindNode('over') + print('keys', over.props.keys()) + self.assertNotIn('phandle', over.props.keys()) + + # Check the merged properties, first the base ones in '/dest' + expect = {'bootph-all', 'compatible', 'stringarray', 'longbytearray', + 'maybe-empty-int'} + + # Properties from 'base' + expect.update({'#address-cells', '#size-cells'}) + + # Properties from 'another' + expect.add('new-prop') + + self.assertEqual(expect, set(dst.props.keys())) + class TestProp(unittest.TestCase): """Test operation of the Prop class""" diff --git a/tools/u_boot_pylib/pyproject.toml b/tools/u_boot_pylib/pyproject.toml index 3f33caf..037c5d6 100644 --- a/tools/u_boot_pylib/pyproject.toml +++ b/tools/u_boot_pylib/pyproject.toml @@ -9,7 +9,7 @@ authors = [ { name="Simon Glass", email="sjg@chromium.org" }, ] description = "U-Boot python library" -readme = "README.md" +readme = "README.rst" requires-python = ">=3.7" classifiers = [ "Programming Language :: Python :: 3", @@ -20,3 +20,7 @@ classifiers = [ [project.urls] "Homepage" = "https://u-boot.readthedocs.io" "Bug Tracker" = "https://source.denx.de/groups/u-boot/-/issues" + +[tool.setuptools.packages.find] +where = [".."] +include = ["u_boot_pylib*"] diff --git a/tools/zynqmp_psu_init_minimize.sh b/tools/zynqmp_psu_init_minimize.sh index 16c622f..5c8b737 100755 --- a/tools/zynqmp_psu_init_minimize.sh +++ b/tools/zynqmp_psu_init_minimize.sh @@ -1,6 +1,6 @@ #!/bin/bash # SPDX-License-Identifier: GPL-2.0+ -# Copyright (C) 2018 Michal Simek <michal.simek@xilinx.com> +# Copyright (C) 2018 Michal Simek <michal.simek@amd.com> # Copyright (C) 2019 Luca Ceresoli <luca@lucaceresoli.net> # Copyright (C) 2022 Weidmüller Interface GmbH & Co. KG # Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com> diff --git a/tools/zynqmpimage.c b/tools/zynqmpimage.c index 5113ba8..bb54f41 100644 --- a/tools/zynqmpimage.c +++ b/tools/zynqmpimage.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2016 Michal Simek <michals@xilinx.com> + * Copyright (C) 2016 Michal Simek <michal.simek@amd.com> * Copyright (C) 2015 Nathan Rossi <nathan@nathanrossi.com> * * The following Boot Header format/structures and values are defined in the diff --git a/tools/zynqmpimage.h b/tools/zynqmpimage.h index 9d526a1..ca74898 100644 --- a/tools/zynqmpimage.h +++ b/tools/zynqmpimage.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright (C) 2016 Michal Simek <michals@xilinx.com> + * Copyright (C) 2016 Michal Simek <michal.simek@amd.com> * Copyright (C) 2015 Nathan Rossi <nathan@nathanrossi.com> * * The following Boot Header format/structures and values are defined in the |