diff options
51 files changed, 2031 insertions, 430 deletions
diff --git a/arch/arm/dts/stm32f769-disco-u-boot.dtsi b/arch/arm/dts/stm32f769-disco-u-boot.dtsi index b5198fd..2c823cc 100644 --- a/arch/arm/dts/stm32f769-disco-u-boot.dtsi +++ b/arch/arm/dts/stm32f769-disco-u-boot.dtsi @@ -28,11 +28,6 @@ button-gpio = <&gpioa 0 0>; }; - dsi_host: dsi_host { - compatible = "synopsys,dw-mipi-dsi"; - status = "okay"; - }; - led1 { compatible = "st,led1"; led-gpio = <&gpioj 5 0>; diff --git a/arch/arm/dts/stm32mp13-pinctrl.dtsi b/arch/arm/dts/stm32mp13-pinctrl.dtsi index d2472cd..b2dce3a 100644 --- a/arch/arm/dts/stm32mp13-pinctrl.dtsi +++ b/arch/arm/dts/stm32mp13-pinctrl.dtsi @@ -6,6 +6,114 @@ #include <dt-bindings/pinctrl/stm32-pinfunc.h> &pinctrl { + adc1_usb_cc_pins_a: adc1-usb-cc-pins-0 { + pins { + pinmux = <STM32_PINMUX('F', 12, ANALOG)>, /* ADC1 in6 */ + <STM32_PINMUX('A', 3, ANALOG)>; /* ADC1 in12 */ + }; + }; + + i2c1_pins_a: i2c1-0 { + pins { + pinmux = <STM32_PINMUX('D', 12, AF5)>, /* I2C1_SCL */ + <STM32_PINMUX('E', 8, AF5)>; /* I2C1_SDA */ + bias-disable; + drive-open-drain; + slew-rate = <0>; + }; + }; + + i2c1_sleep_pins_a: i2c1-sleep-0 { + pins { + pinmux = <STM32_PINMUX('D', 12, ANALOG)>, /* I2C1_SCL */ + <STM32_PINMUX('E', 8, ANALOG)>; /* I2C1_SDA */ + }; + }; + + i2c5_pins_a: i2c5-0 { + pins { + pinmux = <STM32_PINMUX('D', 1, AF4)>, /* I2C5_SCL */ + <STM32_PINMUX('H', 6, AF4)>; /* I2C5_SDA */ + bias-disable; + drive-open-drain; + slew-rate = <0>; + }; + }; + + i2c5_sleep_pins_a: i2c5-sleep-0 { + pins { + pinmux = <STM32_PINMUX('D', 1, ANALOG)>, /* I2C5_SCL */ + <STM32_PINMUX('H', 6, ANALOG)>; /* I2C5_SDA */ + }; + }; + + mcp23017_pins_a: mcp23017-0 { + pins { + pinmux = <STM32_PINMUX('G', 12, GPIO)>; + bias-pull-up; + }; + }; + + pwm3_pins_a: pwm3-0 { + pins { + pinmux = <STM32_PINMUX('B', 1, AF2)>; /* TIM3_CH4 */ + bias-pull-down; + drive-push-pull; + slew-rate = <0>; + }; + }; + + pwm3_sleep_pins_a: pwm3-sleep-0 { + pins { + pinmux = <STM32_PINMUX('B', 1, ANALOG)>; /* TIM3_CH4 */ + }; + }; + + pwm4_pins_a: pwm4-0 { + pins { + pinmux = <STM32_PINMUX('D', 13, AF2)>; /* TIM4_CH2 */ + bias-pull-down; + drive-push-pull; + slew-rate = <0>; + }; + }; + + pwm4_sleep_pins_a: pwm4-sleep-0 { + pins { + pinmux = <STM32_PINMUX('D', 13, ANALOG)>; /* TIM4_CH2 */ + }; + }; + + pwm8_pins_a: pwm8-0 { + pins { + pinmux = <STM32_PINMUX('E', 5, AF3)>; /* TIM8_CH3 */ + bias-pull-down; + drive-push-pull; + slew-rate = <0>; + }; + }; + + pwm8_sleep_pins_a: pwm8-sleep-0 { + pins { + pinmux = <STM32_PINMUX('E', 5, ANALOG)>; /* TIM8_CH3 */ + }; + }; + + pwm14_pins_a: pwm14-0 { + pins { + pinmux = <STM32_PINMUX('F', 9, AF9)>; /* TIM14_CH1 */ + bias-pull-down; + drive-push-pull; + slew-rate = <0>; + }; + }; + + pwm14_sleep_pins_a: pwm14-sleep-0 { + pins { + pinmux = <STM32_PINMUX('F', 9, ANALOG)>; /* TIM14_CH1 */ + }; + }; + sdmmc1_b4_pins_a: sdmmc1-b4-0 { pins { pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */ @@ -108,6 +216,36 @@ }; }; + spi5_pins_a: spi5-0 { + pins1 { + pinmux = <STM32_PINMUX('H', 7, AF6)>, /* SPI5_SCK */ + <STM32_PINMUX('H', 3, AF5)>; /* SPI5_MOSI */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + + pins2 { + pinmux = <STM32_PINMUX('A', 8, AF5)>; /* SPI5_MISO */ + bias-disable; + }; + }; + + spi5_sleep_pins_a: spi5-sleep-0 { + pins { + pinmux = <STM32_PINMUX('H', 7, ANALOG)>, /* SPI5_SCK */ + <STM32_PINMUX('A', 8, ANALOG)>, /* SPI5_MISO */ + <STM32_PINMUX('H', 3, ANALOG)>; /* SPI5_MOSI */ + }; + }; + + stm32g0_intn_pins_a: stm32g0-intn-0 { + pins { + pinmux = <STM32_PINMUX('I', 2, GPIO)>; + bias-pull-up; + }; + }; + uart4_pins_a: uart4-0 { pins1 { pinmux = <STM32_PINMUX('D', 6, AF8)>; /* UART4_TX */ diff --git a/arch/arm/dts/stm32mp131.dtsi b/arch/arm/dts/stm32mp131.dtsi index 6d82bf6..d94ba25 100644 --- a/arch/arm/dts/stm32mp131.dtsi +++ b/arch/arm/dts/stm32mp131.dtsi @@ -77,6 +77,28 @@ always-on; }; + /* PWR 1v1, 1v8 and 3v3 regulators defined as fixed, waiting for SCMI */ + reg11: reg11 { + compatible = "regulator-fixed"; + regulator-name = "reg11"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + }; + + reg18: reg18 { + compatible = "regulator-fixed"; + regulator-name = "reg18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + usb33: usb33 { + compatible = "regulator-fixed"; + regulator-name = "usb33"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + soc { compatible = "simple-bus"; #address-cells = <1>; @@ -97,6 +119,284 @@ }; }; + timers2: timer@40000000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40000000 0x400>; + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "global"; + clocks = <&rcc TIM2_K>; + clock-names = "int"; + dmas = <&dmamux1 18 0x400 0x1>, + <&dmamux1 19 0x400 0x1>, + <&dmamux1 20 0x400 0x1>, + <&dmamux1 21 0x400 0x1>, + <&dmamux1 22 0x400 0x1>; + dma-names = "ch1", "ch2", "ch3", "ch4", "up"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@1 { + compatible = "st,stm32h7-timer-trigger"; + reg = <1>; + status = "disabled"; + }; + + counter { + compatible = "st,stm32-timer-counter"; + status = "disabled"; + }; + }; + + timers3: timer@40001000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40001000 0x400>; + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "global"; + clocks = <&rcc TIM3_K>; + clock-names = "int"; + dmas = <&dmamux1 23 0x400 0x1>, + <&dmamux1 24 0x400 0x1>, + <&dmamux1 25 0x400 0x1>, + <&dmamux1 26 0x400 0x1>, + <&dmamux1 27 0x400 0x1>, + <&dmamux1 28 0x400 0x1>; + dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@2 { + compatible = "st,stm32h7-timer-trigger"; + reg = <2>; + status = "disabled"; + }; + + counter { + compatible = "st,stm32-timer-counter"; + status = "disabled"; + }; + }; + + timers4: timer@40002000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40002000 0x400>; + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "global"; + clocks = <&rcc TIM4_K>; + clock-names = "int"; + dmas = <&dmamux1 29 0x400 0x1>, + <&dmamux1 30 0x400 0x1>, + <&dmamux1 31 0x400 0x1>, + <&dmamux1 32 0x400 0x1>; + dma-names = "ch1", "ch2", "ch3", "up"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@3 { + compatible = "st,stm32h7-timer-trigger"; + reg = <3>; + status = "disabled"; + }; + + counter { + compatible = "st,stm32-timer-counter"; + status = "disabled"; + }; + }; + + timers5: timer@40003000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40003000 0x400>; + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "global"; + clocks = <&rcc TIM5_K>; + clock-names = "int"; + dmas = <&dmamux1 55 0x400 0x1>, + <&dmamux1 56 0x400 0x1>, + <&dmamux1 57 0x400 0x1>, + <&dmamux1 58 0x400 0x1>, + <&dmamux1 59 0x400 0x1>, + <&dmamux1 60 0x400 0x1>; + dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@4 { + compatible = "st,stm32h7-timer-trigger"; + reg = <4>; + status = "disabled"; + }; + + counter { + compatible = "st,stm32-timer-counter"; + status = "disabled"; + }; + }; + + timers6: timer@40004000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40004000 0x400>; + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "global"; + clocks = <&rcc TIM6_K>; + clock-names = "int"; + dmas = <&dmamux1 69 0x400 0x1>; + dma-names = "up"; + status = "disabled"; + + timer@5 { + compatible = "st,stm32h7-timer-trigger"; + reg = <5>; + status = "disabled"; + }; + }; + + timers7: timer@40005000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40005000 0x400>; + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "global"; + clocks = <&rcc TIM7_K>; + clock-names = "int"; + dmas = <&dmamux1 70 0x400 0x1>; + dma-names = "up"; + status = "disabled"; + + timer@6 { + compatible = "st,stm32h7-timer-trigger"; + reg = <6>; + status = "disabled"; + }; + }; + + lptimer1: timer@40009000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-lptimer"; + reg = <0x40009000 0x400>; + interrupts-extended = <&exti 47 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc LPTIM1_K>; + clock-names = "mux"; + wakeup-source; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm-lp"; + #pwm-cells = <3>; + status = "disabled"; + }; + + trigger@0 { + compatible = "st,stm32-lptimer-trigger"; + reg = <0>; + status = "disabled"; + }; + + counter { + compatible = "st,stm32-lptimer-counter"; + status = "disabled"; + }; + + timer { + compatible = "st,stm32-lptimer-timer"; + status = "disabled"; + }; + }; + + i2s2: audio-controller@4000b000 { + compatible = "st,stm32h7-i2s"; + reg = <0x4000b000 0x400>; + #sound-dai-cells = <0>; + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dmamux1 39 0x400 0x01>, + <&dmamux1 40 0x400 0x01>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + spi2: spi@4000b000 { + compatible = "st,stm32h7-spi"; + reg = <0x4000b000 0x400>; + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc SPI2_K>; + resets = <&rcc SPI2_R>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dmamux1 39 0x400 0x01>, + <&dmamux1 40 0x400 0x01>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + i2s3: audio-controller@4000c000 { + compatible = "st,stm32h7-i2s"; + reg = <0x4000c000 0x400>; + #sound-dai-cells = <0>; + interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dmamux1 61 0x400 0x01>, + <&dmamux1 62 0x400 0x01>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + spi3: spi@4000c000 { + compatible = "st,stm32h7-spi"; + reg = <0x4000c000 0x400>; + interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc SPI3_K>; + resets = <&rcc SPI3_R>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dmamux1 61 0x400 0x01>, + <&dmamux1 62 0x400 0x01>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + spdifrx: audio-controller@4000d000 { + compatible = "st,stm32h7-spdifrx"; + reg = <0x4000d000 0x400>; + #sound-dai-cells = <0>; + clocks = <&rcc SPDIF_K>; + clock-names = "kclk"; + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dmamux1 93 0x400 0x01>, + <&dmamux1 94 0x400 0x01>; + dma-names = "rx", "rx-ctrl"; + status = "disabled"; + }; + uart4: serial@40010000 { compatible = "st,stm32h7-uart"; reg = <0x40010000 0x400>; @@ -106,6 +406,241 @@ status = "disabled"; }; + i2c1: i2c@40012000 { + compatible = "st,stm32mp13-i2c"; + reg = <0x40012000 0x400>; + interrupt-names = "event", "error"; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc I2C1_K>; + resets = <&rcc I2C1_R>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dmamux1 33 0x400 0x1>, + <&dmamux1 34 0x400 0x1>; + dma-names = "rx", "tx"; + st,syscfg-fmp = <&syscfg 0x4 0x1>; + i2c-analog-filter; + status = "disabled"; + }; + + i2c2: i2c@40013000 { + compatible = "st,stm32mp13-i2c"; + reg = <0x40013000 0x400>; + interrupt-names = "event", "error"; + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc I2C2_K>; + resets = <&rcc I2C2_R>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dmamux1 35 0x400 0x1>, + <&dmamux1 36 0x400 0x1>; + dma-names = "rx", "tx"; + st,syscfg-fmp = <&syscfg 0x4 0x2>; + i2c-analog-filter; + status = "disabled"; + }; + + timers1: timer@44000000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x44000000 0x400>; + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "brk", "up", "trg-com", "cc"; + clocks = <&rcc TIM1_K>; + clock-names = "int"; + dmas = <&dmamux1 11 0x400 0x1>, + <&dmamux1 12 0x400 0x1>, + <&dmamux1 13 0x400 0x1>, + <&dmamux1 14 0x400 0x1>, + <&dmamux1 15 0x400 0x1>, + <&dmamux1 16 0x400 0x1>, + <&dmamux1 17 0x400 0x1>; + dma-names = "ch1", "ch2", "ch3", "ch4", + "up", "trig", "com"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@0 { + compatible = "st,stm32h7-timer-trigger"; + reg = <0>; + status = "disabled"; + }; + + counter { + compatible = "st,stm32-timer-counter"; + status = "disabled"; + }; + }; + + timers8: timer@44001000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x44001000 0x400>; + interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "brk", "up", "trg-com", "cc"; + clocks = <&rcc TIM8_K>; + clock-names = "int"; + dmas = <&dmamux1 47 0x400 0x1>, + <&dmamux1 48 0x400 0x1>, + <&dmamux1 49 0x400 0x1>, + <&dmamux1 50 0x400 0x1>, + <&dmamux1 51 0x400 0x1>, + <&dmamux1 52 0x400 0x1>, + <&dmamux1 53 0x400 0x1>; + dma-names = "ch1", "ch2", "ch3", "ch4", + "up", "trig", "com"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@7 { + compatible = "st,stm32h7-timer-trigger"; + reg = <7>; + status = "disabled"; + }; + + counter { + compatible = "st,stm32-timer-counter"; + status = "disabled"; + }; + }; + + i2s1: audio-controller@44004000 { + compatible = "st,stm32h7-i2s"; + reg = <0x44004000 0x400>; + #sound-dai-cells = <0>; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dmamux1 37 0x400 0x01>, + <&dmamux1 38 0x400 0x01>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + spi1: spi@44004000 { + compatible = "st,stm32h7-spi"; + reg = <0x44004000 0x400>; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc SPI1_K>; + resets = <&rcc SPI1_R>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dmamux1 37 0x400 0x01>, + <&dmamux1 38 0x400 0x01>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + sai1: sai@4400a000 { + compatible = "st,stm32h7-sai"; + reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>; + ranges = <0 0x4400a000 0x400>; + #address-cells = <1>; + #size-cells = <1>; + interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; + resets = <&rcc SAI1_R>; + status = "disabled"; + + sai1a: audio-controller@4400a004 { + compatible = "st,stm32-sai-sub-a"; + reg = <0x4 0x20>; + #sound-dai-cells = <0>; + clocks = <&rcc SAI1_K>; + clock-names = "sai_ck"; + dmas = <&dmamux1 87 0x400 0x01>; + status = "disabled"; + }; + + sai1b: audio-controller@4400a024 { + compatible = "st,stm32-sai-sub-b"; + reg = <0x24 0x20>; + #sound-dai-cells = <0>; + clocks = <&rcc SAI1_K>; + clock-names = "sai_ck"; + dmas = <&dmamux1 88 0x400 0x01>; + status = "disabled"; + }; + }; + + sai2: sai@4400b000 { + compatible = "st,stm32h7-sai"; + reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>; + ranges = <0 0x4400b000 0x400>; + #address-cells = <1>; + #size-cells = <1>; + interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; + resets = <&rcc SAI2_R>; + status = "disabled"; + + sai2a: audio-controller@4400b004 { + compatible = "st,stm32-sai-sub-a"; + reg = <0x4 0x20>; + #sound-dai-cells = <0>; + clocks = <&rcc SAI2_K>; + clock-names = "sai_ck"; + dmas = <&dmamux1 89 0x400 0x01>; + status = "disabled"; + }; + + sai2b: audio-controller@4400b024 { + compatible = "st,stm32-sai-sub-b"; + reg = <0x24 0x20>; + #sound-dai-cells = <0>; + clocks = <&rcc SAI2_K>; + clock-names = "sai_ck"; + dmas = <&dmamux1 90 0x400 0x01>; + status = "disabled"; + }; + }; + + dfsdm: dfsdm@4400d000 { + compatible = "st,stm32mp1-dfsdm"; + reg = <0x4400d000 0x800>; + clocks = <&rcc DFSDM_K>; + clock-names = "dfsdm"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + dfsdm0: filter@0 { + compatible = "st,stm32-dfsdm-adc"; + reg = <0>; + #io-channel-cells = <1>; + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dmamux1 101 0x400 0x01>; + dma-names = "rx"; + status = "disabled"; + }; + + dfsdm1: filter@1 { + compatible = "st,stm32-dfsdm-adc"; + reg = <1>; + #io-channel-cells = <1>; + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dmamux1 102 0x400 0x01>; + dma-names = "rx"; + status = "disabled"; + }; + }; + dma1: dma-controller@48000000 { compatible = "st,stm32-dma"; reg = <0x48000000 0x400>; @@ -153,6 +688,314 @@ dma-channels = <16>; }; + adc_2: adc@48004000 { + compatible = "st,stm32mp13-adc-core"; + reg = <0x48004000 0x400>; + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc ADC2>, <&rcc ADC2_K>; + clock-names = "bus", "adc"; + interrupt-controller; + #interrupt-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + adc2: adc@0 { + compatible = "st,stm32mp13-adc"; + #io-channel-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; + interrupt-parent = <&adc_2>; + interrupts = <0>; + dmas = <&dmamux1 10 0x400 0x80000001>; + dma-names = "rx"; + status = "disabled"; + + channel@13 { + reg = <13>; + label = "vrefint"; + }; + channel@14 { + reg = <14>; + label = "vddcore"; + }; + channel@16 { + reg = <16>; + label = "vddcpu"; + }; + channel@17 { + reg = <17>; + label = "vddq_ddr"; + }; + }; + }; + + usbotg_hs: usb@49000000 { + compatible = "st,stm32mp15-hsotg", "snps,dwc2"; + reg = <0x49000000 0x40000>; + clocks = <&rcc USBO_K>; + clock-names = "otg"; + resets = <&rcc USBO_R>; + reset-names = "dwc2"; + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; + g-rx-fifo-size = <512>; + g-np-tx-fifo-size = <32>; + g-tx-fifo-size = <256 16 16 16 16 16 16 16>; + dr_mode = "otg"; + otg-rev = <0x200>; + usb33d-supply = <&usb33>; + status = "disabled"; + }; + + i2s4: audio-controller@4c002000 { + compatible = "st,stm32h7-i2s"; + reg = <0x4c002000 0x400>; + #sound-dai-cells = <0>; + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dmamux1 83 0x400 0x01>, + <&dmamux1 84 0x400 0x01>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + spi4: spi@4c002000 { + compatible = "st,stm32h7-spi"; + reg = <0x4c002000 0x400>; + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc SPI4_K>; + resets = <&rcc SPI4_R>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dmamux1 83 0x400 0x01>, + <&dmamux1 84 0x400 0x01>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + spi5: spi@4c003000 { + compatible = "st,stm32h7-spi"; + reg = <0x4c003000 0x400>; + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc SPI5_K>; + resets = <&rcc SPI5_R>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dmamux1 85 0x400 0x01>, + <&dmamux1 86 0x400 0x01>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + i2c3: i2c@4c004000 { + compatible = "st,stm32mp13-i2c"; + reg = <0x4c004000 0x400>; + interrupt-names = "event", "error"; + interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc I2C3_K>; + resets = <&rcc I2C3_R>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dmamux1 73 0x400 0x1>, + <&dmamux1 74 0x400 0x1>; + dma-names = "rx", "tx"; + st,syscfg-fmp = <&syscfg 0x4 0x4>; + i2c-analog-filter; + status = "disabled"; + }; + + i2c4: i2c@4c005000 { + compatible = "st,stm32mp13-i2c"; + reg = <0x4c005000 0x400>; + interrupt-names = "event", "error"; + interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc I2C4_K>; + resets = <&rcc I2C4_R>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dmamux1 75 0x400 0x1>, + <&dmamux1 76 0x400 0x1>; + dma-names = "rx", "tx"; + st,syscfg-fmp = <&syscfg 0x4 0x8>; + i2c-analog-filter; + status = "disabled"; + }; + + i2c5: i2c@4c006000 { + compatible = "st,stm32mp13-i2c"; + reg = <0x4c006000 0x400>; + interrupt-names = "event", "error"; + interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc I2C5_K>; + resets = <&rcc I2C5_R>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dmamux1 115 0x400 0x1>, + <&dmamux1 116 0x400 0x1>; + dma-names = "rx", "tx"; + st,syscfg-fmp = <&syscfg 0x4 0x10>; + i2c-analog-filter; + status = "disabled"; + }; + + timers12: timer@4c007000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x4c007000 0x400>; + interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "global"; + clocks = <&rcc TIM12_K>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@11 { + compatible = "st,stm32h7-timer-trigger"; + reg = <11>; + status = "disabled"; + }; + }; + + timers13: timer@4c008000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x4c008000 0x400>; + interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "global"; + clocks = <&rcc TIM13_K>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@12 { + compatible = "st,stm32h7-timer-trigger"; + reg = <12>; + status = "disabled"; + }; + }; + + timers14: timer@4c009000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x4c009000 0x400>; + interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "global"; + clocks = <&rcc TIM14_K>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@13 { + compatible = "st,stm32h7-timer-trigger"; + reg = <13>; + status = "disabled"; + }; + }; + + timers15: timer@4c00a000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x4c00a000 0x400>; + interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "global"; + clocks = <&rcc TIM15_K>; + clock-names = "int"; + dmas = <&dmamux1 105 0x400 0x1>, + <&dmamux1 106 0x400 0x1>, + <&dmamux1 107 0x400 0x1>, + <&dmamux1 108 0x400 0x1>; + dma-names = "ch1", "up", "trig", "com"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@14 { + compatible = "st,stm32h7-timer-trigger"; + reg = <14>; + status = "disabled"; + }; + }; + + timers16: timer@4c00b000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x4c00b000 0x400>; + interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "global"; + clocks = <&rcc TIM16_K>; + clock-names = "int"; + dmas = <&dmamux1 109 0x400 0x1>, + <&dmamux1 110 0x400 0x1>; + dma-names = "ch1", "up"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@15 { + compatible = "st,stm32h7-timer-trigger"; + reg = <15>; + status = "disabled"; + }; + }; + + timers17: timer@4c00c000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x4c00c000 0x400>; + interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "global"; + clocks = <&rcc TIM17_K>; + clock-names = "int"; + dmas = <&dmamux1 111 0x400 0x1>, + <&dmamux1 112 0x400 0x1>; + dma-names = "ch1", "up"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@16 { + compatible = "st,stm32h7-timer-trigger"; + reg = <16>; + status = "disabled"; + }; + }; + rcc: rcc@50000000 { compatible = "st,stm32mp13-rcc", "syscon"; reg = <0x50000000 0x1000>; @@ -181,6 +1024,111 @@ clocks = <&rcc SYSCFG>; }; + lptimer2: timer@50021000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-lptimer"; + reg = <0x50021000 0x400>; + interrupts-extended = <&exti 48 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc LPTIM2_K>; + clock-names = "mux"; + wakeup-source; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm-lp"; + #pwm-cells = <3>; + status = "disabled"; + }; + + trigger@1 { + compatible = "st,stm32-lptimer-trigger"; + reg = <1>; + status = "disabled"; + }; + + counter { + compatible = "st,stm32-lptimer-counter"; + status = "disabled"; + }; + + timer { + compatible = "st,stm32-lptimer-timer"; + status = "disabled"; + }; + }; + + lptimer3: timer@50022000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-lptimer"; + reg = <0x50022000 0x400>; + interrupts-extended = <&exti 50 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc LPTIM3_K>; + clock-names = "mux"; + wakeup-source; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm-lp"; + #pwm-cells = <3>; + status = "disabled"; + }; + + trigger@2 { + compatible = "st,stm32-lptimer-trigger"; + reg = <2>; + status = "disabled"; + }; + + timer { + compatible = "st,stm32-lptimer-timer"; + status = "disabled"; + }; + }; + + lptimer4: timer@50023000 { + compatible = "st,stm32-lptimer"; + reg = <0x50023000 0x400>; + interrupts-extended = <&exti 52 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc LPTIM4_K>; + clock-names = "mux"; + wakeup-source; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm-lp"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer { + compatible = "st,stm32-lptimer-timer"; + status = "disabled"; + }; + }; + + lptimer5: timer@50024000 { + compatible = "st,stm32-lptimer"; + reg = <0x50024000 0x400>; + interrupts-extended = <&exti 53 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc LPTIM5_K>; + clock-names = "mux"; + wakeup-source; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm-lp"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer { + compatible = "st,stm32-lptimer-timer"; + status = "disabled"; + }; + }; + mdma: dma-controller@58000000 { compatible = "st,stm32h7-mdma"; reg = <0x58000000 0x1000>; @@ -261,13 +1209,31 @@ clocks = <&rcc SDMMC2_K>; clock-names = "apb_pclk"; resets = <&rcc SDMMC2_R>; - cap-sd-highspeed; cap-mmc-highspeed; max-frequency = <130000000>; status = "disabled"; }; + usbh_ohci: usb@5800c000 { + compatible = "generic-ohci"; + reg = <0x5800c000 0x1000>; + clocks = <&usbphyc>, <&rcc USBH>; + resets = <&rcc USBH_R>; + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + usbh_ehci: usb@5800d000 { + compatible = "generic-ehci"; + reg = <0x5800d000 0x1000>; + clocks = <&usbphyc>, <&rcc USBH>; + resets = <&rcc USBH_R>; + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; + companion = <&usbh_ohci>; + status = "disabled"; + }; + iwdg2: watchdog@5a002000 { compatible = "st,stm32mp1-iwdg"; reg = <0x5a002000 0x400>; @@ -276,6 +1242,29 @@ status = "disabled"; }; + usbphyc: usbphyc@5a006000 { + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <0>; + compatible = "st,stm32mp1-usbphyc"; + reg = <0x5a006000 0x1000>; + clocks = <&rcc USBPHY_K>; + resets = <&rcc USBPHY_R>; + vdda1v1-supply = <®11>; + vdda1v8-supply = <®18>; + status = "disabled"; + + usbphyc_port0: usb-phy@0 { + #phy-cells = <0>; + reg = <0>; + }; + + usbphyc_port1: usb-phy@1 { + #phy-cells = <1>; + reg = <1>; + }; + }; + rtc: rtc@5c004000 { compatible = "st,stm32mp1-rtc"; reg = <0x5c004000 0x400>; @@ -294,6 +1283,7 @@ part_number_otp: part_number_otp@4 { reg = <0x4 0x2>; + bits = <0 12>; }; ts_cal1: calib@5c { reg = <0x5c 0x2>; @@ -314,7 +1304,6 @@ ranges = <0 0x50002000 0x8400>; interrupt-parent = <&exti>; st,syscfg = <&exti 0x60 0xff>; - pins-are-numbered; gpioa: gpio@50002000 { gpio-controller; diff --git a/arch/arm/dts/stm32mp133.dtsi b/arch/arm/dts/stm32mp133.dtsi index 531c263..df451c3 100644 --- a/arch/arm/dts/stm32mp133.dtsi +++ b/arch/arm/dts/stm32mp133.dtsi @@ -33,5 +33,36 @@ bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>; status = "disabled"; }; + + adc_1: adc@48003000 { + compatible = "st,stm32mp13-adc-core"; + reg = <0x48003000 0x400>; + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc ADC1>, <&rcc ADC1_K>; + clock-names = "bus", "adc"; + interrupt-controller; + #interrupt-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + adc1: adc@0 { + compatible = "st,stm32mp13-adc"; + #io-channel-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; + interrupt-parent = <&adc_1>; + interrupts = <0>; + dmas = <&dmamux1 9 0x400 0x80000001>; + dma-names = "rx"; + status = "disabled"; + + channel@18 { + reg = <18>; + label = "vrefint"; + }; + }; + }; }; }; diff --git a/arch/arm/dts/stm32mp135f-dk.dts b/arch/arm/dts/stm32mp135f-dk.dts index 52f8659..c40686c 100644 --- a/arch/arm/dts/stm32mp135f-dk.dts +++ b/arch/arm/dts/stm32mp135f-dk.dts @@ -40,7 +40,7 @@ gpio-keys { compatible = "gpio-keys"; - user-pa13 { + button-user { label = "User-PA13"; linux,code = <BTN_1>; gpios = <&gpioa 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; @@ -59,6 +59,22 @@ }; }; + v3v3_sw: v3v3-sw { + compatible = "regulator-fixed"; + regulator-name = "v3v3_sw"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdd_adc: vdd-adc { + compatible = "regulator-fixed"; + regulator-name = "vdd_adc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + vdd_sd: vdd-sd { compatible = "regulator-fixed"; regulator-name = "vdd_sd"; @@ -66,6 +82,101 @@ regulator-max-microvolt = <2900000>; regulator-always-on; }; + + vdd_usb: vdd-usb { + compatible = "regulator-fixed"; + regulator-name = "vdd_usb"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; +}; + +&adc_1 { + pinctrl-names = "default"; + pinctrl-0 = <&adc1_usb_cc_pins_a>; + vdda-supply = <&vdd_adc>; + vref-supply = <&vdd_adc>; + status = "okay"; + adc1: adc@0 { + status = "okay"; + /* + * Type-C USB_PWR_CC1 & USB_PWR_CC2 on in6 & in12. + * Use at least 5 * RC time, e.g. 5 * (Rp + Rd) * C: + * 5 * (5.1 + 47kOhms) * 5pF => 1.3us. + * Use arbitrary margin here (e.g. 5us). + */ + channel@6 { + reg = <6>; + st,min-sample-time-ns = <5000>; + }; + channel@12 { + reg = <12>; + st,min-sample-time-ns = <5000>; + }; + }; +}; + +&i2c1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c1_pins_a>; + pinctrl-1 = <&i2c1_sleep_pins_a>; + i2c-scl-rising-time-ns = <96>; + i2c-scl-falling-time-ns = <3>; + clock-frequency = <1000000>; + status = "okay"; + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + + mcp23017: pinctrl@21 { + compatible = "microchip,mcp23017"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + interrupts = <12 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpiog>; + pinctrl-names = "default"; + pinctrl-0 = <&mcp23017_pins_a>; + interrupt-controller; + #interrupt-cells = <2>; + microchip,irq-mirror; + }; + + typec@53 { + compatible = "st,stm32g0-typec"; + reg = <0x53>; + /* Alert pin on PI2 */ + interrupts = <2 IRQ_TYPE_EDGE_FALLING>; + interrupt-parent = <&gpioi>; + /* Internal pull-up on PI2 */ + pinctrl-names = "default"; + pinctrl-0 = <&stm32g0_intn_pins_a>; + firmware-name = "stm32g0-ucsi.mp135f-dk.fw"; + connector { + compatible = "usb-c-connector"; + label = "USB-C"; + + port { + con_usb_c_g0_ep: endpoint { + remote-endpoint = <&usbotg_hs_ep>; + }; + }; + }; + }; +}; + +&i2c5 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c5_pins_a>; + pinctrl-1 = <&i2c5_sleep_pins_a>; + i2c-scl-rising-time-ns = <170>; + i2c-scl-falling-time-ns = <5>; + clock-frequency = <400000>; + status = "okay"; + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; }; &iwdg2 { @@ -90,8 +201,130 @@ status = "okay"; }; +&spi5 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&spi5_pins_a>; + pinctrl-1 = <&spi5_sleep_pins_a>; + status = "disabled"; +}; + +&timers3 { + /delete-property/dmas; + /delete-property/dma-names; + status = "disabled"; + pwm { + pinctrl-0 = <&pwm3_pins_a>; + pinctrl-1 = <&pwm3_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + status = "okay"; + }; + timer@2 { + status = "okay"; + }; +}; + +&timers4 { + /delete-property/dmas; + /delete-property/dma-names; + status = "disabled"; + pwm { + pinctrl-0 = <&pwm4_pins_a>; + pinctrl-1 = <&pwm4_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + status = "okay"; + }; + timer@3 { + status = "okay"; + }; +}; + +&timers8 { + /delete-property/dmas; + /delete-property/dma-names; + status = "disabled"; + pwm { + pinctrl-0 = <&pwm8_pins_a>; + pinctrl-1 = <&pwm8_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + status = "okay"; + }; + timer@7 { + status = "okay"; + }; +}; + +&timers14 { + status = "disabled"; + pwm { + pinctrl-0 = <&pwm14_pins_a>; + pinctrl-1 = <&pwm14_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + status = "okay"; + }; + timer@13 { + status = "okay"; + }; +}; + &uart4 { pinctrl-names = "default"; pinctrl-0 = <&uart4_pins_a>; status = "okay"; }; + +&usbh_ehci { + phys = <&usbphyc_port0>; + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + /* onboard HUB */ + hub@1 { + compatible = "usb424,2514"; + reg = <1>; + vdd-supply = <&v3v3_sw>; + }; +}; + +&usbotg_hs { + phys = <&usbphyc_port1 0>; + phy-names = "usb2-phy"; + usb-role-switch; + status = "okay"; + port { + usbotg_hs_ep: endpoint { + remote-endpoint = <&con_usb_c_g0_ep>; + }; + }; +}; + +&usbphyc { + status = "okay"; +}; + +&usbphyc_port0 { + phy-supply = <&vdd_usb>; + st,current-boost-microamp = <1000>; + st,decrease-hs-slew-rate; + st,tune-hs-dc-level = <2>; + st,enable-hs-rftime-reduction; + st,trim-hs-current = <11>; + st,trim-hs-impedance = <2>; + st,tune-squelch-level = <1>; + st,enable-hs-rx-gain-eq; + st,no-hs-ftime-ctrl; + st,no-lsfs-sc; +}; + +&usbphyc_port1 { + phy-supply = <&vdd_usb>; + st,current-boost-microamp = <1000>; + st,decrease-hs-slew-rate; + st,tune-hs-dc-level = <2>; + st,enable-hs-rftime-reduction; + st,trim-hs-current = <11>; + st,trim-hs-impedance = <2>; + st,tune-squelch-level = <1>; + st,enable-hs-rx-gain-eq; + st,no-hs-ftime-ctrl; + st,no-lsfs-sc; +}; diff --git a/arch/arm/dts/stm32mp15-pinctrl.dtsi b/arch/arm/dts/stm32mp15-pinctrl.dtsi index 2cc9341..a9d2bec 100644 --- a/arch/arm/dts/stm32mp15-pinctrl.dtsi +++ b/arch/arm/dts/stm32mp15-pinctrl.dtsi @@ -1261,7 +1261,7 @@ }; qspi_bk1_pins_a: qspi-bk1-0 { - pins1 { + pins { pinmux = <STM32_PINMUX('F', 8, AF10)>, /* QSPI_BK1_IO0 */ <STM32_PINMUX('F', 9, AF10)>, /* QSPI_BK1_IO1 */ <STM32_PINMUX('F', 7, AF9)>, /* QSPI_BK1_IO2 */ @@ -1270,12 +1270,6 @@ drive-push-pull; slew-rate = <1>; }; - pins2 { - pinmux = <STM32_PINMUX('B', 6, AF10)>; /* QSPI_BK1_NCS */ - bias-pull-up; - drive-push-pull; - slew-rate = <1>; - }; }; qspi_bk1_sleep_pins_a: qspi-bk1-sleep-0 { @@ -1283,13 +1277,12 @@ pinmux = <STM32_PINMUX('F', 8, ANALOG)>, /* QSPI_BK1_IO0 */ <STM32_PINMUX('F', 9, ANALOG)>, /* QSPI_BK1_IO1 */ <STM32_PINMUX('F', 7, ANALOG)>, /* QSPI_BK1_IO2 */ - <STM32_PINMUX('F', 6, ANALOG)>, /* QSPI_BK1_IO3 */ - <STM32_PINMUX('B', 6, ANALOG)>; /* QSPI_BK1_NCS */ + <STM32_PINMUX('F', 6, ANALOG)>; /* QSPI_BK1_IO3 */ }; }; qspi_bk2_pins_a: qspi-bk2-0 { - pins1 { + pins { pinmux = <STM32_PINMUX('H', 2, AF9)>, /* QSPI_BK2_IO0 */ <STM32_PINMUX('H', 3, AF9)>, /* QSPI_BK2_IO1 */ <STM32_PINMUX('G', 10, AF11)>, /* QSPI_BK2_IO2 */ @@ -1298,7 +1291,34 @@ drive-push-pull; slew-rate = <1>; }; - pins2 { + }; + + qspi_bk2_sleep_pins_a: qspi-bk2-sleep-0 { + pins { + pinmux = <STM32_PINMUX('H', 2, ANALOG)>, /* QSPI_BK2_IO0 */ + <STM32_PINMUX('H', 3, ANALOG)>, /* QSPI_BK2_IO1 */ + <STM32_PINMUX('G', 10, ANALOG)>, /* QSPI_BK2_IO2 */ + <STM32_PINMUX('G', 7, ANALOG)>; /* QSPI_BK2_IO3 */ + }; + }; + + qspi_cs1_pins_a: qspi-cs1-0 { + pins { + pinmux = <STM32_PINMUX('B', 6, AF10)>; /* QSPI_BK1_NCS */ + bias-pull-up; + drive-push-pull; + slew-rate = <1>; + }; + }; + + qspi_cs1_sleep_pins_a: qspi-cs1-sleep-0 { + pins { + pinmux = <STM32_PINMUX('B', 6, ANALOG)>; /* QSPI_BK1_NCS */ + }; + }; + + qspi_cs2_pins_a: qspi-cs2-0 { + pins { pinmux = <STM32_PINMUX('C', 0, AF10)>; /* QSPI_BK2_NCS */ bias-pull-up; drive-push-pull; @@ -1306,13 +1326,9 @@ }; }; - qspi_bk2_sleep_pins_a: qspi-bk2-sleep-0 { + qspi_cs2_sleep_pins_a: qspi-cs2-sleep-0 { pins { - pinmux = <STM32_PINMUX('H', 2, ANALOG)>, /* QSPI_BK2_IO0 */ - <STM32_PINMUX('H', 3, ANALOG)>, /* QSPI_BK2_IO1 */ - <STM32_PINMUX('G', 10, ANALOG)>, /* QSPI_BK2_IO2 */ - <STM32_PINMUX('G', 7, ANALOG)>, /* QSPI_BK2_IO3 */ - <STM32_PINMUX('C', 0, ANALOG)>; /* QSPI_BK2_NCS */ + pinmux = <STM32_PINMUX('C', 0, ANALOG)>; /* QSPI_BK2_NCS */ }; }; diff --git a/arch/arm/dts/stm32mp151.dtsi b/arch/arm/dts/stm32mp151.dtsi index 5d178b5..b3baacb 100644 --- a/arch/arm/dts/stm32mp151.dtsi +++ b/arch/arm/dts/stm32mp151.dtsi @@ -1693,7 +1693,6 @@ ranges = <0 0x50002000 0xa400>; interrupt-parent = <&exti>; st,syscfg = <&exti 0x60 0xff>; - pins-are-numbered; gpioa: gpio@50002000 { gpio-controller; @@ -1822,7 +1821,6 @@ #size-cells = <1>; compatible = "st,stm32mp157-z-pinctrl"; ranges = <0 0x54004000 0x400>; - pins-are-numbered; interrupt-parent = <&exti>; st,syscfg = <&exti 0x60 0xff>; diff --git a/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi b/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi index cff3f49..2623ceb 100644 --- a/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi +++ b/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi @@ -12,6 +12,7 @@ i2c3 = &i2c4; usb0 = &usbotg_hs; }; + config { u-boot,boot-led = "heartbeat"; u-boot,error-led = "error"; diff --git a/arch/arm/dts/stm32mp157c-dk2-scmi-u-boot.dtsi b/arch/arm/dts/stm32mp157c-dk2-scmi-u-boot.dtsi index 5a8fc15..ae93497 100644 --- a/arch/arm/dts/stm32mp157c-dk2-scmi-u-boot.dtsi +++ b/arch/arm/dts/stm32mp157c-dk2-scmi-u-boot.dtsi @@ -4,3 +4,10 @@ */ #include "stm32mp157a-dk1-scmi-u-boot.dtsi" + +/ { + fwu-mdata { + compatible = "u-boot,fwu-mdata-gpt"; + fwu-mdata-store = <&sdmmc1>; + }; +}; diff --git a/arch/arm/dts/stm32mp157c-ev1-scmi-u-boot.dtsi b/arch/arm/dts/stm32mp157c-ev1-scmi-u-boot.dtsi index 71a94f9..9768db8d 100644 --- a/arch/arm/dts/stm32mp157c-ev1-scmi-u-boot.dtsi +++ b/arch/arm/dts/stm32mp157c-ev1-scmi-u-boot.dtsi @@ -14,4 +14,129 @@ spi0 = &qspi; usb0 = &usbotg_hs; }; + + fwu-mdata { + compatible = "u-boot,fwu-mdata-gpt"; + fwu-mdata-store = <&sdmmc1>; + }; +}; + +&flash0 { + bootph-pre-ram; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "fsbl1"; + reg = <0x00000000 0x00040000>; + }; + partition@40000 { + label = "fsbl2"; + reg = <0x00040000 0x00040000>; + }; + partition@80000 { + label = "metadata1"; + reg = <0x00080000 0x00040000>; + }; + partition@c0000 { + label = "metadata2"; + reg = <0x000c0000 0x00040000>; + }; + partition@100000 { + label = "fip-a"; + reg = <0x00100000 0x00400000>; + }; + partition@500000 { + label = "fip-b"; + reg = <0x00500000 0x00400000>; + }; + partition@900000 { + label = "u-boot-env"; + reg = <0x00900000 0x00080000>; + }; + partition@980000 { + label = "nor-user"; + reg = <0x00980000 0x03680000>; + }; + }; +}; + +&fmc { + nand-controller@4,0 { + nand@0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "fsbl1"; + reg = <0x00000000 0x00080000>; + }; + partition@80000 { + label = "fsbl2"; + reg = <0x00080000 0x00080000>; + }; + partition@100000 { + label = "metadata1"; + reg = <0x00100000 0x00080000>; + }; + partition@180000 { + label = "metadata2"; + reg = <0x00180000 0x00080000>; + }; + partition@200000 { + label = "fip-a1"; + reg = <0x00200000 0x00400000>; + }; + partition@600000 { + label = "fip-a2"; + reg = <0x00600000 0x00400000>; + }; + partition@a00000 { + label = "fip-b1"; + reg = <0x00a00000 0x00400000>; + }; + partition@e00000 { + label = "fip-b2"; + reg = <0x00e00000 0x00400000>; + }; + partition@1200000 { + label = "UBI"; + reg = <0x01200000 0x3ee00000>; + }; + }; + }; + }; +}; + +&qspi { + bootph-pre-ram; +}; + +&qspi_clk_pins_a { + bootph-pre-ram; + pins { + bootph-pre-ram; + }; +}; + +&qspi_bk1_pins_a { + bootph-pre-ram; + pins1 { + bootph-pre-ram; + }; + pins2 { + bootph-pre-ram; + }; +}; + +&qspi_bk2_pins_a { + bootph-pre-ram; + pins1 { + bootph-pre-ram; + }; + pins2 { + bootph-pre-ram; + }; }; diff --git a/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi b/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi index cb32c30..1f7fdbc 100644 --- a/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi +++ b/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi @@ -23,6 +23,103 @@ &flash0 { bootph-pre-ram; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + +#if defined(CONFIG_STM32MP15x_STM32IMAGE) || defined(CONFIG_SPL) + partition@0 { + label = "fsbl1"; + reg = <0x00000000 0x00040000>; + }; + partition@80000 { + label = "fsbl2"; + reg = <0x00040000 0x00040000>; + }; + partition@100000 { + label = "ssbl"; + reg = <0x00080000 0x00200000>; + }; + partition@280000 { + label = "u-boot-env"; + reg = <0x00280000 0x00080000>; + }; + partition@300000 { + label = "nor-user"; + reg = <0x00300000 0x03d00000>; + }; +#else + partition@0 { + label = "fsbl1"; + reg = <0x00000000 0x00040000>; + }; + partition@40000 { + label = "fsbl2"; + reg = <0x00040000 0x00040000>; + }; + partition@100000 { + label = "fip"; + reg = <0x00080000 0x00400000>; + }; + partition@480000 { + label = "u-boot-env"; + reg = <0x00480000 0x00080000>; + }; + partition@500000 { + label = "nor-user"; + reg = <0x00500000 0x03b00000>; + }; +#endif + }; +}; + +&fmc { + nand-controller@4,0 { + nand@0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + +#if defined(CONFIG_STM32MP15x_STM32IMAGE) || defined(CONFIG_SPL) + partition@0 { + label = "fsbl"; + reg = <0x00000000 0x00200000>; + }; + partition@200000 { + label = "ssbl1"; + reg = <0x00200000 0x00200000>; + }; + partition@400000 { + label = "ssbl2"; + reg = <0x00400000 0x00200000>; + }; + partition@600000 { + label = "UBI"; + reg = <0x00600000 0x3fa00000>; + }; +#else + partition@0 { + label = "fsbl"; + reg = <0x00000000 0x00200000>; + }; + partition@200000 { + label = "fip1"; + reg = <0x00200000 0x00400000>; + }; + partition@600000 { + label = "fip2"; + reg = <0x00600000 0x00400000>; + }; + partition@1200000 { + label = "UBI"; + reg = <0x00a00000 0x3f600000>; + }; +#endif + }; + }; + }; }; &qspi { @@ -55,4 +152,3 @@ bootph-pre-ram; }; }; - diff --git a/arch/arm/dts/stm32mp157c-ev1.dts b/arch/arm/dts/stm32mp157c-ev1.dts index 2d5db41..542226c 100644 --- a/arch/arm/dts/stm32mp157c-ev1.dts +++ b/arch/arm/dts/stm32mp157c-ev1.dts @@ -8,6 +8,7 @@ #include "stm32mp157c-ed1.dts" #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> +#include <dt-bindings/media/video-interfaces.h> / { model = "STMicroelectronics STM32MP157C eval daughter on eval mother"; @@ -90,7 +91,7 @@ port { dcmi_0: endpoint { remote-endpoint = <&ov5640_0>; - bus-type = <5>; + bus-type = <MEDIA_BUS_TYPE_PARALLEL>; bus-width = <8>; hsync-active = <0>; vsync-active = <0>; @@ -144,7 +145,7 @@ max-speed = <1000>; phy-handle = <&phy0>; - mdio0 { + mdio { #address-cells = <1>; #size-cells = <0>; compatible = "snps,dwmac-mdio"; @@ -255,8 +256,16 @@ &qspi { pinctrl-names = "default", "sleep"; - pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a &qspi_bk2_pins_a>; - pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a &qspi_bk2_sleep_pins_a>; + pinctrl-0 = <&qspi_clk_pins_a + &qspi_bk1_pins_a + &qspi_cs1_pins_a + &qspi_bk2_pins_a + &qspi_cs2_pins_a>; + pinctrl-1 = <&qspi_clk_sleep_pins_a + &qspi_bk1_sleep_pins_a + &qspi_cs1_sleep_pins_a + &qspi_bk2_sleep_pins_a + &qspi_cs2_sleep_pins_a>; reg = <0x58003000 0x1000>, <0x70000000 0x4000000>; #address-cells = <1>; #size-cells = <0>; @@ -393,6 +402,7 @@ st,tune-squelch-level = <3>; st,tune-hs-rx-offset = <2>; st,no-lsfs-sc; + connector { compatible = "usb-a-connector"; vbus-supply = <&vbus_sw>; diff --git a/arch/arm/dts/stm32mp15xx-dhcom-som.dtsi b/arch/arm/dts/stm32mp15xx-dhcom-som.dtsi index 83e2c87..de76174 100644 --- a/arch/arm/dts/stm32mp15xx-dhcom-som.dtsi +++ b/arch/arm/dts/stm32mp15xx-dhcom-som.dtsi @@ -429,8 +429,12 @@ &qspi { pinctrl-names = "default", "sleep"; - pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a>; - pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a>; + pinctrl-0 = <&qspi_clk_pins_a + &qspi_bk1_pins_a + &qspi_cs1_pins_a>; + pinctrl-1 = <&qspi_clk_sleep_pins_a + &qspi_bk1_sleep_pins_a + &qspi_cs1_sleep_pins_a>; reg = <0x58003000 0x1000>, <0x70000000 0x4000000>; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi index bc0730c..a808620 100644 --- a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi +++ b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi @@ -92,6 +92,33 @@ &flash0 { bootph-pre-ram; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "fsbl1"; + reg = <0x00000000 0x00040000>; + }; + partition@40000 { + label = "fsbl2"; + reg = <0x00040000 0x00040000>; + }; + partition@500000 { + label = "uboot"; + reg = <0x00080000 0x00160000>; + }; + partition@900000 { + label = "env1"; + reg = <0x001E0000 0x00010000>; + }; + partition@980000 { + label = "env2"; + reg = <0x001F0000 0x00010000>; + }; + }; }; &qspi { diff --git a/arch/arm/dts/stm32mp15xx-dhcor-som.dtsi b/arch/arm/dts/stm32mp15xx-dhcor-som.dtsi index 98033b5..f36eec1 100644 --- a/arch/arm/dts/stm32mp15xx-dhcor-som.dtsi +++ b/arch/arm/dts/stm32mp15xx-dhcor-som.dtsi @@ -191,8 +191,12 @@ &qspi { pinctrl-names = "default", "sleep"; - pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a>; - pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a>; + pinctrl-0 = <&qspi_clk_pins_a + &qspi_bk1_pins_a + &qspi_cs1_pins_a>; + pinctrl-1 = <&qspi_clk_sleep_pins_a + &qspi_bk1_sleep_pins_a + &qspi_cs1_sleep_pins_a>; reg = <0x58003000 0x1000>, <0x70000000 0x200000>; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi index 804c662..eb905ad 100644 --- a/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi +++ b/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi @@ -28,6 +28,33 @@ &flash0 { bootph-pre-ram; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "fsbl1"; + reg = <0x00000000 0x00040000>; + }; + partition@40000 { + label = "fsbl2"; + reg = <0x00040000 0x00040000>; + }; + partition@500000 { + label = "uboot"; + reg = <0x00080000 0x00160000>; + }; + partition@900000 { + label = "env1"; + reg = <0x001E0000 0x00010000>; + }; + partition@980000 { + label = "env2"; + reg = <0x001F0000 0x00010000>; + }; + }; }; &i2c4 { diff --git a/arch/arm/dts/stm32mp15xx-dkx.dtsi b/arch/arm/dts/stm32mp15xx-dkx.dtsi index 34af901..49b3e76 100644 --- a/arch/arm/dts/stm32mp15xx-dkx.dtsi +++ b/arch/arm/dts/stm32mp15xx-dkx.dtsi @@ -72,7 +72,7 @@ sound { compatible = "audio-graph-card"; - label = "STM32MP1-DK"; + label = "STM32MP15-DK"; routing = "Playback" , "MCLK", "Capture" , "MCLK", @@ -149,7 +149,7 @@ max-speed = <1000>; phy-handle = <&phy0>; - mdio0 { + mdio { #address-cells = <1>; #size-cells = <0>; compatible = "snps,dwmac-mdio"; @@ -509,14 +509,12 @@ sai2a: audio-controller@4400b004 { #clock-cells = <0>; dma-names = "tx"; - clocks = <&rcc SAI2_K>; - clock-names = "sai_ck"; status = "okay"; sai2a_port: port { sai2a_endpoint: endpoint { remote-endpoint = <&cs42l51_tx_endpoint>; - format = "i2s"; + dai-format = "i2s"; mclk-fs = <256>; dai-tdm-slot-num = <2>; dai-tdm-slot-width = <32>; @@ -534,7 +532,7 @@ sai2b_port: port { sai2b_endpoint: endpoint { remote-endpoint = <&cs42l51_rx_endpoint>; - format = "i2s"; + dai-format = "i2s"; mclk-fs = <256>; dai-tdm-slot-num = <2>; dai-tdm-slot-width = <32>; diff --git a/arch/arm/mach-stm32mp/bsec.c b/arch/arm/mach-stm32mp/bsec.c index f5f4b20..0dc1e5c 100644 --- a/arch/arm/mach-stm32mp/bsec.c +++ b/arch/arm/mach-stm32mp/bsec.c @@ -622,7 +622,7 @@ static int stm32mp_bsec_read(struct udevice *dev, int offset, shadow = false; } - if ((offs % 4) || (size % 4)) + if ((offs % 4) || (size % 4) || !size) return -EINVAL; if (IS_ENABLED(CONFIG_OPTEE) && priv->tee) { @@ -678,7 +678,7 @@ static int stm32mp_bsec_write(struct udevice *dev, int offset, shadow = false; } - if ((offs % 4) || (size % 4)) + if ((offs % 4) || (size % 4) || !size) return -EINVAL; if (IS_ENABLED(CONFIG_OPTEE) && priv->tee) { diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c b/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c index cfafa53..c695cc1 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c @@ -180,15 +180,6 @@ U_BOOT_CMD(stm32prog, 5, 0, do_stm32prog, " <size> = size of flashlayout (optional for image with STM32 header)\n" ); -#ifdef CONFIG_STM32MP15x_STM32IMAGE -bool stm32prog_get_tee_partitions(void) -{ - if (stm32prog_data) - return stm32prog_data->tee_detected; - - return false; -} -#endif bool stm32prog_get_fsbl_nor(void) { diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c index 6f3641c..9ba94be 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c @@ -63,6 +63,12 @@ static const efi_guid_t uuid_mmc[3] = { ROOTFS_MMC2_UUID }; +/* + * GUID value defined in the FWU specification for identification + * of the FWU metadata partition. + */ +#define FWU_MDATA_UUID "8a7a84a0-8387-40f6-ab41-a8b9a5a60d23" + /* FIP type partition UUID used by TF-A*/ #define FIP_TYPE_UUID "19D5DF83-11B0-457B-BE2C-7559C13142A5" @@ -208,11 +214,6 @@ static int optee_ta_invoke(struct stm32prog_data *data, int cmd, int type, return rc; } -/* partition handling routines : CONFIG_CMD_MTDPARTS */ -int mtdparts_init(void); -int find_dev_and_part(const char *id, struct mtd_device **dev, - u8 *part_num, struct part_info **part); - char *stm32prog_get_error(struct stm32prog_data *data) { static const char error_msg[] = "Unspecified"; @@ -430,8 +431,14 @@ static int parse_type(struct stm32prog_data *data, } } else if (!strcmp(p, "FIP")) { part->part_type = PART_FIP; + } else if (!strcmp(p, "FWU_MDATA")) { + part->part_type = PART_FWU_MDATA; + } else if (!strcmp(p, "ENV")) { + part->part_type = PART_ENV; } else if (!strcmp(p, "System")) { part->part_type = PART_SYSTEM; + } else if (!strcmp(p, "ESP")) { + part->part_type = PART_ESP; } else if (!strcmp(p, "FileSystem")) { part->part_type = PART_FILESYSTEM; } else if (!strcmp(p, "RawImage")) { @@ -514,7 +521,7 @@ static int parse_offset(struct stm32prog_data *data, stm32prog_err("Layout line %d: invalid part '%s'", i, p); } else { - part->addr = simple_strtoull(p, &tail, 0); + part->addr = simple_strtoull(p, &tail, 10); if (tail == p || *tail != '\0') { stm32prog_err("Layout line %d: invalid offset '%s'", i, p); @@ -741,6 +748,7 @@ static int init_device(struct stm32prog_data *data, struct mmc *mmc = NULL; struct blk_desc *block_dev = NULL; struct mtd_info *mtd = NULL; + struct mtd_info *partition; char mtd_id[16]; int part_id; int ret; @@ -749,6 +757,7 @@ static int init_device(struct stm32prog_data *data, u64 part_addr, part_size; bool part_found; const char *part_name; + u8 i; switch (dev->target) { case STM32PROG_MMC: @@ -793,10 +802,11 @@ static int init_device(struct stm32prog_data *data, stm32prog_err("unknown device type = %d", dev->target); return -ENODEV; } + /* register partitions with MTDIDS/MTDPARTS or OF fallback */ + mtd_probe_devices(); get_mtd_by_target(mtd_id, dev->target, dev->dev_id); log_debug("%s\n", mtd_id); - mtdparts_init(); mtd = get_mtd_device_nm(mtd_id); if (IS_ERR(mtd)) { stm32prog_err("MTD device %s not found", mtd_id); @@ -943,25 +953,23 @@ static int init_device(struct stm32prog_data *data, } if (IS_ENABLED(CONFIG_MTD) && mtd) { - char mtd_part_id[32]; - struct part_info *mtd_part; - struct mtd_device *mtd_dev; - u8 part_num; - - sprintf(mtd_part_id, "%s,%d", mtd_id, - part->part_id - 1); - ret = find_dev_and_part(mtd_part_id, &mtd_dev, - &part_num, &mtd_part); - if (ret != 0) { - stm32prog_err("%s (0x%x): Invalid MTD partition %s", - part->name, part->id, - mtd_part_id); + i = 0; + list_for_each_entry(partition, &mtd->partitions, node) { + if ((part->part_id - 1) == i) { + part_found = true; + break; + } + i++; + } + if (part_found) { + part_addr = partition->offset; + part_size = partition->size; + part_name = partition->name; + } else { + stm32prog_err("%s (0x%x):Couldn't find part %d on device mtd %s", + part->name, part->id, part->part_id, mtd_id); return -ENODEV; } - part_addr = mtd_part->offset; - part_size = mtd_part->size; - part_name = mtd_part->name; - part_found = true; } /* no partition for this device */ @@ -999,9 +1007,6 @@ static int treat_partition_list(struct stm32prog_data *data) INIT_LIST_HEAD(&data->dev[j].part_list); } -#ifdef CONFIG_STM32MP15x_STM32IMAGE - data->tee_detected = false; -#endif data->fsbl_nor_detected = false; for (i = 0; i < data->part_nb; i++) { part = &data->part_array[i]; @@ -1053,14 +1058,6 @@ static int treat_partition_list(struct stm32prog_data *data) !strncmp(part->name, "fsbl", 4)) data->fsbl_nor_detected = true; /* fallthrough */ - case STM32PROG_NAND: - case STM32PROG_SPI_NAND: -#ifdef CONFIG_STM32MP15x_STM32IMAGE - if (!data->tee_detected && - !strncmp(part->name, "tee", 3)) - data->tee_detected = true; - break; -#endif default: break; } @@ -1130,10 +1127,20 @@ static int create_gpt_partitions(struct stm32prog_data *data) case PART_BINARY: type_str = LINUX_RESERVED_UUID; break; + case PART_ENV: + type_str = "u-boot-env"; + break; case PART_FIP: type_str = FIP_TYPE_UUID; break; - default: + case PART_FWU_MDATA: + type_str = FWU_MDATA_UUID; + break; + case PART_ESP: + /* EFI System Partition */ + type_str = "system"; + break; + default: /* PART_FILESYSTEM or PART_SYSTEM for distro */ type_str = "linux"; break; } @@ -1439,8 +1446,11 @@ int stm32prog_otp_write(struct stm32prog_data *data, u32 offset, u8 *buffer, if (!data->otp_part) { data->otp_part = memalign(CONFIG_SYS_CACHELINE_SIZE, otp_size); - if (!data->otp_part) + if (!data->otp_part) { + stm32prog_err("OTP write issue %d", -ENOMEM); + return -ENOMEM; + } } if (!offset) @@ -1503,6 +1513,8 @@ int stm32prog_otp_read(struct stm32prog_data *data, u32 offset, u8 *buffer, memcpy(buffer, (void *)((uintptr_t)data->otp_part + offset), *size); end_otp_read: + if (result) + stm32prog_err("OTP read issue %d", result); log_debug("%s: result %i\n", __func__, result); return result; @@ -1556,6 +1568,8 @@ int stm32prog_otp_start(struct stm32prog_data *data) free(data->otp_part); data->otp_part = NULL; + if (result) + stm32prog_err("OTP write issue %d", result); log_debug("%s: result %i\n", __func__, result); return result; diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h index 58f4b96..feba295 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h @@ -96,12 +96,20 @@ struct stm32_header_v2 { u8 extension_padding[376]; }; -/* partition type in flashlayout file */ +/* + * partition type in flashlayout file + * SYSTEM = linux partition, bootable + * FILESYSTEM = linux partition + * ESP = EFI system partition + */ enum stm32prog_part_type { PART_BINARY, PART_FIP, + PART_FWU_MDATA, + PART_ENV, PART_SYSTEM, PART_FILESYSTEM, + PART_ESP, RAW_IMAGE, }; @@ -149,9 +157,6 @@ struct stm32prog_data { struct stm32prog_dev_t dev[STM32PROG_MAX_DEV]; /* array of device */ int part_nb; /* nb of partition */ struct stm32prog_part_t *part_array; /* array of partition */ -#ifdef CONFIG_STM32MP15x_STM32IMAGE - bool tee_detected; -#endif bool fsbl_nor_detected; /* command internal information */ diff --git a/arch/arm/mach-stm32mp/ecdsa_romapi.c b/arch/arm/mach-stm32mp/ecdsa_romapi.c index 12b42b9..93c561c 100644 --- a/arch/arm/mach-stm32mp/ecdsa_romapi.c +++ b/arch/arm/mach-stm32mp/ecdsa_romapi.c @@ -5,6 +5,7 @@ * Implements ECDSA signature verification via the STM32MP ROM. */ #include <asm/system.h> +#include <asm/arch/sys_proto.h> #include <dm/device.h> #include <linux/types.h> #include <u-boot/ecdsa.h> diff --git a/arch/arm/mach-stm32mp/include/mach/stm32.h b/arch/arm/mach-stm32mp/include/mach/stm32.h index c85ae6a..1cdc5e3 100644 --- a/arch/arm/mach-stm32mp/include/mach/stm32.h +++ b/arch/arm/mach-stm32mp/include/mach/stm32.h @@ -21,8 +21,10 @@ #define STM32_DBGMCU_BASE 0x50081000 #endif #define STM32_FMC2_BASE 0x58002000 +#define STM32_IWDG2_BASE 0x5A002000 #define STM32_DDRCTRL_BASE 0x5A003000 #define STM32_DDRPHYC_BASE 0x5A004000 +#define STM32_IWDG1_BASE 0x5C003000 #define STM32_TZC_BASE 0x5C006000 #define STM32_ETZPC_BASE 0x5C007000 #define STM32_STGEN_BASE 0x5C008000 diff --git a/arch/arm/mach-stm32mp/include/mach/stm32prog.h b/arch/arm/mach-stm32mp/include/mach/stm32prog.h index 99be4e1..23d1adf 100644 --- a/arch/arm/mach-stm32mp/include/mach/stm32prog.h +++ b/arch/arm/mach-stm32mp/include/mach/stm32prog.h @@ -11,8 +11,4 @@ int stm32prog_read_medium_virt(struct dfu_entity *dfu, u64 offset, void *buf, long *len); int stm32prog_get_medium_size_virt(struct dfu_entity *dfu, u64 *size); -#ifdef CONFIG_STM32MP15x_STM32IMAGE -bool stm32prog_get_tee_partitions(void); -#endif - bool stm32prog_get_fsbl_nor(void); diff --git a/arch/arm/mach-stm32mp/include/mach/sys_proto.h b/arch/arm/mach-stm32mp/include/mach/sys_proto.h index 0d39b67..83fb32a 100644 --- a/arch/arm/mach-stm32mp/include/mach/sys_proto.h +++ b/arch/arm/mach-stm32mp/include/mach/sys_proto.h @@ -44,6 +44,7 @@ u32 get_cpu_dev(void); #define CPU_REV1_2 0x1003 #define CPU_REV2 0x2000 #define CPU_REV2_1 0x2001 +#define CPU_REV2_2 0x2003 /* return Silicon revision = REV_ID[15:0] of Device Version */ u32 get_cpu_rev(void); diff --git a/arch/arm/mach-stm32mp/psci.c b/arch/arm/mach-stm32mp/psci.c index 1e69673..39b5200 100644 --- a/arch/arm/mach-stm32mp/psci.c +++ b/arch/arm/mach-stm32mp/psci.c @@ -161,6 +161,12 @@ #define RCC_MP_GRSTCSETR_MPUP0RST BIT(4) #define RCC_MP_GRSTCSETR_MPUP1RST BIT(5) +/* IWDG */ +#define IWDG_KR 0x00 +#define IWDG_KR_RELOAD_KEY 0xaaaa +#define IWDG_EWCR 0x14 +#define IWDG_EWCR_EWIC BIT(14) + #define STM32MP1_PSCI_NR_CPUS 2 #if STM32MP1_PSCI_NR_CPUS > CONFIG_ARMV7_PSCI_NR_CPUS #error "invalid value for CONFIG_ARMV7_PSCI_NR_CPUS" @@ -696,7 +702,18 @@ void __secure psci_system_suspend(u32 __always_unused function_id, u32 ep, u32 context_id) { u32 saved_mcudivr, saved_pll3cr, saved_pll4cr, saved_mssckselr; + u32 gicd_addr = stm32mp_get_gicd_base_address(); + bool iwdg1_wake = false; + bool iwdg2_wake = false; + bool other_wake = false; u32 saved_pwrctl, reg; + u32 gic_enabled[8]; + u32 irqs; + int i; + + /* Cache enable mask of all 256 SPI */ + for (i = 0; i < ARRAY_SIZE(gic_enabled); i++) + gic_enabled[i] = readl(gicd_addr + GICD_ISENABLERn + 0x4 + 4 * i); /* Disable IO compensation */ @@ -725,11 +742,57 @@ void __secure psci_system_suspend(u32 __always_unused function_id, setbits_le32(STM32_PWR_BASE + PWR_CR3, PWR_CR3_DDRSREN); writel(0x3, STM32_RCC_BASE + RCC_MP_SREQSETR); - /* Zzz, enter stop mode */ - asm volatile( - "isb\n" - "dsb\n" - "wfi\n"); + /* Ping the IWDG before entering suspend */ + iwdg1_wake = !!(gic_enabled[4] & BIT(22)); /* SPI 150 */ + iwdg2_wake = !!(gic_enabled[4] & BIT(23)); /* SPI 151 */ + + for (;;) { + /* Ping IWDG1 and ACK pretimer IRQ */ + if (iwdg1_wake) { + writel(IWDG_KR_RELOAD_KEY, STM32_IWDG1_BASE + IWDG_KR); + writel(IWDG_EWCR_EWIC, STM32_IWDG1_BASE + IWDG_EWCR); + } + + /* Ping IWDG2 and ACK pretimer IRQ */ + if (iwdg2_wake) { + writel(IWDG_KR_RELOAD_KEY, STM32_IWDG2_BASE + IWDG_KR); + writel(IWDG_EWCR_EWIC, STM32_IWDG2_BASE + IWDG_EWCR); + } + + iwdg1_wake = false; + iwdg2_wake = false; + + /* Zzz, enter stop mode */ + asm volatile( + "isb\n" + "dsb\n" + "wfi\n"); + + /* Determine the wake up source */ + for (i = 0; i < ARRAY_SIZE(gic_enabled); i++) { + irqs = readl(gicd_addr + GICR_IGROUPMODRn + 0x4 + 4 * i); + irqs &= gic_enabled[i]; + if (!irqs) + continue; + + /* Test whether IWDG pretimeout triggered the wake up. */ + if (i == 4) { /* SPI Num 128..159 */ + iwdg1_wake = !!(irqs & BIT(22)); /* SPI 150 */ + iwdg2_wake = !!(irqs & BIT(23)); /* SPI 151 */ + irqs &= ~(BIT(22) | BIT(23)); + } + + /* Test whether there is any other wake up trigger. */ + if (irqs) { + other_wake = true; + break; + } + } + + /* Other wake up triggers pending, let OS deal with all of it. */ + if (other_wake) + break; + } writel(0x3, STM32_RCC_BASE + RCC_MP_SREQCLRR); ddr_sw_self_refresh_exit(); diff --git a/arch/arm/mach-stm32mp/stm32mp15x.c b/arch/arm/mach-stm32mp/stm32mp15x.c index 660c907..afc56b0 100644 --- a/arch/arm/mach-stm32mp/stm32mp15x.c +++ b/arch/arm/mach-stm32mp/stm32mp15x.c @@ -266,7 +266,7 @@ static const char * const soc_type[] = { }; static const char * const soc_pkg[] = { "??", "AD", "AC", "AB", "AA" }; -static const char * const soc_rev[] = { "?", "A", "B", "Z" }; +static const char * const soc_rev[] = { "?", "A", "B", "Z", "Y"}; static void get_cpu_string_offsets(unsigned int *type, unsigned int *pkg, unsigned int *rev) @@ -307,6 +307,9 @@ static void get_cpu_string_offsets(unsigned int *type, unsigned int *pkg, case CPU_REV2_1: *rev = 3; break; + case CPU_REV2_2: + *rev = 4; + break; default: *rev = 0; break; diff --git a/board/dhelectronics/dh_stm32mp1/board.c b/board/dhelectronics/dh_stm32mp1/board.c index 8d8104a..f9cfabe 100644 --- a/board/dhelectronics/dh_stm32mp1/board.c +++ b/board/dhelectronics/dh_stm32mp1/board.c @@ -184,9 +184,9 @@ int checkboard(void) } #ifdef CONFIG_BOARD_EARLY_INIT_F -static u8 brdcode __section("data"); -static u8 ddr3code __section("data"); -static u8 somcode __section("data"); +static u8 brdcode __section(".data"); +static u8 ddr3code __section(".data"); +static u8 somcode __section(".data"); static u32 opp_voltage_mv __section(".data"); static void board_get_coding_straps(void) diff --git a/board/st/common/Kconfig b/board/st/common/Kconfig index aba3590..c1c254d 100644 --- a/board/st/common/Kconfig +++ b/board/st/common/Kconfig @@ -6,72 +6,6 @@ config CMD_STBOARD This compile the stboard command to read and write the board in the OTP. -config MTDPARTS_NAND0_BOOT - string "mtd boot partitions for nand0" - default "2m(fsbl),2m(ssbl1),2m(ssbl2)" if STM32MP15x_STM32IMAGE || \ - !TFABOOT - default "2m(fsbl),4m(fip1),4m(fip2)" - depends on SYS_MTDPARTS_RUNTIME && ARCH_STM32MP - help - This define the partitions of nand0 used to build mtparts dynamically - for boot from nand0. - Each partition need to be aligned with the device erase block size, - 512KB is the max size for the NAND supported by stm32mp1 platform. - The fsbl partition support multiple copy of the same binary, one by - erase block. - -config MTDPARTS_NAND0_TEE - string "mtd tee partitions for nand0" - default "512k(teeh),512k(teed),512k(teex)" - depends on SYS_MTDPARTS_RUNTIME && ARCH_STM32MP && STM32MP15x_STM32IMAGE - help - This define the tee partitions added in mtparts dynamically - when tee is supported with boot from nand0. - Each partition need to be aligned with the device erase block size, - 512KB is the max size for the NAND supported by stm32mp1 platform. - -config MTDPARTS_NOR0_BOOT - string "mtd boot partitions for nor0" - default "256k(fsbl1),256k(fsbl2),2m(ssbl),512k(u-boot-env)" if STM32MP15x_STM32IMAGE || \ - !TFABOOT - default "256k(fsbl1),256k(fsbl2),4m(fip),512k(u-boot-env)" - depends on SYS_MTDPARTS_RUNTIME && ARCH_STM32MP - help - This define the partitions of nand0 used to build mtparts dynamically - for boot from nor0. - Each partition need to be aligned with the device erase block size, - with 256KB we support all the NOR. - U-Boot env partition (512kB) use 2 erase block for redundancy. - -config MTDPARTS_NOR0_TEE - string "mtd tee partitions for nor0" - default "256k(teeh),512k(teed),256k(teex)" - depends on SYS_MTDPARTS_RUNTIME && ARCH_STM32MP && STM32MP15x_STM32IMAGE - help - This define the tee partitions added in mtparts dynamically - when tee is supported with boot from nor0. - -config MTDPARTS_SPINAND0_BOOT - string "mtd boot partitions for spi-nand0" - default "2m(fsbl),2m(ssbl1),2m(ssbl2)" if STM32MP15x_STM32IMAGE || !TFABOOT - default "2m(fsbl),4m(fip1),4m(fip2)" - depends on SYS_MTDPARTS_RUNTIME && ARCH_STM32MP - help - This define the partitions of nand0 used to build mtparts dynamically - for boot from spi-nand0, - 512KB is the max size for the NAND supported by stm32mp1 platform. - The fsbl partition support multiple copy of the same binary, one by - erase block. - -config MTDPARTS_SPINAND0_TEE - string "mtd tee partitions for spi-nand0" - default "512k(teeh),512k(teed),512k(teex)" - depends on SYS_MTDPARTS_RUNTIME && ARCH_STM32MP && STM32MP15x_STM32IMAGE - help - This define the tee partitions added in mtparts dynamically - when tee is supported with boot from spi-nand0, - 512KB is the max size for the NAND supported by stm32mp1 platform. - config DFU_ALT_RAM0 string "dfu for ram0" default "uImage ram 0xc2000000 0x2000000;devicetree.dtb ram 0xc4000000 0x100000;uramdisk.image.gz ram 0xc4400000 0x10000000" diff --git a/board/st/common/Makefile b/board/st/common/Makefile index 65bbebd..c960829 100644 --- a/board/st/common/Makefile +++ b/board/st/common/Makefile @@ -7,7 +7,6 @@ obj-$(CONFIG_CMD_STBOARD) += cmd_stboard.o obj-$(CONFIG_PMIC_STPMIC1) += stpmic1.o ifeq ($(CONFIG_ARCH_STM32MP),y) -obj-$(CONFIG_SYS_MTDPARTS_RUNTIME) += stm32mp_mtdparts.o obj-$(CONFIG_SET_DFU_ALT_INFO) += stm32mp_dfu.o endif diff --git a/board/st/common/stm32mp_mtdparts.c b/board/st/common/stm32mp_mtdparts.c deleted file mode 100644 index 67a56a2..0000000 --- a/board/st/common/stm32mp_mtdparts.c +++ /dev/null @@ -1,177 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause -/* - * Copyright (C) 2020, STMicroelectronics - All Rights Reserved - */ - -#include <common.h> -#include <dfu.h> -#include <dm.h> -#include <env.h> -#include <env_internal.h> -#include <log.h> -#include <mtd.h> -#include <mtd_node.h> -#ifdef CONFIG_STM32MP15x_STM32IMAGE -#include <tee.h> -#endif -#include <asm/arch/stm32prog.h> -#include <asm/arch/sys_proto.h> -#include <asm/global_data.h> - -#define MTDPARTS_LEN 256 -#define MTDIDS_LEN 128 - -/* - * Get a global data pointer - */ -DECLARE_GLOBAL_DATA_PTR; - -/** - * update the variables "mtdids" and "mtdparts" with boot, tee and user strings - */ -static void board_set_mtdparts(const char *dev, - char *mtdids, - char *mtdparts, - const char *boot, -#ifdef CONFIG_STM32MP15x_STM32IMAGE - const char *tee, -#endif - const char *user) -{ - /* mtdids: "<dev>=<dev>, ...." */ - if (mtdids[0] != '\0') - strcat(mtdids, ","); - strcat(mtdids, dev); - strcat(mtdids, "="); - strcat(mtdids, dev); - - /* mtdparts: "mtdparts=<dev>:<mtdparts_<dev>>;..." */ - if (mtdparts[0] != '\0') - strncat(mtdparts, ";", MTDPARTS_LEN); - else - strcat(mtdparts, "mtdparts="); - - strncat(mtdparts, dev, MTDPARTS_LEN); - strncat(mtdparts, ":", MTDPARTS_LEN); - - if (boot) { - strncat(mtdparts, boot, MTDPARTS_LEN); - strncat(mtdparts, ",", MTDPARTS_LEN); - } - -#ifdef CONFIG_STM32MP15x_STM32IMAGE - if (tee) { - strncat(mtdparts, tee, MTDPARTS_LEN); - strncat(mtdparts, ",", MTDPARTS_LEN); - } -#endif - - strncat(mtdparts, user, MTDPARTS_LEN); -} - -void board_mtdparts_default(const char **mtdids, const char **mtdparts) -{ - struct mtd_info *mtd; - struct udevice *dev; - static char parts[3 * MTDPARTS_LEN + 1]; - static char ids[MTDIDS_LEN + 1]; - static bool mtd_initialized; - bool nor, nand, spinand, serial; -#ifdef CONFIG_STM32MP15x_STM32IMAGE - bool tee = false; -#endif - - if (mtd_initialized) { - *mtdids = ids; - *mtdparts = parts; - return; - } - - nor = false; - nand = false; - spinand = false; - serial = false; - - switch (get_bootmode() & TAMP_BOOT_DEVICE_MASK) { - case BOOT_SERIAL_UART: - case BOOT_SERIAL_USB: - serial = true; - if (IS_ENABLED(CONFIG_CMD_STM32PROG)) { -#ifdef CONFIG_STM32MP15x_STM32IMAGE - tee = stm32prog_get_tee_partitions(); -#endif - nor = stm32prog_get_fsbl_nor(); - } - nand = true; - spinand = true; - break; - case BOOT_FLASH_NAND: - nand = true; - break; - case BOOT_FLASH_SPINAND: - spinand = true; - break; - case BOOT_FLASH_NOR: - nor = true; - break; - default: - break; - } - -#ifdef CONFIG_STM32MP15x_STM32IMAGE - if (!serial && tee_find_device(NULL, NULL, NULL, NULL)) - tee = true; -#endif - - memset(parts, 0, sizeof(parts)); - memset(ids, 0, sizeof(ids)); - - /* probe all MTD devices */ - for (uclass_first_device(UCLASS_MTD, &dev); - dev; - uclass_next_device(&dev)) { - log_debug("mtd device = %s\n", dev->name); - } - - if (nand) { - mtd = get_mtd_device_nm("nand0"); - if (!IS_ERR_OR_NULL(mtd)) { - board_set_mtdparts("nand0", ids, parts, - CONFIG_MTDPARTS_NAND0_BOOT, -#ifdef CONFIG_STM32MP15x_STM32IMAGE - !nor && tee ? CONFIG_MTDPARTS_NAND0_TEE : NULL, -#endif - "-(UBI)"); - put_mtd_device(mtd); - } - } - - if (spinand) { - mtd = get_mtd_device_nm("spi-nand0"); - if (!IS_ERR_OR_NULL(mtd)) { - board_set_mtdparts("spi-nand0", ids, parts, - CONFIG_MTDPARTS_SPINAND0_BOOT, -#ifdef CONFIG_STM32MP15x_STM32IMAGE - !nor && tee ? CONFIG_MTDPARTS_SPINAND0_TEE : NULL, -#endif - "-(UBI)"); - put_mtd_device(mtd); - } - } - - if (nor) { - if (!uclass_get_device(UCLASS_SPI_FLASH, 0, &dev)) { - board_set_mtdparts("nor0", ids, parts, - CONFIG_MTDPARTS_NOR0_BOOT, -#ifdef CONFIG_STM32MP15x_STM32IMAGE - tee ? CONFIG_MTDPARTS_NOR0_TEE : NULL, -#endif - "-(nor_user)"); - } - } - - mtd_initialized = true; - *mtdids = ids; - *mtdparts = parts; - log_debug("mtdids=%s & mtdparts=%s\n", ids, parts); -} diff --git a/board/st/stm32mp1/stm32mp1.c b/board/st/stm32mp1/stm32mp1.c index 5b28ccd..3205a31 100644 --- a/board/st/stm32mp1/stm32mp1.c +++ b/board/st/stm32mp1/stm32mp1.c @@ -25,7 +25,6 @@ #include <log.h> #include <malloc.h> #include <misc.h> -#include <mtd_node.h> #include <net.h> #include <netdev.h> #include <phy.h> @@ -915,20 +914,7 @@ int mmc_get_env_dev(void) #if defined(CONFIG_OF_BOARD_SETUP) int ft_board_setup(void *blob, struct bd_info *bd) { - static const struct node_info nodes[] = { - { "jedec,spi-nor", MTD_DEV_TYPE_NOR, }, - { "spi-nand", MTD_DEV_TYPE_SPINAND}, - { "st,stm32mp15-fmc2", MTD_DEV_TYPE_NAND, }, - { "st,stm32mp1-fmc2-nfc", MTD_DEV_TYPE_NAND, }, - }; - char *boot_device; - - /* Check the boot-source and don't update MTD for serial or usb boot */ - boot_device = env_get("boot_device"); - if (!boot_device || - (strcmp(boot_device, "serial") && strcmp(boot_device, "usb"))) - if (IS_ENABLED(CONFIG_FDT_FIXUP_PARTITIONS)) - fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes)); + fdt_copy_fixed_partitions(blob); if (IS_ENABLED(CONFIG_FDT_SIMPLEFB)) fdt_simplefb_enable_and_mem_rsv(blob); diff --git a/common/fdt_support.c b/common/fdt_support.c index 2053fe3..5e49078 100644 --- a/common/fdt_support.c +++ b/common/fdt_support.c @@ -13,6 +13,7 @@ #include <mapmem.h> #include <net.h> #include <stdio_dev.h> +#include <dm/ofnode.h> #include <linux/ctype.h> #include <linux/types.h> #include <asm/global_data.h> @@ -1050,6 +1051,79 @@ void fdt_fixup_mtdparts(void *blob, const struct node_info *node_info, } #endif +int fdt_copy_fixed_partitions(void *blob) +{ + ofnode node, subnode; + int off, suboff, res; + char path[256]; + int address_cells, size_cells; + u8 i, j, child_count; + + node = ofnode_by_compatible(ofnode_null(), "fixed-partitions"); + while (ofnode_valid(node)) { + /* copy the U-Boot fixed partition */ + address_cells = ofnode_read_simple_addr_cells(node); + size_cells = ofnode_read_simple_size_cells(node); + + res = ofnode_get_path(ofnode_get_parent(node), path, sizeof(path)); + if (res) + return res; + + off = fdt_path_offset(blob, path); + if (off < 0) + return -ENODEV; + + off = fdt_find_or_add_subnode(blob, off, "partitions"); + res = fdt_setprop_string(blob, off, "compatible", "fixed-partitions"); + if (res) + return res; + + res = fdt_setprop_u32(blob, off, "#address-cells", address_cells); + if (res) + return res; + + res = fdt_setprop_u32(blob, off, "#size-cells", size_cells); + if (res) + return res; + + /* + * parse partition in reverse order as fdt_find_or_add_subnode() only + * insert the new node after the parent's properties + */ + child_count = ofnode_get_child_count(node); + for (i = child_count; i > 0 ; i--) { + subnode = ofnode_first_subnode(node); + if (!ofnode_valid(subnode)) + break; + + for (j = 0; (j < i - 1); j++) + subnode = ofnode_next_subnode(subnode); + + if (!ofnode_valid(subnode)) + break; + + const u32 *reg; + int len; + + suboff = fdt_find_or_add_subnode(blob, off, ofnode_get_name(subnode)); + res = fdt_setprop_string(blob, suboff, "label", + ofnode_read_string(subnode, "label")); + if (res) + return res; + + reg = ofnode_get_property(subnode, "reg", &len); + res = fdt_setprop(blob, suboff, "reg", reg, len); + if (res) + return res; + } + + /* go to next fixed-partitions node */ + node = ofnode_by_compatible(node, "fixed-partitions"); + } + + return 0; +} + void fdt_del_node_and_alias(void *blob, const char *alias) { int off = fdt_path_offset(blob, alias); @@ -1065,7 +1139,6 @@ void fdt_del_node_and_alias(void *blob, const char *alias) /* Max address size we deal with */ #define OF_MAX_ADDR_CELLS 4 -#define OF_BAD_ADDR FDT_ADDR_T_NONE #define OF_CHECK_COUNTS(na, ns) ((na) > 0 && (na) <= OF_MAX_ADDR_CELLS && \ (ns) > 0) diff --git a/configs/stm32mp13_defconfig b/configs/stm32mp13_defconfig index b076573..82b6274 100644 --- a/configs/stm32mp13_defconfig +++ b/configs/stm32mp13_defconfig @@ -7,7 +7,7 @@ CONFIG_ENV_OFFSET=0x900000 CONFIG_DEFAULT_DEVICE_TREE="stm32mp135f-dk" CONFIG_SYS_PROMPT="STM32MP> " CONFIG_STM32MP13x=y -CONFIG_DDR_CACHEABLE_SIZE=0x10000000 +CONFIG_DDR_CACHEABLE_SIZE=0x8000000 CONFIG_CMD_STM32KEY=y CONFIG_TARGET_ST_STM32MP13x=y CONFIG_ENV_OFFSET_REDUND=0x940000 @@ -39,7 +39,6 @@ CONFIG_CMD_RNG=y CONFIG_CMD_TIMER=y CONFIG_CMD_REGULATOR=y CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_MTDPARTS=y CONFIG_CMD_LOG=y CONFIG_CMD_UBI=y CONFIG_OF_LIVE=y @@ -59,7 +58,6 @@ CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_STM32_SDMMC2=y CONFIG_MTD=y CONFIG_DM_MTD=y -CONFIG_SYS_MTDPARTS_RUNTIME=y CONFIG_PINCONF=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y @@ -75,7 +73,6 @@ CONFIG_TEE=y CONFIG_OPTEE=y # CONFIG_OPTEE_TA_AVB is not set CONFIG_ERRNO_STR=y -CONFIG_FDT_FIXUP_PARTITIONS=y # CONFIG_LMB_USE_MAX_REGIONS is not set CONFIG_LMB_MEMORY_REGIONS=2 CONFIG_LMB_RESERVED_REGIONS=16 diff --git a/configs/stm32mp15_basic_defconfig b/configs/stm32mp15_basic_defconfig index 13355eb..424ae5d 100644 --- a/configs/stm32mp15_basic_defconfig +++ b/configs/stm32mp15_basic_defconfig @@ -75,7 +75,6 @@ CONFIG_CMD_TIMER=y CONFIG_CMD_PMIC=y CONFIG_CMD_REGULATOR=y CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_MTDPARTS=y CONFIG_CMD_LOG=y CONFIG_CMD_UBI=y # CONFIG_SPL_DOS_PARTITION is not set @@ -102,7 +101,6 @@ CONFIG_SET_DFU_ALT_INFO=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0xC0000000 CONFIG_FASTBOOT_BUF_SIZE=0x02000000 -CONFIG_FASTBOOT_USB_DEV=1 CONFIG_FASTBOOT_FLASH=y CONFIG_FASTBOOT_FLASH_MMC_DEV=1 CONFIG_FASTBOOT_MMC_BOOT_SUPPORT=y @@ -110,7 +108,6 @@ CONFIG_FASTBOOT_MMC_BOOT1_NAME="mmc1boot0" CONFIG_FASTBOOT_MMC_BOOT2_NAME="mmc1boot1" CONFIG_FASTBOOT_MMC_USER_SUPPORT=y CONFIG_FASTBOOT_MMC_USER_NAME="mmc1" -CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_FASTBOOT_CMD_OEM_PARTCONF=y CONFIG_FASTBOOT_CMD_OEM_BOOTBUS=y CONFIG_GPIO_HOG=y @@ -125,7 +122,6 @@ CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_STM32_SDMMC2=y CONFIG_MTD=y CONFIG_DM_MTD=y -CONFIG_SYS_MTDPARTS_RUNTIME=y CONFIG_MTD_RAW_NAND=y CONFIG_NAND_STM32_FMC2=y CONFIG_SYS_NAND_ONFI_DETECTION=y @@ -189,7 +185,6 @@ CONFIG_WDT=y CONFIG_WDT_STM32MP=y # CONFIG_BINMAN_FDT is not set CONFIG_ERRNO_STR=y -CONFIG_FDT_FIXUP_PARTITIONS=y # CONFIG_LMB_USE_MAX_REGIONS is not set CONFIG_LMB_MEMORY_REGIONS=2 CONFIG_LMB_RESERVED_REGIONS=16 diff --git a/configs/stm32mp15_defconfig b/configs/stm32mp15_defconfig index 2669aae..2700b5c 100644 --- a/configs/stm32mp15_defconfig +++ b/configs/stm32mp15_defconfig @@ -3,15 +3,15 @@ CONFIG_ARCH_STM32MP=y CONFIG_TFABOOT=y CONFIG_SYS_MALLOC_F_LEN=0x80000 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc0100000 -CONFIG_ENV_OFFSET=0x480000 +CONFIG_ENV_OFFSET=0x900000 CONFIG_ENV_SECT_SIZE=0x40000 CONFIG_DEFAULT_DEVICE_TREE="stm32mp157c-ev1" CONFIG_SYS_PROMPT="STM32MP> " -CONFIG_DDR_CACHEABLE_SIZE=0x10000000 +CONFIG_DDR_CACHEABLE_SIZE=0x8000000 CONFIG_CMD_STM32KEY=y CONFIG_TYPEC_STUSB160X=y CONFIG_TARGET_ST_STM32MP15x=y -CONFIG_ENV_OFFSET_REDUND=0x4C0000 +CONFIG_ENV_OFFSET_REDUND=0x940000 CONFIG_CMD_STM32PROG=y # CONFIG_ARMV7_NONSEC is not set CONFIG_SYS_LOAD_ADDR=0xc2000000 @@ -51,7 +51,6 @@ CONFIG_CMD_TIMER=y CONFIG_CMD_PMIC=y CONFIG_CMD_REGULATOR=y CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_MTDPARTS=y CONFIG_CMD_LOG=y CONFIG_CMD_UBI=y CONFIG_OF_LIVE=y @@ -75,7 +74,6 @@ CONFIG_SET_DFU_ALT_INFO=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0xC0000000 CONFIG_FASTBOOT_BUF_SIZE=0x02000000 -CONFIG_FASTBOOT_USB_DEV=1 CONFIG_FASTBOOT_FLASH=y CONFIG_FASTBOOT_FLASH_MMC_DEV=1 CONFIG_FASTBOOT_MMC_BOOT_SUPPORT=y @@ -83,7 +81,6 @@ CONFIG_FASTBOOT_MMC_BOOT1_NAME="mmc1boot0" CONFIG_FASTBOOT_MMC_BOOT2_NAME="mmc1boot1" CONFIG_FASTBOOT_MMC_USER_SUPPORT=y CONFIG_FASTBOOT_MMC_USER_NAME="mmc1" -CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_FASTBOOT_CMD_OEM_PARTCONF=y CONFIG_FASTBOOT_CMD_OEM_BOOTBUS=y CONFIG_GPIO_HOG=y @@ -98,7 +95,6 @@ CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_STM32_SDMMC2=y CONFIG_MTD=y CONFIG_DM_MTD=y -CONFIG_SYS_MTDPARTS_RUNTIME=y CONFIG_MTD_RAW_NAND=y CONFIG_NAND_STM32_FMC2=y CONFIG_SYS_NAND_ONFI_DETECTION=y @@ -165,7 +161,6 @@ CONFIG_WDT=y CONFIG_WDT_STM32MP=y # CONFIG_BINMAN_FDT is not set CONFIG_ERRNO_STR=y -CONFIG_FDT_FIXUP_PARTITIONS=y # CONFIG_LMB_USE_MAX_REGIONS is not set CONFIG_LMB_MEMORY_REGIONS=2 CONFIG_LMB_RESERVED_REGIONS=16 diff --git a/configs/stm32mp15_dhcom_basic_defconfig b/configs/stm32mp15_dhcom_basic_defconfig index 430d0bc..77f0faf 100644 --- a/configs/stm32mp15_dhcom_basic_defconfig +++ b/configs/stm32mp15_dhcom_basic_defconfig @@ -85,9 +85,6 @@ CONFIG_CMD_PMIC=y CONFIG_CMD_REGULATOR=y CONFIG_CMD_BTRFS=y CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nor0=nor0" -CONFIG_MTDPARTS_DEFAULT="mtdparts=nor0:256k(fsbl1),256k(fsbl2),1408k(uboot),64k(env1),64k(env2)" # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_ISO_PARTITION is not set # CONFIG_SPL_PARTITION_UUIDS is not set diff --git a/configs/stm32mp15_dhcor_basic_defconfig b/configs/stm32mp15_dhcor_basic_defconfig index f23875f..6438ad8 100644 --- a/configs/stm32mp15_dhcor_basic_defconfig +++ b/configs/stm32mp15_dhcor_basic_defconfig @@ -83,13 +83,11 @@ CONFIG_CMD_PMIC=y CONFIG_CMD_REGULATOR=y CONFIG_CMD_BTRFS=y CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nor0=nor0" -CONFIG_MTDPARTS_DEFAULT="mtdparts=nor0:256k(fsbl1),256k(fsbl2),1408k(uboot),64k(env1),64k(env2)" # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_ISO_PARTITION is not set # CONFIG_SPL_PARTITION_UUIDS is not set CONFIG_OF_LIVE=y +CONFIG_OF_LIST="stm32mp15xx-dhcor-avenger96 stm32mp15xx-dhcor-testbench stm32mp15xx-dhcor-drc-compact" CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-names interrupts-extended interrupt-controller \\\#interrupt-cells interrupt-parent dmas dma-names assigned-clocks assigned-clock-rates assigned-clock-parents hwlocks" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y diff --git a/configs/stm32mp15_trusted_defconfig b/configs/stm32mp15_trusted_defconfig index 5f0fb45..5b94e0c 100644 --- a/configs/stm32mp15_trusted_defconfig +++ b/configs/stm32mp15_trusted_defconfig @@ -52,7 +52,6 @@ CONFIG_CMD_TIMER=y CONFIG_CMD_PMIC=y CONFIG_CMD_REGULATOR=y CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_MTDPARTS=y CONFIG_CMD_LOG=y CONFIG_CMD_UBI=y CONFIG_OF_LIVE=y @@ -76,7 +75,6 @@ CONFIG_SET_DFU_ALT_INFO=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0xC0000000 CONFIG_FASTBOOT_BUF_SIZE=0x02000000 -CONFIG_FASTBOOT_USB_DEV=1 CONFIG_FASTBOOT_FLASH=y CONFIG_FASTBOOT_FLASH_MMC_DEV=1 CONFIG_FASTBOOT_MMC_BOOT_SUPPORT=y @@ -84,7 +82,6 @@ CONFIG_FASTBOOT_MMC_BOOT1_NAME="mmc1boot0" CONFIG_FASTBOOT_MMC_BOOT2_NAME="mmc1boot1" CONFIG_FASTBOOT_MMC_USER_SUPPORT=y CONFIG_FASTBOOT_MMC_USER_NAME="mmc1" -CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_FASTBOOT_CMD_OEM_PARTCONF=y CONFIG_FASTBOOT_CMD_OEM_BOOTBUS=y CONFIG_GPIO_HOG=y @@ -99,7 +96,6 @@ CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_STM32_SDMMC2=y CONFIG_MTD=y CONFIG_DM_MTD=y -CONFIG_SYS_MTDPARTS_RUNTIME=y CONFIG_MTD_RAW_NAND=y CONFIG_NAND_STM32_FMC2=y CONFIG_SYS_NAND_ONFI_DETECTION=y @@ -165,7 +161,6 @@ CONFIG_WDT=y CONFIG_WDT_STM32MP=y # CONFIG_BINMAN_FDT is not set CONFIG_ERRNO_STR=y -CONFIG_FDT_FIXUP_PARTITIONS=y # CONFIG_LMB_USE_MAX_REGIONS is not set CONFIG_LMB_MEMORY_REGIONS=2 CONFIG_LMB_RESERVED_REGIONS=16 diff --git a/drivers/dfu/Kconfig b/drivers/dfu/Kconfig index 8d7f13d..c3a0b93 100644 --- a/drivers/dfu/Kconfig +++ b/drivers/dfu/Kconfig @@ -41,7 +41,6 @@ config DFU_MMC config DFU_MTD bool "MTD back end for DFU" depends on DM_MTD - depends on CMD_MTDPARTS help This option enables using DFU to read and write to on any MTD device. diff --git a/drivers/dfu/dfu_mtd.c b/drivers/dfu/dfu_mtd.c index c7075f1..75e2f6a 100644 --- a/drivers/dfu/dfu_mtd.c +++ b/drivers/dfu/dfu_mtd.c @@ -10,7 +10,6 @@ #include <common.h> #include <dfu.h> #include <mtd.h> -#include <jffs2/load_kernel.h> #include <linux/err.h> #include <linux/ctype.h> @@ -275,7 +274,7 @@ int dfu_fill_entity_mtd(struct dfu_entity *dfu, char *devstr, char **argv, int a { char *s; struct mtd_info *mtd; - int ret, part; + int part; mtd = get_mtd_device_nm(devstr); if (IS_ERR_OR_NULL(mtd)) @@ -299,10 +298,9 @@ int dfu_fill_entity_mtd(struct dfu_entity *dfu, char *devstr, char **argv, int a if (*s) return -EINVAL; } else if ((!strcmp(argv[0], "part")) || (!strcmp(argv[0], "partubi"))) { - char mtd_id[32]; - struct mtd_device *mtd_dev; - u8 part_num; - struct part_info *pi; + struct mtd_info *partition; + int partnum = 0; + bool part_found = false; if (argc != 2) return -EINVAL; @@ -313,19 +311,25 @@ int dfu_fill_entity_mtd(struct dfu_entity *dfu, char *devstr, char **argv, int a if (*s) return -EINVAL; - sprintf(mtd_id, "%s,%d", devstr, part - 1); - printf("using id '%s'\n", mtd_id); + /* register partitions with MTDIDS/MTDPARTS or OF fallback */ + mtd_probe_devices(); - mtdparts_init(); - - ret = find_dev_and_part(mtd_id, &mtd_dev, &part_num, &pi); - if (ret != 0) { - printf("Could not locate '%s'\n", mtd_id); + partnum = 0; + list_for_each_entry(partition, &mtd->partitions, node) { + partnum++; + if (partnum == part) { + part_found = true; + break; + } + } + if (!part_found) { + printf("No partition %d in %s\n", part, mtd->name); return -1; } + log_debug("partition %d:%s in %s\n", partnum, partition->name, mtd->name); - dfu->data.mtd.start = pi->offset; - dfu->data.mtd.size = pi->size; + dfu->data.mtd.start = partition->offset; + dfu->data.mtd.size = partition->size; if (!strcmp(argv[0], "partubi")) dfu->data.mtd.ubi = 1; } else { diff --git a/drivers/power/pmic/stpmic1.c b/drivers/power/pmic/stpmic1.c index 2c85410..8701d4f 100644 --- a/drivers/power/pmic/stpmic1.c +++ b/drivers/power/pmic/stpmic1.c @@ -34,7 +34,9 @@ static const struct pmic_child_info stpmic1_children_info[] = { { .prefix = "ldo", .driver = "stpmic1_ldo" }, { .prefix = "buck", .driver = "stpmic1_buck" }, { .prefix = "vref_ddr", .driver = "stpmic1_vref_ddr" }, + { .prefix = "vref-ddr", .driver = "stpmic1_vref_ddr" }, { .prefix = "pwr_sw", .driver = "stpmic1_pwr_sw" }, + { .prefix = "pwr-sw", .driver = "stpmic1_pwr_sw" }, { .prefix = "boost", .driver = "stpmic1_boost" }, { }, }; diff --git a/drivers/serial/serial_stm32.c b/drivers/serial/serial_stm32.c index 2ba92bf..0085113 100644 --- a/drivers/serial/serial_stm32.c +++ b/drivers/serial/serial_stm32.c @@ -18,6 +18,7 @@ #include <dm/device_compat.h> #include <linux/bitops.h> #include <linux/delay.h> +#include <linux/iopoll.h> #include "serial_stm32.h" #include <dm/device_compat.h> @@ -28,6 +29,10 @@ static void _stm32_serial_setbrg(fdt_addr_t base, { bool stm32f4 = uart_info->stm32f4; u32 int_div, mantissa, fraction, oversampling; + u8 uart_enable_bit = uart_info->uart_enable_bit; + + /* BRR register must be set when uart is disabled */ + clrbits_le32(base + CR1_OFFSET(stm32f4), BIT(uart_enable_bit)); int_div = DIV_ROUND_CLOSEST(clock_rate, baudrate); @@ -43,6 +48,8 @@ static void _stm32_serial_setbrg(fdt_addr_t base, fraction = int_div % oversampling; writel(mantissa | fraction, base + BRR_OFFSET(stm32f4)); + + setbits_le32(base + CR1_OFFSET(stm32f4), BIT(uart_enable_bit)); } static int stm32_serial_setbrg(struct udevice *dev, int baudrate) @@ -181,9 +188,12 @@ static int stm32_serial_probe(struct udevice *dev) struct stm32x7_serial_plat *plat = dev_get_plat(dev); struct clk clk; struct reset_ctl reset; + u32 isr; int ret; + bool stm32f4; plat->uart_info = (struct stm32_uart_info *)dev_get_driver_data(dev); + stm32f4 = plat->uart_info->stm32f4; ret = clk_get_by_index(dev, 0, &clk); if (ret < 0) @@ -195,6 +205,17 @@ static int stm32_serial_probe(struct udevice *dev) return ret; } + /* + * before uart initialization, wait for TC bit (Transmission Complete) + * in case there is still chars from previous bootstage to transmit + */ + ret = read_poll_timeout(readl, isr, isr & USART_ISR_TC, 10, 150, + plat->base + ISR_OFFSET(stm32f4)); + if (ret) { + clk_disable(&clk); + return ret; + } + ret = reset_get_by_index(dev, 0, &reset); if (!ret) { reset_assert(&reset); diff --git a/drivers/serial/serial_stm32.h b/drivers/serial/serial_stm32.h index 5bee68f..b7e7a90 100644 --- a/drivers/serial/serial_stm32.h +++ b/drivers/serial/serial_stm32.h @@ -66,6 +66,7 @@ struct stm32x7_serial_plat { #define USART_CR3_OVRDIS BIT(12) #define USART_ISR_TXE BIT(7) +#define USART_ISR_TC BIT(6) #define USART_ISR_RXNE BIT(5) #define USART_ISR_ORE BIT(3) #define USART_ISR_FE BIT(1) diff --git a/include/configs/stm32f746-disco.h b/include/configs/stm32f746-disco.h index 34856d3..9bf01ca 100644 --- a/include/configs/stm32f746-disco.h +++ b/include/configs/stm32f746-disco.h @@ -36,6 +36,4 @@ #define CFG_SYS_UBOOT_BASE (CFG_SYS_FLASH_BASE + \ CONFIG_SPL_PAD_TO) -/* For splashcreen */ - #endif /* __CONFIG_H */ diff --git a/include/configs/stm32mp15_common.h b/include/configs/stm32mp15_common.h index 7db72a1..29a1197 100644 --- a/include/configs/stm32mp15_common.h +++ b/include/configs/stm32mp15_common.h @@ -92,19 +92,6 @@ "run distro_bootcmd;" \ "fi;\0" -#ifdef CONFIG_FASTBOOT_CMD_OEM_FORMAT -/* eMMC default partitions for fastboot command: oem format */ -#define STM32MP_PARTS_DEFAULT \ - "partitions=" \ - "name=ssbl,size=2M;" \ - "name=bootfs,size=64MB,bootable;" \ - "name=vendorfs,size=16M;" \ - "name=rootfs,size=746M;" \ - "name=userfs,size=-\0" -#else -#define STM32MP_PARTS_DEFAULT -#endif - #define STM32MP_EXTRA \ "env_check=if env info -p -d -q; then env save; fi\0" \ "boot_net_usb_start=true\0" @@ -138,7 +125,6 @@ #define CFG_EXTRA_ENV_SETTINGS \ STM32MP_MEM_LAYOUT \ STM32MP_BOOTCMD \ - STM32MP_PARTS_DEFAULT \ BOOTENV \ STM32MP_EXTRA \ STM32MP_BOARD_EXTRA_ENV diff --git a/include/configs/stm32mp15_st_common.h b/include/configs/stm32mp15_st_common.h index 866cd7a..b45982a 100644 --- a/include/configs/stm32mp15_st_common.h +++ b/include/configs/stm32mp15_st_common.h @@ -47,7 +47,6 @@ #define CFG_EXTRA_ENV_SETTINGS \ STM32MP_MEM_LAYOUT \ ST_STM32MP1_BOOTCMD \ - STM32MP_PARTS_DEFAULT \ BOOTENV \ STM32MP_EXTRA \ STM32MP_BOARD_EXTRA_ENV diff --git a/include/dt-bindings/clock/stm32mp13-clks.h b/include/dt-bindings/clock/stm32mp13-clks.h index 799dee5..da4cb75 100644 --- a/include/dt-bindings/clock/stm32mp13-clks.h +++ b/include/dt-bindings/clock/stm32mp13-clks.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-or-later or BSD-3-Clause */ /* - * Copyright (C) STMicroelectronics 2022 - All Rights Reserved + * Copyright (C) STMicroelectronics 2020 - All Rights Reserved * Author: Gabriel Fernandez <gabriel.fernandez@foss.st.com> for STMicroelectronics. */ diff --git a/include/dt-bindings/media/video-interfaces.h b/include/dt-bindings/media/video-interfaces.h new file mode 100644 index 0000000..68ac4e0 --- /dev/null +++ b/include/dt-bindings/media/video-interfaces.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright (C) 2022 Laurent Pinchart <laurent.pinchart@ideasonboard.com> + */ + +#ifndef __DT_BINDINGS_MEDIA_VIDEO_INTERFACES_H__ +#define __DT_BINDINGS_MEDIA_VIDEO_INTERFACES_H__ + +#define MEDIA_BUS_TYPE_CSI2_CPHY 1 +#define MEDIA_BUS_TYPE_CSI1 2 +#define MEDIA_BUS_TYPE_CCP2 3 +#define MEDIA_BUS_TYPE_CSI2_DPHY 4 +#define MEDIA_BUS_TYPE_PARALLEL 5 +#define MEDIA_BUS_TYPE_BT656 6 + +#endif /* __DT_BINDINGS_MEDIA_VIDEO_INTERFACES_H__ */ diff --git a/include/dt-bindings/reset/stm32mp13-resets.h b/include/dt-bindings/reset/stm32mp13-resets.h index 18ccb05..1b83a01 100644 --- a/include/dt-bindings/reset/stm32mp13-resets.h +++ b/include/dt-bindings/reset/stm32mp13-resets.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-or-later or BSD-3-Clause */ /* - * Copyright (C) STMicroelectronics 2022 - All Rights Reserved + * Copyright (C) STMicroelectronics 2018 - All Rights Reserved * Author: Gabriel Fernandez <gabriel.fernandez@foss.st.com> for STMicroelectronics. */ diff --git a/include/fdt_support.h b/include/fdt_support.h index eeb83e6..2cd8366 100644 --- a/include/fdt_support.h +++ b/include/fdt_support.h @@ -256,6 +256,14 @@ static inline void fdt_fixup_mtdparts(void *fdt, } #endif +/** + * copy the fixed-partition nodes from U-Boot device tree to external blob + * + * @param blob FDT blob to update + * Return: 0 if ok, or non-zero on error + */ +int fdt_copy_fixed_partitions(void *blob); + void fdt_del_node_and_alias(void *blob, const char *alias); /** |