diff options
256 files changed, 6152 insertions, 3146 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 13be6b6..3243bd0 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1860,11 +1860,6 @@ config TARGET_TEN64 Support for Traverse Technologies Ten64 board, based on NXP LS1088A. -config TARGET_COLIBRI_PXA270 - bool "Support colibri_pxa270" - select CPU_PXA27X - select GPIO_EXTRA_HEADER - config ARCH_UNIPHIER bool "Socionext UniPhier SoCs" select BOARD_LATE_INIT @@ -2328,7 +2323,6 @@ source "board/seeed/npi_imx6ull/Kconfig" source "board/socionext/developerbox/Kconfig" source "board/st/stv0991/Kconfig" source "board/tcl/sl50/Kconfig" -source "board/toradex/colibri_pxa270/Kconfig" source "board/traverse/ten64/Kconfig" source "board/variscite/dart_6ul/Kconfig" source "board/vscom/baltos/Kconfig" diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index e7b95d7..1032ce4 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -899,7 +899,6 @@ dtb-$(CONFIG_ARCH_IMX8) += \ imx8qm-rom7720-a1.dtb \ fsl-imx8qxp-ai_ml.dtb \ fsl-imx8qxp-colibri.dtb \ - fsl-imx8qxp-apalis.dtb \ fsl-imx8qxp-mek.dtb \ imx8-deneb.dtb \ imx8-giedi.dtb @@ -939,6 +938,8 @@ dtb-$(CONFIG_ARCH_IMX8M) += \ imx8mq-phanbell.dtb \ imx8mp-evk.dtb \ imx8mp-phyboard-pollux-rdk.dtb \ + imx8mp-venice.dtb \ + imx8mp-venice-gw74xx.dtb \ imx8mp-verdin.dtb \ imx8mq-pico-pi.dtb \ imx8mq-kontron-pitx-imx8m.dtb diff --git a/arch/arm/dts/fsl-imx8qxp-apalis-u-boot.dtsi b/arch/arm/dts/fsl-imx8qxp-apalis-u-boot.dtsi deleted file mode 100644 index e41911a..0000000 --- a/arch/arm/dts/fsl-imx8qxp-apalis-u-boot.dtsi +++ /dev/null @@ -1,139 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -/* - * Copyright 2020 Toradex - */ - -&{/imx8qx-pm} { - - u-boot,dm-pre-proper; -}; - -&mu { - u-boot,dm-pre-proper; -}; - -&clk { - u-boot,dm-pre-proper; -}; - -&iomuxc { - u-boot,dm-pre-proper; -}; - -&pd_lsio { - u-boot,dm-pre-proper; -}; - -&pd_lsio_gpio0 { - u-boot,dm-pre-proper; -}; - -&pd_lsio_gpio1 { - u-boot,dm-pre-proper; -}; - -&pd_lsio_gpio2 { - u-boot,dm-pre-proper; -}; - -&pd_lsio_gpio3 { - u-boot,dm-pre-proper; -}; - -&pd_lsio_gpio4 { - u-boot,dm-pre-proper; -}; - -&pd_lsio_gpio5 { - u-boot,dm-pre-proper; -}; - -&pd_lsio_gpio6 { - u-boot,dm-pre-proper; -}; - -&pd_lsio_gpio7 { - u-boot,dm-pre-proper; -}; - -&pd_dma { - u-boot,dm-pre-proper; -}; - -&pd_dma_lpuart0 { - u-boot,dm-pre-proper; -}; - -&pd_dma_lpuart3 { - u-boot,dm-pre-proper; -}; - -&pd_conn { - u-boot,dm-pre-proper; -}; - -&pd_conn_sdch0 { - u-boot,dm-pre-proper; -}; - -&pd_conn_sdch1 { - u-boot,dm-pre-proper; -}; - -&pd_conn_sdch2 { - u-boot,dm-pre-proper; -}; - -&pd_conn_enet0 { - u-boot,dm-pre-proper; -}; - -&gpio0 { - u-boot,dm-pre-proper; -}; - -&gpio1 { - u-boot,dm-pre-proper; -}; - -&gpio2 { - u-boot,dm-pre-proper; -}; - -&gpio3 { - u-boot,dm-pre-proper; -}; - -&gpio4 { - u-boot,dm-pre-proper; -}; - -&gpio5 { - u-boot,dm-pre-proper; -}; - -&gpio6 { - u-boot,dm-pre-proper; -}; - -&gpio7 { - u-boot,dm-pre-proper; -}; - -&lpuart3 { - u-boot,dm-pre-proper; -}; - -&lpuart0 { - u-boot,dm-pre-proper; -}; - -&usdhc1 { - u-boot,dm-pre-proper; - /delete-property/ assigned-clock-parents; -}; - -&usdhc2 { - u-boot,dm-pre-proper; - /delete-property/ assigned-clock-parents; -}; diff --git a/arch/arm/dts/fsl-imx8qxp-apalis.dts b/arch/arm/dts/fsl-imx8qxp-apalis.dts deleted file mode 100644 index 9cb3d3a..0000000 --- a/arch/arm/dts/fsl-imx8qxp-apalis.dts +++ /dev/null @@ -1,278 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -/* - * Copyright 2020 Toradex - */ - -/dts-v1/; - -#include "fsl-imx8qxp.dtsi" -#include "fsl-imx8qxp-apalis-u-boot.dtsi" - -/ { - model = "Toradex Apalis iMX8X"; - compatible = "toradex,apalis-imx8x", "fsl,imx8qxp"; - - chosen { - bootargs = "console=ttyLP1,115200"; - stdout-path = &lpuart1; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_usb_otg1_vbus: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "usb_otg1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 16 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - }; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog0>, <&pinctrl_hog1>, <&pinctrl_reset_moci>; - - apalis-imx8x { - /* Apalis UART1 */ - pinctrl_lpuart1: lpuart1grp { - fsl,pins = < - SC_P_UART1_RX_ADMA_UART1_RX 0x06000020 /* SODIMM 118 */ - SC_P_UART1_TX_ADMA_UART1_TX 0x06000020 /* SODIMM 112 */ - >; - }; - - /* On-module Gigabit Ethernet PHY Micrel KSZ9031 */ - pinctrl_fec1: fec1grp { - fsl,pins = < - SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x14a0 - SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD 0x14a0 - SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000020 - SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 - SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x61 - SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x61 - SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x61 - SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x61 - SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x61 - SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x61 - SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x61 - SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x61 - SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x61 - SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x61 - SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x61 - SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x61 - /* On-module ETH_RESET# */ - SC_P_MIPI_CSI0_MCLK_OUT_LSIO_GPIO3_IO04 0x06000020 - /* On-module ETH_INT# */ - SC_P_ADC_IN2_LSIO_GPIO1_IO12 0x21 - >; - }; - - /* Apalis BKL_ON */ - pinctrl_gpio_bkl_on: gpio-bkl-on { - fsl,pins = < - SC_P_QSPI0A_DQS_LSIO_GPIO3_IO13 0x40 /* SODIMM 286 */ - >; - }; - - pinctrl_hog0: hog0grp { - fsl,pins = < - SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0 - >; - }; - - pinctrl_hog1: hog1grp { - fsl,pins = < - /* Apalis USBO1_EN */ - SC_P_QSPI0A_SCLK_LSIO_GPIO3_IO16 0x41 /* SODIMM 274 */ - >; - }; - - /* Apalis RESET_MOCI# */ - pinctrl_reset_moci: gpioresetmocigrp { - fsl,pins = < - SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 0x21 - >; - }; - - /* On-module eMMC */ - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 - SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x21 - SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x21 - SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x21 - SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x21 - SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x21 - SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x21 - SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x21 - SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x21 - SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x21 - SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x41 - SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x21 - >; - }; - - pinctrl_usdhc1_100mhz: usdhc1grp100mhz { - fsl,pins = < - SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 - SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x21 - SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x21 - SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x21 - SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x21 - SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x21 - SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x21 - SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x21 - SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x21 - SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x21 - SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x41 - SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x21 - >; - }; - - pinctrl_usdhc1_200mhz: usdhc1grp200mhz { - fsl,pins = < - SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 - SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x21 - SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x21 - SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x21 - SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x21 - SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x21 - SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x21 - SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x21 - SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x21 - SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x21 - SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x41 - SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x21 - >; - }; - - /* Apalis MMC1_CD# */ - pinctrl_usdhc2_gpio: mmc1gpiogrp { - fsl,pins = < - SC_P_USDHC1_CD_B_LSIO_GPIO4_IO22 0x06000021 /* SODIMM 164 */ - >; - }; - - pinctrl_usdhc2_gpio_sleep: usdhc1gpioslpgrp { - fsl,pins = < - SC_P_USDHC1_CD_B_LSIO_GPIO4_IO22 0x60 /* SODIMM 164 */ - >; - }; - - /* Apalis USBH_EN */ - pinctrl_usbh_en: usbhen { - fsl,pins = < - SC_P_USB_SS3_TC1_LSIO_GPIO4_IO04 0x40 /* SODIMM 84 */ - >; - }; - - /* Apalis MMC1 */ - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 /* SODIMM 154 */ - SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x21 /* SODIMM 150 */ - SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x21 /* SODIMM 160 */ - SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x21 /* SODIMM 162 */ - SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x21 /* SODIMM 144 */ - SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x21 /* SODIMM 146 */ - SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2grp100mhz { - fsl,pins = < - SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 /* SODIMM 154 */ - SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x21 /* SODIMM 150 */ - SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x21 /* SODIMM 160 */ - SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x21 /* SODIMM 162 */ - SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x21 /* SODIMM 144 */ - SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x21 /* SODIMM 146 */ - SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2grp200mhz { - fsl,pins = < - SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 /* SODIMM 154 */ - SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x21 /* SODIMM 150 */ - SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x21 /* SODIMM 160 */ - SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x21 /* SODIMM 162 */ - SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x21 /* SODIMM 144 */ - SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x21 /* SODIMM 146 */ - SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21 - >; - }; - - pinctrl_usdhc2_sleep: usdhc2slpgrp { - fsl,pins = < - SC_P_USDHC1_CLK_LSIO_GPIO4_IO23 0x60 /* SODIMM 154 */ - SC_P_USDHC1_CMD_LSIO_GPIO4_IO24 0x60 /* SODIMM 150 */ - SC_P_USDHC1_DATA0_LSIO_GPIO4_IO25 0x60 /* SODIMM 160 */ - SC_P_USDHC1_DATA1_LSIO_GPIO4_IO26 0x60 /* SODIMM 162 */ - SC_P_USDHC1_DATA2_LSIO_GPIO4_IO27 0x60 /* SODIMM 144 */ - SC_P_USDHC1_DATA3_LSIO_GPIO4_IO28 0x60 /* SODIMM 146 */ - SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21 - >; - }; - }; -}; - -/* Apalis Gigabit LAN */ -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1>; - fsl,magic-packet; - phy-handle = <ðphy0>; - phy-mode = "rgmii-id"; - phy-reset-duration = <10>; - phy-reset-post-delay = <150>; - phy-reset-gpios = <&gpio3 4 GPIO_ACTIVE_LOW>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@4 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <4>; - }; - }; -}; - -/* Apalis UART1 */ -&lpuart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lpuart1>; - status = "okay"; -}; - -/* On-module eMMC */ -&usdhc1 { - bus-width = <8>; - non-removable; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc1>; - pinctrl-1 = <&pinctrl_usdhc1_100mhz>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz>; - status = "okay"; -}; - -/* Apalis MMC1 */ -&usdhc2 { - bus-width = <4>; - cd-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; - pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; - pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; - pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>; - disable-wp; - status = "okay"; -}; diff --git a/arch/arm/dts/imx8mm-venice-gw71xx-0x-u-boot.dtsi b/arch/arm/dts/imx8mm-venice-gw71xx-0x-u-boot.dtsi index f5d52c2..b359233 100644 --- a/arch/arm/dts/imx8mm-venice-gw71xx-0x-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-venice-gw71xx-0x-u-boot.dtsi @@ -3,3 +3,49 @@ * Copyright 2021 Gateworks Corporation */ #include "imx8mm-venice-gw700x-u-boot.dtsi" + +&gpio1 { + pci_usb_sel { + gpio-hog; + output-low; + gpios = <6 GPIO_ACTIVE_HIGH>; + line-name = "pci_usb_sel"; + }; + + dio_0 { + gpio-hog; + input; + gpios = <7 GPIO_ACTIVE_HIGH>; + line-name = "dio0"; + }; + + dio_1 { + gpio-hog; + input; + gpios = <9 GPIO_ACTIVE_HIGH>; + line-name = "dio1"; + }; +}; + +&gpio4 { + dio_2 { + gpio-hog; + input; + gpios = <3 GPIO_ACTIVE_HIGH>; + line-name = "dio2"; + }; + + dio_3 { + gpio-hog; + input; + gpios = <4 GPIO_ACTIVE_HIGH>; + line-name = "dio3"; + }; + + pci_wdis { + gpio-hog; + output-high; + gpios = <7 GPIO_ACTIVE_HIGH>; + line-name = "pci_wdis#"; + }; +}; diff --git a/arch/arm/dts/imx8mm-venice-gw72xx-0x-u-boot.dtsi b/arch/arm/dts/imx8mm-venice-gw72xx-0x-u-boot.dtsi index f5d52c2..92e44d4 100644 --- a/arch/arm/dts/imx8mm-venice-gw72xx-0x-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-venice-gw72xx-0x-u-boot.dtsi @@ -3,3 +3,84 @@ * Copyright 2021 Gateworks Corporation */ #include "imx8mm-venice-gw700x-u-boot.dtsi" + +&gpio1 { + rs485_term { + gpio-hog; + output-low; + gpios = <0 GPIO_ACTIVE_HIGH>; + line-name = "rs485_term"; + }; + + mipi_gpio4 { + gpio-hog; + input; + gpios = <1 GPIO_ACTIVE_HIGH>; + line-name = "mipi_gpio4"; + }; + + pci_usb_sel { + gpio-hog; + output-low; + gpios = <6 GPIO_ACTIVE_HIGH>; + line-name = "pci_usb_sel"; + }; + + dio_0 { + gpio-hog; + input; + gpios = <7 GPIO_ACTIVE_HIGH>; + line-name = "dio0"; + }; + + dio_1 { + gpio-hog; + input; + gpios = <9 GPIO_ACTIVE_HIGH>; + line-name = "dio1"; + }; +}; + +&gpio4 { + rs485_en { + gpio-hog; + output-low; + gpios = <0 GPIO_ACTIVE_HIGH>; + line-name = "rs485_en"; + }; + + mipi_gpio3 { + gpio-hog; + input; + gpios = <1 GPIO_ACTIVE_HIGH>; + line-name = "mipi_gpio3"; + }; + + rs485_half { + gpio-hog; + output-low; + gpios = <2 GPIO_ACTIVE_HIGH>; + line-name = "rs485_hd"; + }; + + mipi_gpio2 { + gpio-hog; + input; + gpios = <3 GPIO_ACTIVE_HIGH>; + line-name = "mipi_gpio2"; + }; + + mipi_gpio1 { + gpio-hog; + input; + gpios = <4 GPIO_ACTIVE_HIGH>; + line-name = "mipi_gpio1"; + }; + + pci_wdis { + gpio-hog; + output-high; + gpios = <7 GPIO_ACTIVE_HIGH>; + line-name = "pci_wdis#"; + }; +}; diff --git a/arch/arm/dts/imx8mm-venice-gw73xx-0x-u-boot.dtsi b/arch/arm/dts/imx8mm-venice-gw73xx-0x-u-boot.dtsi index f5d52c2..92e44d4 100644 --- a/arch/arm/dts/imx8mm-venice-gw73xx-0x-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-venice-gw73xx-0x-u-boot.dtsi @@ -3,3 +3,84 @@ * Copyright 2021 Gateworks Corporation */ #include "imx8mm-venice-gw700x-u-boot.dtsi" + +&gpio1 { + rs485_term { + gpio-hog; + output-low; + gpios = <0 GPIO_ACTIVE_HIGH>; + line-name = "rs485_term"; + }; + + mipi_gpio4 { + gpio-hog; + input; + gpios = <1 GPIO_ACTIVE_HIGH>; + line-name = "mipi_gpio4"; + }; + + pci_usb_sel { + gpio-hog; + output-low; + gpios = <6 GPIO_ACTIVE_HIGH>; + line-name = "pci_usb_sel"; + }; + + dio_0 { + gpio-hog; + input; + gpios = <7 GPIO_ACTIVE_HIGH>; + line-name = "dio0"; + }; + + dio_1 { + gpio-hog; + input; + gpios = <9 GPIO_ACTIVE_HIGH>; + line-name = "dio1"; + }; +}; + +&gpio4 { + rs485_en { + gpio-hog; + output-low; + gpios = <0 GPIO_ACTIVE_HIGH>; + line-name = "rs485_en"; + }; + + mipi_gpio3 { + gpio-hog; + input; + gpios = <1 GPIO_ACTIVE_HIGH>; + line-name = "mipi_gpio3"; + }; + + rs485_half { + gpio-hog; + output-low; + gpios = <2 GPIO_ACTIVE_HIGH>; + line-name = "rs485_hd"; + }; + + mipi_gpio2 { + gpio-hog; + input; + gpios = <3 GPIO_ACTIVE_HIGH>; + line-name = "mipi_gpio2"; + }; + + mipi_gpio1 { + gpio-hog; + input; + gpios = <4 GPIO_ACTIVE_HIGH>; + line-name = "mipi_gpio1"; + }; + + pci_wdis { + gpio-hog; + output-high; + gpios = <7 GPIO_ACTIVE_HIGH>; + line-name = "pci_wdis#"; + }; +}; diff --git a/arch/arm/dts/imx8mm-venice-gw7901-u-boot.dtsi b/arch/arm/dts/imx8mm-venice-gw7901-u-boot.dtsi index a801ee1..11c773b 100644 --- a/arch/arm/dts/imx8mm-venice-gw7901-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-venice-gw7901-u-boot.dtsi @@ -5,6 +5,124 @@ #include "imx8mm-venice-u-boot.dtsi" +&gpio1 { + uart1_rs422 { + gpio-hog; + output-high; + gpios = <0 GPIO_ACTIVE_HIGH>; + line-name = "uart1_rs422#"; + }; + + uart1rs485 { + gpio-hog; + output-high; + gpios = <3 GPIO_ACTIVE_HIGH>; + line-name = "uart1_rs485#"; + }; + + uart1rs232 { + gpio-hog; + output-high; + gpios = <5 GPIO_ACTIVE_HIGH>; + line-name = "uart1_rs232#"; + }; + + dig1in { + gpio-hog; + input; + gpios = <6 GPIO_ACTIVE_HIGH>; + line-name = "dig1_in"; + }; + + dig1out { + gpio-hog; + output-low; + gpios = <7 GPIO_ACTIVE_HIGH>; + line-name = "dig1_out"; + }; +}; + +&gpio4 { + uart3_rs232 { + gpio-hog; + output-high; + gpios = <6 GPIO_ACTIVE_HIGH>; + line-name = "uart3_rs232#"; + }; + + uart3_rs422 { + gpio-hog; + output-high; + gpios = <7 GPIO_ACTIVE_HIGH>; + line-name = "uart3_rs422#"; + }; + + uart3_rs485 { + gpio-hog; + output-high; + gpios = <8 GPIO_ACTIVE_HIGH>; + line-name = "uart3_rs485#"; + }; + + uart4_rs485 { + gpio-hog; + output-high; + gpios = <27 GPIO_ACTIVE_HIGH>; + line-name = "uart4_rs485#"; + }; + + sim1det { + gpio-hog; + input; + gpios = <29 GPIO_ACTIVE_HIGH>; + line-name = "sim1_det"; + }; + + sim2det { + gpio-hog; + input; + gpios = <30 GPIO_ACTIVE_HIGH>; + line-name = "sim2_det"; + }; +}; + +&gpio5 { + dig2out { + gpio-hog; + output-low; + gpios = <3 GPIO_ACTIVE_HIGH>; + line-name = "dig2_out"; + }; + + dig2in { + gpio-hog; + input; + gpios = <4 GPIO_ACTIVE_HIGH>; + line-name = "dig2_in"; + }; + + sim2sel { + gpio-hog; + output-low; + gpios = <5 GPIO_ACTIVE_HIGH>; + line-name = "sim2_sel"; + }; + + uart4_rs232 { + gpio-hog; + output-high; + gpios = <10 GPIO_ACTIVE_HIGH>; + line-name = "uart4_rs232#"; + }; + + uart4_rs422 { + gpio-hog; + output-high; + gpios = <13 GPIO_ACTIVE_HIGH>; + line-name = "uart4_rs422#"; + }; +}; + &fec1 { phy-reset-gpios = <&gpio4 19 GPIO_ACTIVE_LOW>; phy-reset-duration = <1>; diff --git a/arch/arm/dts/imx8mm-venice-gw7902-u-boot.dtsi b/arch/arm/dts/imx8mm-venice-gw7902-u-boot.dtsi index d0e5d6c..f21e46b 100644 --- a/arch/arm/dts/imx8mm-venice-gw7902-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-venice-gw7902-u-boot.dtsi @@ -5,10 +5,160 @@ #include "imx8mm-venice-u-boot.dtsi" +&gpio1 { + m2rst { + gpio-hog; + output-low; + gpios = <13 GPIO_ACTIVE_HIGH>; + line-name = "m2_reset"; + }; + + m2wdis { + gpio-hog; + output-high; + gpios = <15 GPIO_ACTIVE_HIGH>; + line-name = "m2_wdis#"; + }; +}; + +&gpio2 { + uart2en { + gpio-hog; + output-high; + gpios = <8 GPIO_ACTIVE_HIGH>; + line-name = "uart2_en#"; + }; +}; + +&gpio3 { + m2gdis { + gpio-hog; + output-high; + gpios = <1 GPIO_ACTIVE_HIGH>; + line-name = "m2_gdis#"; + }; + + m2off { + gpio-hog; + output-high; + gpios = <7 GPIO_ACTIVE_HIGH>; + line-name = "m2_off#"; + }; +}; + +&gpio4 { + ampgpio3 { + gpio-hog; + input; + gpios = <11 GPIO_ACTIVE_HIGH>; + line-name = "amp_gpio3"; + }; + + ampgpio2 { + gpio-hog; + input; + gpios = <12 GPIO_ACTIVE_HIGH>; + line-name = "amp_gpio2"; + }; + + ampgpio1 { + gpio-hog; + input; + gpios = <14 GPIO_ACTIVE_HIGH>; + line-name = "amp_gpio1"; + }; + + ltrpwr { + gpio-hog; + output-low; + gpios = <16 GPIO_ACTIVE_HIGH>; + line-name = "lte_pwr#"; + }; + + lterst { + gpio-hog; + output-low; + gpios = <17 GPIO_ACTIVE_HIGH>; + line-name = "lte_rst"; + }; + + ampgpio4 { + gpio-hog; + input; + gpios = <20 GPIO_ACTIVE_HIGH>; + line-name = "amp_gpio4"; + }; + + appgpio1 { + gpio-hog; + input; + gpios = <21 GPIO_ACTIVE_HIGH>; + line-name = "app_gpio1"; + }; + + uart1rs485 { + gpio-hog; + output-low; + gpios = <23 GPIO_ACTIVE_HIGH>; + line-name = "uart1_rs485"; + }; + + uart1term { + gpio-hog; + output-low; + gpios = <25 GPIO_ACTIVE_HIGH>; + line-name = "uart1_term"; + }; + + uart1half { + gpio-hog; + output-low; + gpios = <26 GPIO_ACTIVE_HIGH>; + line-name = "uart1_half"; + }; + + appgpio2 { + gpio-hog; + input; + gpios = <27 GPIO_ACTIVE_HIGH>; + line-name = "app_gpio2"; + }; + + mipigpio1 { + gpio-hog; + input; + gpios = <28 GPIO_ACTIVE_HIGH>; + line-name = "mipi_gpio1"; + }; +}; + +&gpio5 { + mipigpio4 { + gpio-hog; + input; + gpios = <3 GPIO_ACTIVE_HIGH>; + line-name = "mipi_gpio4"; + }; + + mipigpio3 { + gpio-hog; + input; + gpios = <4 GPIO_ACTIVE_HIGH>; + line-name = "mipi_gpio3"; + }; + + mipigpio2 { + gpio-hog; + input; + gpios = <5 GPIO_ACTIVE_HIGH>; + line-name = "mipi_gpio2"; + }; +}; + &fec1 { phy-reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; phy-reset-duration = <1>; - phy-reset-post-delay = <1>; + phy-reset-post-delay = <300>; }; &pinctrl_fec1 { diff --git a/arch/arm/dts/imx8mm-venice-gw7902.dts b/arch/arm/dts/imx8mm-venice-gw7902.dts index adf5216..b0404ec 100644 --- a/arch/arm/dts/imx8mm-venice-gw7902.dts +++ b/arch/arm/dts/imx8mm-venice-gw7902.dts @@ -243,10 +243,14 @@ ethphy0: ethernet-phy@0 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <0>; + /* TI DP83867 props */ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; + /* GPY111 props */ + rx-internal-delay-ps = <2000>; + tx-internal-delay-ps = <2500>; }; }; }; diff --git a/arch/arm/dts/imx8mm-venice-gw7903-u-boot.dtsi b/arch/arm/dts/imx8mm-venice-gw7903-u-boot.dtsi index 36a6054..896e5d4 100644 --- a/arch/arm/dts/imx8mm-venice-gw7903-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-venice-gw7903-u-boot.dtsi @@ -5,6 +5,89 @@ #include "imx8mm-venice-u-boot.dtsi" +&gpio1 { + rs422en { + gpio-hog; + output-high; + gpios = <10 GPIO_ACTIVE_HIGH>; + line-name = "rs422_en#"; + }; + + rs485en { + gpio-hog; + output-high; + gpios = <11 GPIO_ACTIVE_HIGH>; + line-name = "rs485_en#"; + }; + + rs232en { + gpio-hog; + output-low; + gpios = <12 GPIO_ACTIVE_HIGH>; + line-name = "rs232_en#"; + }; +}; + +&gpio2 { + dig2in { + gpio-hog; + input; + gpios = <0 GPIO_ACTIVE_HIGH>; + line-name = "dig2_in"; + }; + + dig2out { + gpio-hog; + output-high; + gpios = <1 GPIO_ACTIVE_HIGH>; + line-name = "dig2_out#"; + }; + + dig1out { + gpio-hog; + output-high; + gpios = <8 GPIO_ACTIVE_HIGH>; + line-name = "dig1_out#"; + }; + + dig1in { + gpio-hog; + input; + gpios = <9 GPIO_ACTIVE_HIGH>; + line-name = "dig1_in"; + }; +}; + +&gpio5 { + sim1det { + gpio-hog; + input; + gpios = <7 GPIO_ACTIVE_LOW>; + line-name = "sim1_det#"; + }; + + sim2det { + gpio-hog; + input; + gpios = <8 GPIO_ACTIVE_LOW>; + line-name = "sim2_det#"; + }; + + sim2sel { + gpio-hog; + output-low; + gpios = <9 GPIO_ACTIVE_HIGH>; + line-name = "sim2_sel"; + }; + + pci_wdis { + gpio-hog; + output-high; + gpios = <12 GPIO_ACTIVE_HIGH>; + line-name = "pci_wdis#"; + }; +}; + &fec1 { phy-reset-gpios = <&gpio4 25 GPIO_ACTIVE_LOW>; phy-reset-duration = <1>; diff --git a/arch/arm/dts/imx8mm-venice-u-boot.dtsi b/arch/arm/dts/imx8mm-venice-u-boot.dtsi index 42b2903..c61c6de 100644 --- a/arch/arm/dts/imx8mm-venice-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-venice-u-boot.dtsi @@ -57,6 +57,10 @@ u-boot,dm-spl; }; +&gsc { + u-boot,dm-spl; +}; + &i2c2 { u-boot,dm-spl; }; diff --git a/arch/arm/dts/imx8mm-venice.dts b/arch/arm/dts/imx8mm-venice.dts index 54505a0..39b0306 100644 --- a/arch/arm/dts/imx8mm-venice.dts +++ b/arch/arm/dts/imx8mm-venice.dts @@ -27,6 +27,13 @@ pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; + gsc: gsc@20 { + compatible = "gw,gsc"; + reg = <0x20>; + #address-cells = <1>; + #size-cells = <0>; + }; + eeprom@51 { compatible = "atmel,24c02"; reg = <0x51>; diff --git a/arch/arm/dts/imx8mn-venice-gw7902-u-boot.dtsi b/arch/arm/dts/imx8mn-venice-gw7902-u-boot.dtsi index b334b56..17e6828 100644 --- a/arch/arm/dts/imx8mn-venice-gw7902-u-boot.dtsi +++ b/arch/arm/dts/imx8mn-venice-gw7902-u-boot.dtsi @@ -5,10 +5,118 @@ #include "imx8mn-venice-u-boot.dtsi" +&gpio1 { + m2rst { + gpio-hog; + output-low; + gpios = <13 GPIO_ACTIVE_HIGH>; + line-name = "m2_reset"; + }; + + m2wdis { + gpio-hog; + output-high; + gpios = <15 GPIO_ACTIVE_HIGH>; + line-name = "m2_wdis#"; + }; +}; + +&gpio2 { + uart2en { + gpio-hog; + output-high; + gpios = <8 GPIO_ACTIVE_HIGH>; + line-name = "uart2_en#"; + }; +}; + +&gpio3 { + m2gdis { + gpio-hog; + output-high; + gpios = <1 GPIO_ACTIVE_HIGH>; + line-name = "m2_gdis#"; + }; + + m2off { + gpio-hog; + output-high; + gpios = <7 GPIO_ACTIVE_HIGH>; + line-name = "m2_off#"; + }; +}; + +&gpio4 { + appgpio1 { + gpio-hog; + input; + gpios = <21 GPIO_ACTIVE_HIGH>; + line-name = "app_gpio1"; + }; + + uart1rs485 { + gpio-hog; + output-low; + gpios = <23 GPIO_ACTIVE_HIGH>; + line-name = "uart1_rs485"; + }; + + uart1term { + gpio-hog; + output-low; + gpios = <25 GPIO_ACTIVE_HIGH>; + line-name = "uart1_term"; + }; + + uart1half { + gpio-hog; + output-low; + gpios = <26 GPIO_ACTIVE_HIGH>; + line-name = "uart1_half"; + }; + + appgpio2 { + gpio-hog; + input; + gpios = <27 GPIO_ACTIVE_HIGH>; + line-name = "app_gpio2"; + }; + + mipigpio1 { + gpio-hog; + input; + gpios = <28 GPIO_ACTIVE_HIGH>; + line-name = "mipi_gpio1"; + }; +}; + +&gpio5 { + mipigpio4 { + gpio-hog; + input; + gpios = <3 GPIO_ACTIVE_HIGH>; + line-name = "mipi_gpio4"; + }; + + mipigpio3 { + gpio-hog; + input; + gpios = <4 GPIO_ACTIVE_HIGH>; + line-name = "mipi_gpio3"; + }; + + mipigpio2 { + gpio-hog; + input; + gpios = <5 GPIO_ACTIVE_HIGH>; + line-name = "mipi_gpio2"; + }; +}; + &fec1 { phy-reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; phy-reset-duration = <1>; - phy-reset-post-delay = <1>; + phy-reset-post-delay = <300>; }; &pinctrl_fec1 { diff --git a/arch/arm/dts/imx8mn-venice-gw7902.dts b/arch/arm/dts/imx8mn-venice-gw7902.dts index 29897c1..d026d96 100644 --- a/arch/arm/dts/imx8mn-venice-gw7902.dts +++ b/arch/arm/dts/imx8mn-venice-gw7902.dts @@ -242,10 +242,14 @@ ethphy0: ethernet-phy@0 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <0>; + /* TI DP83867 props */ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; + /* GPY111 props */ + rx-internal-delay-ps = <2000>; + tx-internal-delay-ps = <2500>; }; }; }; diff --git a/arch/arm/dts/imx8mn-venice-u-boot.dtsi b/arch/arm/dts/imx8mn-venice-u-boot.dtsi index 055406e..4f23da3 100644 --- a/arch/arm/dts/imx8mn-venice-u-boot.dtsi +++ b/arch/arm/dts/imx8mn-venice-u-boot.dtsi @@ -94,6 +94,10 @@ u-boot,dm-spl; }; +&gsc { + u-boot,dm-spl; +}; + &i2c2 { u-boot,dm-spl; }; diff --git a/arch/arm/dts/imx8mn-venice.dts b/arch/arm/dts/imx8mn-venice.dts index e906a56..eeae225 100644 --- a/arch/arm/dts/imx8mn-venice.dts +++ b/arch/arm/dts/imx8mn-venice.dts @@ -27,6 +27,13 @@ pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; + gsc: gsc@20 { + compatible = "gw,gsc"; + reg = <0x20>; + #address-cells = <1>; + #size-cells = <0>; + }; + eeprom@51 { compatible = "atmel,24c02"; reg = <0x51>; diff --git a/arch/arm/dts/imx8mp-u-boot.dtsi b/arch/arm/dts/imx8mp-u-boot.dtsi index cfc352a..20edd90 100644 --- a/arch/arm/dts/imx8mp-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-u-boot.dtsi @@ -99,8 +99,9 @@ fit { description = "Configuration to load ATF before U-Boot"; - #address-cells = <1>; fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>; + fit,fdt-list = "of-list"; + #address-cells = <1>; images { uboot { @@ -129,7 +130,7 @@ }; }; - fdt { + @fdt-SEQ { description = "NAME"; type = "flat_dt"; compression = "none"; @@ -141,13 +142,13 @@ }; configurations { - default = "conf"; + default = "@config-DEFAULT-SEQ"; - conf { + @config-SEQ { description = "NAME"; + fdt = "fdt-SEQ"; firmware = "uboot"; loadables = "atf"; - fdt = "fdt"; }; }; }; diff --git a/arch/arm/dts/imx8mp-venice-gw74xx-u-boot.dtsi b/arch/arm/dts/imx8mp-venice-gw74xx-u-boot.dtsi new file mode 100644 index 0000000..920246d --- /dev/null +++ b/arch/arm/dts/imx8mp-venice-gw74xx-u-boot.dtsi @@ -0,0 +1,185 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Gateworks Corporation + */ + +#include "imx8mp-u-boot.dtsi" + +/ { + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; + + wdt-reboot { + compatible = "wdt-reboot"; + u-boot,dm-spl; + wdt = <&wdog1>; + }; +}; + +&eqos { + /delete-property/ assigned-clocks; + /delete-property/ assigned-clock-parents; + /delete-property/ assigned-clock-rates; +}; + +ðphy0 { + reset-gpios = <&gpio4 30 GPIO_ACTIVE_LOW>; + reset-delay-us = <1000>; + reset-post-delay-us = <300000>; +}; + +&fec { + phy-reset-gpios = <&gpio4 29 GPIO_ACTIVE_LOW>; + phy-reset-duration = <15>; + phy-reset-post-delay = <100>; +}; + +&gpio1 { + u-boot,dm-spl; + + dio0_hog { + gpio-hog; + input; + gpios = <9 GPIO_ACTIVE_LOW>; + line-name = "dio0"; + }; + + dio1_hog { + gpio-hog; + input; + gpios = <11 GPIO_ACTIVE_LOW>; + line-name = "dio1"; + }; +}; + +&gpio2 { + u-boot,dm-spl; + + pcie1_wdis_hog { + gpio-hog; + gpios = <17 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "pcie1_wdis#"; + }; + + pcie2_wdis_hog { + gpio-hog; + gpios = <18 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "pcie2_wdis#"; + }; + + pcie3_wdis_hog { + gpio-hog; + gpios = <14 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "pcie3_wdis#"; + }; +}; + +&gpio3 { + u-boot,dm-spl; + + m2_dis2_hog { + gpio-hog; + gpios = <0 GPIO_ACTIVE_LOW>; + output-high; + line-name = "m2_gdis#"; + }; + + m2rst_hog { + gpio-hog; + gpios = <6 GPIO_ACTIVE_LOW>; + output-high; + line-name = "m2_rst#"; + }; + + m2_off_hog { + gpio-hog; + gpios = <14 GPIO_ACTIVE_LOW>; + output-high; + line-name = "m2_off#"; + }; +}; + +&gpio4 { + u-boot,dm-spl; + + m2_dis1_hog { + gpio-hog; + gpios = <18 GPIO_ACTIVE_LOW>; + output-high; + line-name = "m2_wdis#"; + }; + + uart_rs485_hog { + gpio-hog; + gpios = <31 GPIO_ACTIVE_LOW>; + output-low; + line-name = "uart_rs485"; + }; +}; + +&gpio5 { + u-boot,dm-spl; + + uart_half_hog { + gpio-hog; + gpios = <0 GPIO_ACTIVE_LOW>; + output-high; + line-name = "uart_half"; + }; + + uart_term_hog { + gpio-hog; + gpios = <1 GPIO_ACTIVE_LOW>; + output-low; + line-name = "uart_term"; + }; +}; + +&i2c1 { + u-boot,dm-spl; +}; + +&i2c2 { + u-boot,dm-spl; +}; + +&i2c3 { + u-boot,dm-spl; +}; + +&pinctrl_i2c1 { + u-boot,dm-spl; +}; + +&pinctrl_wdog { + u-boot,dm-spl; +}; + +&usdhc2 { + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>; + assigned-clock-rates = <400000000>; + assigned-clocks = <&clk IMX8MP_CLK_USDHC2>; + sd-uhs-ddr50; + sd-uhs-sdr104; + u-boot,dm-spl; +}; + +&usdhc3 { + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>; + assigned-clock-rates = <400000000>; + assigned-clocks = <&clk IMX8MP_CLK_USDHC3>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + u-boot,dm-spl; +}; + +&wdog1 { + u-boot,dm-spl; +}; diff --git a/arch/arm/dts/imx8mp-venice-gw74xx.dts b/arch/arm/dts/imx8mp-venice-gw74xx.dts new file mode 100644 index 0000000..ecb117a --- /dev/null +++ b/arch/arm/dts/imx8mp-venice-gw74xx.dts @@ -0,0 +1,923 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Gateworks Corporation + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/linux-event-codes.h> +#include <dt-bindings/leds/common.h> + +#include "imx8mp.dtsi" + +/ { + model = "Gateworks Venice GW74xx i.MX8MP board"; + compatible = "gateworks,imx8mp-gw74xx", "fsl,imx8mp"; + + aliases { + ethernet0 = &eqos; + ethernet1 = &fec; + ethernet2 = &lan1; + ethernet3 = &lan2; + ethernet4 = &lan3; + ethernet5 = &lan4; + ethernet6 = &lan5; + }; + + chosen { + stdout-path = &uart2; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x0 0x40000000 0 0x80000000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-0 { + label = "user_pb"; + gpios = <&gpio 2 GPIO_ACTIVE_LOW>; + linux,code = <BTN_0>; + }; + + key-1 { + label = "user_pb1x"; + linux,code = <BTN_1>; + interrupt-parent = <&gsc>; + interrupts = <0>; + }; + + key-2 { + label = "key_erased"; + linux,code = <BTN_2>; + interrupt-parent = <&gsc>; + interrupts = <1>; + }; + + key-3 { + label = "eeprom_wp"; + linux,code = <BTN_3>; + interrupt-parent = <&gsc>; + interrupts = <2>; + }; + + key-4 { + label = "tamper"; + linux,code = <BTN_4>; + interrupt-parent = <&gsc>; + interrupts = <5>; + }; + + key-5 { + label = "switch_hold"; + linux,code = <BTN_5>; + interrupt-parent = <&gsc>; + interrupts = <7>; + }; + }; + + led-controller { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led-0 { + function = LED_FUNCTION_HEARTBEAT; + color = <LED_COLOR_ID_GREEN>; + gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>; + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + + led-1 { + function = LED_FUNCTION_STATUS; + color = <LED_COLOR_ID_RED>; + gpios = <&gpio2 16 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; + + pps { + compatible = "pps-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pps>; + gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; + }; + + reg_usb2_vbus: regulator-usb2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usb2>; + compatible = "regulator-fixed"; + regulator-name = "usb_usb2_vbus"; + gpio = <&gpio1 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_can2_stby: regulator-can2-stby { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_can>; + regulator-name = "can2_stby"; + gpio = <&gpio3 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_wifi_en: regulator-wifi-en { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_wifi>; + compatible = "regulator-fixed"; + regulator-name = "wl"; + gpio = <&gpio3 9 GPIO_ACTIVE_HIGH>; + startup-delay-us = <100>; + enable-active-high; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; +}; + +/* off-board header */ +&ecspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi2>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&eqos { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + }; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + phy-mode = "rgmii-id"; + local-mac-address = [00 00 00 00 00 00]; + status = "okay"; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can2_stby>; + status = "okay"; +}; + +&gpio1 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "dio0", "", "dio1", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio2 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "pcie3_wdis#", "", "", "pcie1_wdis@", "pcie2_wdis#", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio3 { + gpio-line-names = + "m2_gdis#", "", "", "", "", "", "", "m2_rst#", + "", "", "", "", "", "", "", "", + "m2_off#", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio4 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "m2_wdis#", "", "", "", + "", "", "", "", "", "", "", "uart_rs485"; +}; + +&gpio5 { + gpio-line-names = + "uart_half", "uart_term", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + gsc: gsc@20 { + compatible = "gw,gsc"; + reg = <0x20>; + pinctrl-0 = <&pinctrl_gsc>; + interrupt-parent = <&gpio4>; + interrupts = <20 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <1>; + + adc { + compatible = "gw,gsc-adc"; + #address-cells = <1>; + #size-cells = <0>; + + channel@6 { + gw,mode = <0>; + reg = <0x06>; + label = "temp"; + }; + + channel@8 { + gw,mode = <1>; + reg = <0x08>; + label = "vdd_bat"; + }; + + channel@82 { + gw,mode = <2>; + reg = <0x82>; + label = "vdd_adc1"; + gw,voltage-divider-ohms = <10000 10000>; + }; + + channel@84 { + gw,mode = <2>; + reg = <0x84>; + label = "vdd_adc2"; + gw,voltage-divider-ohms = <10000 10000>; + }; + + channel@86 { + gw,mode = <2>; + reg = <0x86>; + label = "vdd_vin"; + gw,voltage-divider-ohms = <22100 1000>; + }; + + channel@88 { + gw,mode = <2>; + reg = <0x88>; + label = "vdd_3p3"; + gw,voltage-divider-ohms = <10000 10000>; + }; + + channel@8c { + gw,mode = <2>; + reg = <0x8c>; + label = "vdd_2p5"; + gw,voltage-divider-ohms = <10000 10000>; + }; + + channel@90 { + gw,mode = <2>; + reg = <0x90>; + label = "vdd_soc"; + }; + + channel@92 { + gw,mode = <2>; + reg = <0x92>; + label = "vdd_arm"; + }; + + channel@98 { + gw,mode = <2>; + reg = <0x98>; + label = "vdd_1p8"; + }; + + channel@9a { + gw,mode = <2>; + reg = <0x9a>; + label = "vdd_1p2"; + }; + + channel@9c { + gw,mode = <2>; + reg = <0x9c>; + label = "vdd_dram"; + }; + + channel@a2 { + gw,mode = <2>; + reg = <0xa2>; + label = "vdd_gsc"; + gw,voltage-divider-ohms = <10000 10000>; + }; + }; + }; + + gpio: gpio@23 { + compatible = "nxp,pca9555"; + reg = <0x23>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gsc>; + interrupts = <4>; + }; + + pmic@25 { + compatible = "nxp,pca9450c"; + reg = <0x25>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio3>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + + regulators { + BUCK1 { + regulator-name = "BUCK1"; + regulator-min-microvolt = <720000>; + regulator-max-microvolt = <1000000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + BUCK2 { + regulator-name = "BUCK2"; + regulator-min-microvolt = <720000>; + regulator-max-microvolt = <1025000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + nxp,dvs-run-voltage = <950000>; + nxp,dvs-standby-voltage = <850000>; + }; + + BUCK4 { + regulator-name = "BUCK4"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3600000>; + regulator-boot-on; + regulator-always-on; + }; + + BUCK5 { + regulator-name = "BUCK5"; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <1950000>; + regulator-boot-on; + regulator-always-on; + }; + + BUCK6 { + regulator-name = "BUCK6"; + regulator-min-microvolt = <1045000>; + regulator-max-microvolt = <1155000>; + regulator-boot-on; + regulator-always-on; + }; + + LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <1950000>; + regulator-boot-on; + regulator-always-on; + }; + + LDO3 { + regulator-name = "LDO3"; + regulator-min-microvolt = <1710000>; + regulator-max-microvolt = <1890000>; + regulator-boot-on; + regulator-always-on; + }; + + LDO5 { + regulator-name = "LDO5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; + + eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + }; + + eeprom@51 { + compatible = "atmel,24c02"; + reg = <0x51>; + pagesize = <16>; + }; + + eeprom@52 { + compatible = "atmel,24c02"; + reg = <0x52>; + pagesize = <16>; + }; + + eeprom@53 { + compatible = "atmel,24c02"; + reg = <0x53>; + pagesize = <16>; + }; + + rtc@68 { + compatible = "dallas,ds1672"; + reg = <0x68>; + }; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + accelerometer@19 { + compatible = "st,lis2de12"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_accel>; + reg = <0x19>; + st,drdy-int-pin = <1>; + interrupt-parent = <&gpio1>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "INT1"; + }; + + switch: switch@5f { + compatible = "microchip,ksz9897"; + reg = <0x5f>; + pinctrl-0 = <&pinctrl_ksz>; + interrupt-parent = <&gpio4>; + interrupts = <29 IRQ_TYPE_EDGE_FALLING>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + lan1: port@0 { + reg = <0>; + label = "lan1"; + local-mac-address = [00 00 00 00 00 00]; + phy-handle = <&sw_phy0>; + phy-mode = "internal"; + }; + + lan2: port@1 { + reg = <1>; + label = "lan2"; + local-mac-address = [00 00 00 00 00 00]; + phy-handle = <&sw_phy1>; + phy-mode = "internal"; + }; + + lan3: port@2 { + reg = <2>; + label = "lan3"; + local-mac-address = [00 00 00 00 00 00]; + phy-handle = <&sw_phy2>; + phy-mode = "internal"; + }; + + lan4: port@3 { + reg = <3>; + label = "lan4"; + local-mac-address = [00 00 00 00 00 00]; + phy-handle = <&sw_phy3>; + phy-mode = "internal"; + }; + + lan5: port@4 { + reg = <4>; + label = "lan5"; + local-mac-address = [00 00 00 00 00 00]; + phy-handle = <&sw_phy4>; + phy-mode = "internal"; + }; + + port@6 { + reg = <6>; + label = "cpu"; + ethernet = <&fec>; + phy-mode = "rgmii-id"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + + mdios { + #address-cells = <1>; + #size-cells = <0>; + + mdio@0 { + reg = <0>; + compatible = "microchip,ksz-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + sw_phy0: ethernet-phy@0 { + reg = <0x0>; + }; + + sw_phy1: ethernet-phy@1 { + reg = <0x1>; + }; + + sw_phy2: ethernet-phy@2 { + reg = <0x2>; + }; + + sw_phy3: ethernet-phy@3 { + reg = <0x3>; + }; + + sw_phy4: ethernet-phy@4 { + reg = <0x4>; + }; + }; + }; + }; +}; + +/* off-board header */ +&i2c3 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; +}; + +/* off-board header */ +&i2c4 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + status = "okay"; +}; + +/* GPS / off-board header */ +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +/* RS232 console */ +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +/* USB1 - Type C front panel */ +&usb3_phy0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1>; + status = "okay"; +}; + +&usb3_0 { + fsl,over-current-active-low; + status = "okay"; +}; + +&usb_dwc3_0 { + dr_mode = "host"; + status = "okay"; +}; + +/* USB2 - USB3.0 Hub */ +&usb3_phy1 { + vbus-supply = <®_usb2_vbus>; + status = "okay"; +}; + +&usb3_1 { + fsl,permanently-attached; + fsl,disable-port-power-control; + status = "okay"; +}; + +&usb_dwc3_1 { + dr_mode = "host"; + status = "okay"; +}; + +/* eMMC */ +&usdhc3 { + assigned-clocks = <&clk IMX8MP_CLK_USDHC3>; + assigned-clock-rates = <400000000>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x40000041 /* DIO0 */ + MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x40000041 /* DIO1 */ + MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x40000041 /* M2SKT_OFF# */ + MX8MP_IOMUXC_SD2_DATA2__GPIO2_IO17 0x40000159 /* PCIE1_WDIS# */ + MX8MP_IOMUXC_SD2_DATA3__GPIO2_IO18 0x40000159 /* PCIE2_WDIS# */ + MX8MP_IOMUXC_SD2_CMD__GPIO2_IO14 0x40000159 /* PCIE3_WDIS# */ + MX8MP_IOMUXC_NAND_DATA00__GPIO3_IO06 0x40000041 /* M2SKT_RST# */ + MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x40000159 /* M2SKT_WDIS# */ + MX8MP_IOMUXC_NAND_ALE__GPIO3_IO00 0x40000159 /* M2SKT_GDIS# */ + MX8MP_IOMUXC_SAI3_TXD__GPIO5_IO01 0x40000104 /* UART_TERM */ + MX8MP_IOMUXC_SAI3_TXFS__GPIO4_IO31 0x40000104 /* UART_RS485 */ + MX8MP_IOMUXC_SAI3_TXC__GPIO5_IO00 0x40000104 /* UART_HALF */ + >; + }; + + pinctrl_accel: accelgrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x159 + >; + }; + + pinctrl_eqos: eqosgrp { + fsl,pins = < + MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3 + MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3 + MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91 + MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91 + MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91 + MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91 + MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91 + MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91 + MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f + MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f + MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f + MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f + MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f + MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f + MX8MP_IOMUXC_SAI3_RXD__GPIO4_IO30 0x141 /* RST# */ + MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x159 /* IRQ# */ + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91 + MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91 + MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91 + MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91 + MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91 + MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91 + MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f + MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f + MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f + MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f + MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f + MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f + MX8MP_IOMUXC_SAI1_RXFS__ENET1_1588_EVENT0_IN 0x141 + MX8MP_IOMUXC_SAI1_RXC__ENET1_1588_EVENT0_OUT 0x141 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154 + MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154 + >; + }; + + pinctrl_gsc: gscgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x159 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3 + MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c3 + MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c3 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c3 + MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c3 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c3 + MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c3 + >; + }; + + pinctrl_ksz: kszgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x159 /* IRQ# */ + MX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02 0x141 /* RST# */ + >; + }; + + pinctrl_gpio_leds: ledgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_DATA0__GPIO2_IO15 0x19 + MX8MP_IOMUXC_SD2_DATA1__GPIO2_IO16 0x19 + >; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07 0x141 + >; + }; + + pinctrl_pps: ppsgrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x141 + >; + }; + + pinctrl_reg_can: regcangrp { + fsl,pins = < + MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19 0x154 + >; + }; + + pinctrl_reg_usb2: regusb2grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x141 + >; + }; + + pinctrl_reg_wifi: regwifigrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_DATA03__GPIO3_IO09 0x119 + >; + }; + + pinctrl_sai2: sai2grp { + fsl,pins = < + MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI2_TX_SYNC + MX8MP_IOMUXC_SAI2_TXD0__AUDIOMIX_SAI2_TX_DATA00 + MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_SAI2_TX_BCLK + MX8MP_IOMUXC_SAI2_MCLK__AUDIOMIX_SAI2_MCLK + >; + }; + + pinctrl_spi2: spi2grp { + fsl,pins = < + MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x82 + MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x82 + MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x82 + MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x140 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 + MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140 + MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x140 + MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x140 + >; + }; + + pinctrl_usb1: usb1grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x140 + MX8MP_IOMUXC_GPIO1_IO10__USB1_OTG_ID 0x140 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x166 + >; + }; +}; diff --git a/arch/arm/dts/imx8mp-venice-u-boot.dtsi b/arch/arm/dts/imx8mp-venice-u-boot.dtsi new file mode 100644 index 0000000..37f3edc --- /dev/null +++ b/arch/arm/dts/imx8mp-venice-u-boot.dtsi @@ -0,0 +1,74 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Gateworks Corporation + */ + +#include "imx8mp-u-boot.dtsi" + +/ { + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdog1>; + u-boot,dm-spl; + }; +}; + +&gpio1 { + u-boot,dm-spl; +}; + +&gpio2 { + u-boot,dm-spl; +}; + +&gpio3 { + u-boot,dm-spl; +}; + +&gpio4 { + u-boot,dm-spl; +}; + +&gpio5 { + u-boot,dm-spl; +}; + +&uart2 { + u-boot,dm-spl; +}; + +&pinctrl_uart2 { + u-boot,dm-spl; +}; + +&usdhc3 { + u-boot,dm-spl; +}; + +&pinctrl_usdhc3 { + u-boot,dm-spl; +}; + +&i2c1 { + u-boot,dm-spl; +}; + +&pinctrl_i2c1 { + u-boot,dm-spl; +}; + +&gsc { + u-boot,dm-spl; +}; + +&i2c2 { + u-boot,dm-spl; +}; + +&pinctrl_i2c2 { + u-boot,dm-spl; +}; + +&wdog1 { + u-boot,dm-spl; +}; diff --git a/arch/arm/dts/imx8mp-venice.dts b/arch/arm/dts/imx8mp-venice.dts new file mode 100644 index 0000000..6b1a7f1 --- /dev/null +++ b/arch/arm/dts/imx8mp-venice.dts @@ -0,0 +1,159 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Gateworks Corporation + */ + +/dts-v1/; + +#include "imx8mp.dtsi" + +/ { + model = "Gateworks Venice i.MX8MP board"; + compatible = "gateworks,imx8mp-venice", "fsl,imx8mp"; + + chosen { + stdout-path = &uart2; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x0 0x40000000 0 0x80000000>; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + gsc: gsc@20 { + compatible = "gw,gsc"; + reg = <0x20>; + #address-cells = <1>; + #size-cells = <0>; + }; + + eeprom@51 { + compatible = "atmel,24c02"; + reg = <0x51>; + pagesize = <16>; + }; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + eeprom@52 { + compatible = "atmel,24c32"; + reg = <0x52>; + pagesize = <32>; + }; +}; + +/* console */ +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +/* eMMC */ +&usdhc3 { + assigned-clocks = <&clk IMX8MP_CLK_USDHC3>; + assigned-clock-rates = <400000000>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3 + MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c3 + MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c3 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x49 + MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x49 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x166 + >; + }; +}; diff --git a/arch/arm/dts/imx8mp.dtsi b/arch/arm/dts/imx8mp.dtsi index f9d6425..79b6575 100644 --- a/arch/arm/dts/imx8mp.dtsi +++ b/arch/arm/dts/imx8mp.dtsi @@ -4,6 +4,7 @@ */ #include <dt-bindings/clock/imx8mp-clock.h> +#include <dt-bindings/power/imx8mp-power.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> #include <dt-bindings/interrupt-controller/arm-gic.h> @@ -434,6 +435,44 @@ interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; #reset-cells = <1>; }; + + gpc: gpc@303a0000 { + compatible = "fsl,imx8mp-gpc"; + reg = <0x303a0000 0x1000>; + interrupt-parent = <&gic>; + interrupt-controller; + #interrupt-cells = <3>; + + pgc { + #address-cells = <1>; + #size-cells = <0>; + + pgc_pcie_phy: power-domain@1 { + #power-domain-cells = <0>; + reg = <IMX8MP_POWER_DOMAIN_PCIE_PHY>; + }; + + pgc_usb1_phy: power-domain@2 { + #power-domain-cells = <0>; + reg = <IMX8MP_POWER_DOMAIN_USB1_PHY>; + }; + + pgc_usb2_phy: power-domain@3 { + #power-domain-cells = <0>; + reg = <IMX8MP_POWER_DOMAIN_USB2_PHY>; + }; + + pgc_hsiomix: power-domains@17 { + #power-domain-cells = <0>; + reg = <IMX8MP_POWER_DOMAIN_HSIOMIX>; + clocks = <&clk IMX8MP_CLK_HSIO_AXI>, + <&clk IMX8MP_CLK_HSIO_ROOT>; + assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>; + assigned-clock-rates = <500000000>; + }; + }; + }; }; aips2: bus@30400000 { @@ -842,6 +881,28 @@ }; }; + aips4: bus@32c00000 { + compatible = "fsl,aips-bus", "simple-bus"; + reg = <0x32c00000 0x400000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + hsio_blk_ctrl: blk-ctrl@32f10000 { + compatible = "fsl,imx8mp-hsio-blk-ctrl", "syscon"; + reg = <0x32f10000 0x24>; + clocks = <&clk IMX8MP_CLK_USB_ROOT>, + <&clk IMX8MP_CLK_PCIE_ROOT>; + clock-names = "usb", "pcie"; + power-domains = <&pgc_hsiomix>, <&pgc_hsiomix>, + <&pgc_usb1_phy>, <&pgc_usb2_phy>, + <&pgc_hsiomix>, <&pgc_pcie_phy>; + power-domain-names = "bus", "usb", "usb-phy1", + "usb-phy2", "pcie", "pcie-phy"; + #power-domain-cells = <1>; + }; + }; + gic: interrupt-controller@38800000 { compatible = "arm,gic-v3"; reg = <0x38800000 0x10000>, @@ -865,17 +926,20 @@ clock-names = "phy"; assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>; assigned-clock-parents = <&clk IMX8MP_CLK_24M>; + power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY1>; #phy-cells = <0>; status = "disabled"; }; usb3_0: usb@32f10100 { compatible = "fsl,imx8mp-dwc3"; - reg = <0x32f10100 0x8>; + reg = <0x32f10100 0x8>, + <0x381f0000 0x20>; clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, <&clk IMX8MP_CLK_USB_ROOT>; clock-names = "hsio", "suspend"; interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>; #address-cells = <1>; #size-cells = <1>; dma-ranges = <0x40000000 0x40000000 0xc0000000>; @@ -907,16 +971,20 @@ clock-names = "phy"; assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>; assigned-clock-parents = <&clk IMX8MP_CLK_24M>; + power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY2>; #phy-cells = <0>; + status = "disabled"; }; usb3_1: usb@32f10108 { compatible = "fsl,imx8mp-dwc3"; - reg = <0x32f10108 0x8>; + reg = <0x32f10108 0x8>, + <0x382f0000 0x20>; clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, <&clk IMX8MP_CLK_USB_ROOT>; clock-names = "hsio", "suspend"; interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>; #address-cells = <1>; #size-cells = <1>; dma-ranges = <0x40000000 0x40000000 0xc0000000>; diff --git a/arch/arm/dts/imx8mq-evk-u-boot.dtsi b/arch/arm/dts/imx8mq-evk-u-boot.dtsi index 6f9c814..919c1f6 100644 --- a/arch/arm/dts/imx8mq-evk-u-boot.dtsi +++ b/arch/arm/dts/imx8mq-evk-u-boot.dtsi @@ -2,6 +2,34 @@ #include "imx8mq-u-boot.dtsi" +&{/soc@0} { + u-boot,dm-spl; +}; + +&{/soc@0/bus@30000000} { + u-boot,dm-spl; +}; + +&{/soc@0/bus@30400000} { + u-boot,dm-spl; +}; + +&{/soc@0/bus@30800000} { + u-boot,dm-spl; +}; + +&{/soc@0/bus@32c00000} { + u-boot,dm-spl; +}; + +&iomuxc { + u-boot,dm-spl; +}; + +&pinctrl_uart1 { + u-boot,dm-spl; +}; + &usdhc1 { mmc-hs400-1_8v; }; @@ -10,3 +38,7 @@ sd-uhs-sdr104; sd-uhs-ddr50; }; + +&uart1 { + u-boot,dm-spl; +}; diff --git a/arch/arm/include/asm/arch-imx8m/power-domain.h b/arch/arm/include/asm/arch-imx8m/power-domain.h deleted file mode 100644 index 7a833e5..0000000 --- a/arch/arm/include/asm/arch-imx8m/power-domain.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright 2017 NXP - */ - -#ifndef _ASM_ARCH_IMX8M_POWER_DOMAIN_H -#define _ASM_ARCH_IMX8M_POWER_DOMAIN_H - -struct imx8m_power_domain_plat { - int resource_id; - int has_pd; - struct power_domain pd; -}; - -#endif diff --git a/arch/arm/include/asm/arch-mx6/sys_proto.h b/arch/arm/include/asm/arch-mx6/sys_proto.h index c49759a..7845fa8 100644 --- a/arch/arm/include/asm/arch-mx6/sys_proto.h +++ b/arch/arm/include/asm/arch-mx6/sys_proto.h @@ -18,9 +18,6 @@ #define is_usbotg_phy_active(void) (!(readl(USB_PHY0_BASE_ADDR + USBPHY_PWD) & \ USBPHY_PWD_RXPWDRX)) -int imx6_pcie_toggle_power(void); -int imx6_pcie_toggle_reset(struct gpio_desc *gpio, bool active_high); - enum ldo_reg { LDO_ARM, LDO_SOC, diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 9aa1d84..ad0fb36 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -137,7 +137,7 @@ config CMD_NANDBCB config FSL_MFGPROT bool "Support the 'mfgprot' command" - depends on IMX_HAB && ARCH_MX7 + depends on IMX_HAB && (ARCH_MX7 || ARCH_IMX8M) help This option enables the manufacturing protection command which can be used has a protection feature for Manufacturing diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index 77e7270..aa0b644 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -38,8 +38,12 @@ ifeq ($(SOC),$(filter $(SOC),mx7)) obj-y += cpu.o obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o obj-$(CONFIG_ENV_IS_IN_MMC) += mmc_env.o +endif +ifeq ($(SOC),$(filter $(SOC),mx7 imx8m)) +ifneq ($(CONFIG_SPL_BUILD),y) obj-$(CONFIG_FSL_MFGPROT) += cmd_mfgprot.o endif +endif ifeq ($(SOC),$(filter $(SOC),mx5 mx6 mx7)) obj-$(CONFIG_IMX_VIDEO_SKIP) += video.o endif diff --git a/arch/arm/mach-imx/cmd_mfgprot.c b/arch/arm/mach-imx/cmd_mfgprot.c index aed3b2f..ec8a875 100644 --- a/arch/arm/mach-imx/cmd_mfgprot.c +++ b/arch/arm/mach-imx/cmd_mfgprot.c @@ -12,13 +12,11 @@ #include <linux/compiler.h> #include <command.h> #include <common.h> -#include <environment.h> +#include <env.h> #include <fsl_sec.h> #include <mapmem.h> #include <memalign.h> -DECLARE_GLOBAL_DATA_PTR; - /** * do_mfgprot() - Handle the "mfgprot" command-line command * @cmdtp: Command data struct pointer diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig index f969833..5e1b20a 100644 --- a/arch/arm/mach-imx/imx8/Kconfig +++ b/arch/arm/mach-imx/imx8/Kconfig @@ -54,11 +54,6 @@ config TARGET_COLIBRI_IMX8X select BOARD_LATE_INIT select IMX8QXP -config TARGET_APALIS_IMX8X - bool "Support Apalis iMX8X module" - select BOARD_LATE_INIT - select IMX8QXP - config TARGET_DENEB bool "Support i.MX8QXP Capricorn Deneb board" select BOARD_LATE_INIT @@ -105,7 +100,6 @@ source "board/congatec/cgtqmx8/Kconfig" source "board/advantech/imx8qm_rom7720_a1/Kconfig" source "board/toradex/apalis-imx8/Kconfig" source "board/toradex/colibri-imx8x/Kconfig" -source "board/toradex/apalis-imx8x/Kconfig" source "board/siemens/capricorn/Kconfig" config IMX_SNVS_SEC_SC diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig index 55db250..24299ae 100644 --- a/arch/arm/mach-imx/imx8m/Kconfig +++ b/arch/arm/mach-imx/imx8m/Kconfig @@ -97,6 +97,8 @@ config TARGET_IMX8MM_VENICE select IMX8MM select SUPPORT_SPL select IMX8M_LPDDR4 + select GATEWORKS_SC + select MISC config TARGET_KONTRON_MX8MM bool "Kontron Electronics N80xx" @@ -143,6 +145,8 @@ config TARGET_IMX8MN_VENICE select IMX8MN select SUPPORT_SPL select IMX8M_LPDDR4 + select GATEWORKS_SC + select MISC config TARGET_IMX8MP_EVK bool "imx8mp LPDDR4 EVK board" @@ -154,6 +158,15 @@ config TARGET_IMX8MP_EVK select ARCH_MISC_INIT select SPL_CRYPTO if SPL +config TARGET_IMX8MP_VENICE + bool "Support Gateworks Venice iMX8M Plus module" + select BINMAN + select IMX8MP + select SUPPORT_SPL + select IMX8M_LPDDR4 + select GATEWORKS_SC + select MISC + config TARGET_PICO_IMX8MQ bool "Support Technexion Pico iMX8MQ" select BINMAN diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c index 7059d87..8e23e6d 100644 --- a/arch/arm/mach-imx/imx8m/soc.c +++ b/arch/arm/mach-imx/imx8m/soc.c @@ -331,7 +331,7 @@ phys_size_t get_effective_memsize(void) ulong board_get_usable_ram_top(ulong total_size) { - ulong top_addr = PHYS_SDRAM + gd->ram_size; + ulong top_addr; /* * Some IPs have their accessible address space restricted by @@ -339,8 +339,7 @@ ulong board_get_usable_ram_top(ulong total_size) * space below the 4G address boundary (which is 3GiB big), * even when the effective available memory is bigger. */ - if (top_addr > 0x80000000) - top_addr = 0x80000000; + top_addr = clamp_val((u64)PHYS_SDRAM + gd->ram_size, 0, 0xffffffff); /* * rom_pointer[0] stores the TEE memory start address. diff --git a/arch/arm/mach-imx/imx8ulp/clock.c b/arch/arm/mach-imx/imx8ulp/clock.c index 3e71a4f..3e88f46 100644 --- a/arch/arm/mach-imx/imx8ulp/clock.c +++ b/arch/arm/mach-imx/imx8ulp/clock.c @@ -440,10 +440,9 @@ void mxs_set_lcdclk(u32 base_addr, u32 freq_in_khz) debug("PLL4 rate %ukhz\n", pll4_rate); for (pfd = 12; pfd <= 35; pfd++) { - parent_rate = pll4_rate; - parent_rate = parent_rate * 18 / pfd; - for (div = 1; div <= 64; div++) { + parent_rate = pll4_rate; + parent_rate = parent_rate * 18 / pfd; parent_rate = parent_rate / div; for (pcd = 0; pcd < 8; pcd++) { diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index 3d675fc..947b73f 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -227,6 +227,8 @@ config TARGET_GW_VENTANA bool "gw_ventana" depends on MX6QDL select SUPPORT_SPL + select GATEWORKS_SC + select MISC imply CMD_SATA imply CMD_SPL diff --git a/board/bsh/imx8mn_smm_s2/spl.c b/board/bsh/imx8mn_smm_s2/spl.c index 5f04731..0f61acc 100644 --- a/board/bsh/imx8mn_smm_s2/spl.c +++ b/board/bsh/imx8mn_smm_s2/spl.c @@ -40,14 +40,8 @@ void spl_board_init(void) puts("Failed to find clock node. Check device tree\n"); } -#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE) -static const iomux_v3_cfg_t uart_pads[] = { - IMX8MN_PAD_UART4_RXD__UART4_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), - IMX8MN_PAD_UART4_TXD__UART4_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - static const iomux_v3_cfg_t wdog_pads[] = { IMX8MN_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), }; @@ -59,7 +53,6 @@ int board_early_init_f(void) imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); set_wdog_reset(wdog); - imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); init_uart_clk(3); if (IS_ENABLED(CONFIG_NAND_MXS)) { @@ -82,14 +75,14 @@ void board_init_f(ulong dummy) timer_init(); - preloader_console_init(); - ret = spl_init(); if (ret) { debug("spl_init() failed: %d\n", ret); hang(); } + preloader_console_init(); + /* DDR initialization */ spl_dram_init(); diff --git a/board/compulab/imx8mm-cl-iot-gate/imx8mm-cl-iot-gate.c b/board/compulab/imx8mm-cl-iot-gate/imx8mm-cl-iot-gate.c index e6021a4..3d7fff3 100644 --- a/board/compulab/imx8mm-cl-iot-gate/imx8mm-cl-iot-gate.c +++ b/board/compulab/imx8mm-cl-iot-gate/imx8mm-cl-iot-gate.c @@ -335,11 +335,6 @@ static int iot_gate_imx8_update_ext_ied(void) return 0; } -int board_fix_fdt(void *rw_fdt_blob) -{ - return 0; -} - int extension_board_scan(struct list_head *extension_list) { struct extension *extension = NULL; diff --git a/board/freescale/imx8mm_evk/spl.c b/board/freescale/imx8mm_evk/spl.c index cf4882c..7eeec6c 100644 --- a/board/freescale/imx8mm_evk/spl.c +++ b/board/freescale/imx8mm_evk/spl.c @@ -72,14 +72,8 @@ int board_fit_config_name_match(const char *name) } #endif -#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE) -static iomux_v3_cfg_t const uart_pads[] = { - IMX8MM_PAD_UART2_RXD_UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL), - IMX8MM_PAD_UART2_TXD_UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - static iomux_v3_cfg_t const wdog_pads[] = { IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), }; @@ -92,8 +86,6 @@ int board_early_init_f(void) set_wdog_reset(wdog); - imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); - return 0; } @@ -147,8 +139,6 @@ void board_init_f(ulong dummy) timer_init(); - preloader_console_init(); - /* Clear the BSS. */ memset(__bss_start, 0, __bss_end - __bss_start); @@ -166,6 +156,8 @@ void board_init_f(ulong dummy) hang(); } + preloader_console_init(); + enable_tzc380(); power_init_board(); diff --git a/board/freescale/imx8mn_evk/spl.c b/board/freescale/imx8mn_evk/spl.c index dfa81a0..63f335b 100644 --- a/board/freescale/imx8mn_evk/spl.c +++ b/board/freescale/imx8mn_evk/spl.c @@ -115,14 +115,8 @@ int board_fit_config_name_match(const char *name) } #endif -#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE) -static iomux_v3_cfg_t const uart_pads[] = { - IMX8MN_PAD_UART2_RXD__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), - IMX8MN_PAD_UART2_TXD__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - static iomux_v3_cfg_t const wdog_pads[] = { IMX8MN_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), }; @@ -135,8 +129,6 @@ int board_early_init_f(void) set_wdog_reset(wdog); - imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); - return 0; } @@ -152,8 +144,6 @@ void board_init_f(ulong dummy) timer_init(); - preloader_console_init(); - /* Clear the BSS. */ memset(__bss_start, 0, __bss_end - __bss_start); @@ -163,6 +153,8 @@ void board_init_f(ulong dummy) hang(); } + preloader_console_init(); + enable_tzc380(); /* DDR initialization */ diff --git a/board/freescale/imx8mp_evk/imx8mp_evk.c b/board/freescale/imx8mp_evk/imx8mp_evk.c index 62096c2..fb6c61c 100644 --- a/board/freescale/imx8mp_evk/imx8mp_evk.c +++ b/board/freescale/imx8mp_evk/imx8mp_evk.c @@ -20,14 +20,8 @@ DECLARE_GLOBAL_DATA_PTR; -#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE) -static iomux_v3_cfg_t const uart_pads[] = { - MX8MP_PAD_UART2_RXD__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), - MX8MP_PAD_UART2_TXD__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - static iomux_v3_cfg_t const wdog_pads[] = { MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), }; @@ -40,8 +34,6 @@ int board_early_init_f(void) set_wdog_reset(wdog); - imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); - return 0; } diff --git a/board/gateworks/gw_ventana/Kconfig b/board/gateworks/gw_ventana/Kconfig index fee910c..c82e8ae 100644 --- a/board/gateworks/gw_ventana/Kconfig +++ b/board/gateworks/gw_ventana/Kconfig @@ -17,12 +17,4 @@ config CMD_EECONFIG help Provides access to EEPROM configuration on Gateworks Ventana -config CMD_GSC - bool "Enable the 'gsc' command" - help - Provides access to the GSC configuration: - - gsc sleep - sleeps for a period of seconds - gsc wd - enables / disables the watchdog - endif diff --git a/board/gateworks/gw_ventana/Makefile b/board/gateworks/gw_ventana/Makefile index 360d1d4..c407f8e 100644 --- a/board/gateworks/gw_ventana/Makefile +++ b/board/gateworks/gw_ventana/Makefile @@ -6,5 +6,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y := gw_ventana.o gsc.o eeprom.o common.o +obj-y := gw_ventana.o eeprom.o common.o obj-$(CONFIG_SPL_BUILD) += gw_ventana_spl.o diff --git a/board/gateworks/gw_ventana/common.c b/board/gateworks/gw_ventana/common.c index 4144064..74328b2 100644 --- a/board/gateworks/gw_ventana/common.c +++ b/board/gateworks/gw_ventana/common.c @@ -6,15 +6,15 @@ */ #include <common.h> +#include <env.h> +#include <fsl_esdhc_imx.h> +#include <hwconfig.h> #include <log.h> #include <asm/arch/clock.h> #include <asm/arch/mx6-pins.h> #include <asm/arch/sys_proto.h> #include <asm/gpio.h> #include <asm/mach-imx/mxc_i2c.h> -#include <env.h> -#include <fsl_esdhc_imx.h> -#include <hwconfig.h> #include <linux/delay.h> #include "common.h" @@ -1045,7 +1045,7 @@ struct ventana gpio_cfg[GW_UNKNOWN] = { #define SETUP_GPIO_INPUT(gpio, name) \ gpio_request(gpio, name); \ gpio_direction_input(gpio); -void setup_iomux_gpio(int board, struct ventana_board_info *info) +void setup_iomux_gpio(int board) { if (board >= GW_UNKNOWN) return; @@ -1214,8 +1214,6 @@ static struct fsl_esdhc_cfg usdhc_cfg[2]; int board_mmc_init(struct bd_info *bis) { - struct ventana_board_info ventana_info; - int board_type = read_eeprom(CONFIG_I2C_GSC, &ventana_info); int ret; switch (board_type) { @@ -1279,13 +1277,11 @@ int board_mmc_init(struct bd_info *bis) int board_mmc_getcd(struct mmc *mmc) { - struct ventana_board_info ventana_info; struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; - int board = read_eeprom(CONFIG_I2C_GSC, &ventana_info); - int gpio = gpio_cfg[board].mmc_cd; + int gpio = gpio_cfg[board_type].mmc_cd; /* Card Detect */ - switch (board) { + switch (board_type) { case GW560x: /* emmc is always present */ if (cfg->esdhc_base == USDHC2_BASE_ADDR) diff --git a/board/gateworks/gw_ventana/common.h b/board/gateworks/gw_ventana/common.h index 7a60db7..480c667 100644 --- a/board/gateworks/gw_ventana/common.h +++ b/board/gateworks/gw_ventana/common.h @@ -8,7 +8,7 @@ #ifndef _GWVENTANA_COMMON_H_ #define _GWVENTANA_COMMON_H_ -#include "ventana_eeprom.h" +#include "eeprom.h" /* GPIO's common to all baseboards */ #define GP_RS232_EN IMX_GPIO_NR(2, 11) @@ -80,6 +80,6 @@ struct ventana { extern struct ventana gpio_cfg[GW_UNKNOWN]; /* configure gpio iomux/defaults */ -void setup_iomux_gpio(int board, struct ventana_board_info *); +void setup_iomux_gpio(int board); #endif /* #ifndef _GWVENTANA_COMMON_H_ */ diff --git a/board/gateworks/gw_ventana/eeprom.c b/board/gateworks/gw_ventana/eeprom.c index c3a2bbe..e622a9b 100644 --- a/board/gateworks/gw_ventana/eeprom.c +++ b/board/gateworks/gw_ventana/eeprom.c @@ -4,23 +4,211 @@ * Author: Tim Harvey <tharvey@gateworks.com> */ -#include <common.h> #include <command.h> -#include <errno.h> +#include <common.h> +#include <gsc.h> #include <hexdump.h> #include <i2c.h> -#include <log.h> -#include <malloc.h> -#include <asm/bitops.h> -#include <linux/delay.h> +#include <asm/arch/sys_proto.h> +#include <dm/device.h> #include <dm/uclass.h> +#include <linux/ctype.h> +#include <linux/delay.h> + +#include "eeprom.h" + +/* + * EEPROM board info struct populated by read_eeprom so that we only have to + * read it once. + */ +struct ventana_board_info ventana_info; +int board_type; + +#if CONFIG_IS_ENABLED(DM_I2C) +struct udevice *i2c_get_dev(int busno, int slave) +{ + struct udevice *dev, *bus; + int ret; + + ret = uclass_get_device_by_seq(UCLASS_I2C, busno, &bus); + if (ret) + return NULL; + ret = dm_i2c_probe(bus, slave, 0, &dev); + if (ret) + return NULL; + + return dev; +} +#endif + +/* + * The Gateworks System Controller will fail to ACK a master transaction if + * it is busy, which can occur during its 1HZ timer tick while reading ADC's. + * When this does occur, it will never be busy long enough to fail more than + * 2 back-to-back transfers. Thus we wrap i2c_read and i2c_write with + * 3 retries. + */ +int gsc_i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len) +{ + int retry = 3; + int n = 0; + int ret; +#if CONFIG_IS_ENABLED(DM_I2C) + struct udevice *dev; + + dev = i2c_get_dev(BOARD_EEPROM_BUSNO, chip); + if (!dev) + return -ENODEV; + ret = i2c_set_chip_offset_len(dev, alen); + if (ret) { + puts("EEPROM: Failed to set alen\n"); + return ret; + } +#else + i2c_set_bus_num(BOARD_EEPROM_BUSNO); +#endif + + while (n++ < retry) { +#if CONFIG_IS_ENABLED(DM_I2C) + ret = dm_i2c_read(dev, addr, buf, len); +#else + ret = i2c_read(chip, addr, alen, buf, len); +#endif + if (!ret) + break; + debug("%s: 0x%02x 0x%02x retry%d: %d\n", __func__, chip, addr, + n, ret); + if (ret != -ENODEV) + break; + mdelay(10); + } + return ret; +} + +int gsc_i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len) +{ + int retry = 3; + int n = 0; + int ret; +#if CONFIG_IS_ENABLED(DM_I2C) + struct udevice *dev; + + dev = i2c_get_dev(BOARD_EEPROM_BUSNO, chip); + if (!dev) + return -ENODEV; + ret = i2c_set_chip_offset_len(dev, alen); + if (ret) { + puts("EEPROM: Failed to set alen\n"); + return ret; + } +#endif + + while (n++ < retry) { +#if CONFIG_IS_ENABLED(DM_I2C) + ret = dm_i2c_write(dev, addr, buf, len); +#else + ret = i2c_write(chip, addr, alen, buf, len); +#endif + if (!ret) + break; + debug("%s: 0x%02x 0x%02x retry%d: %d\n", __func__, chip, addr, + n, ret); + if (ret != -ENODEV) + break; + mdelay(10); + } + mdelay(100); + return ret; +} + +/* determine BOM revision from model */ +int get_bom_rev(const char *str) +{ + int rev_bom = 0; + int i; + + for (i = strlen(str) - 1; i > 0; i--) { + if (str[i] == '-') + break; + if (str[i] >= '1' && str[i] <= '9') { + rev_bom = str[i] - '0'; + break; + } + } + return rev_bom; +} -#include "gsc.h" -#include "ventana_eeprom.h" +/* determine PCB revision from model */ +char get_pcb_rev(const char *str) +{ + char rev_pcb = 'A'; + int i; + for (i = strlen(str) - 1; i > 0; i--) { + if (str[i] == '-') + break; + if (str[i] >= 'A') { + rev_pcb = str[i]; + break; + } + } + return rev_pcb; +} + +/* + * get dt name based on model and detail level: + */ +const char *gsc_get_dtb_name(int level, char *buf, int sz) +{ + const char *model = (const char *)ventana_info.model; + const char *pre = is_mx6dq() ? "imx6q-" : "imx6dl-"; + int modelno, rev_pcb, rev_bom; + + /* a few board models are dt equivalents to other models */ + if (strncasecmp(model, "gw5906", 6) == 0) + model = "gw552x-d"; + else if (strncasecmp(model, "gw5908", 6) == 0) + model = "gw53xx-f"; + else if (strncasecmp(model, "gw5905", 6) == 0) + model = "gw5904-a"; + + modelno = ((model[2] - '0') * 1000) + + ((model[3] - '0') * 100) + + ((model[4] - '0') * 10) + + (model[5] - '0'); + rev_pcb = tolower(get_pcb_rev(model)); + rev_bom = get_bom_rev(model); + + /* compare model/rev/bom in order of most specific to least */ + snprintf(buf, sz, "%s%04d", pre, modelno); + switch (level) { + case 0: /* full model first (ie gw5400-a1) */ + if (rev_bom) { + snprintf(buf, sz, "%sgw%04d-%c%d", pre, modelno, rev_pcb, rev_bom); + break; + } + fallthrough; + case 1: /* don't care about bom rev (ie gw5400-a) */ + snprintf(buf, sz, "%sgw%04d-%c", pre, modelno, rev_pcb); + break; + case 2: /* don't care about the pcb rev (ie gw5400) */ + snprintf(buf, sz, "%sgw%04d", pre, modelno); + break; + case 3: /* look for generic model (ie gw540x) */ + snprintf(buf, sz, "%sgw%03dx", pre, modelno / 10); + break; + case 4: /* look for more generic model (ie gw54xx) */ + snprintf(buf, sz, "%sgw%02dxx", pre, modelno / 100); + break; + default: /* give up */ + return NULL; + } + + return buf; +} /* read ventana EEPROM, check for validity, and return baseboard type */ int -read_eeprom(int bus, struct ventana_board_info *info) +read_eeprom(struct ventana_board_info *info) { int i; int chksum; @@ -30,29 +218,8 @@ read_eeprom(int bus, struct ventana_board_info *info) memset(info, 0, sizeof(*info)); - /* - * On a board with a missing/depleted backup battery for GSC, the - * board may be ready to probe the GSC before its firmware is - * running. We will wait here indefinately for the GSC/EEPROM. - */ -#if CONFIG_IS_ENABLED(DM_I2C) - while (1) { - if (i2c_get_dev(bus, GSC_EEPROM_ADDR)) - break; - mdelay(1); - } -#else - while (1) { - if (0 == i2c_set_bus_num(bus) && - 0 == i2c_probe(GSC_EEPROM_ADDR)) - break; - mdelay(1); - } -#endif - /* read eeprom config section */ - mdelay(10); - if (gsc_i2c_read(GSC_EEPROM_ADDR, 0x00, 1, buf, sizeof(*info))) { + if (gsc_i2c_read(BOARD_EEPROM_ADDR, 0x00, 1, buf, sizeof(*info))) { puts("EEPROM: Failed to read EEPROM\n"); return GW_UNKNOWN; } @@ -219,14 +386,14 @@ static int do_econfig(struct cmd_tbl *cmdtp, int flag, int argc, info->chksum[1] = chksum & 0xff; /* write new config data */ - if (gsc_i2c_write(GSC_EEPROM_ADDR, info->config - (u8 *)info, + if (gsc_i2c_write(BOARD_EEPROM_ADDR, info->config - (u8 *)info, 1, econfig_bytes, sizeof(econfig_bytes))) { printf("EEPROM: Failed updating config\n"); return CMD_RET_FAILURE; } /* write new config data */ - if (gsc_i2c_write(GSC_EEPROM_ADDR, info->chksum - (u8 *)info, + if (gsc_i2c_write(BOARD_EEPROM_ADDR, info->chksum - (u8 *)info, 1, info->chksum, 2)) { printf("EEPROM: Failed updating checksum\n"); return CMD_RET_FAILURE; diff --git a/board/gateworks/gw_ventana/ventana_eeprom.h b/board/gateworks/gw_ventana/eeprom.h index 2d5c272..2354205 100644 --- a/board/gateworks/gw_ventana/ventana_eeprom.h +++ b/board/gateworks/gw_ventana/eeprom.h @@ -6,6 +6,9 @@ #ifndef _VENTANA_EEPROM_ #define _VENTANA_EEPROM_ +#define BOARD_EEPROM_BUSNO 0 +#define BOARD_EEPROM_ADDR 0x51 + struct ventana_board_info { u8 mac0[6]; /* 0x00: MAC1 */ u8 mac1[6]; /* 0x06: MAC2 */ @@ -137,7 +140,18 @@ struct ventana_eeprom_config { extern struct ventana_eeprom_config econfig[]; extern struct ventana_board_info ventana_info; +extern int board_type; + +int read_eeprom(struct ventana_board_info *info); -int read_eeprom(int bus, struct ventana_board_info *); +/* + * I2C transactions to the GSC are done via these functions which + * perform retries in the case of a busy GSC NAK'ing the transaction + */ +int gsc_i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len); +int gsc_i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len); +const char *gsc_get_dtb_name(int level, char *buf, int sz); +struct udevice *i2c_get_dev(int busno, int slave); +const char *eeprom_get_model(void); #endif diff --git a/board/gateworks/gw_ventana/gsc.h b/board/gateworks/gw_ventana/gsc.h deleted file mode 100644 index 2e1d25b..0000000 --- a/board/gateworks/gw_ventana/gsc.h +++ /dev/null @@ -1,72 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2013 Gateworks Corporation - * - * Author: Tim Harvey <tharvey@gateworks.com> - */ - -#ifndef __ASSEMBLY__ - -/* i2c slave addresses */ -#define GSC_SC_ADDR 0x20 -#define GSC_RTC_ADDR 0x68 -#define GSC_HWMON_ADDR 0x29 -#define GSC_EEPROM_ADDR 0x51 - -/* System Controller registers */ -enum { - GSC_SC_CTRL0 = 0x00, - GSC_SC_CTRL1 = 0x01, - GSC_SC_STATUS = 0x0a, - GSC_SC_FWCRC = 0x0c, - GSC_SC_FWVER = 0x0e, -}; - -/* System Controller Control1 bits */ -enum { - GSC_SC_CTRL1_WDTIME = 4, /* 1 = 60s timeout, 0 = 30s timeout */ - GSC_SC_CTRL1_WDEN = 5, /* 1 = enable, 0 = disable */ - GSC_SC_CTRL1_WDDIS = 7, /* 1 = disable boot watchdog */ -}; - -/* System Controller Interrupt bits */ -enum { - GSC_SC_IRQ_PB = 0, /* Pushbutton switch */ - GSC_SC_IRQ_SECURE = 1, /* Secure Key erase operation complete */ - GSC_SC_IRQ_EEPROM_WP = 2, /* EEPROM write violation */ - GSC_SC_IRQ_GPIO = 4, /* GPIO change */ - GSC_SC_IRQ_TAMPER = 5, /* Tamper detect */ - GSC_SC_IRQ_WATCHDOG = 6, /* Watchdog trip */ - GSC_SC_IRQ_PBLONG = 7, /* Pushbutton long hold */ -}; - -/* Hardware Monitor registers */ -enum { - GSC_HWMON_TEMP = 0x00, - GSC_HWMON_VIN = 0x02, - GSC_HWMON_VDD_3P3 = 0x05, - GSC_HWMON_VBATT = 0x08, - GSC_HWMON_VDD_5P0 = 0x0b, - GSC_HWMON_VDD_CORE = 0x0e, - GSC_HWMON_VDD_SOC = 0x11, - GSC_HWMON_VDD_HIGH = 0x14, - GSC_HWMON_VDD_DDR = 0x17, - GSC_HWMON_VDD_EXT = 0x1a, - GSC_HWMON_VDD_1P8 = 0x1d, - GSC_HWMON_VDD_IO2 = 0x20, - GSC_HWMON_VDD_2P5 = 0x23, - GSC_HWMON_VDD_IO3 = 0x26, - GSC_HWMON_VDD_IO4 = 0x29, -}; - -/* - * I2C transactions to the GSC are done via these functions which - * perform retries in the case of a busy GSC NAK'ing the transaction - */ -int gsc_i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len); -int gsc_i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len); -int gsc_info(int verbose); -int gsc_boot_wd_disable(void); -const char *gsc_get_dtb_name(int level, char *buf, int sz); -struct udevice *i2c_get_dev(int busno, int slave); -#endif diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c index 8748878..c06630a 100644 --- a/board/gateworks/gw_ventana/gw_ventana.c +++ b/board/gateworks/gw_ventana/gw_ventana.c @@ -5,40 +5,29 @@ * Author: Tim Harvey <tharvey@gateworks.com> */ +#include <command.h> #include <common.h> +#include <fdt_support.h> +#include <gsc.h> +#include <hwconfig.h> +#include <i2c.h> +#include <miiphy.h> +#include <mtd_node.h> #include <asm/arch/clock.h> #include <asm/arch/crm_regs.h> #include <asm/arch/mx6-pins.h> #include <asm/arch/mxc_hdmi.h> #include <asm/arch/sys_proto.h> -#include <asm/global_data.h> -#include <asm/gpio.h> #include <asm/mach-imx/boot_mode.h> #include <asm/mach-imx/video.h> -#include <asm/setup.h> -#include <env.h> -#include <hwconfig.h> +#include <jffs2/load_kernel.h> #include <linux/ctype.h> -#include <miiphy.h> -#include <mtd_node.h> #include <linux/delay.h> -#include <power/pmic.h> -#include <fdt_support.h> -#include <jffs2/load_kernel.h> -#include "gsc.h" #include "common.h" DECLARE_GLOBAL_DATA_PTR; - -/* - * EEPROM board info struct populated by read_eeprom so that we only have to - * read it once. - */ -struct ventana_board_info ventana_info; -static int board_type; - /* configure eth0 PHY board-specific LED behavior */ int board_phy_config(struct phy_device *phydev) { @@ -482,9 +471,12 @@ int board_init(void) gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; /* read Gateworks EEPROM into global struct (used later) */ - board_type = read_eeprom(CONFIG_I2C_GSC, &ventana_info); + board_type = read_eeprom(&ventana_info); - setup_iomux_gpio(board_type, &ventana_info); + setup_iomux_gpio(board_type); + + /* show GSC details */ + run_command("gsc", 0); return 0; } @@ -517,7 +509,6 @@ int board_fit_config_name_match(const char *name) int checkboard(void) { struct ventana_board_info *info = &ventana_info; - unsigned char buf[4]; const char *p; int quiet; /* Quiet or minimal output mode */ @@ -541,15 +532,6 @@ int checkboard(void) if (quiet) return 0; - /* Display GSC firmware revision/CRC/status */ - gsc_info(0); - - /* Display RTC */ - if (!gsc_i2c_read(GSC_RTC_ADDR, 0x00, 1, buf, 4)) { - printf("RTC: %d\n", - buf[0] | buf[1]<<8 | buf[2]<<16 | buf[3]<<24); - } - return 0; } #endif diff --git a/board/gateworks/gw_ventana/gw_ventana_spl.c b/board/gateworks/gw_ventana/gw_ventana_spl.c index 3149e88..e85a009 100644 --- a/board/gateworks/gw_ventana/gw_ventana_spl.c +++ b/board/gateworks/gw_ventana/gw_ventana_spl.c @@ -6,26 +6,22 @@ #include <common.h> #include <env.h> +#include <gsc.h> #include <hang.h> +#include <i2c.h> #include <init.h> -#include <log.h> -#include <asm/io.h> +#include <spl.h> #include <asm/arch/crm_regs.h> #include <asm/arch/mx6-ddr.h> #include <asm/arch/mx6-pins.h> #include <asm/arch/sys_proto.h> -#include <asm/mach-imx/boot_mode.h> -#include <asm/mach-imx/iomux-v3.h> #include <asm/mach-imx/mxc_i2c.h> -#include <env.h> -#include <i2c.h> -#include <spl.h> +#include <linux/delay.h> +#include <power/mp5416.h> #include <power/pmic.h> -#include <power/ltc3676_pmic.h> #include <power/pfuze100_pmic.h> -#include <power/mp5416.h> +#include <power/ltc3676_pmic.h> -#include "gsc.h" #include "common.h" #define RTT_NOM_120OHM /* use 120ohm Rtt_nom vs 60ohm (lower power) */ @@ -778,8 +774,6 @@ static void setup_ventana_i2c(int i2c) void setup_pmic(void) { struct pmic *p; - struct ventana_board_info ventana_info; - int board = read_eeprom(CONFIG_I2C_GSC, &ventana_info); const int i2c_pmic = 1; u32 reg; char rev; @@ -817,7 +811,7 @@ void setup_pmic(void) reg |= (SWBST_5_00V | (SWBST_MODE_AUTO << SWBST_MODE_SHIFT)); pmic_reg_write(p, PFUZE100_SWBSTCON1, reg); - if (board == GW54xx && (rev == 'G')) { + if (board_type == GW54xx && (rev == 'G')) { /* Disable VGEN5 */ pmic_reg_write(p, PFUZE100_VGEN5VOL, 0); @@ -873,7 +867,7 @@ void setup_pmic(void) * is a bit shy of the Vmin of 1350mV in the datasheet * for LDO enabled mode but is as high as we can go. */ - switch (board) { + switch (board_type) { case GW560x: /* mask PGOOD during SW3 transition */ pmic_reg_write(p, LTC3676_DVB3B, @@ -931,7 +925,7 @@ void setup_pmic(void) /* configure MP5416 PMIC */ else if (!i2c_probe(0x69)) { puts("PMIC: MP5416\n"); - switch (board) { + switch (board_type) { case GW5910: /* SW1: VDD_ARM 1.2V -> (1.275 to 1.475) */ reg = MP5416_VSET_EN | MP5416_VSET_SW1_SVAL(1475000); @@ -974,11 +968,23 @@ void board_init_f(ulong dummy) /* UART clocks enabled and gd valid - init serial console */ preloader_console_init(); + /* + * On a board with a missing/depleted backup battery for GSC, the + * board may be ready to probe the GSC before its firmware is + * running. We will wait here indefinately for the GSC/EEPROM. + */ + while (1) { + if (!i2c_set_bus_num(BOARD_EEPROM_BUSNO) && + !i2c_probe(BOARD_EEPROM_ADDR)) + break; + mdelay(1); + } + /* read/validate EEPROM info to determine board model and SDRAM cfg */ - board_model = read_eeprom(CONFIG_I2C_GSC, &ventana_info); + board_model = read_eeprom(&ventana_info); /* configure model-specific gpio */ - setup_iomux_gpio(board_model, &ventana_info); + setup_iomux_gpio(board_model); /* provide some some default: 32bit 128MB */ if (GW_UNKNOWN == board_model) @@ -1006,7 +1012,6 @@ void board_boot_order(u32 *spl_boot_list) /* called from board_init_r after gd setup if CONFIG_SPL_BOARD_INIT defined */ /* its our chance to print info about boot device */ -static int board_type; void spl_board_init(void) { u32 boot_device; @@ -1015,7 +1020,7 @@ void spl_board_init(void) boot_device = spl_boot_device(); /* read eeprom again now that we have gd */ - board_type = read_eeprom(CONFIG_I2C_GSC, &ventana_info); + board_type = read_eeprom(&ventana_info); if (board_type == GW_UNKNOWN) hang(); diff --git a/board/gateworks/venice/Kconfig b/board/gateworks/venice/Kconfig index 3034275..9d083dc 100644 --- a/board/gateworks/venice/Kconfig +++ b/board/gateworks/venice/Kconfig @@ -27,3 +27,18 @@ config SYS_CONFIG_NAME config IMX_CONFIG default "board/gateworks/venice/imximage-8mn-lpddr4.cfg" endif + +if TARGET_IMX8MP_VENICE + +config SYS_BOARD + default "venice" + +config SYS_VENDOR + default "gateworks" + +config SYS_CONFIG_NAME + default "imx8mp_venice" + +config IMX_CONFIG + default "board/gateworks/venice/imximage-8mp-lpddr4.cfg" +endif diff --git a/board/gateworks/venice/Makefile b/board/gateworks/venice/Makefile index b8b53fd..faf1348 100644 --- a/board/gateworks/venice/Makefile +++ b/board/gateworks/venice/Makefile @@ -4,7 +4,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y += venice.o gsc.o +obj-y += venice.o eeprom.o ifdef CONFIG_SPL_BUILD obj-y += spl.o @@ -14,4 +14,7 @@ endif ifdef CONFIG_IMX8MN obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing_imx8mn.o endif +ifdef CONFIG_IMX8MP +obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing_imx8mp.o +endif endif diff --git a/board/gateworks/venice/eeprom.c b/board/gateworks/venice/eeprom.c new file mode 100644 index 0000000..7a46f44 --- /dev/null +++ b/board/gateworks/venice/eeprom.c @@ -0,0 +1,363 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2021 Gateworks Corporation + */ + +#include <common.h> +#include <gsc.h> +#include <hexdump.h> +#include <i2c.h> +#include <dm/uclass.h> + +#include "eeprom.h" + +/* I2C */ +#define SOM_EEPROM_BUSNO 0 +#define SOM_EEPROM_ADDR 0x51 +#define BASEBOARD_EEPROM_BUSNO 1 +#define BASEBOARD_EEPROM_ADDR 0x52 + +struct venice_board_info som_info; +struct venice_board_info base_info; +char venice_model[32]; +u32 venice_serial; + +/* return a mac address from EEPROM info */ +int eeprom_getmac(int index, uint8_t *address) +{ + int i, j; + u32 maclow, machigh; + u64 mac; + + j = 0; + if (som_info.macno) { + maclow = som_info.mac[5]; + maclow |= som_info.mac[4] << 8; + maclow |= som_info.mac[3] << 16; + maclow |= som_info.mac[2] << 24; + machigh = som_info.mac[1]; + machigh |= som_info.mac[0] << 8; + mac = machigh; + mac <<= 32; + mac |= maclow; + for (i = 0; i < som_info.macno; i++, j++) { + if (index == j) + goto out; + } + } + + maclow = base_info.mac[5]; + maclow |= base_info.mac[4] << 8; + maclow |= base_info.mac[3] << 16; + maclow |= base_info.mac[2] << 24; + machigh = base_info.mac[1]; + machigh |= base_info.mac[0] << 8; + mac = machigh; + mac <<= 32; + mac |= maclow; + for (i = 0; i < base_info.macno; i++, j++) { + if (index == j) + goto out; + } + + return -EINVAL; + +out: + mac += i; + address[0] = (mac >> 40) & 0xff; + address[1] = (mac >> 32) & 0xff; + address[2] = (mac >> 24) & 0xff; + address[3] = (mac >> 16) & 0xff; + address[4] = (mac >> 8) & 0xff; + address[5] = (mac >> 0) & 0xff; + + return 0; +} + +static int eeprom_read(int busno, int slave, int alen, struct venice_board_info *info) +{ + int i; + int chksum; + unsigned char *buf = (unsigned char *)info; + struct udevice *dev, *bus; + int ret; + + /* probe device */ + ret = uclass_get_device_by_seq(UCLASS_I2C, busno, &bus); + if (ret) + return ret; + ret = dm_i2c_probe(bus, slave, 0, &dev); + if (ret) + return ret; + + /* read eeprom config section */ + memset(info, 0, sizeof(*info)); + ret = i2c_set_chip_offset_len(dev, alen); + if (ret) { + puts("EEPROM: Failed to set alen\n"); + return ret; + } + ret = dm_i2c_read(dev, 0x00, buf, sizeof(*info)); + if (ret) { + if (slave == SOM_EEPROM_ADDR) + printf("EEPROM: Failed to read EEPROM\n"); + return ret; + } + + /* validate checksum */ + for (chksum = 0, i = 0; i < (int)sizeof(*info) - 2; i++) + chksum += buf[i]; + if ((info->chksum[0] != chksum >> 8) || + (info->chksum[1] != (chksum & 0xff))) { + printf("EEPROM: I2C%d@0x%02x: Invalid Checksum\n", busno, slave); + print_hex_dump_bytes("", DUMP_PREFIX_NONE, buf, sizeof(*info)); + memset(info, 0, sizeof(*info)); + return -EINVAL; + } + + /* sanity check valid model */ + if (info->model[0] != 'G' || info->model[1] != 'W') { + printf("EEPROM: I2C%d@0x%02x: Invalid Model in EEPROM\n", busno, slave); + print_hex_dump_bytes("", DUMP_PREFIX_NONE, buf, sizeof(*info)); + memset(info, 0, sizeof(*info)); + return -EINVAL; + } + + return 0; +} + +/* determine BOM revision from model */ +int get_bom_rev(const char *str) +{ + int rev_bom = 0; + int i; + + for (i = strlen(str) - 1; i > 0; i--) { + if (str[i] == '-') + break; + if (str[i] >= '1' && str[i] <= '9') { + rev_bom = str[i] - '0'; + break; + } + } + return rev_bom; +} + +/* determine PCB revision from model */ +char get_pcb_rev(const char *str) +{ + char rev_pcb = 'A'; + int i; + + for (i = strlen(str) - 1; i > 0; i--) { + if (str[i] == '-') + break; + if (str[i] >= 'A') { + rev_pcb = str[i]; + break; + } + } + return rev_pcb; +} + +/* + * get dt name based on model and detail level: + * + * For boards that are a combination of a SoM plus a Baseboard: + * Venice SoM part numbers are GW70xx where xx is: + * 7000-7019: same PCB with som dt of '0x' + * 7020-7039: same PCB with som dt of '2x' + * 7040-7059: same PCB with som dt of '4x' + * 7060-7079: same PCB with som dt of '6x' + * 7080-7099: same PCB with som dt of '8x' + * Venice Baseboard part numbers are GW7xxx where xxx is: + * 7100-7199: same PCB with base dt of '71xx' + * 7200-7299: same PCB with base dt of '72xx' + * 7300-7399: same PCB with base dt of '73xx' + * 7400-7499: same PCB with base dt of '74xx' + * 7500-7599: same PCB with base dt of '75xx' + * 7600-7699: same PCB with base dt of '76xx' + * 7700-7799: same PCB with base dt of '77xx' + * 7800-7899: same PCB with base dt of '78xx' + * DT name is comprised of: + * gw<base dt>-<som dt>-[base-pcb-rev][base-bom-rev][som-pcb-rev][som-bom-rev] + * + * For board models from 7900-7999 each PCB is unique with its own dt: + * DT name is comprised: + * gw<model>-[pcb-rev][bom-rev] + * + */ +#define snprintfcat(dest, sz, fmt, ...) \ + snprintf((dest) + strlen(dest), (sz) - strlen(dest), fmt, ##__VA_ARGS__) +const char *eeprom_get_dtb_name(int level, char *buf, int sz) +{ +#ifdef CONFIG_IMX8MM + const char *pre = "imx8mm-venice-gw"; +#elif CONFIG_IMX8MN + const char *pre = "imx8mn-venice-gw"; +#elif CONFIG_IMX8MP + const char *pre = "imx8mp-venice-gw"; +#endif + int model, rev_pcb, rev_bom; + + model = ((som_info.model[2] - '0') * 1000) + + ((som_info.model[3] - '0') * 100) + + ((som_info.model[4] - '0') * 10) + + (som_info.model[5] - '0'); + rev_pcb = tolower(get_pcb_rev(som_info.model)); + rev_bom = get_bom_rev(som_info.model); + + /* som + baseboard*/ + if (base_info.model[0]) { + /* baseboard id: 7100-7199->71; 7200-7299->72; etc */ + int base = ((base_info.model[2] - '0') * 10) + (base_info.model[3] - '0'); + /* som id: 7000-7019->1; 7020-7039->2; etc */ + int som = ((model % 100) / 20) * 2; + int rev_base_pcb = tolower(get_pcb_rev(base_info.model)); + int rev_base_bom = get_bom_rev(base_info.model); + + snprintf(buf, sz, "%s%2dxx-%dx", pre, base, som); + switch (level) { + case 0: /* full model (ie gw73xx-0x-a1a1) */ + if (rev_base_bom) + snprintfcat(buf, sz, "-%c%d", rev_base_pcb, rev_base_bom); + else + snprintfcat(buf, sz, "-%c", rev_base_pcb); + if (rev_bom) + snprintfcat(buf, sz, "%c%d", rev_pcb, rev_bom); + else + snprintfcat(buf, sz, "%c", rev_pcb); + break; + case 1: /* don't care about SoM revision */ + if (rev_base_bom) + snprintfcat(buf, sz, "-%c%d", rev_base_pcb, rev_base_bom); + else + snprintfcat(buf, sz, "-%c", rev_base_pcb); + snprintfcat(buf, sz, "xx"); + break; + case 2: /* don't care about baseboard revision */ + snprintfcat(buf, sz, "-xx"); + if (rev_bom) + snprintfcat(buf, sz, "%c%d", rev_pcb, rev_bom); + else + snprintfcat(buf, sz, "%c", rev_pcb); + break; + case 3: /* don't care about SoM/baseboard revision */ + break; + default: + return NULL; + } + } else { + snprintf(buf, sz, "%s%04d", pre, model); + switch (level) { + case 0: /* full model wth PCB and BOM revision first (ie gw7901-a1) */ + if (rev_bom) + snprintfcat(buf, sz, "-%c%d", rev_pcb, rev_bom); + else + snprintfcat(buf, sz, "-%c", rev_pcb); + break; + case 1: /* don't care about BOM revision */ + snprintfcat(buf, sz, "-%c", rev_pcb); + break; + case 2: /* don't care about PCB or BOM revision */ + break; + case 3: /* don't care about last digit of model */ + buf[strlen(buf) - 1] = 'x'; + break; + case 4: /* don't care about last two digits of model */ + buf[strlen(buf) - 1] = 'x'; + buf[strlen(buf) - 2] = 'x'; + break; + default: + return NULL; + break; + } + } + + return buf; +} + +static int eeprom_info(bool verbose) +{ + printf("Model : %s\n", venice_model); + printf("Serial : %d\n", som_info.serial); + printf("MFGDate : %02x-%02x-%02x%02x\n", + som_info.mfgdate[0], som_info.mfgdate[1], + som_info.mfgdate[2], som_info.mfgdate[3]); + if (base_info.model[0] && verbose) { + printf("SOM : %s %d %02x-%02x-%02x%02x\n", + som_info.model, som_info.serial, + som_info.mfgdate[0], som_info.mfgdate[1], + som_info.mfgdate[2], som_info.mfgdate[3]); + printf("BASE : %s %d %02x-%02x-%02x%02x\n", + base_info.model, base_info.serial, + base_info.mfgdate[0], base_info.mfgdate[1], + base_info.mfgdate[2], base_info.mfgdate[3]); + } + + return 0; +} + +int eeprom_init(int quiet) +{ + char rev_pcb; + int rev_bom; + int ret; + + ret = eeprom_read(SOM_EEPROM_BUSNO, SOM_EEPROM_ADDR, 1, &som_info); + if (ret) { + puts("ERROR: Failed to probe EEPROM\n"); + memset(&som_info, 0, sizeof(som_info)); + return 0; + } + + /* read optional baseboard EEPROM */ + eeprom_read(BASEBOARD_EEPROM_BUSNO, BASEBOARD_EEPROM_ADDR, 2, &base_info); + + /* create model strings */ + if (base_info.model[0]) { + sprintf(venice_model, "GW%c%c%c%c-%c%c-", + som_info.model[2], /* family */ + base_info.model[3], /* baseboard */ + base_info.model[4], base_info.model[5], /* subload of baseboard */ + som_info.model[4], som_info.model[5]); /* last 2digits of SOM */ + + /* baseboard revision */ + rev_pcb = get_pcb_rev(base_info.model); + rev_bom = get_bom_rev(base_info.model); + if (rev_bom) + sprintf(venice_model + strlen(venice_model), "%c%d", rev_pcb, rev_bom); + else + sprintf(venice_model + strlen(venice_model), "%c", rev_pcb); + /* som revision */ + rev_pcb = get_pcb_rev(som_info.model); + rev_bom = get_bom_rev(som_info.model); + if (rev_bom) + sprintf(venice_model + strlen(venice_model), "%c%d", rev_pcb, rev_bom); + else + sprintf(venice_model + strlen(venice_model), "%c", rev_pcb); + } else { + strcpy(venice_model, som_info.model); + } + venice_serial = som_info.serial; + + if (!quiet) + eeprom_info(false); + + return (16 << som_info.sdram_size); +} + +void board_gsc_info(void) +{ + eeprom_info(true); +} + +const char *eeprom_get_model(void) +{ + return venice_model; +} + +u32 eeprom_get_serial(void) +{ + return venice_serial; +} diff --git a/board/gateworks/venice/gsc.h b/board/gateworks/venice/eeprom.h index b391b2e..37bfe76 100644 --- a/board/gateworks/venice/gsc.h +++ b/board/gateworks/venice/eeprom.h @@ -3,19 +3,8 @@ * Copyright 2021 Gateworks Corporation */ -#ifndef _GSC_H_ -#define _GSC_H_ - -/* I2C bus numbers */ -#define GSC_BUSNO 0 -#define BASEBOARD_EEPROM_BUSNO 1 - -/* I2C slave addresses */ -#define GSC_SC_ADDR 0x20 -#define GSC_RTC_ADDR 0x68 -#define GSC_HWMON_ADDR 0x29 -#define GSC_EEPROM_ADDR 0x51 -#define BASEBOARD_EEPROM_ADDR 0x52 +#ifndef _VENICE_EEPROM_H_ +#define _VENICE_EEPROM_H_ struct venice_board_info { u8 mac[6]; /* 0x00: MAC base */ @@ -35,11 +24,10 @@ struct venice_board_info { u8 chksum[2]; /* 0x4E */ }; -int gsc_init(int quiet); -int gsc_hwmon(void); -const char *gsc_get_model(void); -const char *gsc_get_dtb_name(int level, char *buf, int len); -int gsc_getmac(int index, uint8_t *enetaddr); -uint32_t gsc_get_serial(void); +int eeprom_init(int quiet); +const char *eeprom_get_model(void); +const char *eeprom_get_dtb_name(int level, char *buf, int len); +int eeprom_getmac(int index, uint8_t *enetaddr); +uint32_t eeprom_get_serial(void); #endif diff --git a/board/gateworks/venice/gsc.c b/board/gateworks/venice/gsc.c deleted file mode 100644 index 763b89b..0000000 --- a/board/gateworks/venice/gsc.c +++ /dev/null @@ -1,700 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2021 Gateworks Corporation - */ - -#include <common.h> -#include <command.h> -#include <hang.h> -#include <hexdump.h> -#include <i2c.h> -#include <linux/delay.h> -#include <dm/uclass.h> - -#include "gsc.h" - -DECLARE_GLOBAL_DATA_PTR; - -struct venice_board_info som_info; -struct venice_board_info base_info; -char venice_model[32]; -uint32_t venice_serial; - -/* return a mac address from EEPROM info */ -int gsc_getmac(int index, uint8_t *address) -{ - int i, j; - u32 maclow, machigh; - u64 mac; - - j = 0; - if (som_info.macno) { - maclow = som_info.mac[5]; - maclow |= som_info.mac[4] << 8; - maclow |= som_info.mac[3] << 16; - maclow |= som_info.mac[2] << 24; - machigh = som_info.mac[1]; - machigh |= som_info.mac[0] << 8; - mac = machigh; - mac <<= 32; - mac |= maclow; - for (i = 0; i < som_info.macno; i++, j++) { - if (index == j) - goto out; - } - } - - maclow = base_info.mac[5]; - maclow |= base_info.mac[4] << 8; - maclow |= base_info.mac[3] << 16; - maclow |= base_info.mac[2] << 24; - machigh = base_info.mac[1]; - machigh |= base_info.mac[0] << 8; - mac = machigh; - mac <<= 32; - mac |= maclow; - for (i = 0; i < base_info.macno; i++, j++) { - if (index == j) - goto out; - } - - return -EINVAL; - -out: - mac += i; - address[0] = (mac >> 40) & 0xff; - address[1] = (mac >> 32) & 0xff; - address[2] = (mac >> 24) & 0xff; - address[3] = (mac >> 16) & 0xff; - address[4] = (mac >> 8) & 0xff; - address[5] = (mac >> 0) & 0xff; - - return 0; -} - -/* System Controller registers */ -enum { - GSC_SC_CTRL0 = 0, - GSC_SC_CTRL1 = 1, - GSC_SC_STATUS = 10, - GSC_SC_FWCRC = 12, - GSC_SC_FWVER = 14, - GSC_SC_WP = 15, - GSC_SC_RST_CAUSE = 16, - GSC_SC_THERM_PROTECT = 19, -}; - -/* System Controller Control1 bits */ -enum { - GSC_SC_CTRL1_WDTIME = 4, /* 1 = 60s timeout, 0 = 30s timeout */ - GSC_SC_CTRL1_WDEN = 5, /* 1 = enable, 0 = disable */ - GSC_SC_CTRL1_BOOT_CHK = 6, /* 1 = enable alt boot check */ - GSC_SC_CTRL1_WDDIS = 7, /* 1 = disable boot watchdog */ -}; - -/* System Controller Interrupt bits */ -enum { - GSC_SC_IRQ_PB = 0, /* Pushbutton switch */ - GSC_SC_IRQ_SECURE = 1, /* Secure Key erase operation complete */ - GSC_SC_IRQ_EEPROM_WP = 2, /* EEPROM write violation */ - GSC_SC_IRQ_GPIO = 4, /* GPIO change */ - GSC_SC_IRQ_TAMPER = 5, /* Tamper detect */ - GSC_SC_IRQ_WATCHDOG = 6, /* Watchdog trip */ - GSC_SC_IRQ_PBLONG = 7, /* Pushbutton long hold */ -}; - -/* System Controller WP bits */ -enum { - GSC_SC_WP_ALL = 0, /* Write Protect All EEPROM regions */ - GSC_SC_WP_BOARDINFO = 1, /* Write Protect Board Info region */ -}; - -/* System Controller Reset Cause */ -enum { - GSC_SC_RST_CAUSE_VIN = 0, - GSC_SC_RST_CAUSE_PB = 1, - GSC_SC_RST_CAUSE_WDT = 2, - GSC_SC_RST_CAUSE_CPU = 3, - GSC_SC_RST_CAUSE_TEMP_LOCAL = 4, - GSC_SC_RST_CAUSE_TEMP_REMOTE = 5, - GSC_SC_RST_CAUSE_SLEEP = 6, - GSC_SC_RST_CAUSE_BOOT_WDT = 7, - GSC_SC_RST_CAUSE_BOOT_WDT_MAN = 8, - GSC_SC_RST_CAUSE_SOFT_PWR = 9, - GSC_SC_RST_CAUSE_MAX = 10, -}; - -#include <dm/device.h> -static struct udevice *gsc_get_dev(int busno, int slave) -{ - struct udevice *dev, *bus; - int ret; - - ret = uclass_get_device_by_seq(UCLASS_I2C, busno, &bus); - if (ret) { - printf("GSC : failed I2C%d probe: %d\n", busno, ret); - return NULL; - } - ret = dm_i2c_probe(bus, slave, 0, &dev); - if (ret) - return NULL; - - return dev; -} - -static int gsc_read_eeprom(int bus, int slave, int alen, struct venice_board_info *info) -{ - int i; - int chksum; - unsigned char *buf = (unsigned char *)info; - struct udevice *dev; - int ret; - - /* probe device */ - dev = gsc_get_dev(bus, slave); - if (!dev) { - if (slave == GSC_EEPROM_ADDR) - puts("ERROR: Failed to probe EEPROM\n"); - return -ENODEV; - } - - /* read eeprom config section */ - memset(info, 0, sizeof(*info)); - ret = i2c_set_chip_offset_len(dev, alen); - if (ret) { - puts("EEPROM: Failed to set alen\n"); - return ret; - } - ret = dm_i2c_read(dev, 0x00, buf, sizeof(*info)); - if (ret) { - if (slave == GSC_EEPROM_ADDR) - printf("EEPROM: Failed to read EEPROM\n"); - return ret; - } - - /* validate checksum */ - for (chksum = 0, i = 0; i < (int)sizeof(*info) - 2; i++) - chksum += buf[i]; - if ((info->chksum[0] != chksum >> 8) || - (info->chksum[1] != (chksum & 0xff))) { - printf("EEPROM: I2C%d@0x%02x: Invalid Checksum\n", bus, slave); - print_hex_dump_bytes("", DUMP_PREFIX_NONE, buf, sizeof(*info)); - memset(info, 0, sizeof(*info)); - return -EINVAL; - } - - /* sanity check valid model */ - if (info->model[0] != 'G' || info->model[1] != 'W') { - printf("EEPROM: I2C%d@0x%02x: Invalid Model in EEPROM\n", bus, slave); - print_hex_dump_bytes("", DUMP_PREFIX_NONE, buf, sizeof(*info)); - memset(info, 0, sizeof(*info)); - return -EINVAL; - } - - return 0; -} - -static const char *gsc_get_rst_cause(struct udevice *dev) -{ - static char str[64]; - static const char * const names[] = { - "VIN", - "PB", - "WDT", - "CPU", - "TEMP_L", - "TEMP_R", - "SLEEP", - "BOOT_WDT1", - "BOOT_WDT2", - "SOFT_PWR", - }; - unsigned char reg; - - /* reset cause */ - str[0] = 0; - if (!dm_i2c_read(dev, GSC_SC_RST_CAUSE, ®, 1)) { - if (reg < ARRAY_SIZE(names)) - sprintf(str, "%s", names[reg]); - else - sprintf(str, "0x%02x", reg); - } - - /* thermal protection */ - if (!dm_i2c_read(dev, GSC_SC_THERM_PROTECT, ®, 1)) { - strcat(str, " Thermal Protection "); - if (reg & BIT(0)) - strcat(str, "Enabled"); - else - strcat(str, "Disabled"); - } - - return str; -} - -/* display hardware monitor ADC channels */ -int gsc_hwmon(void) -{ - const void *fdt = gd->fdt_blob; - struct udevice *dev; - int node, reg, mode, len, val, offset; - const char *label; - u8 buf[2]; - int ret; - - node = fdt_node_offset_by_compatible(fdt, -1, "gw,gsc-adc"); - if (node <= 0) - return node; - - /* probe device */ - dev = gsc_get_dev(GSC_BUSNO, GSC_HWMON_ADDR); - if (!dev) { - puts("ERROR: Failed to probe GSC HWMON\n"); - return -ENODEV; - } - - /* iterate over hwmon nodes */ - node = fdt_first_subnode(fdt, node); - while (node > 0) { - reg = fdtdec_get_int(fdt, node, "reg", -1); - mode = fdtdec_get_int(fdt, node, "gw,mode", -1); - offset = fdtdec_get_int(fdt, node, "gw,voltage-offset-microvolt", 0); - label = fdt_stringlist_get(fdt, node, "label", 0, NULL); - - if ((reg == -1) || (mode == -1) || !label) - printf("invalid dt:%s\n", fdt_get_name(fdt, node, NULL)); - - memset(buf, 0, sizeof(buf)); - ret = dm_i2c_read(dev, reg, buf, sizeof(buf)); - if (ret) { - printf("i2c error: %d\n", ret); - continue; - } - val = buf[0] | buf[1] << 8; - if (val >= 0) { - const u32 *div; - int r[2]; - - switch (mode) { - case 0: /* temperature (C*10) */ - if (val > 0x8000) - val -= 0xffff; - printf("%-8s: %d.%ldC\n", label, val / 10, abs(val % 10)); - break; - case 1: /* prescaled voltage */ - if (val != 0xffff) - printf("%-8s: %d.%03dV\n", label, val / 1000, val % 1000); - break; - case 2: /* scaled based on ref volt and resolution */ - val *= 2500; - val /= 1 << 12; - - /* apply pre-scaler voltage divider */ - div = fdt_getprop(fdt, node, "gw,voltage-divider-ohms", &len); - if (div && (len == sizeof(uint32_t) * 2)) { - r[0] = fdt32_to_cpu(div[0]); - r[1] = fdt32_to_cpu(div[1]); - if (r[0] && r[1]) { - val *= (r[0] + r[1]); - val /= r[1]; - } - } - - /* adjust by offset */ - val += (offset / 1000); - - printf("%-8s: %d.%03dV\n", label, val / 1000, val % 1000); - break; - } - } - node = fdt_next_subnode(fdt, node); - } - - return 0; -} - -/* determine BOM revision from model */ -int get_bom_rev(const char *str) -{ - int rev_bom = 0; - int i; - - for (i = strlen(str) - 1; i > 0; i--) { - if (str[i] == '-') - break; - if (str[i] >= '1' && str[i] <= '9') { - rev_bom = str[i] - '0'; - break; - } - } - return rev_bom; -} - -/* determine PCB revision from model */ -char get_pcb_rev(const char *str) -{ - char rev_pcb = 'A'; - int i; - - for (i = strlen(str) - 1; i > 0; i--) { - if (str[i] == '-') - break; - if (str[i] >= 'A') { - rev_pcb = str[i]; - break; - } - } - return rev_pcb; -} - -/* - * get dt name based on model and detail level: - * - * For boards that are a combination of a SoM plus a Baseboard: - * Venice SoM part numbers are GW70xx where xx is: - * 7000-7019: same PCB with som dt of '0x' - * 7020-7039: same PCB with som dt of '2x' - * 7040-7059: same PCB with som dt of '4x' - * 7060-7079: same PCB with som dt of '6x' - * 7080-7099: same PCB with som dt of '8x' - * Venice Baseboard part numbers are GW7xxx where xxx is: - * 7100-7199: same PCB with base dt of '71xx' - * 7200-7299: same PCB with base dt of '72xx' - * 7300-7399: same PCB with base dt of '73xx' - * 7400-7499: same PCB with base dt of '74xx' - * 7500-7599: same PCB with base dt of '75xx' - * 7600-7699: same PCB with base dt of '76xx' - * 7700-7799: same PCB with base dt of '77xx' - * 7800-7899: same PCB with base dt of '78xx' - * DT name is comprised of: - * gw<base dt>-<som dt>-[base-pcb-rev][base-bom-rev][som-pcb-rev][som-bom-rev] - * - * For board models from 7900-7999 each PCB is unique with its own dt: - * DT name is comprised: - * gw<model>-[pcb-rev][bom-rev] - * - */ -#define snprintfcat(dest, sz, fmt, ...) \ - snprintf((dest) + strlen(dest), (sz) - strlen(dest), fmt, ##__VA_ARGS__) -const char *gsc_get_dtb_name(int level, char *buf, int sz) -{ -#ifdef CONFIG_IMX8MM - const char *pre = "imx8mm-venice-gw"; -#else - const char *pre = "imx8mn-venice-gw"; -#endif - int model, rev_pcb, rev_bom; - - model = ((som_info.model[2] - '0') * 1000) - + ((som_info.model[3] - '0') * 100) - + ((som_info.model[4] - '0') * 10) - + (som_info.model[5] - '0'); - rev_pcb = tolower(get_pcb_rev(som_info.model)); - rev_bom = get_bom_rev(som_info.model); - - /* som + baseboard*/ - if (base_info.model[0]) { - /* baseboard id: 7100-7199->71; 7200-7299->72; etc */ - int base = ((base_info.model[2] - '0') * 10) + (base_info.model[3] - '0'); - /* som id: 7000-7019->1; 7020-7039->2; etc */ - int som = ((model % 100) / 20) * 2; - int rev_base_pcb = tolower(get_pcb_rev(base_info.model)); - int rev_base_bom = get_bom_rev(base_info.model); - - snprintf(buf, sz, "%s%2dxx-%dx", pre, base, som); - switch (level) { - case 0: /* full model (ie gw73xx-0x-a1a1) */ - if (rev_base_bom) - snprintfcat(buf, sz, "-%c%d", rev_base_pcb, rev_base_bom); - else - snprintfcat(buf, sz, "-%c", rev_base_pcb); - if (rev_bom) - snprintfcat(buf, sz, "%c%d", rev_pcb, rev_bom); - else - snprintfcat(buf, sz, "%c", rev_pcb); - break; - case 1: /* don't care about SoM revision */ - if (rev_base_bom) - snprintfcat(buf, sz, "-%c%d", rev_base_pcb, rev_base_bom); - else - snprintfcat(buf, sz, "-%c", rev_base_pcb); - snprintfcat(buf, sz, "xx"); - break; - case 2: /* don't care about baseboard revision */ - snprintfcat(buf, sz, "-xx"); - if (rev_bom) - snprintfcat(buf, sz, "%c%d", rev_pcb, rev_bom); - else - snprintfcat(buf, sz, "%c", rev_pcb); - break; - case 3: /* don't care about SoM/baseboard revision */ - break; - default: - return NULL; - } - } else { - snprintf(buf, sz, "%s%04d", pre, model); - switch (level) { - case 0: /* full model wth PCB and BOM revision first (ie gw7901-a1) */ - if (rev_bom) - snprintfcat(buf, sz, "-%c%d", rev_pcb, rev_bom); - else - snprintfcat(buf, sz, "-%c", rev_pcb); - break; - case 1: /* don't care about BOM revision */ - snprintfcat(buf, sz, "-%c", rev_pcb); - break; - case 2: /* don't care about PCB or BOM revision */ - break; - default: - return NULL; - } - } - - return buf; -} - -static int gsc_read(void) -{ - char rev_pcb; - int rev_bom; - int ret; - - ret = gsc_read_eeprom(GSC_BUSNO, GSC_EEPROM_ADDR, 1, &som_info); - if (ret) { - memset(&som_info, 0, sizeof(som_info)); - return ret; - } - - /* read optional baseboard EEPROM */ - gsc_read_eeprom(BASEBOARD_EEPROM_BUSNO, BASEBOARD_EEPROM_ADDR, - 2, &base_info); - - /* create model strings */ - if (base_info.model[0]) { - sprintf(venice_model, "GW%c%c%c%c-%c%c-", - som_info.model[2], /* family */ - base_info.model[3], /* baseboard */ - base_info.model[4], base_info.model[5], /* subload of baseboard */ - som_info.model[4], som_info.model[5]); /* last 2digits of SOM */ - - /* baseboard revision */ - rev_pcb = get_pcb_rev(base_info.model); - rev_bom = get_bom_rev(base_info.model); - if (rev_bom) - sprintf(venice_model + strlen(venice_model), "%c%d", rev_pcb, rev_bom); - else - sprintf(venice_model + strlen(venice_model), "%c", rev_pcb); - /* som revision */ - rev_pcb = get_pcb_rev(som_info.model); - rev_bom = get_bom_rev(som_info.model); - if (rev_bom) - sprintf(venice_model + strlen(venice_model), "%c%d", rev_pcb, rev_bom); - else - sprintf(venice_model + strlen(venice_model), "%c", rev_pcb); - } else { - strcpy(venice_model, som_info.model); - } - venice_serial = som_info.serial; - - return 0; -} - -static int gsc_info(int verbose) -{ - struct udevice *dev; - unsigned char buf[16]; - - printf("Model : %s\n", venice_model); - printf("Serial : %d\n", som_info.serial); - printf("MFGDate : %02x-%02x-%02x%02x\n", - som_info.mfgdate[0], som_info.mfgdate[1], - som_info.mfgdate[2], som_info.mfgdate[3]); - if (base_info.model[0] && verbose > 1) { - printf("SOM : %s %d %02x-%02x-%02x%02x\n", - som_info.model, som_info.serial, - som_info.mfgdate[0], som_info.mfgdate[1], - som_info.mfgdate[2], som_info.mfgdate[3]); - printf("BASE : %s %d %02x-%02x-%02x%02x\n", - base_info.model, base_info.serial, - base_info.mfgdate[0], base_info.mfgdate[1], - base_info.mfgdate[2], base_info.mfgdate[3]); - } - - /* Display RTC */ - puts("RTC : "); - dev = gsc_get_dev(GSC_BUSNO, GSC_RTC_ADDR); - if (!dev) { - puts("Failed to probe GSC RTC\n"); - } else { - dm_i2c_read(dev, 0, buf, 6); - printf("%d\n", buf[0] | buf[1] << 8 | buf[2] << 16 | buf[3] << 24); - } - - /* Display hwmon */ - gsc_hwmon(); - - return 0; -} - -int gsc_init(int quiet) -{ - unsigned char buf[16]; - struct udevice *dev; - int ret; - - /* - * On a board with a missing/depleted backup battery for GSC, the - * board may be ready to probe the GSC before its firmware is - * running. We will wait here indefinately for the GSC/EEPROM. - */ -#ifdef CONFIG_IMX8MN - // TODO: - // IMX8MN boots quicker than IMX8MM and exposes issue - // where because GSC I2C state machine isn't running and its - // SCL/SDA are driven low spams i2c errors - // - // Put a loop here that somehow waits for I2C CLK/DAT to be high - mdelay(40); -#endif - while (1) { - /* probe device */ - dev = gsc_get_dev(GSC_BUSNO, GSC_SC_ADDR); - if (dev) - break; - mdelay(1); - } - - ret = dm_i2c_read(dev, 0, buf, sizeof(buf)); - if (ret) { - puts("ERROR: Failed reading GSC\n"); - return ret; - } - gsc_read(); - - /* banner */ - if (!quiet) { - printf("GSC : v%d 0x%04x", buf[GSC_SC_FWVER], - buf[GSC_SC_FWCRC] | buf[GSC_SC_FWCRC + 1] << 8); - printf(" RST:%s", gsc_get_rst_cause(dev)); - printf("\n"); - gsc_info(1); - } - - if (ret) - hang(); - - return (16 << som_info.sdram_size); -} - -const char *gsc_get_model(void) -{ - return venice_model; -} - -uint32_t gsc_get_serial(void) -{ - return venice_serial; -} - -#if !(IS_ENABLED(CONFIG_SPL_BUILD)) -static int gsc_sleep(unsigned long secs) -{ - unsigned char reg; - struct udevice *dev; - int ret; - - /* probe device */ - dev = gsc_get_dev(GSC_BUSNO, GSC_SC_ADDR); - if (!dev) - return -ENODEV; - - printf("GSC Sleeping for %ld seconds\n", secs); - reg = (secs >> 24) & 0xff; - ret = dm_i2c_write(dev, 9, ®, 1); - if (ret) - goto err; - reg = (secs >> 16) & 0xff; - ret = dm_i2c_write(dev, 8, ®, 1); - if (ret) - goto err; - reg = (secs >> 8) & 0xff; - ret = dm_i2c_write(dev, 7, ®, 1); - if (ret) - goto err; - reg = secs & 0xff; - ret = dm_i2c_write(dev, 6, ®, 1); - if (ret) - goto err; - ret = dm_i2c_read(dev, GSC_SC_CTRL1, ®, 1); - if (ret) - goto err; - reg |= (1 << 2); - ret = dm_i2c_write(dev, GSC_SC_CTRL1, ®, 1); - if (ret) - goto err; - reg &= ~(1 << 2); - reg |= 0x3; - ret = dm_i2c_write(dev, GSC_SC_CTRL1, ®, 1); - if (ret) - goto err; - - return 0; - -err: - printf("i2c error\n"); - return ret; -} - -static int gsc_boot_wd_disable(void) -{ - u8 reg; - struct udevice *dev; - int ret; - - /* probe device */ - dev = gsc_get_dev(GSC_BUSNO, GSC_SC_ADDR); - if (!dev) - return -ENODEV; - - ret = dm_i2c_read(dev, GSC_SC_CTRL1, ®, 1); - if (ret) - goto err; - reg |= (1 << GSC_SC_CTRL1_WDDIS); - reg &= ~(1 << GSC_SC_CTRL1_BOOT_CHK); - ret = dm_i2c_write(dev, GSC_SC_CTRL1, ®, 1); - if (ret) - goto err; - puts("GSC : boot watchdog disabled\n"); - - return 0; - -err: - printf("i2c error"); - return ret; -} - -static int do_gsc(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[]) -{ - if (argc < 2) - return gsc_info(2); - - if (strcasecmp(argv[1], "sleep") == 0) { - if (argc < 3) - return CMD_RET_USAGE; - if (!gsc_sleep(dectoul(argv[2], NULL))) - return CMD_RET_SUCCESS; - } else if (strcasecmp(argv[1], "hwmon") == 0) { - if (!gsc_hwmon()) - return CMD_RET_SUCCESS; - } else if (strcasecmp(argv[1], "wd-disable") == 0) { - if (!gsc_boot_wd_disable()) - return CMD_RET_SUCCESS; - } - - return CMD_RET_USAGE; -} - -U_BOOT_CMD(gsc, 4, 1, do_gsc, "Gateworks System Controller", - "[sleep <secs>]|[hwmon]|[wd-disable]\n"); -#endif diff --git a/board/gateworks/venice/imximage-8mp-lpddr4.cfg b/board/gateworks/venice/imximage-8mp-lpddr4.cfg new file mode 100644 index 0000000..7731d54 --- /dev/null +++ b/board/gateworks/venice/imximage-8mp-lpddr4.cfg @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2022 Gateworks Corporation + */ + + +ROM_VERSION v2 +BOOT_FROM sd +LOADER u-boot-spl-ddr.bin 0x920000 diff --git a/board/gateworks/venice/lpddr4_timing.h b/board/gateworks/venice/lpddr4_timing.h index f9a3ee1..62b8606 100644 --- a/board/gateworks/venice/lpddr4_timing.h +++ b/board/gateworks/venice/lpddr4_timing.h @@ -15,6 +15,8 @@ extern struct dram_timing_info dram_timing_4gb; extern struct dram_timing_info dram_timing_1gb_single_die; extern struct dram_timing_info dram_timing_2gb_single_die; extern struct dram_timing_info dram_timing_2gb_dual_die; +#elif CONFIG_IMX8MP +extern struct dram_timing_info dram_timing_4gb_dual_die; #endif #endif /* __LPDDR4_TIMING_H__ */ diff --git a/board/gateworks/venice/lpddr4_timing_imx8mp.c b/board/gateworks/venice/lpddr4_timing_imx8mp.c new file mode 100644 index 0000000..2e96332 --- /dev/null +++ b/board/gateworks/venice/lpddr4_timing_imx8mp.c @@ -0,0 +1,1846 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include <linux/kernel.h> +#include <asm/arch/ddr.h> + +/* + * Generated code from MX8M_DDR_tool v3.30 using MX8M_Plus RPAv7 + */ +/* ddr phy trained csr */ +static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { + { 0x200b2, 0x0 }, + { 0x1200b2, 0x0 }, + { 0x2200b2, 0x0 }, + { 0x200cb, 0x0 }, + { 0x10043, 0x0 }, + { 0x110043, 0x0 }, + { 0x210043, 0x0 }, + { 0x10143, 0x0 }, + { 0x110143, 0x0 }, + { 0x210143, 0x0 }, + { 0x11043, 0x0 }, + { 0x111043, 0x0 }, + { 0x211043, 0x0 }, + { 0x11143, 0x0 }, + { 0x111143, 0x0 }, + { 0x211143, 0x0 }, + { 0x12043, 0x0 }, + { 0x112043, 0x0 }, + { 0x212043, 0x0 }, + { 0x12143, 0x0 }, + { 0x112143, 0x0 }, + { 0x212143, 0x0 }, + { 0x13043, 0x0 }, + { 0x113043, 0x0 }, + { 0x213043, 0x0 }, + { 0x13143, 0x0 }, + { 0x113143, 0x0 }, + { 0x213143, 0x0 }, + { 0x80, 0x0 }, + { 0x100080, 0x0 }, + { 0x200080, 0x0 }, + { 0x1080, 0x0 }, + { 0x101080, 0x0 }, + { 0x201080, 0x0 }, + { 0x2080, 0x0 }, + { 0x102080, 0x0 }, + { 0x202080, 0x0 }, + { 0x3080, 0x0 }, + { 0x103080, 0x0 }, + { 0x203080, 0x0 }, + { 0x4080, 0x0 }, + { 0x104080, 0x0 }, + { 0x204080, 0x0 }, + { 0x5080, 0x0 }, + { 0x105080, 0x0 }, + { 0x205080, 0x0 }, + { 0x6080, 0x0 }, + { 0x106080, 0x0 }, + { 0x206080, 0x0 }, + { 0x7080, 0x0 }, + { 0x107080, 0x0 }, + { 0x207080, 0x0 }, + { 0x8080, 0x0 }, + { 0x108080, 0x0 }, + { 0x208080, 0x0 }, + { 0x9080, 0x0 }, + { 0x109080, 0x0 }, + { 0x209080, 0x0 }, + { 0x10080, 0x0 }, + { 0x110080, 0x0 }, + { 0x210080, 0x0 }, + { 0x10180, 0x0 }, + { 0x110180, 0x0 }, + { 0x210180, 0x0 }, + { 0x11080, 0x0 }, + { 0x111080, 0x0 }, + { 0x211080, 0x0 }, + { 0x11180, 0x0 }, + { 0x111180, 0x0 }, + { 0x211180, 0x0 }, + { 0x12080, 0x0 }, + { 0x112080, 0x0 }, + { 0x212080, 0x0 }, + { 0x12180, 0x0 }, + { 0x112180, 0x0 }, + { 0x212180, 0x0 }, + { 0x13080, 0x0 }, + { 0x113080, 0x0 }, + { 0x213080, 0x0 }, + { 0x13180, 0x0 }, + { 0x113180, 0x0 }, + { 0x213180, 0x0 }, + { 0x10081, 0x0 }, + { 0x110081, 0x0 }, + { 0x210081, 0x0 }, + { 0x10181, 0x0 }, + { 0x110181, 0x0 }, + { 0x210181, 0x0 }, + { 0x11081, 0x0 }, + { 0x111081, 0x0 }, + { 0x211081, 0x0 }, + { 0x11181, 0x0 }, + { 0x111181, 0x0 }, + { 0x211181, 0x0 }, + { 0x12081, 0x0 }, + { 0x112081, 0x0 }, + { 0x212081, 0x0 }, + { 0x12181, 0x0 }, + { 0x112181, 0x0 }, + { 0x212181, 0x0 }, + { 0x13081, 0x0 }, + { 0x113081, 0x0 }, + { 0x213081, 0x0 }, + { 0x13181, 0x0 }, + { 0x113181, 0x0 }, + { 0x213181, 0x0 }, + { 0x100d0, 0x0 }, + { 0x1100d0, 0x0 }, + { 0x2100d0, 0x0 }, + { 0x101d0, 0x0 }, + { 0x1101d0, 0x0 }, + { 0x2101d0, 0x0 }, + { 0x110d0, 0x0 }, + { 0x1110d0, 0x0 }, + { 0x2110d0, 0x0 }, + { 0x111d0, 0x0 }, + { 0x1111d0, 0x0 }, + { 0x2111d0, 0x0 }, + { 0x120d0, 0x0 }, + { 0x1120d0, 0x0 }, + { 0x2120d0, 0x0 }, + { 0x121d0, 0x0 }, + { 0x1121d0, 0x0 }, + { 0x2121d0, 0x0 }, + { 0x130d0, 0x0 }, + { 0x1130d0, 0x0 }, + { 0x2130d0, 0x0 }, + { 0x131d0, 0x0 }, + { 0x1131d0, 0x0 }, + { 0x2131d0, 0x0 }, + { 0x100d1, 0x0 }, + { 0x1100d1, 0x0 }, + { 0x2100d1, 0x0 }, + { 0x101d1, 0x0 }, + { 0x1101d1, 0x0 }, + { 0x2101d1, 0x0 }, + { 0x110d1, 0x0 }, + { 0x1110d1, 0x0 }, + { 0x2110d1, 0x0 }, + { 0x111d1, 0x0 }, + { 0x1111d1, 0x0 }, + { 0x2111d1, 0x0 }, + { 0x120d1, 0x0 }, + { 0x1120d1, 0x0 }, + { 0x2120d1, 0x0 }, + { 0x121d1, 0x0 }, + { 0x1121d1, 0x0 }, + { 0x2121d1, 0x0 }, + { 0x130d1, 0x0 }, + { 0x1130d1, 0x0 }, + { 0x2130d1, 0x0 }, + { 0x131d1, 0x0 }, + { 0x1131d1, 0x0 }, + { 0x2131d1, 0x0 }, + { 0x10068, 0x0 }, + { 0x10168, 0x0 }, + { 0x10268, 0x0 }, + { 0x10368, 0x0 }, + { 0x10468, 0x0 }, + { 0x10568, 0x0 }, + { 0x10668, 0x0 }, + { 0x10768, 0x0 }, + { 0x10868, 0x0 }, + { 0x11068, 0x0 }, + { 0x11168, 0x0 }, + { 0x11268, 0x0 }, + { 0x11368, 0x0 }, + { 0x11468, 0x0 }, + { 0x11568, 0x0 }, + { 0x11668, 0x0 }, + { 0x11768, 0x0 }, + { 0x11868, 0x0 }, + { 0x12068, 0x0 }, + { 0x12168, 0x0 }, + { 0x12268, 0x0 }, + { 0x12368, 0x0 }, + { 0x12468, 0x0 }, + { 0x12568, 0x0 }, + { 0x12668, 0x0 }, + { 0x12768, 0x0 }, + { 0x12868, 0x0 }, + { 0x13068, 0x0 }, + { 0x13168, 0x0 }, + { 0x13268, 0x0 }, + { 0x13368, 0x0 }, + { 0x13468, 0x0 }, + { 0x13568, 0x0 }, + { 0x13668, 0x0 }, + { 0x13768, 0x0 }, + { 0x13868, 0x0 }, + { 0x10069, 0x0 }, + { 0x10169, 0x0 }, + { 0x10269, 0x0 }, + { 0x10369, 0x0 }, + { 0x10469, 0x0 }, + { 0x10569, 0x0 }, + { 0x10669, 0x0 }, + { 0x10769, 0x0 }, + { 0x10869, 0x0 }, + { 0x11069, 0x0 }, + { 0x11169, 0x0 }, + { 0x11269, 0x0 }, + { 0x11369, 0x0 }, + { 0x11469, 0x0 }, + { 0x11569, 0x0 }, + { 0x11669, 0x0 }, + { 0x11769, 0x0 }, + { 0x11869, 0x0 }, + { 0x12069, 0x0 }, + { 0x12169, 0x0 }, + { 0x12269, 0x0 }, + { 0x12369, 0x0 }, + { 0x12469, 0x0 }, + { 0x12569, 0x0 }, + { 0x12669, 0x0 }, + { 0x12769, 0x0 }, + { 0x12869, 0x0 }, + { 0x13069, 0x0 }, + { 0x13169, 0x0 }, + { 0x13269, 0x0 }, + { 0x13369, 0x0 }, + { 0x13469, 0x0 }, + { 0x13569, 0x0 }, + { 0x13669, 0x0 }, + { 0x13769, 0x0 }, + { 0x13869, 0x0 }, + { 0x1008c, 0x0 }, + { 0x11008c, 0x0 }, + { 0x21008c, 0x0 }, + { 0x1018c, 0x0 }, + { 0x11018c, 0x0 }, + { 0x21018c, 0x0 }, + { 0x1108c, 0x0 }, + { 0x11108c, 0x0 }, + { 0x21108c, 0x0 }, + { 0x1118c, 0x0 }, + { 0x11118c, 0x0 }, + { 0x21118c, 0x0 }, + { 0x1208c, 0x0 }, + { 0x11208c, 0x0 }, + { 0x21208c, 0x0 }, + { 0x1218c, 0x0 }, + { 0x11218c, 0x0 }, + { 0x21218c, 0x0 }, + { 0x1308c, 0x0 }, + { 0x11308c, 0x0 }, + { 0x21308c, 0x0 }, + { 0x1318c, 0x0 }, + { 0x11318c, 0x0 }, + { 0x21318c, 0x0 }, + { 0x1008d, 0x0 }, + { 0x11008d, 0x0 }, + { 0x21008d, 0x0 }, + { 0x1018d, 0x0 }, + { 0x11018d, 0x0 }, + { 0x21018d, 0x0 }, + { 0x1108d, 0x0 }, + { 0x11108d, 0x0 }, + { 0x21108d, 0x0 }, + { 0x1118d, 0x0 }, + { 0x11118d, 0x0 }, + { 0x21118d, 0x0 }, + { 0x1208d, 0x0 }, + { 0x11208d, 0x0 }, + { 0x21208d, 0x0 }, + { 0x1218d, 0x0 }, + { 0x11218d, 0x0 }, + { 0x21218d, 0x0 }, + { 0x1308d, 0x0 }, + { 0x11308d, 0x0 }, + { 0x21308d, 0x0 }, + { 0x1318d, 0x0 }, + { 0x11318d, 0x0 }, + { 0x21318d, 0x0 }, + { 0x100c0, 0x0 }, + { 0x1100c0, 0x0 }, + { 0x2100c0, 0x0 }, + { 0x101c0, 0x0 }, + { 0x1101c0, 0x0 }, + { 0x2101c0, 0x0 }, + { 0x102c0, 0x0 }, + { 0x1102c0, 0x0 }, + { 0x2102c0, 0x0 }, + { 0x103c0, 0x0 }, + { 0x1103c0, 0x0 }, + { 0x2103c0, 0x0 }, + { 0x104c0, 0x0 }, + { 0x1104c0, 0x0 }, + { 0x2104c0, 0x0 }, + { 0x105c0, 0x0 }, + { 0x1105c0, 0x0 }, + { 0x2105c0, 0x0 }, + { 0x106c0, 0x0 }, + { 0x1106c0, 0x0 }, + { 0x2106c0, 0x0 }, + { 0x107c0, 0x0 }, + { 0x1107c0, 0x0 }, + { 0x2107c0, 0x0 }, + { 0x108c0, 0x0 }, + { 0x1108c0, 0x0 }, + { 0x2108c0, 0x0 }, + { 0x110c0, 0x0 }, + { 0x1110c0, 0x0 }, + { 0x2110c0, 0x0 }, + { 0x111c0, 0x0 }, + { 0x1111c0, 0x0 }, + { 0x2111c0, 0x0 }, + { 0x112c0, 0x0 }, + { 0x1112c0, 0x0 }, + { 0x2112c0, 0x0 }, + { 0x113c0, 0x0 }, + { 0x1113c0, 0x0 }, + { 0x2113c0, 0x0 }, + { 0x114c0, 0x0 }, + { 0x1114c0, 0x0 }, + { 0x2114c0, 0x0 }, + { 0x115c0, 0x0 }, + { 0x1115c0, 0x0 }, + { 0x2115c0, 0x0 }, + { 0x116c0, 0x0 }, + { 0x1116c0, 0x0 }, + { 0x2116c0, 0x0 }, + { 0x117c0, 0x0 }, + { 0x1117c0, 0x0 }, + { 0x2117c0, 0x0 }, + { 0x118c0, 0x0 }, + { 0x1118c0, 0x0 }, + { 0x2118c0, 0x0 }, + { 0x120c0, 0x0 }, + { 0x1120c0, 0x0 }, + { 0x2120c0, 0x0 }, + { 0x121c0, 0x0 }, + { 0x1121c0, 0x0 }, + { 0x2121c0, 0x0 }, + { 0x122c0, 0x0 }, + { 0x1122c0, 0x0 }, + { 0x2122c0, 0x0 }, + { 0x123c0, 0x0 }, + { 0x1123c0, 0x0 }, + { 0x2123c0, 0x0 }, + { 0x124c0, 0x0 }, + { 0x1124c0, 0x0 }, + { 0x2124c0, 0x0 }, + { 0x125c0, 0x0 }, + { 0x1125c0, 0x0 }, + { 0x2125c0, 0x0 }, + { 0x126c0, 0x0 }, + { 0x1126c0, 0x0 }, + { 0x2126c0, 0x0 }, + { 0x127c0, 0x0 }, + { 0x1127c0, 0x0 }, + { 0x2127c0, 0x0 }, + { 0x128c0, 0x0 }, + { 0x1128c0, 0x0 }, + { 0x2128c0, 0x0 }, + { 0x130c0, 0x0 }, + { 0x1130c0, 0x0 }, + { 0x2130c0, 0x0 }, + { 0x131c0, 0x0 }, + { 0x1131c0, 0x0 }, + { 0x2131c0, 0x0 }, + { 0x132c0, 0x0 }, + { 0x1132c0, 0x0 }, + { 0x2132c0, 0x0 }, + { 0x133c0, 0x0 }, + { 0x1133c0, 0x0 }, + { 0x2133c0, 0x0 }, + { 0x134c0, 0x0 }, + { 0x1134c0, 0x0 }, + { 0x2134c0, 0x0 }, + { 0x135c0, 0x0 }, + { 0x1135c0, 0x0 }, + { 0x2135c0, 0x0 }, + { 0x136c0, 0x0 }, + { 0x1136c0, 0x0 }, + { 0x2136c0, 0x0 }, + { 0x137c0, 0x0 }, + { 0x1137c0, 0x0 }, + { 0x2137c0, 0x0 }, + { 0x138c0, 0x0 }, + { 0x1138c0, 0x0 }, + { 0x2138c0, 0x0 }, + { 0x100c1, 0x0 }, + { 0x1100c1, 0x0 }, + { 0x2100c1, 0x0 }, + { 0x101c1, 0x0 }, + { 0x1101c1, 0x0 }, + { 0x2101c1, 0x0 }, + { 0x102c1, 0x0 }, + { 0x1102c1, 0x0 }, + { 0x2102c1, 0x0 }, + { 0x103c1, 0x0 }, + { 0x1103c1, 0x0 }, + { 0x2103c1, 0x0 }, + { 0x104c1, 0x0 }, + { 0x1104c1, 0x0 }, + { 0x2104c1, 0x0 }, + { 0x105c1, 0x0 }, + { 0x1105c1, 0x0 }, + { 0x2105c1, 0x0 }, + { 0x106c1, 0x0 }, + { 0x1106c1, 0x0 }, + { 0x2106c1, 0x0 }, + { 0x107c1, 0x0 }, + { 0x1107c1, 0x0 }, + { 0x2107c1, 0x0 }, + { 0x108c1, 0x0 }, + { 0x1108c1, 0x0 }, + { 0x2108c1, 0x0 }, + { 0x110c1, 0x0 }, + { 0x1110c1, 0x0 }, + { 0x2110c1, 0x0 }, + { 0x111c1, 0x0 }, + { 0x1111c1, 0x0 }, + { 0x2111c1, 0x0 }, + { 0x112c1, 0x0 }, + { 0x1112c1, 0x0 }, + { 0x2112c1, 0x0 }, + { 0x113c1, 0x0 }, + { 0x1113c1, 0x0 }, + { 0x2113c1, 0x0 }, + { 0x114c1, 0x0 }, + { 0x1114c1, 0x0 }, + { 0x2114c1, 0x0 }, + { 0x115c1, 0x0 }, + { 0x1115c1, 0x0 }, + { 0x2115c1, 0x0 }, + { 0x116c1, 0x0 }, + { 0x1116c1, 0x0 }, + { 0x2116c1, 0x0 }, + { 0x117c1, 0x0 }, + { 0x1117c1, 0x0 }, + { 0x2117c1, 0x0 }, + { 0x118c1, 0x0 }, + { 0x1118c1, 0x0 }, + { 0x2118c1, 0x0 }, + { 0x120c1, 0x0 }, + { 0x1120c1, 0x0 }, + { 0x2120c1, 0x0 }, + { 0x121c1, 0x0 }, + { 0x1121c1, 0x0 }, + { 0x2121c1, 0x0 }, + { 0x122c1, 0x0 }, + { 0x1122c1, 0x0 }, + { 0x2122c1, 0x0 }, + { 0x123c1, 0x0 }, + { 0x1123c1, 0x0 }, + { 0x2123c1, 0x0 }, + { 0x124c1, 0x0 }, + { 0x1124c1, 0x0 }, + { 0x2124c1, 0x0 }, + { 0x125c1, 0x0 }, + { 0x1125c1, 0x0 }, + { 0x2125c1, 0x0 }, + { 0x126c1, 0x0 }, + { 0x1126c1, 0x0 }, + { 0x2126c1, 0x0 }, + { 0x127c1, 0x0 }, + { 0x1127c1, 0x0 }, + { 0x2127c1, 0x0 }, + { 0x128c1, 0x0 }, + { 0x1128c1, 0x0 }, + { 0x2128c1, 0x0 }, + { 0x130c1, 0x0 }, + { 0x1130c1, 0x0 }, + { 0x2130c1, 0x0 }, + { 0x131c1, 0x0 }, + { 0x1131c1, 0x0 }, + { 0x2131c1, 0x0 }, + { 0x132c1, 0x0 }, + { 0x1132c1, 0x0 }, + { 0x2132c1, 0x0 }, + { 0x133c1, 0x0 }, + { 0x1133c1, 0x0 }, + { 0x2133c1, 0x0 }, + { 0x134c1, 0x0 }, + { 0x1134c1, 0x0 }, + { 0x2134c1, 0x0 }, + { 0x135c1, 0x0 }, + { 0x1135c1, 0x0 }, + { 0x2135c1, 0x0 }, + { 0x136c1, 0x0 }, + { 0x1136c1, 0x0 }, + { 0x2136c1, 0x0 }, + { 0x137c1, 0x0 }, + { 0x1137c1, 0x0 }, + { 0x2137c1, 0x0 }, + { 0x138c1, 0x0 }, + { 0x1138c1, 0x0 }, + { 0x2138c1, 0x0 }, + { 0x10020, 0x0 }, + { 0x110020, 0x0 }, + { 0x210020, 0x0 }, + { 0x11020, 0x0 }, + { 0x111020, 0x0 }, + { 0x211020, 0x0 }, + { 0x12020, 0x0 }, + { 0x112020, 0x0 }, + { 0x212020, 0x0 }, + { 0x13020, 0x0 }, + { 0x113020, 0x0 }, + { 0x213020, 0x0 }, + { 0x20072, 0x0 }, + { 0x20073, 0x0 }, + { 0x20074, 0x0 }, + { 0x100aa, 0x0 }, + { 0x110aa, 0x0 }, + { 0x120aa, 0x0 }, + { 0x130aa, 0x0 }, + { 0x20010, 0x0 }, + { 0x120010, 0x0 }, + { 0x220010, 0x0 }, + { 0x20011, 0x0 }, + { 0x120011, 0x0 }, + { 0x220011, 0x0 }, + { 0x100ae, 0x0 }, + { 0x1100ae, 0x0 }, + { 0x2100ae, 0x0 }, + { 0x100af, 0x0 }, + { 0x1100af, 0x0 }, + { 0x2100af, 0x0 }, + { 0x110ae, 0x0 }, + { 0x1110ae, 0x0 }, + { 0x2110ae, 0x0 }, + { 0x110af, 0x0 }, + { 0x1110af, 0x0 }, + { 0x2110af, 0x0 }, + { 0x120ae, 0x0 }, + { 0x1120ae, 0x0 }, + { 0x2120ae, 0x0 }, + { 0x120af, 0x0 }, + { 0x1120af, 0x0 }, + { 0x2120af, 0x0 }, + { 0x130ae, 0x0 }, + { 0x1130ae, 0x0 }, + { 0x2130ae, 0x0 }, + { 0x130af, 0x0 }, + { 0x1130af, 0x0 }, + { 0x2130af, 0x0 }, + { 0x20020, 0x0 }, + { 0x120020, 0x0 }, + { 0x220020, 0x0 }, + { 0x100a0, 0x0 }, + { 0x100a1, 0x0 }, + { 0x100a2, 0x0 }, + { 0x100a3, 0x0 }, + { 0x100a4, 0x0 }, + { 0x100a5, 0x0 }, + { 0x100a6, 0x0 }, + { 0x100a7, 0x0 }, + { 0x110a0, 0x0 }, + { 0x110a1, 0x0 }, + { 0x110a2, 0x0 }, + { 0x110a3, 0x0 }, + { 0x110a4, 0x0 }, + { 0x110a5, 0x0 }, + { 0x110a6, 0x0 }, + { 0x110a7, 0x0 }, + { 0x120a0, 0x0 }, + { 0x120a1, 0x0 }, + { 0x120a2, 0x0 }, + { 0x120a3, 0x0 }, + { 0x120a4, 0x0 }, + { 0x120a5, 0x0 }, + { 0x120a6, 0x0 }, + { 0x120a7, 0x0 }, + { 0x130a0, 0x0 }, + { 0x130a1, 0x0 }, + { 0x130a2, 0x0 }, + { 0x130a3, 0x0 }, + { 0x130a4, 0x0 }, + { 0x130a5, 0x0 }, + { 0x130a6, 0x0 }, + { 0x130a7, 0x0 }, + { 0x2007c, 0x0 }, + { 0x12007c, 0x0 }, + { 0x22007c, 0x0 }, + { 0x2007d, 0x0 }, + { 0x12007d, 0x0 }, + { 0x22007d, 0x0 }, + { 0x400fd, 0x0 }, + { 0x400c0, 0x0 }, + { 0x90201, 0x0 }, + { 0x190201, 0x0 }, + { 0x290201, 0x0 }, + { 0x90202, 0x0 }, + { 0x190202, 0x0 }, + { 0x290202, 0x0 }, + { 0x90203, 0x0 }, + { 0x190203, 0x0 }, + { 0x290203, 0x0 }, + { 0x90204, 0x0 }, + { 0x190204, 0x0 }, + { 0x290204, 0x0 }, + { 0x90205, 0x0 }, + { 0x190205, 0x0 }, + { 0x290205, 0x0 }, + { 0x90206, 0x0 }, + { 0x190206, 0x0 }, + { 0x290206, 0x0 }, + { 0x90207, 0x0 }, + { 0x190207, 0x0 }, + { 0x290207, 0x0 }, + { 0x90208, 0x0 }, + { 0x190208, 0x0 }, + { 0x290208, 0x0 }, + { 0x10062, 0x0 }, + { 0x10162, 0x0 }, + { 0x10262, 0x0 }, + { 0x10362, 0x0 }, + { 0x10462, 0x0 }, + { 0x10562, 0x0 }, + { 0x10662, 0x0 }, + { 0x10762, 0x0 }, + { 0x10862, 0x0 }, + { 0x11062, 0x0 }, + { 0x11162, 0x0 }, + { 0x11262, 0x0 }, + { 0x11362, 0x0 }, + { 0x11462, 0x0 }, + { 0x11562, 0x0 }, + { 0x11662, 0x0 }, + { 0x11762, 0x0 }, + { 0x11862, 0x0 }, + { 0x12062, 0x0 }, + { 0x12162, 0x0 }, + { 0x12262, 0x0 }, + { 0x12362, 0x0 }, + { 0x12462, 0x0 }, + { 0x12562, 0x0 }, + { 0x12662, 0x0 }, + { 0x12762, 0x0 }, + { 0x12862, 0x0 }, + { 0x13062, 0x0 }, + { 0x13162, 0x0 }, + { 0x13262, 0x0 }, + { 0x13362, 0x0 }, + { 0x13462, 0x0 }, + { 0x13562, 0x0 }, + { 0x13662, 0x0 }, + { 0x13762, 0x0 }, + { 0x13862, 0x0 }, + { 0x20077, 0x0 }, + { 0x10001, 0x0 }, + { 0x11001, 0x0 }, + { 0x12001, 0x0 }, + { 0x13001, 0x0 }, + { 0x10040, 0x0 }, + { 0x10140, 0x0 }, + { 0x10240, 0x0 }, + { 0x10340, 0x0 }, + { 0x10440, 0x0 }, + { 0x10540, 0x0 }, + { 0x10640, 0x0 }, + { 0x10740, 0x0 }, + { 0x10840, 0x0 }, + { 0x10030, 0x0 }, + { 0x10130, 0x0 }, + { 0x10230, 0x0 }, + { 0x10330, 0x0 }, + { 0x10430, 0x0 }, + { 0x10530, 0x0 }, + { 0x10630, 0x0 }, + { 0x10730, 0x0 }, + { 0x10830, 0x0 }, + { 0x11040, 0x0 }, + { 0x11140, 0x0 }, + { 0x11240, 0x0 }, + { 0x11340, 0x0 }, + { 0x11440, 0x0 }, + { 0x11540, 0x0 }, + { 0x11640, 0x0 }, + { 0x11740, 0x0 }, + { 0x11840, 0x0 }, + { 0x11030, 0x0 }, + { 0x11130, 0x0 }, + { 0x11230, 0x0 }, + { 0x11330, 0x0 }, + { 0x11430, 0x0 }, + { 0x11530, 0x0 }, + { 0x11630, 0x0 }, + { 0x11730, 0x0 }, + { 0x11830, 0x0 }, + { 0x12040, 0x0 }, + { 0x12140, 0x0 }, + { 0x12240, 0x0 }, + { 0x12340, 0x0 }, + { 0x12440, 0x0 }, + { 0x12540, 0x0 }, + { 0x12640, 0x0 }, + { 0x12740, 0x0 }, + { 0x12840, 0x0 }, + { 0x12030, 0x0 }, + { 0x12130, 0x0 }, + { 0x12230, 0x0 }, + { 0x12330, 0x0 }, + { 0x12430, 0x0 }, + { 0x12530, 0x0 }, + { 0x12630, 0x0 }, + { 0x12730, 0x0 }, + { 0x12830, 0x0 }, + { 0x13040, 0x0 }, + { 0x13140, 0x0 }, + { 0x13240, 0x0 }, + { 0x13340, 0x0 }, + { 0x13440, 0x0 }, + { 0x13540, 0x0 }, + { 0x13640, 0x0 }, + { 0x13740, 0x0 }, + { 0x13840, 0x0 }, + { 0x13030, 0x0 }, + { 0x13130, 0x0 }, + { 0x13230, 0x0 }, + { 0x13330, 0x0 }, + { 0x13430, 0x0 }, + { 0x13530, 0x0 }, + { 0x13630, 0x0 }, + { 0x13730, 0x0 }, + { 0x13830, 0x0 }, +}; + +/* DRAM PHY init engine image */ +static struct dram_cfg_param ddr_phy_pie[] = { + { 0xd0000, 0x0 }, + { 0x90000, 0x10 }, + { 0x90001, 0x400 }, + { 0x90002, 0x10e }, + { 0x90003, 0x0 }, + { 0x90004, 0x0 }, + { 0x90005, 0x8 }, + { 0x90029, 0xb }, + { 0x9002a, 0x480 }, + { 0x9002b, 0x109 }, + { 0x9002c, 0x8 }, + { 0x9002d, 0x448 }, + { 0x9002e, 0x139 }, + { 0x9002f, 0x8 }, + { 0x90030, 0x478 }, + { 0x90031, 0x109 }, + { 0x90032, 0x0 }, + { 0x90033, 0xe8 }, + { 0x90034, 0x109 }, + { 0x90035, 0x2 }, + { 0x90036, 0x10 }, + { 0x90037, 0x139 }, + { 0x90038, 0xb }, + { 0x90039, 0x7c0 }, + { 0x9003a, 0x139 }, + { 0x9003b, 0x44 }, + { 0x9003c, 0x633 }, + { 0x9003d, 0x159 }, + { 0x9003e, 0x14f }, + { 0x9003f, 0x630 }, + { 0x90040, 0x159 }, + { 0x90041, 0x47 }, + { 0x90042, 0x633 }, + { 0x90043, 0x149 }, + { 0x90044, 0x4f }, + { 0x90045, 0x633 }, + { 0x90046, 0x179 }, + { 0x90047, 0x8 }, + { 0x90048, 0xe0 }, + { 0x90049, 0x109 }, + { 0x9004a, 0x0 }, + { 0x9004b, 0x7c8 }, + { 0x9004c, 0x109 }, + { 0x9004d, 0x0 }, + { 0x9004e, 0x1 }, + { 0x9004f, 0x8 }, + { 0x90050, 0x0 }, + { 0x90051, 0x45a }, + { 0x90052, 0x9 }, + { 0x90053, 0x0 }, + { 0x90054, 0x448 }, + { 0x90055, 0x109 }, + { 0x90056, 0x40 }, + { 0x90057, 0x633 }, + { 0x90058, 0x179 }, + { 0x90059, 0x1 }, + { 0x9005a, 0x618 }, + { 0x9005b, 0x109 }, + { 0x9005c, 0x40c0 }, + { 0x9005d, 0x633 }, + { 0x9005e, 0x149 }, + { 0x9005f, 0x8 }, + { 0x90060, 0x4 }, + { 0x90061, 0x48 }, + { 0x90062, 0x4040 }, + { 0x90063, 0x633 }, + { 0x90064, 0x149 }, + { 0x90065, 0x0 }, + { 0x90066, 0x4 }, + { 0x90067, 0x48 }, + { 0x90068, 0x40 }, + { 0x90069, 0x633 }, + { 0x9006a, 0x149 }, + { 0x9006b, 0x10 }, + { 0x9006c, 0x4 }, + { 0x9006d, 0x18 }, + { 0x9006e, 0x0 }, + { 0x9006f, 0x4 }, + { 0x90070, 0x78 }, + { 0x90071, 0x549 }, + { 0x90072, 0x633 }, + { 0x90073, 0x159 }, + { 0x90074, 0xd49 }, + { 0x90075, 0x633 }, + { 0x90076, 0x159 }, + { 0x90077, 0x94a }, + { 0x90078, 0x633 }, + { 0x90079, 0x159 }, + { 0x9007a, 0x441 }, + { 0x9007b, 0x633 }, + { 0x9007c, 0x149 }, + { 0x9007d, 0x42 }, + { 0x9007e, 0x633 }, + { 0x9007f, 0x149 }, + { 0x90080, 0x1 }, + { 0x90081, 0x633 }, + { 0x90082, 0x149 }, + { 0x90083, 0x0 }, + { 0x90084, 0xe0 }, + { 0x90085, 0x109 }, + { 0x90086, 0xa }, + { 0x90087, 0x10 }, + { 0x90088, 0x109 }, + { 0x90089, 0x9 }, + { 0x9008a, 0x3c0 }, + { 0x9008b, 0x149 }, + { 0x9008c, 0x9 }, + { 0x9008d, 0x3c0 }, + { 0x9008e, 0x159 }, + { 0x9008f, 0x18 }, + { 0x90090, 0x10 }, + { 0x90091, 0x109 }, + { 0x90092, 0x0 }, + { 0x90093, 0x3c0 }, + { 0x90094, 0x109 }, + { 0x90095, 0x18 }, + { 0x90096, 0x4 }, + { 0x90097, 0x48 }, + { 0x90098, 0x18 }, + { 0x90099, 0x4 }, + { 0x9009a, 0x58 }, + { 0x9009b, 0xb }, + { 0x9009c, 0x10 }, + { 0x9009d, 0x109 }, + { 0x9009e, 0x1 }, + { 0x9009f, 0x10 }, + { 0x900a0, 0x109 }, + { 0x900a1, 0x5 }, + { 0x900a2, 0x7c0 }, + { 0x900a3, 0x109 }, + { 0x40000, 0x811 }, + { 0x40020, 0x880 }, + { 0x40040, 0x0 }, + { 0x40060, 0x0 }, + { 0x40001, 0x4008 }, + { 0x40021, 0x83 }, + { 0x40041, 0x4f }, + { 0x40061, 0x0 }, + { 0x40002, 0x4040 }, + { 0x40022, 0x83 }, + { 0x40042, 0x51 }, + { 0x40062, 0x0 }, + { 0x40003, 0x811 }, + { 0x40023, 0x880 }, + { 0x40043, 0x0 }, + { 0x40063, 0x0 }, + { 0x40004, 0x720 }, + { 0x40024, 0xf }, + { 0x40044, 0x1740 }, + { 0x40064, 0x0 }, + { 0x40005, 0x16 }, + { 0x40025, 0x83 }, + { 0x40045, 0x4b }, + { 0x40065, 0x0 }, + { 0x40006, 0x716 }, + { 0x40026, 0xf }, + { 0x40046, 0x2001 }, + { 0x40066, 0x0 }, + { 0x40007, 0x716 }, + { 0x40027, 0xf }, + { 0x40047, 0x2800 }, + { 0x40067, 0x0 }, + { 0x40008, 0x716 }, + { 0x40028, 0xf }, + { 0x40048, 0xf00 }, + { 0x40068, 0x0 }, + { 0x40009, 0x720 }, + { 0x40029, 0xf }, + { 0x40049, 0x1400 }, + { 0x40069, 0x0 }, + { 0x4000a, 0xe08 }, + { 0x4002a, 0xc15 }, + { 0x4004a, 0x0 }, + { 0x4006a, 0x0 }, + { 0x4000b, 0x625 }, + { 0x4002b, 0x15 }, + { 0x4004b, 0x0 }, + { 0x4006b, 0x0 }, + { 0x4000c, 0x4028 }, + { 0x4002c, 0x80 }, + { 0x4004c, 0x0 }, + { 0x4006c, 0x0 }, + { 0x4000d, 0xe08 }, + { 0x4002d, 0xc1a }, + { 0x4004d, 0x0 }, + { 0x4006d, 0x0 }, + { 0x4000e, 0x625 }, + { 0x4002e, 0x1a }, + { 0x4004e, 0x0 }, + { 0x4006e, 0x0 }, + { 0x4000f, 0x4040 }, + { 0x4002f, 0x80 }, + { 0x4004f, 0x0 }, + { 0x4006f, 0x0 }, + { 0x40010, 0x2604 }, + { 0x40030, 0x15 }, + { 0x40050, 0x0 }, + { 0x40070, 0x0 }, + { 0x40011, 0x708 }, + { 0x40031, 0x5 }, + { 0x40051, 0x0 }, + { 0x40071, 0x2002 }, + { 0x40012, 0x8 }, + { 0x40032, 0x80 }, + { 0x40052, 0x0 }, + { 0x40072, 0x0 }, + { 0x40013, 0x2604 }, + { 0x40033, 0x1a }, + { 0x40053, 0x0 }, + { 0x40073, 0x0 }, + { 0x40014, 0x708 }, + { 0x40034, 0xa }, + { 0x40054, 0x0 }, + { 0x40074, 0x2002 }, + { 0x40015, 0x4040 }, + { 0x40035, 0x80 }, + { 0x40055, 0x0 }, + { 0x40075, 0x0 }, + { 0x40016, 0x60a }, + { 0x40036, 0x15 }, + { 0x40056, 0x1200 }, + { 0x40076, 0x0 }, + { 0x40017, 0x61a }, + { 0x40037, 0x15 }, + { 0x40057, 0x1300 }, + { 0x40077, 0x0 }, + { 0x40018, 0x60a }, + { 0x40038, 0x1a }, + { 0x40058, 0x1200 }, + { 0x40078, 0x0 }, + { 0x40019, 0x642 }, + { 0x40039, 0x1a }, + { 0x40059, 0x1300 }, + { 0x40079, 0x0 }, + { 0x4001a, 0x4808 }, + { 0x4003a, 0x880 }, + { 0x4005a, 0x0 }, + { 0x4007a, 0x0 }, + { 0x900a4, 0x0 }, + { 0x900a5, 0x790 }, + { 0x900a6, 0x11a }, + { 0x900a7, 0x8 }, + { 0x900a8, 0x7aa }, + { 0x900a9, 0x2a }, + { 0x900aa, 0x10 }, + { 0x900ab, 0x7b2 }, + { 0x900ac, 0x2a }, + { 0x900ad, 0x0 }, + { 0x900ae, 0x7c8 }, + { 0x900af, 0x109 }, + { 0x900b0, 0x10 }, + { 0x900b1, 0x10 }, + { 0x900b2, 0x109 }, + { 0x900b3, 0x10 }, + { 0x900b4, 0x2a8 }, + { 0x900b5, 0x129 }, + { 0x900b6, 0x8 }, + { 0x900b7, 0x370 }, + { 0x900b8, 0x129 }, + { 0x900b9, 0xa }, + { 0x900ba, 0x3c8 }, + { 0x900bb, 0x1a9 }, + { 0x900bc, 0xc }, + { 0x900bd, 0x408 }, + { 0x900be, 0x199 }, + { 0x900bf, 0x14 }, + { 0x900c0, 0x790 }, + { 0x900c1, 0x11a }, + { 0x900c2, 0x8 }, + { 0x900c3, 0x4 }, + { 0x900c4, 0x18 }, + { 0x900c5, 0xe }, + { 0x900c6, 0x408 }, + { 0x900c7, 0x199 }, + { 0x900c8, 0x8 }, + { 0x900c9, 0x8568 }, + { 0x900ca, 0x108 }, + { 0x900cb, 0x18 }, + { 0x900cc, 0x790 }, + { 0x900cd, 0x16a }, + { 0x900ce, 0x8 }, + { 0x900cf, 0x1d8 }, + { 0x900d0, 0x169 }, + { 0x900d1, 0x10 }, + { 0x900d2, 0x8558 }, + { 0x900d3, 0x168 }, + { 0x900d4, 0x70 }, + { 0x900d5, 0x788 }, + { 0x900d6, 0x16a }, + { 0x900d7, 0x1ff8 }, + { 0x900d8, 0x85a8 }, + { 0x900d9, 0x1e8 }, + { 0x900da, 0x50 }, + { 0x900db, 0x798 }, + { 0x900dc, 0x16a }, + { 0x900dd, 0x60 }, + { 0x900de, 0x7a0 }, + { 0x900df, 0x16a }, + { 0x900e0, 0x8 }, + { 0x900e1, 0x8310 }, + { 0x900e2, 0x168 }, + { 0x900e3, 0x8 }, + { 0x900e4, 0xa310 }, + { 0x900e5, 0x168 }, + { 0x900e6, 0xa }, + { 0x900e7, 0x408 }, + { 0x900e8, 0x169 }, + { 0x900e9, 0x6e }, + { 0x900ea, 0x0 }, + { 0x900eb, 0x68 }, + { 0x900ec, 0x0 }, + { 0x900ed, 0x408 }, + { 0x900ee, 0x169 }, + { 0x900ef, 0x0 }, + { 0x900f0, 0x8310 }, + { 0x900f1, 0x168 }, + { 0x900f2, 0x0 }, + { 0x900f3, 0xa310 }, + { 0x900f4, 0x168 }, + { 0x900f5, 0x1ff8 }, + { 0x900f6, 0x85a8 }, + { 0x900f7, 0x1e8 }, + { 0x900f8, 0x68 }, + { 0x900f9, 0x798 }, + { 0x900fa, 0x16a }, + { 0x900fb, 0x78 }, + { 0x900fc, 0x7a0 }, + { 0x900fd, 0x16a }, + { 0x900fe, 0x68 }, + { 0x900ff, 0x790 }, + { 0x90100, 0x16a }, + { 0x90101, 0x8 }, + { 0x90102, 0x8b10 }, + { 0x90103, 0x168 }, + { 0x90104, 0x8 }, + { 0x90105, 0xab10 }, + { 0x90106, 0x168 }, + { 0x90107, 0xa }, + { 0x90108, 0x408 }, + { 0x90109, 0x169 }, + { 0x9010a, 0x58 }, + { 0x9010b, 0x0 }, + { 0x9010c, 0x68 }, + { 0x9010d, 0x0 }, + { 0x9010e, 0x408 }, + { 0x9010f, 0x169 }, + { 0x90110, 0x0 }, + { 0x90111, 0x8b10 }, + { 0x90112, 0x168 }, + { 0x90113, 0x1 }, + { 0x90114, 0xab10 }, + { 0x90115, 0x168 }, + { 0x90116, 0x0 }, + { 0x90117, 0x1d8 }, + { 0x90118, 0x169 }, + { 0x90119, 0x80 }, + { 0x9011a, 0x790 }, + { 0x9011b, 0x16a }, + { 0x9011c, 0x18 }, + { 0x9011d, 0x7aa }, + { 0x9011e, 0x6a }, + { 0x9011f, 0xa }, + { 0x90120, 0x0 }, + { 0x90121, 0x1e9 }, + { 0x90122, 0x8 }, + { 0x90123, 0x8080 }, + { 0x90124, 0x108 }, + { 0x90125, 0xf }, + { 0x90126, 0x408 }, + { 0x90127, 0x169 }, + { 0x90128, 0xc }, + { 0x90129, 0x0 }, + { 0x9012a, 0x68 }, + { 0x9012b, 0x9 }, + { 0x9012c, 0x0 }, + { 0x9012d, 0x1a9 }, + { 0x9012e, 0x0 }, + { 0x9012f, 0x408 }, + { 0x90130, 0x169 }, + { 0x90131, 0x0 }, + { 0x90132, 0x8080 }, + { 0x90133, 0x108 }, + { 0x90134, 0x8 }, + { 0x90135, 0x7aa }, + { 0x90136, 0x6a }, + { 0x90137, 0x0 }, + { 0x90138, 0x8568 }, + { 0x90139, 0x108 }, + { 0x9013a, 0xb7 }, + { 0x9013b, 0x790 }, + { 0x9013c, 0x16a }, + { 0x9013d, 0x1f }, + { 0x9013e, 0x0 }, + { 0x9013f, 0x68 }, + { 0x90140, 0x8 }, + { 0x90141, 0x8558 }, + { 0x90142, 0x168 }, + { 0x90143, 0xf }, + { 0x90144, 0x408 }, + { 0x90145, 0x169 }, + { 0x90146, 0xd }, + { 0x90147, 0x0 }, + { 0x90148, 0x68 }, + { 0x90149, 0x0 }, + { 0x9014a, 0x408 }, + { 0x9014b, 0x169 }, + { 0x9014c, 0x0 }, + { 0x9014d, 0x8558 }, + { 0x9014e, 0x168 }, + { 0x9014f, 0x8 }, + { 0x90150, 0x3c8 }, + { 0x90151, 0x1a9 }, + { 0x90152, 0x3 }, + { 0x90153, 0x370 }, + { 0x90154, 0x129 }, + { 0x90155, 0x20 }, + { 0x90156, 0x2aa }, + { 0x90157, 0x9 }, + { 0x90158, 0x8 }, + { 0x90159, 0xe8 }, + { 0x9015a, 0x109 }, + { 0x9015b, 0x0 }, + { 0x9015c, 0x8140 }, + { 0x9015d, 0x10c }, + { 0x9015e, 0x10 }, + { 0x9015f, 0x8138 }, + { 0x90160, 0x104 }, + { 0x90161, 0x8 }, + { 0x90162, 0x448 }, + { 0x90163, 0x109 }, + { 0x90164, 0xf }, + { 0x90165, 0x7c0 }, + { 0x90166, 0x109 }, + { 0x90167, 0x0 }, + { 0x90168, 0xe8 }, + { 0x90169, 0x109 }, + { 0x9016a, 0x47 }, + { 0x9016b, 0x630 }, + { 0x9016c, 0x109 }, + { 0x9016d, 0x8 }, + { 0x9016e, 0x618 }, + { 0x9016f, 0x109 }, + { 0x90170, 0x8 }, + { 0x90171, 0xe0 }, + { 0x90172, 0x109 }, + { 0x90173, 0x0 }, + { 0x90174, 0x7c8 }, + { 0x90175, 0x109 }, + { 0x90176, 0x8 }, + { 0x90177, 0x8140 }, + { 0x90178, 0x10c }, + { 0x90179, 0x0 }, + { 0x9017a, 0x478 }, + { 0x9017b, 0x109 }, + { 0x9017c, 0x0 }, + { 0x9017d, 0x1 }, + { 0x9017e, 0x8 }, + { 0x9017f, 0x8 }, + { 0x90180, 0x4 }, + { 0x90181, 0x0 }, + { 0x90006, 0x8 }, + { 0x90007, 0x7c8 }, + { 0x90008, 0x109 }, + { 0x90009, 0x0 }, + { 0x9000a, 0x400 }, + { 0x9000b, 0x106 }, + { 0xd00e7, 0x400 }, + { 0x90017, 0x0 }, + { 0x9001f, 0x29 }, + { 0x90026, 0x68 }, + { 0x400d0, 0x0 }, + { 0x400d1, 0x101 }, + { 0x400d2, 0x105 }, + { 0x400d3, 0x107 }, + { 0x400d4, 0x10f }, + { 0x400d5, 0x202 }, + { 0x400d6, 0x20a }, + { 0x400d7, 0x20b }, + { 0x2003a, 0x2 }, + { 0x200be, 0x3 }, + { 0x2000b, 0x34b }, + { 0x2000c, 0xbb }, + { 0x2000d, 0x753 }, + { 0x2000e, 0x2c }, + { 0x12000b, 0x70 }, + { 0x12000c, 0x19 }, + { 0x12000d, 0xfa }, + { 0x12000e, 0x10 }, + { 0x22000b, 0x1c }, + { 0x22000c, 0x6 }, + { 0x22000d, 0x3e }, + { 0x22000e, 0x10 }, + { 0x9000c, 0x0 }, + { 0x9000d, 0x173 }, + { 0x9000e, 0x60 }, + { 0x9000f, 0x6110 }, + { 0x90010, 0x2152 }, + { 0x90011, 0xdfbd }, + { 0x90012, 0x2060 }, + { 0x90013, 0x6152 }, + { 0x20010, 0x5a }, + { 0x20011, 0x3 }, + { 0x40080, 0xe0 }, + { 0x40081, 0x12 }, + { 0x40082, 0xe0 }, + { 0x40083, 0x12 }, + { 0x40084, 0xe0 }, + { 0x40085, 0x12 }, + { 0x140080, 0xe0 }, + { 0x140081, 0x12 }, + { 0x140082, 0xe0 }, + { 0x140083, 0x12 }, + { 0x140084, 0xe0 }, + { 0x140085, 0x12 }, + { 0x240080, 0xe0 }, + { 0x240081, 0x12 }, + { 0x240082, 0xe0 }, + { 0x240083, 0x12 }, + { 0x240084, 0xe0 }, + { 0x240085, 0x12 }, + { 0x400fd, 0xf }, + { 0x10011, 0x1 }, + { 0x10012, 0x1 }, + { 0x10013, 0x180 }, + { 0x10018, 0x1 }, + { 0x10002, 0x6209 }, + { 0x100b2, 0x1 }, + { 0x101b4, 0x1 }, + { 0x102b4, 0x1 }, + { 0x103b4, 0x1 }, + { 0x104b4, 0x1 }, + { 0x105b4, 0x1 }, + { 0x106b4, 0x1 }, + { 0x107b4, 0x1 }, + { 0x108b4, 0x1 }, + { 0x11011, 0x1 }, + { 0x11012, 0x1 }, + { 0x11013, 0x180 }, + { 0x11018, 0x1 }, + { 0x11002, 0x6209 }, + { 0x110b2, 0x1 }, + { 0x111b4, 0x1 }, + { 0x112b4, 0x1 }, + { 0x113b4, 0x1 }, + { 0x114b4, 0x1 }, + { 0x115b4, 0x1 }, + { 0x116b4, 0x1 }, + { 0x117b4, 0x1 }, + { 0x118b4, 0x1 }, + { 0x12011, 0x1 }, + { 0x12012, 0x1 }, + { 0x12013, 0x180 }, + { 0x12018, 0x1 }, + { 0x12002, 0x6209 }, + { 0x120b2, 0x1 }, + { 0x121b4, 0x1 }, + { 0x122b4, 0x1 }, + { 0x123b4, 0x1 }, + { 0x124b4, 0x1 }, + { 0x125b4, 0x1 }, + { 0x126b4, 0x1 }, + { 0x127b4, 0x1 }, + { 0x128b4, 0x1 }, + { 0x13011, 0x1 }, + { 0x13012, 0x1 }, + { 0x13013, 0x180 }, + { 0x13018, 0x1 }, + { 0x13002, 0x6209 }, + { 0x130b2, 0x1 }, + { 0x131b4, 0x1 }, + { 0x132b4, 0x1 }, + { 0x133b4, 0x1 }, + { 0x134b4, 0x1 }, + { 0x135b4, 0x1 }, + { 0x136b4, 0x1 }, + { 0x137b4, 0x1 }, + { 0x138b4, 0x1 }, + { 0x20089, 0x1 }, + { 0x20088, 0x19 }, + { 0xc0080, 0x2 }, + { 0xd0000, 0x1 } +}; + +/* + * Generated code from MX8M_DDR_tool v3.30 using MX8M Plus RPAv7 + * - 4GiB: imx8mp-gw7401 1x Micron MT53D1024M32D4DT 2-ch dual-die per channel + */ +/* P0 message block paremeter for training firmware */ +static struct dram_cfg_param ddr_ddrc_cfg_4gb_dual_die[] = { + /** Initialize DDRC registers **/ + { 0x3d400304, 0x1 }, + { 0x3d400030, 0x1 }, + { 0x3d400000, 0xa3080020 }, + { 0x3d400020, 0x1203 }, + { 0x3d400024, 0x16e3600 }, + { 0x3d400064, 0x5b00d2 }, + { 0x3d400070, 0x7027f90 }, + { 0x3d400074, 0x790 }, + { 0x3d4000d0, 0xc00305ba }, + { 0x3d4000d4, 0x940000 }, + { 0x3d4000dc, 0xd4002d }, + { 0x3d4000e0, 0x310000 }, + { 0x3d4000e8, 0x660048 }, + { 0x3d4000ec, 0x160048 }, + { 0x3d400100, 0x191e1920 }, + { 0x3d400104, 0x60630 }, + { 0x3d40010c, 0xb0b000 }, + { 0x3d400110, 0xe04080e }, + { 0x3d400114, 0x2040c0c }, + { 0x3d400118, 0x1010007 }, + { 0x3d40011c, 0x401 }, + { 0x3d400130, 0x20600 }, + { 0x3d400134, 0xc100002 }, + { 0x3d400138, 0xd8 }, + { 0x3d400144, 0x96004b }, + { 0x3d400180, 0x2ee0017 }, + { 0x3d400184, 0x2605b8e }, + { 0x3d400188, 0x0 }, + { 0x3d400190, 0x497820a }, + { 0x3d400194, 0x80303 }, + { 0x3d4001b4, 0x170a }, + { 0x3d4001a0, 0xe0400018 }, + { 0x3d4001a4, 0xdf00e4 }, + { 0x3d4001a8, 0x80000000 }, + { 0x3d4001b0, 0x11 }, + { 0x3d4001c0, 0x1 }, + { 0x3d4001c4, 0x1 }, + { 0x3d4000f4, 0xc99 }, + { 0x3d400108, 0x70e1617 }, + { 0x3d400200, 0x17 }, + { 0x3d40020c, 0x0 }, + { 0x3d400210, 0x1f1f }, + { 0x3d400204, 0x80808 }, + { 0x3d400214, 0x7070707 }, + { 0x3d400218, 0x7070707 }, + { 0x3d40021c, 0xf0f }, + { 0x3d400250, 0x1705 }, + { 0x3d400254, 0x2c }, + { 0x3d40025c, 0x4000030 }, + { 0x3d400264, 0x900093e7 }, + { 0x3d40026c, 0x2005574 }, + { 0x3d400400, 0x111 }, + { 0x3d400404, 0x72ff }, + { 0x3d400408, 0x72ff }, + { 0x3d400494, 0x2100e07 }, + { 0x3d400498, 0x620096 }, + { 0x3d40049c, 0x1100e07 }, + { 0x3d4004a0, 0xc8012c }, + { 0x3d402020, 0x1001 }, + { 0x3d402024, 0x30d400 }, + { 0x3d402050, 0x20d000 }, + { 0x3d402064, 0xc001c }, + { 0x3d4020dc, 0x840000 }, + { 0x3d4020e0, 0x330000 }, + { 0x3d4020e8, 0x660048 }, + { 0x3d4020ec, 0x160048 }, + { 0x3d402100, 0xa040305 }, + { 0x3d402104, 0x30407 }, + { 0x3d402108, 0x203060b }, + { 0x3d40210c, 0x505000 }, + { 0x3d402110, 0x2040202 }, + { 0x3d402114, 0x2030202 }, + { 0x3d402118, 0x1010004 }, + { 0x3d40211c, 0x301 }, + { 0x3d402130, 0x20300 }, + { 0x3d402134, 0xa100002 }, + { 0x3d402138, 0x1d }, + { 0x3d402144, 0x14000a }, + { 0x3d402180, 0x640004 }, + { 0x3d402190, 0x3818200 }, + { 0x3d402194, 0x80303 }, + { 0x3d4021b4, 0x100 }, + { 0x3d4020f4, 0xc99 }, + { 0x3d403020, 0x1001 }, + { 0x3d403024, 0xc3500 }, + { 0x3d403050, 0x20d000 }, + { 0x3d403064, 0x30007 }, + { 0x3d4030dc, 0x840000 }, + { 0x3d4030e0, 0x330000 }, + { 0x3d4030e8, 0x660048 }, + { 0x3d4030ec, 0x160048 }, + { 0x3d403100, 0xa010102 }, + { 0x3d403104, 0x30404 }, + { 0x3d403108, 0x203060b }, + { 0x3d40310c, 0x505000 }, + { 0x3d403110, 0x2040202 }, + { 0x3d403114, 0x2030202 }, + { 0x3d403118, 0x1010004 }, + { 0x3d40311c, 0x301 }, + { 0x3d403130, 0x20300 }, + { 0x3d403134, 0xa100002 }, + { 0x3d403138, 0x8 }, + { 0x3d403144, 0x50003 }, + { 0x3d403180, 0x190004 }, + { 0x3d403190, 0x3818200 }, + { 0x3d403194, 0x80303 }, + { 0x3d4031b4, 0x100 }, + { 0x3d4030f4, 0xc99 }, + { 0x3d400028, 0x0 }, +}; + +/* PHY Initialize Configuration */ +static struct dram_cfg_param ddr_ddrphy_cfg_4gb_dual_die[] = { + { 0x100a0, 0x0 }, + { 0x100a1, 0x1 }, + { 0x100a2, 0x3 }, + { 0x100a3, 0x2 }, + { 0x100a4, 0x5 }, + { 0x100a5, 0x4 }, + { 0x100a6, 0x7 }, + { 0x100a7, 0x6 }, + { 0x110a0, 0x0 }, + { 0x110a1, 0x1 }, + { 0x110a2, 0x2 }, + { 0x110a3, 0x3 }, + { 0x110a4, 0x4 }, + { 0x110a5, 0x5 }, + { 0x110a6, 0x6 }, + { 0x110a7, 0x7 }, + { 0x120a0, 0x0 }, + { 0x120a1, 0x1 }, + { 0x120a2, 0x2 }, + { 0x120a3, 0x3 }, + { 0x120a4, 0x4 }, + { 0x120a5, 0x5 }, + { 0x120a6, 0x6 }, + { 0x120a7, 0x7 }, + { 0x130a0, 0x0 }, + { 0x130a1, 0x1 }, + { 0x130a2, 0x3 }, + { 0x130a3, 0x4 }, + { 0x130a4, 0x5 }, + { 0x130a5, 0x2 }, + { 0x130a6, 0x7 }, + { 0x130a7, 0x6 }, + { 0x1005f, 0x1ff }, + { 0x1015f, 0x1ff }, + { 0x1105f, 0x1ff }, + { 0x1115f, 0x1ff }, + { 0x1205f, 0x1ff }, + { 0x1215f, 0x1ff }, + { 0x1305f, 0x1ff }, + { 0x1315f, 0x1ff }, + { 0x11005f, 0x1ff }, + { 0x11015f, 0x1ff }, + { 0x11105f, 0x1ff }, + { 0x11115f, 0x1ff }, + { 0x11205f, 0x1ff }, + { 0x11215f, 0x1ff }, + { 0x11305f, 0x1ff }, + { 0x11315f, 0x1ff }, + { 0x21005f, 0x1ff }, + { 0x21015f, 0x1ff }, + { 0x21105f, 0x1ff }, + { 0x21115f, 0x1ff }, + { 0x21205f, 0x1ff }, + { 0x21215f, 0x1ff }, + { 0x21305f, 0x1ff }, + { 0x21315f, 0x1ff }, + { 0x55, 0x1ff }, + { 0x1055, 0x1ff }, + { 0x2055, 0x1ff }, + { 0x3055, 0x1ff }, + { 0x4055, 0x1ff }, + { 0x5055, 0x1ff }, + { 0x6055, 0x1ff }, + { 0x7055, 0x1ff }, + { 0x8055, 0x1ff }, + { 0x9055, 0x1ff }, + { 0x200c5, 0x19 }, + { 0x1200c5, 0x7 }, + { 0x2200c5, 0x7 }, + { 0x2002e, 0x2 }, + { 0x12002e, 0x2 }, + { 0x22002e, 0x2 }, + { 0x90204, 0x0 }, + { 0x190204, 0x0 }, + { 0x290204, 0x0 }, + { 0x20024, 0x1a3 }, + { 0x2003a, 0x2 }, + { 0x120024, 0x1a3 }, + { 0x2003a, 0x2 }, + { 0x220024, 0x1a3 }, + { 0x2003a, 0x2 }, + { 0x20056, 0x3 }, + { 0x120056, 0x3 }, + { 0x220056, 0x3 }, + { 0x1004d, 0xe00 }, + { 0x1014d, 0xe00 }, + { 0x1104d, 0xe00 }, + { 0x1114d, 0xe00 }, + { 0x1204d, 0xe00 }, + { 0x1214d, 0xe00 }, + { 0x1304d, 0xe00 }, + { 0x1314d, 0xe00 }, + { 0x11004d, 0xe00 }, + { 0x11014d, 0xe00 }, + { 0x11104d, 0xe00 }, + { 0x11114d, 0xe00 }, + { 0x11204d, 0xe00 }, + { 0x11214d, 0xe00 }, + { 0x11304d, 0xe00 }, + { 0x11314d, 0xe00 }, + { 0x21004d, 0xe00 }, + { 0x21014d, 0xe00 }, + { 0x21104d, 0xe00 }, + { 0x21114d, 0xe00 }, + { 0x21204d, 0xe00 }, + { 0x21214d, 0xe00 }, + { 0x21304d, 0xe00 }, + { 0x21314d, 0xe00 }, + { 0x10049, 0xeba }, + { 0x10149, 0xeba }, + { 0x11049, 0xeba }, + { 0x11149, 0xeba }, + { 0x12049, 0xeba }, + { 0x12149, 0xeba }, + { 0x13049, 0xeba }, + { 0x13149, 0xeba }, + { 0x110049, 0xeba }, + { 0x110149, 0xeba }, + { 0x111049, 0xeba }, + { 0x111149, 0xeba }, + { 0x112049, 0xeba }, + { 0x112149, 0xeba }, + { 0x113049, 0xeba }, + { 0x113149, 0xeba }, + { 0x210049, 0xeba }, + { 0x210149, 0xeba }, + { 0x211049, 0xeba }, + { 0x211149, 0xeba }, + { 0x212049, 0xeba }, + { 0x212149, 0xeba }, + { 0x213049, 0xeba }, + { 0x213149, 0xeba }, + { 0x43, 0x63 }, + { 0x1043, 0x63 }, + { 0x2043, 0x63 }, + { 0x3043, 0x63 }, + { 0x4043, 0x63 }, + { 0x5043, 0x63 }, + { 0x6043, 0x63 }, + { 0x7043, 0x63 }, + { 0x8043, 0x63 }, + { 0x9043, 0x63 }, + { 0x20018, 0x3 }, + { 0x20075, 0x4 }, + { 0x20050, 0x0 }, + { 0x20008, 0x2ee }, + { 0x120008, 0x64 }, + { 0x220008, 0x19 }, + { 0x20088, 0x9 }, + { 0x200b2, 0x104 }, + { 0x10043, 0x5a1 }, + { 0x10143, 0x5a1 }, + { 0x11043, 0x5a1 }, + { 0x11143, 0x5a1 }, + { 0x12043, 0x5a1 }, + { 0x12143, 0x5a1 }, + { 0x13043, 0x5a1 }, + { 0x13143, 0x5a1 }, + { 0x1200b2, 0x104 }, + { 0x110043, 0x5a1 }, + { 0x110143, 0x5a1 }, + { 0x111043, 0x5a1 }, + { 0x111143, 0x5a1 }, + { 0x112043, 0x5a1 }, + { 0x112143, 0x5a1 }, + { 0x113043, 0x5a1 }, + { 0x113143, 0x5a1 }, + { 0x2200b2, 0x104 }, + { 0x210043, 0x5a1 }, + { 0x210143, 0x5a1 }, + { 0x211043, 0x5a1 }, + { 0x211143, 0x5a1 }, + { 0x212043, 0x5a1 }, + { 0x212143, 0x5a1 }, + { 0x213043, 0x5a1 }, + { 0x213143, 0x5a1 }, + { 0x200fa, 0x1 }, + { 0x1200fa, 0x1 }, + { 0x2200fa, 0x1 }, + { 0x20019, 0x1 }, + { 0x120019, 0x1 }, + { 0x220019, 0x1 }, + { 0x200f0, 0x660 }, + { 0x200f1, 0x0 }, + { 0x200f2, 0x4444 }, + { 0x200f3, 0x8888 }, + { 0x200f4, 0x5665 }, + { 0x200f5, 0x0 }, + { 0x200f6, 0x0 }, + { 0x200f7, 0xf000 }, + { 0x20025, 0x0 }, + { 0x2002d, 0x0 }, + { 0x12002d, 0x0 }, + { 0x22002d, 0x0 }, + { 0x2007d, 0x212 }, + { 0x12007d, 0x212 }, + { 0x22007d, 0x212 }, + { 0x2007c, 0x61 }, + { 0x12007c, 0x61 }, + { 0x22007c, 0x61 }, + { 0x1004a, 0x500 }, + { 0x1104a, 0x500 }, + { 0x1204a, 0x500 }, + { 0x1304a, 0x500 }, + { 0x2002c, 0x0 }, +}; + +static struct dram_cfg_param ddr_fsp0_cfg_4gb_dual_die[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0xbb8 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x14 }, + { 0x54008, 0x131f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54012, 0x310 }, + { 0x54019, 0x2dd4 }, + { 0x5401a, 0x31 }, + { 0x5401b, 0x4866 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x2dd4 }, + { 0x54020, 0x31 }, + { 0x54021, 0x4866 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x3 }, + { 0x54032, 0xd400 }, + { 0x54033, 0x312d }, + { 0x54034, 0x6600 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1600 }, + { 0x54038, 0xd400 }, + { 0x54039, 0x312d }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x48 }, + { 0x5403c, 0x48 }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + +/* P1 message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp1_cfg_4gb_dual_die[] = { + { 0xd0000, 0x0 }, + { 0x54002, 0x101 }, + { 0x54003, 0x190 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x14 }, + { 0x54008, 0x121f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54012, 0x310 }, + { 0x54019, 0x84 }, + { 0x5401a, 0x33 }, + { 0x5401b, 0x4866 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x84 }, + { 0x54020, 0x33 }, + { 0x54021, 0x4866 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x3 }, + { 0x54032, 0x8400 }, + { 0x54033, 0x3300 }, + { 0x54034, 0x6600 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1600 }, + { 0x54038, 0x8400 }, + { 0x54039, 0x3300 }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x48 }, + { 0x5403c, 0x48 }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + +/* P2 message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp2_cfg_4gb_dual_die[] = { + { 0xd0000, 0x0 }, + { 0x54002, 0x102 }, + { 0x54003, 0x64 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x14 }, + { 0x54008, 0x121f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54012, 0x310 }, + { 0x54019, 0x84 }, + { 0x5401a, 0x33 }, + { 0x5401b, 0x4866 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x84 }, + { 0x54020, 0x33 }, + { 0x54021, 0x4866 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x3 }, + { 0x54032, 0x8400 }, + { 0x54033, 0x3300 }, + { 0x54034, 0x6600 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1600 }, + { 0x54038, 0x8400 }, + { 0x54039, 0x3300 }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x48 }, + { 0x5403c, 0x48 }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + +/* P0 2D message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp0_2d_cfg_4gb_dual_die[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0xbb8 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x14 }, + { 0x54008, 0x61 }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54010, 0x1f7f }, + { 0x54012, 0x310 }, + { 0x54019, 0x2dd4 }, + { 0x5401a, 0x31 }, + { 0x5401b, 0x4866 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x2dd4 }, + { 0x54020, 0x31 }, + { 0x54021, 0x4866 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x3 }, + { 0x54032, 0xd400 }, + { 0x54033, 0x312d }, + { 0x54034, 0x6600 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1600 }, + { 0x54038, 0xd400 }, + { 0x54039, 0x312d }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x48 }, + { 0x5403c, 0x48 }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + +static struct dram_fsp_msg ddr_dram_fsp_msg_4gb_dual_die[] = { + { + /* P0 3000mts 1D */ + .drate = 3000, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg_4gb_dual_die, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg_4gb_dual_die), + }, + { + /* P1 400mts 1D */ + .drate = 400, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp1_cfg_4gb_dual_die, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg_4gb_dual_die), + }, + { + /* P2 100mts 1D */ + .drate = 100, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp2_cfg_4gb_dual_die, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg_4gb_dual_die), + }, + { + /* P0 3000mts 2D */ + .drate = 3000, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg_4gb_dual_die, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg_4gb_dual_die), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info dram_timing_4gb_dual_die = { + .ddrc_cfg = ddr_ddrc_cfg_4gb_dual_die, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg_4gb_dual_die), + .ddrphy_cfg = ddr_ddrphy_cfg_4gb_dual_die, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg_4gb_dual_die), + .fsp_msg = ddr_dram_fsp_msg_4gb_dual_die, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg_4gb_dual_die), + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 3000, 400, 100, }, +}; diff --git a/board/gateworks/venice/spl.c b/board/gateworks/venice/spl.c index b56e1b6..223f22d 100644 --- a/board/gateworks/venice/spl.c +++ b/board/gateworks/venice/spl.c @@ -7,36 +7,29 @@ #include <cpu_func.h> #include <hang.h> #include <i2c.h> -#include <image.h> #include <init.h> -#include <log.h> #include <spl.h> -#include <asm/io.h> #include <asm/mach-imx/gpio.h> -#include <asm/mach-imx/iomux-v3.h> #include <asm/arch/clock.h> #include <asm/arch/imx8mm_pins.h> #include <asm/arch/imx8mn_pins.h> +#include <asm/arch/imx8mp_pins.h> #include <asm/arch/sys_proto.h> #include <asm/mach-imx/boot_mode.h> #include <asm/arch/ddr.h> #include <asm-generic/gpio.h> - #include <dm/uclass.h> #include <dm/device.h> -#include <dm/uclass-internal.h> -#include <dm/device-internal.h> - +#include <linux/delay.h> #include <power/bd71837.h> #include <power/mp5416.h> +#include <power/pca9450.h> -#include "gsc.h" +#include "eeprom.h" #include "lpddr4_timing.h" #define PCIE_RSTN IMX_GPIO_NR(4, 6) -DECLARE_GLOBAL_DATA_PTR; - static void spl_dram_init(int size) { struct dram_timing_info *dram_timing; @@ -59,14 +52,13 @@ static void spl_dram_init(int size) printf("Unknown DDR configuration: %d MiB\n", size); dram_timing = &dram_timing_1gb; size = 1024; -#endif -#ifdef CONFIG_IMX8MN +#elif CONFIG_IMX8MN case 1024: dram_timing = &dram_timing_1gb_single_die; break; case 2048: - if (!strcmp(gsc_get_model(), "GW7902-SP466-A") || - !strcmp(gsc_get_model(), "GW7902-SP466-B")) { + if (!strcmp(eeprom_get_model(), "GW7902-SP466-A") || + !strcmp(eeprom_get_model(), "GW7902-SP466-B")) { dram_timing = &dram_timing_2gb_dual_die; } else { dram_timing = &dram_timing_2gb_single_die; @@ -76,6 +68,14 @@ static void spl_dram_init(int size) printf("Unknown DDR configuration: %d MiB\n", size); dram_timing = &dram_timing_2gb_dual_die; size = 2048; +#elif CONFIG_IMX8MP + case 4096: + dram_timing = &dram_timing_4gb_dual_die; + break; + default: + printf("Unknown DDR configuration: %d GiB\n", size); + dram_timing = &dram_timing_4gb_dual_die; + size = 4096; #endif } @@ -99,8 +99,7 @@ static iomux_v3_cfg_t const uart_pads[] = { static iomux_v3_cfg_t const wdog_pads[] = { IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), }; -#endif -#ifdef CONFIG_IMX8MN +#elif CONFIG_IMX8MN static const iomux_v3_cfg_t uart_pads[] = { IMX8MN_PAD_UART2_RXD__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), IMX8MN_PAD_UART2_TXD__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), @@ -109,6 +108,16 @@ static const iomux_v3_cfg_t uart_pads[] = { static const iomux_v3_cfg_t wdog_pads[] = { IMX8MN_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), }; +#elif CONFIG_IMX8MP +static const iomux_v3_cfg_t uart_pads[] = { + MX8MP_PAD_UART2_RXD__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX8MP_PAD_UART2_TXD__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static const iomux_v3_cfg_t wdog_pads[] = { + MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), +}; + #endif int board_early_init_f(void) @@ -149,7 +158,7 @@ static int dm_i2c_clrsetbits(struct udevice *dev, uint reg, uint clr, uint set) static int power_init_board(void) { - const char *model = gsc_get_model(); + const char *model = eeprom_get_model(); struct udevice *bus; struct udevice *dev; int ret; @@ -174,6 +183,41 @@ static int power_init_board(void) BIT(7) | MP5416_VSET_SW3_SVAL(920000)); } + else if (!strncmp(model, "GW74", 4)) { + ret = uclass_get_device_by_seq(UCLASS_I2C, 0, &bus); + if (ret) { + printf("PMIC : failed I2C1 probe: %d\n", ret); + return ret; + } + ret = dm_i2c_probe(bus, 0x25, 0, &dev); + if (ret) { + printf("PMIC : failed probe: %d\n", ret); + return ret; + } + puts("PMIC : PCA9450\n"); + + /* BUCKxOUT_DVS0/1 control BUCK123 output */ + dm_i2c_reg_write(dev, PCA9450_BUCK123_DVS, 0x29); + + /* Buck 1 DVS control through PMIC_STBY_REQ */ + dm_i2c_reg_write(dev, PCA9450_BUCK1CTRL, 0x59); + + /* Set DVS1 to 0.8v for suspend */ + dm_i2c_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x10); + + /* increase VDD_DRAM to 0.95v for 3Ghz DDR */ + dm_i2c_reg_write(dev, PCA9450_BUCK3OUT_DVS0, 0x1C); + + /* VDD_DRAM off in suspend: B1_ENMODE=10 */ + dm_i2c_reg_write(dev, PCA9450_BUCK3CTRL, 0x4a); + + /* set VDD_SNVS_0V8 from default 0.85V */ + dm_i2c_reg_write(dev, PCA9450_LDO2CTRL, 0xC0); + + /* set WDOG_B_CFG to cold reset */ + dm_i2c_reg_write(dev, PCA9450_RESET_CTRL, 0xA1); + } + else if ((!strncmp(model, "GW7901", 6)) || (!strncmp(model, "GW7902", 6))) { if (!strncmp(model, "GW7901", 6)) @@ -243,22 +287,36 @@ void board_init_f(ulong dummy) hang(); } - ret = uclass_get_device_by_name(UCLASS_CLK, - "clock-controller@30380000", - &dev); - if (ret < 0) { - printf("Failed to find clock node. Check device tree\n"); - hang(); - } - enable_tzc380(); /* need to hold PCIe switch in reset otherwise it can lock i2c bus EEPROM is on */ gpio_request(PCIE_RSTN, "perst#"); gpio_direction_output(PCIE_RSTN, 0); - /* GSC */ - dram_sz = gsc_init(0); + /* + * probe GSC device + * + * On a board with a missing/depleted backup battery for GSC, the + * board may be ready to probe the GSC before its firmware is + * running. We will wait here indefinately for the GSC EEPROM. + */ +#ifdef CONFIG_IMX8MN + /* + * IMX8MN boots quicker than IMX8MM and exposes issue + * where because GSC I2C state machine isn't running and its + * SCL/SDA are driven low the I2C driver spams 'Arbitration lost' + * I2C errors. + * + * TODO: Put a loop here that somehow waits for I2C CLK/DAT to be high + */ + mdelay(50); +#endif + while (1) { + if (!uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(gsc), &dev)) + break; + mdelay(1); + } + dram_sz = eeprom_init(0); /* PMIC */ power_init_board(); @@ -272,15 +330,22 @@ void board_init_f(ulong dummy) /* determine prioritized order of boot devices to load U-Boot from */ void board_boot_order(u32 *spl_boot_list) { + int i = 0; + /* * If the SPL was loaded via serial loader, we try to get * U-Boot proper via USB SDP. */ - if (spl_boot_device() == BOOT_DEVICE_BOARD) - spl_boot_list[0] = BOOT_DEVICE_BOARD; + if (spl_boot_device() == BOOT_DEVICE_BOARD) { +#ifdef CONFIG_IMX8MM + spl_boot_list[i++] = BOOT_DEVICE_BOARD; +#else + spl_boot_list[i++] = BOOT_DEVICE_BOOTROM; +#endif + } /* we have only eMMC in default venice dt */ - spl_boot_list[0] = BOOT_DEVICE_MMC1; + spl_boot_list[i++] = BOOT_DEVICE_MMC1; } /* return boot device based on where the SPL was loaded from */ diff --git a/board/gateworks/venice/venice.c b/board/gateworks/venice/venice.c index 425c690..4290a69 100644 --- a/board/gateworks/venice/venice.c +++ b/board/gateworks/venice/venice.c @@ -3,21 +3,13 @@ * Copyright 2021 Gateworks Corporation */ -#include <common.h> #include <init.h> #include <led.h> -#include <linux/delay.h> #include <miiphy.h> -#include <netdev.h> - #include <asm/arch/clock.h> #include <asm/arch/sys_proto.h> -#include <asm/io.h> -#include <asm/unaligned.h> - -#include "gsc.h" -DECLARE_GLOBAL_DATA_PTR; +#include "eeprom.h" int board_phys_sdram_size(phys_size_t *size) { @@ -37,7 +29,7 @@ int board_fit_config_name_match(const char *name) char buf[32]; do { - dtb = gsc_get_dtb_name(i++, buf, sizeof(buf)); + dtb = eeprom_get_dtb_name(i++, buf, sizeof(buf)); if (!strcmp(dtb, name)) { if (!init++) printf("DTB : %s\n", name); @@ -48,18 +40,36 @@ int board_fit_config_name_match(const char *name) return -1; } -#if (IS_ENABLED(CONFIG_FEC_MXC)) +#if (IS_ENABLED(CONFIG_NET)) static int setup_fec(void) { struct iomuxc_gpr_base_regs *gpr = (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; +#ifndef CONFIG_IMX8MP /* Use 125M anatop REF_CLK1 for ENET1, not from external */ clrsetbits_le32(&gpr->gpr[1], 0x2000, 0); +#else + /* Enable RGMII TX clk output */ + setbits_le32(&gpr->gpr[1], BIT(22)); +#endif return 0; } +static int setup_eqos(void) +{ + struct iomuxc_gpr_base_regs *gpr = + (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; + + /* set INTF as RGMII, enable RGMII TXC clock */ + clrsetbits_le32(&gpr->gpr[1], + IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK, BIT(16)); + setbits_le32(&gpr->gpr[1], BIT(19) | BIT(21)); + + return set_clk_eqos(ENET_125MHZ); +} + int board_phy_config(struct phy_device *phydev) { unsigned short val; @@ -96,16 +106,16 @@ int board_phy_config(struct phy_device *phydev) return 0; } -#endif // IS_ENABLED(CONFIG_FEC_MXC) +#endif // IS_ENABLED(CONFIG_NET) int board_init(void) { - gsc_init(1); + eeprom_init(1); if (IS_ENABLED(CONFIG_FEC_MXC)) setup_fec(); - - gsc_hwmon(); + if (IS_ENABLED(CONFIG_DWC_ETH_QOS)) + setup_eqos(); return 0; } @@ -122,13 +132,13 @@ int board_late_init(void) /* Set board serial/model */ if (!env_get("serial#")) - env_set_ulong("serial#", gsc_get_serial()); - env_set("model", gsc_get_model()); + env_set_ulong("serial#", eeprom_get_serial()); + env_set("model", eeprom_get_model()); /* Set fdt_file vars */ i = 0; do { - str = gsc_get_dtb_name(i, fdt, sizeof(fdt)); + str = eeprom_get_dtb_name(i, fdt, sizeof(fdt)); if (str) { sprintf(env, "fdt_file%d", i + 1); strcat(fdt, ".dtb"); @@ -146,7 +156,7 @@ int board_late_init(void) sprintf(env, "ethaddr"); str = env_get(env); if (!str) { - ret = gsc_getmac(i, enetaddr); + ret = eeprom_getmac(i, enetaddr); if (!ret) eth_env_set_enetaddr(env, enetaddr); } @@ -166,7 +176,7 @@ int ft_board_setup(void *blob, struct bd_info *bd) int off; /* set board model dt prop */ - fdt_setprop_string(blob, 0, "board", gsc_get_model()); + fdt_setprop_string(blob, 0, "board", eeprom_get_model()); /* update temp thresholds */ off = fdt_path_offset(blob, "/thermal-zones/cpu-thermal/trips"); diff --git a/board/toradex/apalis-imx8x/Kconfig b/board/toradex/apalis-imx8x/Kconfig deleted file mode 100644 index d6cda7e..0000000 --- a/board/toradex/apalis-imx8x/Kconfig +++ /dev/null @@ -1,33 +0,0 @@ -if TARGET_APALIS_IMX8X - -config SYS_BOARD - default "apalis-imx8x" - -config SYS_VENDOR - default "toradex" - -config SYS_CONFIG_NAME - default "apalis-imx8x" - -config TDX_CFG_BLOCK - default y - -config TDX_HAVE_MMC - default y - -config TDX_CFG_BLOCK_DEV - default "0" - -config TDX_CFG_BLOCK_PART - default "1" - -# Toradex config block in eMMC, at the end of 1st "boot sector" -config TDX_CFG_BLOCK_OFFSET - default "-512" - -config IMX_CONFIG - default "board/toradex/apalis-imx8x/apalis-imx8x-imximage.cfg" - -source "board/toradex/common/Kconfig" - -endif diff --git a/board/toradex/apalis-imx8x/MAINTAINERS b/board/toradex/apalis-imx8x/MAINTAINERS deleted file mode 100644 index 93d6cdd..0000000 --- a/board/toradex/apalis-imx8x/MAINTAINERS +++ /dev/null @@ -1,10 +0,0 @@ -Apalis iMX8X -M: Marcel Ziswiler <marcel.ziswiler@toradex.com> -W: http://developer.toradex.com/software/linux/linux-software -S: Maintained -F: arch/arm/dts/fsl-imx8x-apalis.dts -F: arch/arm/dts/fsl-imx8x-apalis-u-boot.dtsi -F: board/toradex/apalis-imx8x/ -F: configs/apalis-imx8x_defconfig -F: doc/board/toradex/apalis-imx8x.rst -F: include/configs/apalis-imx8x.h diff --git a/board/toradex/apalis-imx8x/Makefile b/board/toradex/apalis-imx8x/Makefile deleted file mode 100644 index 9d6e85b..0000000 --- a/board/toradex/apalis-imx8x/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright 2020 Toradex -# - -obj-y += apalis-imx8x.o diff --git a/board/toradex/apalis-imx8x/apalis-imx8x-imximage.cfg b/board/toradex/apalis-imx8x/apalis-imx8x-imximage.cfg deleted file mode 100644 index c229706..0000000 --- a/board/toradex/apalis-imx8x/apalis-imx8x-imximage.cfg +++ /dev/null @@ -1,23 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2020 Toradex - * - * Refer doc/imx/mkimage/imx8image.txt for more details about how-to configure - * and create imx8image boot image - */ - - -/* Boot from SD, sector size 0x400 */ -BOOT_FROM EMMC_FASTBOOT 0x400 -/* SoC type IMX8QX */ -SOC_TYPE IMX8QX -/* Append seco container image */ -APPEND mx8qx-ahab-container.img -/* Create the 2nd container */ -CONTAINER -/* Add scfw image with exec attribute */ -IMAGE SCU mx8qx-apalis-scfw-tcm.bin -/* Add ATF image with exec attribute */ -IMAGE A35 bl31.bin 0x80000000 -/* Add U-Boot image with load attribute */ -DATA A35 u-boot-dtb.bin 0x80020000 diff --git a/board/toradex/apalis-imx8x/apalis-imx8x.c b/board/toradex/apalis-imx8x/apalis-imx8x.c deleted file mode 100644 index ac3bac6..0000000 --- a/board/toradex/apalis-imx8x/apalis-imx8x.c +++ /dev/null @@ -1,155 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2020 Toradex - */ - -#include <common.h> -#include <cpu_func.h> -#include <init.h> - -#include <asm/arch/clock.h> -#include <asm/arch/imx8-pins.h> -#include <asm/arch/iomux.h> -#include <asm/arch/sci/sci.h> -#include <asm/arch/sys_proto.h> -#include <asm/global_data.h> -#include <asm/gpio.h> -#include <asm/io.h> -#include <env.h> -#include <errno.h> -#include <linux/libfdt.h> - -#include "../common/tdx-cfg-block.h" - -DECLARE_GLOBAL_DATA_PTR; - -#define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \ - (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ - (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ - (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) - -static iomux_cfg_t uart1_pads[] = { - SC_P_UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL), - SC_P_UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - -static void setup_iomux_uart(void) -{ - imx8_iomux_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); -} - -void board_mem_get_layout(u64 *phys_sdram_1_start, - u64 *phys_sdram_1_size, - u64 *phys_sdram_2_start, - u64 *phys_sdram_2_size) -{ - u32 is_dualx = 0, val = 0; - sc_err_t scierr = sc_misc_otp_fuse_read(-1, 6, &val); - - if (scierr == SC_ERR_NONE) { - /* DX has two A35 cores disabled */ - is_dualx = (val & 0xf) != 0x0; - } - - *phys_sdram_1_start = PHYS_SDRAM_1; - if (is_dualx) - /* Our DX based SKUs only have 1 GB RAM */ - *phys_sdram_1_size = SZ_1G; - else - *phys_sdram_1_size = PHYS_SDRAM_1_SIZE; - *phys_sdram_2_start = PHYS_SDRAM_2; - *phys_sdram_2_size = PHYS_SDRAM_2_SIZE; -} - -int board_early_init_f(void) -{ - sc_pm_clock_rate_t rate; - sc_err_t err = 0; - - /* - * This works around that having only UART3 up the baudrate is 1.2M - * instead of 115.2k. Set UART0 clock root to 80 MHz - */ - rate = 80000000; - err = sc_pm_set_clock_rate(-1, SC_R_UART_0, SC_PM_CLK_PER, &rate); - if (err != SC_ERR_NONE) - return 0; - - /* Set UART3 clock root to 80 MHz and enable it */ - rate = SC_80MHZ; - err = sc_pm_setup_uart(SC_R_UART_1, rate); - if (err != SC_ERR_NONE) - return 0; - - setup_iomux_uart(); - - return 0; -} - -#if IS_ENABLED(CONFIG_DM_GPIO) -static void board_gpio_init(void) -{ - /* TODO */ -} -#else -static inline void board_gpio_init(void) {} -#endif - -#if IS_ENABLED(CONFIG_FEC_MXC) -#include <miiphy.h> - -int board_phy_config(struct phy_device *phydev) -{ - if (phydev->drv->config) - phydev->drv->config(phydev); - - return 0; -} -#endif - -int checkboard(void) -{ - puts("Model: Toradex Apalis iMX8X\n"); - - build_info(); - print_bootinfo(); - - return 0; -} - -int board_init(void) -{ - board_gpio_init(); - - return 0; -} - -/* - * Board specific reset that is system reset. - */ -void reset_cpu(void) -{ - /* TODO */ -} - -#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) -int ft_board_setup(void *blob, struct bd_info *bd) -{ - return ft_common_board_setup(blob, bd); -} -#endif - -int board_mmc_get_env_dev(int devno) -{ - return devno; -} - -int board_late_init(void) -{ -#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG -/* TODO move to common */ - env_set("board_name", "Apalis iMX8X"); -#endif - - return 0; -} diff --git a/board/toradex/apalis_imx6/apalis_imx6.c b/board/toradex/apalis_imx6/apalis_imx6.c index a78d52d..5604c46 100644 --- a/board/toradex/apalis_imx6/apalis_imx6.c +++ b/board/toradex/apalis_imx6/apalis_imx6.c @@ -304,13 +304,6 @@ static void setup_dtemode_uart(void) clrbits_le32((u32 *)(UART4_BASE + UCR3), UCR3_DCD | UCR3_RI); clrbits_le32((u32 *)(UART5_BASE + UCR3), UCR3_DCD | UCR3_RI); } -static void setup_dcemode_uart(void) -{ - clrbits_le32((u32 *)(UART1_BASE + UFCR), UFCR_DCEDTE); - clrbits_le32((u32 *)(UART2_BASE + UFCR), UFCR_DCEDTE); - clrbits_le32((u32 *)(UART4_BASE + UFCR), UFCR_DCEDTE); - clrbits_le32((u32 *)(UART5_BASE + UFCR), UFCR_DCEDTE); -} static void setup_iomux_dte_uart(void) { @@ -318,12 +311,6 @@ static void setup_iomux_dte_uart(void) imx_iomux_v3_setup_multiple_pads(uart1_pads_dte, ARRAY_SIZE(uart1_pads_dte)); } -static void setup_iomux_dce_uart(void) -{ - setup_dcemode_uart(); - imx_iomux_v3_setup_multiple_pads(uart1_pads_dce, - ARRAY_SIZE(uart1_pads_dce)); -} #ifdef CONFIG_USB_EHCI_MX6 int board_ehci_hcd_init(int port) @@ -665,11 +652,8 @@ int board_early_init_f(void) { imx_iomux_v3_setup_multiple_pads(pwr_intb_pads, ARRAY_SIZE(pwr_intb_pads)); -#ifndef CONFIG_TDX_APALIS_IMX6_V1_0 setup_iomux_dte_uart(); -#else - setup_iomux_dce_uart(); -#endif + return 0; } @@ -714,23 +698,7 @@ int board_late_init(void) rev = get_board_revision(); snprintf(env_str, ARRAY_SIZE(env_str), "%.4x", rev); env_set("board_rev", env_str); - -#ifndef CONFIG_TDX_APALIS_IMX6_V1_0 - if ((rev & 0xfff0) == 0x0100) { - char *fdt_env; - - /* reconfigure the UART to DCE mode dynamically if on V1.0 HW */ - setup_iomux_dce_uart(); - - /* if using the default device tree, use version for V1.0 HW */ - fdt_env = env_get("fdt_file"); - if ((fdt_env != NULL) && (strcmp(FDT_FILE, fdt_env) == 0)) { - env_set("fdt_file", FDT_FILE_V1_0); - printf("patching fdt_file to " FDT_FILE_V1_0 "\n"); - } - } -#endif /* CONFIG_TDX_APALIS_IMX6_V1_0 */ -#endif /* CONFIG_REVISION_TAG */ +#endif /* CONFIG_BOARD_LATE_INIT */ #ifdef CONFIG_CMD_USB_SDP if (is_boot_from_usb()) { @@ -1129,10 +1097,8 @@ void board_init_f(ulong dummy) /* UART clocks enabled and gd valid - init serial console */ preloader_console_init(); -#ifndef CONFIG_TDX_APALIS_IMX6_V1_0 /* Make sure we use dte mode */ setup_dtemode_uart(); -#endif /* DDR initialization */ spl_dram_init(); diff --git a/board/toradex/colibri_imx7/colibri_imx7.c b/board/toradex/colibri_imx7/colibri_imx7.c index 6822102..486299b 100644 --- a/board/toradex/colibri_imx7/colibri_imx7.c +++ b/board/toradex/colibri_imx7/colibri_imx7.c @@ -319,40 +319,16 @@ int ft_board_setup(void *blob, struct bd_info *bd) #endif #ifdef CONFIG_USB_EHCI_MX7 -static iomux_v3_cfg_t const usb_otg2_pads[] = { - MX7D_PAD_UART3_CTS_B__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - -int board_ehci_hcd_init(int port) +int board_fix_fdt(void *rw_fdt_blob) { - switch (port) { - case 0: - break; - case 1: - if (is_cpu_type(MXC_CPU_MX7S)) - return -ENODEV; - - imx_iomux_v3_setup_multiple_pads(usb_otg2_pads, - ARRAY_SIZE(usb_otg2_pads)); - break; - default: - return -EINVAL; - } - return 0; -} + /* i.MX 7Solo has only one single USB OTG1 but no USB host port */ + if (is_cpu_type(MXC_CPU_MX7S)) { + int offset = fdt_path_offset(rw_fdt_blob, "/soc/bus@30800000/usb@30b20000"); -int board_usb_phy_mode(int port) -{ - switch (port) { - case 0: - if (gpio_get_value(USB_CDET_GPIO)) - return USB_INIT_DEVICE; - else - return USB_INIT_HOST; - case 1: - default: - return USB_INIT_HOST; + return fdt_status_disabled(rw_fdt_blob, offset); } + + return 0; } #if defined(CONFIG_BOARD_LATE_INIT) @@ -373,4 +349,4 @@ int board_late_init(void) } #endif /* CONFIG_BOARD_LATE_INIT */ -#endif +#endif /* CONFIG_USB_EHCI_MX7 */ diff --git a/board/toradex/colibri_pxa270/Kconfig b/board/toradex/colibri_pxa270/Kconfig deleted file mode 100644 index f646baa..0000000 --- a/board/toradex/colibri_pxa270/Kconfig +++ /dev/null @@ -1,23 +0,0 @@ -if TARGET_COLIBRI_PXA270 - -config SYS_BOARD - default "colibri_pxa270" - -config SYS_VENDOR - default "toradex" - -config SYS_CONFIG_NAME - default "colibri_pxa270" - -config TDX_CFG_BLOCK - default y - -config TDX_HAVE_NOR - default y - -config TDX_CFG_BLOCK_OFFSET - default "262144" - -source "board/toradex/common/Kconfig" - -endif diff --git a/board/toradex/colibri_pxa270/MAINTAINERS b/board/toradex/colibri_pxa270/MAINTAINERS deleted file mode 100644 index b378d7b..0000000 --- a/board/toradex/colibri_pxa270/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -COLIBRI_PXA270 BOARD -M: Marek Vasut <marek.vasut@gmail.com> -S: Maintained -F: board/toradex/colibri_pxa270/ -F: include/configs/colibri_pxa270.h -F: configs/colibri_pxa270_defconfig diff --git a/board/toradex/colibri_pxa270/Makefile b/board/toradex/colibri_pxa270/Makefile deleted file mode 100644 index ea610cf..0000000 --- a/board/toradex/colibri_pxa270/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Toradex Colibri PXA270 Support -# -# Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com> - -obj-y := colibri_pxa270.o diff --git a/board/toradex/colibri_pxa270/colibri_pxa270.c b/board/toradex/colibri_pxa270/colibri_pxa270.c deleted file mode 100644 index 25fbf41..0000000 --- a/board/toradex/colibri_pxa270/colibri_pxa270.c +++ /dev/null @@ -1,153 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Toradex Colibri PXA270 Support - * - * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com> - * Copyright (C) 2016-2019 Marcel Ziswiler <marcel.ziswiler@toradex.com> - */ - -#include <common.h> -#include <cpu_func.h> -#include <dm.h> -#include <init.h> -#include <net.h> -#include <asm/arch/hardware.h> -#include <asm/arch/pxa.h> -#include <asm/arch/regs-mmc.h> -#include <asm/arch/regs-uart.h> -#include <asm/global_data.h> -#include <asm/io.h> -#include <dm/platdata.h> -#include <dm/platform_data/pxa_mmc_gen.h> -#include <dm/platform_data/serial_pxa.h> -#include <netdev.h> -#include <serial.h> -#include <usb.h> -#include <asm/mach-types.h> -#include <linux/delay.h> -#include "../common/tdx-common.h" - -DECLARE_GLOBAL_DATA_PTR; - -int board_init(void) -{ - /* We have RAM, disable cache */ - dcache_disable(); - icache_disable(); - - /* arch number of Toradex Colibri PXA270 */ - gd->bd->bi_arch_number = MACH_TYPE_COLIBRI; - - /* address of boot parameters */ - gd->bd->bi_boot_params = 0xa0000100; - - return 0; -} - -int checkboard(void) -{ - puts("Model: Toradex Colibri PXA270\n"); - - return 0; -} - -#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) -int ft_board_setup(void *blob, struct bd_info *bd) -{ - return ft_common_board_setup(blob, bd); -} -#endif - -int dram_init(void) -{ - pxa2xx_dram_init(); - gd->ram_size = PHYS_SDRAM_1_SIZE; - return 0; -} - -#ifdef CONFIG_CMD_USB -int board_usb_init(int index, enum usb_init_type init) -{ - writel((readl(UHCHR) | UHCHR_PCPL | UHCHR_PSPL) & - ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE), - UHCHR); - - writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR); - - while (UHCHR & UHCHR_FSBIR) - ; - - writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR); - writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE); - - /* Clear any OTG Pin Hold */ - if (readl(PSSR) & PSSR_OTGPH) - writel(readl(PSSR) | PSSR_OTGPH, PSSR); - - writel(readl(UHCRHDA) & ~(0x200), UHCRHDA); - writel(readl(UHCRHDA) | 0x100, UHCRHDA); - - /* Set port power control mask bits, only 3 ports. */ - writel(readl(UHCRHDB) | (0x7 << 17), UHCRHDB); - - /* enable port 2 */ - writel(readl(UP2OCR) | UP2OCR_HXOE | UP2OCR_HXS | - UP2OCR_DMPDE | UP2OCR_DPPDE, UP2OCR); - - return 0; -} - -int board_usb_cleanup(int index, enum usb_init_type init) -{ - return 0; -} - -void usb_board_stop(void) -{ - writel(readl(UHCHR) | UHCHR_FHR, UHCHR); - udelay(11); - writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR); - - writel(readl(UHCCOMS) | 1, UHCCOMS); - udelay(10); - - writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN); -} -#endif - -#ifdef CONFIG_DRIVER_DM9000 -int board_eth_init(struct bd_info *bis) -{ - return dm9000_initialize(bis); -} -#endif - -#ifdef CONFIG_CMD_MMC -#if !CONFIG_IS_ENABLED(DM_MMC) -int board_mmc_init(struct bd_info *bis) -{ - pxa_mmc_register(0); - return 0; -} -#else /* !CONFIG_IS_ENABLED(DM_MMC) */ -static const struct pxa_mmc_plat mmc_plat = { - .base = (struct pxa_mmc_regs *)MMC0_BASE, -}; - -U_BOOT_DRVINFO(pxa_mmcs) = { - .name = "pxa_mmc", - .plat = &mmc_plat, -}; -#endif /* !CONFIG_IS_ENABLED(DM_MMC) */ -#endif - -static const struct pxa_serial_plat serial_plat = { - .base = (struct pxa_uart_regs *)FFUART_BASE, - .port = FFUART_INDEX, - .baudrate = CONFIG_BAUDRATE, -}; - -U_BOOT_DRVINFO(pxa_serials) = { - .name = "serial_pxa", - .plat = &serial_plat, -}; diff --git a/board/toradex/common/tdx-cfg-block.c b/board/toradex/common/tdx-cfg-block.c index 7cadd05..9c87289 100644 --- a/board/toradex/common/tdx-cfg-block.c +++ b/board/toradex/common/tdx-cfg-block.c @@ -13,7 +13,6 @@ #if defined(CONFIG_TARGET_APALIS_IMX6) || \ defined(CONFIG_TARGET_APALIS_IMX8) || \ - defined(CONFIG_TARGET_APALIS_IMX8X) || \ defined(CONFIG_TARGET_COLIBRI_IMX6) || \ defined(CONFIG_TARGET_COLIBRI_IMX8X) || \ defined(CONFIG_TARGET_VERDIN_IMX8MM) || \ @@ -23,11 +22,6 @@ #else #define is_cpu_type(cpu) (0) #endif -#if defined(CONFIG_CPU_PXA27X) -#include <asm/arch-pxa/pxa.h> -#else -#define cpu_is_pxa27x(cpu) (0) -#endif #include <cli.h> #include <console.h> #include <env.h> @@ -370,16 +364,12 @@ static int get_cfgblock_interactive(void) /* Unknown module by default */ tdx_hw_tag.prodid = 0; - if (cpu_is_pxa27x()) - sprintf(message, "Is the module the 312 MHz version? [y/N] "); - else - sprintf(message, "Is the module an IT version? [y/N] "); + sprintf(message, "Is the module an IT version? [y/N] "); len = cli_readline(message); it = console_buffer[0]; #if defined(CONFIG_TARGET_APALIS_IMX8) || \ - defined(CONFIG_TARGET_APALIS_IMX8X) || \ defined(CONFIG_TARGET_COLIBRI_IMX6ULL) || \ defined(CONFIG_TARGET_COLIBRI_IMX8X) || \ defined(CONFIG_TARGET_VERDIN_IMX8MM) || \ @@ -451,16 +441,7 @@ static int get_cfgblock_interactive(void) tdx_hw_tag.prodid = APALIS_IMX8QP; } } else if (is_cpu_type(MXC_CPU_IMX8QXP)) { -#ifdef CONFIG_TARGET_APALIS_IMX8X - if (it == 'y' || it == 'Y' || wb == 'y' || wb == 'Y') { - tdx_hw_tag.prodid = APALIS_IMX8QXP_WIFI_BT_IT; - } else { - if (gd->ram_size == 0x40000000) - tdx_hw_tag.prodid = APALIS_IMX8DXP; - else - tdx_hw_tag.prodid = APALIS_IMX8QXP; - } -#elif CONFIG_TARGET_COLIBRI_IMX8X +#ifdef CONFIG_TARGET_COLIBRI_IMX8X if (it == 'y' || it == 'Y') { if (wb == 'y' || wb == 'Y') tdx_hw_tag.prodid = COLIBRI_IMX8QXP_WIFI_BT_IT; @@ -511,11 +492,6 @@ static int get_cfgblock_interactive(void) tdx_hw_tag.prodid = COLIBRI_T20_256MB; else tdx_hw_tag.prodid = COLIBRI_T20_512MB; - } else if (cpu_is_pxa27x()) { - if (it == 'y' || it == 'Y') - tdx_hw_tag.prodid = COLIBRI_PXA270_312MHZ; - else - tdx_hw_tag.prodid = COLIBRI_PXA270_520MHZ; } #if defined(CONFIG_TARGET_APALIS_T30) || defined(CONFIG_TARGET_COLIBRI_T30) else if (!strcmp("tegra30", soc)) { @@ -563,10 +539,6 @@ static int get_cfgblock_interactive(void) tdx_hw_tag.ver_minor = console_buffer[2] - '0'; tdx_hw_tag.ver_assembly = console_buffer[3] - 'A'; - if (cpu_is_pxa27x() && tdx_hw_tag.ver_major == 1) - tdx_hw_tag.prodid -= (COLIBRI_PXA270_312MHZ - - COLIBRI_PXA270_V1_312MHZ); - while (len < 8) { sprintf(message, "Enter module serial number: "); len = cli_readline(message); diff --git a/configs/am335x_guardian_defconfig b/configs/am335x_guardian_defconfig index 60e428d..3464ba8 100644 --- a/configs/am335x_guardian_defconfig +++ b/configs/am335x_guardian_defconfig @@ -30,7 +30,6 @@ CONFIG_AUTOBOOT_STOP_STR=" " CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_ARCH_MISC_INIT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -CONFIG_SPL_SEPARATE_BSS=y # CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_ETH=y diff --git a/configs/am3517_evm_defconfig b/configs/am3517_evm_defconfig index 52c2a67..904fc53 100644 --- a/configs/am3517_evm_defconfig +++ b/configs/am3517_evm_defconfig @@ -17,7 +17,6 @@ CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTDELAY=10 CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then echo SD/MMC found on device $mmcdev; if run loadbootenv; then run importbootenv; fi; echo Checking if uenvcmd is set ...; if test -n $uenvcmd; then echo Running uenvcmd ...; run uenvcmd; fi; echo Running default loadimage ...; setenv bootfile zImage; if run loadimage; then run loadfdt; run mmcboot; fi; else run nandboot; fi" CONFIG_SPL_SYS_MALLOC_SIMPLE=y -CONFIG_SPL_SEPARATE_BSS=y # CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set # CONFIG_SPL_FS_EXT4 is not set # CONFIG_SPL_I2C is not set diff --git a/configs/am57xx_evm_defconfig b/configs/am57xx_evm_defconfig index 807828d..4223f00 100644 --- a/configs/am57xx_evm_defconfig +++ b/configs/am57xx_evm_defconfig @@ -27,7 +27,6 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_AVB_VERIFY=y CONFIG_ANDROID_AB=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y -CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_DMA=y # CONFIG_SPL_NAND_SUPPORT is not set CONFIG_SPL_DM_SPI_FLASH=y diff --git a/configs/am57xx_hs_evm_defconfig b/configs/am57xx_hs_evm_defconfig index e398fe7..be48a8d 100644 --- a/configs/am57xx_hs_evm_defconfig +++ b/configs/am57xx_hs_evm_defconfig @@ -32,7 +32,6 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_AVB_VERIFY=y CONFIG_ANDROID_AB=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y -CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_DMA=y # CONFIG_SPL_NAND_SUPPORT is not set CONFIG_SPL_DM_SPI_FLASH=y diff --git a/configs/am57xx_hs_evm_usb_defconfig b/configs/am57xx_hs_evm_usb_defconfig index 6514a4f..194103a 100644 --- a/configs/am57xx_hs_evm_usb_defconfig +++ b/configs/am57xx_hs_evm_usb_defconfig @@ -35,7 +35,6 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_AVB_VERIFY=y CONFIG_ANDROID_AB=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y -CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_DMA=y # CONFIG_SPL_NAND_SUPPORT is not set CONFIG_SPL_DM_SPI_FLASH=y diff --git a/configs/am64x_evm_a53_defconfig b/configs/am64x_evm_a53_defconfig index bceb35f..4149921 100644 --- a/configs/am64x_evm_a53_defconfig +++ b/configs/am64x_evm_a53_defconfig @@ -33,7 +33,6 @@ CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_STACK_R=y -CONFIG_SPL_SEPARATE_BSS=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400 CONFIG_SPL_DMA=y diff --git a/configs/am65x_evm_a53_defconfig b/configs/am65x_evm_a53_defconfig index 2e5d87c..9f41b39 100644 --- a/configs/am65x_evm_a53_defconfig +++ b/configs/am65x_evm_a53_defconfig @@ -35,7 +35,6 @@ CONFIG_LOGLEVEL=7 CONFIG_CONSOLE_MUX=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_STACK_R=y -CONFIG_SPL_SEPARATE_BSS=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400 CONFIG_SPL_DMA=y diff --git a/configs/am65x_hs_evm_a53_defconfig b/configs/am65x_hs_evm_a53_defconfig index 72d41cb..5a12401 100644 --- a/configs/am65x_hs_evm_a53_defconfig +++ b/configs/am65x_hs_evm_a53_defconfig @@ -37,7 +37,6 @@ CONFIG_LOGLEVEL=7 CONFIG_CONSOLE_MUX=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_STACK_R=y -CONFIG_SPL_SEPARATE_BSS=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400 CONFIG_SPL_DMA=y diff --git a/configs/apalis-imx8_defconfig b/configs/apalis-imx8_defconfig index 19edbbb..beb20f6 100644 --- a/configs/apalis-imx8_defconfig +++ b/configs/apalis-imx8_defconfig @@ -15,6 +15,7 @@ CONFIG_SYS_MEMTEST_END=0x89000000 CONFIG_DISTRO_DEFAULTS=y CONFIG_REMAKE_ELF=y CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y CONFIG_OF_SYSTEM_SETUP=y CONFIG_LOG=y # CONFIG_DISPLAY_BOARDINFO is not set diff --git a/configs/apalis-imx8x_defconfig b/configs/apalis-imx8x_defconfig deleted file mode 100644 index b67cdec..0000000 --- a/configs/apalis-imx8x_defconfig +++ /dev/null @@ -1,82 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_IMX8=y -CONFIG_SYS_TEXT_BASE=0x80020000 -CONFIG_SYS_MALLOC_LEN=0x2800000 -CONFIG_SYS_MALLOC_F_LEN=0x4000 -CONFIG_NR_DRAM_BANKS=3 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0xFFFFDE00 -CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-apalis" -CONFIG_TARGET_APALIS_IMX8X=y -CONFIG_SYS_LOAD_ADDR=0x89000000 -CONFIG_SYS_MEMTEST_START=0x88000000 -CONFIG_SYS_MEMTEST_END=0x89000000 -CONFIG_DISTRO_DEFAULTS=y -CONFIG_REMAKE_ELF=y -CONFIG_FIT=y -CONFIG_OF_SYSTEM_SETUP=y -CONFIG_BOOTDELAY=1 -CONFIG_LOG=y -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_SYS_PROMPT="Apalis iMX8X # " -CONFIG_CMD_CPU=y -# CONFIG_BOOTM_NETBSD is not set -CONFIG_CMD_ASKENV=y -CONFIG_CMD_MEMTEST=y -CONFIG_CMD_CLK=y -CONFIG_CMD_DM=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_PCI=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_UUID=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=1 -CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y -CONFIG_USE_ETHPRIME=y -CONFIG_ETHPRIME="eth0" -CONFIG_VERSION_VARIABLE=y -CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_IP_DEFRAG=y -CONFIG_TFTP_BLOCKSIZE=4096 -CONFIG_TFTP_TSIZE=y -CONFIG_BOOTCOUNT_LIMIT=y -CONFIG_BOOTCOUNT_ENV=y -CONFIG_CLK_IMX8=y -CONFIG_CPU=y -CONFIG_MXC_GPIO=y -CONFIG_DM_I2C=y -CONFIG_SYS_I2C_IMX_LPI2C=y -CONFIG_I2C_MUX=y -CONFIG_I2C_MUX_PCA954x=y -CONFIG_MISC=y -CONFIG_SUPPORT_EMMC_BOOT=y -CONFIG_FSL_USDHC=y -CONFIG_PHYLIB=y -CONFIG_PHY_ADDR_ENABLE=y -CONFIG_PHY_MICREL=y -CONFIG_PHY_MICREL_KSZ90X1=y -CONFIG_DM_ETH=y -CONFIG_FEC_MXC_SHARE_MDIO=y -CONFIG_FEC_MXC_MDIO_BASE=0x5B040000 -CONFIG_FEC_MXC=y -CONFIG_MII=y -CONFIG_PCI=y -CONFIG_PINCTRL=y -CONFIG_PINCTRL_IMX8=y -CONFIG_POWER_DOMAIN=y -CONFIG_IMX8_POWER_DOMAIN=y -CONFIG_DM_REGULATOR=y -CONFIG_DM_REGULATOR_FIXED=y -CONFIG_DM_REGULATOR_GPIO=y -CONFIG_DM_SERIAL=y -CONFIG_FSL_LPUART=y -CONFIG_DM_THERMAL=y -CONFIG_IMX_SCU_THERMAL=y -# CONFIG_EFI_LOADER is not set diff --git a/configs/apalis-tk1_defconfig b/configs/apalis-tk1_defconfig index 9645c2f..e098b11 100644 --- a/configs/apalis-tk1_defconfig +++ b/configs/apalis-tk1_defconfig @@ -12,6 +12,7 @@ CONFIG_TEGRA124=y CONFIG_TARGET_APALIS_TK1=y CONFIG_SYS_LOAD_ADDR=0x81000000 CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y CONFIG_OF_SYSTEM_SETUP=y CONFIG_BOOTDELAY=1 CONFIG_BOOTCOMMAND="setenv fdtfile ${soc}-${fdt_module}-${fdt_board}.dtb && run distro_bootcmd" diff --git a/configs/apalis_imx6_defconfig b/configs/apalis_imx6_defconfig index 3fa1bb5..ea4ad27 100644 --- a/configs/apalis_imx6_defconfig +++ b/configs/apalis_imx6_defconfig @@ -26,8 +26,11 @@ CONFIG_SYS_MEMTEST_START=0x10000000 CONFIG_SYS_MEMTEST_END=0x10010000 CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y CONFIG_BOOTDELAY=1 CONFIG_BOOTCOMMAND="run distro_bootcmd; usb start; setenv stdout serial,vidconsole; setenv stdin serial,usbkbd" +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="test -n ${fdtfile} || setenv fdtfile imx6q-apalis-${fdt_board}.dtb" CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y @@ -56,7 +59,6 @@ CONFIG_CMD_USB=y CONFIG_CMD_USB_SDP=y CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_NFS is not set -CONFIG_CMD_BMP=y CONFIG_CMD_BOOTCOUNT=y CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y @@ -106,13 +108,4 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x1b67 CONFIG_USB_GADGET_PRODUCT_NUM=0x4000 CONFIG_CI_UDC=y CONFIG_USB_GADGET_DOWNLOAD=y -CONFIG_DM_VIDEO=y -CONFIG_VIDEO_LOGO=y -# CONFIG_VIDEO_BPP8 is not set -# CONFIG_VIDEO_BPP32 is not set -CONFIG_SYS_WHITE_ON_BLACK=y -CONFIG_VIDEO_IPUV3=y -CONFIG_SPLASH_SCREEN=y -CONFIG_SPLASH_SCREEN_ALIGN=y -CONFIG_BMP_16BPP=y CONFIG_OF_LIBFDT_OVERLAY=y diff --git a/configs/brppt1_mmc_defconfig b/configs/brppt1_mmc_defconfig index dac5f25..f1e7f81 100644 --- a/configs/brppt1_mmc_defconfig +++ b/configs/brppt1_mmc_defconfig @@ -32,7 +32,6 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_ARCH_MISC_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y -CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_I2C=y # CONFIG_SPL_NAND_SUPPORT is not set CONFIG_SPL_POWER=y diff --git a/configs/brppt1_nand_defconfig b/configs/brppt1_nand_defconfig index 451b6ef..d75090a 100644 --- a/configs/brppt1_nand_defconfig +++ b/configs/brppt1_nand_defconfig @@ -29,7 +29,6 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_ARCH_MISC_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y -CONFIG_SPL_SEPARATE_BSS=y # CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set CONFIG_SPL_I2C=y CONFIG_SPL_NAND_DRIVERS=y diff --git a/configs/brppt1_spi_defconfig b/configs/brppt1_spi_defconfig index 972f166..3378048 100644 --- a/configs/brppt1_spi_defconfig +++ b/configs/brppt1_spi_defconfig @@ -36,7 +36,6 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_ARCH_MISC_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y -CONFIG_SPL_SEPARATE_BSS=y # CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set CONFIG_SPL_I2C=y # CONFIG_SPL_NAND_SUPPORT is not set diff --git a/configs/brsmarc1_defconfig b/configs/brsmarc1_defconfig index 2c73c12..1eef3bd 100644 --- a/configs/brsmarc1_defconfig +++ b/configs/brsmarc1_defconfig @@ -35,7 +35,6 @@ CONFIG_BOARD_TYPES=y CONFIG_ARCH_MISC_INIT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_SYS_MALLOC_SIMPLE=y -CONFIG_SPL_SEPARATE_BSS=y # CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set CONFIG_SPL_I2C=y # CONFIG_SPL_NAND_SUPPORT is not set diff --git a/configs/brxre1_defconfig b/configs/brxre1_defconfig index 07acc20..c1acbe0 100644 --- a/configs/brxre1_defconfig +++ b/configs/brxre1_defconfig @@ -31,7 +31,6 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_ARCH_MISC_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y -CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_I2C=y # CONFIG_SPL_NAND_SUPPORT is not set CONFIG_SPL_POWER=y diff --git a/configs/cgtqmx8_defconfig b/configs/cgtqmx8_defconfig index 094cb41..2cf882f 100644 --- a/configs/cgtqmx8_defconfig +++ b/configs/cgtqmx8_defconfig @@ -29,7 +29,6 @@ CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript CONFIG_LOG=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_BOARD_INIT=y -CONFIG_SPL_SEPARATE_BSS=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x800 CONFIG_SYS_MMCSD_FS_BOOT_PARTITION=0 diff --git a/configs/colibri-imx6ull-emmc_defconfig b/configs/colibri-imx6ull-emmc_defconfig index 8811d77..eb4b6a7 100644 --- a/configs/colibri-imx6ull-emmc_defconfig +++ b/configs/colibri-imx6ull-emmc_defconfig @@ -13,10 +13,10 @@ CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x88000000 CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y CONFIG_BOOTDELAY=1 CONFIG_USE_PREBOOT=y -CONFIG_PREBOOT="setenv fdtfile imx6ull-colibri${variant}-${fdt_board}.dtb" -# CONFIG_CONSOLE_MUX is not set +CONFIG_PREBOOT="test -n ${fdtfile} || setenv fdtfile imx6ull-colibri${variant}-${fdt_board}.dtb" CONFIG_SYS_CONSOLE_IS_IN_ENV=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y @@ -37,7 +37,6 @@ CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_USB_SDP=y CONFIG_CMD_USB_MASS_STORAGE=y -CONFIG_CMD_BMP=y CONFIG_CMD_BOOTCOUNT=y CONFIG_CMD_CACHE=y CONFIG_CMD_REGULATOR=y @@ -79,10 +78,4 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x1b67 CONFIG_USB_GADGET_PRODUCT_NUM=0x4000 CONFIG_CI_UDC=y CONFIG_USB_GADGET_DOWNLOAD=y -CONFIG_DM_VIDEO=y -CONFIG_VIDEO_LOGO=y -CONFIG_SYS_WHITE_ON_BLACK=y -CONFIG_SPLASH_SCREEN=y -CONFIG_SPLASH_SCREEN_ALIGN=y -CONFIG_BMP_16BPP=y CONFIG_OF_LIBFDT_OVERLAY=y diff --git a/configs/colibri-imx6ull_defconfig b/configs/colibri-imx6ull_defconfig index b75e217..d082547 100644 --- a/configs/colibri-imx6ull_defconfig +++ b/configs/colibri-imx6ull_defconfig @@ -14,11 +14,11 @@ CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x88000000 CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y CONFIG_BOOTDELAY=1 CONFIG_BOOTCOMMAND="run ubiboot || run distro_bootcmd;" CONFIG_USE_PREBOOT=y -CONFIG_PREBOOT="setenv fdtfile imx6ull-colibri${variant}-${fdt_board}.dtb" -# CONFIG_CONSOLE_MUX is not set +CONFIG_PREBOOT="test -n ${fdtfile} || setenv fdtfile imx6ull-colibri${variant}-${fdt_board}.dtb" CONFIG_SYS_CONSOLE_IS_IN_ENV=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y @@ -42,7 +42,6 @@ CONFIG_CMD_NAND_TORTURE=y CONFIG_CMD_USB=y CONFIG_CMD_USB_SDP=y CONFIG_CMD_USB_MASS_STORAGE=y -CONFIG_CMD_BMP=y CONFIG_CMD_BOOTCOUNT=y CONFIG_CMD_CACHE=y CONFIG_CMD_REGULATOR=y @@ -95,12 +94,5 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x1b67 CONFIG_USB_GADGET_PRODUCT_NUM=0x4000 CONFIG_CI_UDC=y CONFIG_USB_GADGET_DOWNLOAD=y -CONFIG_DM_VIDEO=y -CONFIG_VIDEO_LOGO=y -CONFIG_SYS_WHITE_ON_BLACK=y -CONFIG_VIDEO_MXS=y -CONFIG_SPLASH_SCREEN=y -CONFIG_SPLASH_SCREEN_ALIGN=y -CONFIG_BMP_16BPP=y CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_FDT_FIXUP_PARTITIONS=y diff --git a/configs/colibri-imx8x_defconfig b/configs/colibri-imx8x_defconfig index 80bc27b..0c9d6b6 100644 --- a/configs/colibri-imx8x_defconfig +++ b/configs/colibri-imx8x_defconfig @@ -15,6 +15,7 @@ CONFIG_SYS_MEMTEST_END=0x89000000 CONFIG_DISTRO_DEFAULTS=y CONFIG_REMAKE_ELF=y CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y CONFIG_LOG=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y diff --git a/configs/colibri_imx6_defconfig b/configs/colibri_imx6_defconfig index 04b73a8..4f38d5c 100644 --- a/configs/colibri_imx6_defconfig +++ b/configs/colibri_imx6_defconfig @@ -25,8 +25,11 @@ CONFIG_SYS_MEMTEST_START=0x10000000 CONFIG_SYS_MEMTEST_END=0x10010000 CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y CONFIG_BOOTDELAY=1 CONFIG_BOOTCOMMAND="run distro_bootcmd; usb start; setenv stdout serial,vidconsole; setenv stdin serial,usbkbd" +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="test -n ${fdtfile} || setenv fdtfile imx6dl-colibri-${fdt_board}.dtb" CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y @@ -55,7 +58,6 @@ CONFIG_CMD_USB=y CONFIG_CMD_USB_SDP=y CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_NFS is not set -CONFIG_CMD_BMP=y CONFIG_CMD_BOOTCOUNT=y CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y @@ -104,13 +106,4 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x1b67 CONFIG_USB_GADGET_PRODUCT_NUM=0x4000 CONFIG_CI_UDC=y CONFIG_USB_GADGET_DOWNLOAD=y -CONFIG_DM_VIDEO=y -CONFIG_VIDEO_LOGO=y -# CONFIG_VIDEO_BPP8 is not set -# CONFIG_VIDEO_BPP32 is not set -CONFIG_SYS_WHITE_ON_BLACK=y -CONFIG_VIDEO_IPUV3=y -CONFIG_SPLASH_SCREEN=y -CONFIG_SPLASH_SCREEN_ALIGN=y -CONFIG_BMP_16BPP=y CONFIG_OF_LIBFDT_OVERLAY=y diff --git a/configs/colibri_imx7_defconfig b/configs/colibri_imx7_defconfig index 1ccc716..973afc1 100644 --- a/configs/colibri_imx7_defconfig +++ b/configs/colibri_imx7_defconfig @@ -10,14 +10,16 @@ CONFIG_TARGET_COLIBRI_IMX7=y CONFIG_IMX_RDC=y CONFIG_IMX_BOOTAUX=y CONFIG_IMX_HAB=y +CONFIG_OF_BOARD_FIXUP=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x8c000000 CONFIG_DISTRO_DEFAULTS=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y CONFIG_BOOTDELAY=1 CONFIG_BOOTCOMMAND="run ubiboot ; echo ; echo ubiboot failed ; run distro_bootcmd;" CONFIG_USE_PREBOOT=y -CONFIG_PREBOOT="setenv fdtfile ${soc}-colibri-${fdt_board}.dtb " -# CONFIG_CONSOLE_MUX is not set +CONFIG_PREBOOT="test -n ${fdtfile} || setenv fdtfile ${soc}-colibri-${fdt_board}.dtb " CONFIG_SYS_CONSOLE_IS_IN_ENV=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y @@ -38,9 +40,9 @@ CONFIG_CMD_MTD=y CONFIG_CMD_NAND_TRIMFFS=y CONFIG_CMD_NAND_TORTURE=y CONFIG_CMD_USB=y +CONFIG_CMD_USB_SDP=y CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_BOOTP_PXE is not set -CONFIG_CMD_BMP=y CONFIG_CMD_BOOTCOUNT=y CONFIG_CMD_CACHE=y # CONFIG_CMD_HASH is not set @@ -90,12 +92,5 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x1b67 CONFIG_USB_GADGET_PRODUCT_NUM=0x4000 CONFIG_CI_UDC=y CONFIG_USB_GADGET_DOWNLOAD=y -CONFIG_DM_VIDEO=y -CONFIG_VIDEO_LOGO=y -CONFIG_SYS_WHITE_ON_BLACK=y -CONFIG_VIDEO_MXS=y -CONFIG_SPLASH_SCREEN=y -CONFIG_SPLASH_SCREEN_ALIGN=y -CONFIG_BMP_16BPP=y CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_FDT_FIXUP_PARTITIONS=y diff --git a/configs/colibri_imx7_emmc_defconfig b/configs/colibri_imx7_emmc_defconfig index dcac585..01b1cb8 100644 --- a/configs/colibri_imx7_emmc_defconfig +++ b/configs/colibri_imx7_emmc_defconfig @@ -15,10 +15,10 @@ CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x8c000000 CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y CONFIG_BOOTDELAY=1 CONFIG_USE_PREBOOT=y -CONFIG_PREBOOT="setenv fdtfile ${soc}-colibri-emmc-${fdt_board}.dtb" -# CONFIG_CONSOLE_MUX is not set +CONFIG_PREBOOT="test -n ${fdtfile} || setenv fdtfile ${soc}-colibri-emmc-${fdt_board}.dtb" CONFIG_SYS_CONSOLE_IS_IN_ENV=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y @@ -37,8 +37,8 @@ CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y +CONFIG_CMD_USB_SDP=y CONFIG_CMD_USB_MASS_STORAGE=y -CONFIG_CMD_BMP=y CONFIG_CMD_BOOTCOUNT=y CONFIG_CMD_CACHE=y # CONFIG_CMD_HASH is not set @@ -83,10 +83,4 @@ CONFIG_USB_GADGET_MANUFACTURER="Toradex" CONFIG_USB_GADGET_VENDOR_NUM=0x1b67 CONFIG_USB_GADGET_PRODUCT_NUM=0x4000 CONFIG_CI_UDC=y -CONFIG_DM_VIDEO=y -CONFIG_VIDEO_LOGO=y -CONFIG_SYS_WHITE_ON_BLACK=y -CONFIG_SPLASH_SCREEN=y -CONFIG_SPLASH_SCREEN_ALIGN=y -CONFIG_BMP_16BPP=y CONFIG_OF_LIBFDT_OVERLAY=y diff --git a/configs/colibri_pxa270_defconfig b/configs/colibri_pxa270_defconfig deleted file mode 100644 index 7d86567..0000000 --- a/configs/colibri_pxa270_defconfig +++ /dev/null @@ -1,57 +0,0 @@ -CONFIG_ARM=y -CONFIG_SYS_DCACHE_OFF=y -CONFIG_ARCH_CPU_INIT=y -CONFIG_TARGET_COLIBRI_PXA270=y -CONFIG_SYS_TEXT_BASE=0x0 -CONFIG_SYS_MALLOC_LEN=0x20000 -CONFIG_NR_DRAM_BANKS=1 -CONFIG_ENV_SIZE=0x40000 -CONFIG_ENV_SECT_SIZE=0x40000 -CONFIG_SYS_LOAD_ADDR=0xa0000000 -CONFIG_ENV_ADDR=0x80000 -CONFIG_ENV_VARS_UBOOT_CONFIG=y -CONFIG_HAS_BOARD_SIZE_LIMIT=y -CONFIG_BOARD_SIZE_LIMIT=262144 -CONFIG_TIMESTAMP=y -CONFIG_SYS_MONITOR_BASE=0x00000000 -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="console=tty0 console=ttyS0,115200" -CONFIG_USE_BOOTCOMMAND=y -CONFIG_BOOTCOMMAND="if fatload mmc 0 0xa0000000 uImage; then bootm 0xa0000000; fi; if usb reset && fatload usb 0 0xa0000000 uImage; then bootm 0xa0000000; fi; bootm 0xc0000;" -CONFIG_SYS_DEVICE_NULLDEV=y -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_DISPLAY_BOARDINFO_LATE=y -# CONFIG_CMDLINE_EDITING is not set -# CONFIG_AUTO_COMPLETE is not set -# CONFIG_SYS_LONGHELP is not set -CONFIG_SYS_PROMPT="$ " -# CONFIG_CMD_ELF is not set -# CONFIG_CMD_EXPORTENV is not set -# CONFIG_CMD_IMPORTENV is not set -CONFIG_CMD_DM=y -# CONFIG_CMD_LOADB is not set -# CONFIG_CMD_LOADS is not set -CONFIG_CMD_MMC=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_BOOTP_BOOTFILESIZE=y -CONFIG_CMD_PING=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_FLASH=y -CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y -CONFIG_NET_RETRY_COUNT=10 -CONFIG_DM=y -CONFIG_PXA_MMC_GENERIC=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_PROTECTION=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_DRIVER_DM9000=y -CONFIG_DM_SERIAL=y -CONFIG_PXA_SERIAL=y -CONFIG_USB=y -# CONFIG_REGEX is not set -CONFIG_OF_LIBFDT=y diff --git a/configs/colibri_t20_defconfig b/configs/colibri_t20_defconfig index b883fc1..00f45dc 100644 --- a/configs/colibri_t20_defconfig +++ b/configs/colibri_t20_defconfig @@ -25,7 +25,6 @@ CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_NFS is not set -CONFIG_CMD_BMP=y CONFIG_CMD_CACHE=y CONFIG_CMD_PMIC=y CONFIG_CMD_REGULATOR=y @@ -69,8 +68,4 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x1b67 CONFIG_USB_GADGET_PRODUCT_NUM=0x4000 CONFIG_CI_UDC=y CONFIG_USB_GADGET_DOWNLOAD=y -CONFIG_DM_VIDEO=y -# CONFIG_VIDEO_BPP8 is not set -CONFIG_VIDEO_TEGRA20=y -CONFIG_CONSOLE_SCROLL_LINES=10 CONFIG_OF_LIBFDT_OVERLAY=y diff --git a/configs/colibri_vf_defconfig b/configs/colibri_vf_defconfig index fa508d3..c5f4322 100644 --- a/configs/colibri_vf_defconfig +++ b/configs/colibri_vf_defconfig @@ -20,7 +20,7 @@ CONFIG_BOOTDELAY=1 CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="run ubiboot || run distro_bootcmd;" CONFIG_USE_PREBOOT=y -CONFIG_PREBOOT="setenv fdtfile ${soc}-colibri-${fdt_board}.dtb" +CONFIG_PREBOOT="test -n ${fdtfile} || setenv fdtfile ${soc}-colibri-${fdt_board}.dtb" CONFIG_LOGLEVEL=3 # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y @@ -52,7 +52,6 @@ CONFIG_CMD_DHCP=y # CONFIG_CMD_NFS is not set CONFIG_CMD_MII=y CONFIG_CMD_PING=y -CONFIG_CMD_BMP=y CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y @@ -99,10 +98,6 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x1b67 CONFIG_USB_GADGET_PRODUCT_NUM=0x4000 CONFIG_CI_UDC=y CONFIG_USB_GADGET_DOWNLOAD=y -CONFIG_DM_VIDEO=y -# CONFIG_VIDEO_BPP8 is not set -# CONFIG_VIDEO_BPP16 is not set -CONFIG_SPLASH_SCREEN_ALIGN=y CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_FDT_FIXUP_PARTITIONS=y # CONFIG_EFI_LOADER is not set diff --git a/configs/da850evm_defconfig b/configs/da850evm_defconfig index 6785daa..bfc8488 100644 --- a/configs/da850evm_defconfig +++ b/configs/da850evm_defconfig @@ -34,7 +34,6 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_CLOCKS=y CONFIG_MISC_INIT_R=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y -CONFIG_SPL_SEPARATE_BSS=y # CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_SPI_LOAD=y diff --git a/configs/da850evm_nand_defconfig b/configs/da850evm_nand_defconfig index 013ea64..0f5e135 100644 --- a/configs/da850evm_nand_defconfig +++ b/configs/da850evm_nand_defconfig @@ -31,7 +31,6 @@ CONFIG_DEFAULT_FDT_FILE="da850-evm.dtb" CONFIG_BOARD_EARLY_INIT_F=y CONFIG_CLOCKS=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y -CONFIG_SPL_SEPARATE_BSS=y # CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set CONFIG_SPL_NAND_SUPPORT=y CONFIG_SPL_NAND_DRIVERS=y diff --git a/configs/deneb_defconfig b/configs/deneb_defconfig index 55034ad..425fff6 100644 --- a/configs/deneb_defconfig +++ b/configs/deneb_defconfig @@ -36,7 +36,6 @@ CONFIG_LOG=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y -CONFIG_SPL_SEPARATE_BSS=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x800 CONFIG_SPL_POWER_DOMAIN=y diff --git a/configs/dra7xx_evm_defconfig b/configs/dra7xx_evm_defconfig index 1aee9d7..e972d3b 100644 --- a/configs/dra7xx_evm_defconfig +++ b/configs/dra7xx_evm_defconfig @@ -27,7 +27,6 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_BOARD_EARLY_INIT_F=y # CONFIG_MISC_INIT_R is not set CONFIG_SPL_SYS_MALLOC_SIMPLE=y -CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_DMA=y CONFIG_SPL_NAND_DRIVERS=y CONFIG_SPL_NAND_ECC=y diff --git a/configs/dra7xx_hs_evm_defconfig b/configs/dra7xx_hs_evm_defconfig index 728515d..1e872b5 100644 --- a/configs/dra7xx_hs_evm_defconfig +++ b/configs/dra7xx_hs_evm_defconfig @@ -32,7 +32,6 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_BOARD_EARLY_INIT_F=y # CONFIG_MISC_INIT_R is not set CONFIG_SPL_SYS_MALLOC_SIMPLE=y -CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_DMA=y # CONFIG_SPL_NAND_SUPPORT is not set CONFIG_SPL_NAND_DRIVERS=y diff --git a/configs/dra7xx_hs_evm_usb_defconfig b/configs/dra7xx_hs_evm_usb_defconfig index 9ebe454..8c07da9 100644 --- a/configs/dra7xx_hs_evm_usb_defconfig +++ b/configs/dra7xx_hs_evm_usb_defconfig @@ -34,7 +34,6 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_BOARD_EARLY_INIT_F=y # CONFIG_MISC_INIT_R is not set CONFIG_SPL_SYS_MALLOC_SIMPLE=y -CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_DMA=y # CONFIG_SPL_NAND_SUPPORT is not set CONFIG_SPL_DM_SPI_FLASH=y diff --git a/configs/evb-rk3568_defconfig b/configs/evb-rk3568_defconfig index d2af961..1d61c15 100644 --- a/configs/evb-rk3568_defconfig +++ b/configs/evb-rk3568_defconfig @@ -26,7 +26,6 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-evb.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_STACK_R=y -CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_ATF=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y diff --git a/configs/giedi_defconfig b/configs/giedi_defconfig index 0744325..4fbf7eb 100644 --- a/configs/giedi_defconfig +++ b/configs/giedi_defconfig @@ -36,7 +36,6 @@ CONFIG_LOG=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y -CONFIG_SPL_SEPARATE_BSS=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x800 CONFIG_SPL_POWER_DOMAIN=y diff --git a/configs/gwventana_emmc_defconfig b/configs/gwventana_emmc_defconfig index f65f28e..28a73fb 100644 --- a/configs/gwventana_emmc_defconfig +++ b/configs/gwventana_emmc_defconfig @@ -14,11 +14,11 @@ CONFIG_SYS_I2C_MXC_I2C1=y CONFIG_SYS_I2C_MXC_I2C2=y CONFIG_SYS_I2C_MXC_I2C3=y CONFIG_CMD_EECONFIG=y -CONFIG_CMD_GSC=y CONFIG_DEFAULT_DEVICE_TREE="imx6q-gw54xx" CONFIG_SPL_TEXT_BASE=0x00908000 CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK_R_ADDR=0x18000000 CONFIG_SPL=y CONFIG_ENV_OFFSET_REDUND=0xD1400 diff --git a/configs/gwventana_gw5904_defconfig b/configs/gwventana_gw5904_defconfig index 1d95fb0..9deb080 100644 --- a/configs/gwventana_gw5904_defconfig +++ b/configs/gwventana_gw5904_defconfig @@ -14,11 +14,11 @@ CONFIG_SYS_I2C_MXC_I2C1=y CONFIG_SYS_I2C_MXC_I2C2=y CONFIG_SYS_I2C_MXC_I2C3=y CONFIG_CMD_EECONFIG=y -CONFIG_CMD_GSC=y CONFIG_DEFAULT_DEVICE_TREE="imx6q-gw54xx" CONFIG_SPL_TEXT_BASE=0x00908000 CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK_R_ADDR=0x18000000 CONFIG_SPL=y CONFIG_ENV_OFFSET_REDUND=0xD1400 diff --git a/configs/gwventana_nand_defconfig b/configs/gwventana_nand_defconfig index 275b2c6..8ef794c 100644 --- a/configs/gwventana_nand_defconfig +++ b/configs/gwventana_nand_defconfig @@ -14,11 +14,11 @@ CONFIG_SYS_I2C_MXC_I2C1=y CONFIG_SYS_I2C_MXC_I2C2=y CONFIG_SYS_I2C_MXC_I2C3=y CONFIG_CMD_EECONFIG=y -CONFIG_CMD_GSC=y CONFIG_DEFAULT_DEVICE_TREE="imx6q-gw54xx" CONFIG_SPL_TEXT_BASE=0x00908000 CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK_R_ADDR=0x18000000 CONFIG_SPL=y CONFIG_ENV_OFFSET_REDUND=0x1080000 diff --git a/configs/imx6q_logic_defconfig b/configs/imx6q_logic_defconfig index 0a8ac8f..560733e 100644 --- a/configs/imx6q_logic_defconfig +++ b/configs/imx6q_logic_defconfig @@ -27,7 +27,6 @@ CONFIG_BOOTCOMMAND="run autoboot" CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y CONFIG_SPL_RAW_IMAGE_SUPPORT=y -CONFIG_SPL_SEPARATE_BSS=y # CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set CONFIG_SPL_DMA=y CONFIG_SPL_I2C=y diff --git a/configs/imx8mm-cl-iot-gate-optee_defconfig b/configs/imx8mm-cl-iot-gate-optee_defconfig index c736fd8..0bde51a 100644 --- a/configs/imx8mm-cl-iot-gate-optee_defconfig +++ b/configs/imx8mm-cl-iot-gate-optee_defconfig @@ -26,7 +26,6 @@ CONFIG_SPL_LOAD_FIT=y CONFIG_OF_SYSTEM_SETUP=y CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_BOARD_INIT=y -CONFIG_SPL_SEPARATE_BSS=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_I2C=y diff --git a/configs/imx8mm-cl-iot-gate_defconfig b/configs/imx8mm-cl-iot-gate_defconfig index f1ace0d..d734586 100644 --- a/configs/imx8mm-cl-iot-gate_defconfig +++ b/configs/imx8mm-cl-iot-gate_defconfig @@ -28,7 +28,6 @@ CONFIG_SPL_LOAD_FIT=y CONFIG_OF_SYSTEM_SETUP=y CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_BOARD_INIT=y -CONFIG_SPL_SEPARATE_BSS=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_I2C=y diff --git a/configs/imx8mm-icore-mx8mm-ctouch2_defconfig b/configs/imx8mm-icore-mx8mm-ctouch2_defconfig index c8acc2e..535ff6d 100644 --- a/configs/imx8mm-icore-mx8mm-ctouch2_defconfig +++ b/configs/imx8mm-icore-mx8mm-ctouch2_defconfig @@ -24,7 +24,6 @@ CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" CONFIG_OF_SYSTEM_SETUP=y CONFIG_DEFAULT_FDT_FILE="imx8mm-icore-mx8mm-ctouch2.dtb" CONFIG_SPL_BOARD_INIT=y -CONFIG_SPL_SEPARATE_BSS=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_POWER=y diff --git a/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig b/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig index 6dd8275..101d5a0 100644 --- a/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig +++ b/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig @@ -24,7 +24,6 @@ CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" CONFIG_OF_SYSTEM_SETUP=y CONFIG_DEFAULT_FDT_FILE="imx8mm-icore-mx8mm-edimm2.2.dtb" CONFIG_SPL_BOARD_INIT=y -CONFIG_SPL_SEPARATE_BSS=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_POWER=y diff --git a/configs/imx8mm-mx8menlo_defconfig b/configs/imx8mm-mx8menlo_defconfig index b63ff2f..0d3e19e 100644 --- a/configs/imx8mm-mx8menlo_defconfig +++ b/configs/imx8mm-mx8menlo_defconfig @@ -35,7 +35,6 @@ CONFIG_LOG=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_BOARD_INIT=y -CONFIG_SPL_SEPARATE_BSS=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_I2C=y diff --git a/configs/imx8mm_beacon_defconfig b/configs/imx8mm_beacon_defconfig index 403934a..9cd8ac9 100644 --- a/configs/imx8mm_beacon_defconfig +++ b/configs/imx8mm_beacon_defconfig @@ -26,7 +26,6 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; fi;" CONFIG_DEFAULT_FDT_FILE="imx8mm-beacon-kit.dtb" CONFIG_SPL_BOARD_INIT=y -CONFIG_SPL_SEPARATE_BSS=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_I2C=y diff --git a/configs/imx8mm_data_modul_edm_sbc_defconfig b/configs/imx8mm_data_modul_edm_sbc_defconfig index dc9aeb9..afc8c43 100644 --- a/configs/imx8mm_data_modul_edm_sbc_defconfig +++ b/configs/imx8mm_data_modul_edm_sbc_defconfig @@ -44,7 +44,6 @@ CONFIG_BOARD_LATE_INIT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_LEGACY_IMAGE_SUPPORT=y CONFIG_SPL_LEGACY_IMAGE_CRC_CHECK=y -CONFIG_SPL_SEPARATE_BSS=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_I2C=y diff --git a/configs/imx8mm_evk_defconfig b/configs/imx8mm_evk_defconfig index 36bf17d..ec3206b 100644 --- a/configs/imx8mm_evk_defconfig +++ b/configs/imx8mm_evk_defconfig @@ -24,7 +24,6 @@ CONFIG_SPL_LOAD_FIT=y CONFIG_OF_SYSTEM_SETUP=y CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_BOARD_INIT=y -CONFIG_SPL_SEPARATE_BSS=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_I2C=y @@ -80,6 +79,7 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_DM_PWM=y CONFIG_PWM_IMX=y +CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y diff --git a/configs/imx8mm_venice_defconfig b/configs/imx8mm_venice_defconfig index 7e6bb68..490de19 100644 --- a/configs/imx8mm_venice_defconfig +++ b/configs/imx8mm_venice_defconfig @@ -16,7 +16,7 @@ CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_ENV_OFFSET_REDUND=0xff8000 -CONFIG_SYS_LOAD_ADDR=0x40480000 +CONFIG_SYS_LOAD_ADDR=0x48200000 CONFIG_SYS_MEMTEST_START=0x40000000 CONFIG_SYS_MEMTEST_END=0x80000000 CONFIG_LTO=y @@ -31,7 +31,6 @@ CONFIG_OF_SYSTEM_SETUP=y CONFIG_USE_PREBOOT=y CONFIG_PREBOOT="gsc wd-disable" CONFIG_BOARD_LATE_INIT=y -CONFIG_SPL_SEPARATE_BSS=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_I2C=y @@ -40,13 +39,17 @@ CONFIG_SPL_WATCHDOG=y CONFIG_SYS_PROMPT="u-boot=> " # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set -# CONFIG_CMD_CRC32 is not set +CONFIG_CRC32_VERIFY=y +CONFIG_CMD_MD5SUM=y +CONFIG_MD5SUM_VERIFY=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_CLK=y CONFIG_CMD_FUSE=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y CONFIG_CMD_UUID=y @@ -71,6 +74,7 @@ CONFIG_SPL_CLK_COMPOSITE_CCF=y CONFIG_CLK_COMPOSITE_CCF=y CONFIG_SPL_CLK_IMX8MM=y CONFIG_CLK_IMX8MM=y +CONFIG_GPIO_HOG=y CONFIG_MXC_GPIO=y CONFIG_DM_I2C=y CONFIG_LED=y @@ -98,6 +102,8 @@ CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_PINCTRL_IMX8M=y +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8M_POWER_DOMAIN=y CONFIG_DM_PMIC=y CONFIG_DM_PMIC_BD71837=y CONFIG_SPL_DM_PMIC_BD71837=y @@ -106,6 +112,8 @@ CONFIG_SPL_DM_PMIC_MP5416=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_SERIAL=y +# CONFIG_SPL_DM_SERIAL is not set CONFIG_MXC_UART=y CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y @@ -113,5 +121,22 @@ CONFIG_SYSRESET_PSCI=y CONFIG_SYSRESET_WATCHDOG=y CONFIG_DM_THERMAL=y CONFIG_IMX_TMU=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_ASIX88179=y +CONFIG_USB_ETHER_LAN75XX=y +CONFIG_USB_ETHER_LAN78XX=y +CONFIG_USB_ETHER_MCS7830=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_USB_ETHER_SMSC95XX=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Gateworks" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_IMX_WATCHDOG=y CONFIG_HEXDUMP=y +CONFIG_OF_LIBFDT_OVERLAY=y diff --git a/configs/imx8mn_beacon_2g_defconfig b/configs/imx8mn_beacon_2g_defconfig index b942607..145f96d 100644 --- a/configs/imx8mn_beacon_2g_defconfig +++ b/configs/imx8mn_beacon_2g_defconfig @@ -34,7 +34,6 @@ CONFIG_DEFAULT_FDT_FILE="imx8mn-beacon-kit.dtb" CONFIG_ARCH_MISC_INIT=y CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_BOOTROM_SUPPORT=y -CONFIG_SPL_SEPARATE_BSS=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_I2C=y diff --git a/configs/imx8mn_beacon_defconfig b/configs/imx8mn_beacon_defconfig index fdd9590..9052e68 100644 --- a/configs/imx8mn_beacon_defconfig +++ b/configs/imx8mn_beacon_defconfig @@ -33,7 +33,6 @@ CONFIG_DEFAULT_FDT_FILE="imx8mn-beacon-kit.dtb" CONFIG_ARCH_MISC_INIT=y CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_BOOTROM_SUPPORT=y -CONFIG_SPL_SEPARATE_BSS=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_I2C=y diff --git a/configs/imx8mn_bsh_smm_s2_defconfig b/configs/imx8mn_bsh_smm_s2_defconfig index 3d67079..49f4253 100644 --- a/configs/imx8mn_bsh_smm_s2_defconfig +++ b/configs/imx8mn_bsh_smm_s2_defconfig @@ -28,7 +28,6 @@ CONFIG_ARCH_MISC_INIT=y CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_BOOTROM_SUPPORT=y -CONFIG_SPL_SEPARATE_BSS=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_I2C=y @@ -80,6 +79,7 @@ CONFIG_SPL_DM_PMIC_BD71837=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_SYSRESET=y CONFIG_SYSRESET_PSCI=y diff --git a/configs/imx8mn_bsh_smm_s2pro_defconfig b/configs/imx8mn_bsh_smm_s2pro_defconfig index c5809f5..52661ec 100644 --- a/configs/imx8mn_bsh_smm_s2pro_defconfig +++ b/configs/imx8mn_bsh_smm_s2pro_defconfig @@ -29,7 +29,6 @@ CONFIG_ARCH_MISC_INIT=y CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_BOOTROM_SUPPORT=y -CONFIG_SPL_SEPARATE_BSS=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_I2C=y @@ -77,6 +76,7 @@ CONFIG_SPL_DM_PMIC_BD71837=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_SYSRESET=y CONFIG_SYSRESET_PSCI=y diff --git a/configs/imx8mn_ddr4_evk_defconfig b/configs/imx8mn_ddr4_evk_defconfig index 917cdb5..56a30744 100644 --- a/configs/imx8mn_ddr4_evk_defconfig +++ b/configs/imx8mn_ddr4_evk_defconfig @@ -16,7 +16,7 @@ CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 -CONFIG_SYS_LOAD_ADDR=0x40480000 +CONFIG_SYS_LOAD_ADDR=0x42000000 CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y CONFIG_FIT_EXTERNAL_OFFSET=0x3000 @@ -27,7 +27,6 @@ CONFIG_DEFAULT_FDT_FILE="imx8mn-ddr4-evk.dtb" CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_BOOTROM_SUPPORT=y -CONFIG_SPL_SEPARATE_BSS=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_I2C=y @@ -76,6 +75,7 @@ CONFIG_PINCTRL_IMX8M=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y diff --git a/configs/imx8mn_evk_defconfig b/configs/imx8mn_evk_defconfig index b2981d1..22fad70 100644 --- a/configs/imx8mn_evk_defconfig +++ b/configs/imx8mn_evk_defconfig @@ -1,6 +1,4 @@ CONFIG_ARM=y -CONFIG_SPL_SYS_ICACHE_OFF=y -CONFIG_SPL_SYS_DCACHE_OFF=y CONFIG_ARCH_IMX8M=y CONFIG_SYS_TEXT_BASE=0x40200000 CONFIG_SYS_MALLOC_LEN=0x2000000 @@ -18,7 +16,7 @@ CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 -CONFIG_SYS_LOAD_ADDR=0x40480000 +CONFIG_SYS_LOAD_ADDR=0x42000000 CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y CONFIG_FIT_EXTERNAL_OFFSET=0x3000 @@ -33,7 +31,6 @@ CONFIG_SPL_BOOTROM_SUPPORT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_LEGACY_IMAGE_SUPPORT=y CONFIG_SPL_LEGACY_IMAGE_CRC_CHECK=y -CONFIG_SPL_SEPARATE_BSS=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_I2C=y @@ -84,7 +81,6 @@ CONFIG_SPL_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_DM_SERIAL=y -# CONFIG_SPL_DM_SERIAL is not set CONFIG_MXC_UART=y CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y diff --git a/configs/imx8mn_var_som_defconfig b/configs/imx8mn_var_som_defconfig index 707c58f..5ec82f2 100644 --- a/configs/imx8mn_var_som_defconfig +++ b/configs/imx8mn_var_som_defconfig @@ -29,7 +29,6 @@ CONFIG_DEFAULT_FDT_FILE="freescale/imx8mn-var-som-symphony.dtb" CONFIG_ARCH_MISC_INIT=y CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_BOOTROM_SUPPORT=y -CONFIG_SPL_SEPARATE_BSS=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_I2C=y diff --git a/configs/imx8mn_venice_defconfig b/configs/imx8mn_venice_defconfig index 02d79fb..639fee7 100644 --- a/configs/imx8mn_venice_defconfig +++ b/configs/imx8mn_venice_defconfig @@ -13,10 +13,11 @@ CONFIG_SPL_TEXT_BASE=0x912000 CONFIG_TARGET_IMX8MN_VENICE=y CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_ENV_OFFSET_REDUND=0xff8000 CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 -CONFIG_SYS_LOAD_ADDR=0x40480000 +CONFIG_SYS_LOAD_ADDR=0x48200000 CONFIG_SYS_MEMTEST_START=0x40000000 CONFIG_SYS_MEMTEST_END=0x80000000 CONFIG_LTO=y @@ -32,7 +33,6 @@ CONFIG_USE_PREBOOT=y CONFIG_PREBOOT="gsc wd-disable" CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_BOOTROM_SUPPORT=y -CONFIG_SPL_SEPARATE_BSS=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_I2C=y @@ -40,13 +40,17 @@ CONFIG_SPL_WATCHDOG=y CONFIG_SYS_PROMPT="u-boot=> " # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set -# CONFIG_CMD_CRC32 is not set +CONFIG_CRC32_VERIFY=y +CONFIG_CMD_MD5SUM=y +CONFIG_MD5SUM_VERIFY=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_CLK=y CONFIG_CMD_FUSE=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y CONFIG_CMD_UUID=y @@ -69,6 +73,7 @@ CONFIG_TFTP_BLOCKSIZE=4096 CONFIG_SPL_DM=y CONFIG_SPL_CLK_IMX8MN=y CONFIG_CLK_IMX8MN=y +CONFIG_GPIO_HOG=y CONFIG_MXC_GPIO=y CONFIG_DM_I2C=y CONFIG_LED=y @@ -96,6 +101,8 @@ CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_PINCTRL_IMX8M=y +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8M_POWER_DOMAIN=y CONFIG_DM_PMIC=y CONFIG_DM_PMIC_BD71837=y CONFIG_SPL_DM_PMIC_BD71837=y @@ -104,6 +111,8 @@ CONFIG_SPL_DM_PMIC_MP5416=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_SERIAL=y +# CONFIG_SPL_DM_SERIAL is not set CONFIG_MXC_UART=y CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y @@ -111,5 +120,22 @@ CONFIG_SYSRESET_PSCI=y CONFIG_SYSRESET_WATCHDOG=y CONFIG_DM_THERMAL=y CONFIG_IMX_TMU=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_ASIX88179=y +CONFIG_USB_ETHER_LAN75XX=y +CONFIG_USB_ETHER_LAN78XX=y +CONFIG_USB_ETHER_MCS7830=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_USB_ETHER_SMSC95XX=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Gateworks" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_IMX_WATCHDOG=y CONFIG_HEXDUMP=y +CONFIG_OF_LIBFDT_OVERLAY=y diff --git a/configs/imx8mp_evk_defconfig b/configs/imx8mp_evk_defconfig index c64b699..081f7e0 100644 --- a/configs/imx8mp_evk_defconfig +++ b/configs/imx8mp_evk_defconfig @@ -32,7 +32,6 @@ CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_BOOTROM_SUPPORT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y -CONFIG_SPL_SEPARATE_BSS=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_I2C=y @@ -91,6 +90,7 @@ CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_SPL_POWER_I2C=y +CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y diff --git a/configs/imx8mp_rsb3720a1_4G_defconfig b/configs/imx8mp_rsb3720a1_4G_defconfig index c7d5b25..a7585ba 100644 --- a/configs/imx8mp_rsb3720a1_4G_defconfig +++ b/configs/imx8mp_rsb3720a1_4G_defconfig @@ -39,7 +39,6 @@ CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_BOOTROM_SUPPORT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y -CONFIG_SPL_SEPARATE_BSS=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_I2C=y diff --git a/configs/imx8mp_rsb3720a1_6G_defconfig b/configs/imx8mp_rsb3720a1_6G_defconfig index 5e36be8..5d06dc4 100644 --- a/configs/imx8mp_rsb3720a1_6G_defconfig +++ b/configs/imx8mp_rsb3720a1_6G_defconfig @@ -39,7 +39,6 @@ CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_BOOTROM_SUPPORT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y -CONFIG_SPL_SEPARATE_BSS=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_I2C=y diff --git a/configs/imx8mp_venice_defconfig b/configs/imx8mp_venice_defconfig new file mode 100644 index 0000000..97c8bb5 --- /dev/null +++ b/configs/imx8mp_venice_defconfig @@ -0,0 +1,141 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_SYS_TEXT_BASE=0x40200000 +CONFIG_SYS_MALLOC_LEN=0x2000000 +CONFIG_SPL_GPIO=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_ENV_SIZE=0x8000 +CONFIG_ENV_OFFSET=0xff0000 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="imx8mp-venice" +CONFIG_SPL_TEXT_BASE=0x920000 +CONFIG_TARGET_IMX8MP_VENICE=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL=y +CONFIG_ENV_OFFSET_REDUND=0xff8000 +CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 +CONFIG_SYS_LOAD_ADDR=0x40480000 +CONFIG_SYS_MEMTEST_START=0x40000000 +CONFIG_SYS_MEMTEST_END=0x80000000 +CONFIG_LTO=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 +CONFIG_SPL_LOAD_FIT=y +# CONFIG_USE_SPL_FIT_GENERATOR is not set +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_SYSTEM_SETUP=y +# CONFIG_USE_BOOTCOMMAND is not set +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="gsc wd-disable" +CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_BOOTROM_SUPPORT=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 +CONFIG_SPL_I2C=y +CONFIG_SPL_WATCHDOG=y +CONFIG_SYS_PROMPT="u-boot=> " +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CRC32_VERIFY=y +CONFIG_CMD_MD5SUM=y +CONFIG_MD5SUM_VERIFY=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_CLK=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_UUID=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT4_WRITE=y +# CONFIG_ISO_PARTITION is not set +# CONFIG_SPL_EFI_PARTITION is not set +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIST="imx8mp-venice imx8mp-venice-gw74xx" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_IP_DEFRAG=y +CONFIG_TFTP_BLOCKSIZE=4096 +CONFIG_SPL_DM=y +CONFIG_CLK_COMPOSITE_CCF=y +CONFIG_CLK_IMX8MP=y +CONFIG_GPIO_HOG=y +CONFIG_MXC_GPIO=y +CONFIG_DM_I2C=y +CONFIG_LED=y +CONFIG_LED_BLINK=y +CONFIG_LED_GPIO=y +CONFIG_SPL_MISC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_USDHC=y +CONFIG_PHY_TI_DP83867=y +CONFIG_PHY_FIXED=y +CONFIG_DM_ETH=y +CONFIG_DM_MDIO=y +CONFIG_DM_DSA=y +CONFIG_DM_ETH_PHY=y +CONFIG_PHY_GIGE=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_IMX=y +CONFIG_FEC_MXC=y +CONFIG_KSZ9477=y +CONFIG_RGMII=y +CONFIG_MII=y +CONFIG_PHY_IMX8MQ_USB=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8M_POWER_DOMAIN=y +CONFIG_IMX8MP_HSIOMIX_BLKCTRL=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_BD71837=y +CONFIG_SPL_DM_PMIC_BD71837=y +CONFIG_DM_PMIC_MP5416=y +CONFIG_SPL_DM_PMIC_MP5416=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_SERIAL=y +# CONFIG_SPL_DM_SERIAL is not set +CONFIG_MXC_UART=y +CONFIG_SYSRESET=y +CONFIG_SPL_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_SYSRESET_WATCHDOG=y +CONFIG_DM_THERMAL=y +CONFIG_IMX_TMU=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_XHCI_DWC3_OF_SIMPLE=y +CONFIG_USB_EHCI_HCD=y +CONFIG_MXC_USB_OTG_HACTIVE=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_ASIX88179=y +CONFIG_USB_ETHER_LAN75XX=y +CONFIG_USB_ETHER_LAN78XX=y +CONFIG_USB_ETHER_MCS7830=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_USB_ETHER_SMSC95XX=y +CONFIG_IMX_WATCHDOG=y +CONFIG_HEXDUMP=y +CONFIG_OF_LIBFDT_OVERLAY=y diff --git a/configs/imx8mq_cm_defconfig b/configs/imx8mq_cm_defconfig index c959347..1cca21e 100644 --- a/configs/imx8mq_cm_defconfig +++ b/configs/imx8mq_cm_defconfig @@ -28,7 +28,6 @@ CONFIG_SPL_LOAD_FIT=y CONFIG_OF_SYSTEM_SETUP=y CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_BOARD_INIT=y -CONFIG_SPL_SEPARATE_BSS=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_I2C=y diff --git a/configs/imx8mq_evk_defconfig b/configs/imx8mq_evk_defconfig index df7a259..780f931 100644 --- a/configs/imx8mq_evk_defconfig +++ b/configs/imx8mq_evk_defconfig @@ -80,6 +80,7 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_SPL_POWER_I2C=y CONFIG_DM_RESET=y +CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_DM_THERMAL=y CONFIG_USB=y diff --git a/configs/imx8qm_mek_defconfig b/configs/imx8qm_mek_defconfig index eb61ee8..2e42872 100644 --- a/configs/imx8qm_mek_defconfig +++ b/configs/imx8qm_mek_defconfig @@ -30,7 +30,6 @@ CONFIG_LOG=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y -CONFIG_SPL_SEPARATE_BSS=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x800 CONFIG_SPL_POWER_DOMAIN=y diff --git a/configs/imx8qm_rom7720_a1_4G_defconfig b/configs/imx8qm_rom7720_a1_4G_defconfig index fa1968b..d9997cf 100644 --- a/configs/imx8qm_rom7720_a1_4G_defconfig +++ b/configs/imx8qm_rom7720_a1_4G_defconfig @@ -26,7 +26,6 @@ CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript CONFIG_LOG=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_BOARD_INIT=y -CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_POWER_DOMAIN=y CONFIG_SPL_WATCHDOG=y CONFIG_HUSH_PARSER=y diff --git a/configs/imx8qxp_mek_defconfig b/configs/imx8qxp_mek_defconfig index 817b9af..43f42f7 100644 --- a/configs/imx8qxp_mek_defconfig +++ b/configs/imx8qxp_mek_defconfig @@ -30,7 +30,6 @@ CONFIG_LOG=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y -CONFIG_SPL_SEPARATE_BSS=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x800 CONFIG_SPL_POWER_DOMAIN=y diff --git a/configs/imx8ulp_evk_defconfig b/configs/imx8ulp_evk_defconfig index c6eddce..f47c801 100644 --- a/configs/imx8ulp_evk_defconfig +++ b/configs/imx8ulp_evk_defconfig @@ -29,7 +29,6 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_BOOTROM_SUPPORT=y -CONFIG_SPL_SEPARATE_BSS=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_WATCHDOG=y diff --git a/configs/iot2050_defconfig b/configs/iot2050_defconfig index 10abb77..175ec70 100644 --- a/configs/iot2050_defconfig +++ b/configs/iot2050_defconfig @@ -34,7 +34,6 @@ CONFIG_CONSOLE_MUX=y CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_STACK_R=y -CONFIG_SPL_SEPARATE_BSS=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400 CONFIG_SPL_DM_MAILBOX=y diff --git a/configs/j7200_evm_a72_defconfig b/configs/j7200_evm_a72_defconfig index 3d0d197..3eba698 100644 --- a/configs/j7200_evm_a72_defconfig +++ b/configs/j7200_evm_a72_defconfig @@ -35,7 +35,6 @@ CONFIG_LOGLEVEL=7 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_STACK_R=y -CONFIG_SPL_SEPARATE_BSS=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400 CONFIG_SPL_DMA=y diff --git a/configs/j721e_evm_a72_defconfig b/configs/j721e_evm_a72_defconfig index 792a902..931abf5 100644 --- a/configs/j721e_evm_a72_defconfig +++ b/configs/j721e_evm_a72_defconfig @@ -32,7 +32,6 @@ CONFIG_LOGLEVEL=7 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_STACK_R=y -CONFIG_SPL_SEPARATE_BSS=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400 CONFIG_SPL_DMA=y diff --git a/configs/j721e_hs_evm_a72_defconfig b/configs/j721e_hs_evm_a72_defconfig index 8146af9..3890b6c 100644 --- a/configs/j721e_hs_evm_a72_defconfig +++ b/configs/j721e_hs_evm_a72_defconfig @@ -35,7 +35,6 @@ CONFIG_LOGLEVEL=7 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_STACK_R=y -CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y CONFIG_SPL_DM_MAILBOX=y diff --git a/configs/j721s2_evm_a72_defconfig b/configs/j721s2_evm_a72_defconfig index e0d1245..0023f73 100644 --- a/configs/j721s2_evm_a72_defconfig +++ b/configs/j721s2_evm_a72_defconfig @@ -35,7 +35,6 @@ CONFIG_LOGLEVEL=7 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_STACK_R=y -CONFIG_SPL_SEPARATE_BSS=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400 CONFIG_SPL_DMA=y diff --git a/configs/kontron-sl-mx6ul_defconfig b/configs/kontron-sl-mx6ul_defconfig index c4f8fdb..a59dacf 100644 --- a/configs/kontron-sl-mx6ul_defconfig +++ b/configs/kontron-sl-mx6ul_defconfig @@ -28,7 +28,6 @@ CONFIG_BOARD_TYPES=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_LEGACY_IMAGE_SUPPORT=y CONFIG_SPL_LEGACY_IMAGE_CRC_CHECK=y -CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_USB_HOST=y CONFIG_SPL_USB_GADGET=y CONFIG_SPL_WATCHDOG=y diff --git a/configs/kontron-sl-mx8mm_defconfig b/configs/kontron-sl-mx8mm_defconfig index fa612aa..1375c78 100644 --- a/configs/kontron-sl-mx8mm_defconfig +++ b/configs/kontron-sl-mx8mm_defconfig @@ -27,7 +27,6 @@ CONFIG_SPL_LOAD_FIT=y CONFIG_OF_BOARD_SETUP=y CONFIG_BOARD_TYPES=y CONFIG_SPL_BOARD_INIT=y -CONFIG_SPL_SEPARATE_BSS=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 # CONFIG_SPL_FIT_IMAGE_TINY is not set diff --git a/configs/kontron_sl28_defconfig b/configs/kontron_sl28_defconfig index 0d2c067..7a00e48 100644 --- a/configs/kontron_sl28_defconfig +++ b/configs/kontron_sl28_defconfig @@ -34,7 +34,6 @@ CONFIG_USE_BOOTARGS=y CONFIG_BOARD_LATE_INIT=y CONFIG_PCI_INIT_R=y CONFIG_SPL_BOARD_INIT=y -CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x230000 diff --git a/configs/mx6cuboxi_defconfig b/configs/mx6cuboxi_defconfig index 6422ac5..1e2e332 100644 --- a/configs/mx6cuboxi_defconfig +++ b/configs/mx6cuboxi_defconfig @@ -26,7 +26,6 @@ CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd" CONFIG_USE_PREBOOT=y CONFIG_PREBOOT="if hdmidet; then usb start; setenv stdin serial,usbkbd; setenv stdout serial,vidconsole; setenv stderr serial,vidconsole; else setenv stdin serial; setenv stdout serial; setenv stderr serial; fi;" CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_FS_EXT4=y CONFIG_SPL_I2C=y CONFIG_SPL_WATCHDOG=y diff --git a/configs/mx6sabreauto_defconfig b/configs/mx6sabreauto_defconfig index 7160825..0c7aaa6 100644 --- a/configs/mx6sabreauto_defconfig +++ b/configs/mx6sabreauto_defconfig @@ -33,7 +33,6 @@ CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev};if mmc rescan; then if run loa CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y CONFIG_SPL_LEGACY_IMAGE_SUPPORT=y -CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_FIT_IMAGE_TINY=y CONFIG_SPL_FS_EXT4=y CONFIG_SPL_I2C=y diff --git a/configs/mx6sabresd_defconfig b/configs/mx6sabresd_defconfig index 6d12247..c8d9ebd 100644 --- a/configs/mx6sabresd_defconfig +++ b/configs/mx6sabresd_defconfig @@ -32,7 +32,6 @@ CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev};if mmc rescan; then if run loa CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y CONFIG_SPL_LEGACY_IMAGE_SUPPORT=y -CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_FIT_IMAGE_TINY=y CONFIG_SPL_USB_HOST=y CONFIG_SPL_USB_GADGET=y diff --git a/configs/omap35_logic_defconfig b/configs/omap35_logic_defconfig index 1da37e7..d6ca3c2 100644 --- a/configs/omap35_logic_defconfig +++ b/configs/omap35_logic_defconfig @@ -21,7 +21,6 @@ CONFIG_PREBOOT="setenv preboot;saveenv;" CONFIG_DEFAULT_FDT_FILE="logicpd-torpedo-35xx-devkit.dtb" CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y -CONFIG_SPL_SEPARATE_BSS=y # CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set # CONFIG_SPL_FS_EXT4 is not set # CONFIG_SPL_I2C is not set diff --git a/configs/omap35_logic_somlv_defconfig b/configs/omap35_logic_somlv_defconfig index 89154cd..34b3af8 100644 --- a/configs/omap35_logic_somlv_defconfig +++ b/configs/omap35_logic_somlv_defconfig @@ -22,7 +22,6 @@ CONFIG_PREBOOT="setenv preboot;saveenv;" CONFIG_DEFAULT_FDT_FILE="logicpd-som-lv-35xx-devkit.dtb" CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y -CONFIG_SPL_SEPARATE_BSS=y # CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set # CONFIG_SPL_FS_EXT4 is not set # CONFIG_SPL_I2C is not set diff --git a/configs/omap3_beagle_defconfig b/configs/omap3_beagle_defconfig index c7111f4..4767c0b 100644 --- a/configs/omap3_beagle_defconfig +++ b/configs/omap3_beagle_defconfig @@ -15,7 +15,6 @@ CONFIG_USE_PREBOOT=y CONFIG_DEFAULT_FDT_FILE="omap3-beagle.dtb" CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y -CONFIG_SPL_SEPARATE_BSS=y # CONFIG_SPL_FS_EXT4 is not set CONFIG_SPL_MTD_SUPPORT=y CONFIG_SPL_NAND_DRIVERS=y diff --git a/configs/omap3_evm_defconfig b/configs/omap3_evm_defconfig index b89ab39..d451e20 100644 --- a/configs/omap3_evm_defconfig +++ b/configs/omap3_evm_defconfig @@ -15,7 +15,6 @@ CONFIG_USE_PREBOOT=y CONFIG_DEFAULT_FDT_FILE="omap3-evm.dtb" CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y -CONFIG_SPL_SEPARATE_BSS=y # CONFIG_SPL_FS_EXT4 is not set CONFIG_SPL_MTD_SUPPORT=y CONFIG_SPL_NAND_DRIVERS=y diff --git a/configs/omap3_logic_defconfig b/configs/omap3_logic_defconfig index a13bdeb..2397ba5 100644 --- a/configs/omap3_logic_defconfig +++ b/configs/omap3_logic_defconfig @@ -20,7 +20,6 @@ CONFIG_USE_PREBOOT=y CONFIG_PREBOOT="setenv preboot;saveenv;" CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y -CONFIG_SPL_SEPARATE_BSS=y # CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set # CONFIG_SPL_FS_EXT4 is not set # CONFIG_SPL_I2C is not set diff --git a/configs/omap3_logic_somlv_defconfig b/configs/omap3_logic_somlv_defconfig index c663162..721516d 100644 --- a/configs/omap3_logic_somlv_defconfig +++ b/configs/omap3_logic_somlv_defconfig @@ -22,7 +22,6 @@ CONFIG_PREBOOT="setenv preboot;saveenv;" CONFIG_DEFAULT_FDT_FILE="logicpd-som-lv-37xx-devkit.dtb" CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y -CONFIG_SPL_SEPARATE_BSS=y # CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set # CONFIG_SPL_FS_EXT4 is not set # CONFIG_SPL_I2C is not set diff --git a/configs/omapl138_lcdk_defconfig b/configs/omapl138_lcdk_defconfig index 73bba9f..799dc40 100644 --- a/configs/omapl138_lcdk_defconfig +++ b/configs/omapl138_lcdk_defconfig @@ -32,7 +32,6 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_CLOCKS=y CONFIG_MISC_INIT_R=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y -CONFIG_SPL_SEPARATE_BSS=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xb5 CONFIG_SPL_NAND_SUPPORT=y CONFIG_SPL_NAND_DRIVERS=y diff --git a/configs/openpiton_riscv64_spl_defconfig b/configs/openpiton_riscv64_spl_defconfig index 4ea4db9..cbcbe42 100644 --- a/configs/openpiton_riscv64_spl_defconfig +++ b/configs/openpiton_riscv64_spl_defconfig @@ -22,7 +22,6 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="fdt addr ${fdtcontroladdr}; fdt move ${fdtcontroladdr} ${fdt_addr_r}; load mmc ${mmcdev}:${mmcpart} ${kernel_addr_r} ${image}; booti ${kernel_addr_r} - ${fdt_addr_r}; " # CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set CONFIG_SPL_SYS_MALLOC_SIMPLE=y -CONFIG_SPL_SEPARATE_BSS=y # CONFIG_SPL_BANNER_PRINT is not set CONFIG_SPL_CPU=y CONFIG_SPL_FS_EXT4=y diff --git a/configs/pcm058_defconfig b/configs/pcm058_defconfig index b30270a..8b6a8b3 100644 --- a/configs/pcm058_defconfig +++ b/configs/pcm058_defconfig @@ -30,7 +30,6 @@ CONFIG_BOOTDELAY=3 CONFIG_BOOTCOMMAND="run mmcboot;run nandboot" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_BOARD_INIT=y -CONFIG_SPL_SEPARATE_BSS=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x18a CONFIG_SPL_DMA=y CONFIG_SPL_FS_EXT4=y diff --git a/configs/phycore-am335x-r2-regor_defconfig b/configs/phycore-am335x-r2-regor_defconfig index 9e35724..1344a23 100644 --- a/configs/phycore-am335x-r2-regor_defconfig +++ b/configs/phycore-am335x-r2-regor_defconfig @@ -22,7 +22,6 @@ CONFIG_BOOTCOMMAND="run distro_bootcmd" CONFIG_DEFAULT_FDT_FILE="am335x-regor-rdk.dtb" CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_ARCH_MISC_INIT=y -CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_I2C=y CONFIG_SPL_MTD_SUPPORT=y CONFIG_SPL_NAND_DRIVERS=y diff --git a/configs/phycore-am335x-r2-wega_defconfig b/configs/phycore-am335x-r2-wega_defconfig index 10b5ffd..45ded51 100644 --- a/configs/phycore-am335x-r2-wega_defconfig +++ b/configs/phycore-am335x-r2-wega_defconfig @@ -22,7 +22,6 @@ CONFIG_BOOTCOMMAND="run distro_bootcmd" CONFIG_DEFAULT_FDT_FILE="am335x-wega-rdk.dtb" CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_ARCH_MISC_INIT=y -CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_I2C=y CONFIG_SPL_MTD_SUPPORT=y CONFIG_SPL_NAND_DRIVERS=y diff --git a/configs/phycore-imx8mm_defconfig b/configs/phycore-imx8mm_defconfig index 83ad5ec..ba5833f 100644 --- a/configs/phycore-imx8mm_defconfig +++ b/configs/phycore-imx8mm_defconfig @@ -27,7 +27,6 @@ CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadimage; the CONFIG_DEFAULT_FDT_FILE="oftree" CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_BOARD_INIT=y -CONFIG_SPL_SEPARATE_BSS=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_I2C=y diff --git a/configs/phycore-imx8mp_defconfig b/configs/phycore-imx8mp_defconfig index 1052ccb..86d0f4d 100644 --- a/configs/phycore-imx8mp_defconfig +++ b/configs/phycore-imx8mp_defconfig @@ -30,7 +30,6 @@ CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_BOOTROM_SUPPORT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y -CONFIG_SPL_SEPARATE_BSS=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_I2C=y diff --git a/configs/pico-imx6_defconfig b/configs/pico-imx6_defconfig index 0bd6613..5330556 100644 --- a/configs/pico-imx6_defconfig +++ b/configs/pico-imx6_defconfig @@ -27,7 +27,6 @@ CONFIG_SPL_LOAD_FIT=y CONFIG_BOOTCOMMAND="run default_boot" CONFIG_DEFAULT_FDT_FILE="ask" CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y -CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_FIT_IMAGE_TINY=y CONFIG_SPL_FS_EXT4=y CONFIG_SPL_USB_HOST=y diff --git a/configs/sifive_unleashed_defconfig b/configs/sifive_unleashed_defconfig index 49a913b..fe2227e 100644 --- a/configs/sifive_unleashed_defconfig +++ b/configs/sifive_unleashed_defconfig @@ -22,7 +22,6 @@ CONFIG_DEFAULT_FDT_FILE="sifive/hifive-unleashed-a00.dtb" CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y CONFIG_MISC_INIT_R=y -CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_DM_RESET=y CONFIG_SPL_SPI_LOAD=y diff --git a/configs/sifive_unmatched_defconfig b/configs/sifive_unmatched_defconfig index f0aeace..5d07084 100644 --- a/configs/sifive_unmatched_defconfig +++ b/configs/sifive_unmatched_defconfig @@ -26,7 +26,6 @@ CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_ID_EEPROM=y -CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_DM_RESET=y CONFIG_SPL_SPI_LOAD=y diff --git a/configs/verdin-imx8mm_defconfig b/configs/verdin-imx8mm_defconfig index 94ba1f5..46d4dd7 100644 --- a/configs/verdin-imx8mm_defconfig +++ b/configs/verdin-imx8mm_defconfig @@ -21,18 +21,18 @@ CONFIG_SYS_MEMTEST_END=0x80000000 CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y CONFIG_FIT_EXTERNAL_OFFSET=0x3000 +CONFIG_FIT_VERBOSE=y CONFIG_SPL_LOAD_FIT=y # CONFIG_USE_SPL_FIT_GENERATOR is not set CONFIG_OF_SYSTEM_SETUP=y # CONFIG_USE_BOOTCOMMAND is not set CONFIG_USE_PREBOOT=y -CONFIG_PREBOOT="setenv fdtfile imx8mm-verdin-${variant}-${fdt_board}.dtb" +CONFIG_PREBOOT="test -n ${fdtfile} || setenv fdtfile imx8mm-verdin-${variant}-${fdt_board}.dtb" CONFIG_LOG=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_BOARD_INIT=y -CONFIG_SPL_SEPARATE_BSS=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_I2C=y diff --git a/configs/verdin-imx8mp_defconfig b/configs/verdin-imx8mp_defconfig index 44fcfa1..4b7cf74 100644 --- a/configs/verdin-imx8mp_defconfig +++ b/configs/verdin-imx8mp_defconfig @@ -34,7 +34,7 @@ CONFIG_SPL_LOAD_FIT=y CONFIG_OF_SYSTEM_SETUP=y CONFIG_BOOTDELAY=1 CONFIG_USE_PREBOOT=y -CONFIG_PREBOOT="setenv fdtfile imx8mp-verdin-${variant}-${fdt_board}.dtb" +CONFIG_PREBOOT="test -n ${fdtfile} || setenv fdtfile imx8mp-verdin-${variant}-${fdt_board}.dtb" CONFIG_LOG=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y @@ -43,7 +43,6 @@ CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_BOOTROM_SUPPORT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y -CONFIG_SPL_SEPARATE_BSS=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_I2C=y diff --git a/configs/wandboard_defconfig b/configs/wandboard_defconfig index 90fce5a..569b587 100644 --- a/configs/wandboard_defconfig +++ b/configs/wandboard_defconfig @@ -33,7 +33,6 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_FIT_IMAGE_TINY=y CONFIG_SPL_FS_EXT4=y CONFIG_SPL_I2C=y diff --git a/doc/board/nxp/imx8mn_evk.rst b/doc/board/nxp/imx8mn_evk.rst index 711545a..c45bb7b 100644 --- a/doc/board/nxp/imx8mn_evk.rst +++ b/doc/board/nxp/imx8mn_evk.rst @@ -42,7 +42,6 @@ Build U-Boot $ export CROSS_COMPILE=aarch64-poky-linux- $ make imx8mn_ddr4_evk_defconfig - $ export ATF_LOAD_ADDR=0x960000 $ make Burn the flash.bin to MicroSD card offset 32KB: diff --git a/doc/board/toradex/apalis-imx8x.rst b/doc/board/toradex/apalis-imx8x.rst deleted file mode 100644 index e62578b..0000000 --- a/doc/board/toradex/apalis-imx8x.rst +++ /dev/null @@ -1,77 +0,0 @@ -.. SPDX-License-Identifier: GPL-2.0+ - -Apalis iMX8X V1.1A Module (SoC NXP i.MX8QXP RevB) -================================================= - -Quick Start ------------ - -- Get and Build the ARM trusted firmware -- Get System Controller firmware -- Get SECO container -- Build U-Boot -- Load U-Boot binary using uuu -- Flash U-Boot binary into the eMMC -- Boot - -Note: builddir is U-Boot build directory (source directory for in-tree builds) - -Get and Build the ARM Trusted Firmware --------------------------------------- - -.. code-block:: bash - - $ cd $(builddir) - $ git clone -b toradex_imx_5.4.70_2.3.0 http://git.toradex.com/cgit/imx-atf.git - $ make PLAT=imx8qx bl31 -C imx-atf - $ cp imx-atf/build/imx8qx/release/bl31.bin $(builddir) - -Get System Controller firmware ---------------------------------------- - -.. code-block:: bash - - $ wget https://github.com/toradex/i.MX-System-Controller-Firmware/raw/master/src/scfw_export_mx8qx_b0/build_mx8qx_b0/mx8qx-apalis-scfw-tcm.bin - -Get SECO container ---------------------------------------- - -.. code-block:: bash - - $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/imx-seco-3.7.4.bin - $ sh imx-seco-3.7.4.bin - $ cp imx-seco-3.7.4/firmware/seco/mx8qxb0-ahab-container.img $(builddir)/mx8qx-ahab-container.img - -Build U-Boot ------------- -.. code-block:: bash - - $ make apalis-imx8x_defconfig - $ make u-boot-dtb.imx - -Load the U-Boot Binary Using UUU --------------------------------- - -Get the latest version of the universal update utility (uuu) aka ``mfgtools 3.0``: - -https://community.nxp.com/external-link.jspa?url=https%3A%2F%2Fgithub.com%2FNXPmicro%2Fmfgtools%2Freleases - -Put the module into USB recovery aka serial downloader mode, connect USB device -to your host and execute uuu: - -.. code-block:: bash - - sudo ./uuu $(builddir)/u-boot-dtb.imx - -Flash the U-Boot Binary into the eMMC -------------------------------------- - -Burn the ``u-boot-dtb.imx`` binary to the primary eMMC hardware boot area -partition and boot: - -.. code-block:: bash - - load mmc 1:1 $loadaddr u-boot-dtb.imx - setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt ${blkcnt} / 0x200 - mmc dev 0 1 - mmc write ${loadaddr} 0x0 ${blkcnt} diff --git a/doc/board/toradex/index.rst b/doc/board/toradex/index.rst index 1cd926a..ead5efb 100644 --- a/doc/board/toradex/index.rst +++ b/doc/board/toradex/index.rst @@ -7,7 +7,6 @@ Toradex :maxdepth: 2 apalis-imx8 - apalis-imx8x colibri_imx7 colibri-imx8x verdin-imx8mm diff --git a/doc/device-tree-bindings/watchdog/common.txt b/doc/device-tree-bindings/watchdog/common.txt new file mode 100644 index 0000000..9db6dd6 --- /dev/null +++ b/doc/device-tree-bindings/watchdog/common.txt @@ -0,0 +1,12 @@ +Common watchdog properties. + +Optional properties: +- timeout-sec : Timeout of the watchdog in seconds + If this timeout is not defined, the value of WATCHDOG_TIMEOUT_MSECS will + be used instead. +- hw_margin_ms : Period used to reset the watchdog in ms + If this period is not defined, the default value is 1000. +- u-boot,noautostart : Specify that this watchdog should not autostart + When the config option WATCHDOG_AUTOSTART is set, all enabled + watchdogs are started. This property allows specifying that this + watchdog should NOT be started. diff --git a/drivers/crypto/fsl/fsl_blob.c b/drivers/crypto/fsl/fsl_blob.c index e8202cc..9b6e4bc 100644 --- a/drivers/crypto/fsl/fsl_blob.c +++ b/drivers/crypto/fsl/fsl_blob.c @@ -71,6 +71,10 @@ int blob_decap(u8 *key_mod, u8 *src, u8 *dst, u32 len) ret = run_descriptor_jr(desc); if (ret) { + /* clear the blob data output buffer */ + memset(dst, 0x00, len); + size = ALIGN(len, ARCH_DMA_MINALIGN); + flush_dcache_range((unsigned long)dst, (unsigned long)dst + size); printf("Error in blob decapsulation: %d\n", ret); } else { size = ALIGN(len, ARCH_DMA_MINALIGN); diff --git a/drivers/crypto/fsl/fsl_hash.c b/drivers/crypto/fsl/fsl_hash.c index 2379b70..a52c4ac 100644 --- a/drivers/crypto/fsl/fsl_hash.c +++ b/drivers/crypto/fsl/fsl_hash.c @@ -168,18 +168,18 @@ int caam_hash(const unsigned char *pbuf, unsigned int buf_len, uint32_t *desc; unsigned int size; - desc = malloc_cache_aligned(sizeof(int) * MAX_CAAM_DESCSIZE); - if (!desc) { - debug("Not enough memory for descriptor allocation\n"); - return -ENOMEM; - } - if (!IS_ALIGNED((uintptr_t)pbuf, ARCH_DMA_MINALIGN) || !IS_ALIGNED((uintptr_t)pout, ARCH_DMA_MINALIGN)) { puts("Error: Address arguments are not aligned\n"); return -EINVAL; } + desc = malloc_cache_aligned(sizeof(int) * MAX_CAAM_DESCSIZE); + if (!desc) { + debug("Not enough memory for descriptor allocation\n"); + return -ENOMEM; + } + size = ALIGN(buf_len, ARCH_DMA_MINALIGN); flush_dcache_range((unsigned long)pbuf, (unsigned long)pbuf + size); @@ -190,6 +190,8 @@ int caam_hash(const unsigned char *pbuf, unsigned int buf_len, size = ALIGN(sizeof(int) * MAX_CAAM_DESCSIZE, ARCH_DMA_MINALIGN); flush_dcache_range((unsigned long)desc, (unsigned long)desc + size); + size = ALIGN(driver_hash[algo].digestsize, ARCH_DMA_MINALIGN); + invalidate_dcache_range((unsigned long)pout, (unsigned long)pout + size); ret = run_descriptor_jr(desc); diff --git a/drivers/pci/pcie_imx.c b/drivers/pci/pcie_imx.c index 2cec390..46ac017 100644 --- a/drivers/pci/pcie_imx.c +++ b/drivers/pci/pcie_imx.c @@ -14,6 +14,7 @@ #include <log.h> #include <malloc.h> #include <pci.h> +#include <power/regulator.h> #include <asm/arch/clock.h> #include <asm/arch/iomux.h> #include <asm/arch/crm_regs.h> @@ -102,6 +103,7 @@ struct imx_pcie_priv { void __iomem *cfg_base; struct gpio_desc reset_gpio; bool reset_active_high; + struct udevice *vpcie; }; /* @@ -530,7 +532,7 @@ static int imx6_pcie_init_phy(void) return 0; } -__weak int imx6_pcie_toggle_power(void) +int imx6_pcie_toggle_power(struct udevice *vpcie) { #ifdef CONFIG_PCIE_IMX_POWER_GPIO gpio_request(CONFIG_PCIE_IMX_POWER_GPIO, "pcie_power"); @@ -540,10 +542,19 @@ __weak int imx6_pcie_toggle_power(void) mdelay(20); gpio_free(CONFIG_PCIE_IMX_POWER_GPIO); #endif + +#if CONFIG_IS_ENABLED(DM_REGULATOR) + if (vpcie) { + regulator_set_enable(vpcie, false); + mdelay(20); + regulator_set_enable(vpcie, true); + mdelay(20); + } +#endif return 0; } -__weak int imx6_pcie_toggle_reset(struct gpio_desc *gpio, bool active_high) +int imx6_pcie_toggle_reset(struct gpio_desc *gpio, bool active_high) { /* * See 'PCI EXPRESS BASE SPECIFICATION, REV 3.0, SECTION 6.6.1' @@ -559,12 +570,6 @@ __weak int imx6_pcie_toggle_reset(struct gpio_desc *gpio, bool active_high) * configuration file and the condition below will handle the rest * of the reset toggling. * - * In case your #PERST toggling logic is more complex, for example - * connected via CPLD or somesuch, you can override this function - * in your board file and implement reset logic as needed. You must - * not forget to wait at least 20 ms after de-asserting #PERST in - * this case either though. - * * In case your #PERST line of the PCIe EP device is not connected * at all, your design is broken and you should fix your design, * otherwise you will observe problems like for example the link @@ -598,7 +603,7 @@ static int imx6_pcie_deassert_core_reset(struct imx_pcie_priv *priv) { struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; - imx6_pcie_toggle_power(); + imx6_pcie_toggle_power(priv->vpcie); enable_pcie_clock(); @@ -717,6 +722,10 @@ static int imx_pcie_dm_probe(struct udevice *dev) { struct imx_pcie_priv *priv = dev_get_priv(dev); +#if CONFIG_IS_ENABLED(DM_REGULATOR) + device_get_supply_regulator(dev, "vpcie-supply", &priv->vpcie); +#endif + /* if PERST# valid from dt then assert it */ gpio_request_by_name(dev, "reset-gpio", 0, &priv->reset_gpio, GPIOD_IS_OUT); diff --git a/drivers/power/domain/Kconfig b/drivers/power/domain/Kconfig index 93d2599..7e1b8c0 100644 --- a/drivers/power/domain/Kconfig +++ b/drivers/power/domain/Kconfig @@ -35,10 +35,18 @@ config IMX8_POWER_DOMAIN config IMX8M_POWER_DOMAIN bool "Enable i.MX8M power domain driver" depends on POWER_DOMAIN && ARCH_IMX8M + select CLK help Enable support for manipulating NXP i.MX8M on-SoC power domains via requests to the ATF. +config IMX8MP_HSIOMIX_BLKCTRL + bool "Enable i.MX8MP HSIOMIX domain driver" + depends on POWER_DOMAIN && IMX8MP + select CLK + help + Enable support for manipulating NXP i.MX8MP on-SoC HSIOMIX block controller. + config MTK_POWER_DOMAIN bool "Enable the MediaTek power domain driver" depends on POWER_DOMAIN && ARCH_MEDIATEK diff --git a/drivers/power/domain/Makefile b/drivers/power/domain/Makefile index 7c8af67..e624477 100644 --- a/drivers/power/domain/Makefile +++ b/drivers/power/domain/Makefile @@ -8,6 +8,7 @@ obj-$(CONFIG_APPLE_PMGR_POWER_DOMAIN) += apple-pmgr.o obj-$(CONFIG_BCM6328_POWER_DOMAIN) += bcm6328-power-domain.o obj-$(CONFIG_IMX8_POWER_DOMAIN) += imx8-power-domain-legacy.o imx8-power-domain.o obj-$(CONFIG_IMX8M_POWER_DOMAIN) += imx8m-power-domain.o +obj-$(CONFIG_IMX8MP_HSIOMIX_BLKCTRL) += imx8mp-hsiomix.o obj-$(CONFIG_MTK_POWER_DOMAIN) += mtk-power-domain.o obj-$(CONFIG_MESON_GX_VPU_POWER_DOMAIN) += meson-gx-pwrc-vpu.o obj-$(CONFIG_MESON_EE_POWER_DOMAIN) += meson-ee-pwrc.o diff --git a/drivers/power/domain/apple-pmgr.c b/drivers/power/domain/apple-pmgr.c index 4d06e76..402c5b1 100644 --- a/drivers/power/domain/apple-pmgr.c +++ b/drivers/power/domain/apple-pmgr.c @@ -42,16 +42,6 @@ static int apple_reset_of_xlate(struct reset_ctl *reset_ctl, return 0; } -static int apple_reset_request(struct reset_ctl *reset_ctl) -{ - return 0; -} - -static int apple_reset_free(struct reset_ctl *reset_ctl) -{ - return 0; -} - static int apple_reset_assert(struct reset_ctl *reset_ctl) { struct apple_pmgr_priv *priv = dev_get_priv(reset_ctl->dev->parent); @@ -80,8 +70,6 @@ static int apple_reset_deassert(struct reset_ctl *reset_ctl) struct reset_ops apple_reset_ops = { .of_xlate = apple_reset_of_xlate, - .request = apple_reset_request, - .rfree = apple_reset_free, .rst_assert = apple_reset_assert, .rst_deassert = apple_reset_deassert, }; @@ -92,16 +80,6 @@ static struct driver apple_reset_driver = { .ops = &apple_reset_ops, }; -static int apple_pmgr_request(struct power_domain *power_domain) -{ - return 0; -} - -static int apple_pmgr_rfree(struct power_domain *power_domain) -{ - return 0; -} - static int apple_pmgr_ps_set(struct power_domain *power_domain, u32 pstate) { struct apple_pmgr_priv *priv = dev_get_priv(power_domain->dev); @@ -121,11 +99,6 @@ static int apple_pmgr_on(struct power_domain *power_domain) return apple_pmgr_ps_set(power_domain, APPLE_PMGR_PS_ACTIVE); } -static int apple_pmgr_off(struct power_domain *power_domain) -{ - return 0; -} - static int apple_pmgr_of_xlate(struct power_domain *power_domain, struct ofnode_phandle_args *args) { @@ -167,10 +140,7 @@ static int apple_pmgr_probe(struct udevice *dev) } struct power_domain_ops apple_pmgr_ops = { - .request = apple_pmgr_request, - .rfree = apple_pmgr_rfree, .on = apple_pmgr_on, - .off = apple_pmgr_off, .of_xlate = apple_pmgr_of_xlate, }; diff --git a/drivers/power/domain/bcm6328-power-domain.c b/drivers/power/domain/bcm6328-power-domain.c index 6e720e0..80144dd 100644 --- a/drivers/power/domain/bcm6328-power-domain.c +++ b/drivers/power/domain/bcm6328-power-domain.c @@ -24,11 +24,6 @@ static int bcm6328_power_domain_request(struct power_domain *power_domain) return 0; } -static int bcm6328_power_domain_free(struct power_domain *power_domain) -{ - return 0; -} - static int bcm6328_power_domain_on(struct power_domain *power_domain) { struct bcm6328_power_domain *priv = dev_get_priv(power_domain->dev); @@ -64,7 +59,6 @@ static const struct udevice_id bcm6328_power_domain_ids[] = { }; struct power_domain_ops bcm6328_power_domain_ops = { - .rfree = bcm6328_power_domain_free, .off = bcm6328_power_domain_off, .on = bcm6328_power_domain_on, .request = bcm6328_power_domain_request, diff --git a/drivers/power/domain/imx8-power-domain-legacy.c b/drivers/power/domain/imx8-power-domain-legacy.c index e2fae2d..bf45891 100644 --- a/drivers/power/domain/imx8-power-domain-legacy.c +++ b/drivers/power/domain/imx8-power-domain-legacy.c @@ -84,20 +84,6 @@ int imx8_power_domain_lookup_name(const char *name, return 0; } -static int imx8_power_domain_request(struct power_domain *power_domain) -{ - debug("%s(power_domain=%p)\n", __func__, power_domain); - - return 0; -} - -static int imx8_power_domain_free(struct power_domain *power_domain) -{ - debug("%s(power_domain=%p)\n", __func__, power_domain); - - return 0; -} - static int imx8_power_domain_on(struct power_domain *power_domain) { struct udevice *dev = power_domain->dev; @@ -364,8 +350,6 @@ static const struct udevice_id imx8_power_domain_ids[] = { }; struct power_domain_ops imx8_power_domain_ops = { - .request = imx8_power_domain_request, - .rfree = imx8_power_domain_free, .on = imx8_power_domain_on, .off = imx8_power_domain_off, .of_xlate = imx8_power_domain_of_xlate, diff --git a/drivers/power/domain/imx8-power-domain.c b/drivers/power/domain/imx8-power-domain.c index 6461ab2..17b5d57 100644 --- a/drivers/power/domain/imx8-power-domain.c +++ b/drivers/power/domain/imx8-power-domain.c @@ -12,20 +12,6 @@ #include <asm/arch/power-domain.h> #include <asm/arch/sci/sci.h> -static int imx8_power_domain_request(struct power_domain *power_domain) -{ - debug("%s(power_domain=%p)\n", __func__, power_domain); - - return 0; -} - -static int imx8_power_domain_free(struct power_domain *power_domain) -{ - debug("%s(power_domain=%p)\n", __func__, power_domain); - - return 0; -} - static int imx8_power_domain_on(struct power_domain *power_domain) { u32 resource_id = power_domain->id; @@ -60,13 +46,6 @@ static int imx8_power_domain_off(struct power_domain *power_domain) return 0; } -static int imx8_power_domain_probe(struct udevice *dev) -{ - debug("%s(dev=%s)\n", __func__, dev->name); - - return 0; -} - static const struct udevice_id imx8_power_domain_ids[] = { { .compatible = "fsl,imx8qxp-scu-pd" }, { .compatible = "fsl,scu-pd" }, @@ -74,8 +53,6 @@ static const struct udevice_id imx8_power_domain_ids[] = { }; struct power_domain_ops imx8_power_domain_ops_v2 = { - .request = imx8_power_domain_request, - .rfree = imx8_power_domain_free, .on = imx8_power_domain_on, .off = imx8_power_domain_off, }; @@ -84,6 +61,5 @@ U_BOOT_DRIVER(imx8_power_domain_v2) = { .name = "imx8_power_domain_v2", .id = UCLASS_POWER_DOMAIN, .of_match = imx8_power_domain_ids, - .probe = imx8_power_domain_probe, .ops = &imx8_power_domain_ops_v2, }; diff --git a/drivers/power/domain/imx8m-power-domain.c b/drivers/power/domain/imx8m-power-domain.c index 5d34bc1..145f6ec 100644 --- a/drivers/power/domain/imx8m-power-domain.c +++ b/drivers/power/domain/imx8m-power-domain.c @@ -4,65 +4,446 @@ */ #include <common.h> +#include <clk.h> #include <dm.h> #include <malloc.h> #include <power-domain-uclass.h> #include <asm/global_data.h> #include <asm/io.h> -#include <asm/arch/power-domain.h> #include <asm/mach-imx/sys_proto.h> #include <dm/device-internal.h> #include <dm/device.h> +#include <dm/device_compat.h> #include <imx_sip.h> -#include <linux/arm-smccc.h> +#include <linux/bitmap.h> +#include <wait_bit.h> + +#include <dt-bindings/power/imx8mm-power.h> +#include <dt-bindings/power/imx8mn-power.h> +#include <dt-bindings/power/imx8mp-power.h> +#include <dt-bindings/power/imx8mq-power.h> DECLARE_GLOBAL_DATA_PTR; -static int imx8m_power_domain_request(struct power_domain *power_domain) -{ - return 0; -} +#define GPC_PGC_CPU_MAPPING 0x0ec +#define IMX8MP_GPC_PGC_CPU_MAPPING 0x1cc -static int imx8m_power_domain_free(struct power_domain *power_domain) -{ - return 0; -} +#define IMX8M_PCIE2_A53_DOMAIN BIT(15) +#define IMX8M_OTG2_A53_DOMAIN BIT(5) +#define IMX8M_OTG1_A53_DOMAIN BIT(4) +#define IMX8M_PCIE1_A53_DOMAIN BIT(3) + +#define IMX8MM_OTG2_A53_DOMAIN BIT(5) +#define IMX8MM_OTG1_A53_DOMAIN BIT(4) +#define IMX8MM_PCIE_A53_DOMAIN BIT(3) + +#define IMX8MN_OTG1_A53_DOMAIN BIT(4) +#define IMX8MN_MIPI_A53_DOMAIN BIT(2) + +#define IMX8MP_HSIOMIX_A53_DOMAIN BIT(19) +#define IMX8MP_USB2_PHY_A53_DOMAIN BIT(5) +#define IMX8MP_USB1_PHY_A53_DOMAIN BIT(4) +#define IMX8MP_PCIE_PHY_A53_DOMAIN BIT(3) + +#define IMX8MP_GPC_PU_PGC_SW_PUP_REQ 0x0d8 +#define IMX8MP_GPC_PU_PGC_SW_PDN_REQ 0x0e4 + +#define GPC_PU_PGC_SW_PUP_REQ 0x0f8 +#define GPC_PU_PGC_SW_PDN_REQ 0x104 + +#define IMX8M_PCIE2_SW_Pxx_REQ BIT(13) +#define IMX8M_OTG2_SW_Pxx_REQ BIT(3) +#define IMX8M_OTG1_SW_Pxx_REQ BIT(2) +#define IMX8M_PCIE1_SW_Pxx_REQ BIT(1) + +#define IMX8MM_OTG2_SW_Pxx_REQ BIT(3) +#define IMX8MM_OTG1_SW_Pxx_REQ BIT(2) +#define IMX8MM_PCIE_SW_Pxx_REQ BIT(1) + +#define IMX8MN_OTG1_SW_Pxx_REQ BIT(2) +#define IMX8MN_MIPI_SW_Pxx_REQ BIT(0) + +#define IMX8MP_HSIOMIX_Pxx_REQ BIT(17) +#define IMX8MP_USB2_PHY_Pxx_REQ BIT(3) +#define IMX8MP_USB1_PHY_Pxx_REQ BIT(2) +#define IMX8MP_PCIE_PHY_SW_Pxx_REQ BIT(1) + +#define GPC_M4_PU_PDN_FLG 0x1bc + +#define IMX8MP_GPC_PU_PWRHSK 0x190 +#define GPC_PU_PWRHSK 0x1fc + +#define IMX8MM_HSIO_HSK_PWRDNACKN (BIT(23) | BIT(24)) +#define IMX8MM_HSIO_HSK_PWRDNREQN (BIT(5) | BIT(6)) + +#define IMX8MN_HSIO_HSK_PWRDNACKN BIT(23) +#define IMX8MN_HSIO_HSK_PWRDNREQN BIT(5) + +#define IMX8MP_HSIOMIX_PWRDNACKN BIT(28) +#define IMX8MP_HSIOMIX_PWRDNREQN BIT(12) + +/* + * The PGC offset values in Reference Manual + * (Rev. 1, 01/2018 and the older ones) GPC chapter's + * GPC_PGC memory map are incorrect, below offset + * values are from design RTL. + */ +#define IMX8M_PGC_PCIE1 17 +#define IMX8M_PGC_OTG1 18 +#define IMX8M_PGC_OTG2 19 +#define IMX8M_PGC_PCIE2 29 + +#define IMX8MM_PGC_PCIE 17 +#define IMX8MM_PGC_OTG1 18 +#define IMX8MM_PGC_OTG2 19 + +#define IMX8MN_PGC_OTG1 18 + +#define IMX8MP_PGC_PCIE 13 +#define IMX8MP_PGC_USB1 14 +#define IMX8MP_PGC_USB2 15 +#define IMX8MP_PGC_HSIOMIX 29 + +#define GPC_PGC_CTRL(n) (0x800 + (n) * 0x40) +#define GPC_PGC_SR(n) (GPC_PGC_CTRL(n) + 0xc) + +#define GPC_PGC_CTRL_PCR BIT(0) + +struct imx_pgc_regs { + u16 map; + u16 pup; + u16 pdn; + u16 hsk; +}; + +struct imx_pgc_domain { + unsigned long pgc; + + const struct { + u32 pxx; + u32 map; + u32 hskreq; + u32 hskack; + } bits; + + const bool keep_clocks; +}; + +struct imx_pgc_domain_data { + const struct imx_pgc_domain *domains; + size_t domains_num; + const struct imx_pgc_regs *pgc_regs; +}; + +struct imx8m_power_domain_plat { + struct power_domain pd; + const struct imx_pgc_domain *domain; + const struct imx_pgc_regs *regs; + struct clk_bulk clk; + void __iomem *base; + int resource_id; + int has_pd; +}; + +#if defined(CONFIG_IMX8MM) || defined(CONFIG_IMX8MN) || defined(CONFIG_IMX8MQ) +static const struct imx_pgc_regs imx7_pgc_regs = { + .map = GPC_PGC_CPU_MAPPING, + .pup = GPC_PU_PGC_SW_PUP_REQ, + .pdn = GPC_PU_PGC_SW_PDN_REQ, + .hsk = GPC_PU_PWRHSK, +}; +#endif + +#ifdef CONFIG_IMX8MQ +static const struct imx_pgc_domain imx8m_pgc_domains[] = { + [IMX8M_POWER_DOMAIN_PCIE1] = { + .bits = { + .pxx = IMX8M_PCIE1_SW_Pxx_REQ, + .map = IMX8M_PCIE1_A53_DOMAIN, + }, + .pgc = BIT(IMX8M_PGC_PCIE1), + }, + + [IMX8M_POWER_DOMAIN_USB_OTG1] = { + .bits = { + .pxx = IMX8M_OTG1_SW_Pxx_REQ, + .map = IMX8M_OTG1_A53_DOMAIN, + }, + .pgc = BIT(IMX8M_PGC_OTG1), + }, + + [IMX8M_POWER_DOMAIN_USB_OTG2] = { + .bits = { + .pxx = IMX8M_OTG2_SW_Pxx_REQ, + .map = IMX8M_OTG2_A53_DOMAIN, + }, + .pgc = BIT(IMX8M_PGC_OTG2), + }, + + [IMX8M_POWER_DOMAIN_PCIE2] = { + .bits = { + .pxx = IMX8M_PCIE2_SW_Pxx_REQ, + .map = IMX8M_PCIE2_A53_DOMAIN, + }, + .pgc = BIT(IMX8M_PGC_PCIE2), + }, +}; + +static const struct imx_pgc_domain_data imx8m_pgc_domain_data = { + .domains = imx8m_pgc_domains, + .domains_num = ARRAY_SIZE(imx8m_pgc_domains), + .pgc_regs = &imx7_pgc_regs, +}; +#endif + +#ifdef CONFIG_IMX8MM +static const struct imx_pgc_domain imx8mm_pgc_domains[] = { + [IMX8MM_POWER_DOMAIN_HSIOMIX] = { + .bits = { + .pxx = 0, /* no power sequence control */ + .map = 0, /* no power sequence control */ + .hskreq = IMX8MM_HSIO_HSK_PWRDNREQN, + .hskack = IMX8MM_HSIO_HSK_PWRDNACKN, + }, + .keep_clocks = true, + }, + + [IMX8MM_POWER_DOMAIN_PCIE] = { + .bits = { + .pxx = IMX8MM_PCIE_SW_Pxx_REQ, + .map = IMX8MM_PCIE_A53_DOMAIN, + }, + .pgc = BIT(IMX8MM_PGC_PCIE), + }, + + [IMX8MM_POWER_DOMAIN_OTG1] = { + .bits = { + .pxx = IMX8MM_OTG1_SW_Pxx_REQ, + .map = IMX8MM_OTG1_A53_DOMAIN, + }, + .pgc = BIT(IMX8MM_PGC_OTG1), + }, + + [IMX8MM_POWER_DOMAIN_OTG2] = { + .bits = { + .pxx = IMX8MM_OTG2_SW_Pxx_REQ, + .map = IMX8MM_OTG2_A53_DOMAIN, + }, + .pgc = BIT(IMX8MM_PGC_OTG2), + }, +}; + +static const struct imx_pgc_domain_data imx8mm_pgc_domain_data = { + .domains = imx8mm_pgc_domains, + .domains_num = ARRAY_SIZE(imx8mm_pgc_domains), + .pgc_regs = &imx7_pgc_regs, +}; +#endif + +#ifdef CONFIG_IMX8MN +static const struct imx_pgc_domain imx8mn_pgc_domains[] = { + [IMX8MN_POWER_DOMAIN_HSIOMIX] = { + .bits = { + .pxx = 0, /* no power sequence control */ + .map = 0, /* no power sequence control */ + .hskreq = IMX8MN_HSIO_HSK_PWRDNREQN, + .hskack = IMX8MN_HSIO_HSK_PWRDNACKN, + }, + .keep_clocks = true, + }, + + [IMX8MN_POWER_DOMAIN_OTG1] = { + .bits = { + .pxx = IMX8MN_OTG1_SW_Pxx_REQ, + .map = IMX8MN_OTG1_A53_DOMAIN, + }, + .pgc = BIT(IMX8MN_PGC_OTG1), + }, +}; + +static const struct imx_pgc_domain_data imx8mn_pgc_domain_data = { + .domains = imx8mn_pgc_domains, + .domains_num = ARRAY_SIZE(imx8mn_pgc_domains), + .pgc_regs = &imx7_pgc_regs, +}; +#endif + +#ifdef CONFIG_IMX8MP +static const struct imx_pgc_domain imx8mp_pgc_domains[] = { + [IMX8MP_POWER_DOMAIN_PCIE_PHY] = { + .bits = { + .pxx = IMX8MP_PCIE_PHY_SW_Pxx_REQ, + .map = IMX8MP_PCIE_PHY_A53_DOMAIN, + }, + .pgc = BIT(IMX8MP_PGC_PCIE), + }, + + [IMX8MP_POWER_DOMAIN_USB1_PHY] = { + .bits = { + .pxx = IMX8MP_USB1_PHY_Pxx_REQ, + .map = IMX8MP_USB1_PHY_A53_DOMAIN, + }, + .pgc = BIT(IMX8MP_PGC_USB1), + }, + + [IMX8MP_POWER_DOMAIN_USB2_PHY] = { + .bits = { + .pxx = IMX8MP_USB2_PHY_Pxx_REQ, + .map = IMX8MP_USB2_PHY_A53_DOMAIN, + }, + .pgc = BIT(IMX8MP_PGC_USB2), + }, + + [IMX8MP_POWER_DOMAIN_HSIOMIX] = { + .bits = { + .pxx = IMX8MP_HSIOMIX_Pxx_REQ, + .map = IMX8MP_HSIOMIX_A53_DOMAIN, + .hskreq = IMX8MP_HSIOMIX_PWRDNREQN, + .hskack = IMX8MP_HSIOMIX_PWRDNACKN, + }, + .pgc = BIT(IMX8MP_PGC_HSIOMIX), + .keep_clocks = true, + }, +}; + +static const struct imx_pgc_regs imx8mp_pgc_regs = { + .map = IMX8MP_GPC_PGC_CPU_MAPPING, + .pup = IMX8MP_GPC_PU_PGC_SW_PUP_REQ, + .pdn = IMX8MP_GPC_PU_PGC_SW_PDN_REQ, + .hsk = IMX8MP_GPC_PU_PWRHSK, +}; + +static const struct imx_pgc_domain_data imx8mp_pgc_domain_data = { + .domains = imx8mp_pgc_domains, + .domains_num = ARRAY_SIZE(imx8mp_pgc_domains), + .pgc_regs = &imx8mp_pgc_regs, +}; +#endif static int imx8m_power_domain_on(struct power_domain *power_domain) { struct udevice *dev = power_domain->dev; - struct imx8m_power_domain_plat *pdata; + struct imx8m_power_domain_plat *pdata = dev_get_plat(dev); + const struct imx_pgc_domain *domain = pdata->domain; + const struct imx_pgc_regs *regs = pdata->regs; + void __iomem *base = pdata->base; + u32 pgc; + int ret; - pdata = dev_get_plat(dev); + if (pdata->clk.count) { + ret = clk_enable_bulk(&pdata->clk); + if (ret) { + dev_err(dev, "failed to enable reset clocks\n"); + return ret; + } + } - if (pdata->resource_id < 0) - return -EINVAL; + if (domain->bits.pxx) { + /* request the domain to power up */ + setbits_le32(base + regs->pup, domain->bits.pxx); - if (pdata->has_pd) - power_domain_on(&pdata->pd); + /* + * As per "5.5.9.4 Example Code 4" in IMX7DRM.pdf wait + * for PUP_REQ/PDN_REQ bit to be cleared + */ + ret = wait_for_bit_le32(base + regs->pup, domain->bits.pxx, + false, 1000, false); + if (ret) { + dev_err(dev, "failed to command PGC\n"); + goto out_clk_disable; + } - arm_smccc_smc(IMX_SIP_GPC, IMX_SIP_GPC_PM_DOMAIN, - pdata->resource_id, 1, 0, 0, 0, 0, NULL); + /* disable power control */ + for_each_set_bit(pgc, &domain->pgc, 32) { + clrbits_le32(base + GPC_PGC_CTRL(pgc), + GPC_PGC_CTRL_PCR); + } + } + + /* delay for reset to propagate */ + udelay(5); + + /* request the ADB400 to power up */ + if (domain->bits.hskreq) + setbits_le32(base + regs->hsk, domain->bits.hskreq); + + /* Disable reset clocks for all devices in the domain */ + if (!domain->keep_clocks && pdata->clk.count) + clk_disable_bulk(&pdata->clk); return 0; + +out_clk_disable: + if (pdata->clk.count) + clk_disable_bulk(&pdata->clk); + return ret; } static int imx8m_power_domain_off(struct power_domain *power_domain) { struct udevice *dev = power_domain->dev; - struct imx8m_power_domain_plat *pdata; - pdata = dev_get_plat(dev); + struct imx8m_power_domain_plat *pdata = dev_get_plat(dev); + const struct imx_pgc_domain *domain = pdata->domain; + const struct imx_pgc_regs *regs = pdata->regs; + void __iomem *base = pdata->base; + u32 pgc; + int ret; + + /* Enable reset clocks for all devices in the domain */ + if (!domain->keep_clocks && pdata->clk.count) { + ret = clk_enable_bulk(&pdata->clk); + if (ret) + return ret; + } + + /* request the ADB400 to power down */ + if (domain->bits.hskreq) { + clrbits_le32(base + regs->hsk, domain->bits.hskreq); + + ret = wait_for_bit_le32(base + regs->hsk, domain->bits.hskack, + false, 1000, false); + if (ret) { + dev_err(dev, "failed to power down ADB400\n"); + goto out_clk_disable; + } + } - if (pdata->resource_id < 0) - return -EINVAL; + if (domain->bits.pxx) { + /* enable power control */ + for_each_set_bit(pgc, &domain->pgc, 32) { + setbits_le32(base + GPC_PGC_CTRL(pgc), + GPC_PGC_CTRL_PCR); + } - arm_smccc_smc(IMX_SIP_GPC, IMX_SIP_GPC_PM_DOMAIN, - pdata->resource_id, 0, 0, 0, 0, 0, NULL); + /* request the domain to power down */ + setbits_le32(base + regs->pdn, domain->bits.pxx); + + /* + * As per "5.5.9.4 Example Code 4" in IMX7DRM.pdf wait + * for PUP_REQ/PDN_REQ bit to be cleared + */ + ret = wait_for_bit_le32(base + regs->pdn, domain->bits.pxx, + false, 1000, false); + if (ret) { + dev_err(dev, "failed to command PGC\n"); + goto out_clk_disable; + } + } + + /* Disable reset clocks for all devices in the domain */ + if (pdata->clk.count) + clk_disable_bulk(&pdata->clk); if (pdata->has_pd) power_domain_off(&pdata->pd); return 0; + +out_clk_disable: + if (!domain->keep_clocks && pdata->clk.count) + clk_disable_bulk(&pdata->clk); + + return ret; } static int imx8m_power_domain_of_xlate(struct power_domain *power_domain, @@ -83,6 +464,12 @@ static int imx8m_power_domain_bind(struct udevice *dev) /* Bind the subnode to this driver */ name = fdt_get_name(gd->fdt_blob, offset, NULL); + /* Descend into 'pgc' subnode */ + if (!strstr(name, "power-domain")) { + offset = fdt_first_subnode(gd->fdt_blob, offset); + name = fdt_get_name(gd->fdt_blob, offset, NULL); + } + ret = device_bind_with_driver_data(dev, dev->driver, name, dev->driver_data, offset_to_ofnode(offset), @@ -102,15 +489,34 @@ static int imx8m_power_domain_bind(struct udevice *dev) static int imx8m_power_domain_probe(struct udevice *dev) { + struct imx8m_power_domain_plat *pdata = dev_get_plat(dev); + int ret; + + /* Nothing to do for non-"power-domain" driver instances. */ + if (!strstr(dev->name, "power-domain")) + return 0; + + /* Grab optional power domain clock. */ + ret = clk_get_bulk(dev, &pdata->clk); + if (ret && ret != -ENOENT) { + dev_err(dev, "Failed to get domain clock (%d)\n", ret); + return ret; + } + return 0; } static int imx8m_power_domain_of_to_plat(struct udevice *dev) { struct imx8m_power_domain_plat *pdata = dev_get_plat(dev); + struct imx_pgc_domain_data *domain_data = + (struct imx_pgc_domain_data *)dev_get_driver_data(dev); pdata->resource_id = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "reg", -1); + pdata->domain = &domain_data->domains[pdata->resource_id]; + pdata->regs = domain_data->pgc_regs; + pdata->base = dev_read_addr_ptr(dev->parent); if (!power_domain_get(dev, &pdata->pd)) pdata->has_pd = 1; @@ -119,15 +525,22 @@ static int imx8m_power_domain_of_to_plat(struct udevice *dev) } static const struct udevice_id imx8m_power_domain_ids[] = { - { .compatible = "fsl,imx8mq-gpc" }, - { .compatible = "fsl,imx8mm-gpc" }, - { .compatible = "fsl,imx8mn-gpc" }, +#ifdef CONFIG_IMX8MQ + { .compatible = "fsl,imx8mq-gpc", .data = (long)&imx8m_pgc_domain_data }, +#endif +#ifdef CONFIG_IMX8MM + { .compatible = "fsl,imx8mm-gpc", .data = (long)&imx8mm_pgc_domain_data }, +#endif +#ifdef CONFIG_IMX8MN + { .compatible = "fsl,imx8mn-gpc", .data = (long)&imx8mn_pgc_domain_data }, +#endif +#ifdef CONFIG_IMX8MP + { .compatible = "fsl,imx8mp-gpc", .data = (long)&imx8mp_pgc_domain_data }, +#endif { } }; struct power_domain_ops imx8m_power_domain_ops = { - .request = imx8m_power_domain_request, - .rfree = imx8m_power_domain_free, .on = imx8m_power_domain_on, .off = imx8m_power_domain_off, .of_xlate = imx8m_power_domain_of_xlate, diff --git a/drivers/power/domain/imx8mp-hsiomix.c b/drivers/power/domain/imx8mp-hsiomix.c new file mode 100644 index 0000000..6a721a9 --- /dev/null +++ b/drivers/power/domain/imx8mp-hsiomix.c @@ -0,0 +1,159 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2022 Marek Vasut <marex@denx.de> + */ + +#include <common.h> +#include <asm/io.h> +#include <clk.h> +#include <dm.h> +#include <dm/device.h> +#include <dm/device_compat.h> +#include <power-domain-uclass.h> + +#include <dt-bindings/power/imx8mp-power.h> + +#define GPR_REG0 0x0 +#define PCIE_CLOCK_MODULE_EN BIT(0) +#define USB_CLOCK_MODULE_EN BIT(1) + +struct imx8mp_hsiomix_priv { + void __iomem *base; + struct clk clk_usb; + struct power_domain pd_bus; + struct power_domain pd_usb; + struct power_domain pd_usb_phy1; + struct power_domain pd_usb_phy2; +}; + +static int imx8mp_hsiomix_on(struct power_domain *power_domain) +{ + struct udevice *dev = power_domain->dev; + struct imx8mp_hsiomix_priv *priv = dev_get_priv(dev); + struct power_domain *domain; + int ret; + + ret = power_domain_on(&priv->pd_bus); + if (ret) + return ret; + + if (power_domain->id == IMX8MP_HSIOBLK_PD_USB) { + domain = &priv->pd_usb; + } else if (power_domain->id == IMX8MP_HSIOBLK_PD_USB_PHY1) { + domain = &priv->pd_usb_phy1; + } else if (power_domain->id == IMX8MP_HSIOBLK_PD_USB_PHY2) { + domain = &priv->pd_usb_phy2; + } else { + ret = -EINVAL; + goto err_pd; + } + + ret = power_domain_on(domain); + if (ret) + goto err_pd; + + ret = clk_enable(&priv->clk_usb); + if (ret) + goto err_clk; + + if (power_domain->id == IMX8MP_HSIOBLK_PD_USB) + setbits_le32(priv->base + GPR_REG0, USB_CLOCK_MODULE_EN); + + return 0; + +err_clk: + power_domain_off(domain); +err_pd: + power_domain_off(&priv->pd_bus); + return ret; +} + +static int imx8mp_hsiomix_off(struct power_domain *power_domain) +{ + struct udevice *dev = power_domain->dev; + struct imx8mp_hsiomix_priv *priv = dev_get_priv(dev); + + if (power_domain->id == IMX8MP_HSIOBLK_PD_USB) + clrbits_le32(priv->base + GPR_REG0, USB_CLOCK_MODULE_EN); + + clk_disable(&priv->clk_usb); + + if (power_domain->id == IMX8MP_HSIOBLK_PD_USB) + power_domain_off(&priv->pd_usb); + else if (power_domain->id == IMX8MP_HSIOBLK_PD_USB_PHY1) + power_domain_off(&priv->pd_usb_phy1); + else if (power_domain->id == IMX8MP_HSIOBLK_PD_USB_PHY2) + power_domain_off(&priv->pd_usb_phy2); + + power_domain_off(&priv->pd_bus); + + return 0; +} + +static int imx8mp_hsiomix_of_xlate(struct power_domain *power_domain, + struct ofnode_phandle_args *args) +{ + power_domain->id = args->args[0]; + + return 0; +} + +static int imx8mp_hsiomix_probe(struct udevice *dev) +{ + struct imx8mp_hsiomix_priv *priv = dev_get_priv(dev); + int ret; + + priv->base = dev_read_addr_ptr(dev); + + ret = clk_get_by_name(dev, "usb", &priv->clk_usb); + if (ret < 0) + return ret; + + ret = power_domain_get_by_name(dev, &priv->pd_bus, "bus"); + if (ret < 0) + goto err_pd_bus; + + ret = power_domain_get_by_name(dev, &priv->pd_usb, "usb"); + if (ret < 0) + goto err_pd_usb; + + ret = power_domain_get_by_name(dev, &priv->pd_usb_phy1, "usb-phy1"); + if (ret < 0) + goto err_pd_usb_phy1; + + ret = power_domain_get_by_name(dev, &priv->pd_usb_phy2, "usb-phy2"); + if (ret < 0) + goto err_pd_usb_phy2; + + return 0; + +err_pd_usb_phy2: + power_domain_free(&priv->pd_usb_phy1); +err_pd_usb_phy1: + power_domain_free(&priv->pd_usb); +err_pd_usb: + power_domain_free(&priv->pd_bus); +err_pd_bus: + clk_free(&priv->clk_usb); + return ret; +} + +static const struct udevice_id imx8mp_hsiomix_ids[] = { + { .compatible = "fsl,imx8mp-hsio-blk-ctrl" }, + { } +}; + +struct power_domain_ops imx8mp_hsiomix_ops = { + .on = imx8mp_hsiomix_on, + .off = imx8mp_hsiomix_off, + .of_xlate = imx8mp_hsiomix_of_xlate, +}; + +U_BOOT_DRIVER(imx8mp_hsiomix) = { + .name = "imx8mp_hsiomix", + .id = UCLASS_POWER_DOMAIN, + .of_match = imx8mp_hsiomix_ids, + .probe = imx8mp_hsiomix_probe, + .priv_auto = sizeof(struct imx8mp_hsiomix_priv), + .ops = &imx8mp_hsiomix_ops, +}; diff --git a/drivers/power/domain/meson-ee-pwrc.c b/drivers/power/domain/meson-ee-pwrc.c index a4d50e7..676fded 100644 --- a/drivers/power/domain/meson-ee-pwrc.c +++ b/drivers/power/domain/meson-ee-pwrc.c @@ -273,16 +273,6 @@ static bool pwrc_ee_get_power(struct power_domain *power_domain) return (reg & pwrc_domain->top_pd->sleep_mask); } -static int meson_ee_pwrc_request(struct power_domain *power_domain) -{ - return 0; -} - -static int meson_ee_pwrc_free(struct power_domain *power_domain) -{ - return 0; -} - static int meson_ee_pwrc_off(struct power_domain *power_domain) { struct meson_ee_pwrc_priv *priv = dev_get_priv(power_domain->dev); @@ -387,10 +377,8 @@ static int meson_ee_pwrc_of_xlate(struct power_domain *power_domain, } struct power_domain_ops meson_ee_pwrc_ops = { - .rfree = meson_ee_pwrc_free, .off = meson_ee_pwrc_off, .on = meson_ee_pwrc_on, - .request = meson_ee_pwrc_request, .of_xlate = meson_ee_pwrc_of_xlate, }; diff --git a/drivers/power/domain/meson-gx-pwrc-vpu.c b/drivers/power/domain/meson-gx-pwrc-vpu.c index eb94af2..612660c 100644 --- a/drivers/power/domain/meson-gx-pwrc-vpu.c +++ b/drivers/power/domain/meson-gx-pwrc-vpu.c @@ -45,16 +45,6 @@ struct meson_gx_pwrc_vpu_priv { struct clk_bulk clks; }; -static int meson_pwrc_vpu_request(struct power_domain *power_domain) -{ - return 0; -} - -static int meson_pwrc_vpu_free(struct power_domain *power_domain) -{ - return 0; -} - static int meson_gx_pwrc_vpu_on(struct power_domain *power_domain) { struct meson_gx_pwrc_vpu_priv *priv = dev_get_priv(power_domain->dev); @@ -274,10 +264,8 @@ static int meson_pwrc_vpu_of_xlate(struct power_domain *power_domain, } struct power_domain_ops meson_gx_pwrc_vpu_ops = { - .rfree = meson_pwrc_vpu_free, .off = meson_pwrc_vpu_off, .on = meson_pwrc_vpu_on, - .request = meson_pwrc_vpu_request, .of_xlate = meson_pwrc_vpu_of_xlate, }; diff --git a/drivers/power/domain/mtk-power-domain.c b/drivers/power/domain/mtk-power-domain.c index ca2ded0..3b84147 100644 --- a/drivers/power/domain/mtk-power-domain.c +++ b/drivers/power/domain/mtk-power-domain.c @@ -317,11 +317,6 @@ static int scpsys_power_request(struct power_domain *power_domain) return 0; } -static int scpsys_power_free(struct power_domain *power_domain) -{ - return 0; -} - static int mtk_power_domain_hook(struct udevice *dev) { struct scp_domain *scpd = dev_get_priv(dev); @@ -399,7 +394,6 @@ static const struct udevice_id mtk_power_domain_ids[] = { }; struct power_domain_ops mtk_power_domain_ops = { - .rfree = scpsys_power_free, .off = scpsys_power_off, .on = scpsys_power_on, .request = scpsys_power_request, diff --git a/drivers/power/domain/power-domain-uclass.c b/drivers/power/domain/power-domain-uclass.c index 33f9206..74c33d4 100644 --- a/drivers/power/domain/power-domain-uclass.c +++ b/drivers/power/domain/power-domain-uclass.c @@ -71,7 +71,7 @@ int power_domain_get_by_index(struct udevice *dev, return ret; } - ret = ops->request(power_domain); + ret = ops->request ? ops->request(power_domain) : 0; if (ret) { debug("ops->request() failed: %d\n", ret); return ret; @@ -80,6 +80,20 @@ int power_domain_get_by_index(struct udevice *dev, return 0; } +int power_domain_get_by_name(struct udevice *dev, + struct power_domain *power_domain, const char *name) +{ + int index; + + index = dev_read_stringlist_search(dev, "power-domain-names", name); + if (index < 0) { + debug("fdt_stringlist_search() failed: %d\n", index); + return index; + } + + return power_domain_get_by_index(dev, power_domain, index); +} + int power_domain_get(struct udevice *dev, struct power_domain *power_domain) { return power_domain_get_by_index(dev, power_domain, 0); @@ -91,7 +105,7 @@ int power_domain_free(struct power_domain *power_domain) debug("%s(power_domain=%p)\n", __func__, power_domain); - return ops->rfree(power_domain); + return ops->rfree ? ops->rfree(power_domain) : 0; } int power_domain_on(struct power_domain *power_domain) @@ -100,7 +114,7 @@ int power_domain_on(struct power_domain *power_domain) debug("%s(power_domain=%p)\n", __func__, power_domain); - return ops->on(power_domain); + return ops->on ? ops->on(power_domain) : 0; } int power_domain_off(struct power_domain *power_domain) @@ -109,7 +123,7 @@ int power_domain_off(struct power_domain *power_domain) debug("%s(power_domain=%p)\n", __func__, power_domain); - return ops->off(power_domain); + return ops->off ? ops->off(power_domain) : 0; } #if CONFIG_IS_ENABLED(OF_REAL) diff --git a/drivers/power/domain/tegra186-power-domain.c b/drivers/power/domain/tegra186-power-domain.c index 707735c..46da541 100644 --- a/drivers/power/domain/tegra186-power-domain.c +++ b/drivers/power/domain/tegra186-power-domain.c @@ -15,22 +15,6 @@ #define UPDATE BIT(0) #define ON BIT(1) -static int tegra186_power_domain_request(struct power_domain *power_domain) -{ - debug("%s(power_domain=%p) (dev=%p, id=%lu)\n", __func__, - power_domain, power_domain->dev, power_domain->id); - - return 0; -} - -static int tegra186_power_domain_free(struct power_domain *power_domain) -{ - debug("%s(power_domain=%p) (dev=%p, id=%lu)\n", __func__, - power_domain, power_domain->dev, power_domain->id); - - return 0; -} - static int tegra186_power_domain_common(struct power_domain *power_domain, bool on) { @@ -73,22 +57,12 @@ static int tegra186_power_domain_off(struct power_domain *power_domain) } struct power_domain_ops tegra186_power_domain_ops = { - .request = tegra186_power_domain_request, - .rfree = tegra186_power_domain_free, .on = tegra186_power_domain_on, .off = tegra186_power_domain_off, }; -static int tegra186_power_domain_probe(struct udevice *dev) -{ - debug("%s(dev=%p)\n", __func__, dev); - - return 0; -} - U_BOOT_DRIVER(tegra186_power_domain) = { .name = "tegra186_power_domain", .id = UCLASS_POWER_DOMAIN, - .probe = tegra186_power_domain_probe, .ops = &tegra186_power_domain_ops, }; diff --git a/drivers/power/domain/ti-power-domain.c b/drivers/power/domain/ti-power-domain.c index 752e76b..292fff0 100644 --- a/drivers/power/domain/ti-power-domain.c +++ b/drivers/power/domain/ti-power-domain.c @@ -356,17 +356,6 @@ static int ti_power_domain_of_xlate(struct power_domain *pd, return 0; } - -static int ti_power_domain_request(struct power_domain *pd) -{ - return 0; -} - -static int ti_power_domain_free(struct power_domain *pd) -{ - return 0; -} - static const struct udevice_id ti_power_domain_of_match[] = { { .compatible = "ti,sci-pm-domain" }, { /* sentinel */ } @@ -376,8 +365,6 @@ static struct power_domain_ops ti_power_domain_ops = { .on = ti_power_domain_on, .off = ti_power_domain_off, .of_xlate = ti_power_domain_of_xlate, - .request = ti_power_domain_request, - .rfree = ti_power_domain_free, }; U_BOOT_DRIVER(ti_pm_domains) = { diff --git a/drivers/power/domain/ti-sci-power-domain.c b/drivers/power/domain/ti-sci-power-domain.c index f18e456..0140e5e 100644 --- a/drivers/power/domain/ti-sci-power-domain.c +++ b/drivers/power/domain/ti-sci-power-domain.c @@ -44,18 +44,6 @@ static int ti_sci_power_domain_probe(struct udevice *dev) return 0; } -static int ti_sci_power_domain_request(struct power_domain *pd) -{ - debug("%s(pd=%p)\n", __func__, pd); - return 0; -} - -static int ti_sci_power_domain_free(struct power_domain *pd) -{ - debug("%s(pd=%p)\n", __func__, pd); - return 0; -} - static int ti_sci_power_domain_on(struct power_domain *pd) { struct ti_sci_power_domain_data *data = dev_get_priv(pd->dev); @@ -123,8 +111,6 @@ static const struct udevice_id ti_sci_power_domain_of_match[] = { }; static struct power_domain_ops ti_sci_power_domain_ops = { - .request = ti_sci_power_domain_request, - .rfree = ti_sci_power_domain_free, .on = ti_sci_power_domain_on, .off = ti_sci_power_domain_off, .of_xlate = ti_sci_power_domain_of_xlate, diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c index 2c5205d..6e1a1d0 100644 --- a/drivers/usb/dwc3/dwc3-generic.c +++ b/drivers/usb/dwc3/dwc3-generic.c @@ -220,11 +220,62 @@ U_BOOT_DRIVER(dwc3_generic_host) = { #endif struct dwc3_glue_ops { - void (*select_dr_mode)(struct udevice *dev, int index, + void (*glue_configure)(struct udevice *dev, int index, enum usb_dr_mode mode); }; -void dwc3_ti_select_dr_mode(struct udevice *dev, int index, +void dwc3_imx8mp_glue_configure(struct udevice *dev, int index, + enum usb_dr_mode mode) +{ +/* USB glue registers */ +#define USB_CTRL0 0x00 +#define USB_CTRL1 0x04 + +#define USB_CTRL0_PORTPWR_EN BIT(12) /* 1 - PPC enabled (default) */ +#define USB_CTRL0_USB3_FIXED BIT(22) /* 1 - USB3 permanent attached */ +#define USB_CTRL0_USB2_FIXED BIT(23) /* 1 - USB2 permanent attached */ + +#define USB_CTRL1_OC_POLARITY BIT(16) /* 0 - HIGH / 1 - LOW */ +#define USB_CTRL1_PWR_POLARITY BIT(17) /* 0 - HIGH / 1 - LOW */ + fdt_addr_t regs = dev_read_addr_index(dev, 1); + void *base = map_physmem(regs, 0x8, MAP_NOCACHE); + u32 value; + + value = readl(base + USB_CTRL0); + + if (dev_read_bool(dev, "fsl,permanently-attached")) + value |= (USB_CTRL0_USB2_FIXED | USB_CTRL0_USB3_FIXED); + else + value &= ~(USB_CTRL0_USB2_FIXED | USB_CTRL0_USB3_FIXED); + + if (dev_read_bool(dev, "fsl,disable-port-power-control")) + value &= ~(USB_CTRL0_PORTPWR_EN); + else + value |= USB_CTRL0_PORTPWR_EN; + + writel(value, base + USB_CTRL0); + + value = readl(base + USB_CTRL1); + if (dev_read_bool(dev, "fsl,over-current-active-low")) + value |= USB_CTRL1_OC_POLARITY; + else + value &= ~USB_CTRL1_OC_POLARITY; + + if (dev_read_bool(dev, "fsl,power-active-low")) + value |= USB_CTRL1_PWR_POLARITY; + else + value &= ~USB_CTRL1_PWR_POLARITY; + + writel(value, base + USB_CTRL1); + + unmap_physmem(base, MAP_NOCACHE); +} + +struct dwc3_glue_ops imx8mp_ops = { + .glue_configure = dwc3_imx8mp_glue_configure, +}; + +void dwc3_ti_glue_configure(struct udevice *dev, int index, enum usb_dr_mode mode) { #define USBOTGSS_UTMI_OTG_STATUS 0x0084 @@ -305,7 +356,7 @@ enum dwc3_omap_utmi_mode { } struct dwc3_glue_ops ti_ops = { - .select_dr_mode = dwc3_ti_select_dr_mode, + .glue_configure = dwc3_ti_glue_configure, }; static int dwc3_glue_bind(struct udevice *parent) @@ -453,8 +504,8 @@ static int dwc3_glue_probe(struct udevice *dev) dr_mode = usb_get_dr_mode(dev_ofnode(child)); device_find_next_child(&child); - if (ops && ops->select_dr_mode) - ops->select_dr_mode(dev, index, dr_mode); + if (ops && ops->glue_configure) + ops->glue_configure(dev, index, dr_mode); index++; } @@ -482,6 +533,7 @@ static const struct udevice_id dwc3_glue_ids[] = { { .compatible = "rockchip,rk3328-dwc3" }, { .compatible = "rockchip,rk3399-dwc3" }, { .compatible = "qcom,dwc3" }, + { .compatible = "fsl,imx8mp-dwc3", .data = (ulong)&imx8mp_ops }, { .compatible = "fsl,imx8mq-dwc3" }, { .compatible = "intel,tangier-dwc3" }, { } diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index 5b614cf..03e8e72 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -197,6 +197,14 @@ config WDT_MTK The watchdog timer is stopped when initialized. It performs full SoC reset. +config WDT_NPCM + bool "Nuvoton watchdog timer support" + depends on WDT && ARCH_NPCM + help + This enables Nuvoton npcm7xx/npcm8xx watchdog timer driver, + The watchdog timer is stopped when initialized. + It performs full SoC reset. + config WDT_OCTEONTX bool "OcteonTX core watchdog support" depends on WDT && (ARCH_OCTEONTX || ARCH_OCTEONTX2) diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index a35bd55..1089cd2 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -31,6 +31,7 @@ obj-$(CONFIG_WDT_MPC8xx) += mpc8xx_wdt.o obj-$(CONFIG_WDT_MT7620) += mt7620_wdt.o obj-$(CONFIG_WDT_MT7621) += mt7621_wdt.o obj-$(CONFIG_WDT_MTK) += mtk_wdt.o +obj-$(CONFIG_WDT_NPCM) += npcm_wdt.o obj-$(CONFIG_WDT_OCTEONTX) += octeontx_wdt.o obj-$(CONFIG_WDT_OMAP3) += omap_wdt.o obj-$(CONFIG_WDT_SBSA) += sbsa_gwdt.o diff --git a/drivers/watchdog/npcm_wdt.c b/drivers/watchdog/npcm_wdt.c new file mode 100644 index 0000000..256020f --- /dev/null +++ b/drivers/watchdog/npcm_wdt.c @@ -0,0 +1,116 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2022 Nuvoton Technology, Inc + */ + +#include <dm.h> +#include <errno.h> +#include <log.h> +#include <wdt.h> +#include <asm/io.h> +#include <linux/delay.h> +#include <linux/err.h> + +#define NPCM_WTCLK (BIT(10) | BIT(11)) /* Clock divider */ +#define NPCM_WTE BIT(7) /* Enable */ +#define NPCM_WTIE BIT(6) /* Enable irq */ +#define NPCM_WTIS (BIT(4) | BIT(5)) /* Interval selection */ +#define NPCM_WTIF BIT(3) /* Interrupt flag*/ +#define NPCM_WTRF BIT(2) /* Reset flag */ +#define NPCM_WTRE BIT(1) /* Reset enable */ +#define NPCM_WTR BIT(0) /* Reset counter */ + +struct npcm_wdt_priv { + void __iomem *regs; +}; + +static int npcm_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags) +{ + struct npcm_wdt_priv *priv = dev_get_priv(dev); + u32 time_out, val; + + time_out = (u32)(timeout_ms) / 1000; + if (time_out < 2) + val = 0x800; + else if (time_out < 3) + val = 0x420; + else if (time_out < 6) + val = 0x810; + else if (time_out < 11) + val = 0x430; + else if (time_out < 22) + val = 0x820; + else if (time_out < 44) + val = 0xc00; + else if (time_out < 87) + val = 0x830; + else if (time_out < 173) + val = 0xc10; + else if (time_out < 688) + val = 0xc20; + else + val = 0xc30; + + val |= NPCM_WTRE | NPCM_WTE | NPCM_WTR | NPCM_WTIE; + writel(val, priv->regs); + + return 0; +} + +static int npcm_wdt_stop(struct udevice *dev) +{ + struct npcm_wdt_priv *priv = dev_get_priv(dev); + + writel(0, priv->regs); + + return 0; +} + +static int npcm_wdt_reset(struct udevice *dev) +{ + struct npcm_wdt_priv *priv = dev_get_priv(dev); + + writel(NPCM_WTR | NPCM_WTRE | NPCM_WTE, priv->regs); + + return 0; +} + +static int npcm_wdt_of_to_plat(struct udevice *dev) +{ + struct npcm_wdt_priv *priv = dev_get_priv(dev); + + priv->regs = dev_read_addr_ptr(dev); + if (!priv->regs) + return -EINVAL; + + return 0; +} + +static const struct wdt_ops npcm_wdt_ops = { + .start = npcm_wdt_start, + .reset = npcm_wdt_reset, + .stop = npcm_wdt_stop, +}; + +static const struct udevice_id npcm_wdt_ids[] = { + { .compatible = "nuvoton,npcm750-wdt" }, + { } +}; + +static int npcm_wdt_probe(struct udevice *dev) +{ + debug("%s() wdt%u\n", __func__, dev_seq(dev)); + npcm_wdt_stop(dev); + + return 0; +} + +U_BOOT_DRIVER(npcm_wdt) = { + .name = "npcm_wdt", + .id = UCLASS_WDT, + .of_match = npcm_wdt_ids, + .probe = npcm_wdt_probe, + .priv_auto = sizeof(struct npcm_wdt_priv), + .of_to_plat = npcm_wdt_of_to_plat, + .ops = &npcm_wdt_ops, +}; diff --git a/include/configs/apalis-imx8.h b/include/configs/apalis-imx8.h index e759f18..c842226 100644 --- a/include/configs/apalis-imx8.h +++ b/include/configs/apalis-imx8.h @@ -38,6 +38,7 @@ BOOTENV \ MEM_LAYOUT_ENV_SETTINGS \ "boot_file=Image\0" \ + "boot_script_dhcp=boot.scr\0" \ "console=ttyLP1 earlycon\0" \ "fdt_addr=0x83000000\0" \ "fdt_file=fsl-imx8qm-apalis-eval.dtb\0" \ @@ -49,11 +50,6 @@ "root=PARTUUID=${uuid} rootwait " \ "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ "mmcpart=1\0" \ - "netargs=setenv bootargs console=${console},${baudrate} " \ - "root=/dev/nfs ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp" \ - "\0" \ - "nfsboot=run netargs; dhcp ${loadaddr} ${boot_file}; tftp ${fdt_addr} " \ - "apalis-imx8/${fdt_file}; booti ${loadaddr} - ${fdt_addr}\0" \ "panel=NULL\0" \ "script=boot.scr\0" \ "update_uboot=askenv confirm Did you load u-boot-dtb.imx (y/N)?; " \ diff --git a/include/configs/apalis-imx8x.h b/include/configs/apalis-imx8x.h deleted file mode 100644 index 17f1981..0000000 --- a/include/configs/apalis-imx8x.h +++ /dev/null @@ -1,124 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2020 Toradex - */ - -#ifndef __APALIS_IMX8X_H -#define __APALIS_IMX8X_H - -#include <asm/arch/imx-regs.h> -#include <linux/sizes.h> -#include <linux/stringify.h> - -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#define USDHC1_BASE_ADDR 0x5b010000 -#define USDHC2_BASE_ADDR 0x5b020000 - -#define CONFIG_IPADDR 192.168.10.2 -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_SERVERIP 192.168.10.1 - -#define MEM_LAYOUT_ENV_SETTINGS \ - "kernel_addr_r=0x80280000\0" \ - "fdt_addr_r=0x83100000\0" \ - "ramdisk_addr_r=0x8a000000\0" \ - "scriptaddr=0x83200000\0" - -#ifdef CONFIG_AHAB_BOOT -#define AHAB_ENV "sec_boot=yes\0" -#else -#define AHAB_ENV "sec_boot=no\0" -#endif - -/* Boot M4 */ -#define M4_BOOT_ENV \ - "m4_0_image=m4_0.bin\0" \ - "loadm4image_0=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} " \ - "${m4_0_image}\0" \ - "m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr} 0\0" \ - -#define MFG_NAND_PARTITION "" - -#define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 1) \ - func(MMC, mmc, 0) \ - func(DHCP, dhcp, na) -#include <config_distro_bootcmd.h> -#undef BOOTENV_RUN_NET_USB_START -#define BOOTENV_RUN_NET_USB_START "" - -#define CONFIG_MFG_ENV_SETTINGS \ - "mfgtool_args=setenv bootargs ${consoleargs} " \ - "rdinit=/linuxrc g_mass_storage.stall=0 " \ - "g_mass_storage.removable=1 g_mass_storage.idVendor=0x066F " \ - "g_mass_storage.idProduct=0x37FF " \ - "g_mass_storage.iSerialNumber=\"\" " MFG_NAND_PARTITION \ - "${vidargs} clk_ignore_unused\0" \ - "initrd_addr=0x83800000\0" \ - "bootcmd_mfg=run mfgtool_args;booti ${loadaddr} ${initrd_addr} " \ - "${fdt_addr};\0" \ - -/* Initial environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - AHAB_ENV \ - BOOTENV \ - CONFIG_MFG_ENV_SETTINGS \ - M4_BOOT_ENV \ - MEM_LAYOUT_ENV_SETTINGS \ - "boot_file=Image\0" \ - "consoleargs=console=ttyLP3,${baudrate} earlycon\0" \ - "fdt_file=imx8qxp-apalis-eval.dtb\0" \ - "fdtfile=imx8qxp-apalis-eval.dtb\0" \ - "finduuid=part uuid mmc ${mmcdev}:2 uuid\0" \ - "image=Image\0" \ - "initrd_addr=0x83800000\0" \ - "mmcargs=setenv bootargs ${consoleargs} " \ - "root=PARTUUID=${uuid} rootwait " \ - "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ - "mmcpart=1\0" \ - "netargs=setenv bootargs ${consoleargs} " \ - "root=/dev/nfs ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp " \ - "${vidargs}\0" \ - "nfsboot=run netargs; dhcp ${loadaddr} ${image}; tftp ${fdt_addr} " \ - "apalis-imx8x/${fdt_file}; booti ${loadaddr} - " \ - "${fdt_addr}\0" \ - "panel=NULL\0" \ - "script=boot.scr\0" \ - "update_uboot=askenv confirm Did you load u-boot-dtb.imx (y/N)?; " \ - "if test \"$confirm\" = \"y\"; then " \ - "setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt " \ - "${blkcnt} / 0x200; mmc dev 0 1; mmc write ${loadaddr} 0x0 " \ - "${blkcnt}; fi\0" \ - "vidargs=video=imxdpufb5:off video=imxdpufb6:off video=imxdpufb7:off\0" - -/* Link Definitions */ - -#define CONFIG_SYS_INIT_SP_ADDR 0x80200000 - -/* Environment in eMMC, before config block at the end of 1st "boot sector" */ - -/* On Apalis iMX8X USDHC1 is eMMC, USDHC2 is 4-bit SD */ -#define CONFIG_SYS_FSL_USDHC_NUM 2 - -#define CONFIG_SYS_BOOTM_LEN SZ_64M /* Increase max gunzip size */ - -#define CONFIG_SYS_SDRAM_BASE 0x80000000 -#define PHYS_SDRAM_1 0x80000000 -#define PHYS_SDRAM_2 0x880000000 -#define PHYS_SDRAM_1_SIZE SZ_2G /* 2 GB */ -#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 GB */ - -/* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE SZ_2K -#define CONFIG_SYS_MAXARGS 64 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) - -/* Networking */ -#define CONFIG_FEC_ENET_DEV 0 -#define IMX_FEC_BASE 0x5b040000 -#define CONFIG_FEC_MXC_PHYADDR 0x4 -#define PHY_ANEG_TIMEOUT 20000 - -#endif /* __APALIS_IMX8X_H */ diff --git a/include/configs/apalis-tk1.h b/include/configs/apalis-tk1.h index 59c9019..face78e 100644 --- a/include/configs/apalis-tk1.h +++ b/include/configs/apalis-tk1.h @@ -59,18 +59,9 @@ "update_uboot=run set_blkcnt && mmc dev 0 ${uboot_hwpart} && " \ "mmc write ${loadaddr} ${uboot_blk} ${blkcnt}\0" \ -#define NFS_BOOTCMD \ - "nfsargs=ip=:::::eth0:on root=/dev/nfs rw\0" \ - "nfsboot=pci enum; run setup; setenv bootargs ${defargs} ${nfsargs} " \ - "${setupargs} ${vidargs}; echo Booting via DHCP/TFTP/NFS...; " \ - "run nfsdtbload; dhcp ${kernel_addr_r} " \ - "&& run fdt_fixup && bootz ${kernel_addr_r} - ${dtbparam}\0" \ - "nfsdtbload=setenv dtbparam; tftp ${fdt_addr_r} " \ - "${soc}-${fdt_module}-${fdt_board}.dtb " \ - "&& setenv dtbparam ${fdt_addr_r}\0" - #define BOARD_EXTRA_ENV_SETTINGS \ "boot_file=zImage\0" \ + "boot_script_dhcp=boot.scr\0" \ "console=ttyS0\0" \ "defargs=lp0_vec=2064@0xf46ff000 core_edp_mv=1150 core_edp_ma=4000 " \ "usb_port_owner_info=2 lane_owner_info=6 emc_max_dvfs=0 " \ @@ -79,7 +70,6 @@ "fdt_board=eval\0" \ "fdt_fixup=;\0" \ "fdt_module=" FDT_MODULE "\0" \ - NFS_BOOTCMD \ UBOOT_UPDATE \ "setethupdate=if env exists ethaddr; then; else setenv ethaddr " \ "00:14:2d:00:00:00; fi; pci enum && tftpboot ${loadaddr} " \ diff --git a/include/configs/apalis_imx6.h b/include/configs/apalis_imx6.h index ea5711d..aa93d10 100644 --- a/include/configs/apalis_imx6.h +++ b/include/configs/apalis_imx6.h @@ -89,32 +89,15 @@ "ramdisk_addr_r=0x12200000\0" \ "scriptaddr=0x17000000\0" -#define NFS_BOOTCMD \ - "nfsargs=ip=:::::eth0:on root=/dev/nfs ro\0" \ - "nfsboot=run setup; " \ - "setenv bootargs ${defargs} ${nfsargs} ${setupargs} " \ - "${vidargs}; echo Booting via DHCP/TFTP/NFS...; " \ - "run nfsdtbload; dhcp ${kernel_addr_r} " \ - "&& run fdt_fixup && bootz ${kernel_addr_r} ${dtbparam}\0" \ - "nfsdtbload=setenv dtbparam; tftp ${fdt_addr_r} ${fdt_file} " \ - "&& setenv dtbparam \" - ${fdt_addr_r}\" && true\0" - -#ifndef CONFIG_TDX_APALIS_IMX6_V1_0 -#define FDT_FILE "imx6q-apalis-eval.dtb" -#define FDT_FILE_V1_0 "imx6q-apalis_v1_0-eval.dtb" -#else -#define FDT_FILE "imx6q-apalis_v1_0-eval.dtb" -#endif #define CONFIG_EXTRA_ENV_SETTINGS \ BOOTENV \ "boot_file=zImage\0" \ + "boot_script_dhcp=boot.scr\0" \ "console=ttymxc0\0" \ "defargs=enable_wait_mode=off vmalloc=400M\0" \ - "fdt_file=" FDT_FILE "\0" \ - "fdtfile=" FDT_FILE "\0" \ + "fdt_board=eval\0" \ "fdt_fixup=;\0" \ MEM_LAYOUT_ENV_SETTINGS \ - NFS_BOOTCMD \ UBOOT_UPDATE \ "setethupdate=if env exists ethaddr; then; else setenv ethaddr " \ "00:14:2d:00:00:00; fi; tftpboot ${loadaddr} " \ diff --git a/include/configs/apalis_t30.h b/include/configs/apalis_t30.h index b7a2fb6..d1d518a 100644 --- a/include/configs/apalis_t30.h +++ b/include/configs/apalis_t30.h @@ -47,7 +47,8 @@ "mmc write ${loadaddr} ${uboot_blk} ${blkcnt}\0" \ #define BOARD_EXTRA_ENV_SETTINGS \ - UBOOT_UPDATE + UBOOT_UPDATE \ + "boot_script_dhcp=boot.scr\0" #include "tegra-common-post.h" diff --git a/include/configs/aristainetos2.h b/include/configs/aristainetos2.h index 611b6d7..8ee97f1 100644 --- a/include/configs/aristainetos2.h +++ b/include/configs/aristainetos2.h @@ -26,12 +26,10 @@ #include "mx6_common.h" -#define CONFIG_MMCROOT "/dev/mmcblk0p1" /* MMC Configs */ #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR -#define IMX_FEC_BASE ENET_BASE_ADDR #define CONFIG_FEC_MXC_PHYADDR 0 #define CONFIG_SYS_SPI_ST_ENABLE_WP_PIN @@ -183,7 +181,7 @@ "${pubkey}\0" \ "mainRargs=setenv bootargs console=${console},${baudrate} " \ "rescue_sysnum=${rescue_sysnum} root=${emmcroot} rootfstype=ext4\0" \ - "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcroot=/dev/mmcblk0p1 rootwait rw\0" \ "mmcargs=setenv bootargs console=${console},${baudrate} " \ "root=${mmcroot}\0" \ "mmcRargs=setenv bootargs console=${console},${baudrate} " \ diff --git a/include/configs/capricorn-common.h b/include/configs/capricorn-common.h index 1466be1..364bd50 100644 --- a/include/configs/capricorn-common.h +++ b/include/configs/capricorn-common.h @@ -109,7 +109,6 @@ #define CONFIG_SYS_INIT_SP_ADDR 0x80200000 /* On CCP board, USDHC1 is for eMMC */ -#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* eMMC */ #define CONFIG_SYS_SDRAM_BASE 0x80000000 #define PHYS_SDRAM_1 0x80000000 diff --git a/include/configs/cgtqmx8.h b/include/configs/cgtqmx8.h index b5817f1..6da0483 100644 --- a/include/configs/cgtqmx8.h +++ b/include/configs/cgtqmx8.h @@ -78,7 +78,7 @@ "fdt_file=imx8qm-cgt-qmx8.dtb\0" \ "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ "mmcpart=1\0" \ - "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcroot=/dev/mmcblk1p2 rootwait rw\0" \ "mmcautodetect=yes\0" \ "mmcargs=setenv bootargs console=${console},${baudrate} root=${mmcroot} earlycon\0 " \ "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ @@ -122,7 +122,6 @@ #define CONFIG_SYS_INIT_SP_ADDR 0x80200000 -#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ #define CONFIG_SYS_FSL_USDHC_NUM 3 #define CONFIG_SYS_SDRAM_BASE 0x80000000 diff --git a/include/configs/cl-som-imx7.h b/include/configs/cl-som-imx7.h index 8af80f5..4b494d8 100644 --- a/include/configs/cl-som-imx7.h +++ b/include/configs/cl-som-imx7.h @@ -104,7 +104,6 @@ #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR #define CONFIG_SYS_FSL_USDHC_NUM 2 -#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */ #endif /* USB Configs */ diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h index f836f92..600999b 100644 --- a/include/configs/cm_fx6.h +++ b/include/configs/cm_fx6.h @@ -147,7 +147,6 @@ /* Ethernet */ #define CONFIG_FEC_MXC_PHYADDR 0 -#define IMX_FEC_BASE ENET_BASE_ADDR /* USB */ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) diff --git a/include/configs/colibri-imx6ull.h b/include/configs/colibri-imx6ull.h index 281815e..9e5212a 100644 --- a/include/configs/colibri-imx6ull.h +++ b/include/configs/colibri-imx6ull.h @@ -16,7 +16,6 @@ #define PHYS_SDRAM_SIZE SZ_1G /* ENET1 */ -#define IMX_FEC_BASE ENET2_BASE_ADDR /* MMC Config */ #define CONFIG_SYS_FSL_ESDHC_ADDR 0 @@ -50,15 +49,6 @@ "ramdisk_addr_r=0x82200000\0" \ "scriptaddr=0x87000000\0" -#define NFS_BOOTCMD \ - "nfsargs=ip=:::::eth0: root=/dev/nfs\0" \ - "nfsboot=run setup; " \ - "setenv bootargs ${defargs} ${nfsargs} " \ - "${setupargs} ${vidargs}; echo Booting from NFS...;" \ - "dhcp ${kernel_addr_r} && " \ - "tftp ${fdt_addr_r} ${fdtfile} && " \ - "run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \ - #define UBI_BOOTCMD \ "ubiargs=ubi.mtd=ubi root=ubi0:rootfs rw rootfstype=ubifs " \ "ubi.fm_autoconvert=1\0" \ @@ -98,9 +88,9 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ BOOTENV \ MEM_LAYOUT_ENV_SETTINGS \ - NFS_BOOTCMD \ UBI_BOOTCMD \ UBOOT_UPDATE \ + "boot_script_dhcp=boot.scr\0" \ "bootubipart=ubi\0" \ "console=ttymxc0\0" \ "defargs=user_debug=30\0" \ diff --git a/include/configs/colibri-imx8x.h b/include/configs/colibri-imx8x.h index 265b729..3ed89c2 100644 --- a/include/configs/colibri-imx8x.h +++ b/include/configs/colibri-imx8x.h @@ -67,6 +67,7 @@ M4_BOOT_ENV \ MEM_LAYOUT_ENV_SETTINGS \ "boot_file=Image\0" \ + "boot_script_dhcp=boot.scr\0" \ "consoleargs=console=ttyLP3,${baudrate} earlycon\0" \ "fdt_addr=0x83000000\0" \ "fdt_file=fsl-imx8qxp-colibri-dsihdmi-eval-v3.dtb\0" \ @@ -79,12 +80,6 @@ "root=PARTUUID=${uuid} rootwait " \ "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ "mmcpart=1\0" \ - "netargs=setenv bootargs ${consoleargs} " \ - "root=/dev/nfs ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp " \ - "${vidargs}\0" \ - "nfsboot=run netargs; dhcp ${loadaddr} ${image}; tftp ${fdt_addr} " \ - "colibri-imx8x/${fdt_file}; booti ${loadaddr} - " \ - "${fdt_addr}\0" \ "panel=NULL\0" \ "script=boot.scr\0" \ "update_uboot=askenv confirm Did you load u-boot-dtb.imx (y/N)?; " \ diff --git a/include/configs/colibri_imx6.h b/include/configs/colibri_imx6.h index 0d1a1bc..9ca6bef 100644 --- a/include/configs/colibri_imx6.h +++ b/include/configs/colibri_imx6.h @@ -78,27 +78,15 @@ "ramdisk_addr_r=0x12200000\0" \ "scriptaddr=0x17000000\0" -#define NFS_BOOTCMD \ - "nfsargs=ip=:::::eth0:on root=/dev/nfs rw\0" \ - "nfsboot=run setup; " \ - "setenv bootargs ${defargs} ${nfsargs} ${setupargs} " \ - "${vidargs}; echo Booting via DHCP/TFTP/NFS...; " \ - "run nfsdtbload; dhcp ${kernel_addr_r} " \ - "&& run fdt_fixup && bootz ${kernel_addr_r} ${dtbparam}\0" \ - "nfsdtbload=setenv dtbparam; tftp ${fdt_addr_r} ${fdt_file} " \ - "&& setenv dtbparam \" - ${fdt_addr_r}\" && true\0" - -#define FDT_FILE "imx6dl-colibri-eval-v3.dtb" #define CONFIG_EXTRA_ENV_SETTINGS \ BOOTENV \ "boot_file=zImage\0" \ + "boot_script_dhcp=boot.scr\0" \ "console=ttymxc0\0" \ "defargs=enable_wait_mode=off galcore.contiguousSize=50331648\0" \ - "fdt_file=" FDT_FILE "\0" \ - "fdtfile=" FDT_FILE "\0" \ + "fdt_board=eval-v3\0" \ "fdt_fixup=;\0" \ MEM_LAYOUT_ENV_SETTINGS \ - NFS_BOOTCMD \ UBOOT_UPDATE \ "setethupdate=if env exists ethaddr; then; else setenv ethaddr " \ "00:14:2d:00:00:00; fi; tftpboot ${loadaddr} " \ diff --git a/include/configs/colibri_imx7.h b/include/configs/colibri_imx7.h index 0382724..3dba7bc 100644 --- a/include/configs/colibri_imx7.h +++ b/include/configs/colibri_imx7.h @@ -89,15 +89,6 @@ "ramdisk_addr_r=0x82100000\0" \ "scriptaddr=0x87000000\0" -#define NFS_BOOTCMD \ - "nfsargs=ip=:::::eth0: root=/dev/nfs\0" \ - "nfsboot=run setup; " \ - "setenv bootargs ${defargs} ${nfsargs} " \ - "${setupargs} ${vidargs}; echo Booting from NFS...;" \ - "dhcp ${kernel_addr_r} && " \ - "tftp ${fdt_addr_r} ${soc}-colibri${variant}-${fdt_board}.dtb && " \ - "run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \ - #define UBI_BOOTCMD \ "ubiargs=ubi.mtd=ubi root=ubi0:rootfs rootfstype=ubifs " \ "ubi.fm_autoconvert=1\0" \ @@ -136,10 +127,10 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ BOOTENV \ MEM_LAYOUT_ENV_SETTINGS \ - NFS_BOOTCMD \ MODULE_EXTRA_ENV_SETTINGS \ UBOOT_UPDATE \ "boot_file=zImage\0" \ + "boot_script_dhcp=boot.scr\0" \ "bootubipart=ubi\0" \ "console=ttymxc0\0" \ "defargs=\0" \ diff --git a/include/configs/colibri_pxa270.h b/include/configs/colibri_pxa270.h deleted file mode 100644 index 809afb7..0000000 --- a/include/configs/colibri_pxa270.h +++ /dev/null @@ -1,150 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Toradex Colibri PXA270 configuration file - * - * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com> - * Copyright (C) 2015-2016 Marcel Ziswiler <marcel@ziswiler.com> - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Board Configuration Options - */ - -/* - * Environment settings - */ - -/* - * Serial Console Configuration - */ - -/* - * Bootloader Components Configuration - */ - -/* I2C support */ -#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) -#define CONFIG_SYS_I2C_PXA -#define CONFIG_PXA_STD_I2C -#define CONFIG_PXA_PWR_I2C -#endif - -/* LCD support */ -#ifdef CONFIG_LCD -#define CONFIG_PXA_LCD -#define CONFIG_PXA_VGA -#endif - -/* - * Networking Configuration - */ -#ifdef CONFIG_CMD_NET - -#define CONFIG_DM9000_BASE 0x08000000 -#define DM9000_IO (CONFIG_DM9000_BASE) -#define DM9000_DATA (CONFIG_DM9000_BASE + 4) -#endif - -/* - * Clock Configuration - */ -#define CONFIG_SYS_CPUSPEED 0x290 /* 520MHz */ - -/* - * DRAM Map - */ -#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ - -#define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */ -#define CONFIG_SYS_DRAM_SIZE 0x04000000 /* 64 MB DRAM */ - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_SP_ADDR 0x5c010000 - -/* - * NOR FLASH - */ -#ifdef CONFIG_CMD_FLASH -#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ -#define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */ -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 - -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT - -#define CONFIG_SYS_MAX_FLASH_SECT (4 + 255) - -#define CONFIG_SYS_FLASH_ERASE_TOUT (25 * CONFIG_SYS_HZ) -#define CONFIG_SYS_FLASH_WRITE_TOUT (25 * CONFIG_SYS_HZ) -#define CONFIG_SYS_FLASH_LOCK_TOUT (25 * CONFIG_SYS_HZ) -#define CONFIG_SYS_FLASH_UNLOCK_TOUT (25 * CONFIG_SYS_HZ) -#endif - -#define CONFIG_SYS_MONITOR_LEN 0x40000 - -/* Skip factory configuration block */ - -/* - * GPIO settings - */ -#define CONFIG_SYS_GPSR0_VAL 0x00000000 -#define CONFIG_SYS_GPSR1_VAL 0x00020000 -#define CONFIG_SYS_GPSR2_VAL 0x0002c000 -#define CONFIG_SYS_GPSR3_VAL 0x00000000 - -#define CONFIG_SYS_GPCR0_VAL 0x00000000 -#define CONFIG_SYS_GPCR1_VAL 0x00000000 -#define CONFIG_SYS_GPCR2_VAL 0x00000000 -#define CONFIG_SYS_GPCR3_VAL 0x00000000 - -#define CONFIG_SYS_GPDR0_VAL 0xc8008000 -#define CONFIG_SYS_GPDR1_VAL 0xfc02a981 -#define CONFIG_SYS_GPDR2_VAL 0x92c3ffff -#define CONFIG_SYS_GPDR3_VAL 0x0061e804 - -#define CONFIG_SYS_GAFR0_L_VAL 0x80100000 -#define CONFIG_SYS_GAFR0_U_VAL 0xa5c00010 -#define CONFIG_SYS_GAFR1_L_VAL 0x6992901a -#define CONFIG_SYS_GAFR1_U_VAL 0xaaa50008 -#define CONFIG_SYS_GAFR2_L_VAL 0xaaaaaaaa -#define CONFIG_SYS_GAFR2_U_VAL 0x4109a002 -#define CONFIG_SYS_GAFR3_L_VAL 0x54000310 -#define CONFIG_SYS_GAFR3_U_VAL 0x00005401 - -#define CONFIG_SYS_PSSR_VAL 0x30 - -/* - * Clock settings - */ -#define CONFIG_SYS_CKEN 0x00500240 -#define CONFIG_SYS_CCCR 0x02000290 - -/* - * Memory settings - */ -#define CONFIG_SYS_MSC0_VAL 0x9ee1c5f2 -#define CONFIG_SYS_MSC1_VAL 0x9ee1f994 -#define CONFIG_SYS_MSC2_VAL 0x9ee19ee1 -#define CONFIG_SYS_MDCNFG_VAL 0x090009c9 -#define CONFIG_SYS_MDREFR_VAL 0x2003a031 -#define CONFIG_SYS_MDMRS_VAL 0x00220022 -#define CONFIG_SYS_FLYCNFG_VAL 0x00010001 -#define CONFIG_SYS_SXCNFG_VAL 0x40044004 - -/* - * PCMCIA and CF Interfaces - */ -#define CONFIG_SYS_MECR_VAL 0x00000000 -#define CONFIG_SYS_MCMEM0_VAL 0x00028307 -#define CONFIG_SYS_MCMEM1_VAL 0x00014307 -#define CONFIG_SYS_MCATT0_VAL 0x00038787 -#define CONFIG_SYS_MCATT1_VAL 0x0001c787 -#define CONFIG_SYS_MCIO0_VAL 0x0002830f -#define CONFIG_SYS_MCIO1_VAL 0x0001430f - -#include "pxa-common.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/colibri_t20.h b/include/configs/colibri_t20.h index fdf6bb2..f6b3ab1 100644 --- a/include/configs/colibri_t20.h +++ b/include/configs/colibri_t20.h @@ -24,6 +24,7 @@ /* Environment in NAND, 64K is a bit excessive but erase block is 512K anyway */ #define BOARD_EXTRA_ENV_SETTINGS \ + "boot_script_dhcp=boot.scr\0" \ "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ UBOOT_UPDATE diff --git a/include/configs/colibri_t30.h b/include/configs/colibri_t30.h index cbe73bf..1ce0def 100644 --- a/include/configs/colibri_t30.h +++ b/include/configs/colibri_t30.h @@ -45,7 +45,8 @@ "mmc write ${loadaddr} ${uboot_blk} ${blkcnt}\0" \ #define BOARD_EXTRA_ENV_SETTINGS \ - UBOOT_UPDATE + UBOOT_UPDATE \ + "boot_script_dhcp=boot.scr\0" #include "tegra-common-post.h" diff --git a/include/configs/colibri_vf.h b/include/configs/colibri_vf.h index c536672..99b0cbb 100644 --- a/include/configs/colibri_vf.h +++ b/include/configs/colibri_vf.h @@ -35,15 +35,6 @@ "update_uboot=nand erase.part u-boot && " \ "nand write ${loadaddr} u-boot ${filesize}\0" \ -#define NFS_BOOTCMD \ - "nfsargs=ip=:::::eth0: root=/dev/nfs\0" \ - "nfsboot=run setup; " \ - "setenv bootargs ${defargs} ${nfsargs} ${mtdparts} " \ - "${setupargs} ${vidargs}; echo Booting from NFS...;" \ - "dhcp ${kernel_addr_r} && " \ - "tftp ${fdt_addr_r} ${soc}-colibri-${fdt_board}.dtb && " \ - "run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \ - #define UBI_BOOTCMD \ "ubiargs=ubi.mtd=ubi root=ubi0:rootfs rootfstype=ubifs " \ "ubi.fm_autoconvert=1\0" \ @@ -68,9 +59,9 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ BOOTENV \ MEM_LAYOUT_ENV_SETTINGS \ - NFS_BOOTCMD \ UBI_BOOTCMD \ UBOOT_UPDATE \ + "boot_script_dhcp=boot.scr\0" \ "console=ttyLP0\0" \ "defargs=user_debug=30\0" \ "dfu_alt_info=" DFU_ALT_NAND_INFO "\0" \ diff --git a/include/configs/dh_imx6.h b/include/configs/dh_imx6.h index 3d3fab5..2b14464 100644 --- a/include/configs/dh_imx6.h +++ b/include/configs/dh_imx6.h @@ -31,7 +31,6 @@ #define CONFIG_SYS_BOOTCOUNT_BE /* FEC ethernet */ -#define IMX_FEC_BASE ENET_BASE_ADDR #define CONFIG_FEC_MXC_PHYADDR 7 /* MMC Configs */ diff --git a/include/configs/ge_bx50v3.h b/include/configs/ge_bx50v3.h index 8d467e4..c80a076 100644 --- a/include/configs/ge_bx50v3.h +++ b/include/configs/ge_bx50v3.h @@ -123,6 +123,5 @@ #define CONFIG_PCI_SCAN_SHOW #define CONFIG_PCIE_IMX -#define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(1, 5) #endif /* __GE_BX50V3_CONFIG_H */ diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h index 8158222..86d0fb6 100644 --- a/include/configs/gw_ventana.h +++ b/include/configs/gw_ventana.h @@ -31,9 +31,6 @@ #undef CONFIG_SYS_BOOTM_LEN #define CONFIG_SYS_BOOTM_LEN (64 << 20) -/* I2C Configs */ -#define CONFIG_I2C_GSC 0 - /* MMC Configs */ #define CONFIG_SYS_FSL_ESDHC_ADDR 0 diff --git a/include/configs/imx7-cm.h b/include/configs/imx7-cm.h index 46ca1c5..2d9f8bb 100644 --- a/include/configs/imx7-cm.h +++ b/include/configs/imx7-cm.h @@ -31,7 +31,7 @@ "fdt_addr=0x83000000\0" \ "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ "mmcpart=1\0" \ - "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \ "mmcargs=setenv bootargs console=${console},${baudrate} " \ "root=${mmcroot}\0" \ "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ @@ -83,7 +83,6 @@ #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR #define CONFIG_SYS_FSL_USDHC_NUM 2 -#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */ /* USB Configs */ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) diff --git a/include/configs/imx8mm-cl-iot-gate.h b/include/configs/imx8mm-cl-iot-gate.h index b2cde03..c20c32b 100644 --- a/include/configs/imx8mm-cl-iot-gate.h +++ b/include/configs/imx8mm-cl-iot-gate.h @@ -88,7 +88,7 @@ "bootm_size=0x10000000\0" \ "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ "mmcpart=1\0" \ - "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcroot=/dev/mmcblk1p2 rootwait rw\0" \ "mmcautodetect=yes\0" \ "mmcargs=setenv bootargs console=${console} root=${mmcroot}\0 " \ "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ @@ -140,7 +140,6 @@ #define CONFIG_SYS_INIT_SP_ADDR \ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) -#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ #define CONFIG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 diff --git a/include/configs/imx8mm_evk.h b/include/configs/imx8mm_evk.h index 23467f5..42b7848 100644 --- a/include/configs/imx8mm_evk.h +++ b/include/configs/imx8mm_evk.h @@ -52,7 +52,7 @@ "initrd_addr=0x43800000\0" \ "bootm_size=0x10000000\0" \ "mmcpart=1\0" \ - "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcroot=/dev/mmcblk1p2 rootwait rw\0" \ /* Link Definitions */ @@ -63,7 +63,6 @@ #define CONFIG_SYS_INIT_SP_ADDR \ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) -#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ #define CONFIG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 @@ -78,11 +77,6 @@ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ sizeof(CONFIG_SYS_PROMPT) + 16) -/* USDHC */ - -#define CONFIG_SYS_FSL_USDHC_NUM 2 -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 - #define CONFIG_FEC_MXC_PHYADDR 0 #define FEC_QUIRK_ENET_MAC diff --git a/include/configs/imx8mm_venice.h b/include/configs/imx8mm_venice.h index eee59a4..1b26e02 100644 --- a/include/configs/imx8mm_venice.h +++ b/include/configs/imx8mm_venice.h @@ -29,16 +29,19 @@ #endif #define MEM_LAYOUT_ENV_SETTINGS \ - "fdt_addr_r=0x44000000\0" \ - "kernel_addr_r=0x42000000\0" \ - "ramdisk_addr_r=0x46400000\0" \ - "scriptaddr=0x46000000\0" + "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "fdt_addr_r=0x50200000\0" \ + "scriptaddr=0x50280000\0" \ + "ramdisk_addr_r=0x50300000\0" \ + "kernel_comp_addr_r=0x40200000\0" /* Enable Distro Boot */ #ifndef CONFIG_SPL_BUILD #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 1) \ func(MMC, mmc, 2) \ + func(USB, usb, 0) \ + func(USB, usb, 1) \ func(DHCP, dhcp, na) #include <config_distro_bootcmd.h> #else @@ -108,10 +111,6 @@ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ sizeof(CONFIG_SYS_PROMPT) + 16) -/* USDHC */ -#define CONFIG_SYS_FSL_USDHC_NUM 2 -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 - /* FEC */ #define CONFIG_FEC_MXC_PHYADDR 0 #define FEC_QUIRK_ENET_MAC diff --git a/include/configs/imx8mn_evk.h b/include/configs/imx8mn_evk.h index 142fc3e..0341322 100644 --- a/include/configs/imx8mn_evk.h +++ b/include/configs/imx8mn_evk.h @@ -39,19 +39,27 @@ #endif /* Initial environment variables */ +/* see include/configs/ti_armv7_common.h */ +#define ENV_MEM_LAYOUT_SETTINGS \ + "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "kernel_addr_r=0x42000000\0" \ + "fdt_addr_r=0x48000000\0" \ + "fdtoverlay_addr_r=0x49000000\0" \ + "ramdisk_addr_r=0x48080000\0" \ + "initrd_addr=0x48080000\0" \ + "scriptaddr=0x40000000\0" \ + "pxefile_addr_r=0x40100000\0" + #define CONFIG_EXTRA_ENV_SETTINGS \ "image=Image\0" \ BOOTENV \ - "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ - "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "console=ttymxc1,115200\0" \ - "fdt_addr_r=0x43000000\0" \ "boot_fit=no\0" \ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ - "initrd_addr=0x43800000\0" \ "bootm_size=0x10000000\0" \ "mmcpart=1\0" \ - "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcroot=/dev/mmcblk1p2 rootwait rw\0" \ + ENV_MEM_LAYOUT_SETTINGS /* Link Definitions */ @@ -62,7 +70,6 @@ #define CONFIG_SYS_INIT_SP_ADDR \ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) -#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ #define CONFIG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 @@ -77,9 +84,4 @@ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ sizeof(CONFIG_SYS_PROMPT) + 16) -/* USDHC */ - -#define CONFIG_SYS_FSL_USDHC_NUM 2 -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 - #endif diff --git a/include/configs/imx8mn_venice.h b/include/configs/imx8mn_venice.h index d977d32..a482677 100644 --- a/include/configs/imx8mn_venice.h +++ b/include/configs/imx8mn_venice.h @@ -26,16 +26,18 @@ #endif #define MEM_LAYOUT_ENV_SETTINGS \ - "fdt_addr_r=0x44000000\0" \ - "kernel_addr_r=0x42000000\0" \ - "ramdisk_addr_r=0x46400000\0" \ - "scriptaddr=0x46000000\0" + "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "fdt_addr_r=0x50200000\0" \ + "scriptaddr=0x50280000\0" \ + "ramdisk_addr_r=0x50300000\0" \ + "kernel_comp_addr_r=0x40200000\0" /* Enable Distro Boot */ #ifndef CONFIG_SPL_BUILD #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 1) \ func(MMC, mmc, 2) \ + func(USB, usb, 0) \ func(DHCP, dhcp, na) #include <config_distro_bootcmd.h> #else @@ -104,9 +106,6 @@ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ sizeof(CONFIG_SYS_PROMPT) + 16) -/* USDHC */ -#define CONFIG_SYS_FSL_USDHC_NUM 2 -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 /* FEC */ #define CONFIG_FEC_MXC_PHYADDR 0 diff --git a/include/configs/imx8mp_evk.h b/include/configs/imx8mp_evk.h index 5b185cf..cc8d65c 100644 --- a/include/configs/imx8mp_evk.h +++ b/include/configs/imx8mp_evk.h @@ -61,7 +61,7 @@ "initrd_addr=0x43800000\0" \ "bootm_size=0x10000000\0" \ "mmcpart=1\0" \ - "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcroot=/dev/mmcblk1p2 rootwait rw\0" \ /* Link Definitions */ @@ -72,7 +72,6 @@ #define CONFIG_SYS_INIT_SP_ADDR \ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) -#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ /* Totally 6GB DDR */ #define CONFIG_SYS_SDRAM_BASE 0x40000000 @@ -90,7 +89,4 @@ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_FSL_USDHC_NUM 2 -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 - #endif diff --git a/include/configs/imx8mp_rsb3720.h b/include/configs/imx8mp_rsb3720.h index 2553f0d..c5dd545 100644 --- a/include/configs/imx8mp_rsb3720.h +++ b/include/configs/imx8mp_rsb3720.h @@ -104,7 +104,7 @@ "bootm_size=0x10000000\0" \ "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ "mmcpart=1\0" \ - "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcroot=/dev/mmcblk1p2 rootwait rw\0" \ "mmcautodetect=yes\0" \ "mmcargs=setenv bootargs ${jh_clk} console=${console} root=${mmcroot}\0 " \ "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ @@ -155,7 +155,6 @@ #define CONFIG_SYS_INIT_SP_ADDR \ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) -#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ /* Totally 6GB or 4G DDR */ #define CONFIG_SYS_SDRAM_BASE 0x40000000 diff --git a/include/configs/imx8mp_venice.h b/include/configs/imx8mp_venice.h new file mode 100644 index 0000000..aa0396d --- /dev/null +++ b/include/configs/imx8mp_venice.h @@ -0,0 +1,109 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2022 Gateworks Corporation + */ + +#ifndef __IMX8MP_VENICE_H +#define __IMX8MP_VENICE_H + +#include <asm/arch/imx-regs.h> +#include <linux/sizes.h> + +#define CONFIG_SPL_MAX_SIZE (152 * 1024) +#define CONFIG_SYS_MONITOR_LEN SZ_512K +#define CONFIG_SYS_UBOOT_BASE \ + (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SPL_STACK 0x960000 +#define CONFIG_SPL_BSS_START_ADDR 0x0098FC00 +#define CONFIG_SPL_BSS_MAX_SIZE 0x400 /* 1 KB */ +#define CONFIG_SYS_SPL_MALLOC_START 0x42200000 +#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 KB */ + +/* For RAW image gives a error info not panic */ +#define CONFIG_SPL_ABORT_ON_RAW_IMAGE +#endif + +#define MEM_LAYOUT_ENV_SETTINGS \ + "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "fdt_addr_r=0x50200000\0" \ + "scriptaddr=0x50280000\0" \ + "ramdisk_addr_r=0x50300000\0" \ + "kernel_comp_addr_r=0x40200000\0" + +/* Enable Distro Boot */ +#ifndef CONFIG_SPL_BUILD +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 1) \ + func(MMC, mmc, 2) \ + func(USB, usb, 0) \ + func(DHCP, dhcp, na) +#include <config_distro_bootcmd.h> +#else +#define BOOTENV +#endif + +/* Initial environment variables */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + BOOTENV \ + MEM_LAYOUT_ENV_SETTINGS \ + "script=boot.scr\0" \ + "bootm_size=0x10000000\0" \ + "dev=2\0" \ + "preboot=gsc wd-disable\0" \ + "console=ttymxc1,115200\0" \ + "update_firmware=" \ + "tftpboot $loadaddr $image && " \ + "setexpr blkcnt $filesize + 0x1ff && " \ + "setexpr blkcnt $blkcnt / 0x200 && " \ + "mmc dev $dev && " \ + "mmc write $loadaddr 0x40 $blkcnt\0" \ + "loadfdt=" \ + "if $fsload $fdt_addr_r $dir/$fdt_file1; " \ + "then echo loaded $fdt_file1; " \ + "elif $fsload $fdt_addr_r $dir/$fdt_file2; " \ + "then echo loaded $fdt_file2; " \ + "elif $fsload $fdt_addr_r $dir/$fdt_file3; " \ + "then echo loaded $fdt_file3; " \ + "elif $fsload $fdt_addr_r $dir/$fdt_file4; " \ + "then echo loaded $fdt_file4; " \ + "elif $fsload $fdt_addr_r $dir/$fdt_file5; " \ + "then echo loaded $fdt_file5; " \ + "fi\0" \ + "boot_net=" \ + "setenv fsload tftpboot; " \ + "run loadfdt && tftpboot $kernel_addr_r $dir/Image && " \ + "booti $kernel_addr_r - $fdt_addr_r\0" \ + "update_rootfs=" \ + "tftpboot $loadaddr $image && " \ + "gzwrite mmc $dev $loadaddr $filesize 100000 1000000\0" \ + "update_all=" \ + "tftpboot $loadaddr $image && " \ + "gzwrite mmc $dev $loadaddr $filesize\0" \ + "erase_env=mmc dev $dev; mmc erase 0x7f08 0x40\0" + +#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 +#define CONFIG_SYS_INIT_RAM_SIZE SZ_2M +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +#define CONFIG_SYS_SDRAM_BASE 0x40000000 + +/* SDRAM configuration */ +#define PHYS_SDRAM 0x40000000 +#define PHYS_SDRAM_SIZE SZ_4G +#define CONFIG_SYS_BOOTM_LEN SZ_256M + +/* UART */ +#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR + +/* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE SZ_2K +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#endif diff --git a/include/configs/imx8mq_cm.h b/include/configs/imx8mq_cm.h index a3bb3c9..989486a 100644 --- a/include/configs/imx8mq_cm.h +++ b/include/configs/imx8mq_cm.h @@ -55,7 +55,7 @@ "initrd_addr=0x43800000\0" \ "bootm_size=0x10000000\0" \ "mmcpart=1\0" \ - "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcroot=/dev/mmcblk1p2 rootwait rw\0" \ /* Link Definitions */ @@ -66,7 +66,6 @@ #define CONFIG_SYS_INIT_SP_ADDR \ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) -#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ #define CONFIG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 diff --git a/include/configs/imx8mq_evk.h b/include/configs/imx8mq_evk.h index 94886fa..f7929e5 100644 --- a/include/configs/imx8mq_evk.h +++ b/include/configs/imx8mq_evk.h @@ -62,7 +62,7 @@ "initrd_addr=0x43800000\0" \ "bootm_size=0x10000000\0" \ "mmcpart=1\0" \ - "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcroot=/dev/mmcblk1p2 rootwait rw\0" \ /* Link Definitions */ @@ -73,7 +73,6 @@ #define CONFIG_SYS_INIT_SP_ADDR \ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) -#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ #define CONFIG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 diff --git a/include/configs/imx8mq_phanbell.h b/include/configs/imx8mq_phanbell.h index ef5992d..f641011 100644 --- a/include/configs/imx8mq_phanbell.h +++ b/include/configs/imx8mq_phanbell.h @@ -52,7 +52,7 @@ "initrd_high=0xffffffffffffffff\0" \ "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ "mmcpart=1\0" \ - "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcroot=/dev/mmcblk1p2 rootwait rw\0" \ "mmcautodetect=yes\0" \ "mmcargs=setenv bootargs console=${console} root=${mmcroot}\0 " \ "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ @@ -101,7 +101,6 @@ #define CONFIG_SYS_INIT_SP_ADDR \ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) -#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ #define CONFIG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 diff --git a/include/configs/imx8qm_mek.h b/include/configs/imx8qm_mek.h index a9c52d2..61d56e2 100644 --- a/include/configs/imx8qm_mek.h +++ b/include/configs/imx8qm_mek.h @@ -29,10 +29,6 @@ #define CONFIG_SPL_ABORT_ON_RAW_IMAGE #endif -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#define USDHC1_BASE_ADDR 0x5B010000 -#define USDHC2_BASE_ADDR 0x5B020000 - #ifdef CONFIG_AHAB_BOOT #define AHAB_ENV "sec_boot=yes\0" #else @@ -54,7 +50,7 @@ "initrd_high=0xffffffffffffffff\0" \ "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ "mmcpart=1\0" \ - "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcroot=/dev/mmcblk1p2 rootwait rw\0" \ "mmcautodetect=yes\0" \ "mmcargs=setenv bootargs console=${console} root=${mmcroot}\0 " \ "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ @@ -121,8 +117,6 @@ /* Default environment is in SD */ /* On LPDDR4 board, USDHC1 is for eMMC, USDHC2 is for SD on CPU board */ -#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ -#define CONFIG_SYS_FSL_USDHC_NUM 2 #define CONFIG_SYS_SDRAM_BASE 0x80000000 #define PHYS_SDRAM_1 0x80000000 diff --git a/include/configs/imx8qm_rom7720.h b/include/configs/imx8qm_rom7720.h index c7cace2..81ab5d8 100644 --- a/include/configs/imx8qm_rom7720.h +++ b/include/configs/imx8qm_rom7720.h @@ -66,7 +66,7 @@ "initrd_addr=0x83800000\0" \ "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ "mmcpart=1\0" \ - "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcroot=/dev/mmcblk2p2 rootwait rw\0" \ "mmcautodetect=yes\0" \ "mmcargs=setenv bootargs console=${console},${baudrate} root=${mmcroot} earlycon\0 " \ "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ @@ -114,7 +114,6 @@ * USDHC3 is for SD on base board On DDR4 board, USDHC1 is mux for NAND, * USDHC2 is for SD, USDHC3 is for SD on base board */ -#define CONFIG_MMCROOT "/dev/mmcblk2p2" /* USDHC3 */ #define CONFIG_SYS_FSL_USDHC_NUM 3 #define CONFIG_SYS_SDRAM_BASE 0x80000000 diff --git a/include/configs/imx8qxp_mek.h b/include/configs/imx8qxp_mek.h index 9052a91..26dc4de 100644 --- a/include/configs/imx8qxp_mek.h +++ b/include/configs/imx8qxp_mek.h @@ -27,10 +27,6 @@ #define CONFIG_SPL_ABORT_ON_RAW_IMAGE #endif -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#define USDHC1_BASE_ADDR 0x5B010000 -#define USDHC2_BASE_ADDR 0x5B020000 - #ifdef CONFIG_AHAB_BOOT #define AHAB_ENV "sec_boot=yes\0" #else @@ -52,7 +48,7 @@ "initrd_high=0xffffffffffffffff\0" \ "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ "mmcpart=1\0" \ - "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcroot=/dev/mmcblk1p2 rootwait rw\0" \ "mmcautodetect=yes\0" \ "mmcargs=setenv bootargs console=${console},${baudrate} root=${mmcroot}\0 " \ "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ @@ -119,8 +115,6 @@ /* Default environment is in SD */ /* On LPDDR4 board, USDHC1 is for eMMC, USDHC2 is for SD on CPU board */ -#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ -#define CONFIG_SYS_FSL_USDHC_NUM 2 #define CONFIG_SYS_SDRAM_BASE 0x80000000 #define PHYS_SDRAM_1 0x80000000 diff --git a/include/configs/imx8ulp_evk.h b/include/configs/imx8ulp_evk.h index f274b66..05df43b 100644 --- a/include/configs/imx8ulp_evk.h +++ b/include/configs/imx8ulp_evk.h @@ -56,7 +56,7 @@ "initrd_addr=0x83800000\0" \ "bootm_size=0x10000000\0" \ "mmcpart=1\0" \ - "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcroot=/dev/mmcblk2p2 rootwait rw\0" \ /* Link Definitions */ @@ -65,7 +65,6 @@ #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) -#define CONFIG_MMCROOT "/dev/mmcblk2p2" #define CONFIG_SYS_SDRAM_BASE 0x80000000 #define PHYS_SDRAM 0x80000000 diff --git a/include/configs/liteboard.h b/include/configs/liteboard.h index d0960bc..fdea724 100644 --- a/include/configs/liteboard.h +++ b/include/configs/liteboard.h @@ -35,7 +35,7 @@ "ip_dyn=yes\0" \ "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ "mmcpart=1\0" \ - "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \ "mmcautodetect=yes\0" \ "mmcargs=setenv bootargs console=${console},${baudrate} " \ "root=${mmcroot}\0" \ @@ -100,7 +100,6 @@ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) /* FLASH and environment organization */ -#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USB Configs */ #ifdef CONFIG_CMD_USB @@ -113,7 +112,6 @@ #ifdef CONFIG_CMD_NET #define CONFIG_FEC_ENET_DEV 0 -#define IMX_FEC_BASE ENET_BASE_ADDR #define CONFIG_FEC_MXC_PHYADDR 0x0 #endif diff --git a/include/configs/m53menlo.h b/include/configs/m53menlo.h index 5bd6cbe..90877f5 100644 --- a/include/configs/m53menlo.h +++ b/include/configs/m53menlo.h @@ -69,7 +69,6 @@ * Ethernet on SOC (FEC) */ #ifdef CONFIG_CMD_NET -#define IMX_FEC_BASE FEC_BASE_ADDR #define CONFIG_FEC_MXC_PHYADDR 0x0 #endif diff --git a/include/configs/mccmon6.h b/include/configs/mccmon6.h index 5918429..dcce52e 100644 --- a/include/configs/mccmon6.h +++ b/include/configs/mccmon6.h @@ -40,7 +40,6 @@ #define CONFIG_SYS_FLASH_BANKS_SIZES { (32 * SZ_1M) } /* Ethernet Configuration */ -#define IMX_FEC_BASE ENET_BASE_ADDR #define CONFIG_FEC_MXC_PHYADDR 1 #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/mx6sllevk.h b/include/configs/mx6sllevk.h index 0793028..1b32f58 100644 --- a/include/configs/mx6sllevk.h +++ b/include/configs/mx6sllevk.h @@ -25,7 +25,7 @@ "ip_dyn=yes\0" \ "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ "mmcpart=1\0" \ - "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \ "mmcautodetect=yes\0" \ "mmcargs=setenv bootargs console=${console},${baudrate} " \ "root=${mmcroot}\0" \ @@ -92,7 +92,6 @@ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) /* Environment organization */ -#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */ /* MMC Configs */ #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h index b679d13..76e3dc8 100644 --- a/include/configs/mx6sxsabresd.h +++ b/include/configs/mx6sxsabresd.h @@ -126,7 +126,6 @@ /* Network */ -#define IMX_FEC_BASE ENET_BASE_ADDR #define CONFIG_FEC_MXC_PHYADDR 0x1 #ifdef CONFIG_CMD_USB @@ -149,6 +148,4 @@ #endif #endif -#define CONFIG_SYS_FSL_USDHC_NUM 3 - #endif /* __CONFIG_H */ diff --git a/include/configs/mx6ul_14x14_evk.h b/include/configs/mx6ul_14x14_evk.h index 17e7ae0..03d799c 100644 --- a/include/configs/mx6ul_14x14_evk.h +++ b/include/configs/mx6ul_14x14_evk.h @@ -47,7 +47,7 @@ "videomode=video=ctfb:x:480,y:272,depth:24,pclk:108695,le:8,ri:4,up:2,lo:4,hs:41,vs:10,sync:0,vmode:0\0" \ "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ "mmcpart=1\0" \ - "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcroot=/dev/mmcblk1p2 rootwait rw\0" \ "mmcautodetect=yes\0" \ "mmcargs=setenv bootargs console=${console},${baudrate} " \ "root=${mmcroot}\0" \ @@ -121,7 +121,6 @@ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) /* environment organization */ -#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ /* USB Configs */ #ifdef CONFIG_CMD_USB @@ -135,10 +134,8 @@ #define CONFIG_FEC_ENET_DEV 1 #if (CONFIG_FEC_ENET_DEV == 0) -#define IMX_FEC_BASE ENET_BASE_ADDR #define CONFIG_FEC_MXC_PHYADDR 0x2 #elif (CONFIG_FEC_ENET_DEV == 1) -#define IMX_FEC_BASE ENET2_BASE_ADDR #define CONFIG_FEC_MXC_PHYADDR 0x1 #endif #endif diff --git a/include/configs/mx6ullevk.h b/include/configs/mx6ullevk.h index dfcdc00..bc494b4 100644 --- a/include/configs/mx6ullevk.h +++ b/include/configs/mx6ullevk.h @@ -43,7 +43,7 @@ "videomode=video=ctfb:x:480,y:272,depth:24,pclk:108695,le:8,ri:4,up:2,lo:4,hs:41,vs:10,sync:0,vmode:0\0" \ "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ "mmcpart=1\0" \ - "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcroot=/dev/mmcblk1p2 rootwait rw\0" \ "mmcautodetect=yes\0" \ "mmcargs=setenv bootargs console=${console},${baudrate} " \ "root=${mmcroot}\0" \ @@ -118,7 +118,6 @@ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) /* environment organization */ -#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ #define CONFIG_IOMUX_LPSR diff --git a/include/configs/mx7dsabresd.h b/include/configs/mx7dsabresd.h index d411b1a..aaad232 100644 --- a/include/configs/mx7dsabresd.h +++ b/include/configs/mx7dsabresd.h @@ -14,9 +14,6 @@ #define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR -/* MMC Config*/ -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 - #ifdef CONFIG_IMX_BOOTAUX /* Set to QSPI1 A flash at default */ #define CONFIG_SYS_AUXCORE_BOOTDATA 0x60000000 @@ -111,12 +108,6 @@ /* DMA stuff, needed for GPMI/MXS NAND support */ #endif -#ifdef CONFIG_NAND_MXS -#define CONFIG_SYS_FSL_USDHC_NUM 1 -#else -#define CONFIG_SYS_FSL_USDHC_NUM 2 -#endif - /* USB Configs */ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) diff --git a/include/configs/mx7ulp_com.h b/include/configs/mx7ulp_com.h index ce6afcd..f8a5009 100644 --- a/include/configs/mx7ulp_com.h +++ b/include/configs/mx7ulp_com.h @@ -17,8 +17,6 @@ #define CONFIG_SYS_BOOTM_LEN 0x1000000 -#define CONFIG_MMCROOT "/dev/mmcblk0p2" - /* Using ULP WDOG for reset */ #define WDOG_BASE_ADDR WDG1_RBASE @@ -41,7 +39,7 @@ "fdt_addr=0x63000000\0" \ "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ "mmcpart=1\0" \ - "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \ "mmcargs=setenv bootargs console=${console},${baudrate} " \ "root=${mmcroot}\0" \ "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ diff --git a/include/configs/mx7ulp_evk.h b/include/configs/mx7ulp_evk.h index e80d748..7644274 100644 --- a/include/configs/mx7ulp_evk.h +++ b/include/configs/mx7ulp_evk.h @@ -13,7 +13,6 @@ #define CONFIG_SYS_BOOTM_LEN 0x1000000 -#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */ /* Using ULP WDOG for reset */ #define WDOG_BASE_ADDR WDG1_RBASE @@ -47,7 +46,7 @@ "ip_dyn=yes\0" \ "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ "mmcpart=1\0" \ - "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \ "mmcautodetect=yes\0" \ "mmcargs=setenv bootargs console=${console},${baudrate} " \ "root=${mmcroot}\0" \ diff --git a/include/configs/npi_imx6ull.h b/include/configs/npi_imx6ull.h index 1e40fad..c250fa6 100644 --- a/include/configs/npi_imx6ull.h +++ b/include/configs/npi_imx6ull.h @@ -46,7 +46,6 @@ #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #ifdef CONFIG_CMD_NET -#define IMX_FEC_BASE ENET_BASE_ADDR #define CONFIG_FEC_MXC_PHYADDR 0x1 #endif diff --git a/include/configs/phycore_imx8mm.h b/include/configs/phycore_imx8mm.h index 7438d0a..71f0c42 100644 --- a/include/configs/phycore_imx8mm.h +++ b/include/configs/phycore_imx8mm.h @@ -77,7 +77,6 @@ #define CONFIG_SYS_INIT_SP_ADDR \ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) -#define CONFIG_MMCROOT "/dev/mmcblk2p2" /* USDHC3 */ #define CONFIG_SYS_SDRAM_BASE 0x40000000 @@ -92,8 +91,4 @@ #define CONFIG_SYS_MAXARGS 64 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -/* USDHC */ -#define CONFIG_SYS_FSL_USDHC_NUM 2 -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 - #endif /* __PHYCORE_IMX8MM_H */ diff --git a/include/configs/phycore_imx8mp.h b/include/configs/phycore_imx8mp.h index 8c5ffee..0c963b6 100644 --- a/include/configs/phycore_imx8mp.h +++ b/include/configs/phycore_imx8mp.h @@ -77,7 +77,6 @@ #define CONFIG_SYS_INIT_SP_ADDR \ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) -#define CONFIG_MMCROOT "/dev/mmcblk2p2" /* USDHC3 */ #define CONFIG_SYS_SDRAM_BASE 0x40000000 @@ -92,8 +91,4 @@ #define CONFIG_SYS_MAXARGS 64 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -/* USDHC */ -#define CONFIG_SYS_FSL_USDHC_NUM 2 -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 - #endif /* __PHYCORE_IMX8MP_H */ diff --git a/include/configs/pico-imx6.h b/include/configs/pico-imx6.h index 855d799..c288908 100644 --- a/include/configs/pico-imx6.h +++ b/include/configs/pico-imx6.h @@ -117,7 +117,6 @@ /* Environment organization */ /* Ethernet Configuration */ -#define IMX_FEC_BASE ENET_BASE_ADDR #define CONFIG_FEC_MXC_PHYADDR 1 /* Framebuffer */ diff --git a/include/configs/pico-imx6ul.h b/include/configs/pico-imx6ul.h index 39be433..1f111ea 100644 --- a/include/configs/pico-imx6ul.h +++ b/include/configs/pico-imx6ul.h @@ -27,7 +27,6 @@ /* Network support */ -#define IMX_FEC_BASE ENET2_BASE_ADDR #define CONFIG_FEC_MXC_PHYADDR 0x1 #define CONFIG_MXC_UART_BASE UART6_BASE_ADDR diff --git a/include/configs/pico-imx8mq.h b/include/configs/pico-imx8mq.h index 495fddf..9584527 100644 --- a/include/configs/pico-imx8mq.h +++ b/include/configs/pico-imx8mq.h @@ -46,7 +46,7 @@ "initrd_high=0xffffffffffffffff\0" \ "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ "mmcpart=1\0" \ - "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcroot=/dev/mmcblk1p2 rootwait rw\0" \ "mmcautodetect=yes\0" \ "mmcargs=setenv bootargs console=${console} root=${mmcroot}\0 " \ "loadbootscript=" \ @@ -80,7 +80,6 @@ #define CONFIG_SYS_INIT_SP_ADDR \ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) -#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ #define CONFIG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 diff --git a/include/configs/pxa-common.h b/include/configs/pxa-common.h deleted file mode 100644 index 7a78f98..0000000 --- a/include/configs/pxa-common.h +++ /dev/null @@ -1,27 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Toradex Colibri PXA270 configuration file - * - * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com> - */ - -#ifndef __CONFIG_PXA_COMMON_H__ -#define __CONFIG_PXA_COMMON_H__ - -/* - * OHCI USB - */ -#ifdef CONFIG_CMD_USB -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_CPU_INIT -#define CONFIG_SYS_USB_OHCI_BOARD_INIT -#ifdef CONFIG_CPU_PXA27X -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3 -#else -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 -#endif -#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x4c000000 -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "pxa-ohci" -#endif - -#endif /* __CONFIG_PXA_COMMON_H__ */ diff --git a/include/configs/somlabs_visionsom_6ull.h b/include/configs/somlabs_visionsom_6ull.h index 9946fe9..d476129 100644 --- a/include/configs/somlabs_visionsom_6ull.h +++ b/include/configs/somlabs_visionsom_6ull.h @@ -78,7 +78,6 @@ #endif #ifdef CONFIG_CMD_NET -#define IMX_FEC_BASE ENET_BASE_ADDR #define CONFIG_FEC_MXC_PHYADDR 0x1 #endif diff --git a/include/configs/tqma6.h b/include/configs/tqma6.h index c11e5c1..e0cd1ec 100644 --- a/include/configs/tqma6.h +++ b/include/configs/tqma6.h @@ -55,7 +55,6 @@ #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ -#define IMX_FEC_BASE ENET_BASE_ADDR #if defined(CONFIG_TQMA6X_MMC_BOOT) diff --git a/include/configs/verdin-imx8mm.h b/include/configs/verdin-imx8mm.h index 6c5b190..da3dc95 100644 --- a/include/configs/verdin-imx8mm.h +++ b/include/configs/verdin-imx8mm.h @@ -52,17 +52,12 @@ MEM_LAYOUT_ENV_SETTINGS \ "bootcmd_mfg=fastboot 0\0" \ "boot_file=Image\0" \ + "boot_script_dhcp=boot.scr\0" \ "console=ttymxc0\0" \ "fdt_addr=0x43000000\0" \ "fdt_board=dev\0" \ "initrd_addr=0x43800000\0" \ "initrd_high=0xffffffffffffffff\0" \ - "netargs=setenv bootargs console=${console},${baudrate} " \ - "root=/dev/nfs ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp" \ - "\0" \ - "nfsboot=run netargs; dhcp ${loadaddr} ${boot_file}; " \ - "tftp ${fdt_addr} verdin/${fdtfile}; " \ - "booti ${loadaddr} - ${fdt_addr}\0" \ "setup=setenv setupargs console=${console},${baudrate} " \ "console=tty1 consoleblank=0 earlycon\0" \ "update_uboot=askenv confirm Did you load flash.bin (y/N)?; " \ @@ -97,9 +92,6 @@ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ sizeof(CONFIG_SYS_PROMPT) + 16) -/* USDHC */ -#define CONFIG_SYS_FSL_USDHC_NUM 2 -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 /* ENET */ #define CONFIG_FEC_MXC_PHYADDR 7 diff --git a/include/configs/verdin-imx8mp.h b/include/configs/verdin-imx8mp.h index 9e29dc1..7b74077 100644 --- a/include/configs/verdin-imx8mp.h +++ b/include/configs/verdin-imx8mp.h @@ -76,12 +76,6 @@ "fdt_board=dev\0" \ "initrd_addr=0x43800000\0" \ "initrd_high=0xffffffffffffffff\0" \ - "netargs=setenv bootargs console=${console},${baudrate} " \ - "root=/dev/nfs ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp" \ - "\0" \ - "nfsboot=run netargs; dhcp ${loadaddr} ${boot_file}; " \ - "tftp ${fdt_addr} verdin/${fdtfile}; " \ - "booti ${loadaddr} - ${fdt_addr}\0" \ "setup=setenv setupargs console=${console},${baudrate} console=tty1 " \ "consoleblank=0 earlycon\0" \ "update_uboot=askenv confirm Did you load flash.bin (y/N)?; " \ @@ -116,8 +110,4 @@ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ sizeof(CONFIG_SYS_PROMPT) + 16) -/* USDHC */ -#define CONFIG_SYS_FSL_USDHC_NUM 2 -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 - #endif /* __VERDIN_IMX8MP_H */ diff --git a/include/configs/vf610twr.h b/include/configs/vf610twr.h index db7c8be..ec9049e 100644 --- a/include/configs/vf610twr.h +++ b/include/configs/vf610twr.h @@ -23,7 +23,6 @@ #define CONFIG_SYS_FSL_ESDHC_ADDR 0 #define CONFIG_SYS_FSL_ESDHC_NUM 1 -#define IMX_FEC_BASE ENET_BASE_ADDR #define CONFIG_FEC_MXC_PHYADDR 0 /* I2C Configs */ diff --git a/include/configs/vining_2000.h b/include/configs/vining_2000.h index e101739..e7d4fd16 100644 --- a/include/configs/vining_2000.h +++ b/include/configs/vining_2000.h @@ -44,7 +44,6 @@ #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 /* Network */ -#define IMX_FEC_BASE ENET_BASE_ADDR #define CONFIG_FEC_MXC_PHYADDR 0x0 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET diff --git a/include/configs/xpress.h b/include/configs/xpress.h index 13cfa2c..bd39b32 100644 --- a/include/configs/xpress.h +++ b/include/configs/xpress.h @@ -34,7 +34,6 @@ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) /* Environment is in stored in the eMMC boot partition */ -#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC2 */ /* USB Configs */ #define CONFIG_EHCI_HCD_INIT_AFTER_RESET @@ -43,7 +42,6 @@ #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_FEC_ENET_DEV 0 -#define IMX_FEC_BASE ENET_BASE_ADDR #define CONFIG_FEC_MXC_PHYADDR 0x0 #define CONFIG_UBOOT_SECTOR_START 0x2 @@ -61,7 +59,7 @@ "ip_dyn=yes\0" \ "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ "mmcpart=1\0" \ - "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \ "mmcautodetect=yes\0" \ "mmcargs=setenv bootargs console=${console},${baudrate} " \ "root=${mmcroot}\0" \ diff --git a/include/dt-bindings/power/imx8mp-power.h b/include/dt-bindings/power/imx8mp-power.h new file mode 100644 index 0000000..3f72bf7 --- /dev/null +++ b/include/dt-bindings/power/imx8mp-power.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +/* + * Copyright (C) 2020 Pengutronix, Sascha Hauer <kernel@pengutronix.de> + */ + +#ifndef __DT_BINDINGS_IMX8MP_POWER_DOMAIN_POWER_H__ +#define __DT_BINDINGS_IMX8MP_POWER_DOMAIN_POWER_H__ + +#define IMX8MP_POWER_DOMAIN_MIPI_PHY1 0 +#define IMX8MP_POWER_DOMAIN_PCIE_PHY 1 +#define IMX8MP_POWER_DOMAIN_USB1_PHY 2 +#define IMX8MP_POWER_DOMAIN_USB2_PHY 3 +#define IMX8MP_POWER_DOMAIN_MLMIX 4 +#define IMX8MP_POWER_DOMAIN_AUDIOMIX 5 +#define IMX8MP_POWER_DOMAIN_GPU2D 6 +#define IMX8MP_POWER_DOMAIN_GPUMIX 7 +#define IMX8MP_POWER_DOMAIN_VPUMIX 8 +#define IMX8MP_POWER_DOMAIN_GPU3D 9 +#define IMX8MP_POWER_DOMAIN_MEDIAMIX 10 +#define IMX8MP_POWER_DOMAIN_VPU_G1 11 +#define IMX8MP_POWER_DOMAIN_VPU_G2 12 +#define IMX8MP_POWER_DOMAIN_VPU_VC8000E 13 +#define IMX8MP_POWER_DOMAIN_HDMIMIX 14 +#define IMX8MP_POWER_DOMAIN_HDMI_PHY 15 +#define IMX8MP_POWER_DOMAIN_MIPI_PHY2 16 +#define IMX8MP_POWER_DOMAIN_HSIOMIX 17 +#define IMX8MP_POWER_DOMAIN_MEDIAMIX_ISPDWP 18 + +#define IMX8MP_HSIOBLK_PD_USB 0 +#define IMX8MP_HSIOBLK_PD_USB_PHY1 1 +#define IMX8MP_HSIOBLK_PD_USB_PHY2 2 +#define IMX8MP_HSIOBLK_PD_PCIE 3 +#define IMX8MP_HSIOBLK_PD_PCIE_PHY 4 + +#define IMX8MP_MEDIABLK_PD_MIPI_DSI_1 0 +#define IMX8MP_MEDIABLK_PD_MIPI_CSI2_1 1 +#define IMX8MP_MEDIABLK_PD_LCDIF_1 2 +#define IMX8MP_MEDIABLK_PD_ISI 3 +#define IMX8MP_MEDIABLK_PD_MIPI_CSI2_2 4 +#define IMX8MP_MEDIABLK_PD_LCDIF_2 5 +#define IMX8MP_MEDIABLK_PD_ISP2 6 +#define IMX8MP_MEDIABLK_PD_ISP1 7 +#define IMX8MP_MEDIABLK_PD_DWE 8 +#define IMX8MP_MEDIABLK_PD_MIPI_DSI_2 9 + +#endif diff --git a/include/power-domain.h b/include/power-domain.h index 113276b..2ff6c77 100644 --- a/include/power-domain.h +++ b/include/power-domain.h @@ -108,6 +108,27 @@ int power_domain_get_by_index(struct udevice *dev, #endif /** + * power_domain_get_by_name - Get the named power domain for a device. + * + * @dev: The client device. + * @power_domain: A pointer to a power domain struct to initialize. + * @name: Power domain name to be powered on. + * + * Return: 0 if OK, or a negative error code. + */ +#if CONFIG_IS_ENABLED(POWER_DOMAIN) +int power_domain_get_by_name(struct udevice *dev, + struct power_domain *power_domain, const char *name); +#else +static inline +int power_domain_get_by_name(struct udevice *dev, + struct power_domain *power_domain, const char *name) +{ + return -ENOSYS; +} +#endif + +/** * power_domain_free - Free a previously requested power domain. * * @power_domain: A power domain struct that was previously successfully diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 0c3c0b3..bddf9b1 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -316,7 +316,6 @@ CONFIG_HUSH_INIT_VAR CONFIG_HWCONFIG CONFIG_HW_ENV_SETTINGS CONFIG_I2C_ENV_EEPROM_BUS -CONFIG_I2C_GSC CONFIG_I2C_MULTI_BUS CONFIG_I2C_MVTWSI CONFIG_I2C_MVTWSI_BASE @@ -417,7 +416,6 @@ CONFIG_MII_DEFAULT_TSEC CONFIG_MISC_COMMON CONFIG_MIU_2BIT_21_7_INTERLEAVED CONFIG_MIU_2BIT_INTERLEAVED -CONFIG_MMCROOT CONFIG_MMC_DEFAULT_DEV CONFIG_MMC_SUNXI_SLOT CONFIG_MONITOR_IS_IN_RAM @@ -522,9 +520,6 @@ CONFIG_PPC_SPINTABLE_COMPATIBLE CONFIG_PRAM CONFIG_PSRAM_SCFG CONFIG_PWM -CONFIG_PXA_LCD -CONFIG_PXA_PWR_I2C -CONFIG_PXA_STD_I2C CONFIG_PXA_VGA CONFIG_QBMAN_CLK_DIV CONFIG_RAMBOOT_NAND @@ -711,14 +706,12 @@ CONFIG_SYS_CACHE_DCACR CONFIG_SYS_CACHE_ICACR CONFIG_SYS_CACHE_STASHING CONFIG_SYS_CBSIZE -CONFIG_SYS_CCCR CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR_PHYS_HIGH CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSR_DO_NOT_RELOCATE CONFIG_SYS_CFI_FLASH_STATUS_POLL -CONFIG_SYS_CKEN CONFIG_SYS_CLK CONFIG_SYS_CLKTL_CBCDR CONFIG_SYS_CORE_SRAM @@ -903,7 +896,6 @@ CONFIG_SYS_DPAA_DCE CONFIG_SYS_DPAA_FMAN CONFIG_SYS_DPAA_PME CONFIG_SYS_DPAA_RMAN -CONFIG_SYS_DRAM_BASE CONFIG_SYS_DRAM_SIZE CONFIG_SYS_DRAM_TEST CONFIG_SYS_DSPI_CTAR0 @@ -953,7 +945,6 @@ CONFIG_SYS_FLASH_SECT_SZ CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH_UNLOCK_TOUT CONFIG_SYS_FLASH_WRITE_TOUT -CONFIG_SYS_FLYCNFG_VAL CONFIG_SYS_FM1_10GEC1_PHY_ADDR CONFIG_SYS_FM1_CLK CONFIG_SYS_FM1_DTSEC1_PHY_ADDR @@ -1171,14 +1162,6 @@ CONFIG_SYS_FTSDMC021_CR2 CONFIG_SYS_FTSDMC021_TP1 CONFIG_SYS_FTSDMC021_TP2 CONFIG_SYS_FTSMC020_CONFIGS -CONFIG_SYS_GAFR0_L_VAL -CONFIG_SYS_GAFR0_U_VAL -CONFIG_SYS_GAFR1_L_VAL -CONFIG_SYS_GAFR1_U_VAL -CONFIG_SYS_GAFR2_L_VAL -CONFIG_SYS_GAFR2_U_VAL -CONFIG_SYS_GAFR3_L_VAL -CONFIG_SYS_GAFR3_U_VAL CONFIG_SYS_GBL_DATA_OFFSET CONFIG_SYS_GBL_DATA_SIZE CONFIG_SYS_GIC400_ADDR @@ -1186,14 +1169,6 @@ CONFIG_SYS_GP1DIR CONFIG_SYS_GP1ODR CONFIG_SYS_GP2DIR CONFIG_SYS_GP2ODR -CONFIG_SYS_GPCR0_VAL -CONFIG_SYS_GPCR1_VAL -CONFIG_SYS_GPCR2_VAL -CONFIG_SYS_GPCR3_VAL -CONFIG_SYS_GPDR0_VAL -CONFIG_SYS_GPDR1_VAL -CONFIG_SYS_GPDR2_VAL -CONFIG_SYS_GPDR3_VAL CONFIG_SYS_GPIO1_EN CONFIG_SYS_GPIO1_FUNC CONFIG_SYS_GPIO1_LED @@ -1202,10 +1177,6 @@ CONFIG_SYS_GPIO_EN CONFIG_SYS_GPIO_FUNC CONFIG_SYS_GPIO_OUT CONFIG_SYS_GPR1 -CONFIG_SYS_GPSR0_VAL -CONFIG_SYS_GPSR1_VAL -CONFIG_SYS_GPSR2_VAL -CONFIG_SYS_GPSR3_VAL CONFIG_SYS_HALT_BEFOR_RAM_JUMP CONFIG_SYS_HMI_BASE CONFIG_SYS_HZ_CLOCK @@ -1230,7 +1201,6 @@ CONFIG_SYS_I2C_PCA9557_ADDR CONFIG_SYS_I2C_PINMUX_CLR CONFIG_SYS_I2C_PINMUX_REG CONFIG_SYS_I2C_PINMUX_SET -CONFIG_SYS_I2C_PXA CONFIG_SYS_I2C_RTC_ADDR CONFIG_SYS_I2C_TCA642X_ADDR CONFIG_SYS_I2C_TCA642X_BUS_NUM @@ -1313,22 +1283,14 @@ CONFIG_SYS_MAX_NAND_CHIPS CONFIG_SYS_MAX_NAND_DEVICE CONFIG_SYS_MBAR CONFIG_SYS_MBAR2 -CONFIG_SYS_MCATT0_VAL -CONFIG_SYS_MCATT1_VAL CONFIG_SYS_MCFRRTC_BASE -CONFIG_SYS_MCIO0_VAL -CONFIG_SYS_MCIO1_VAL CONFIG_SYS_MCKR CONFIG_SYS_MCKR1_VAL CONFIG_SYS_MCKR2_VAL CONFIG_SYS_MCKR_CSS -CONFIG_SYS_MCMEM0_VAL -CONFIG_SYS_MCMEM1_VAL CONFIG_SYS_MDCNFG_VAL CONFIG_SYS_MDIO1_OFFSET -CONFIG_SYS_MDMRS_VAL CONFIG_SYS_MDREFR_VAL -CONFIG_SYS_MECR_VAL CONFIG_SYS_MEMAC_LITTLE_ENDIAN CONFIG_SYS_MEMORY_BASE CONFIG_SYS_MEMORY_SIZE @@ -1417,9 +1379,6 @@ CONFIG_SYS_MPC8xxx_DDR_OFFSET CONFIG_SYS_MPC8xxx_PIC_ADDR CONFIG_SYS_MRAM_BASE CONFIG_SYS_MRAM_SIZE -CONFIG_SYS_MSC0_VAL -CONFIG_SYS_MSC1_VAL -CONFIG_SYS_MSC2_VAL CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST CONFIG_SYS_NAND_AMASK CONFIG_SYS_NAND_BASE @@ -1621,7 +1580,6 @@ CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PME_CLK CONFIG_SYS_POST_MEMORY CONFIG_SYS_POST_MEM_REGIONS -CONFIG_SYS_PSSR_VAL CONFIG_SYS_PTV CONFIG_SYS_PUAPAR CONFIG_SYS_QMAN_CENA_BASE @@ -1760,7 +1718,6 @@ CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS CONFIG_SYS_SST_SECT CONFIG_SYS_SST_SECTSZ CONFIG_SYS_STACK_SIZE -CONFIG_SYS_SXCNFG_VAL CONFIG_SYS_TBIPA_VALUE CONFIG_SYS_TCLK CONFIG_SYS_TIMERBASE |