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-rw-r--r--arch/arm/dts/k3-am654-base-board-ddr4-1600MTs.dtsi30
-rw-r--r--arch/arm/dts/k3-am654-ddr.dtsi9
-rw-r--r--drivers/ram/k3-am654-ddrss.c55
-rw-r--r--drivers/ram/k3-am654-ddrss.h10
4 files changed, 85 insertions, 19 deletions
diff --git a/arch/arm/dts/k3-am654-base-board-ddr4-1600MTs.dtsi b/arch/arm/dts/k3-am654-base-board-ddr4-1600MTs.dtsi
index e861cb7..d07aaea 100644
--- a/arch/arm/dts/k3-am654-base-board-ddr4-1600MTs.dtsi
+++ b/arch/arm/dts/k3-am654-base-board-ddr4-1600MTs.dtsi
@@ -1,15 +1,16 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
- * This file was generated by the AM65x_DRA80xM EMIF Tool:
+ * This file was generated by AM65x_DRA80xM_EMIF_Tool_1.98.xlsm
* http://www.ti.com/lit/pdf/spracj0
* Configuration Parameters
* Memory Type: DDR4
- * Data Rate: 1600
+ * Data Rate: 1600 MT/s
* ECC Enabled: No
- * Data Width: 32
+ * Data Width: 32 bits
*/
#define DDR_PLL_FREQUENCY 400000000
+#define DDRSS_V2H_CTL_REG 0x000073FF
#define DDRCTL_MSTR 0x41040010
#define DDRCTL_RFSHCTL0 0x00210070
#define DDRCTL_ECCCFG0 0x00000000
@@ -32,10 +33,10 @@
#define DDRCTL_DRAMTMG5 0x04040302
#define DDRCTL_DRAMTMG6 0x00000004
#define DDRCTL_DRAMTMG7 0x00000404
-#define DDRCTL_DRAMTMG8 0x03030C05
+#define DDRCTL_DRAMTMG8 0x03030A05
#define DDRCTL_DRAMTMG9 0x00020208
#define DDRCTL_DRAMTMG10 0x001C180A
-#define DDRCTL_DRAMTMG11 0x1106010E
+#define DDRCTL_DRAMTMG11 0x0E06010E
#define DDRCTL_DRAMTMG12 0x00020008
#define DDRCTL_DRAMTMG13 0x0B100002
#define DDRCTL_DRAMTMG14 0x00000000
@@ -47,7 +48,7 @@
#define DDRCTL_DFITMG1 0x000A0606
#define DDRCTL_DFITMG2 0x00000604
#define DDRCTL_DFIMISC 0x00000001
-#define DDRCTL_ADDRMAP0 0x001F1F1F
+#define DDRCTL_ADDRMAP0 0x0000001F
#define DDRCTL_ADDRMAP1 0x003F0808
#define DDRCTL_ADDRMAP2 0x00000000
#define DDRCTL_ADDRMAP3 0x00000000
@@ -83,13 +84,13 @@
#define DDRPHY_DCR 0x0000040C
#define DDRPHY_DTPR0 0x041A0B06
#define DDRPHY_DTPR1 0x28140000
-#define DDRPHY_DTPR2 0x0034E300
-#define DDRPHY_DTPR3 0x02800800
+#define DDRPHY_DTPR2 0x0034E255
+#define DDRPHY_DTPR3 0x01D50800
#define DDRPHY_DTPR4 0x31180805
#define DDRPHY_DTPR5 0x00250B06
#define DDRPHY_DTPR6 0x00000505
#define DDRPHY_ZQCR 0x008A2A58
-#define DDRPHY_ZQ0PR0 0x000077DD
+#define DDRPHY_ZQ0PR0 0x000077DD
#define DDRPHY_ZQ1PR0 0x000077DD
#define DDRPHY_MR0 0x00000214
#define DDRPHY_MR1 0x00000501
@@ -109,6 +110,8 @@
#define DDRPHY_DX8SL2PLLCR0 0x021c4000
#define DDRPHY_DTCR0 0x8000B1C7
#define DDRPHY_DTCR1 0x00010236
+#define DDRPHY_ACIOCR0 0x30070000
+#define DDRPHY_ACIOCR3 0x00000001
#define DDRPHY_ACIOCR5 0x04800000
#define DDRPHY_IOVCR0 0x0F0C0C0C
#define DDRPHY_DX0GCR0 0x00000000
@@ -148,9 +151,12 @@
#define DDRPHY_DX3GTR0 0x00020002
#define DDRPHY_DX4GTR0 0x00020002
#define DDRPHY_ODTCR 0x00010000
-#define DDRPHY_DX8SL0IOCR 0x04800000
-#define DDRPHY_DX8SL1IOCR 0x04800000
-#define DDRPHY_DX8SL2IOCR 0x04800000
+#define DDRPHY_DX8SL0IOCR 0x74800000
+#define DDRPHY_DX8SL1IOCR 0x74800000
+#define DDRPHY_DX8SL2IOCR 0x74800000
#define DDRPHY_DX8SL0DXCTL2 0x00141830
#define DDRPHY_DX8SL1DXCTL2 0x00141830
#define DDRPHY_DX8SL2DXCTL2 0x00141830
+#define DDRPHY_DX8SL0DQSCTL 0x01264000
+#define DDRPHY_DX8SL1DQSCTL 0x01264000
+#define DDRPHY_DX8SL2DQSCTL 0x01264000
diff --git a/arch/arm/dts/k3-am654-ddr.dtsi b/arch/arm/dts/k3-am654-ddr.dtsi
index 622a3ed..b228796 100644
--- a/arch/arm/dts/k3-am654-ddr.dtsi
+++ b/arch/arm/dts/k3-am654-ddr.dtsi
@@ -17,6 +17,10 @@
assigned-clock-rates = <DDR_PLL_FREQUENCY>;
u-boot,dm-spl;
+ ti,ss-reg = <
+ DDRSS_V2H_CTL_REG
+ >;
+
ti,ctl-reg = <
DDRCTL_DFIMISC
DDRCTL_DFITMG0
@@ -132,12 +136,15 @@
DDRPHY_DX8SL0DXCTL2
DDRPHY_DX8SL0IOCR
DDRPHY_DX8SL0PLLCR0
+ DDRPHY_DX8SL0DQSCTL
DDRPHY_DX8SL1DXCTL2
DDRPHY_DX8SL1IOCR
DDRPHY_DX8SL1PLLCR0
+ DDRPHY_DX8SL1DQSCTL
DDRPHY_DX8SL2DXCTL2
DDRPHY_DX8SL2IOCR
DDRPHY_DX8SL2PLLCR0
+ DDRPHY_DX8SL2DQSCTL
DDRPHY_DXCCR
DDRPHY_ODTCR
DDRPHY_PGCR0
@@ -168,6 +175,8 @@
>;
ti,phy-ioctl = <
+ DDRPHY_ACIOCR0
+ DDRPHY_ACIOCR3
DDRPHY_ACIOCR5
DDRPHY_IOVCR0
>;
diff --git a/drivers/ram/k3-am654-ddrss.c b/drivers/ram/k3-am654-ddrss.c
index 100cb9f..7015d8c 100644
--- a/drivers/ram/k3-am654-ddrss.c
+++ b/drivers/ram/k3-am654-ddrss.c
@@ -259,6 +259,8 @@ static void am654_ddrss_phy_configuration(struct am654_ddrss_desc *ddrss)
ddrss_phy_writel(DDRSS_DDRPHY_DTCR0, ctrl->ddrphy_dtcr0);
ddrss_phy_writel(DDRSS_DDRPHY_DTCR1, ctrl->ddrphy_dtcr1);
+ ddrss_phy_writel(DDRSS_DDRPHY_ACIOCR0, ioctl->ddrphy_aciocr0);
+ ddrss_phy_writel(DDRSS_DDRPHY_ACIOCR3, ioctl->ddrphy_aciocr3);
ddrss_phy_writel(DDRSS_DDRPHY_ACIOCR5, ioctl->ddrphy_aciocr5);
ddrss_phy_writel(DDRSS_DDRPHY_IOVCR0, ioctl->ddrphy_iovcr0);
@@ -294,6 +296,10 @@ static void am654_ddrss_phy_configuration(struct am654_ddrss_desc *ddrss)
ddrss_phy_writel(DDRSS_DDRPHY_DX8SL1DXCTL2, cfg->ddrphy_dx8sl1dxctl2);
ddrss_phy_writel(DDRSS_DDRPHY_DX8SL2DXCTL2, cfg->ddrphy_dx8sl2dxctl2);
+ ddrss_phy_writel(DDRSS_DDRPHY_DX8SL0DQSCTL, cfg->ddrphy_dx8sl0dqsctl);
+ ddrss_phy_writel(DDRSS_DDRPHY_DX8SL1DQSCTL, cfg->ddrphy_dx8sl1dqsctl);
+ ddrss_phy_writel(DDRSS_DDRPHY_DX8SL2DQSCTL, cfg->ddrphy_dx8sl2dqsctl);
+
debug("%s: DDR phy register configuration completed\n", __func__);
}
@@ -479,18 +485,43 @@ int VREF_training(struct am654_ddrss_desc *ddrss)
int enable_dqs_pd(struct am654_ddrss_desc *ddrss)
{
- ddrss_phy_writel(DDRSS_DDRPHY_DX8SL0DQSCTL, 0x012640F7);
- ddrss_phy_writel(DDRSS_DDRPHY_DX8SL1DQSCTL, 0x012640F7);
- ddrss_phy_writel(DDRSS_DDRPHY_DX8SL2DQSCTL, 0x012640F7);
+ u32 val;
+
+ val = ddrss_phy_readl(DDRSS_DDRPHY_DX8SL0DQSCTL);
+ val &= ~0xFF;
+ val |= 0xF7;
+ ddrss_phy_writel(DDRSS_DDRPHY_DX8SL0DQSCTL, val);
+
+ val = ddrss_phy_readl(DDRSS_DDRPHY_DX8SL1DQSCTL);
+ val &= ~0xFF;
+ val |= 0xF7;
+ ddrss_phy_writel(DDRSS_DDRPHY_DX8SL1DQSCTL, val);
+
+ val = ddrss_phy_readl(DDRSS_DDRPHY_DX8SL2DQSCTL);
+ val &= ~0xFF;
+ val |= 0xF7;
+ ddrss_phy_writel(DDRSS_DDRPHY_DX8SL2DQSCTL, val);
+
sdelay(16);
return 0;
}
int disable_dqs_pd(struct am654_ddrss_desc *ddrss)
{
- ddrss_phy_writel(DDRSS_DDRPHY_DX8SL0DQSCTL, 0x01264000);
- ddrss_phy_writel(DDRSS_DDRPHY_DX8SL1DQSCTL, 0x01264000);
- ddrss_phy_writel(DDRSS_DDRPHY_DX8SL2DQSCTL, 0x01264000);
+ u32 val;
+
+ val = ddrss_phy_readl(DDRSS_DDRPHY_DX8SL0DQSCTL);
+ val &= ~0xFF;
+ ddrss_phy_writel(DDRSS_DDRPHY_DX8SL0DQSCTL, val);
+
+ val = ddrss_phy_readl(DDRSS_DDRPHY_DX8SL1DQSCTL);
+ val &= ~0xFF;
+ ddrss_phy_writel(DDRSS_DDRPHY_DX8SL1DQSCTL, val);
+
+ val = ddrss_phy_readl(DDRSS_DDRPHY_DX8SL2DQSCTL);
+ val &= ~0xFF;
+ ddrss_phy_writel(DDRSS_DDRPHY_DX8SL2DQSCTL, val);
+
sdelay(16);
return 0;
}
@@ -595,12 +626,14 @@ static int am654_ddrss_init(struct am654_ddrss_desc *ddrss)
{
int ret;
u32 val;
+ struct ddrss_ss_reg_params *reg = &ddrss->params.ss_reg;
debug("Starting DDR initialization...\n");
debug("%s(ddrss=%p)\n", __func__, ddrss);
- ddrss_writel(ddrss->ddrss_ss_cfg, DDRSS_V2H_CTL_REG, 0x000073FF);
+ ddrss_writel(ddrss->ddrss_ss_cfg, DDRSS_V2H_CTL_REG,
+ reg->ddrss_v2h_ctl_reg);
am654_ddrss_ctrl_configuration(ddrss);
@@ -901,6 +934,14 @@ static int am654_ddrss_ofdata_to_priv(struct udevice *dev)
}
ddrss->ddrss_phy_cfg = (void *)reg;
+ ret = dev_read_u32_array(dev, "ti,ss-reg",
+ (u32 *)&ddrss->params.ss_reg,
+ sizeof(ddrss->params.ss_reg) / sizeof(u32));
+ if (ret) {
+ dev_err(dev, "Cannot read ti,ss-reg params\n");
+ return ret;
+ }
+
ret = dev_read_u32_array(dev, "ti,ctl-reg",
(u32 *)&ddrss->params.ctl_reg,
sizeof(ddrss->params.ctl_reg) / sizeof(u32));
diff --git a/drivers/ram/k3-am654-ddrss.h b/drivers/ram/k3-am654-ddrss.h
index 78d73cd..94a7c91 100644
--- a/drivers/ram/k3-am654-ddrss.h
+++ b/drivers/ram/k3-am654-ddrss.h
@@ -996,6 +996,10 @@
PGSR0_DIDONE_MASK)
#define PGSR0_DATA_TR_INIT_MASK (PGSR0_DRAM_INIT_MASK)
+struct ddrss_ss_reg_params {
+ u32 ddrss_v2h_ctl_reg;
+};
+
struct ddrss_ddrctl_reg_params {
u32 ddrctl_dfimisc;
u32 ddrctl_dfitmg0;
@@ -1111,12 +1115,15 @@ struct ddrss_ddrphy_cfg_params {
u32 ddrphy_dx8sl0dxctl2;
u32 ddrphy_dx8sl0iocr;
u32 ddrphy_dx8sl0pllcr0;
+ u32 ddrphy_dx8sl0dqsctl;
u32 ddrphy_dx8sl1dxctl2;
u32 ddrphy_dx8sl1iocr;
u32 ddrphy_dx8sl1pllcr0;
+ u32 ddrphy_dx8sl1dqsctl;
u32 ddrphy_dx8sl2dxctl2;
u32 ddrphy_dx8sl2iocr;
u32 ddrphy_dx8sl2pllcr0;
+ u32 ddrphy_dx8sl2dqsctl;
u32 ddrphy_dxccr;
u32 ddrphy_odtcr;
u32 ddrphy_pgcr0;
@@ -1147,6 +1154,8 @@ struct ddrss_ddrphy_ctrl_params {
};
struct ddrss_ddrphy_ioctl_params {
+ u32 ddrphy_aciocr0;
+ u32 ddrphy_aciocr3;
u32 ddrphy_aciocr5;
u32 ddrphy_iovcr0;
};
@@ -1173,6 +1182,7 @@ struct ddrss_ddrphy_zq_params {
};
struct ddrss_params {
+ struct ddrss_ss_reg_params ss_reg;
struct ddrss_ddrctl_reg_params ctl_reg;
struct ddrss_ddrctl_crc_params ctl_crc;
struct ddrss_ddrctl_ecc_params ctl_ecc;
generated by cgit v1.1 at 2024-07-14 12:52:21 +0000