diff options
| -rw-r--r-- | arch/arm/Kconfig | 2 | ||||
| -rw-r--r-- | arch/arm/mach-sunxi/Kconfig | 3 | ||||
| -rw-r--r-- | board/sunxi/board.c | 51 | ||||
| -rw-r--r-- | configs/libretech_all_h3_it_h5_defconfig | 2 | ||||
| -rw-r--r-- | configs/libretech_all_h5_cc_h5_defconfig | 2 | ||||
| -rw-r--r-- | configs/oceanic_5205_5inmfd_defconfig | 1 | ||||
| -rw-r--r-- | configs/orangepi_pc2_defconfig | 2 | ||||
| -rw-r--r-- | configs/orangepi_r1_defconfig | 2 | ||||
| -rw-r--r-- | configs/orangepi_win_defconfig | 2 | ||||
| -rw-r--r-- | configs/orangepi_zero2_defconfig | 2 | ||||
| -rw-r--r-- | configs/orangepi_zero_defconfig | 2 | ||||
| -rw-r--r-- | configs/pine64-lts_defconfig | 2 | ||||
| -rw-r--r-- | configs/pine_h64_defconfig | 2 | ||||
| -rw-r--r-- | configs/pinecube_defconfig | 2 | ||||
| -rw-r--r-- | configs/sopine_baseboard_defconfig | 1 | ||||
| -rw-r--r-- | drivers/mtd/spi/spi-nor-ids.c | 2 | ||||
| -rw-r--r-- | drivers/spi/Kconfig | 6 | ||||
| -rw-r--r-- | drivers/spi/Makefile | 1 | ||||
| -rw-r--r-- | drivers/spi/cadence_qspi.c | 14 | ||||
| -rw-r--r-- | drivers/spi/cadence_qspi.h | 2 | ||||
| -rw-r--r-- | drivers/spi/designware_spi.c | 2 | ||||
| -rw-r--r-- | drivers/spi/iproc_qspi.c | 576 | ||||
| -rw-r--r-- | env/Kconfig | 7 |
23 files changed, 662 insertions, 26 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 391a77c..4567c18 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1062,6 +1062,8 @@ config ARCH_SUNXI select DM_ETH select DM_GPIO select DM_I2C if I2C + select DM_SPI if SPI + select DM_SPI_FLASH if SPI select DM_KEYBOARD select DM_MMC if MMC select DM_SCSI if SCSI diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index d1c60d2..73da6b8 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -332,9 +332,6 @@ config MACH_SUN9I config MACH_SUN50I bool "sun50i (Allwinner A64)" select ARM64 - select SPI - select DM_SPI if SPI - select DM_SPI_FLASH select PHY_SUN4I_USB select SUN6I_PRCM select SUNXI_DE2 diff --git a/board/sunxi/board.c b/board/sunxi/board.c index 82c52b2..a096159 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -171,21 +171,56 @@ void i2c_init_board(void) #endif } -#if defined(CONFIG_ENV_IS_IN_MMC) && defined(CONFIG_ENV_IS_IN_FAT) +/* + * Try to use the environment from the boot source first. + * For MMC, this means a FAT partition on the boot device (SD or eMMC). + * If the raw MMC environment is also enabled, this is tried next. + * SPI flash falls back to FAT (on SD card). + */ enum env_location env_get_location(enum env_operation op, int prio) { - switch (prio) { - case 0: - return ENVL_FAT; + enum env_location boot_loc = ENVL_FAT; - case 1: - return ENVL_MMC; + gd->env_load_prio = prio; + switch (sunxi_get_boot_device()) { + case BOOT_DEVICE_MMC1: + case BOOT_DEVICE_MMC2: + boot_loc = ENVL_FAT; + break; + case BOOT_DEVICE_NAND: + if (IS_ENABLED(CONFIG_ENV_IS_IN_NAND)) + boot_loc = ENVL_NAND; + break; + case BOOT_DEVICE_SPI: + if (IS_ENABLED(CONFIG_ENV_IS_IN_SPI_FLASH)) + boot_loc = ENVL_SPI_FLASH; + break; + case BOOT_DEVICE_BOARD: + break; default: - return ENVL_UNKNOWN; + break; + } + + /* Always try to access the environment on the boot device first. */ + if (prio == 0) + return boot_loc; + + if (prio == 1) { + switch (boot_loc) { + case ENVL_SPI_FLASH: + return ENVL_FAT; + case ENVL_FAT: + if (IS_ENABLED(CONFIG_ENV_IS_IN_MMC)) + return ENVL_MMC; + break; + default: + break; + } } + + return ENVL_UNKNOWN; } -#endif #ifdef CONFIG_DM_MMC static void mmc_pinmux_setup(int sdc); diff --git a/configs/libretech_all_h3_it_h5_defconfig b/configs/libretech_all_h3_it_h5_defconfig index 7f0e0be..cb7ffb4 100644 --- a/configs/libretech_all_h3_it_h5_defconfig +++ b/configs/libretech_all_h3_it_h5_defconfig @@ -7,9 +7,7 @@ CONFIG_DRAM_CLK=672 CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_SPL_SPI_SUNXI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_XMC=y CONFIG_SPI=y -CONFIG_DM_SPI=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/libretech_all_h5_cc_h5_defconfig b/configs/libretech_all_h5_cc_h5_defconfig index 25bfe52..c3aa4b1 100644 --- a/configs/libretech_all_h5_cc_h5_defconfig +++ b/configs/libretech_all_h5_cc_h5_defconfig @@ -7,10 +7,8 @@ CONFIG_DRAM_CLK=672 CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_SPL_SPI_SUNXI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_XMC=y CONFIG_SUN8I_EMAC=y CONFIG_SPI=y -CONFIG_DM_SPI=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/oceanic_5205_5inmfd_defconfig b/configs/oceanic_5205_5inmfd_defconfig index 9ba115c..7ce63ba 100644 --- a/configs/oceanic_5205_5inmfd_defconfig +++ b/configs/oceanic_5205_5inmfd_defconfig @@ -11,5 +11,6 @@ CONFIG_MMC0_CD_PIN="" CONFIG_SPL_SPI_SUNXI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SUN8I_EMAC=y +CONFIG_SPI=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/orangepi_pc2_defconfig b/configs/orangepi_pc2_defconfig index 2eaddcf..777af8c 100644 --- a/configs/orangepi_pc2_defconfig +++ b/configs/orangepi_pc2_defconfig @@ -11,9 +11,11 @@ CONFIG_SPL_SPI_SUNXI=y CONFIG_SPL_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MVTWSI=y +CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SUN8I_EMAC=y CONFIG_SY8106A_POWER=y CONFIG_SY8106A_VOUT1_VOLT=1100 +CONFIG_SPI=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_MUSB_GADGET=y diff --git a/configs/orangepi_r1_defconfig b/configs/orangepi_r1_defconfig index 745451c..4496aa4 100644 --- a/configs/orangepi_r1_defconfig +++ b/configs/orangepi_r1_defconfig @@ -8,6 +8,8 @@ CONFIG_DRAM_CLK=624 CONFIG_SPL_SPI_SUNXI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_CONSOLE_MUX=y +CONFIG_SPI_FLASH_WINBOND=y CONFIG_SUN8I_EMAC=y +CONFIG_SPI=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/orangepi_win_defconfig b/configs/orangepi_win_defconfig index 8c2179b..3b78ad7 100644 --- a/configs/orangepi_win_defconfig +++ b/configs/orangepi_win_defconfig @@ -7,7 +7,9 @@ CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y CONFIG_MACPWR="PD14" CONFIG_SPL_SPI_SUNXI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPI_FLASH_WINBOND=y CONFIG_PHY_REALTEK=y CONFIG_SUN8I_EMAC=y +CONFIG_SPI=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/orangepi_zero2_defconfig b/configs/orangepi_zero2_defconfig index 22563c8..54faf6a 100644 --- a/configs/orangepi_zero2_defconfig +++ b/configs/orangepi_zero2_defconfig @@ -15,5 +15,7 @@ CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 +CONFIG_SPI_FLASH_MACRONIX=y CONFIG_PHY_REALTEK=y CONFIG_SUN8I_EMAC=y +CONFIG_SPI=y diff --git a/configs/orangepi_zero_defconfig b/configs/orangepi_zero_defconfig index 332cd47..2dc69d2 100644 --- a/configs/orangepi_zero_defconfig +++ b/configs/orangepi_zero_defconfig @@ -8,6 +8,8 @@ CONFIG_DRAM_CLK=624 CONFIG_SPL_SPI_SUNXI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_CONSOLE_MUX=y +CONFIG_SPI_FLASH_WINBOND=y CONFIG_SUN8I_EMAC=y +CONFIG_SPI=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/pine64-lts_defconfig b/configs/pine64-lts_defconfig index 6209e68..45a9e77 100644 --- a/configs/pine64-lts_defconfig +++ b/configs/pine64-lts_defconfig @@ -10,6 +10,8 @@ CONFIG_MMC0_CD_PIN="" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_SPL_SPI_SUNXI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPI_FLASH_WINBOND=y CONFIG_SUN8I_EMAC=y +CONFIG_SPI=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/pine_h64_defconfig b/configs/pine_h64_defconfig index 1928509..1e730dd 100644 --- a/configs/pine_h64_defconfig +++ b/configs/pine_h64_defconfig @@ -11,8 +11,10 @@ CONFIG_USB3_VBUS_PIN="PL5" CONFIG_SPL_SPI_SUNXI=y # CONFIG_PSCI_RESET is not set # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPI_FLASH_WINBOND=y CONFIG_SUN8I_EMAC=y CONFIG_PHY_SUN50I_USB3=y +CONFIG_SPI=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/pinecube_defconfig b/configs/pinecube_defconfig index 0c71d59..e779663 100644 --- a/configs/pinecube_defconfig +++ b/configs/pinecube_defconfig @@ -12,8 +12,10 @@ CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 +CONFIG_SPI_FLASH_WINBOND=y # CONFIG_NETDEVICES is not set CONFIG_AXP209_POWER=y CONFIG_AXP_DCDC2_VOLT=1250 CONFIG_AXP_DCDC3_VOLT=3300 CONFIG_CONS_INDEX=3 +CONFIG_SPI=y diff --git a/configs/sopine_baseboard_defconfig b/configs/sopine_baseboard_defconfig index 0093076..982f7b0 100644 --- a/configs/sopine_baseboard_defconfig +++ b/configs/sopine_baseboard_defconfig @@ -13,5 +13,6 @@ CONFIG_SPL_SPI_SUNXI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPI_FLASH_WINBOND=y CONFIG_SUN8I_EMAC=y +CONFIG_SPI=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index b551ebd..763bab0 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -119,7 +119,7 @@ const struct flash_info spi_nor_ids[] = { }, { INFO("gd25lq128", 0xc86018, 0, 64 * 1024, 256, - SECT_4K | SPI_NOR_DUAL_READ | + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) }, { diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 0a6a85f..423a757 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -185,6 +185,12 @@ config ICH_SPI access the SPI NOR flash on platforms embedding this Intel ICH IP core. +config IPROC_QSPI + bool "Broadcom iProc QSPI Flash Controller driver" + help + Enable Broadcom iProc QSPI Flash Controller driver. + This driver can be used to access the SPI NOR flash. + config KIRKWOOD_SPI bool "Marvell Kirkwood SPI Driver" help diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index bea746f..7f43f84 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -34,6 +34,7 @@ obj-$(CONFIG_FSL_DSPI) += fsl_dspi.o obj-$(CONFIG_FSL_ESPI) += fsl_espi.o obj-$(CONFIG_SYNQUACER_SPI) += spi-synquacer.o obj-$(CONFIG_ICH_SPI) += ich.o +obj-$(CONFIG_IPROC_QSPI) += iproc_qspi.o obj-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o obj-$(CONFIG_MESON_SPIFC) += meson_spifc.o obj-$(CONFIG_MPC8XX_SPI) += mpc8xx_spi.o diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c index d1b3808..db68061 100644 --- a/drivers/spi/cadence_qspi.c +++ b/drivers/spi/cadence_qspi.c @@ -201,11 +201,9 @@ static int cadence_spi_probe(struct udevice *bus) } } - ret = reset_get_bulk(bus, &priv->resets); - if (ret) - dev_warn(bus, "Can't get reset: %d\n", ret); - else - reset_deassert_bulk(&priv->resets); + priv->resets = devm_reset_bulk_get_optional(bus); + if (priv->resets) + reset_deassert_bulk(priv->resets); if (!priv->qspi_is_init) { cadence_qspi_apb_controller_init(plat); @@ -220,8 +218,12 @@ static int cadence_spi_probe(struct udevice *bus) static int cadence_spi_remove(struct udevice *dev) { struct cadence_spi_priv *priv = dev_get_priv(dev); + int ret = 0; + + if (priv->resets) + ret = reset_release_bulk(priv->resets); - return reset_release_bulk(&priv->resets); + return ret; } static int cadence_spi_set_mode(struct udevice *bus, uint mode) diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h index 49b4011..19345ca 100644 --- a/drivers/spi/cadence_qspi.h +++ b/drivers/spi/cadence_qspi.h @@ -56,7 +56,7 @@ struct cadence_spi_priv { unsigned int qspi_calibrated_cs; unsigned int previous_hz; - struct reset_ctl_bulk resets; + struct reset_ctl_bulk *resets; }; /* Functions call declaration */ diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c index 7421211..fc22f54 100644 --- a/drivers/spi/designware_spi.c +++ b/drivers/spi/designware_spi.c @@ -572,7 +572,7 @@ static int dw_spi_exec_op(struct spi_slave *slave, const struct spi_mem_op *op) int pos, i, ret = 0; struct udevice *bus = slave->dev->parent; struct dw_spi_priv *priv = dev_get_priv(bus); - u8 op_len = sizeof(op->cmd.opcode) + op->addr.nbytes + op->dummy.nbytes; + u8 op_len = op->cmd.nbytes + op->addr.nbytes + op->dummy.nbytes; u8 op_buf[op_len]; u32 cr0; diff --git a/drivers/spi/iproc_qspi.c b/drivers/spi/iproc_qspi.c new file mode 100644 index 0000000..b5c2743 --- /dev/null +++ b/drivers/spi/iproc_qspi.c @@ -0,0 +1,576 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020-2021 Broadcom + */ + +#include <common.h> +#include <dm.h> +#include <spi.h> +#include <spi-mem.h> +#include <asm/io.h> +#include <linux/delay.h> +#include <linux/err.h> +#include <linux/iopoll.h> +#include <linux/log2.h> + +/* Delay required to change the mode of operation */ +#define BUSY_DELAY_US 1 +#define BUSY_TIMEOUT_US 200000 +#define DWORD_ALIGNED(a) (!(((ulong)(a)) & 3)) + +/* Chip attributes */ +#define QSPI_AXI_CLK 175000000 +#define SPBR_MIN 8U +#define SPBR_MAX 255U +#define NUM_CDRAM 16U + +#define CDRAM_PCS0 2 +#define CDRAM_CONT BIT(7) +#define CDRAM_BITS_EN BIT(6) +#define CDRAM_QUAD_MODE BIT(8) +#define CDRAM_RBIT_INPUT BIT(10) +#define MSPI_SPE BIT(6) +#define MSPI_CONT_AFTER_CMD BIT(7) +#define MSPI_MSTR BIT(7) + +/* Register fields */ +#define MSPI_SPCR0_MSB_BITS_8 0x00000020 +#define BSPI_RAF_CONTROL_START_MASK 0x00000001 +#define BSPI_RAF_STATUS_SESSION_BUSY_MASK 0x00000001 +#define BSPI_RAF_STATUS_FIFO_EMPTY_MASK 0x00000002 +#define BSPI_STRAP_OVERRIDE_DATA_QUAD_SHIFT 3 +#define BSPI_STRAP_OVERRIDE_4BYTE_SHIFT 2 +#define BSPI_STRAP_OVERRIDE_DATA_DUAL_SHIFT 1 +#define BSPI_STRAP_OVERRIDE_SHIFT 0 +#define BSPI_BPC_DATA_SHIFT 0 +#define BSPI_BPC_MODE_SHIFT 8 +#define BSPI_BPC_ADDR_SHIFT 16 +#define BSPI_BPC_CMD_SHIFT 24 +#define BSPI_BPP_ADDR_SHIFT 16 + +/* MSPI registers */ +#define MSPI_SPCR0_LSB_REG 0x000 +#define MSPI_SPCR0_MSB_REG 0x004 +#define MSPI_SPCR1_LSB_REG 0x008 +#define MSPI_SPCR1_MSB_REG 0x00c +#define MSPI_NEWQP_REG 0x010 +#define MSPI_ENDQP_REG 0x014 +#define MSPI_SPCR2_REG 0x018 +#define MSPI_STATUS_REG 0x020 +#define MSPI_CPTQP_REG 0x024 +#define MSPI_TX_REG 0x040 +#define MSPI_RX_REG 0x0c0 +#define MSPI_CDRAM_REG 0x140 +#define MSPI_WRITE_LOCK_REG 0x180 +#define MSPI_DISABLE_FLUSH_GEN_REG 0x184 + +/* BSPI registers */ +#define BSPI_REVISION_ID_REG 0x000 +#define BSPI_SCRATCH_REG 0x004 +#define BSPI_MAST_N_BOOT_CTRL_REG 0x008 +#define BSPI_BUSY_STATUS_REG 0x00c +#define BSPI_INTR_STATUS_REG 0x010 +#define BSPI_B0_STATUS_REG 0x014 +#define BSPI_B0_CTRL_REG 0x018 +#define BSPI_B1_STATUS_REG 0x01c +#define BSPI_B1_CTRL_REG 0x020 +#define BSPI_STRAP_OVERRIDE_CTRL_REG 0x024 +#define BSPI_FLEX_MODE_ENABLE_REG 0x028 +#define BSPI_BITS_PER_CYCLE_REG 0x02C +#define BSPI_BITS_PER_PHASE_REG 0x030 +#define BSPI_CMD_AND_MODE_BYTE_REG 0x034 +#define BSPI_FLASH_UPPER_ADDR_BYTE_REG 0x038 +#define BSPI_XOR_VALUE_REG 0x03C +#define BSPI_XOR_ENABLE_REG 0x040 +#define BSPI_PIO_MODE_ENABLE_REG 0x044 +#define BSPI_PIO_IODIR_REG 0x048 +#define BSPI_PIO_DATA_REG 0x04C + +/* RAF registers */ +#define BSPI_RAF_START_ADDRESS_REG 0x00 +#define BSPI_RAF_NUM_WORDS_REG 0x04 +#define BSPI_RAF_CTRL_REG 0x08 +#define BSPI_RAF_FULLNESS_REG 0x0C +#define BSPI_RAF_WATERMARK_REG 0x10 +#define BSPI_RAF_STATUS_REG 0x14 +#define BSPI_RAF_READ_DATA_REG 0x18 +#define BSPI_RAF_WORD_CNT_REG 0x1C +#define BSPI_RAF_CURR_ADDR_REG 0x20 + +#define XFER_DUAL BIT(30) +#define XFER_QUAD BIT(31) + +#define FLUSH_BIT BIT(0) +#define MAST_N_BOOT_BIT BIT(0) +#define WRITE_LOCK_BIT BIT(0) + +#define CEIL(m, n) (((m) + (n) - 1) / (n)) +#define UPPER_BYTE_MASK 0xFF000000 +#define SIZE_16MB 0x001000000 + +/* + * struct bcmspi_priv - qspi private structure + * + * @bspi_addr: bspi read address + * @bspi_4byte_addr: bspi 4 byte address mode + * @mspi: mspi registers block address + * @bspi: bspi registers block address + * @bspi_raf: bspi raf registers block address + */ +struct bcmspi_priv { + u32 bspi_addr; + bool bspi_4byte_addr; + fdt_addr_t mspi; + fdt_addr_t bspi; + fdt_addr_t bspi_raf; +}; + +/* BSPI mode */ + +static void bspi_flush_prefetch_buffers(struct bcmspi_priv *priv) +{ + writel(0, priv->bspi + BSPI_B0_CTRL_REG); + writel(0, priv->bspi + BSPI_B1_CTRL_REG); + writel(FLUSH_BIT, priv->bspi + BSPI_B0_CTRL_REG); + writel(FLUSH_BIT, priv->bspi + BSPI_B1_CTRL_REG); +} + +static int bspi_enable(struct bcmspi_priv *priv) +{ + /* Disable write lock */ + writel(0, priv->mspi + MSPI_WRITE_LOCK_REG); + /* Flush prefetch buffers */ + bspi_flush_prefetch_buffers(priv); + /* Switch to BSPI */ + writel(0, priv->bspi + BSPI_MAST_N_BOOT_CTRL_REG); + + return 0; +} + +static int bspi_disable(struct bcmspi_priv *priv) +{ + int ret; + uint val; + + if ((readl(priv->bspi + BSPI_MAST_N_BOOT_CTRL_REG) & 1) == 0) { + ret = readl_poll_timeout(priv->bspi + BSPI_BUSY_STATUS_REG, val, !(val & 1), + BUSY_TIMEOUT_US); + if (ret) { + printf("%s: Failed to disable bspi, device busy\n", __func__); + return ret; + } + + /* Switch to MSPI */ + writel(MAST_N_BOOT_BIT, priv->bspi + BSPI_MAST_N_BOOT_CTRL_REG); + udelay(BUSY_DELAY_US); + + val = readl(priv->bspi + BSPI_MAST_N_BOOT_CTRL_REG); + if (!(val & 1)) { + printf("%s: Failed to enable mspi\n", __func__); + return -EBUSY; + } + } + + /* Enable write lock */ + writel(WRITE_LOCK_BIT, priv->mspi + MSPI_WRITE_LOCK_REG); + + return 0; +} + +static int bspi_read_via_raf(struct bcmspi_priv *priv, u8 *rx, uint bytes) +{ + u32 status; + uint words; + int aligned; + int ret; + + /* + * Flush data from the previous session (unlikely) + * Read outstanding bits in the poll condition to empty FIFO + */ + ret = readl_poll_timeout(priv->bspi_raf + BSPI_RAF_STATUS_REG, + status, + (!readl(priv->bspi_raf + BSPI_RAF_READ_DATA_REG) && + status & BSPI_RAF_STATUS_FIFO_EMPTY_MASK) && + !(status & BSPI_RAF_STATUS_SESSION_BUSY_MASK), + BUSY_TIMEOUT_US); + if (ret) { + printf("%s: Failed to flush fifo\n", __func__); + return ret; + } + + /* Transfer is in words */ + words = CEIL(bytes, 4); + + /* Setup hardware */ + if (priv->bspi_4byte_addr) { + u32 val = priv->bspi_addr & UPPER_BYTE_MASK; + + if (val != readl(priv->bspi + BSPI_FLASH_UPPER_ADDR_BYTE_REG)) { + writel(val, priv->bspi + BSPI_FLASH_UPPER_ADDR_BYTE_REG); + bspi_flush_prefetch_buffers(priv); + } + } + + writel(priv->bspi_addr & ~UPPER_BYTE_MASK, priv->bspi_raf + BSPI_RAF_START_ADDRESS_REG); + writel(words, priv->bspi_raf + BSPI_RAF_NUM_WORDS_REG); + writel(0, priv->bspi_raf + BSPI_RAF_WATERMARK_REG); + + /* Start reading */ + writel(BSPI_RAF_CONTROL_START_MASK, priv->bspi_raf + BSPI_RAF_CTRL_REG); + aligned = DWORD_ALIGNED(rx); + while (bytes) { + status = readl(priv->bspi_raf + BSPI_RAF_STATUS_REG); + if (!(status & BSPI_RAF_STATUS_FIFO_EMPTY_MASK)) { + /* RAF is LE only, convert data to host endianness */ + u32 data = le32_to_cpu(readl(priv->bspi_raf + BSPI_RAF_READ_DATA_REG)); + + /* Check if we can use the whole word */ + if (aligned && bytes >= 4) { + *(u32 *)rx = data; + rx += 4; + bytes -= 4; + } else { + uint chunk = min(bytes, 4U); + + /* Read out bytes one by one */ + while (chunk) { + *rx++ = (u8)data; + data >>= 8; + chunk--; + bytes--; + } + } + + continue; + } + if (!(status & BSPI_RAF_STATUS_SESSION_BUSY_MASK)) { + /* FIFO is empty and the session is done */ + break; + } + } + + return 0; +} + +static int bspi_read(struct bcmspi_priv *priv, u8 *rx, uint bytes) +{ + int ret; + + /* Transfer data */ + while (bytes > 0) { + /* Special handing since RAF cannot go across 16MB boundary */ + uint trans = bytes; + /* Divide into multiple transfers if it goes across the 16MB boundary */ + if (priv->bspi_4byte_addr && (priv->bspi_addr >> 24) != + ((priv->bspi_addr + bytes) >> 24)) + trans = SIZE_16MB - (priv->bspi_addr & ~UPPER_BYTE_MASK); + + ret = bspi_read_via_raf(priv, rx, trans); + if (ret) + return ret; + + priv->bspi_addr += trans; + rx += trans; + bytes -= trans; + } + + bspi_flush_prefetch_buffers(priv); + return 0; +} + +static void bspi_set_flex_mode(struct bcmspi_priv *priv, const struct spi_mem_op *op) +{ + int bpp = (op->dummy.nbytes * 8) / op->dummy.buswidth; + int cmd = op->cmd.opcode; + int bpc = ilog2(op->data.buswidth) << BSPI_BPC_DATA_SHIFT | + ilog2(op->addr.buswidth) << BSPI_BPC_ADDR_SHIFT | + ilog2(op->cmd.buswidth) << BSPI_BPC_CMD_SHIFT; + int so = BIT(BSPI_STRAP_OVERRIDE_SHIFT) | + (op->data.buswidth > 1) << BSPI_STRAP_OVERRIDE_DATA_DUAL_SHIFT | + (op->addr.nbytes > 3) << BSPI_STRAP_OVERRIDE_4BYTE_SHIFT | + (op->data.buswidth > 3) << BSPI_STRAP_OVERRIDE_DATA_QUAD_SHIFT; + + /* Disable flex mode first */ + writel(0, priv->bspi + BSPI_FLEX_MODE_ENABLE_REG); + + /* Configure single, dual or quad mode */ + writel(bpc, priv->bspi + BSPI_BITS_PER_CYCLE_REG); + + /* Opcode */ + writel(cmd, priv->bspi + BSPI_CMD_AND_MODE_BYTE_REG); + + /* Count of dummy cycles */ + writel(bpp, priv->bspi + BSPI_BITS_PER_PHASE_REG); + + /* Enable 4-byte address */ + if (priv->bspi_4byte_addr) { + setbits_le32(priv->bspi + BSPI_BITS_PER_PHASE_REG, BIT(BSPI_BPP_ADDR_SHIFT)); + } else { + clrbits_le32(priv->bspi + BSPI_BITS_PER_PHASE_REG, BIT(BSPI_BPP_ADDR_SHIFT)); + writel(0, priv->bspi + BSPI_FLASH_UPPER_ADDR_BYTE_REG); + } + + /* Enable flex mode to take effect */ + writel(1, priv->bspi + BSPI_FLEX_MODE_ENABLE_REG); + + /* Flush prefetch buffers since 32MB window BSPI could be used */ + bspi_flush_prefetch_buffers(priv); + + /* Override the strap settings */ + writel(so, priv->bspi + BSPI_STRAP_OVERRIDE_CTRL_REG); +} + +static int bspi_exec_op(struct spi_slave *slave, const struct spi_mem_op *op) +{ + struct udevice *bus = dev_get_parent(slave->dev); + struct bcmspi_priv *priv = dev_get_priv(bus); + int ret = -ENOTSUPP; + + /* BSPI read */ + if (op->data.dir == SPI_MEM_DATA_IN && + op->data.nbytes && op->addr.nbytes) { + priv->bspi_4byte_addr = (op->addr.nbytes > 3); + priv->bspi_addr = op->addr.val; + bspi_set_flex_mode(priv, op); + ret = bspi_read(priv, op->data.buf.in, op->data.nbytes); + } + + return ret; +} + +static const struct spi_controller_mem_ops bspi_mem_ops = { + .exec_op = bspi_exec_op, +}; + +/* MSPI mode */ + +static int mspi_exec(struct bcmspi_priv *priv, uint bytes, const u8 *tx, u8 *rx, ulong flags) +{ + u32 cdr = CDRAM_PCS0 | CDRAM_CONT; + bool use_16bits = !(bytes & 1); + + if (flags & XFER_QUAD) { + cdr |= CDRAM_QUAD_MODE; + + if (!tx) + cdr |= CDRAM_RBIT_INPUT; + } + + while (bytes) { + uint chunk; + uint queues; + uint i; + uint val; + int ret; + + if (use_16bits) { + chunk = min(bytes, NUM_CDRAM * 2); + queues = (chunk + 1) / 2; + bytes -= chunk; + + /* Fill CDRAMs */ + for (i = 0; i < queues; i++) + writel(cdr | CDRAM_BITS_EN, priv->mspi + MSPI_CDRAM_REG + 4 * i); + + /* Fill TXRAMs */ + for (i = 0; i < chunk; i++) + writel(tx ? tx[i] : 0xff, priv->mspi + MSPI_TX_REG + 4 * i); + } else { + /* Determine how many bytes to process this time */ + chunk = min(bytes, NUM_CDRAM); + queues = chunk; + bytes -= chunk; + + /* Fill CDRAMs and TXRAMS */ + for (i = 0; i < chunk; i++) { + writel(cdr, priv->mspi + MSPI_CDRAM_REG + 4 * i); + writel(tx ? tx[i] : 0xff, priv->mspi + MSPI_TX_REG + 8 * i); + } + } + + /* Setup queue pointers */ + writel(0, priv->mspi + MSPI_NEWQP_REG); + writel(queues - 1, priv->mspi + MSPI_ENDQP_REG); + + /* Deassert CS if requested and it's the last transfer */ + if (bytes == 0 && (flags & SPI_XFER_END)) + clrbits_le32(priv->mspi + MSPI_CDRAM_REG + ((queues - 1) << 2), CDRAM_CONT); + + /* Kick off */ + writel(0, priv->mspi + MSPI_STATUS_REG); + if (bytes == 0 && (flags & SPI_XFER_END)) + writel(MSPI_SPE, priv->mspi + MSPI_SPCR2_REG); + else + writel(MSPI_SPE | MSPI_CONT_AFTER_CMD, + priv->mspi + MSPI_SPCR2_REG); + + ret = readl_poll_timeout(priv->mspi + MSPI_STATUS_REG, val, (val & 1), + BUSY_TIMEOUT_US); + if (ret) { + printf("%s: Failed to disable bspi, device busy\n", __func__); + return ret; + } + + /* Read data out */ + if (rx) { + if (use_16bits) { + for (i = 0; i < chunk; i++) + rx[i] = readl(priv->mspi + MSPI_RX_REG + 4 * i) & 0xff; + } else { + for (i = 0; i < chunk; i++) + rx[i] = readl(priv->mspi + MSPI_RX_REG + 8 * i + 4) & 0xff; + } + } + + /* Advance pointers */ + if (tx) + tx += chunk; + if (rx) + rx += chunk; + } + + return 0; +} + +static int mspi_xfer(struct udevice *dev, uint bitlen, const void *dout, void *din, ulong flags) +{ + struct udevice *bus = dev_get_parent(dev); + struct bcmspi_priv *priv = dev_get_priv(bus); + uint bytes; + int ret = 0; + + /* we can only transfer multiples of 8 bits */ + if (bitlen % 8) + return -EPROTONOSUPPORT; + + bytes = bitlen / 8; + + if (flags & SPI_XFER_BEGIN) { + /* Switch to MSPI */ + ret = bspi_disable(priv); + if (ret) + return ret; + } + + /* MSPI: Transfer */ + if (bytes) + ret = mspi_exec(priv, bytes, dout, din, flags); + + if (flags & SPI_XFER_END) { + /* Switch back to BSPI */ + ret = bspi_enable(priv); + if (ret) + return ret; + } + + return ret; +} + +/* iProc interface */ + +static int iproc_qspi_set_speed(struct udevice *bus, uint speed) +{ + struct bcmspi_priv *priv = dev_get_priv(bus); + uint spbr; + + /* MSPI: SCK configuration */ + spbr = (QSPI_AXI_CLK - 1) / (2 * speed) + 1; + writel(max(min(spbr, SPBR_MAX), SPBR_MIN), priv->mspi + MSPI_SPCR0_LSB_REG); + + return 0; +} + +static int iproc_qspi_set_mode(struct udevice *bus, uint mode) +{ + struct bcmspi_priv *priv = dev_get_priv(bus); + + /* MSPI: set master bit and mode */ + writel(MSPI_MSTR /* Master */ | (mode & 3), priv->mspi + MSPI_SPCR0_MSB_REG); + + return 0; +} + +static int iproc_qspi_claim_bus(struct udevice *dev) +{ + /* Nothing to do */ + return 0; +} + +static int iproc_qspi_release_bus(struct udevice *dev) +{ + struct udevice *bus = dev_get_parent(dev); + struct bcmspi_priv *priv = dev_get_priv(bus); + + /* Make sure no operation is in progress */ + writel(0, priv->mspi + MSPI_SPCR2_REG); + udelay(BUSY_DELAY_US); + + return 0; +} + +static int iproc_qspi_of_to_plat(struct udevice *bus) +{ + struct bcmspi_priv *priv = dev_get_priv(bus); + + priv->bspi = dev_read_addr_name(bus, "bspi"); + if (IS_ERR((void *)priv->bspi)) { + printf("%s: Failed to get bspi base address\n", __func__); + return PTR_ERR((void *)priv->bspi); + } + + priv->bspi_raf = dev_read_addr_name(bus, "bspi_raf"); + if (IS_ERR((void *)priv->bspi_raf)) { + printf("%s: Failed to get bspi_raf base address\n", __func__); + return PTR_ERR((void *)priv->bspi_raf); + } + + priv->mspi = dev_read_addr_name(bus, "mspi"); + if (IS_ERR((void *)priv->mspi)) { + printf("%s: Failed to get mspi base address\n", __func__); + return PTR_ERR((void *)priv->mspi); + } + + return 0; +} + +static int iproc_qspi_probe(struct udevice *bus) +{ + struct bcmspi_priv *priv = dev_get_priv(bus); + + /* configure mspi */ + writel(0, priv->mspi + MSPI_SPCR1_LSB_REG); + writel(0, priv->mspi + MSPI_SPCR1_MSB_REG); + writel(0, priv->mspi + MSPI_NEWQP_REG); + writel(0, priv->mspi + MSPI_ENDQP_REG); + writel(0, priv->mspi + MSPI_SPCR2_REG); + + /* configure bspi */ + bspi_enable(priv); + + return 0; +} + +static const struct dm_spi_ops iproc_qspi_ops = { + .claim_bus = iproc_qspi_claim_bus, + .release_bus = iproc_qspi_release_bus, + .xfer = mspi_xfer, + .set_speed = iproc_qspi_set_speed, + .set_mode = iproc_qspi_set_mode, + .mem_ops = &bspi_mem_ops, +}; + +static const struct udevice_id iproc_qspi_ids[] = { + { .compatible = "brcm,iproc-qspi" }, + { } +}; + +U_BOOT_DRIVER(iproc_qspi) = { + .name = "iproc_qspi", + .id = UCLASS_SPI, + .of_match = iproc_qspi_ids, + .ops = &iproc_qspi_ops, + .of_to_plat = iproc_qspi_of_to_plat, + .priv_auto = sizeof(struct bcmspi_priv), + .probe = iproc_qspi_probe, +}; diff --git a/env/Kconfig b/env/Kconfig index 6dc8d8d..b9d0472 100644 --- a/env/Kconfig +++ b/env/Kconfig @@ -320,6 +320,7 @@ config ENV_IS_IN_SPI_FLASH default y if NORTHBRIDGE_INTEL_IVYBRIDGE default y if INTEL_QUARK default y if INTEL_QUEENSBAY + default y if ARCH_SUNXI help Define this if you have a SPI Flash memory device which you want to use for the environment. @@ -536,7 +537,7 @@ config ENV_OFFSET ENV_IS_IN_SPI_FLASH default 0x3f8000 if ARCH_ROCKCHIP && ENV_IS_IN_MMC default 0x140000 if ARCH_ROCKCHIP && ENV_IS_IN_SPI_FLASH - default 0x88000 if ARCH_SUNXI + default 0xF0000 if ARCH_SUNXI default 0xE0000 if ARCH_ZYNQ default 0x1E00000 if ARCH_ZYNQMP default 0x7F40000 if ARCH_VERSAL @@ -559,7 +560,8 @@ config ENV_OFFSET_REDUND config ENV_SIZE hex "Environment Size" default 0x40000 if ENV_IS_IN_SPI_FLASH && ARCH_ZYNQMP - default 0x20000 if ARCH_SUNXI || ARCH_ZYNQ || ARCH_OMAP2PLUS || ARCH_AT91 + default 0x20000 if ARCH_ZYNQ || ARCH_OMAP2PLUS || ARCH_AT91 + default 0x10000 if ARCH_SUNXI default 0x8000 if ARCH_ROCKCHIP && ENV_IS_IN_MMC default 0x2000 if ARCH_ROCKCHIP && ENV_IS_IN_SPI_FLASH default 0x8000 if ARCH_ZYNQMP || ARCH_VERSAL @@ -575,6 +577,7 @@ config ENV_SECT_SIZE default 0x40000 if ARCH_ZYNQMP || ARCH_VERSAL default 0x20000 if ARCH_ZYNQ || ARCH_OMAP2PLUS || ARCH_AT91 default 0x20000 if MICROBLAZE && ENV_IS_IN_SPI_FLASH + default 0x10000 if ARCH_SUNXI && ENV_IS_IN_SPI_FLASH help Size of the sector containing the environment. |