diff options
427 files changed, 10198 insertions, 3311 deletions
diff --git a/.azure-pipelines.yml b/.azure-pipelines.yml index 473ddee..a78c8d6 100644 --- a/.azure-pipelines.yml +++ b/.azure-pipelines.yml @@ -182,7 +182,7 @@ jobs: OVERRIDE: "-O clang-10" sandbox_spl: TEST_PY_BD: "sandbox_spl" - TEST_PY_TEST_SPEC: "test_ofplatdata or test_handoff" + TEST_PY_TEST_SPEC: "test_ofplatdata or test_handoff or test_spl" sandbox_flattree: TEST_PY_BD: "sandbox_flattree" evb_ast2500: diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 9ac2b33..b1e0b3b 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -198,7 +198,7 @@ sandbox_spl test.py: tags: [ 'all' ] variables: TEST_PY_BD: "sandbox_spl" - TEST_PY_TEST_SPEC: "test_ofplatdata or test_handoff" + TEST_PY_TEST_SPEC: "test_ofplatdata or test_handoff or test_spl" <<: *buildman_and_testpy_dfn evb-ast2500 test.py: diff --git a/.travis.yml b/.travis.yml index fb8f731..cb48ff3 100644 --- a/.travis.yml +++ b/.travis.yml @@ -512,7 +512,7 @@ matrix: - name: "test/py sandbox_spl" env: - TEST_PY_BD="sandbox_spl" - TEST_PY_TEST_SPEC="test_ofplatdata or test_handoff" + TEST_PY_TEST_SPEC="test_ofplatdata or test_handoff or test_spl" TOOLCHAIN="i386" TEST_PY_TOOLS="yes" - name: "test/py sandbox_flattree" diff --git a/MAINTAINERS b/MAINTAINERS index d9f8032..874cf2c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -462,7 +462,7 @@ F: arch/arm/include/asm/arch-stv0991/ ARM SUNXI M: Jagan Teki <jagan@amarulasolutions.com> -M: Maxime Ripard <mripard@kernel.org> +M: Andre Przywara <andre.przywara@arm.com> S: Maintained T: git https://gitlab.denx.de/u-boot/custodians/u-boot-sunxi.git F: arch/arm/cpu/armv7/sunxi/ @@ -546,6 +546,7 @@ M: Michal Simek <monstr@monstr.eu> S: Maintained T: git https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze.git F: arch/arm/mach-zynq/ +F: doc/board/xilinx/ F: drivers/clk/clk_zynq.c F: drivers/fpga/zynqpl.c F: drivers/gpio/zynq_gpio.c @@ -757,6 +758,7 @@ T: git https://gitlab.denx.de/u-boot/u-boot.git F: common/log* F: cmd/log.c F: doc/develop/logging.rst +F: lib/getopt.c F: test/log/ F: test/py/tests/test_log.py @@ -807,7 +807,7 @@ libs-$(CONFIG_API) += api/ ifdef CONFIG_POST libs-y += post/ endif -libs-$(CONFIG_UNIT_TEST) += test/ test/dm/ +libs-$(CONFIG_UNIT_TEST) += test/ libs-$(CONFIG_UT_ENV) += test/env/ libs-$(CONFIG_UT_OPTEE) += test/optee/ libs-$(CONFIG_UT_OVERLAY) += test/overlay/ diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 80f0960..b2f7fcb 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1620,6 +1620,16 @@ config TARGET_LS1046AFRWY development platform that supports the QorIQ LS1046A Layerscape Architecture processor. +config TARGET_SL28 + bool "Support sl28" + select ARCH_LS1028A + select ARM64 + select ARMV8_MULTIENTRY + select SUPPORT_SPL + select BINMAN + help + Support for Kontron SMARC-sAL28 board. + config TARGET_COLIBRI_PXA270 bool "Support colibri_pxa270" select CPU_PXA @@ -1998,6 +2008,7 @@ source "board/hisilicon/hikey/Kconfig" source "board/hisilicon/hikey960/Kconfig" source "board/hisilicon/poplar/Kconfig" source "board/isee/igep003x/Kconfig" +source "board/kontron/sl28/Kconfig" source "board/myir/mys_6ulx/Kconfig" source "board/spear/spear300/Kconfig" source "board/spear/spear310/Kconfig" diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index e610528..596b88d 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -1147,15 +1147,15 @@ int arch_early_init_r(void) * EC*_PMUX(rgmii) bits in RCW. * e.g. dpmac 17 and 18 in LX2160A can be configured as SGMII from * serdes bits and as RGMII via EC1_PMUX/EC2_PMUX bits - * Now if a dpmac is enabled by serdes bits then it takes precedence - * over EC*_PMUX bits. i.e. in LX2160A if we select serdes protocol - * that configures dpmac17 as SGMII and set the EC1_PMUX as RGMII, - * then the dpmac is SGMII and not RGMII. + * Now if a dpmac is enabled as RGMII through ECx_PMUX then it takes + * precedence over SerDes protocol. i.e. in LX2160A if we select serdes + * protocol that configures dpmac17 as SGMII and set the EC1_PMUX as + * RGMII, then the dpmac is RGMII and not SGMII. * - * Therefore, move the fsl_rgmii_init after fsl_serdes_init. in - * fsl_rgmii_init function of SOC, we will check if the dpmac is enabled - * or not? if it is (fsl_serdes_init has already enabled the dpmac), - * then don't enable it. + * Therefore, even thought fsl_rgmii_init is after fsl_serdes_init + * function of SOC, the dpmac will be enabled as RGMII even if it was + * also enabled before as SGMII. If ECx_PMUX is not configured for + * RGMII, DPMAC will remain configured as SGMII from fsl_serdes_init(). */ fsl_rgmii_init(); #endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.pci_iommu_extra b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.pci_iommu_extra new file mode 100644 index 0000000..43db4d8 --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.pci_iommu_extra @@ -0,0 +1,67 @@ +# +# Copyright 2020 NXP +# +# SPDX-License-Identifier: GPL-2.0+ +# + +Specifying extra IOMMU mappings for PCI controllers + +This feature can be enabled through the PCI_IOMMU_EXTRA_MAPPINGS Kconfig option. + +The "pci_iommu_extra" env var or "pci-iommu-extra" device tree property (to be +used for example in more static scenarios such as hardwired PCI endpoints that +get initialized later in the system setup) allows two things: + - for a SRIOV capable PCI EP identified by its B.D.F specify the maximum number + of VFs that will ever be created for it + - for hot-plug case, specify the B.D.F with which the device will show up on + the PCI bus + +The env var consists of a list of <bdf>,<action> pairs for a certain pci bus +identified by its controller's base register address, as defined in the "reg" +property in the device tree. + +pci_iommu_extra = pci@<addr1>,<bdf>,<action>,<bdf>,<action>, + pci@<addr2>,<bdf>,<action>,<bdf>,<action>,... + +where: + <addr> is the base register address of the pci controller for which the + subsequent <bdf>,<action> pairs apply + <bdf> identifies to which B.D.F the action applies to + <action> can be: + - "vfs=<number>" to specify that for the PCI EP identified previously by + the <bdf> to include mappings for <number> of VFs. + The variant "noari_vfs=<number>" is available to disable taking ARI into + account. + - "hp" to specify that on this <bdf> there will be a hot-plugged device so + it needs a mapping +The device tree property must be placed under the correct pci controller node +and only the bdf and action pairs need to be specified, like this: + +pci-iommu-extra = "<bdf>,<action>,<bdf>,<action>,..."; + +Note: the env var has priority over the device tree property. + +For example, given this configuration on bus 6: + +=> pci 6 +Scanning PCI devices on bus 6 +BusDevFun VendorId DeviceId Device Class Sub-Class +_____________________________________________________________ +06.00.00 0x8086 0x1572 Network controller 0x00 +06.00.01 0x8086 0x1572 Network controller 0x00 + +The following u-boot env var will create iommu mappings for 3 VFs for each PF: + +=> setenv pci_iommu_extra pci@0x3800000,6.0.0,vfs=3,6.0.1,vfs=3 + +For the device tree case, this would be specified like this: + +pci-iommu-extra = "6.0.0,vfs=3,6.0.1,vfs=3"; + +To add an iommu mapping for a hot-plugged device, please see following example: + +=> setenv pci_iommu_extra pci@0x3800000,2.16.0,hp + +For the device tree case, this would be specified like this: + +pci-iommu-extra = "2.16.0,hp"; diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c index 7400b2c..6d3391d 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c @@ -437,13 +437,52 @@ __weak void fdt_fixup_ecam(void *blob) } #endif +/* + * If it is a non-E part the crypto is disabled on the following SoCs: + * - LS1043A + * - LS1088A + * - LS2080A + * - LS2088A + * and their personalities. + * + * On all other SoCs just the export-controlled ciphers are disabled, that + * means that the following is still working: + * - hashing (using MDHA - message digest hash accelerator) + * - random number generation (using RNG4) + * - cyclic redundancy checking (using CRCA) + * - runtime integrity checker (RTIC) + * + * The linux driver will figure out what is available and what is not. + * Therefore, we just remove the crypto node on the SoCs which have no crypto + * support at all. + */ +static bool crypto_is_disabled(unsigned int svr) +{ + if (IS_E_PROCESSOR(svr)) + return false; + + if (IS_SVR_DEV(svr, SVR_DEV(SVR_LS1043A))) + return true; + + if (IS_SVR_DEV(svr, SVR_DEV(SVR_LS1088A))) + return true; + + if (IS_SVR_DEV(svr, SVR_DEV(SVR_LS2080A))) + return true; + + if (IS_SVR_DEV(svr, SVR_DEV(SVR_LS2088A))) + return true; + + return false; +} + void ft_cpu_setup(void *blob, struct bd_info *bd) { struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); unsigned int svr = gur_in32(&gur->svr); /* delete crypto node if not on an E-processor */ - if (!IS_E_PROCESSOR(svr)) + if (crypto_is_disabled(svr)) fdt_fixup_crypto_node(blob, 0); #if CONFIG_SYS_FSL_SEC_COMPAT >= 4 else { diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index b195723..5362b73 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -72,6 +72,8 @@ dtb-$(CONFIG_MACH_S700) += \ dtb-$(CONFIG_ROCKCHIP_PX30) += \ px30-evb.dtb \ px30-firefly.dtb \ + px30-px30-core-ctouch2.dtb \ + px30-px30-core-edimm2.2.dtb \ rk3326-odroid-go2.dtb dtb-$(CONFIG_ROCKCHIP_RK3036) += \ @@ -279,6 +281,7 @@ dtb-$(CONFIG_ARCH_ZYNQ) += \ zynq-zc770-xm013.dtb \ zynq-zed.dtb \ zynq-zturn.dtb \ + zynq-zturn-v5.dtb \ zynq-zybo.dtb \ zynq-zybo-z7.dtb dtb-$(CONFIG_ARCH_ZYNQMP) += \ @@ -424,6 +427,9 @@ dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \ fsl-ls1012a-2g5rdb.dtb \ fsl-ls1012a-frdm.dtb \ fsl-ls1012a-frwy.dtb +dtb-$(CONFIG_TARGET_SL28) += fsl-ls1028a-kontron-sl28.dtb \ + fsl-ls1028a-kontron-sl28-var3.dtb \ + fsl-ls1028a-kontron-sl28-var4.dtb \ dtb-$(CONFIG_TARGET_DRAGONBOARD410C) += dragonboard410c.dtb dtb-$(CONFIG_TARGET_DRAGONBOARD820C) += dragonboard820c.dtb diff --git a/arch/arm/dts/armada-cp110-master.dtsi b/arch/arm/dts/armada-cp110-master.dtsi index cd5c974..7d0d31d 100644 --- a/arch/arm/dts/armada-cp110-master.dtsi +++ b/arch/arm/dts/armada-cp110-master.dtsi @@ -285,15 +285,18 @@ }; cpm_nand: nand@720000 { - compatible = "marvell,mvebu-pxa3xx-nand"; - reg = <0x720000 0x100>; + compatible = "marvell,armada-8k-nand-controller", + "marvell,armada370-nand-controller"; + reg = <0x720000 0x54>; #address-cells = <1>; - - clocks = <&cpm_syscon0 1 2>; + #size-cells = <0>; + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "core", "reg"; + clocks = <&cpm_syscon0 1 2>, + <&cpm_syscon0 1 17>; + marvell,system-controller = <&cpm_syscon0>; nand-enable-arbiter; num-cs = <1>; - nand-ecc-strength = <4>; - nand-ecc-step-size = <512>; status = "disabled"; }; diff --git a/arch/arm/dts/armada-cp110-slave.dtsi b/arch/arm/dts/armada-cp110-slave.dtsi index b426a4e..6cf2177 100644 --- a/arch/arm/dts/armada-cp110-slave.dtsi +++ b/arch/arm/dts/armada-cp110-slave.dtsi @@ -267,6 +267,22 @@ utmi-port = <UTMI_PHY_TO_USB3_HOST0>; status = "disabled"; }; + + cps_nand: nand@720000 { + compatible = "marvell,armada-8k-nand-controller", + "marvell,armada370-nand-controller"; + reg = <0x720000 0x54>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "core", "reg"; + clocks = <&cps_syscon0 1 2>, + <&cps_syscon0 1 17>; + marvell,system-controller = <&cps_syscon0>; + nand-enable-arbiter; + num-cs = <1>; + status = "disabled"; + }; }; cps_pcie0: pcie@f4600000 { diff --git a/arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi b/arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi new file mode 100644 index 0000000..2375549 --- /dev/null +++ b/arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi @@ -0,0 +1,135 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include <config.h> + +/ { + aliases { + mmc0 = &esdhc0; + mmc1 = &esdhc1; + i2c0 = &i2c0; + i2c1 = &i2c3; + i2c2 = &i2c4; + rtc0 = &rtc; + ethernet0 = &enetc0; + ethernet1 = &enetc1; + ethernet2 = &enetc2; + ethernet3 = &enetc6; + }; + + binman { + filename = "u-boot.rom"; + pad-byte = <0xff>; + + u-boot-spl { + }; + + fit { + offset = <CONFIG_SPL_PAD_TO>; + description = "FIT image with multiple configurations"; + + images { + uboot { + description = "U-Boot"; + type = "firmware"; + os = "u-boot"; + arch = "arm"; + compression = "none"; + load = <CONFIG_SYS_TEXT_BASE>; + + u-boot-nodtb { + }; + }; + + fdt-1 { + description = "fsl-ls1028a-kontron-sl28"; + type = "flat_dt"; + arch = "arm"; + compression = "none"; + + blob { + filename = "arch/arm/dts/fsl-ls1028a-kontron-sl28.dtb"; + }; + }; + + fdt-2 { + description = "fsl-ls1028a-kontron-sl28-var3"; + type = "flat_dt"; + arch = "arm"; + compression = "none"; + + blob { + filename = "arch/arm/dts/fsl-ls1028a-kontron-sl28-var3.dtb"; + }; + }; + + fdt-3 { + description = "fsl-ls1028a-kontron-sl28-var4"; + type = "flat_dt"; + arch = "arm"; + compression = "none"; + + blob { + filename = "arch/arm/dts/fsl-ls1028a-kontron-sl28-var4.dtb"; + }; + }; + }; + + configurations { + default = "conf-1"; + + conf-1 { + description = "fsl-ls1028a-kontron-sl28"; + firmware = "uboot"; + loadables = "uboot"; + fdt = "fdt-1"; + }; + + conf-2 { + description = "fsl-ls1028a-kontron-sl28-var3"; + firmware = "uboot"; + loadables = "uboot"; + fdt = "fdt-2"; + }; + + conf-3 { + description = "fsl-ls1028a-kontron-sl28-var4"; + firmware = "uboot"; + loadables = "uboot"; + fdt = "fdt-3"; + }; + }; + }; + }; +}; + +&i2c0 { + rtc: rtc@32 { + }; +}; + +&fspi { + u-boot,dm-pre-reloc; + flash@0 { + u-boot,dm-pre-reloc; + }; +}; + +&dspi2 { + u-boot,dm-pre-reloc; +}; + +&esdhc0 { + u-boot,dm-pre-reloc; +}; + +&esdhc1 { + u-boot,dm-pre-reloc; +}; + +&serial0 { + u-boot,dm-pre-reloc; +}; + +&sysclk { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var3-u-boot.dtsi b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var3-u-boot.dtsi new file mode 100644 index 0000000..79b771e --- /dev/null +++ b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var3-u-boot.dtsi @@ -0,0 +1,2 @@ +// SPDX-License-Identifier: GPL-2.0+ +#include "fsl-ls1028a-kontron-sl28-u-boot.dtsi" diff --git a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var3.dts b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var3.dts new file mode 100644 index 0000000..0c8b2af --- /dev/null +++ b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var3.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Device Tree file for the Kontron SMARC-sAL28 board. + * + * Copyright (C) 2019 Michael Walle <michael@walle.cc> + * + */ + +/dts-v1/; +#include "fsl-ls1028a-kontron-sl28.dts" + +/ { + model = "Kontron SMARC-sAL28 (Single PHY)"; + compatible = "kontron,sl28-var3", "kontron,sl28", "fsl,ls1028a"; +}; diff --git a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var4-u-boot.dtsi b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var4-u-boot.dtsi new file mode 100644 index 0000000..79b771e --- /dev/null +++ b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var4-u-boot.dtsi @@ -0,0 +1,2 @@ +// SPDX-License-Identifier: GPL-2.0+ +#include "fsl-ls1028a-kontron-sl28-u-boot.dtsi" diff --git a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var4.dts b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var4.dts new file mode 100644 index 0000000..33b1630 --- /dev/null +++ b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var4.dts @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Device Tree file for the Kontron SMARC-sAL28 board. + * + * This is for the network variant 4 which has two ethernet ports. It + * extends the base and provides one more port connected via RGMII. + * + * Copyright (C) 2019 Michael Walle <michael@walle.cc> + * + */ + +/dts-v1/; +#include "fsl-ls1028a-kontron-sl28.dts" +#include <dt-bindings/net/qca-ar803x.h> + +/ { + model = "Kontron SMARC-sAL28 (Dual PHY)"; + compatible = "kontron,sl28-var4", "kontron,sl28", "fsl,ls1028a"; +}; + +&enetc1 { + phy-handle = <&phy1>; + phy-mode = "rgmii-id"; + status = "okay"; +}; + +&mdio0 { + phy1: ethernet-phy@4 { + reg = <0x4>; + eee-broken-1000t; + eee-broken-100tx; + + qca,clk-out-frequency = <125000000>; + qca,clk-out-strength = <AR803X_STRENGTH_FULL>; + + vddio-supply = <&vddh>; + + vddio: vddio-regulator { + regulator-name = "VDDIO"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vddh: vddh-regulator { + regulator-name = "VDDH"; + }; + }; +}; diff --git a/arch/arm/dts/fsl-ls1028a-kontron-sl28.dts b/arch/arm/dts/fsl-ls1028a-kontron-sl28.dts new file mode 100644 index 0000000..9561a58 --- /dev/null +++ b/arch/arm/dts/fsl-ls1028a-kontron-sl28.dts @@ -0,0 +1,189 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Device Tree file for the Kontron SMARC-sAL28 board. + * + * Copyright (C) 2019 Michael Walle <michael@walle.cc> + * + */ + +/dts-v1/; +#include "fsl-ls1028a.dtsi" + +/ { + model = "Kontron SMARC-sAL28"; + compatible = "kontron,sl28", "fsl,ls1028a"; + + aliases { + serial0 = &serial0; + serial1 = &serial1; + serial2 = &lpuart1; + spi0 = &fspi; + spi1 = &dspi2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&dspi2 { + status = "okay"; +}; + +&enetc0 { + phy-handle = <&phy0>; + phy-mode = "sgmii"; + status = "okay"; +}; + +&enetc2 { + status = "disabled"; +}; + +&enetc6 { + status = "disabled"; +}; + +&esdhc0 { + sd-uhs-sdr104; + sd-uhs-sdr50; + sd-uhs-sdr25; + sd-uhs-sdr12; + status = "okay"; +}; + +&esdhc1 { + mmc-hs200-1_8v; + mmc-hs400-1_8v; + bus-width = <8>; + status = "okay"; +}; + +&fspi { + status = "okay"; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + m25p,fast-read; + spi-max-frequency = <133000000>; + reg = <0>; + /* The following setting enables 1-1-2 (CMD-ADDR-DATA) mode */ + spi-rx-bus-width = <2>; /* 2 SPI Rx lines */ + spi-tx-bus-width = <1>; /* 1 SPI Tx line */ + + partition@0 { + reg = <0x000000 0x010000>; + label = "rcw"; + read-only; + }; + + partition@10000 { + reg = <0x010000 0x0f0000>; + label = "failsafe bootloader"; + read-only; + }; + + partition@100000 { + reg = <0x100000 0x040000>; + label = "failsafe DP firmware"; + read-only; + }; + + partition@140000 { + reg = <0x140000 0x0a0000>; + label = "failsafe trusted firmware"; + read-only; + }; + + partition@1e0000 { + reg = <0x1e0000 0x020000>; + label = "reserved"; + read-only; + }; + + partition@200000 { + reg = <0x200000 0x010000>; + label = "configuration store"; + }; + + partition@210000 { + reg = <0x210000 0x0f0000>; + label = "bootloader"; + }; + + partition@300000 { + reg = <0x300000 0x040000>; + label = "DP firmware"; + }; + + partition@340000 { + reg = <0x340000 0x0a0000>; + label = "trusted firmware"; + }; + + partition@3e0000 { + reg = <0x3e0000 0x020000>; + label = "bootloader environment"; + }; + }; +}; + +&i2c0 { + status = "okay"; + + rtc@32 { + compatible = "microcrystal,rv8803"; + reg = <0x32>; + }; + + eeprom@50 { + compatible = "atmel,24c32"; + reg = <0x50>; + pagesize = <32>; + }; +}; + +&i2c3 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c32"; + reg = <0x50>; + pagesize = <32>; + }; +}; + +&lpuart1 { + status = "okay"; +}; + +&mdio0 { + status = "okay"; + phy0: ethernet-phy@5 { + reg = <0x5>; + eee-broken-1000t; + eee-broken-100tx; + }; +}; + +&serial0 { + status = "okay"; +}; + +&serial1 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; + +&usb2 { + status = "okay"; +}; diff --git a/arch/arm/dts/px30-engicam-common.dtsi b/arch/arm/dts/px30-engicam-common.dtsi new file mode 100644 index 0000000..bd5bde9 --- /dev/null +++ b/arch/arm/dts/px30-engicam-common.dtsi @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Engicam srl + * Copyright (c) 2020 Amarula Solutions + * Copyright (c) 2020 Amarula Solutions(India) + */ + +/ { + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; /* +5V */ + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; +}; + +&gmac { + clock_in_out = "output"; + phy-supply = <&vcc_3v3>; /* +3V3_SOM */ + snps,reset-active-low; + snps,reset-delays-us = <0 50000 50000>; + snps,reset-gpio = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&sdmmc { + cap-sd-highspeed; + card-detect-delay = <800>; + vmmc-supply = <&vcc_3v3>; /* +3V3_SOM */ + vqmmc-supply = <&vcc_3v3>; + status = "okay"; +}; + +&uart2 { + pinctrl-0 = <&uart2m1_xfer>; + status = "okay"; +}; diff --git a/arch/arm/dts/px30-engicam-ctouch2.dtsi b/arch/arm/dts/px30-engicam-ctouch2.dtsi new file mode 100644 index 0000000..58425b1 --- /dev/null +++ b/arch/arm/dts/px30-engicam-ctouch2.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Engicam srl + * Copyright (c) 2020 Amarula Solutions + * Copyright (c) 2020 Amarula Solutions(India) + */ + +#include "px30-engicam-common.dtsi" diff --git a/arch/arm/dts/px30-engicam-edimm2.2.dtsi b/arch/arm/dts/px30-engicam-edimm2.2.dtsi new file mode 100644 index 0000000..cb00988 --- /dev/null +++ b/arch/arm/dts/px30-engicam-edimm2.2.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Engicam srl + * Copyright (c) 2020 Amarula Solutions(India) + */ + +#include "px30-engicam-common.dtsi" diff --git a/arch/arm/dts/px30-px30-core-ctouch2.dts b/arch/arm/dts/px30-px30-core-ctouch2.dts new file mode 100644 index 0000000..2da0128 --- /dev/null +++ b/arch/arm/dts/px30-px30-core-ctouch2.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd + * Copyright (c) 2020 Engicam srl + * Copyright (c) 2020 Amarula Solutions + * Copyright (c) 2020 Amarula Solutions(India) + */ + +/dts-v1/; +#include "px30.dtsi" +#include "px30-engicam-ctouch2.dtsi" +#include "px30-px30-core.dtsi" + +/ { + model = "Engicam PX30.Core C.TOUCH 2.0"; + compatible = "engicam,px30-core-ctouch2", "engicam,px30-px30-core", + "rockchip,px30"; + + chosen { + stdout-path = "serial2:115200n8"; + }; +}; diff --git a/arch/arm/dts/px30-px30-core-edimm2.2.dts b/arch/arm/dts/px30-px30-core-edimm2.2.dts new file mode 100644 index 0000000..c36280c --- /dev/null +++ b/arch/arm/dts/px30-px30-core-edimm2.2.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd + * Copyright (c) 2020 Engicam srl + * Copyright (c) 2020 Amarula Solutions(India) + */ + +/dts-v1/; +#include "px30.dtsi" +#include "px30-engicam-edimm2.2.dtsi" +#include "px30-px30-core.dtsi" + +/ { + model = "Engicam PX30.Core EDIMM2.2 Starter Kit"; + compatible = "engicam,px30-core-edimm2.2", "engicam,px30-px30-core", + "rockchip,px30"; + + chosen { + stdout-path = "serial2:115200n8"; + }; +}; diff --git a/arch/arm/dts/px30-px30-core.dtsi b/arch/arm/dts/px30-px30-core.dtsi new file mode 100644 index 0000000..16e6cf2 --- /dev/null +++ b/arch/arm/dts/px30-px30-core.dtsi @@ -0,0 +1,232 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd + * Copyright (c) 2020 Engicam srl + * Copyright (c) 2020 Amarula Solutons + * Copyright (c) 2020 Amarula Solutons(India) + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/rockchip.h> + +/ { + compatible = "engicam,px30-px30-core", "rockchip,px30"; +}; + +&cpu0 { + cpu-supply = <&vdd_arm>; +}; + +&cpu1 { + cpu-supply = <&vdd_arm>; +}; + +&cpu2 { + cpu-supply = <&vdd_arm>; +}; + +&cpu3 { + cpu-supply = <&vdd_arm>; +}; + +&emmc { + cap-mmc-highspeed; + mmc-hs200-1_8v; + non-removable; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PA7 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc5v0_sys>; + + regulators { + vdd_log: DCDC_REG1 { + regulator-name = "vdd_log"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vdd_arm: DCDC_REG2 { + regulator-name = "vdd_arm"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_3v3: DCDC_REG4 { + regulator-name = "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc3v3_sys: DCDC_REG5 { + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_1v0: LDO_REG1 { + regulator-name = "vcc_1v0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc_1v8: LDO_REG2 { + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_1v0: LDO_REG3 { + regulator-name = "vdd_1v0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc3v0_pmu: LDO_REG4 { + regulator-name = "vcc3v0_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + + }; + }; + + vccio_sd: LDO_REG5 { + regulator-name = "vccio_sd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc5v0_host: SWITCH_REG2 { + regulator-name = "vcc5v0_host"; + regulator-always-on; + regulator-boot-on; + }; + }; + }; +}; + +&io_domains { + vccio1-supply = <&vcc_3v3>; + vccio2-supply = <&vcc_3v3>; + vccio3-supply = <&vcc_3v3>; + vccio4-supply = <&vcc_3v3>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_1v8>; + status = "okay"; +}; + +&pinctrl { + pmic { + pmic_int: pmic_int { + rockchip,pins = <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pmu_io_domains { + pmuio1-supply = <&vcc_3v3>; + pmuio2-supply = <&vcc_3v3>; + status = "okay"; +}; + +&tsadc { + rockchip,hw-tshut-mode = <1>; + rockchip,hw-tshut-polarity = <1>; + status = "okay"; +}; diff --git a/arch/arm/dts/rk3288-rock-pi-n8-u-boot.dtsi b/arch/arm/dts/rk3288-rock-pi-n8-u-boot.dtsi index e9d7404..538607d 100644 --- a/arch/arm/dts/rk3288-rock-pi-n8-u-boot.dtsi +++ b/arch/arm/dts/rk3288-rock-pi-n8-u-boot.dtsi @@ -5,6 +5,12 @@ #include "rk3288-u-boot.dtsi" +/{ + chosen { + stdout-path = &uart2; + }; +}; + &dmc { rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d 0x6 0x0 0x8 0x4 0x17 0x24 0xd 0x6 diff --git a/arch/arm/dts/rk3288-tinker-u-boot.dtsi b/arch/arm/dts/rk3288-tinker-u-boot.dtsi index 732aa4f..56d10c8 100644 --- a/arch/arm/dts/rk3288-tinker-u-boot.dtsi +++ b/arch/arm/dts/rk3288-tinker-u-boot.dtsi @@ -17,6 +17,13 @@ rockchip,sdram-params = <0x20d266a4 0x5b6 2 533000000 6 9 0>; }; +&i2c2 { + m24c08@50 { + compatible = "at,24c08", "i2c-eeprom"; + reg = <0x50>; + }; +}; + &pinctrl { u-boot,dm-pre-reloc; }; diff --git a/arch/arm/dts/rk3288-tinker.dts b/arch/arm/dts/rk3288-tinker.dts index 4b8405f..8b1848c 100644 --- a/arch/arm/dts/rk3288-tinker.dts +++ b/arch/arm/dts/rk3288-tinker.dts @@ -27,18 +27,7 @@ status = "okay"; }; -&uart2 { - reg-shift = <2>; -}; - &usb_host1 { vbus-supply = <&vcc5v0_host>; status = "okay"; }; - -&i2c2 { - m24c08@50 { - compatible = "at,24c08", "i2c-eeprom"; - reg = <0x50>; - }; -}; diff --git a/arch/arm/dts/versal-mini-emmc0.dts b/arch/arm/dts/versal-mini-emmc0.dts index 7826a28..6a6e746 100644 --- a/arch/arm/dts/versal-mini-emmc0.dts +++ b/arch/arm/dts/versal-mini-emmc0.dts @@ -16,10 +16,10 @@ #size-cells = <2>; model = "Xilinx Versal MINI eMMC0"; - clk25: clk25 { + clk200: clk200 { compatible = "fixed-clock"; #clock-cells = <0x0>; - clock-frequency = <25000000>; + clock-frequency = <200000000>; }; dcc: dcc { @@ -38,9 +38,12 @@ sdhci0: sdhci@f1040000 { compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a"; status = "okay"; + non-removable; + disable-wp; + bus-width = <8>; reg = <0x0 0xf1040000 0x0 0x10000>; clock-names = "clk_xin", "clk_ahb"; - clocks = <&clk25 &clk25>; + clocks = <&clk200 &clk200>; xlnx,device_id = <0>; no-1-8-v; xlnx,mio-bank = <0>; diff --git a/arch/arm/dts/versal-mini-emmc1.dts b/arch/arm/dts/versal-mini-emmc1.dts index 2f28f85..c342e6b 100644 --- a/arch/arm/dts/versal-mini-emmc1.dts +++ b/arch/arm/dts/versal-mini-emmc1.dts @@ -16,10 +16,10 @@ #size-cells = <2>; model = "Xilinx Versal MINI eMMC1"; - clk25: clk25 { + clk200: clk200 { compatible = "fixed-clock"; #clock-cells = <0x0>; - clock-frequency = <25000000>; + clock-frequency = <200000000>; }; dcc: dcc { @@ -38,9 +38,12 @@ sdhci1: sdhci@f1050000 { compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a"; status = "okay"; + non-removable; + disable-wp; + bus-width = <8>; reg = <0x0 0xf1050000 0x0 0x10000>; clock-names = "clk_xin", "clk_ahb"; - clocks = <&clk25 &clk25>; + clocks = <&clk200 &clk200>; xlnx,device_id = <1>; no-1-8-v; xlnx,mio-bank = <0>; diff --git a/arch/arm/dts/zynq-zturn-common.dtsi b/arch/arm/dts/zynq-zturn-common.dtsi new file mode 100644 index 0000000..1d7af02 --- /dev/null +++ b/arch/arm/dts/zynq-zturn-common.dtsi @@ -0,0 +1,120 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2015 Andrea Merello <adnrea.merello@gmail.com> + * Copyright (C) 2017 Alexander Graf <agraf@suse.de> + * + * Based on zynq-zed.dts which is: + * Copyright (C) 2011 - 2014 Xilinx + * Copyright (C) 2012 National Instruments Corp. + * + */ + +/dts-v1/; +/include/ "zynq-7000.dtsi" + +/ { + compatible = "xlnx,zynq-7000"; + + aliases { + ethernet0 = &gem0; + serial0 = &uart1; + serial1 = &uart0; + mmc0 = &sdhci0; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x40000000>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-leds { + compatible = "gpio-leds"; + usr-led1 { + label = "usr-led1"; + gpios = <&gpio0 0x0 0x1>; + default-state = "off"; + }; + + usr-led2 { + label = "usr-led2"; + gpios = <&gpio0 0x9 0x1>; + default-state = "off"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + K1 { + label = "K1"; + gpios = <&gpio0 0x32 0x1>; + linux,code = <0x66>; + wakeup-source; + autorepeat; + }; + }; +}; + +&clkc { + ps-clk-frequency = <33333333>; +}; + +&qspi { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&gem0 { + status = "okay"; + phy-mode = "rgmii-id"; + phy-handle = <ðernet_phy>; + + ethernet_phy: ethernet-phy@0 { + }; +}; + +&sdhci0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&uart0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&uart1 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&usb0 { + status = "okay"; + dr_mode = "host"; +}; + +&can0 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <400000>; + + stlm75@49 { + status = "okay"; + compatible = "lm75"; + reg = <0x49>; + }; + + accelerometer@53 { + compatible = "adi,adxl345", "adxl345", "adi,adxl34x", "adxl34x"; + reg = <0x53>; + interrupt-parent = <&intc>; + interrupts = <0x0 0x1e 0x4>; + }; +}; diff --git a/arch/arm/dts/zynq-zturn-v5.dts b/arch/arm/dts/zynq-zturn-v5.dts new file mode 100644 index 0000000..536632a --- /dev/null +++ b/arch/arm/dts/zynq-zturn-v5.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0 + +/dts-v1/; +/include/ "zynq-zturn-common.dtsi" + +/ { + model = "Zynq Z-Turn MYIR Board V5"; + compatible = "myir,zynq-zturn-v5", "xlnx,zynq-7000"; +}; + +&gem0 { + ethernet_phy: ethernet-phy@0 { + reg = <0x3>; + }; +}; diff --git a/arch/arm/dts/zynq-zturn.dts b/arch/arm/dts/zynq-zturn.dts index 600e8ee..620b24a 100644 --- a/arch/arm/dts/zynq-zturn.dts +++ b/arch/arm/dts/zynq-zturn.dts @@ -1,122 +1,15 @@ // SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2015 Andrea Merello <adnrea.merello@gmail.com> - * Copyright (C) 2017 Alexander Graf <agraf@suse.de> - * - * Based on zynq-zed.dts which is: - * Copyright (C) 2011 - 2014 Xilinx - * Copyright (C) 2012 National Instruments Corp. - * - */ /dts-v1/; -/include/ "zynq-7000.dtsi" +/include/ "zynq-zturn-common.dtsi" / { model = "Zynq Z-Turn MYIR Board"; compatible = "myir,zynq-zturn", "xlnx,zynq-7000"; - - aliases { - ethernet0 = &gem0; - serial0 = &uart1; - serial1 = &uart0; - mmc0 = &sdhci0; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x40000000>; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - gpio-leds { - compatible = "gpio-leds"; - usr-led1 { - label = "usr-led1"; - gpios = <&gpio0 0x0 0x1>; - default-state = "off"; - }; - - usr-led2 { - label = "usr-led2"; - gpios = <&gpio0 0x9 0x1>; - default-state = "off"; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - autorepeat; - K1 { - label = "K1"; - gpios = <&gpio0 0x32 0x1>; - linux,code = <0x66>; - wakeup-source; - autorepeat; - }; - }; -}; - -&clkc { - ps-clk-frequency = <33333333>; -}; - -&qspi { - u-boot,dm-pre-reloc; - status = "okay"; }; &gem0 { - status = "okay"; - phy-mode = "rgmii-id"; - phy-handle = <ðernet_phy>; - ethernet_phy: ethernet-phy@0 { reg = <0x0>; }; }; - -&sdhci0 { - u-boot,dm-pre-reloc; - status = "okay"; -}; - -&uart0 { - u-boot,dm-pre-reloc; - status = "okay"; -}; - -&uart1 { - u-boot,dm-pre-reloc; - status = "okay"; -}; - -&usb0 { - status = "okay"; - dr_mode = "host"; -}; - -&can0 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - clock-frequency = <400000>; - - stlm75@49 { - status = "okay"; - compatible = "lm75"; - reg = <0x49>; - }; - - accelerometer@53 { - compatible = "adi,adxl345", "adxl345", "adi,adxl34x", "adxl34x"; - reg = <0x53>; - interrupt-parent = <&intc>; - interrupts = <0x0 0x1e 0x4>; - }; -}; diff --git a/arch/arm/dts/zynqmp-mini-qspi.dts b/arch/arm/dts/zynqmp-mini-qspi.dts index a76e640..9b4320f 100644 --- a/arch/arm/dts/zynqmp-mini-qspi.dts +++ b/arch/arm/dts/zynqmp-mini-qspi.dts @@ -70,7 +70,7 @@ reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; - spi-max-frequency = <108000000>; + spi-max-frequency = <40000000>; }; }; diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index baa9fa8..24a64b7 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -396,7 +396,7 @@ struct ccsr_gur { #define FSL_CHASSIS3_EC2_REGSR 27 #define FSL_CHASSIS3_EC1_REGSR_PRTCL_MASK 0x00000003 #define FSL_CHASSIS3_EC1_REGSR_PRTCL_SHIFT 0 -#define FSL_CHASSIS3_EC2_REGSR_PRTCL_MASK 0x00000007 +#define FSL_CHASSIS3_EC2_REGSR_PRTCL_MASK 0x0000000C #define FSL_CHASSIS3_EC2_REGSR_PRTCL_SHIFT 2 #define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK 0x001F0000 #define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT 16 diff --git a/arch/arm/mach-imx/mx6/soc.c b/arch/arm/mach-imx/mx6/soc.c index e129286..a636107 100644 --- a/arch/arm/mach-imx/mx6/soc.c +++ b/arch/arm/mach-imx/mx6/soc.c @@ -34,7 +34,7 @@ struct scu_regs { u32 fpga_rev; }; -#if defined(CONFIG_IMX_THERMAL) +#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_IMX_THERMAL) static const struct imx_thermal_plat imx6_thermal_plat = { .regs = (void *)ANATOP_BASE_ADDR, .fuse_bank = 1, diff --git a/arch/arm/mach-rockchip/px30/Kconfig b/arch/arm/mach-rockchip/px30/Kconfig index f5373c6..16090f5 100644 --- a/arch/arm/mach-rockchip/px30/Kconfig +++ b/arch/arm/mach-rockchip/px30/Kconfig @@ -2,10 +2,31 @@ if ROCKCHIP_PX30 config TARGET_EVB_PX30 bool "EVB_PX30" + help + This target config option used for below listed px30 boards. + + EVB_PX30: + * EVB_PX30 is an evaluation board for Rockchip PX30. config TARGET_ODROID_GO2 bool "ODROID_GO2" +config TARGET_PX30_CORE + bool "Engicam PX30.Core" + help + PX30.Core EDIMM2.2: + * PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam. + * EDIMM2.2 is a Form Factor Capacitive Evaluation Board from Engicam. + * PX30.Core needs to mount on top of EDIMM2.2 for creating complete + PX30.Core EDIMM2.2 Starter Kit. + + PX30.Core CTOUCH2: + * PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam. + * CTOUCH2.0 is a general purpose Carrier board with capacitive + touch interface support. + * PX30.Core needs to mount on top of CTOUCH2.0 for creating complete + PX30.Core C.TOUCH Carrier board. + config ROCKCHIP_BOOT_MODE_REG default 0xff010200 @@ -39,6 +60,7 @@ config DEBUG_UART_CHANNEL For using the UART for early debugging the route to use needs to be declared (0 or 1). +source "board/engicam/px30_core/Kconfig" source "board/hardkernel/odroid_go2/Kconfig" source "board/rockchip/evb_px30/Kconfig" diff --git a/arch/arm/mach-zynq/spl.c b/arch/arm/mach-zynq/spl.c index cb8cfd2..d09141c 100644 --- a/arch/arm/mach-zynq/spl.c +++ b/arch/arm/mach-zynq/spl.c @@ -9,7 +9,6 @@ #include <init.h> #include <log.h> #include <spl.h> -#include <generated/dt.h> #include <asm/io.h> #include <asm/spl.h> @@ -86,16 +85,3 @@ void spl_board_prepare_for_boot(void) ps7_post_config(); debug("SPL bye\n"); } - -#ifdef CONFIG_SPL_LOAD_FIT -int board_fit_config_name_match(const char *name) -{ - /* Just empty function now - can't decide what to choose */ - debug("%s: Check %s, default %s\n", __func__, name, DEVICE_TREE); - - if (!strcmp(name, DEVICE_TREE)) - return 0; - - return -1; -} -#endif diff --git a/arch/arm/mach-zynqmp/include/mach/sys_proto.h b/arch/arm/mach-zynqmp/include/mach/sys_proto.h index f2b3cea..1c12eac 100644 --- a/arch/arm/mach-zynqmp/include/mach/sys_proto.h +++ b/arch/arm/mach-zynqmp/include/mach/sys_proto.h @@ -9,6 +9,16 @@ #define ZYNQMP_CSU_SILICON_VER_MASK 0xF #define KEY_PTR_LEN 32 +#define IV_SIZE 12 +#define RSA_KEY_SIZE 512 +#define MODULUS_LEN 512 +#define PRIV_EXPO_LEN 512 +#define PUB_EXPO_LEN 4 + +#define ZYNQMP_SHA3_INIT 1 +#define ZYNQMP_SHA3_UPDATE 2 +#define ZYNQMP_SHA3_FINAL 4 +#define ZYNQMP_SHA3_SIZE 48 #define ZYNQMP_FPGA_BIT_AUTH_DDR 1 #define ZYNQMP_FPGA_BIT_AUTH_OCM 2 diff --git a/arch/arm/mach-zynqmp/spl.c b/arch/arm/mach-zynqmp/spl.c index 9dd61e2..88386b2 100644 --- a/arch/arm/mach-zynqmp/spl.c +++ b/arch/arm/mach-zynqmp/spl.c @@ -119,13 +119,3 @@ int spl_start_uboot(void) return 0; } #endif - -#ifdef CONFIG_SPL_LOAD_FIT -int board_fit_config_name_match(const char *name) -{ - /* Just empty function now - can't decide what to choose */ - debug("%s: %s\n", __func__, name); - - return -1; -} -#endif diff --git a/arch/microblaze/Kconfig b/arch/microblaze/Kconfig index ff6b3c7..99a17bc 100644 --- a/arch/microblaze/Kconfig +++ b/arch/microblaze/Kconfig @@ -16,10 +16,14 @@ config TARGET_MICROBLAZE_GENERIC select OF_CONTROL select SUPPORT_SPL select SYSRESET + select DM_SPI + select DM_SPI_FLASH + select SPI imply CMD_DM endchoice +source "board/xilinx/Kconfig" source "board/xilinx/microblaze-generic/Kconfig" endmenu diff --git a/arch/microblaze/cpu/start.S b/arch/microblaze/cpu/start.S index cbec299..9479737 100644 --- a/arch/microblaze/cpu/start.S +++ b/arch/microblaze/cpu/start.S @@ -13,31 +13,108 @@ .text .global _start _start: - /* - * reserve registers: - * r10: Stores little/big endian offset for vectors - * r2: Stores imm opcode - * r3: Stores brai opcode - */ - mts rmsr, r0 /* disable cache */ addi r8, r0, __end mts rslr, r8 - /* TODO: Redo this code to call board_init_f_*() */ + #if defined(CONFIG_SPL_BUILD) addi r1, r0, CONFIG_SPL_STACK_ADDR - mts rshr, r1 - addi r1, r1, -4 /* Decrement SP to top of memory */ -#else -#if CONFIG_VAL(SYS_MALLOC_F_LEN) - addi r1, r0, CONFIG_SYS_INIT_SP_OFFSET - CONFIG_VAL(SYS_MALLOC_F_LEN) #else addi r1, r0, CONFIG_SYS_INIT_SP_OFFSET #endif - mts rshr, r1 + addi r1, r1, -4 /* Decrement SP to top of memory */ + /* Call board_init_f_alloc_reserve with the current stack pointer as + * parameter. */ + add r5, r0, r1 + bralid r15, board_init_f_alloc_reserve + nop + + /* board_init_f_alloc_reserve returns a pointer to the allocated area + * in r3. Set the new stack pointer below this area. */ + add r1, r0, r3 + mts rshr, r1 + addi r1, r1, -4 + + /* Call board_init_f_init_reserve with the address returned by + * board_init_f_alloc_reserve as parameter. */ + add r5, r0, r3 + bralid r15, board_init_f_init_reserve + nop + +#if !defined(CONFIG_SPL_BUILD) + /* Setup vectors with pre-relocation symbols */ + or r5, r0, r0 + bralid r15, __setup_exceptions + nop +#endif + + /* Flush cache before enable cache */ + addik r5, r0, 0 + addik r6, r0, XILINX_DCACHE_BYTE_SIZE + bralid r15, flush_cache + nop + + /* enable instruction and data cache */ + mfs r12, rmsr + ori r12, r12, 0x1a0 + mts rmsr, r12 + +clear_bss: + /* clear BSS segments */ + addi r5, r0, __bss_start + addi r4, r0, __bss_end + cmp r6, r5, r4 + beqi r6, 3f +2: + swi r0, r5, 0 /* write zero to loc */ + addi r5, r5, 4 /* increment to next loc */ + cmp r6, r5, r4 /* check if we have reach the end */ + bnei r6, 2b +3: /* jumping to board_init */ +#ifdef CONFIG_DEBUG_UART + bralid r15, debug_uart_init + nop +#endif +#ifndef CONFIG_SPL_BUILD + or r5, r0, r0 /* flags - empty */ + brai board_init_f +#else + brai board_init_r +#endif +1: bri 1b + +#ifndef CONFIG_SPL_BUILD + .text + .ent __setup_exceptions + .align 2 +/* + * Set up reset, interrupt, user exception and hardware exception vectors. + * + * Parameters: + * r5 - relocation offset (zero when setting up vectors before + * relocation, and gd->reloc_off when setting up vectors after + * relocation) + * - the relocation offset is added to the _exception_handler, + * _interrupt_handler and _hw_exception_handler symbols to reflect the + * post-relocation memory addresses + * + * Reserve registers: + * r10: Stores little/big endian offset for vectors + * r2: Stores imm opcode + * r3: Stores brai opcode + */ +__setup_exceptions: + addik r1, r1, -28 + swi r2, r1, 4 + swi r3, r1, 8 + swi r6, r1, 12 + swi r7, r1, 16 + swi r8, r1, 20 + swi r10, r1, 24 + /* Find-out if u-boot is running on BIG/LITTLE endian platform * There are some steps which is necessary to keep in mind: * 1. Setup offset value to r6 @@ -76,7 +153,7 @@ _start: swi r2, r0, 0x8 /* user vector exception - imm opcode */ swi r3, r0, 0xC /* user vector exception - brai opcode */ - addik r6, r0, _exception_handler + addik r6, r5, _exception_handler sw r6, r1, r0 /* * BIG ENDIAN memory map for user exception @@ -109,7 +186,7 @@ _start: swi r2, r0, 0x10 /* interrupt - imm opcode */ swi r3, r0, 0x14 /* interrupt - brai opcode */ - addik r6, r0, _interrupt_handler + addik r6, r5, _interrupt_handler sw r6, r1, r0 lhu r7, r1, r10 rsubi r8, r10, 0x12 @@ -121,67 +198,26 @@ _start: swi r2, r0, 0x20 /* hardware exception - imm opcode */ swi r3, r0, 0x24 /* hardware exception - brai opcode */ - addik r6, r0, _hw_exception_handler + addik r6, r5, _hw_exception_handler sw r6, r1, r0 lhu r7, r1, r10 rsubi r8, r10, 0x22 sh r7, r0, r8 rsubi r8, r10, 0x26 sh r6, r0, r8 -#endif /* CONFIG_SPL_BUILD */ - - /* Flush cache before enable cache */ - addik r5, r0, 0 - addik r6, r0, XILINX_DCACHE_BYTE_SIZE - bralid r15, flush_cache - nop - - /* enable instruction and data cache */ - mfs r12, rmsr - ori r12, r12, 0x1a0 - mts rmsr, r12 - /* TODO: Redo this code to call board_init_f_*() */ -clear_bss: - /* clear BSS segments */ - addi r5, r0, __bss_start - addi r4, r0, __bss_end - cmp r6, r5, r4 - beqi r6, 3f -2: - swi r0, r5, 0 /* write zero to loc */ - addi r5, r5, 4 /* increment to next loc */ - cmp r6, r5, r4 /* check if we have reach the end */ - bnei r6, 2b -3: /* jumping to board_init */ -#ifdef CONFIG_DEBUG_UART - bralid r15, debug_uart_init - nop -#endif -#ifndef CONFIG_SPL_BUILD - or r5, r0, r0 /* flags - empty */ - addi r31, r0, _gd -#if CONFIG_VAL(SYS_MALLOC_F_LEN) - addi r6, r0, CONFIG_SYS_INIT_SP_OFFSET - swi r6, r31, GD_MALLOC_BASE -#endif - brai board_init_f -#else - addi r31, r0, _gd -#if CONFIG_VAL(SYS_MALLOC_F_LEN) - addi r6, r0, CONFIG_SPL_STACK_ADDR - swi r6, r31, GD_MALLOC_BASE -#endif - brai board_init_r -#endif -1: bri 1b + lwi r10, r1, 24 + lwi r8, r1, 20 + lwi r7, r1, 16 + lwi r6, r1, 12 + lwi r3, r1, 8 + lwi r2, r1, 4 + addik r1, r1, 28 - .section .bss -.align 4 -_gd: - .space GENERATED_GBL_DATA_SIZE + rtsd r15, 8 + or r0, r0, r0 + .end __setup_exceptions -#ifndef CONFIG_SPL_BUILD /* * Read 16bit little endian */ @@ -249,39 +285,10 @@ relocate_code: addi r24, r0, CONFIG_SYS_TEXT_BASE /* Get reloc offset */ rsub r23, r24, r23 /* keep - this is already here gd->reloc_off */ - addik r6, r0, 0x2 /* BIG/LITTLE endian offset */ - lwi r7, r0, 0x28 - swi r6, r0, 0x28 /* used first unused MB vector */ - lbui r10, r0, 0x28 /* used first unused MB vector */ - swi r7, r0, 0x28 - -#ifdef CONFIG_SYS_USR_EXCEP - addik r6, r0, _exception_handler - addk r6, r6, r23 /* add offset */ - sw r6, r1, r0 - lhu r7, r1, r10 - rsubi r8, r10, 0xa - sh r7, r0, r8 - rsubi r8, r10, 0xe - sh r6, r0, r8 -#endif - addik r6, r0, _hw_exception_handler - addk r6, r6, r23 /* add offset */ - sw r6, r1, r0 - lhu r7, r1, r10 - rsubi r8, r10, 0x22 - sh r7, r0, r8 - rsubi r8, r10, 0x26 - sh r6, r0, r8 - - addik r6, r0, _interrupt_handler - addk r6, r6, r23 /* add offset */ - sw r6, r1, r0 - lhu r7, r1, r10 - rsubi r8, r10, 0x12 - sh r7, r0, r8 - rsubi r8, r10, 0x16 - sh r6, r0, r8 + /* Setup vectors with post-relocation symbols */ + add r5, r0, r23 /* load gd->reloc_off to r5 */ + bralid r15, __setup_exceptions + nop /* Check if GOT exist */ addik r21, r23, _got_start diff --git a/arch/sandbox/cpu/sdl.c b/arch/sandbox/cpu/sdl.c index 7dc3dab..d4dab36 100644 --- a/arch/sandbox/cpu/sdl.c +++ b/arch/sandbox/cpu/sdl.c @@ -127,7 +127,8 @@ int sandbox_sdl_init_display(int width, int height, int log2_bpp, sdl.pitch = sdl.width * sdl.depth / 8; SDL_Window *screen = SDL_CreateWindow("U-Boot", SDL_WINDOWPOS_UNDEFINED, SDL_WINDOWPOS_UNDEFINED, - sdl.vis_width, sdl.vis_height, 0); + sdl.vis_width, sdl.vis_height, + SDL_WINDOW_RESIZABLE); if (!screen) { printf("Unable to initialise SDL screen: %s\n", SDL_GetError()); diff --git a/arch/sandbox/cpu/spl.c b/arch/sandbox/cpu/spl.c index 7ab8919..9a77da1 100644 --- a/arch/sandbox/cpu/spl.c +++ b/arch/sandbox/cpu/spl.c @@ -12,6 +12,7 @@ #include <spl.h> #include <asm/spl.h> #include <asm/state.h> +#include <test/test.h> DECLARE_GLOBAL_DATA_PTR; @@ -53,19 +54,14 @@ SPL_LOAD_IMAGE_METHOD("sandbox", 9, BOOT_DEVICE_BOARD, spl_board_load_image); void spl_board_init(void) { struct sandbox_state *state = state_get_current(); - struct udevice *dev; preloader_console_init(); - if (state->show_of_platdata) { - /* - * Scan all the devices so that we can output their platform - * data. See sandbox_spl_probe(). - */ - printf("Scanning misc devices\n"); - for (uclass_first_device(UCLASS_MISC, &dev); - dev; - uclass_next_device(&dev)) - ; + + if (state->run_unittests) { + int ret; + + ret = dm_test_main(state->select_unittests); + /* continue execution into U-Boot */ } } diff --git a/arch/sandbox/cpu/start.c b/arch/sandbox/cpu/start.c index c6a2bbe..58ada13 100644 --- a/arch/sandbox/cpu/start.c +++ b/arch/sandbox/cpu/start.c @@ -365,14 +365,23 @@ static int sandbox_cmdline_cb_log_level(struct sandbox_state *state, SANDBOX_CMDLINE_OPT_SHORT(log_level, 'L', 1, "Set log level (0=panic, 7=debug)"); -static int sandbox_cmdline_cb_show_of_platdata(struct sandbox_state *state, +static int sandbox_cmdline_cb_unittests(struct sandbox_state *state, + const char *arg) +{ + state->run_unittests = true; + + return 0; +} +SANDBOX_CMDLINE_OPT_SHORT(unittests, 'u', 0, "Run unit tests"); + +static int sandbox_cmdline_cb_select_unittests(struct sandbox_state *state, const char *arg) { - state->show_of_platdata = true; + state->select_unittests = arg; return 0; } -SANDBOX_CMDLINE_OPT(show_of_platdata, 0, "Show of-platdata in SPL"); +SANDBOX_CMDLINE_OPT_SHORT(select_unittests, 'k', 1, "Select unit tests to run"); static void setup_ram_buf(struct sandbox_state *state) { diff --git a/arch/sandbox/dts/sandbox.dts b/arch/sandbox/dts/sandbox.dts index 20f6893..8b50a40 100644 --- a/arch/sandbox/dts/sandbox.dts +++ b/arch/sandbox/dts/sandbox.dts @@ -69,6 +69,7 @@ clock-frequency = <400000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c0>; + u-boot,dm-pre-reloc; }; pcic: pci@0 { diff --git a/arch/sandbox/dts/sandbox.dtsi b/arch/sandbox/dts/sandbox.dtsi index 0faad3f..81cdc55 100644 --- a/arch/sandbox/dts/sandbox.dtsi +++ b/arch/sandbox/dts/sandbox.dtsi @@ -29,6 +29,32 @@ }; }; + clk_fixed: clk-fixed { + u-boot,dm-pre-reloc; + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1234>; + }; + + clk_sandbox: clk-sbox { + u-boot,dm-pre-reloc; + compatible = "sandbox,clk"; + #clock-cells = <1>; + assigned-clocks = <&clk_sandbox 3>; + assigned-clock-rates = <321>; + }; + + clk-test { + u-boot,dm-pre-reloc; + compatible = "sandbox,clk-test"; + clocks = <&clk_fixed>, + <&clk_sandbox 1>, + <&clk_sandbox 0>, + <&clk_sandbox 3>, + <&clk_sandbox 2>; + clock-names = "fixed", "i2c", "spi", "uart2", "uart1"; + }; + gpio_a: gpios@0 { u-boot,dm-pre-reloc; gpio-controller; @@ -64,6 +90,7 @@ reg = <0x43>; compatible = "sandbox-rtc"; sandbox,emul = <&emul0>; + u-boot,dm-pre-reloc; }; sandbox_pmic: sandbox_pmic { reg = <0x40>; diff --git a/arch/sandbox/include/asm/state.h b/arch/sandbox/include/asm/state.h index 1bfad30..bca1306 100644 --- a/arch/sandbox/include/asm/state.h +++ b/arch/sandbox/include/asm/state.h @@ -90,8 +90,9 @@ struct sandbox_state { bool skip_delays; /* Ignore any time delays (for test) */ bool show_test_output; /* Don't suppress stdout in tests */ int default_log_level; /* Default log level for sandbox */ - bool show_of_platdata; /* Show of-platdata in SPL */ bool ram_buf_read; /* true if we read the RAM buffer */ + bool run_unittests; /* Run unit tests */ + const char *select_unittests; /* Unit test to run */ /* Pointer to information for each SPI bus/cs */ struct sandbox_spi_info spi[CONFIG_SANDBOX_SPI_MAX_BUS] diff --git a/arch/x86/cpu/apollolake/Kconfig b/arch/x86/cpu/apollolake/Kconfig index 35a425c..c6c1350 100644 --- a/arch/x86/cpu/apollolake/Kconfig +++ b/arch/x86/cpu/apollolake/Kconfig @@ -85,6 +85,8 @@ config APL_SPI_FLASH_BOOT bool "Support booting with SPI-flash driver instead memory-mapped SPI" select TPL_SPI_FLASH_SUPPORT select TPL_SPI_SUPPORT + select TPL_DM_SPI + select TPL_DM_SPI_FLASH help This enables SPI and SPI flash in TPL. Without the this only available boot method is to use memory-mapped SPI. Since this is diff --git a/arch/x86/cpu/apollolake/spl.c b/arch/x86/cpu/apollolake/spl.c index 5a53831..089b37c 100644 --- a/arch/x86/cpu/apollolake/spl.c +++ b/arch/x86/cpu/apollolake/spl.c @@ -90,7 +90,8 @@ static int apl_flash_probe(struct udevice *dev) */ static int apl_flash_bind(struct udevice *dev) { - if (CONFIG_IS_ENABLED(OF_PLATDATA)) { + if (CONFIG_IS_ENABLED(OF_PLATDATA) && + !CONFIG_IS_ENABLED(OF_PLATDATA_PARENT)) { struct dm_spi_slave_platdata *plat; struct udevice *spi; int ret; diff --git a/board/engicam/common/Kconfig b/board/engicam/common/Kconfig new file mode 100644 index 0000000..38328fd --- /dev/null +++ b/board/engicam/common/Kconfig @@ -0,0 +1,8 @@ +config IMX6_ENGICAM_COMMON + bool "Engicam i.MX6 Common code" + depends on SPL && MX6 + default y if TARGET_MX6Q_ENGICAM || TARGET_MX6UL_ENGICAM + help + Common SPL and U-Boot proper code for Engicam i.MX6 targets. + + Enable it in board Kconfig if it uses i.MX6 variant Engicam boards. diff --git a/board/engicam/common/Makefile b/board/engicam/common/Makefile index b392bf6..15f0eaa 100644 --- a/board/engicam/common/Makefile +++ b/board/engicam/common/Makefile @@ -1,5 +1,8 @@ # SPDX-License-Identifier: GPL-2.0+ # Copyright (C) 2016 Amarula Solutions B.V. -obj-y := board.o -obj-$(CONFIG_SPL_BUILD) += spl.o +ifdef CONFIG_SPL_BUILD +obj-$(CONFIG_IMX6_ENGICAM_COMMON) += spl.o +else +obj-$(CONFIG_IMX6_ENGICAM_COMMON) += board.o +endif diff --git a/board/engicam/imx6q/Kconfig b/board/engicam/imx6q/Kconfig index 48eb60c..fab8da0 100644 --- a/board/engicam/imx6q/Kconfig +++ b/board/engicam/imx6q/Kconfig @@ -9,4 +9,6 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "imx6-engicam" +source "board/engicam/common/Kconfig" + endif diff --git a/board/engicam/imx6ul/Kconfig b/board/engicam/imx6ul/Kconfig index e91dd15..58f25d0 100644 --- a/board/engicam/imx6ul/Kconfig +++ b/board/engicam/imx6ul/Kconfig @@ -9,4 +9,6 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "imx6-engicam" +source "board/engicam/common/Kconfig" + endif diff --git a/board/engicam/px30_core/Kconfig b/board/engicam/px30_core/Kconfig new file mode 100644 index 0000000..a03be78 --- /dev/null +++ b/board/engicam/px30_core/Kconfig @@ -0,0 +1,16 @@ +if TARGET_PX30_CORE + +config SYS_BOARD + default "px30_core" + +config SYS_VENDOR + default "engicam" + +config SYS_CONFIG_NAME + default "px30_core" + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select RAM_PX30_DDR4 + +endif diff --git a/board/engicam/px30_core/MAINTAINERS b/board/engicam/px30_core/MAINTAINERS new file mode 100644 index 0000000..b87ca22 --- /dev/null +++ b/board/engicam/px30_core/MAINTAINERS @@ -0,0 +1,13 @@ +PX30-Core-CTOUCH2.0 +M: Jagan Teki <jagan@amarulasolutions.com> +M: Suniel Mahesh <sunil@amarulasolutions.com> +S: Maintained +F: configs/px30-core-ctouch2-px30_defconfig + +PX30-Core-EDIMM2.2 +M: Jagan Teki <jagan@amarulasolutions.com> +M: Suniel Mahesh <sunil@amarulasolutions.com> +S: Maintained +F: board/engicam/px30_core +F: include/configs/px30_core.h +F: configs/px30-core-edimm2.2-px30_defconfig diff --git a/board/engicam/px30_core/Makefile b/board/engicam/px30_core/Makefile new file mode 100644 index 0000000..321fdb0 --- /dev/null +++ b/board/engicam/px30_core/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (c) 2020 Amarula Solutions(India) +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += px30_core.o diff --git a/board/engicam/px30_core/px30_core.c b/board/engicam/px30_core/px30_core.c new file mode 100644 index 0000000..3adc2f1 --- /dev/null +++ b/board/engicam/px30_core/px30_core.c @@ -0,0 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2020 Amarula Solutions(India) + */ diff --git a/board/freescale/common/vid.c b/board/freescale/common/vid.c index 20c97aa..9c51f50 100644 --- a/board/freescale/common/vid.c +++ b/board/freescale/common/vid.c @@ -379,6 +379,7 @@ static int set_voltage_to_LTC(int i2caddress, int vdd) { int ret, vdd_last, vdd_target = vdd; int count = 100, temp = 0; + unsigned char value; /* Scale up to the LTC resolution is 1/4096V */ vdd = (vdd * 4096) / 1000; @@ -391,16 +392,51 @@ static int set_voltage_to_LTC(int i2caddress, int vdd) /* Write the desired voltage code to the regulator */ #ifndef CONFIG_DM_I2C + /* Check write protect state */ + ret = i2c_read(I2C_VOL_MONITOR_ADDR, + PMBUS_CMD_WRITE_PROTECT, 1, + (void *)&value, sizeof(value)); + if (ret) + goto exit; + + if (value != EN_WRITE_ALL_CMD) { + value = EN_WRITE_ALL_CMD; + ret = i2c_write(I2C_VOL_MONITOR_ADDR, + PMBUS_CMD_WRITE_PROTECT, 1, + (void *)&value, sizeof(value)); + if (ret) + goto exit; + } + ret = i2c_write(I2C_VOL_MONITOR_ADDR, - PMBUS_CMD_PAGE_PLUS_WRITE, 1, (void *)&buff, 5); + PMBUS_CMD_PAGE_PLUS_WRITE, 1, + (void *)&buff, sizeof(buff)); #else struct udevice *dev; ret = i2c_get_chip_for_busnum(0, I2C_VOL_MONITOR_ADDR, 1, &dev); - if (!ret) + if (!ret) { + /* Check write protect state */ + ret = dm_i2c_read(dev, + PMBUS_CMD_WRITE_PROTECT, + (void *)&value, sizeof(value)); + if (ret) + goto exit; + + if (value != EN_WRITE_ALL_CMD) { + value = EN_WRITE_ALL_CMD; + ret = dm_i2c_write(dev, + PMBUS_CMD_WRITE_PROTECT, + (void *)&value, sizeof(value)); + if (ret) + goto exit; + } + ret = dm_i2c_write(dev, PMBUS_CMD_PAGE_PLUS_WRITE, - (void *)&buff, 5); + (void *)&buff, sizeof(buff)); + } #endif +exit: if (ret) { printf("VID: I2C failed to write to the volatge regulator\n"); return -1; @@ -892,7 +928,7 @@ exit: static int print_vdd(void) { - int vdd_last, ret, i2caddress; + int vdd_last, ret, i2caddress = 0; ret = i2c_multiplexer_select_vid_channel(I2C_MUX_CH_VOL_MONITOR); if (ret) { diff --git a/board/freescale/common/vid.h b/board/freescale/common/vid.h index 99778e9..65b348e 100644 --- a/board/freescale/common/vid.h +++ b/board/freescale/common/vid.h @@ -18,6 +18,25 @@ /* step the IR regulator in 5mV increments */ #define IR_VDD_STEP_DOWN 5 #define IR_VDD_STEP_UP 5 + +/* LTC3882 */ +#define PMBUS_CMD_WRITE_PROTECT 0x10 +/* + * WRITE_PROTECT command supported values + * 0x80: Disable all writes except WRITE_PROTECT, PAGE, + * STORE_USER_ALL and MFR_EE_UNLOCK commands. + * 0x40: Disable all writes except WRITE_PROTECT, PAGE, STORE_USER_ALL, + * MFR_EE_UNLOCK, OPERATION, CLEAR_PEAKS and CLEAR_FAULTS commands. + * Individual faults can also be cleared by writing a 1 to the + * respective status bit. + * 0x20: Disable all writes except WRITE_PROTECT, PAGE, STORE_USER_ ALL, + * MFR_EE_UNLOCK, OPERATION, CLEAR_PEAKS, CLEAR_FAULTS, ON_OFF_CONFIG + * and VOUT_COMMAND commands. Individual faults can be cleared by + * writing a 1 to the respective status bit. + * 0x00: Enables write to all commands + */ +#define EN_WRITE_ALL_CMD (0) + int adjust_vdd(ulong vdd_override); #endif /* __VID_H_ */ diff --git a/board/kontron/sl28/Kconfig b/board/kontron/sl28/Kconfig new file mode 100644 index 0000000..cdec39b --- /dev/null +++ b/board/kontron/sl28/Kconfig @@ -0,0 +1,18 @@ +if TARGET_SL28 + +config SYS_BOARD + default "sl28" + +config SYS_VENDOR + default "kontron" + +config SYS_SOC + default "fsl-layerscape" + +config SYS_CONFIG_NAME + default "kontron_sl28" + +config SYS_TEXT_BASE + default 0x96000000 + +endif diff --git a/board/kontron/sl28/MAINTAINERS b/board/kontron/sl28/MAINTAINERS new file mode 100644 index 0000000..a7b0fbb --- /dev/null +++ b/board/kontron/sl28/MAINTAINERS @@ -0,0 +1,7 @@ +Kontron SMARC-sAL28 board +M: Michael Walle <michael@walle.cc> +S: Maintained +F: arch/arm/dts/fsl-ls1028a-kontron-sl28-* +F: board/kontron/sl28/ +F: configs/kontron_sl28_defconfig +F: include/configs/kontron_sl28.h diff --git a/board/kontron/sl28/Makefile b/board/kontron/sl28/Makefile new file mode 100644 index 0000000..74d8012 --- /dev/null +++ b/board/kontron/sl28/Makefile @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0+ + +ifndef CONFIG_SPL_BUILD +obj-y += sl28.o cmds.o +endif + +obj-y += common.o ddr.o +obj-$(CONFIG_SPL_BUILD) += spl.o diff --git a/board/kontron/sl28/cmds.c b/board/kontron/sl28/cmds.c new file mode 100644 index 0000000..046d3b4 --- /dev/null +++ b/board/kontron/sl28/cmds.c @@ -0,0 +1,178 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * sl28 extension commands + * + * Copyright (c) 2020 Kontron Europe GmbH + */ + +#include <common.h> +#include <command.h> +#include <i2c.h> +#include <linux/delay.h> + +#define CPLD_I2C_ADDR 0x4a +#define REG_UFM_CTRL 0x02 +#define UFM_CTRL_DCLK BIT(1) +#define UFM_CTRL_DIN BIT(2) +#define UFM_CTRL_PROGRAM BIT(3) +#define UFM_CTRL_ERASE BIT(4) +#define UFM_CTRL_DSHIFT BIT(5) +#define UFM_CTRL_DOUT BIT(6) +#define UFM_CTRL_BUSY BIT(7) + +static int ufm_shift_data(struct udevice *dev, u16 data_in, u16 *data_out) +{ + int i; + int ret; + u16 data = 0; + + /* latch data */ + ret = dm_i2c_reg_write(dev, REG_UFM_CTRL, 0); + if (ret < 0) + return ret; + ret = dm_i2c_reg_write(dev, REG_UFM_CTRL, UFM_CTRL_DCLK); + if (ret < 0) + return ret; + + /* assert drshift */ + ret = dm_i2c_reg_write(dev, REG_UFM_CTRL, + UFM_CTRL_DSHIFT | UFM_CTRL_DCLK); + if (ret < 0) + return ret; + + /* clock 16 data bits, reverse order */ + for (i = 15; i >= 0; i--) { + u8 din = (data_in & (1 << i)) ? UFM_CTRL_DIN : 0; + + ret = dm_i2c_reg_write(dev, REG_UFM_CTRL, UFM_CTRL_DSHIFT + | din); + if (ret < 0) + return ret; + if (data_out) { + ret = dm_i2c_reg_read(dev, REG_UFM_CTRL); + if (ret < 0) + return ret; + if (ret & UFM_CTRL_DOUT) + data |= (1 << i); + } + ret = dm_i2c_reg_write(dev, REG_UFM_CTRL, + UFM_CTRL_DSHIFT | UFM_CTRL_DCLK | din); + if (ret < 0) + return ret; + } + + /* deassert drshift */ + ret = dm_i2c_reg_write(dev, REG_UFM_CTRL, UFM_CTRL_DCLK); + if (ret < 0) + return ret; + + if (data_out) + *data_out = data; + + return ret; +} + +static int ufm_erase(struct udevice *dev) +{ + int ret; + + /* erase, tEPMX is 500ms */ + ret = dm_i2c_reg_write(dev, REG_UFM_CTRL, + UFM_CTRL_DCLK | UFM_CTRL_ERASE); + if (ret < 0) + return ret; + ret = dm_i2c_reg_write(dev, REG_UFM_CTRL, UFM_CTRL_DCLK); + if (ret < 0) + return ret; + mdelay(500); + + return 0; +} + +static int ufm_program(struct udevice *dev) +{ + int ret; + + /* program, tPPMX is 100us */ + ret = dm_i2c_reg_write(dev, REG_UFM_CTRL, + UFM_CTRL_DCLK | UFM_CTRL_PROGRAM); + if (ret < 0) + return ret; + ret = dm_i2c_reg_write(dev, REG_UFM_CTRL, UFM_CTRL_DCLK); + if (ret < 0) + return ret; + udelay(100); + + return 0; +} + +static int ufm_write(struct udevice *dev, u16 data) +{ + int ret; + + ret = ufm_shift_data(dev, data, NULL); + if (ret < 0) + return ret; + + ret = ufm_erase(dev); + if (ret < 0) + return ret; + + return ufm_program(dev); +} + +static int ufm_read(struct udevice *dev, u16 *data) +{ + return ufm_shift_data(dev, 0, data); +} + +static int do_sl28_nvm(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + struct udevice *dev; + u16 nvm; + int ret; + char *endp; + + if (i2c_get_chip_for_busnum(0, CPLD_I2C_ADDR, 1, &dev)) + return CMD_RET_FAILURE; + + if (argc > 1) { + nvm = simple_strtoul(argv[1], &endp, 16); + if (*endp != '\0') { + printf("ERROR: argument is not a valid number\n"); + ret = -EINVAL; + goto out; + } + + /* + * We swap all bits, because the a zero bit in hardware means the + * feature is enabled. But this is hard for the user. + */ + nvm ^= 0xffff; + + ret = ufm_write(dev, nvm); + if (ret) + goto out; + printf("New settings will be activated after the next power cycle!\n"); + } else { + ret = ufm_read(dev, &nvm); + if (ret) + goto out; + nvm ^= 0xffff; + + printf("%04hx\n", nvm); + } + + return CMD_RET_SUCCESS; + +out: + printf("command failed (%d)\n", ret); + return CMD_RET_FAILURE; +} + +static char sl28_help_text[] = + "nvm [<hex>] - display/set the 16 non-volatile bits\n"; + +U_BOOT_CMD_WITH_SUBCMDS(sl28, "SMARC-sAL28 specific", sl28_help_text, + U_BOOT_SUBCMD_MKENT(nvm, 2, 1, do_sl28_nvm)); diff --git a/board/kontron/sl28/common.c b/board/kontron/sl28/common.c new file mode 100644 index 0000000..14704f7 --- /dev/null +++ b/board/kontron/sl28/common.c @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include <common.h> +#include <asm/arch-fsl-layerscape/soc.h> + +int board_early_init_f(void) +{ + fsl_lsch3_early_init_f(); + return 0; +} diff --git a/board/kontron/sl28/ddr.c b/board/kontron/sl28/ddr.c new file mode 100644 index 0000000..d111b6d --- /dev/null +++ b/board/kontron/sl28/ddr.c @@ -0,0 +1,98 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include <common.h> +#include <asm/io.h> +#include <fsl_ddr_sdram.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define DCFG_GPPORCR1 0x20 + +#define GPPORCR1_MEM_MASK (0x7 << 5) +#define GPPORCR1_MEM_512MB_CS0 (0x0 << 5) +#define GPPORCR1_MEM_1GB_CS0 (0x1 << 5) +#define GPPORCR1_MEM_2GB_CS0 (0x2 << 5) +#define GPPORCR1_MEM_4GB_CS0_1 (0x3 << 5) +#define GPPORCR1_MEM_4GB_CS0_2 (0x4 << 5) +#define GPPORCR1_MEM_8GB_CS0_1_2_3 (0x5 << 5) +#define GPPORCR1_MEM_8GB_CS0_1 (0x6 << 5) + +static fsl_ddr_cfg_regs_t __maybe_unused ddr_cfg_regs = { + .cs[0].bnds = 0x0000007f, + .cs[0].config = 0x80044402, + .cs[1].bnds = 0x008000ff, + .cs[1].config = 0x80004402, + + .timing_cfg_0 = 0x9011010c, + .timing_cfg_3 = 0x010c1000, + .timing_cfg_1 = 0xbcb48c66, + .timing_cfg_2 = 0x0fc0d118, + .ddr_sdram_cfg = 0xe70c000c, + .ddr_sdram_cfg_2 = 0x24401111, + .ddr_sdram_mode = 0x00441c70, + .ddr_sdram_mode_3 = 0x00001c70, + .ddr_sdram_mode_5 = 0x00001c70, + .ddr_sdram_mode_7 = 0x00001c70, + .ddr_sdram_mode_2 = 0x00180000, + .ddr_sdram_mode_4 = 0x00180000, + .ddr_sdram_mode_6 = 0x00180000, + .ddr_sdram_mode_8 = 0x00180000, + + .ddr_sdram_interval = 0x0c30030c, + .ddr_data_init = 0xdeadbeef, + + .ddr_sdram_clk_cntl = 0x02400000, + + .timing_cfg_4 = 0x00000001, + .timing_cfg_5 = 0x04401400, + + .ddr_zq_cntl = 0x89080600, + .ddr_wrlvl_cntl = 0x8675f606, + .ddr_wrlvl_cntl_2 = 0x04080700, + .ddr_wrlvl_cntl_3 = 0x00000009, + + .ddr_cdr1 = 0x80040000, + .ddr_cdr2 = 0x0000bc01, +}; + +int fsl_initdram(void) +{ + u32 gpporcr1 = in_le32(DCFG_BASE + DCFG_GPPORCR1); + phys_size_t dram_size; + + switch (gpporcr1 & GPPORCR1_MEM_MASK) { + case GPPORCR1_MEM_2GB_CS0: + dram_size = 0x80000000; + ddr_cfg_regs.cs[1].bnds = 0; + ddr_cfg_regs.cs[1].config = 0; + ddr_cfg_regs.cs[1].config_2 = 0; + break; + case GPPORCR1_MEM_4GB_CS0_1: + dram_size = 0x100000000ULL; + break; + case GPPORCR1_MEM_512MB_CS0: + dram_size = 0x20000000; + fallthrough; /* for now */ + case GPPORCR1_MEM_1GB_CS0: + dram_size = 0x40000000; + fallthrough; /* for now */ + case GPPORCR1_MEM_4GB_CS0_2: + dram_size = 0x100000000ULL; + fallthrough; /* for now */ + case GPPORCR1_MEM_8GB_CS0_1: + case GPPORCR1_MEM_8GB_CS0_1_2_3: + dram_size = 0x200000000ULL; + fallthrough; /* for now */ + default: + panic("Unsupported memory configuration (%08x)\n", + gpporcr1 & GPPORCR1_MEM_MASK); + break; + } + + if (!IS_ENABLED(CONFIG_SPL) || IS_ENABLED(CONFIG_SPL_BUILD)) + fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0); + + gd->ram_size = dram_size; + + return 0; +} diff --git a/board/kontron/sl28/sl28.c b/board/kontron/sl28/sl28.c new file mode 100644 index 0000000..b18127c --- /dev/null +++ b/board/kontron/sl28/sl28.c @@ -0,0 +1,68 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include <common.h> +#include <malloc.h> +#include <errno.h> +#include <fsl_ddr.h> +#include <fdt_support.h> +#include <linux/libfdt.h> +#include <env_internal.h> +#include <asm/arch-fsl-layerscape/soc.h> +#include <asm/arch-fsl-layerscape/fsl_icid.h> +#include <i2c.h> +#include <asm/arch/soc.h> +#include <fsl_immap.h> +#include <netdev.h> + +#include <fdtdec.h> +#include <miiphy.h> + +DECLARE_GLOBAL_DATA_PTR; + +int board_init(void) +{ + if (CONFIG_IS_ENABLED(FSL_CAAM)) + sec_init(); + + return 0; +} + +int board_eth_init(struct bd_info *bis) +{ + return pci_eth_init(bis); +} + +int checkboard(void) +{ + printf("EL: %d\n", current_el()); + return 0; +} + +void detail_board_ddr_info(void) +{ + puts("\nDDR "); + print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, ""); + print_ddr_info(0); +} + +int ft_board_setup(void *blob, struct bd_info *bd) +{ + u64 base[CONFIG_NR_DRAM_BANKS]; + u64 size[CONFIG_NR_DRAM_BANKS]; + int nbanks = CONFIG_NR_DRAM_BANKS; + int i; + + ft_cpu_setup(blob, bd); + + /* fixup DT for the two GPP DDR banks */ + for (i = 0; i < nbanks; i++) { + base[i] = gd->bd->bi_dram[i].start; + size[i] = gd->bd->bi_dram[i].size; + } + + fdt_fixup_memory_banks(blob, base, size, nbanks); + + fdt_fixup_icid(blob); + + return 0; +} diff --git a/board/kontron/sl28/spl.c b/board/kontron/sl28/spl.c new file mode 100644 index 0000000..fa5829e --- /dev/null +++ b/board/kontron/sl28/spl.c @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include <common.h> +#include <asm/io.h> +#include <asm/spl.h> + +#define DCFG_RCWSR25 0x160 +#define GPINFO_HW_VARIANT_MASK 0xff + +int sl28_variant(void) +{ + return in_le32(DCFG_BASE + DCFG_RCWSR25) & GPINFO_HW_VARIANT_MASK; +} + +int board_fit_config_name_match(const char *name) +{ + int variant = sl28_variant(); + + switch (variant) { + case 3: + return strcmp(name, "fsl-ls1028a-kontron-sl28-var3"); + case 4: + return strcmp(name, "fsl-ls1028a-kontron-sl28-var4"); + default: + return strcmp(name, "fsl-ls1028a-kontron-sl28"); + } +} + +void board_boot_order(u32 *spl_boot_list) +{ + spl_boot_list[0] = BOOT_DEVICE_SPI; +} diff --git a/board/sandbox/sandbox.c b/board/sandbox/sandbox.c index 937ce28..18a605d 100644 --- a/board/sandbox/sandbox.c +++ b/board/sandbox/sandbox.c @@ -21,10 +21,12 @@ */ gd_t *gd; +#if !CONFIG_IS_ENABLED(OF_PLATDATA) /* Add a simple GPIO device */ U_BOOT_DEVICE(gpio_sandbox) = { .name = "sandbox_gpio", }; +#endif void flush_cache(unsigned long start, unsigned long size) { diff --git a/board/xilinx/Kconfig b/board/xilinx/Kconfig index c80d0a8..64507b5 100644 --- a/board/xilinx/Kconfig +++ b/board/xilinx/Kconfig @@ -50,9 +50,34 @@ config XILINX_OF_BOARD_DTB_ADDR config BOOT_SCRIPT_OFFSET hex "Boot script offset" - depends on ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_VERSAL - default 0xFC0000 if ARCH_ZYNQ + depends on ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_VERSAL || MICROBLAZE + default 0xFC0000 if ARCH_ZYNQ || MICROBLAZE default 0x3E80000 if ARCH_ZYNQMP default 0x7F80000 if ARCH_VERSAL help - Specifies distro boot script offset in NAND/NOR flash. + Specifies distro boot script offset in NAND/QSPI/NOR flash. + +config ZYNQ_MAC_IN_EEPROM + bool "Reading MAC address from EEPROM" + help + Enable this option if your MAC address is saved in eeprom and + xlnx,eeprom DT property in chosen node points to it. + +if ZYNQ_MAC_IN_EEPROM + +config ZYNQ_GEM_I2C_MAC_OFFSET + hex "Set the I2C MAC offset" + default 0x0 + depends on DM_I2C + help + Set the MAC offset for i2C. + +endif + +config CMD_FRU + bool "FRU information for product" + help + This option enables FRU commands to capture and display FRU + information present in the device. The FRU Information is used + to primarily to provide "inventory" information about the boards + that the FRU Information Device is located on. diff --git a/board/xilinx/common/Makefile b/board/xilinx/common/Makefile new file mode 100644 index 0000000..2120284 --- /dev/null +++ b/board/xilinx/common/Makefile @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# (C) Copyright 2020 Xilinx, Inc. +# Michal Simek <michal.simek@xilinx.com> +# + +obj-y += board.o +ifndef CONFIG_SPL_BUILD +obj-$(CONFIG_CMD_FRU) += fru.o fru_ops.o +endif diff --git a/board/xilinx/common/board.c b/board/xilinx/common/board.c index b0f60c4..cdc06a3 100644 --- a/board/xilinx/common/board.c +++ b/board/xilinx/common/board.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * (C) Copyright 2014 - 2019 Xilinx, Inc. + * (C) Copyright 2014 - 2020 Xilinx, Inc. * Michal Simek <michal.simek@xilinx.com> */ @@ -11,7 +11,14 @@ #include <dm/uclass.h> #include <i2c.h> #include <linux/sizes.h> +#include <malloc.h> #include "board.h" +#include <dm.h> +#include <i2c_eeprom.h> +#include <net.h> +#include <generated/dt.h> + +#include "fru.h" #if defined(CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET) int zynq_board_read_rom_ethaddr(unsigned char *ethaddr) @@ -41,6 +48,277 @@ int zynq_board_read_rom_ethaddr(unsigned char *ethaddr) } #endif +#define EEPROM_HEADER_MAGIC 0xdaaddeed +#define EEPROM_HDR_MANUFACTURER_LEN 16 +#define EEPROM_HDR_NAME_LEN 16 +#define EEPROM_HDR_REV_LEN 8 +#define EEPROM_HDR_SERIAL_LEN 20 +#define EEPROM_HDR_NO_OF_MAC_ADDR 4 +#define EEPROM_HDR_ETH_ALEN ETH_ALEN + +struct xilinx_board_description { + u32 header; + char manufacturer[EEPROM_HDR_MANUFACTURER_LEN + 1]; + char name[EEPROM_HDR_NAME_LEN + 1]; + char revision[EEPROM_HDR_REV_LEN + 1]; + char serial[EEPROM_HDR_SERIAL_LEN + 1]; + u8 mac_addr[EEPROM_HDR_NO_OF_MAC_ADDR][EEPROM_HDR_ETH_ALEN + 1]; +}; + +static int highest_id = -1; +static struct xilinx_board_description **board_info; + +#define XILINX_I2C_DETECTION_BITS sizeof(struct fru_common_hdr) + +/* Variable which stores pointer to array which stores eeprom content */ +struct xilinx_legacy_format { + char board_sn[18]; /* 0x0 */ + char unused0[14]; /* 0x12 */ + char eth_mac[6]; /* 0x20 */ + char unused1[170]; /* 0x26 */ + char board_name[11]; /* 0xd0 */ + char unused2[5]; /* 0xdc */ + char board_revision[3]; /* 0xe0 */ + char unused3[29]; /* 0xe3 */ +}; + +static void xilinx_eeprom_legacy_cleanup(char *eeprom, int size) +{ + int i; + char byte; + + for (i = 0; i < size; i++) { + byte = eeprom[i]; + + /* Remove all ffs and spaces */ + if (byte == 0xff || byte == ' ') + eeprom[i] = 0; + + /* Convert strings to lower case */ + if (byte >= 'A' && byte <= 'Z') + eeprom[i] = byte + 'a' - 'A'; + } +} + +static int xilinx_read_eeprom_legacy(struct udevice *dev, char *name, + struct xilinx_board_description *desc) +{ + int ret, size; + struct xilinx_legacy_format *eeprom_content; + bool eth_valid = false; + + size = sizeof(*eeprom_content); + + eeprom_content = calloc(1, size); + if (!eeprom_content) + return -ENOMEM; + + debug("%s: I2C EEPROM read pass data at %p\n", __func__, + eeprom_content); + + ret = dm_i2c_read(dev, 0, (uchar *)eeprom_content, size); + if (ret) { + debug("%s: I2C EEPROM read failed\n", __func__); + free(eeprom_content); + return ret; + } + + xilinx_eeprom_legacy_cleanup((char *)eeprom_content, size); + + printf("Xilinx I2C Legacy format at %s:\n", name); + printf(" Board name:\t%s\n", eeprom_content->board_name); + printf(" Board rev:\t%s\n", eeprom_content->board_revision); + printf(" Board SN:\t%s\n", eeprom_content->board_sn); + + eth_valid = is_valid_ethaddr((const u8 *)eeprom_content->eth_mac); + if (eth_valid) + printf(" Ethernet mac:\t%pM\n", eeprom_content->eth_mac); + + /* Terminating \0 chars ensure end of string */ + strcpy(desc->name, eeprom_content->board_name); + strcpy(desc->revision, eeprom_content->board_revision); + strcpy(desc->serial, eeprom_content->board_sn); + if (eth_valid) + memcpy(desc->mac_addr[0], eeprom_content->eth_mac, ETH_ALEN); + + desc->header = EEPROM_HEADER_MAGIC; + + free(eeprom_content); + + return ret; +} + +static bool xilinx_detect_legacy(u8 *buffer) +{ + int i; + char c; + + for (i = 0; i < XILINX_I2C_DETECTION_BITS; i++) { + c = buffer[i]; + + if (c < '0' || c > '9') + return false; + } + + return true; +} + +static int xilinx_read_eeprom_fru(struct udevice *dev, char *name, + struct xilinx_board_description *desc) +{ + int ret, eeprom_size; + u8 *fru_content; + + /* FIXME this is shortcut - if eeprom type is wrong it will fail */ + eeprom_size = i2c_eeprom_size(dev); + + fru_content = calloc(1, eeprom_size); + if (!fru_content) + return -ENOMEM; + + debug("%s: I2C EEPROM read pass data at %p\n", __func__, + fru_content); + + ret = dm_i2c_read(dev, 0, (uchar *)fru_content, + eeprom_size); + if (ret) { + debug("%s: I2C EEPROM read failed\n", __func__); + free(fru_content); + return ret; + } + + printf("Xilinx I2C FRU format at %s:\n", name); + fru_capture((unsigned long)fru_content); + ret = fru_display(0); + if (ret) { + printf("FRU format decoding failed.\n"); + return ret; + } + + if (desc->header == EEPROM_HEADER_MAGIC) { + debug("Information already filled\n"); + return -EINVAL; + } + + /* It is clear that FRU was captured and structures were filled */ + strncpy(desc->manufacturer, (char *)fru_data.brd.manufacturer_name, + sizeof(desc->manufacturer)); + strncpy(desc->name, (char *)fru_data.brd.product_name, + sizeof(desc->name)); + strncpy(desc->revision, (char *)fru_data.brd.rev, + sizeof(desc->revision)); + strncpy(desc->serial, (char *)fru_data.brd.serial_number, + sizeof(desc->serial)); + desc->header = EEPROM_HEADER_MAGIC; + + return 0; +} + +static bool xilinx_detect_fru(u8 *buffer) +{ + u8 checksum = 0; + int i; + + checksum = fru_checksum((u8 *)buffer, sizeof(struct fru_common_hdr)); + if (checksum) { + debug("%s Common header CRC FAIL\n", __func__); + return false; + } + + bool all_zeros = true; + /* Checksum over all zeros is also zero that's why detect this case */ + for (i = 0; i < sizeof(struct fru_common_hdr); i++) { + if (buffer[i] != 0) + all_zeros = false; + } + + if (all_zeros) + return false; + + debug("%s Common header CRC PASS\n", __func__); + return true; +} + +static int xilinx_read_eeprom_single(char *name, + struct xilinx_board_description *desc) +{ + int ret; + struct udevice *dev; + ofnode eeprom; + u8 buffer[XILINX_I2C_DETECTION_BITS]; + + eeprom = ofnode_get_aliases_node(name); + if (!ofnode_valid(eeprom)) + return -ENODEV; + + ret = uclass_get_device_by_ofnode(UCLASS_I2C_EEPROM, eeprom, &dev); + if (ret) + return ret; + + ret = dm_i2c_read(dev, 0, buffer, sizeof(buffer)); + if (ret) { + debug("%s: I2C EEPROM read failed\n", __func__); + return ret; + } + + debug("%s: i2c memory detected: %s\n", __func__, name); + + if (CONFIG_IS_ENABLED(CMD_FRU) && xilinx_detect_fru(buffer)) + return xilinx_read_eeprom_fru(dev, name, desc); + + if (xilinx_detect_legacy(buffer)) + return xilinx_read_eeprom_legacy(dev, name, desc); + + return -ENODEV; +} + +__maybe_unused int xilinx_read_eeprom(void) +{ + int id, ret; + char name_buf[8]; /* 8 bytes should be enough for nvmem+number */ + struct xilinx_board_description *desc; + + highest_id = dev_read_alias_highest_id("nvmem"); + /* No nvmem aliases present */ + if (highest_id < 0) + return -EINVAL; + + board_info = calloc(1, sizeof(desc) * highest_id); + if (!board_info) + return -ENOMEM; + + debug("%s: Highest ID %d, board_info %p\n", __func__, + highest_id, board_info); + + for (id = 0; id <= highest_id; id++) { + snprintf(name_buf, sizeof(name_buf), "nvmem%d", id); + + /* Alloc structure */ + desc = board_info[id]; + if (!desc) { + desc = calloc(1, sizeof(*desc)); + if (!desc) + return -ENOMEM; + + board_info[id] = desc; + } + + /* Ignoring return value for supporting multiple chips */ + ret = xilinx_read_eeprom_single(name_buf, desc); + if (ret) { + free(desc); + board_info[id] = NULL; + } + } + + /* + * Consider to clean board_info structure when board/cards are not + * detected. + */ + + return 0; +} + #if defined(CONFIG_OF_BOARD) || defined(CONFIG_OF_SEPARATE) void *board_fdt_blob_setup(void) { @@ -75,12 +353,36 @@ void *board_fdt_blob_setup(void) } #endif +#if defined(CONFIG_BOARD_LATE_INIT) +static int env_set_by_index(const char *name, int index, char *data) +{ + char var[32]; + + if (!index) + sprintf(var, "board_%s", name); + else + sprintf(var, "card%d_%s", index, name); + + return env_set(var, data); +} + int board_late_init_xilinx(void) { u32 ret = 0; + int i, id, macid = 0; + struct xilinx_board_description *desc; phys_size_t bootm_size = gd->ram_size; + struct bd_info *bd = gd->bd; + + if (!CONFIG_IS_ENABLED(MICROBLAZE) && bd->bi_dram[0].start) { + ulong scriptaddr; - if (CONFIG_IS_ENABLED(ARCH_ZYNQ)) + scriptaddr = env_get_hex("scriptaddr", 0); + ret |= env_set_hex("scriptaddr", + bd->bi_dram[0].start + scriptaddr); + } + + if (CONFIG_IS_ENABLED(ARCH_ZYNQ) || CONFIG_IS_ENABLED(MICROBLAZE)) bootm_size = min(bootm_size, (phys_size_t)(SZ_512M + SZ_256M)); ret |= env_set_hex("script_offset_f", CONFIG_BOOT_SCRIPT_OFFSET); @@ -88,8 +390,49 @@ int board_late_init_xilinx(void) ret |= env_set_addr("bootm_low", (void *)gd->ram_base); ret |= env_set_addr("bootm_size", (void *)bootm_size); + for (id = 0; id <= highest_id; id++) { + desc = board_info[id]; + if (desc && desc->header == EEPROM_HEADER_MAGIC) { + if (desc->manufacturer[0]) + ret |= env_set_by_index("manufacturer", id, + desc->manufacturer); + if (desc->name[0]) + ret |= env_set_by_index("name", id, + desc->name); + if (desc->revision[0]) + ret |= env_set_by_index("rev", id, + desc->revision); + if (desc->serial[0]) + ret |= env_set_by_index("serial", id, + desc->serial); + + if (!CONFIG_IS_ENABLED(NET)) + continue; + + for (i = 0; i < EEPROM_HDR_NO_OF_MAC_ADDR; i++) { + if (!desc->mac_addr[i]) + continue; + + if (is_valid_ethaddr((const u8 *)desc->mac_addr[i])) + ret |= eth_env_set_enetaddr_by_index("eth", + macid++, desc->mac_addr[i]); + } + } + } + if (ret) printf("%s: Saving run time variables FAILED\n", __func__); return 0; } +#endif + +int __maybe_unused board_fit_config_name_match(const char *name) +{ + debug("%s: Check %s, default %s\n", __func__, name, DEVICE_TREE); + + if (!strcmp(name, DEVICE_TREE)) + return 0; + + return -1; +} diff --git a/board/xilinx/common/board.h b/board/xilinx/common/board.h index 180dfbc..69e6424 100644 --- a/board/xilinx/common/board.h +++ b/board/xilinx/common/board.h @@ -9,4 +9,6 @@ int board_late_init_xilinx(void); +int xilinx_read_eeprom(void); + #endif /* BOARD_XILINX_COMMON_BOARD_H */ diff --git a/board/xilinx/common/fru.c b/board/xilinx/common/fru.c new file mode 100644 index 0000000..ccf4872 --- /dev/null +++ b/board/xilinx/common/fru.c @@ -0,0 +1,91 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * (C) Copyright 2019 - 2020 Xilinx, Inc. + */ + +#include <common.h> +#include <command.h> +#include <fdtdec.h> +#include <malloc.h> + +#include "fru.h" + +static int do_fru_capture(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + unsigned long addr; + char *endp; + + if (argc < cmdtp->maxargs) + return CMD_RET_USAGE; + + addr = simple_strtoul(argv[2], &endp, 16); + if (*argv[1] == 0 || *endp != 0) + return -1; + + return fru_capture(addr); +} + +static int do_fru_display(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + fru_display(1); + return CMD_RET_SUCCESS; +} + +static int do_fru_generate(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + unsigned long addr; + + if (argc < cmdtp->maxargs) + return CMD_RET_USAGE; + + addr = simple_strtoul(argv[2], NULL, 16); + + return fru_generate(addr, argv[3], argv[4], argv[5], argv[6], argv[7]); +} + +static struct cmd_tbl cmd_fru_sub[] = { + U_BOOT_CMD_MKENT(capture, 3, 0, do_fru_capture, "", ""), + U_BOOT_CMD_MKENT(display, 2, 0, do_fru_display, "", ""), + U_BOOT_CMD_MKENT(board_gen, 8, 0, do_fru_generate, "", ""), +}; + +static int do_fru(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + struct cmd_tbl *c; + int ret; + + if (argc < 2) + return CMD_RET_USAGE; + + c = find_cmd_tbl(argv[1], &cmd_fru_sub[0], + ARRAY_SIZE(cmd_fru_sub)); + if (!c) + return CMD_RET_USAGE; + + ret = c->cmd(c, flag, argc, argv); + + return cmd_process_error(c, ret); +} + +/***************************************************/ +#ifdef CONFIG_SYS_LONGHELP +static char fru_help_text[] = + "capture <addr> - Parse and capture FRU table present at address.\n" + "fru display - Displays content of FRU table that was captured using\n" + " fru capture command\n" + "fru board_gen <addr> <manufacturer> <board name> <serial number>\n" + " <part number> <revision> - Generate FRU format with\n" + " board info area filled based on parameters. <addr> is\n" + " pointing to place where FRU is generated.\n" + ; +#endif + +U_BOOT_CMD( + fru, 8, 1, do_fru, + "FRU table info", + fru_help_text +) diff --git a/board/xilinx/common/fru.h b/board/xilinx/common/fru.h new file mode 100644 index 0000000..a3e6520 --- /dev/null +++ b/board/xilinx/common/fru.h @@ -0,0 +1,83 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2019 Xilinx, Inc. + * Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> + */ + +#ifndef __FRU_H +#define __FRU_H + +struct fru_common_hdr { + u8 version; + u8 off_internal; + u8 off_chassis; + u8 off_board; + u8 off_product; + u8 off_multirec; + u8 pad; + u8 crc; +}; + +#define FRU_BOARD_MAX_LEN 32 + +struct __packed fru_board_info_header { + u8 ver; + u8 len; + u8 lang_code; + u8 time[3]; +}; + +struct __packed fru_board_info_member { + u8 type_len; + u8 *name; +}; + +struct fru_board_data { + u8 ver; + u8 len; + u8 lang_code; + u8 time[3]; + u8 manufacturer_type_len; + u8 manufacturer_name[FRU_BOARD_MAX_LEN]; + u8 product_name_type_len; + u8 product_name[FRU_BOARD_MAX_LEN]; + u8 serial_number_type_len; + u8 serial_number[FRU_BOARD_MAX_LEN]; + u8 part_number_type_len; + u8 part_number[FRU_BOARD_MAX_LEN]; + u8 file_id_type_len; + u8 file_id[FRU_BOARD_MAX_LEN]; + /* Xilinx custom fields */ + u8 rev_type_len; + u8 rev[FRU_BOARD_MAX_LEN]; +}; + +struct fru_table { + bool captured; + struct fru_common_hdr hdr; + struct fru_board_data brd; +}; + +#define FRU_TYPELEN_CODE_MASK 0xC0 +#define FRU_TYPELEN_LEN_MASK 0x3F +#define FRU_COMMON_HDR_VER_MASK 0xF +#define FRU_COMMON_HDR_LEN_MULTIPLIER 8 +#define FRU_LANG_CODE_ENGLISH 0 +#define FRU_LANG_CODE_ENGLISH_1 25 +#define FRU_TYPELEN_EOF 0xC1 + +/* This should be minimum of fields */ +#define FRU_BOARD_AREA_TOTAL_FIELDS 5 +#define FRU_TYPELEN_TYPE_SHIFT 6 +#define FRU_TYPELEN_TYPE_BINARY 0 +#define FRU_TYPELEN_TYPE_ASCII8 3 + +int fru_display(int verbose); +int fru_capture(unsigned long addr); +int fru_generate(unsigned long addr, char *manufacturer, char *board_name, + char *serial_no, char *part_no, char *revision); +u8 fru_checksum(u8 *addr, u8 len); + +extern struct fru_table fru_data; + +#endif /* FRU_H */ diff --git a/board/xilinx/common/fru_ops.c b/board/xilinx/common/fru_ops.c new file mode 100644 index 0000000..fc3add7 --- /dev/null +++ b/board/xilinx/common/fru_ops.c @@ -0,0 +1,362 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * (C) Copyright 2019 - 2020 Xilinx, Inc. + */ + +#include <common.h> +#include <cpu_func.h> +#include <env.h> +#include <fdtdec.h> +#include <log.h> +#include <malloc.h> +#include <asm/io.h> +#include <asm/arch/hardware.h> + +#include "fru.h" + +struct fru_table fru_data __section(.data); + +static u16 fru_cal_area_len(u8 len) +{ + return len * FRU_COMMON_HDR_LEN_MULTIPLIER; +} + +static u8 fru_version(u8 ver) +{ + return ver & FRU_COMMON_HDR_VER_MASK; +} + +static int fru_check_language(u8 code) +{ + if (code != FRU_LANG_CODE_ENGLISH && code != FRU_LANG_CODE_ENGLISH_1) { + printf("FRU_ERROR: Only English Language is supported\n"); + return -EINVAL; + } + + return 0; +} + +u8 fru_checksum(u8 *addr, u8 len) +{ + u8 checksum = 0; + + while (len--) { + checksum += *addr; + addr++; + } + + return checksum; +} + +static int fru_check_type_len(u8 type_len, u8 language, u8 *type) +{ + int len; + + if (type_len == FRU_TYPELEN_EOF) + return -EINVAL; + + *type = (type_len & FRU_TYPELEN_CODE_MASK) >> FRU_TYPELEN_TYPE_SHIFT; + + len = type_len & FRU_TYPELEN_LEN_MASK; + + return len; +} + +/* Return len */ +static u8 fru_gen_type_len(u8 *addr, char *name) +{ + int len = strlen(name); + struct fru_board_info_member *member; + + member = (struct fru_board_info_member *)addr; + member->type_len = FRU_TYPELEN_TYPE_ASCII8 << FRU_TYPELEN_TYPE_SHIFT; + member->type_len |= len; + + debug("%lx/%lx: Add %s to 0x%lx (len 0x%x)\n", (ulong)addr, + (ulong)&member->type_len, name, (ulong)&member->name, len); + memcpy(&member->name, name, len); + + /* Add +1 for type_len parameter */ + return 1 + len; +} + +int fru_generate(unsigned long addr, char *manufacturer, char *board_name, + char *serial_no, char *part_no, char *revision) +{ + struct fru_common_hdr *header = (struct fru_common_hdr *)addr; + struct fru_board_info_header *board_info; + u8 *member; + u8 len, pad, modulo; + + header->version = 1; /* Only version 1.0 is supported now */ + header->off_internal = 0; /* not present */ + header->off_chassis = 0; /* not present */ + header->off_board = (sizeof(*header)) / 8; /* Starting offset 8 */ + header->off_product = 0; /* not present */ + header->off_multirec = 0; /* not present */ + header->pad = 0; + /* + * This unsigned byte can be used to calculate a zero checksum + * for the data area following the header. I.e. the modulo 256 sum of + * the record data bytes plus the checksum byte equals zero. + */ + header->crc = 0; /* Clear before calculation */ + header->crc = 0 - fru_checksum((u8 *)header, sizeof(*header)); + + /* board info is just right after header */ + board_info = (void *)((u8 *)header + sizeof(*header)); + + debug("header %lx, board_info %lx\n", (ulong)header, (ulong)board_info); + + board_info->ver = 1; /* 1.0 spec */ + board_info->lang_code = 0; /* English */ + board_info->time[0] = 0; /* unspecified */ + board_info->time[1] = 0; /* unspecified */ + board_info->time[2] = 0; /* unspecified */ + + /* Member fields are just after board_info header */ + member = (u8 *)board_info + sizeof(*board_info); + + len = fru_gen_type_len(member, manufacturer); /* Board Manufacturer */ + member += len; + len = fru_gen_type_len(member, board_name); /* Board Product name */ + member += len; + len = fru_gen_type_len(member, serial_no); /* Board Serial number */ + member += len; + len = fru_gen_type_len(member, part_no); /* Board part number */ + member += len; + len = fru_gen_type_len(member, "U-Boot generator"); /* File ID */ + member += len; + len = fru_gen_type_len(member, revision); /* Revision */ + member += len; + + *member++ = 0xc1; /* Indication of no more fields */ + + len = member - (u8 *)board_info; /* Find current length */ + len += 1; /* Add checksum there too for calculation */ + + modulo = len % 8; + + if (modulo) { + /* Do not fill last item which is checksum */ + for (pad = 0; pad < 8 - modulo; pad++) + *member++ = 0; + + /* Increase structure size */ + len += 8 - modulo; + } + + board_info->len = len / 8; /* Size in multiples of 8 bytes */ + + *member = 0; /* Clear before calculation */ + *member = 0 - fru_checksum((u8 *)board_info, len); + + debug("checksum %x(addr %x)\n", *member, len); + + env_set_hex("fru_addr", addr); + env_set_hex("filesize", (unsigned long)member - addr + 1); + + return 0; +} + +static int fru_parse_board(unsigned long addr) +{ + u8 i, type; + int len; + u8 *data, *term; + + memcpy(&fru_data.brd.ver, (void *)addr, 6); + addr += 6; + data = (u8 *)&fru_data.brd.manufacturer_type_len; + + for (i = 0; ; i++, data += FRU_BOARD_MAX_LEN) { + len = fru_check_type_len(*(u8 *)addr, fru_data.brd.lang_code, + &type); + /* + * Stop cature if it end of fields + */ + if (len == -EINVAL) + break; + + /* This record type/len field */ + *data++ = *(u8 *)addr; + + /* Add offset to match data */ + addr += 1; + + /* If len is 0 it means empty field that's why skip writing */ + if (!len) + continue; + + /* Record data field */ + memcpy(data, (u8 *)addr, len); + term = data + (u8)len; + *term = 0; + addr += len; + } + + if (i < FRU_BOARD_AREA_TOTAL_FIELDS) { + printf("Board area require minimum %d fields\n", + FRU_BOARD_AREA_TOTAL_FIELDS); + return -EINVAL; + } + + return 0; +} + +int fru_capture(unsigned long addr) +{ + struct fru_common_hdr *hdr; + u8 checksum = 0; + + checksum = fru_checksum((u8 *)addr, sizeof(struct fru_common_hdr)); + if (checksum) { + printf("%s Common header CRC error\n", __func__); + return -EINVAL; + } + + hdr = (struct fru_common_hdr *)addr; + + memcpy((void *)&fru_data.hdr, (void *)hdr, + sizeof(struct fru_common_hdr)); + + fru_data.captured = true; + + if (hdr->off_board) { + addr += fru_cal_area_len(hdr->off_board); + fru_parse_board(addr); + } + + env_set_hex("fru_addr", addr); + + return 0; +} + +static int fru_display_board(struct fru_board_data *brd, int verbose) +{ + u32 time = 0; + u8 type; + int len; + u8 *data; + static const char * const typecode[] = { + "Binary/Unspecified", + "BCD plus", + "6-bit ASCII", + "8-bit ASCII", + "2-byte UNICODE" + }; + static const char * const boardinfo[] = { + "Manufacturer Name", + "Product Name", + "Serial No", + "Part Number", + "File ID", + /* Xilinx spec */ + "Revision Number", + }; + + if (verbose) { + printf("*****BOARD INFO*****\n"); + printf("Version:%d\n", fru_version(brd->ver)); + printf("Board Area Length:%d\n", fru_cal_area_len(brd->len)); + } + + if (fru_check_language(brd->lang_code)) + return -EINVAL; + + time = brd->time[2] << 16 | brd->time[1] << 8 | + brd->time[0]; + + if (verbose) + printf("Time in Minutes from 0:00hrs 1/1/96: %d\n", time); + + data = (u8 *)&brd->manufacturer_type_len; + + for (u8 i = 0; i < (sizeof(boardinfo) / sizeof(*boardinfo)); i++) { + len = fru_check_type_len(*data++, brd->lang_code, + &type); + if (len == -EINVAL) { + printf("**** EOF for Board Area ****\n"); + break; + } + + if (type <= FRU_TYPELEN_TYPE_ASCII8 && + (brd->lang_code == FRU_LANG_CODE_ENGLISH || + brd->lang_code == FRU_LANG_CODE_ENGLISH_1)) + debug("Type code: %s\n", typecode[type]); + else + debug("Type code: %s\n", typecode[type + 1]); + + if (!len) { + debug("%s not found\n", boardinfo[i]); + continue; + } + + switch (type) { + case FRU_TYPELEN_TYPE_BINARY: + debug("Length: %d\n", len); + printf(" %s: 0x%x\n", boardinfo[i], *data); + break; + case FRU_TYPELEN_TYPE_ASCII8: + debug("Length: %d\n", len); + printf(" %s: %s\n", boardinfo[i], data); + break; + default: + debug("Unsupported type %x\n", type); + } + + data += FRU_BOARD_MAX_LEN; + } + + return 0; +} + +static void fru_display_common_hdr(struct fru_common_hdr *hdr, int verbose) +{ + if (!verbose) + return; + + printf("*****COMMON HEADER*****\n"); + printf("Version:%d\n", fru_version(hdr->version)); + if (hdr->off_internal) + printf("Internal Use Area Offset:%d\n", + fru_cal_area_len(hdr->off_internal)); + else + printf("*** No Internal Area ***\n"); + + if (hdr->off_chassis) + printf("Chassis Info Area Offset:%d\n", + fru_cal_area_len(hdr->off_chassis)); + else + printf("*** No Chassis Info Area ***\n"); + + if (hdr->off_board) + printf("Board Area Offset:%d\n", + fru_cal_area_len(hdr->off_board)); + else + printf("*** No Board Area ***\n"); + + if (hdr->off_product) + printf("Product Info Area Offset:%d\n", + fru_cal_area_len(hdr->off_product)); + else + printf("*** No Product Info Area ***\n"); + + if (hdr->off_multirec) + printf("MultiRecord Area Offset:%d\n", + fru_cal_area_len(hdr->off_multirec)); + else + printf("*** No MultiRecord Area ***\n"); +} + +int fru_display(int verbose) +{ + if (!fru_data.captured) { + printf("FRU data not available please run fru parse\n"); + return -EINVAL; + } + + fru_display_common_hdr(&fru_data.hdr, verbose); + + return fru_display_board(&fru_data.brd, verbose); +} diff --git a/board/xilinx/microblaze-generic/microblaze-generic.c b/board/xilinx/microblaze-generic/microblaze-generic.c index 4e569e9..e590999 100644 --- a/board/xilinx/microblaze-generic/microblaze-generic.c +++ b/board/xilinx/microblaze-generic/microblaze-generic.c @@ -18,6 +18,7 @@ #include <dm/lists.h> #include <fdtdec.h> #include <linux/sizes.h> +#include "../common/board.h" DECLARE_GLOBAL_DATA_PTR; @@ -36,7 +37,8 @@ int dram_init(void) int board_late_init(void) { - ulong max_size, lowmem_size; + ulong max_size; + u32 status = 0; #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SYSRESET_MICROBLAZE) int ret; @@ -55,12 +57,19 @@ int board_late_init(void) max_size = gd->start_addr_sp - CONFIG_STACK_SIZE; max_size = round_down(max_size, SZ_16M); - /* Linux default LOWMEM_SIZE is 0x30000000 = 768MB */ - lowmem_size = gd->ram_base + 768 * 1024 * 1024; + status |= env_set_hex("scriptaddr", max_size + SZ_2M); - env_set_addr("initrd_high", (void *)min_t(ulong, max_size, - lowmem_size)); - env_set_addr("fdt_high", (void *)min_t(ulong, max_size, lowmem_size)); + status |= env_set_hex("pxefile_addr_r", max_size + SZ_1M); - return 0; + status |= env_set_hex("kernel_addr_r", gd->ram_base + SZ_32M); + + status |= env_set_hex("fdt_addr_r", gd->ram_base + SZ_32M - SZ_1M); + + status |= env_set_hex("ramdisk_addr_r", + gd->ram_base + SZ_32M + SZ_4M + SZ_2M); + + if (status) + printf("%s: Saving run time variables FAILED\n", __func__); + + return board_late_init_xilinx(); } diff --git a/board/xilinx/versal/Makefile b/board/xilinx/versal/Makefile index 90e0343..4a46ca0 100644 --- a/board/xilinx/versal/Makefile +++ b/board/xilinx/versal/Makefile @@ -6,4 +6,3 @@ obj-y := board.o obj-$(CONFIG_CMD_VERSAL) += cmds.o -obj-y += ../common/board.o diff --git a/board/xilinx/versal/board.c b/board/xilinx/versal/board.c index a5ca4ca..912c114 100644 --- a/board/xilinx/versal/board.c +++ b/board/xilinx/versal/board.c @@ -36,6 +36,9 @@ int board_init(void) fpga_add(fpga_xilinx, &versalpl); #endif + if (CONFIG_IS_ENABLED(DM_I2C) && CONFIG_IS_ENABLED(I2C_EEPROM)) + xilinx_read_eeprom(); + return 0; } diff --git a/board/xilinx/zynq/Makefile b/board/xilinx/zynq/Makefile index 096a7ac..8566171 100644 --- a/board/xilinx/zynq/Makefile +++ b/board/xilinx/zynq/Makefile @@ -4,7 +4,6 @@ # Wolfgang Denk, DENX Software Engineering, wd@denx.de. obj-y := board.o -obj-y += ../common/board.o ifneq ($(CONFIG_XILINX_PS_INIT_FILE),"") PS_INIT_FILE := $(shell cd $(srctree); readlink -f $(CONFIG_XILINX_PS_INIT_FILE)) diff --git a/board/xilinx/zynq/zynq-zturn-v5/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zturn-v5/ps7_init_gpl.c new file mode 100644 index 0000000..5d57386 --- /dev/null +++ b/board/xilinx/zynq/zynq-zturn-v5/ps7_init_gpl.c @@ -0,0 +1,273 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) Xilinx, Inc. + */ + +#include <asm/arch/ps7_init_gpl.h> + +static unsigned long ps7_pll_init_data[] = { + EMIT_WRITE(0xF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0xF8000110, 0x003FFFF0U, 0x000FA220U), + EMIT_MASKWRITE(0xF8000100, 0x0007F000U, 0x00028000U), + EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000010U), + EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000000U), + EMIT_MASKPOLL(0xF800010C, 0x00000001U), + EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000000U), + EMIT_MASKWRITE(0xF8000120, 0x1F003F30U, 0x1F000200U), + EMIT_MASKWRITE(0xF8000114, 0x003FFFF0U, 0x0012C220U), + EMIT_MASKWRITE(0xF8000104, 0x0007F000U, 0x00020000U), + EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000010U), + EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000000U), + EMIT_MASKPOLL(0xF800010C, 0x00000002U), + EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000000U), + EMIT_MASKWRITE(0xF8000124, 0xFFF00003U, 0x0C200003U), + EMIT_MASKWRITE(0xF8000118, 0x003FFFF0U, 0x001452C0U), + EMIT_MASKWRITE(0xF8000108, 0x0007F000U, 0x0001E000U), + EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000010U), + EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000000U), + EMIT_MASKPOLL(0xF800010C, 0x00000004U), + EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000000U), + EMIT_WRITE(0xF8000004, 0x0000767BU), + EMIT_EXIT(), +}; + +static unsigned long ps7_clock_init_data[] = { + EMIT_WRITE(0xF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0xF8000128, 0x03F03F01U, 0x00700F01U), + EMIT_MASKWRITE(0xF8000138, 0x00000011U, 0x00000001U), + EMIT_MASKWRITE(0xF8000140, 0x03F03F71U, 0x00100801U), + EMIT_MASKWRITE(0xF800014C, 0x00003F31U, 0x00000501U), + EMIT_MASKWRITE(0xF8000150, 0x00003F33U, 0x00001401U), + EMIT_MASKWRITE(0xF8000154, 0x00003F33U, 0x00000A03U), + EMIT_MASKWRITE(0xF800015C, 0x03F03F33U, 0x00200501U), + EMIT_MASKWRITE(0xF8000160, 0x007F007FU, 0x00000000U), + EMIT_MASKWRITE(0xF8000168, 0x00003F31U, 0x00000501U), + EMIT_MASKWRITE(0xF8000170, 0x03F03F30U, 0x00200500U), + EMIT_MASKWRITE(0xF8000180, 0x03F03F30U, 0x00400500U), + EMIT_MASKWRITE(0xF80001C4, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0xF800012C, 0x01FFCCCDU, 0x01FD044DU), + EMIT_WRITE(0xF8000004, 0x0000767BU), + EMIT_EXIT(), +}; + +static unsigned long ps7_ddr_init_data[] = { + EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000080U), + EMIT_MASKWRITE(0xF8006004, 0x0007FFFFU, 0x00001082U), + EMIT_MASKWRITE(0xF8006008, 0x03FFFFFFU, 0x03C0780FU), + EMIT_MASKWRITE(0xF800600C, 0x03FFFFFFU, 0x02001001U), + EMIT_MASKWRITE(0xF8006010, 0x03FFFFFFU, 0x00014001U), + EMIT_MASKWRITE(0xF8006014, 0x001FFFFFU, 0x0004285BU), + EMIT_MASKWRITE(0xF8006018, 0xF7FFFFFFU, 0x44E458D3U), + EMIT_MASKWRITE(0xF800601C, 0xFFFFFFFFU, 0x7282BCE5U), + EMIT_MASKWRITE(0xF8006020, 0x7FDFFFFCU, 0x270872D0U), + EMIT_MASKWRITE(0xF8006024, 0x0FFFFFC3U, 0x00000000U), + EMIT_MASKWRITE(0xF8006028, 0x00003FFFU, 0x00002007U), + EMIT_MASKWRITE(0xF800602C, 0xFFFFFFFFU, 0x00000008U), + EMIT_MASKWRITE(0xF8006030, 0xFFFFFFFFU, 0x00040B30U), + EMIT_MASKWRITE(0xF8006034, 0x13FF3FFFU, 0x000116D4U), + EMIT_MASKWRITE(0xF8006038, 0x00000003U, 0x00000000U), + EMIT_MASKWRITE(0xF800603C, 0x000FFFFFU, 0x00000777U), + EMIT_MASKWRITE(0xF8006040, 0xFFFFFFFFU, 0xFFF00000U), + EMIT_MASKWRITE(0xF8006044, 0x0FFFFFFFU, 0x0F666666U), + EMIT_MASKWRITE(0xF8006048, 0x0003F03FU, 0x0003C008U), + EMIT_MASKWRITE(0xF8006050, 0xFF0F8FFFU, 0x77010800U), + EMIT_MASKWRITE(0xF8006058, 0x00010000U, 0x00000000U), + EMIT_MASKWRITE(0xF800605C, 0x0000FFFFU, 0x00005003U), + EMIT_MASKWRITE(0xF8006060, 0x000017FFU, 0x0000003EU), + EMIT_MASKWRITE(0xF8006064, 0x00021FE0U, 0x00020000U), + EMIT_MASKWRITE(0xF8006068, 0x03FFFFFFU, 0x00284141U), + EMIT_MASKWRITE(0xF800606C, 0x0000FFFFU, 0x00001610U), + EMIT_MASKWRITE(0xF8006078, 0x03FFFFFFU, 0x00466111U), + EMIT_MASKWRITE(0xF800607C, 0x000FFFFFU, 0x00032222U), + EMIT_MASKWRITE(0xF80060A4, 0xFFFFFFFFU, 0x10200802U), + EMIT_MASKWRITE(0xF80060A8, 0x0FFFFFFFU, 0x0690CB73U), + EMIT_MASKWRITE(0xF80060AC, 0x000001FFU, 0x000001FEU), + EMIT_MASKWRITE(0xF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU), + EMIT_MASKWRITE(0xF80060B4, 0x00000200U, 0x00000200U), + EMIT_MASKWRITE(0xF80060B8, 0x01FFFFFFU, 0x00200066U), + EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000000U), + EMIT_MASKWRITE(0xF80060C8, 0x000000FFU, 0x00000000U), + EMIT_MASKWRITE(0xF80060DC, 0x00000001U, 0x00000000U), + EMIT_MASKWRITE(0xF80060F0, 0x0000FFFFU, 0x00000000U), + EMIT_MASKWRITE(0xF80060F4, 0x0000000FU, 0x00000008U), + EMIT_MASKWRITE(0xF8006114, 0x000000FFU, 0x00000000U), + EMIT_MASKWRITE(0xF8006118, 0x7FFFFFCFU, 0x40000001U), + EMIT_MASKWRITE(0xF800611C, 0x7FFFFFCFU, 0x40000001U), + EMIT_MASKWRITE(0xF8006120, 0x7FFFFFCFU, 0x40000001U), + EMIT_MASKWRITE(0xF8006124, 0x7FFFFFCFU, 0x40000001U), + EMIT_MASKWRITE(0xF800612C, 0x000FFFFFU, 0x0002A81FU), + EMIT_MASKWRITE(0xF8006130, 0x000FFFFFU, 0x00029822U), + EMIT_MASKWRITE(0xF8006134, 0x000FFFFFU, 0x00026C10U), + EMIT_MASKWRITE(0xF8006138, 0x000FFFFFU, 0x00026013U), + EMIT_MASKWRITE(0xF8006140, 0x000FFFFFU, 0x00000035U), + EMIT_MASKWRITE(0xF8006144, 0x000FFFFFU, 0x00000035U), + EMIT_MASKWRITE(0xF8006148, 0x000FFFFFU, 0x00000035U), + EMIT_MASKWRITE(0xF800614C, 0x000FFFFFU, 0x00000035U), + EMIT_MASKWRITE(0xF8006154, 0x000FFFFFU, 0x0000009FU), + EMIT_MASKWRITE(0xF8006158, 0x000FFFFFU, 0x000000A2U), + EMIT_MASKWRITE(0xF800615C, 0x000FFFFFU, 0x00000090U), + EMIT_MASKWRITE(0xF8006160, 0x000FFFFFU, 0x00000093U), + EMIT_MASKWRITE(0xF8006168, 0x001FFFFFU, 0x000000FFU), + EMIT_MASKWRITE(0xF800616C, 0x001FFFFFU, 0x000000FBU), + EMIT_MASKWRITE(0xF8006170, 0x001FFFFFU, 0x000000F0U), + EMIT_MASKWRITE(0xF8006174, 0x001FFFFFU, 0x000000EDU), + EMIT_MASKWRITE(0xF800617C, 0x000FFFFFU, 0x000000DFU), + EMIT_MASKWRITE(0xF8006180, 0x000FFFFFU, 0x000000E2U), + EMIT_MASKWRITE(0xF8006184, 0x000FFFFFU, 0x000000D0U), + EMIT_MASKWRITE(0xF8006188, 0x000FFFFFU, 0x000000D3U), + EMIT_MASKWRITE(0xF8006190, 0x6FFFFEFEU, 0x00040080U), + EMIT_MASKWRITE(0xF8006194, 0x000FFFFFU, 0x0001FC82U), + EMIT_MASKWRITE(0xF8006204, 0xFFFFFFFFU, 0x00000000U), + EMIT_MASKWRITE(0xF8006208, 0x000703FFU, 0x000003FFU), + EMIT_MASKWRITE(0xF800620C, 0x000703FFU, 0x000003FFU), + EMIT_MASKWRITE(0xF8006210, 0x000703FFU, 0x000003FFU), + EMIT_MASKWRITE(0xF8006214, 0x000703FFU, 0x000003FFU), + EMIT_MASKWRITE(0xF8006218, 0x000F03FFU, 0x000003FFU), + EMIT_MASKWRITE(0xF800621C, 0x000F03FFU, 0x000003FFU), + EMIT_MASKWRITE(0xF8006220, 0x000F03FFU, 0x000003FFU), + EMIT_MASKWRITE(0xF8006224, 0x000F03FFU, 0x000003FFU), + EMIT_MASKWRITE(0xF80062A8, 0x00000FF5U, 0x00000000U), + EMIT_MASKWRITE(0xF80062AC, 0xFFFFFFFFU, 0x00000000U), + EMIT_MASKWRITE(0xF80062B0, 0x003FFFFFU, 0x00005125U), + EMIT_MASKWRITE(0xF80062B4, 0x0003FFFFU, 0x000012A8U), + EMIT_MASKPOLL(0xF8000B74, 0x00002000U), + EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000081U), + EMIT_MASKPOLL(0xF8006054, 0x00000007U), + EMIT_EXIT(), +}; + +static unsigned long ps7_mio_init_data[] = { + EMIT_WRITE(0xF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0xF8000B40, 0x00000FFFU, 0x00000600U), + EMIT_MASKWRITE(0xF8000B44, 0x00000FFFU, 0x00000600U), + EMIT_MASKWRITE(0xF8000B48, 0x00000FFFU, 0x00000672U), + EMIT_MASKWRITE(0xF8000B4C, 0x00000FFFU, 0x00000672U), + EMIT_MASKWRITE(0xF8000B50, 0x00000FFFU, 0x00000674U), + EMIT_MASKWRITE(0xF8000B54, 0x00000FFFU, 0x00000674U), + EMIT_MASKWRITE(0xF8000B58, 0x00000FFFU, 0x00000600U), + EMIT_MASKWRITE(0xF8000B5C, 0xFFFFFFFFU, 0x0018C61CU), + EMIT_MASKWRITE(0xF8000B60, 0xFFFFFFFFU, 0x00F9861CU), + EMIT_MASKWRITE(0xF8000B64, 0xFFFFFFFFU, 0x00F9861CU), + EMIT_MASKWRITE(0xF8000B68, 0xFFFFFFFFU, 0x00F9861CU), + EMIT_MASKWRITE(0xF8000B6C, 0x00007FFFU, 0x00000260U), + EMIT_MASKWRITE(0xF8000B70, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0xF8000B70, 0x00000021U, 0x00000020U), + EMIT_MASKWRITE(0xF8000B70, 0x07FEFFFFU, 0x00000823U), + EMIT_MASKWRITE(0xF8000700, 0x00003FFFU, 0x00001600U), + EMIT_MASKWRITE(0xF8000704, 0x00003FFFU, 0x00000602U), + EMIT_MASKWRITE(0xF8000708, 0x00003FFFU, 0x00000602U), + EMIT_MASKWRITE(0xF800070C, 0x00003FFFU, 0x00000602U), + EMIT_MASKWRITE(0xF8000710, 0x00003FFFU, 0x00000602U), + EMIT_MASKWRITE(0xF8000714, 0x00003FFFU, 0x00000602U), + EMIT_MASKWRITE(0xF8000718, 0x00003FFFU, 0x00000602U), + EMIT_MASKWRITE(0xF800071C, 0x00003FFFU, 0x00000600U), + EMIT_MASKWRITE(0xF8000720, 0x00003FFFU, 0x00000602U), + EMIT_MASKWRITE(0xF8000724, 0x00003FFFU, 0x00000600U), + EMIT_MASKWRITE(0xF8000728, 0x00003FFFU, 0x000016E1U), + EMIT_MASKWRITE(0xF800072C, 0x00003FFFU, 0x000016E0U), + EMIT_MASKWRITE(0xF8000730, 0x00003FFFU, 0x00001640U), + EMIT_MASKWRITE(0xF8000734, 0x00003FFFU, 0x00001640U), + EMIT_MASKWRITE(0xF8000738, 0x00003FFFU, 0x00001621U), + EMIT_MASKWRITE(0xF800073C, 0x00003FFFU, 0x00001620U), + EMIT_MASKWRITE(0xF8000740, 0x00003FFFU, 0x00001202U), + EMIT_MASKWRITE(0xF8000744, 0x00003FFFU, 0x00001202U), + EMIT_MASKWRITE(0xF8000748, 0x00003FFFU, 0x00001202U), + EMIT_MASKWRITE(0xF800074C, 0x00003FFFU, 0x00001202U), + EMIT_MASKWRITE(0xF8000750, 0x00003FFFU, 0x00001202U), + EMIT_MASKWRITE(0xF8000754, 0x00003FFFU, 0x00001202U), + EMIT_MASKWRITE(0xF8000758, 0x00003FFFU, 0x00001203U), + EMIT_MASKWRITE(0xF800075C, 0x00003FFFU, 0x00001203U), + EMIT_MASKWRITE(0xF8000760, 0x00003FFFU, 0x00001203U), + EMIT_MASKWRITE(0xF8000764, 0x00003FFFU, 0x00001203U), + EMIT_MASKWRITE(0xF8000768, 0x00003FFFU, 0x00001203U), + EMIT_MASKWRITE(0xF800076C, 0x00003FFFU, 0x00001203U), + EMIT_MASKWRITE(0xF8000770, 0x00003FFFU, 0x00001204U), + EMIT_MASKWRITE(0xF8000774, 0x00003FFFU, 0x00001205U), + EMIT_MASKWRITE(0xF8000778, 0x00003FFFU, 0x00001204U), + EMIT_MASKWRITE(0xF800077C, 0x00003FFFU, 0x00001205U), + EMIT_MASKWRITE(0xF8000780, 0x00003FFFU, 0x00001204U), + EMIT_MASKWRITE(0xF8000784, 0x00003FFFU, 0x00001204U), + EMIT_MASKWRITE(0xF8000788, 0x00003FFFU, 0x00001204U), + EMIT_MASKWRITE(0xF800078C, 0x00003FFFU, 0x00001204U), + EMIT_MASKWRITE(0xF8000790, 0x00003FFFU, 0x00001205U), + EMIT_MASKWRITE(0xF8000794, 0x00003FFFU, 0x00001204U), + EMIT_MASKWRITE(0xF8000798, 0x00003FFFU, 0x00001204U), + EMIT_MASKWRITE(0xF800079C, 0x00003FFFU, 0x00001204U), + EMIT_MASKWRITE(0xF80007A0, 0x00003FFFU, 0x00001280U), + EMIT_MASKWRITE(0xF80007A4, 0x00003FFFU, 0x00001280U), + EMIT_MASKWRITE(0xF80007A8, 0x00003FFFU, 0x00001280U), + EMIT_MASKWRITE(0xF80007AC, 0x00003FFFU, 0x00001280U), + EMIT_MASKWRITE(0xF80007B0, 0x00003FFFU, 0x00001280U), + EMIT_MASKWRITE(0xF80007B4, 0x00003FFFU, 0x00001280U), + EMIT_MASKWRITE(0xF80007B8, 0x00003F01U, 0x00000201U), + EMIT_MASKWRITE(0xF80007BC, 0x00003F01U, 0x00000201U), + EMIT_MASKWRITE(0xF80007C0, 0x00003FFFU, 0x000012E0U), + EMIT_MASKWRITE(0xF80007C4, 0x00003FFFU, 0x000012E1U), + EMIT_MASKWRITE(0xF80007C8, 0x00003FFFU, 0x00000200U), + EMIT_MASKWRITE(0xF80007CC, 0x00003FFFU, 0x00000200U), + EMIT_MASKWRITE(0xF80007D0, 0x00003FFFU, 0x00001280U), + EMIT_MASKWRITE(0xF80007D4, 0x00003FFFU, 0x00001280U), + EMIT_MASKWRITE(0xF8000830, 0x003F003FU, 0x002E002FU), + EMIT_WRITE(0xF8000004, 0x0000767BU), + EMIT_EXIT(), +}; + +static unsigned long ps7_peripherals_init_data[] = { + EMIT_WRITE(0xF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0xF8000B48, 0x00000180U, 0x00000180U), + EMIT_MASKWRITE(0xF8000B4C, 0x00000180U, 0x00000180U), + EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U), + EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U), + EMIT_WRITE(0xF8000004, 0x0000767BU), + EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U), + EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U), + EMIT_MASKWRITE(0xE000A244, 0x003FFFFFU, 0x00080000U), + EMIT_MASKWRITE(0xE000A00C, 0x003F003FU, 0x00370008U), + EMIT_MASKWRITE(0xE000A248, 0x003FFFFFU, 0x00080000U), + EMIT_MASKWRITE(0xE000A00C, 0x003F003FU, 0x00370000U), + EMIT_MASKDELAY(0xF8F00200, 1), + EMIT_MASKWRITE(0xE000A00C, 0x003F003FU, 0x00370008U), + EMIT_EXIT(), +}; + +static unsigned long ps7_post_config_0[] = { + EMIT_WRITE(0xF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0xF8000900, 0x0000000FU, 0x0000000FU), + EMIT_MASKWRITE(0xF8000240, 0xFFFFFFFFU, 0x00000000U), + EMIT_WRITE(0xF8000004, 0x0000767BU), + EMIT_EXIT(), +}; + +int ps7_post_config(void) +{ + return ps7_config(ps7_post_config_0); +} + +int ps7_init(void) +{ + int ret; + + ret = ps7_config(ps7_mio_init_data); + if (ret != PS7_INIT_SUCCESS) + return ret; + + ret = ps7_config(ps7_pll_init_data); + if (ret != PS7_INIT_SUCCESS) + return ret; + + ret = ps7_config(ps7_clock_init_data); + if (ret != PS7_INIT_SUCCESS) + return ret; + + ret = ps7_config(ps7_ddr_init_data); + if (ret != PS7_INIT_SUCCESS) + return ret; + + ret = ps7_config(ps7_peripherals_init_data); + if (ret != PS7_INIT_SUCCESS) + return ret; + return PS7_INIT_SUCCESS; +} diff --git a/board/xilinx/zynqmp/MAINTAINERS b/board/xilinx/zynqmp/MAINTAINERS index 04fc7f3..9cd4f3f 100644 --- a/board/xilinx/zynqmp/MAINTAINERS +++ b/board/xilinx/zynqmp/MAINTAINERS @@ -3,6 +3,7 @@ M: Michal Simek <michal.simek@xilinx.com> S: Maintained F: arch/arm/dts/zynqmp-* F: arch/arm/dts/avnet-ultra96* +F: board/xilinx/common/ F: board/xilinx/zynqmp/ F: include/configs/xilinx_zynqmp* F: configs/xilinx_zynqmp* diff --git a/board/xilinx/zynqmp/Makefile b/board/xilinx/zynqmp/Makefile index 398c6aa..7d8277c 100644 --- a/board/xilinx/zynqmp/Makefile +++ b/board/xilinx/zynqmp/Makefile @@ -4,7 +4,6 @@ # Michal Simek <michal.simek@xilinx.com> obj-y := zynqmp.o -obj-y += ../common/board.o ifneq ($(CONFIG_XILINX_PS_INIT_FILE),"") PS_INIT_FILE := $(shell cd $(srctree); readlink -f $(CONFIG_XILINX_PS_INIT_FILE)) diff --git a/board/xilinx/zynqmp/cmds.c b/board/xilinx/zynqmp/cmds.c index c0d28a7..cf63ad9 100644 --- a/board/xilinx/zynqmp/cmds.c +++ b/board/xilinx/zynqmp/cmds.c @@ -9,11 +9,22 @@ #include <cpu_func.h> #include <env.h> #include <malloc.h> +#include <memalign.h> #include <zynqmp_firmware.h> #include <asm/arch/hardware.h> #include <asm/arch/sys_proto.h> #include <asm/io.h> +struct aes { + u64 srcaddr; + u64 ivaddr; + u64 keyaddr; + u64 dstaddr; + u64 len; + u64 op; + u64 keysrc; +}; + static int do_zynqmp_verify_secure(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { @@ -107,6 +118,66 @@ static int do_zynqmp_mmio_write(struct cmd_tbl *cmdtp, int flag, int argc, return ret; } +static int do_zynqmp_aes(struct cmd_tbl *cmdtp, int flag, int argc, + char * const argv[]) +{ + ALLOC_CACHE_ALIGN_BUFFER(struct aes, aes, 1); + int ret; + u32 ret_payload[PAYLOAD_ARG_CNT]; + + if (zynqmp_firmware_version() <= PMUFW_V1_0) { + puts("ERR: PMUFW v1.0 or less is detected\n"); + puts("ERR: Encrypt/Decrypt feature is not supported\n"); + puts("ERR: Please upgrade PMUFW\n"); + return CMD_RET_FAILURE; + } + + if (argc < cmdtp->maxargs - 1) + return CMD_RET_USAGE; + + aes->srcaddr = simple_strtoul(argv[2], NULL, 16); + aes->ivaddr = simple_strtoul(argv[3], NULL, 16); + aes->len = simple_strtoul(argv[4], NULL, 16); + aes->op = simple_strtoul(argv[5], NULL, 16); + aes->keysrc = simple_strtoul(argv[6], NULL, 16); + aes->dstaddr = simple_strtoul(argv[7], NULL, 16); + + flush_dcache_range((ulong)aes, (ulong)(aes) + + roundup(sizeof(struct aes), ARCH_DMA_MINALIGN)); + + if (aes->srcaddr && aes->ivaddr && aes->dstaddr) { + flush_dcache_range(aes->srcaddr, + (aes->srcaddr + + roundup(aes->len, ARCH_DMA_MINALIGN))); + flush_dcache_range(aes->ivaddr, + (aes->ivaddr + + roundup(IV_SIZE, ARCH_DMA_MINALIGN))); + flush_dcache_range(aes->dstaddr, + (aes->dstaddr + + roundup(aes->len, ARCH_DMA_MINALIGN))); + } + + if (aes->keysrc == 0) { + if (argc < cmdtp->maxargs) + return CMD_RET_USAGE; + + aes->keyaddr = simple_strtoul(argv[8], NULL, 16); + if (aes->keyaddr) + flush_dcache_range(aes->keyaddr, + (aes->keyaddr + + roundup(KEY_PTR_LEN, + ARCH_DMA_MINALIGN))); + } + + ret = xilinx_pm_request(PM_SECURE_AES, upper_32_bits((ulong)aes), + lower_32_bits((ulong)aes), 0, 0, ret_payload); + if (ret || ret_payload[1]) + printf("Failed: AES op status:0x%x, errcode:0x%x\n", + ret, ret_payload[1]); + + return ret; +} + #ifdef CONFIG_DEFINE_TCM_OCM_MMAP static int do_zynqmp_tcm_init(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) @@ -148,11 +219,145 @@ static int do_zynqmp_pmufw(struct cmd_tbl *cmdtp, int flag, int argc, return 0; } +static int do_zynqmp_rsa(struct cmd_tbl *cmdtp, int flag, int argc, + char * const argv[]) +{ + u64 srcaddr, mod, exp; + u32 srclen, rsaop, size, ret_payload[PAYLOAD_ARG_CNT]; + int ret; + + if (argc != cmdtp->maxargs) + return CMD_RET_USAGE; + + if (zynqmp_firmware_version() <= PMUFW_V1_0) { + puts("ERR: PMUFW v1.0 or less is detected\n"); + puts("ERR: Encrypt/Decrypt feature is not supported\n"); + puts("ERR: Please upgrade PMUFW\n"); + return CMD_RET_FAILURE; + } + + srcaddr = simple_strtoul(argv[2], NULL, 16); + srclen = simple_strtoul(argv[3], NULL, 16); + if (srclen != RSA_KEY_SIZE) { + puts("ERR: srclen should be equal to 0x200(512 bytes)\n"); + return CMD_RET_USAGE; + } + + mod = simple_strtoul(argv[4], NULL, 16); + exp = simple_strtoul(argv[5], NULL, 16); + rsaop = simple_strtoul(argv[6], NULL, 16); + if (!(rsaop == 0 || rsaop == 1)) { + puts("ERR: rsaop should be either 0 or 1\n"); + return CMD_RET_USAGE; + } + + memcpy((void *)srcaddr + srclen, (void *)mod, MODULUS_LEN); + + /* + * For encryption we load public exponent (key size 4096-bits), + * for decryption we load private exponent (32-bits) + */ + if (rsaop) { + memcpy((void *)srcaddr + srclen + MODULUS_LEN, + (void *)exp, PUB_EXPO_LEN); + size = srclen + MODULUS_LEN + PUB_EXPO_LEN; + } else { + memcpy((void *)srcaddr + srclen + MODULUS_LEN, + (void *)exp, PRIV_EXPO_LEN); + size = srclen + MODULUS_LEN + PRIV_EXPO_LEN; + } + + flush_dcache_range((ulong)srcaddr, + (ulong)(srcaddr) + roundup(size, ARCH_DMA_MINALIGN)); + + ret = xilinx_pm_request(PM_SECURE_RSA, upper_32_bits((ulong)srcaddr), + lower_32_bits((ulong)srcaddr), srclen, rsaop, + ret_payload); + if (ret || ret_payload[1]) { + printf("Failed: RSA status:0x%x, errcode:0x%x\n", + ret, ret_payload[1]); + return CMD_RET_FAILURE; + } + + return CMD_RET_SUCCESS; +} + +static int do_zynqmp_sha3(struct cmd_tbl *cmdtp, int flag, + int argc, char * const argv[]) +{ + u64 srcaddr, hashaddr; + u32 srclen, ret_payload[PAYLOAD_ARG_CNT]; + int ret; + + if (argc > cmdtp->maxargs || argc < (cmdtp->maxargs - 1)) + return CMD_RET_USAGE; + + if (zynqmp_firmware_version() <= PMUFW_V1_0) { + puts("ERR: PMUFW v1.0 or less is detected\n"); + puts("ERR: Encrypt/Decrypt feature is not supported\n"); + puts("ERR: Please upgrade PMUFW\n"); + return CMD_RET_FAILURE; + } + + srcaddr = simple_strtoul(argv[2], NULL, 16); + srclen = simple_strtoul(argv[3], NULL, 16); + + if (argc == 5) { + hashaddr = simple_strtoul(argv[4], NULL, 16); + flush_dcache_range(hashaddr, + hashaddr + roundup(ZYNQMP_SHA3_SIZE, + ARCH_DMA_MINALIGN)); + } else { + hashaddr = srcaddr; + } + + /* Check srcaddr or srclen != 0 */ + if (!srcaddr || !srclen) { + puts("ERR: srcaddr & srclen should not be 0\n"); + return CMD_RET_USAGE; + } + + flush_dcache_range(srcaddr, + srcaddr + roundup(srclen, ARCH_DMA_MINALIGN)); + + ret = xilinx_pm_request(PM_SECURE_SHA, 0, 0, 0, + ZYNQMP_SHA3_INIT, ret_payload); + if (ret || ret_payload[1]) { + printf("Failed: SHA INIT status:0x%x, errcode:0x%x\n", + ret, ret_payload[1]); + return CMD_RET_FAILURE; + } + + ret = xilinx_pm_request(PM_SECURE_SHA, upper_32_bits((ulong)srcaddr), + lower_32_bits((ulong)srcaddr), + srclen, ZYNQMP_SHA3_UPDATE, ret_payload); + if (ret || ret_payload[1]) { + printf("Failed: SHA UPDATE status:0x%x, errcode:0x%x\n", + ret, ret_payload[1]); + return CMD_RET_FAILURE; + } + + ret = xilinx_pm_request(PM_SECURE_SHA, upper_32_bits((ulong)hashaddr), + lower_32_bits((ulong)hashaddr), + ZYNQMP_SHA3_SIZE, ZYNQMP_SHA3_FINAL, + ret_payload); + if (ret || ret_payload[1]) { + printf("Failed: SHA FINAL status:0x%x, errcode:0x%x\n", + ret, ret_payload[1]); + return CMD_RET_FAILURE; + } + + return CMD_RET_SUCCESS; +} + static struct cmd_tbl cmd_zynqmp_sub[] = { U_BOOT_CMD_MKENT(secure, 5, 0, do_zynqmp_verify_secure, "", ""), U_BOOT_CMD_MKENT(pmufw, 4, 0, do_zynqmp_pmufw, "", ""), U_BOOT_CMD_MKENT(mmio_read, 3, 0, do_zynqmp_mmio_read, "", ""), U_BOOT_CMD_MKENT(mmio_write, 5, 0, do_zynqmp_mmio_write, "", ""), + U_BOOT_CMD_MKENT(aes, 9, 0, do_zynqmp_aes, "", ""), + U_BOOT_CMD_MKENT(rsa, 7, 0, do_zynqmp_rsa, "", ""), + U_BOOT_CMD_MKENT(sha3, 5, 0, do_zynqmp_sha3, "", ""), #ifdef CONFIG_DEFINE_TCM_OCM_MMAP U_BOOT_CMD_MKENT(tcminit, 3, 0, do_zynqmp_tcm_init, "", ""), #endif @@ -196,6 +401,14 @@ static char zynqmp_help_text[] = "zynqmp mmio_read address - read from address\n" "zynqmp mmio_write address mask value - write value after masking to\n" " address\n" + "zynqmp aes srcaddr ivaddr len aesop keysrc dstaddr [keyaddr] -\n" + " Encrypts or decrypts blob of data at src address and puts it\n" + " back to dstaddr using key and iv at keyaddr and ivaddr\n" + " respectively. keysrc value specifies from which source key\n" + " has to be used, it can be User/Device/PUF key. A value of 0\n" + " for KUP(user key),1 for DeviceKey and 2 for PUF key. The\n" + " aesop value specifies the operation which can be 0 for\n" + " decrypt and 1 for encrypt operation\n" #ifdef CONFIG_DEFINE_TCM_OCM_MMAP "zynqmp tcminit mode - Initialize the TCM with zeros. TCM needs to be\n" " initialized before accessing to avoid ECC\n" @@ -204,11 +417,24 @@ static char zynqmp_help_text[] = " lock(0)/split(1)\n" #endif "zynqmp pmufw address size - load PMU FW configuration object\n" + "zynqmp rsa srcaddr srclen mod exp rsaop -\n" + " Performs RSA encryption and RSA decryption on blob of data\n" + " at srcaddr and puts it back in srcaddr using modulus and\n" + " public or private exponent\n" + " srclen : must be key size(4096 bits)\n" + " exp : private key exponent for RSA decryption(4096 bits)\n" + " public key exponent for RSA encryption(32 bits)\n" + " rsaop : 0 for RSA Decryption, 1 for RSA Encryption\n" + "zynqmp sha3 srcaddr srclen [key_addr] -\n" + " Generates sha3 hash value for data blob at srcaddr and puts\n" + " 48 bytes hash value into srcaddr\n" + " Optional key_addr can be specified for saving sha3 hash value\n" + " Note: srcaddr/srclen should not be 0\n" ; #endif U_BOOT_CMD( - zynqmp, 5, 1, do_zynqmp, + zynqmp, 9, 1, do_zynqmp, "ZynqMP sub-system", zynqmp_help_text ) diff --git a/board/xilinx/zynqmp/tap_delays.c b/board/xilinx/zynqmp/tap_delays.c index 5fde0ae..1cab25f 100644 --- a/board/xilinx/zynqmp/tap_delays.c +++ b/board/xilinx/zynqmp/tap_delays.c @@ -6,8 +6,10 @@ */ #include <common.h> +#include <zynqmp_tap_delay.h> #include <asm/arch/sys_proto.h> #include <linux/delay.h> +#include <mmc.h> #define SD_DLL_CTRL 0xFF180358 #define SD_ITAP_DLY 0xFF180314 @@ -25,43 +27,9 @@ #define SD1_ITAPDLYENA_MASK 0x01000000 #define SD1_ITAPDLYENA 0x01000000 #define SD0_ITAPDLYSEL_MASK 0x000000FF -#define SD0_ITAPDLYSEL_HSD 0x00000015 -#define SD0_ITAPDLYSEL_SD_DDR50 0x0000003D -#define SD0_ITAPDLYSEL_MMC_DDR50 0x00000012 - #define SD1_ITAPDLYSEL_MASK 0x00FF0000 -#define SD1_ITAPDLYSEL_HSD 0x00150000 -#define SD1_ITAPDLYSEL_SD_DDR50 0x003D0000 -#define SD1_ITAPDLYSEL_MMC_DDR50 0x00120000 - #define SD0_OTAPDLYSEL_MASK 0x0000003F -#define SD0_OTAPDLYSEL_MMC_HSD 0x00000006 -#define SD0_OTAPDLYSEL_SD_HSD 0x00000005 -#define SD0_OTAPDLYSEL_SDR50 0x00000003 -#define SD0_OTAPDLYSEL_SDR104_B0 0x00000003 -#define SD0_OTAPDLYSEL_SDR104_B2 0x00000002 -#define SD0_OTAPDLYSEL_SD_DDR50 0x00000004 -#define SD0_OTAPDLYSEL_MMC_DDR50 0x00000006 - #define SD1_OTAPDLYSEL_MASK 0x003F0000 -#define SD1_OTAPDLYSEL_MMC_HSD 0x00060000 -#define SD1_OTAPDLYSEL_SD_HSD 0x00050000 -#define SD1_OTAPDLYSEL_SDR50 0x00030000 -#define SD1_OTAPDLYSEL_SDR104_B0 0x00030000 -#define SD1_OTAPDLYSEL_SDR104_B2 0x00020000 -#define SD1_OTAPDLYSEL_SD_DDR50 0x00040000 -#define SD1_OTAPDLYSEL_MMC_DDR50 0x00060000 - -#define MMC_BANK2 0x2 - -#define MMC_TIMING_UHS_SDR25 1 -#define MMC_TIMING_UHS_SDR50 2 -#define MMC_TIMING_UHS_SDR104 3 -#define MMC_TIMING_UHS_DDR50 4 -#define MMC_TIMING_MMC_HS200 5 -#define MMC_TIMING_SD_HS 6 -#define MMC_TIMING_MMC_DDR52 7 -#define MMC_TIMING_MMC_HS 8 void zynqmp_dll_reset(u8 deviceid) { @@ -82,149 +50,49 @@ void zynqmp_dll_reset(u8 deviceid) zynqmp_mmio_write(SD_DLL_CTRL, SD1_DLL_RST_MASK, 0x0); } -static void arasan_zynqmp_tap_sdr104(u8 deviceid, u8 timing, u8 bank) -{ - if (deviceid == 0) { - /* Program OTAP */ - if (bank == MMC_BANK2) - zynqmp_mmio_write(SD_OTAP_DLY, SD0_OTAPDLYSEL_MASK, - SD0_OTAPDLYSEL_SDR104_B2); - else - zynqmp_mmio_write(SD_OTAP_DLY, SD0_OTAPDLYSEL_MASK, - SD0_OTAPDLYSEL_SDR104_B0); - } else { - /* Program OTAP */ - if (bank == MMC_BANK2) - zynqmp_mmio_write(SD_OTAP_DLY, SD1_OTAPDLYSEL_MASK, - SD1_OTAPDLYSEL_SDR104_B2); - else - zynqmp_mmio_write(SD_OTAP_DLY, SD1_OTAPDLYSEL_MASK, - SD1_OTAPDLYSEL_SDR104_B0); - } -} - -static void arasan_zynqmp_tap_hs(u8 deviceid, u8 timing, u8 bank) -{ - if (deviceid == 0) { - /* Program ITAP */ - zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPCHGWIN_MASK, - SD0_ITAPCHGWIN); - zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPDLYENA_MASK, - SD0_ITAPDLYENA); - zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPDLYSEL_MASK, - SD0_ITAPDLYSEL_HSD); - zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPCHGWIN_MASK, 0x0); - /* Program OTAP */ - if (timing == MMC_TIMING_MMC_HS) - zynqmp_mmio_write(SD_OTAP_DLY, SD0_OTAPDLYSEL_MASK, - SD0_OTAPDLYSEL_MMC_HSD); - else - zynqmp_mmio_write(SD_OTAP_DLY, SD0_OTAPDLYSEL_MASK, - SD0_OTAPDLYSEL_SD_HSD); - } else { - /* Program ITAP */ - zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPCHGWIN_MASK, - SD1_ITAPCHGWIN); - zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPDLYENA_MASK, - SD1_ITAPDLYENA); - zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPDLYSEL_MASK, - SD1_ITAPDLYSEL_HSD); - zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPCHGWIN_MASK, 0x0); - /* Program OTAP */ - if (timing == MMC_TIMING_MMC_HS) - zynqmp_mmio_write(SD_OTAP_DLY, SD1_OTAPDLYSEL_MASK, - SD1_OTAPDLYSEL_MMC_HSD); - else - zynqmp_mmio_write(SD_OTAP_DLY, SD1_OTAPDLYSEL_MASK, - SD1_OTAPDLYSEL_SD_HSD); - } -} - -static void arasan_zynqmp_tap_ddr50(u8 deviceid, u8 timing, u8 bank) +void arasan_zynqmp_set_tapdelay(u8 deviceid, u32 itap_delay, u32 otap_delay) { if (deviceid == 0) { + zynqmp_mmio_write(SD_DLL_CTRL, SD0_DLL_RST_MASK, + SD0_DLL_RST); /* Program ITAP */ - zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPCHGWIN_MASK, - SD0_ITAPCHGWIN); - zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPDLYENA_MASK, - SD0_ITAPDLYENA); - if (timing == MMC_TIMING_UHS_DDR50) - zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPDLYSEL_MASK, - SD0_ITAPDLYSEL_SD_DDR50); - else + if (itap_delay) { + zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPCHGWIN_MASK, + SD0_ITAPCHGWIN); + zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPDLYENA_MASK, + SD0_ITAPDLYENA); zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPDLYSEL_MASK, - SD0_ITAPDLYSEL_MMC_DDR50); - zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPCHGWIN_MASK, 0x0); + itap_delay); + zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPCHGWIN_MASK, + 0x0); + } + /* Program OTAP */ - if (timing == MMC_TIMING_UHS_DDR50) - zynqmp_mmio_write(SD_OTAP_DLY, SD0_OTAPDLYSEL_MASK, - SD0_OTAPDLYSEL_SD_DDR50); - else + if (otap_delay) zynqmp_mmio_write(SD_OTAP_DLY, SD0_OTAPDLYSEL_MASK, - SD0_OTAPDLYSEL_MMC_DDR50); - } else { - /* Program ITAP */ - zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPCHGWIN_MASK, - SD1_ITAPCHGWIN); - zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPDLYENA_MASK, - SD1_ITAPDLYENA); - if (timing == MMC_TIMING_UHS_DDR50) - zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPDLYSEL_MASK, - SD1_ITAPDLYSEL_SD_DDR50); - else - zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPDLYSEL_MASK, - SD1_ITAPDLYSEL_MMC_DDR50); - zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPCHGWIN_MASK, 0x0); - /* Program OTAP */ - if (timing == MMC_TIMING_UHS_DDR50) - zynqmp_mmio_write(SD_OTAP_DLY, SD1_OTAPDLYSEL_MASK, - SD1_OTAPDLYSEL_SD_DDR50); - else - zynqmp_mmio_write(SD_OTAP_DLY, SD1_OTAPDLYSEL_MASK, - SD1_OTAPDLYSEL_MMC_DDR50); - } -} + otap_delay); -static void arasan_zynqmp_tap_sdr50(u8 deviceid, u8 timing, u8 bank) -{ - if (deviceid == 0) { - /* Program OTAP */ - zynqmp_mmio_write(SD_OTAP_DLY, SD0_OTAPDLYSEL_MASK, - SD0_OTAPDLYSEL_SDR50); + zynqmp_mmio_write(SD_DLL_CTRL, SD0_DLL_RST_MASK, 0x0); } else { - /* Program OTAP */ - zynqmp_mmio_write(SD_OTAP_DLY, SD1_OTAPDLYSEL_MASK, - SD1_OTAPDLYSEL_SDR50); - } -} - -void arasan_zynqmp_set_tapdelay(u8 deviceid, u8 timing, u8 bank) -{ - if (deviceid == 0) - zynqmp_mmio_write(SD_DLL_CTRL, SD0_DLL_RST_MASK, - SD0_DLL_RST); - else zynqmp_mmio_write(SD_DLL_CTRL, SD1_DLL_RST_MASK, SD1_DLL_RST); + /* Program ITAP */ + if (itap_delay) { + zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPCHGWIN_MASK, + SD1_ITAPCHGWIN); + zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPDLYENA_MASK, + SD1_ITAPDLYENA); + zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPDLYSEL_MASK, + (itap_delay << 16)); + zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPCHGWIN_MASK, + 0x0); + } - switch (timing) { - case MMC_TIMING_UHS_SDR25: - arasan_zynqmp_tap_hs(deviceid, timing, bank); - break; - case MMC_TIMING_UHS_SDR50: - arasan_zynqmp_tap_sdr50(deviceid, timing, bank); - break; - case MMC_TIMING_UHS_SDR104: - case MMC_TIMING_MMC_HS200: - arasan_zynqmp_tap_sdr104(deviceid, timing, bank); - break; - case MMC_TIMING_UHS_DDR50: - arasan_zynqmp_tap_ddr50(deviceid, timing, bank); - break; - } + /* Program OTAP */ + if (otap_delay) + zynqmp_mmio_write(SD_OTAP_DLY, SD1_OTAPDLYSEL_MASK, + (otap_delay << 16)); - if (deviceid == 0) - zynqmp_mmio_write(SD_DLL_CTRL, SD0_DLL_RST_MASK, 0x0); - else zynqmp_mmio_write(SD_DLL_CTRL, SD1_DLL_RST_MASK, 0x0); + } } diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index 28f067a..731285a 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -40,12 +40,12 @@ #include "pm_cfg_obj.h" #define ZYNQMP_VERSION_SIZE 7 -#define EFUSE_VCU_DIS_MASK 0x100 -#define EFUSE_VCU_DIS_SHIFT 8 -#define EFUSE_GPU_DIS_MASK 0x20 -#define EFUSE_GPU_DIS_SHIFT 5 -#define IDCODE2_PL_INIT_MASK 0x200 -#define IDCODE2_PL_INIT_SHIFT 9 +#define EFUSE_VCU_DIS_MASK 0x100 +#define EFUSE_VCU_DIS_SHIFT 8 +#define EFUSE_GPU_DIS_MASK 0x20 +#define EFUSE_GPU_DIS_SHIFT 5 +#define IDCODE2_PL_INIT_MASK 0x200 +#define IDCODE2_PL_INIT_SHIFT 9 DECLARE_GLOBAL_DATA_PTR; @@ -100,7 +100,7 @@ static const struct { { .id = 0x04738093, .device = 9, - .variants = ZYNQMP_VARIANT_EG, + .variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG, }, { .id = 0x04740093, @@ -190,8 +190,13 @@ static char *zynqmp_get_silicon_idcode_name(void) u32 idcode, idcode2; char name[ZYNQMP_VERSION_SIZE]; u32 ret_payload[PAYLOAD_ARG_CNT]; + int ret; - xilinx_pm_request(PM_GET_CHIPID, 0, 0, 0, 0, ret_payload); + ret = xilinx_pm_request(PM_GET_CHIPID, 0, 0, 0, 0, ret_payload); + if (ret) { + debug("%s: Getting chipid failed\n", __func__); + return "unknown"; + } /* * Firmware returns: @@ -204,7 +209,7 @@ static char *zynqmp_get_silicon_idcode_name(void) idcode = ret_payload[1]; idcode2 = ret_payload[2] >> ZYNQMP_CSU_VERSION_EMPTY_SHIFT; - debug("%s, IDCODE: 0x%0X, IDCODE2: 0x%0X\r\n", __func__, idcode, + debug("%s, IDCODE: 0x%0x, IDCODE2: 0x%0x\r\n", __func__, idcode, idcode2); for (i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) { @@ -216,8 +221,10 @@ static char *zynqmp_get_silicon_idcode_name(void) return "unknown"; /* Add device prefix to the name */ - strncpy(name, "zu", ZYNQMP_VERSION_SIZE); - strncat(&name[2], simple_itoa(zynqmp_devices[i].device), 2); + ret = snprintf(name, ZYNQMP_VERSION_SIZE, "zu%d", + zynqmp_devices[i].device); + if (ret < 0) + return "unknown"; if (zynqmp_devices[i].variants & ZYNQMP_VARIANT_EV) { /* Devices with EV variant might be EG/CG/EV family */ @@ -321,6 +328,9 @@ int board_init(void) if (sizeof(CONFIG_ZYNQMP_SPL_PM_CFG_OBJ_FILE) > 1) zynqmp_pmufw_load_config_object(zynqmp_pm_cfg_obj, zynqmp_pm_cfg_obj_size); +#else + if (CONFIG_IS_ENABLED(DM_I2C) && CONFIG_IS_ENABLED(I2C_EEPROM)) + xilinx_read_eeprom(); #endif printf("EL Level:\tEL%d\n", current_el()); diff --git a/cmd/Kconfig b/cmd/Kconfig index 58864f6..1595de9 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -1074,6 +1074,14 @@ config CMD_CLONE initial flashing by external block device without network or usb support. +config CMD_OPTEE_RPMB + bool "Enable read/write support on RPMB via OPTEE" + depends on SUPPORT_EMMC_RPMB && OPTEE + help + Enable the commands for reading, writing persistent named values + in the Replay Protection Memory Block partition in eMMC by + using Persistent Objects in OPTEE + config CMD_MTD bool "mtd" depends on MTD @@ -2231,6 +2239,7 @@ config CMD_KGDB config CMD_LOG bool "log - Generation, control and access to logging" select LOG + select GETOPT help This provides access to logging features. It allows the output of log data to be controlled to a limited extent (setting up the default diff --git a/cmd/Makefile b/cmd/Makefile index 0cbee6c..dd86675 100644 --- a/cmd/Makefile +++ b/cmd/Makefile @@ -98,6 +98,7 @@ obj-$(CONFIG_CMD_MISC) += misc.o obj-$(CONFIG_CMD_MDIO) += mdio.o obj-$(CONFIG_CMD_SLEEP) += sleep.o obj-$(CONFIG_CMD_MMC) += mmc.o +obj-$(CONFIG_CMD_OPTEE_RPMB) += optee_rpmb.o obj-$(CONFIG_MP) += mp.o obj-$(CONFIG_CMD_MTD) += mtd.o obj-$(CONFIG_CMD_MTDPARTS) += mtdparts.o @@ -7,27 +7,298 @@ #include <common.h> #include <command.h> #include <dm.h> +#include <getopt.h> #include <log.h> +#include <malloc.h> static char log_fmt_chars[LOGF_COUNT] = "clFLfm"; +static enum log_level_t parse_log_level(char *const arg) +{ + enum log_level_t ret; + ulong level; + + if (!strict_strtoul(arg, 10, &level)) { + if (level > _LOG_MAX_LEVEL) { + printf("Only log levels <= %d are supported\n", + _LOG_MAX_LEVEL); + return LOGL_NONE; + } + return level; + } + + ret = log_get_level_by_name(arg); + if (ret == LOGL_NONE) + printf("Unknown log level \"%s\"\n", arg); + return ret; +} + static int do_log_level(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { + enum log_level_t log_level; + if (argc > 1) { - long log_level = simple_strtol(argv[1], NULL, 10); + log_level = parse_log_level(argv[1]); - if (log_level < 0 || log_level > _LOG_MAX_LEVEL) { - printf("Only log levels <= %d are supported\n", - _LOG_MAX_LEVEL); + if (log_level == LOGL_NONE) return CMD_RET_FAILURE; - } gd->default_log_level = log_level; } else { - printf("Default log level: %d\n", gd->default_log_level); + for (log_level = LOGL_FIRST; log_level <= _LOG_MAX_LEVEL; + log_level++) + printf("%s%s\n", log_get_level_name(log_level), + log_level == gd->default_log_level ? + " (default)" : ""); } - return 0; + return CMD_RET_SUCCESS; +} + +static int do_log_categories(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + enum log_category_t cat; + const char *name; + + for (cat = LOGC_FIRST; cat < LOGC_COUNT; cat++) { + name = log_get_cat_name(cat); + /* + * Invalid category names (e.g. <invalid> or <missing>) begin + * with '<'. + */ + if (name[0] == '<') + continue; + printf("%s\n", name); + } + + return CMD_RET_SUCCESS; +} + +static int do_log_drivers(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + struct log_device *ldev; + + list_for_each_entry(ldev, &gd->log_head, sibling_node) + printf("%s\n", ldev->drv->name); + + return CMD_RET_SUCCESS; +} + +static int do_log_filter_list(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + int opt; + const char *drv_name = "console"; + struct getopt_state gs; + struct log_filter *filt; + struct log_device *ldev; + + getopt_init_state(&gs); + while ((opt = getopt(&gs, argc, argv, "d:")) > 0) { + switch (opt) { + case 'd': + drv_name = gs.arg; + break; + default: + return CMD_RET_USAGE; + } + } + + if (gs.index != argc) + return CMD_RET_USAGE; + + ldev = log_device_find_by_name(drv_name); + if (!ldev) { + printf("Could not find log device for \"%s\"\n", drv_name); + return CMD_RET_FAILURE; + } + + /* <3> < 6 > <2+1 + 7 > < 16 > < unbounded... */ + printf("num policy level categories files\n"); + list_for_each_entry(filt, &ldev->filter_head, sibling_node) { + printf("%3d %6.6s %s %-7.7s ", filt->filter_num, + filt->flags & LOGFF_DENY ? "deny" : "allow", + filt->flags & LOGFF_LEVEL_MIN ? ">=" : "<=", + log_get_level_name(filt->level)); + + if (filt->flags & LOGFF_HAS_CAT) { + int i; + + if (filt->cat_list[0] != LOGC_END) + printf("%16.16s %s\n", + log_get_cat_name(filt->cat_list[0]), + filt->file_list ? filt->file_list : ""); + + for (i = 1; i < LOGF_MAX_CATEGORIES && + filt->cat_list[i] != LOGC_END; i++) + printf("%21c %16.16s\n", ' ', + log_get_cat_name(filt->cat_list[i])); + } else { + printf("%16c %s\n", ' ', + filt->file_list ? filt->file_list : ""); + } + } + + return CMD_RET_SUCCESS; +} + +static int do_log_filter_add(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + bool level_set = false; + bool print_num = false; + bool type_set = false; + char *file_list = NULL; + const char *drv_name = "console"; + int opt, err; + int cat_count = 0; + int flags = 0; + enum log_category_t cat_list[LOGF_MAX_CATEGORIES + 1]; + enum log_level_t level = LOGL_MAX; + struct getopt_state gs; + + getopt_init_state(&gs); + while ((opt = getopt(&gs, argc, argv, "Ac:d:Df:l:L:p")) > 0) { + switch (opt) { + case 'A': +#define do_type() do { \ + if (type_set) { \ + printf("Allow or deny set twice\n"); \ + return CMD_RET_USAGE; \ + } \ + type_set = true; \ +} while (0) + do_type(); + break; + case 'c': { + enum log_category_t cat; + + if (cat_count >= LOGF_MAX_CATEGORIES) { + printf("Too many categories\n"); + return CMD_RET_FAILURE; + } + + cat = log_get_cat_by_name(gs.arg); + if (cat == LOGC_NONE) { + printf("Unknown category \"%s\"\n", gs.arg); + return CMD_RET_FAILURE; + } + + cat_list[cat_count++] = cat; + break; + } + case 'd': + drv_name = gs.arg; + break; + case 'D': + do_type(); + flags |= LOGFF_DENY; + break; + case 'f': + file_list = gs.arg; + break; + case 'l': +#define do_level() do { \ + if (level_set) { \ + printf("Log level set twice\n"); \ + return CMD_RET_USAGE; \ + } \ + level = parse_log_level(gs.arg); \ + if (level == LOGL_NONE) \ + return CMD_RET_FAILURE; \ + level_set = true; \ +} while (0) + do_level(); + break; + case 'L': + do_level(); + flags |= LOGFF_LEVEL_MIN; + break; + case 'p': + print_num = true; + break; + default: + return CMD_RET_USAGE; + } + } + + if (gs.index != argc) + return CMD_RET_USAGE; + + cat_list[cat_count] = LOGC_END; + err = log_add_filter_flags(drv_name, cat_count ? cat_list : NULL, level, + file_list, flags); + if (err < 0) { + printf("Could not add filter (err = %d)\n", err); + return CMD_RET_FAILURE; + } else if (print_num) { + printf("%d\n", err); + } + + return CMD_RET_SUCCESS; +} + +static int do_log_filter_remove(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + bool all = false; + int opt, err; + ulong filter_num; + const char *drv_name = "console"; + struct getopt_state gs; + + getopt_init_state(&gs); + while ((opt = getopt(&gs, argc, argv, "ad:")) > 0) { + switch (opt) { + case 'a': + all = true; + break; + case 'd': + drv_name = gs.arg; + break; + default: + return CMD_RET_USAGE; + } + } + + if (all) { + struct log_filter *filt, *tmp_filt; + struct log_device *ldev; + + if (gs.index != argc) + return CMD_RET_USAGE; + + ldev = log_device_find_by_name(drv_name); + if (!ldev) { + printf("Could not find log device for \"%s\"\n", + drv_name); + return CMD_RET_FAILURE; + } + + list_for_each_entry_safe(filt, tmp_filt, &ldev->filter_head, + sibling_node) { + list_del(&filt->sibling_node); + free(filt); + } + } else { + if (gs.index + 1 != argc) + return CMD_RET_USAGE; + + if (strict_strtoul(argv[gs.index], 10, &filter_num)) { + printf("Invalid filter number \"%s\"\n", argv[gs.index]); + return CMD_RET_FAILURE; + } + + err = log_remove_filter(drv_name, filter_num); + if (err) { + printf("Could not remove filter (err = %d)\n", err); + return CMD_RET_FAILURE; + } + } + + return CMD_RET_SUCCESS; } static int do_log_format(struct cmd_tbl *cmdtp, int flag, int argc, @@ -103,39 +374,31 @@ static int do_log_rec(struct cmd_tbl *cmdtp, int flag, int argc, return 0; } -static struct cmd_tbl log_sub[] = { - U_BOOT_CMD_MKENT(level, CONFIG_SYS_MAXARGS, 1, do_log_level, "", ""), -#ifdef CONFIG_LOG_TEST - U_BOOT_CMD_MKENT(test, 2, 1, do_log_test, "", ""), -#endif - U_BOOT_CMD_MKENT(format, CONFIG_SYS_MAXARGS, 1, do_log_format, "", ""), - U_BOOT_CMD_MKENT(rec, CONFIG_SYS_MAXARGS, 1, do_log_rec, "", ""), -}; - -static int do_log(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) -{ - struct cmd_tbl *cp; - - if (argc < 2) - return CMD_RET_USAGE; - - /* drop initial "log" arg */ - argc--; - argv++; - - cp = find_cmd_tbl(argv[0], log_sub, ARRAY_SIZE(log_sub)); - if (cp) - return cp->cmd(cmdtp, flag, argc, argv); - - return CMD_RET_USAGE; -} - #ifdef CONFIG_SYS_LONGHELP static char log_help_text[] = - "level - get/set log level\n" -#ifdef CONFIG_LOG_TEST - "log test - run log tests\n" -#endif + "level [<level>] - get/set log level\n" + "categories - list log categories\n" + "drivers - list log drivers\n" + "log filter-list [OPTIONS] - list all filters for a log driver\n" + "\t-d <driver> - Specify the log driver to list filters from; defaults\n" + "\t to console\n" + "log filter-add [OPTIONS] - add a new filter to a driver\n" + "\t-A - Allow messages matching this filter; mutually exclusive with -D\n" + "\t This is the default.\n" + "\t-c <category> - Category to match; may be specified multiple times\n" + "\t-d <driver> - Specify the log driver to add the filter to; defaults\n" + "\t to console\n" + "\t-D - Deny messages matching this filter; mutually exclusive with -A\n" + "\t-f <files_list> - A comma-separated list of files to match\n" + "\t-l <level> - Match log levels less than or equal to <level>;\n" + "\t mutually-exclusive with -L\n" + "\t-L <level> - Match log levels greather than or equal to <level>;\n" + "\t mutually-exclusive with -l\n" + "\t-p - Print the filter number on success\n" + "log filter-remove [OPTIONS] [<num>] - Remove filter number <num>\n" + "\t-a - Remove ALL filters\n" + "\t-d <driver> - Specify the log driver to remove the filter from;\n" + "\t defaults to console\n" "log format <fmt> - set log output format. <fmt> is a string where\n" "\teach letter indicates something that should be displayed:\n" "\tc=category, l=level, F=file, L=line number, f=function, m=msg\n" @@ -145,7 +408,14 @@ static char log_help_text[] = ; #endif -U_BOOT_CMD( - log, CONFIG_SYS_MAXARGS, 1, do_log, - "log system", log_help_text +U_BOOT_CMD_WITH_SUBCMDS(log, "log system", log_help_text, + U_BOOT_SUBCMD_MKENT(level, 2, 1, do_log_level), + U_BOOT_SUBCMD_MKENT(categories, 1, 1, do_log_categories), + U_BOOT_SUBCMD_MKENT(drivers, 1, 1, do_log_drivers), + U_BOOT_SUBCMD_MKENT(filter-list, 3, 1, do_log_filter_list), + U_BOOT_SUBCMD_MKENT(filter-add, CONFIG_SYS_MAXARGS, 1, + do_log_filter_add), + U_BOOT_SUBCMD_MKENT(filter-remove, 4, 1, do_log_filter_remove), + U_BOOT_SUBCMD_MKENT(format, 2, 1, do_log_format), + U_BOOT_SUBCMD_MKENT(rec, 7, 1, do_log_rec), ); diff --git a/cmd/optee_rpmb.c b/cmd/optee_rpmb.c new file mode 100644 index 0000000..0d6b1cb --- /dev/null +++ b/cmd/optee_rpmb.c @@ -0,0 +1,272 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +#include <command.h> +#include <common.h> +#include <env.h> +#include <errno.h> +#include <image.h> +#include <malloc.h> +#include <mmc.h> +#include <tee.h> +#include <tee/optee_ta_avb.h> + +static struct udevice *tee; +static u32 session; + +static int avb_ta_open_session(void) +{ + const struct tee_optee_ta_uuid uuid = TA_AVB_UUID; + struct tee_open_session_arg arg; + int rc; + + tee = tee_find_device(tee, NULL, NULL, NULL); + if (!tee) + return -ENODEV; + + memset(&arg, 0, sizeof(arg)); + tee_optee_ta_uuid_to_octets(arg.uuid, &uuid); + rc = tee_open_session(tee, &arg, 0, NULL); + if (!rc) + session = arg.session; + + return 0; +} + +static int invoke_func(u32 func, ulong num_param, struct tee_param *param) +{ + struct tee_invoke_arg arg; + + if (!tee) + if (avb_ta_open_session()) + return -ENODEV; + + memset(&arg, 0, sizeof(arg)); + arg.func = func; + arg.session = session; + + if (tee_invoke_func(tee, &arg, num_param, param)) + return -EFAULT; + switch (arg.ret) { + case TEE_SUCCESS: + return 0; + case TEE_ERROR_OUT_OF_MEMORY: + case TEE_ERROR_STORAGE_NO_SPACE: + return -ENOSPC; + case TEE_ERROR_ITEM_NOT_FOUND: + return -EIO; + case TEE_ERROR_TARGET_DEAD: + /* + * The TA has paniced, close the session to reload the TA + * for the next request. + */ + tee_close_session(tee, session); + tee = NULL; + return -EIO; + default: + return -EIO; + } +} + +static int read_persistent_value(const char *name, + size_t buffer_size, + u8 *out_buffer, + size_t *out_num_bytes_read) +{ + int rc = 0; + struct tee_shm *shm_name; + struct tee_shm *shm_buf; + struct tee_param param[2]; + size_t name_size = strlen(name) + 1; + + if (!tee) + if (avb_ta_open_session()) + return -ENODEV; + + rc = tee_shm_alloc(tee, name_size, + TEE_SHM_ALLOC, &shm_name); + if (rc) + return -ENOMEM; + + rc = tee_shm_alloc(tee, buffer_size, + TEE_SHM_ALLOC, &shm_buf); + if (rc) { + rc = -ENOMEM; + goto free_name; + } + + memcpy(shm_name->addr, name, name_size); + + memset(param, 0, sizeof(param)); + param[0].attr = TEE_PARAM_ATTR_TYPE_MEMREF_INPUT; + param[0].u.memref.shm = shm_name; + param[0].u.memref.size = name_size; + param[1].attr = TEE_PARAM_ATTR_TYPE_MEMREF_INOUT; + param[1].u.memref.shm = shm_buf; + param[1].u.memref.size = buffer_size; + + rc = invoke_func(TA_AVB_CMD_READ_PERSIST_VALUE, + 2, param); + if (rc) + goto out; + + if (param[1].u.memref.size > buffer_size) { + rc = -EINVAL; + goto out; + } + + *out_num_bytes_read = param[1].u.memref.size; + + memcpy(out_buffer, shm_buf->addr, *out_num_bytes_read); + +out: + tee_shm_free(shm_buf); +free_name: + tee_shm_free(shm_name); + + return rc; +} + +static int write_persistent_value(const char *name, + size_t value_size, + const u8 *value) +{ + int rc = 0; + struct tee_shm *shm_name; + struct tee_shm *shm_buf; + struct tee_param param[2]; + size_t name_size = strlen(name) + 1; + + if (!tee) { + if (avb_ta_open_session()) + return -ENODEV; + } + if (!value_size) + return -EINVAL; + + rc = tee_shm_alloc(tee, name_size, + TEE_SHM_ALLOC, &shm_name); + if (rc) + return -ENOMEM; + + rc = tee_shm_alloc(tee, value_size, + TEE_SHM_ALLOC, &shm_buf); + if (rc) { + rc = -ENOMEM; + goto free_name; + } + + memcpy(shm_name->addr, name, name_size); + memcpy(shm_buf->addr, value, value_size); + + memset(param, 0, sizeof(param)); + param[0].attr = TEE_PARAM_ATTR_TYPE_MEMREF_INPUT; + param[0].u.memref.shm = shm_name; + param[0].u.memref.size = name_size; + param[1].attr = TEE_PARAM_ATTR_TYPE_MEMREF_INPUT; + param[1].u.memref.shm = shm_buf; + param[1].u.memref.size = value_size; + + rc = invoke_func(TA_AVB_CMD_WRITE_PERSIST_VALUE, + 2, param); + if (rc) + goto out; + +out: + tee_shm_free(shm_buf); +free_name: + tee_shm_free(shm_name); + + return rc; +} + +int do_optee_rpmb_read(struct cmd_tbl *cmdtp, int flag, int argc, + char * const argv[]) +{ + const char *name; + size_t bytes; + size_t bytes_read; + void *buffer; + char *endp; + + if (argc != 3) + return CMD_RET_USAGE; + + name = argv[1]; + bytes = simple_strtoul(argv[2], &endp, 10); + if (*endp && *endp != '\n') + return CMD_RET_USAGE; + + buffer = malloc(bytes); + if (!buffer) + return CMD_RET_FAILURE; + + if (read_persistent_value(name, bytes, buffer, &bytes_read) == 0) { + printf("Read %zu bytes, value = %s\n", bytes_read, + (char *)buffer); + free(buffer); + return CMD_RET_SUCCESS; + } + + printf("Failed to read persistent value\n"); + + free(buffer); + + return CMD_RET_FAILURE; +} + +int do_optee_rpmb_write(struct cmd_tbl *cmdtp, int flag, int argc, + char * const argv[]) +{ + const char *name; + const char *value; + + if (argc != 3) + return CMD_RET_USAGE; + + name = argv[1]; + value = argv[2]; + + if (write_persistent_value(name, strlen(value) + 1, + (const uint8_t *)value) == 0) { + printf("Wrote %zu bytes\n", strlen(value) + 1); + return CMD_RET_SUCCESS; + } + + printf("Failed to write persistent value\n"); + + return CMD_RET_FAILURE; +} + +static struct cmd_tbl cmd_optee_rpmb[] = { + U_BOOT_CMD_MKENT(read_pvalue, 3, 0, do_optee_rpmb_read, "", ""), + U_BOOT_CMD_MKENT(write_pvalue, 3, 0, do_optee_rpmb_write, "", ""), +}; + +static int do_optee_rpmb(struct cmd_tbl *cmdtp, int flag, int argc, + char * const argv[]) +{ + struct cmd_tbl *cp; + + cp = find_cmd_tbl(argv[1], cmd_optee_rpmb, ARRAY_SIZE(cmd_optee_rpmb)); + + argc--; + argv++; + + if (!cp || argc > cp->maxargs) + return CMD_RET_USAGE; + + if (flag == CMD_FLAG_REPEAT) + return CMD_RET_FAILURE; + + return cp->cmd(cmdtp, flag, argc, argv); +} + +U_BOOT_CMD ( + optee_rpmb, 29, 0, do_optee_rpmb, + "Provides commands for testing secure storage on RPMB on OPTEE", + "read_pvalue <name> <bytes> - read a persistent value <name>\n" + "optee_rpmb write_pvalue <name> <value> - write a persistent value <name>\n" + ); diff --git a/common/Kconfig b/common/Kconfig index 318d372..2bce8c9 100644 --- a/common/Kconfig +++ b/common/Kconfig @@ -599,9 +599,15 @@ endmenu menu "Update support" +config UPDATE_COMMON + bool + default n + select DFU_WRITE_ALT + config UPDATE_TFTP bool "Auto-update using fitImage via TFTP" depends on FIT + select UPDATE_COMMON help This option allows performing update of NOR with data in fitImage sent via TFTP boot. @@ -616,6 +622,15 @@ config UPDATE_TFTP_MSEC_MAX default 100 depends on UPDATE_TFTP +config UPDATE_FIT + bool "Firmware update using fitImage" + depends on FIT + depends on DFU + select UPDATE_COMMON + help + This option allows performing update of DFU-capable storage with + data in fitImage. + config ANDROID_AB bool "Android A/B updates" default n diff --git a/common/Makefile b/common/Makefile index 2e7a090..bcf352d 100644 --- a/common/Makefile +++ b/common/Makefile @@ -53,8 +53,7 @@ obj-$(CONFIG_LCD_ROTATION) += lcd_console_rotation.o obj-$(CONFIG_LCD_DT_SIMPLEFB) += lcd_simplefb.o obj-$(CONFIG_LYNXKDI) += lynxkdi.o obj-$(CONFIG_MENU) += menu.o -obj-$(CONFIG_UPDATE_TFTP) += update.o -obj-$(CONFIG_DFU_TFTP) += update.o +obj-$(CONFIG_UPDATE_COMMON) += update.o obj-$(CONFIG_USB_KEYBOARD) += usb_kbd.o obj-$(CONFIG_CMDLINE) += cli_readline.o cli_simple.o diff --git a/common/board_r.c b/common/board_r.c index b9217b2..29dd7d2 100644 --- a/common/board_r.c +++ b/common/board_r.c @@ -73,6 +73,9 @@ #if defined(CONFIG_GPIO_HOG) #include <asm/gpio.h> #endif +#ifdef CONFIG_EFI_SETUP_EARLY +#include <efi_loader.h> +#endif DECLARE_GLOBAL_DATA_PTR; @@ -296,20 +299,21 @@ static int initr_noncached(void) } #endif -#ifdef CONFIG_OF_LIVE static int initr_of_live(void) { - int ret; + if (CONFIG_IS_ENABLED(OF_LIVE)) { + int ret; - bootstage_start(BOOTSTAGE_ID_ACCUM_OF_LIVE, "of_live"); - ret = of_live_build(gd->fdt_blob, (struct device_node **)&gd->of_root); - bootstage_accum(BOOTSTAGE_ID_ACCUM_OF_LIVE); - if (ret) - return ret; + bootstage_start(BOOTSTAGE_ID_ACCUM_OF_LIVE, "of_live"); + ret = of_live_build(gd->fdt_blob, + (struct device_node **)gd_of_root_ptr()); + bootstage_accum(BOOTSTAGE_ID_ACCUM_OF_LIVE); + if (ret) + return ret; + } return 0; } -#endif #ifdef CONFIG_DM static int initr_dm(void) @@ -713,9 +717,7 @@ static init_fnc_t init_sequence_r[] = { #ifdef CONFIG_SYS_NONCACHED_MEMORY initr_noncached, #endif -#ifdef CONFIG_OF_LIVE initr_of_live, -#endif #ifdef CONFIG_DM initr_dm, #endif @@ -890,6 +892,9 @@ static init_fnc_t init_sequence_r[] = { #if defined(CONFIG_PRAM) initr_mem, #endif +#ifdef CONFIG_EFI_SETUP_EARLY + (init_fnc_t)efi_init_obj_list, +#endif run_main_loop, }; diff --git a/common/fdt_support.c b/common/fdt_support.c index a565b47..5ae75df 100644 --- a/common/fdt_support.c +++ b/common/fdt_support.c @@ -611,14 +611,9 @@ int fdt_record_loadable(void *blob, u32 index, const char *name, if (node < 0) return node; - /* - * We record these as 32bit entities, possibly truncating addresses. - * However, spl_fit.c is not 64bit safe either: i.e. we should not - * have an issue here. - */ - fdt_setprop_u32(blob, node, "load-addr", load_addr); + fdt_setprop_u64(blob, node, "load", load_addr); if (entry_point != -1) - fdt_setprop_u32(blob, node, "entry-point", entry_point); + fdt_setprop_u64(blob, node, "entry", entry_point); fdt_setprop_u32(blob, node, "size", size); if (type) fdt_setprop_string(blob, node, "type", type); diff --git a/common/image-fit.c b/common/image-fit.c index d54eff9..c82d4d8 100644 --- a/common/image-fit.c +++ b/common/image-fit.c @@ -791,17 +791,18 @@ static int fit_image_get_address(const void *fit, int noffset, char *name, return -1; } - if (len > sizeof(ulong)) { - printf("Unsupported %s address size\n", name); - return -1; - } - cell_len = len >> 2; /* Use load64 to avoid compiling warning for 32-bit target */ while (cell_len--) { load64 = (load64 << 32) | uimage_to_cpu(*cell); cell++; } + + if (len > sizeof(ulong) && (uint32_t)(load64 >> 32)) { + printf("Unsupported %s address size\n", name); + return -1; + } + *load = (ulong)load64; return 0; diff --git a/common/log.c b/common/log.c index 9f98e9a..4b6f3fc 100644 --- a/common/log.c +++ b/common/log.c @@ -13,7 +13,7 @@ DECLARE_GLOBAL_DATA_PTR; -static const char *log_cat_name[] = { +static const char *const log_cat_name[] = { "none", "arch", "board", @@ -31,7 +31,7 @@ static const char *log_cat_name[] = { _Static_assert(ARRAY_SIZE(log_cat_name) == LOGC_COUNT - LOGC_NONE, "log_cat_name size"); -static const char *log_level_name[] = { +static const char *const log_level_name[] = { "EMERG", "ALERT", "CRIT", @@ -99,7 +99,7 @@ enum log_level_t log_get_level_by_name(const char *name) return LOGL_NONE; } -static struct log_device *log_device_find_by_name(const char *drv_name) +struct log_device *log_device_find_by_name(const char *drv_name) { struct log_device *ldev; @@ -111,15 +111,7 @@ static struct log_device *log_device_find_by_name(const char *drv_name) return NULL; } -/** - * log_has_cat() - check if a log category exists within a list - * - * @cat_list: List of categories to check, at most LOGF_MAX_CATEGORIES entries - * long, terminated by LC_END if fewer - * @cat: Category to search for - * @return true if @cat is in @cat_list, else false - */ -static bool log_has_cat(enum log_category_t cat_list[], enum log_category_t cat) +bool log_has_cat(enum log_category_t cat_list[], enum log_category_t cat) { int i; @@ -131,16 +123,7 @@ static bool log_has_cat(enum log_category_t cat_list[], enum log_category_t cat) return false; } -/** - * log_has_file() - check if a file is with a list - * - * @file_list: List of files to check, separated by comma - * @file: File to check for. This string is matched against the end of each - * file in the list, i.e. ignoring any preceding path. The list is - * intended to consist of relative pathnames, e.g. common/main.c,cmd/log.c - * @return true if @file is in @file_list, else false - */ -static bool log_has_file(const char *file_list, const char *file) +bool log_has_file(const char *file_list, const char *file) { int file_len = strlen(file); const char *s, *p; @@ -179,15 +162,25 @@ static bool log_passes_filters(struct log_device *ldev, struct log_rec *rec) } list_for_each_entry(filt, &ldev->filter_head, sibling_node) { - if (rec->level > filt->max_level) + if (filt->flags & LOGFF_LEVEL_MIN) { + if (rec->level < filt->level) + continue; + } else if (rec->level > filt->level) { continue; + } + if ((filt->flags & LOGFF_HAS_CAT) && !log_has_cat(filt->cat_list, rec->cat)) continue; + if (filt->file_list && !log_has_file(filt->file_list, rec->file)) continue; - return true; + + if (filt->flags & LOGFF_DENY) + return false; + else + return true; } return false; @@ -263,8 +256,9 @@ int _log(enum log_category_t cat, enum log_level_t level, const char *file, return 0; } -int log_add_filter(const char *drv_name, enum log_category_t cat_list[], - enum log_level_t max_level, const char *file_list) +int log_add_filter_flags(const char *drv_name, enum log_category_t cat_list[], + enum log_level_t level, const char *file_list, + int flags) { struct log_filter *filt; struct log_device *ldev; @@ -278,6 +272,7 @@ int log_add_filter(const char *drv_name, enum log_category_t cat_list[], if (!filt) return -ENOMEM; + filt->flags = flags; if (cat_list) { filt->flags |= LOGFF_HAS_CAT; for (i = 0; ; i++) { @@ -290,16 +285,20 @@ int log_add_filter(const char *drv_name, enum log_category_t cat_list[], break; } } - filt->max_level = max_level; + filt->level = level; if (file_list) { filt->file_list = strdup(file_list); if (!filt->file_list) { - ret = ENOMEM; + ret = -ENOMEM; goto err; } } filt->filter_num = ldev->next_filter_num++; - list_add_tail(&filt->sibling_node, &ldev->filter_head); + /* Add deny filters to the beginning of the list */ + if (flags & LOGFF_DENY) + list_add(&filt->sibling_node, &ldev->filter_head); + else + list_add_tail(&filt->sibling_node, &ldev->filter_head); return filt->filter_num; diff --git a/common/spl/spl_atf.c b/common/spl/spl_atf.c index b54b4f0..9bd25f6 100644 --- a/common/spl/spl_atf.c +++ b/common/spl/spl_atf.c @@ -132,10 +132,11 @@ static int spl_fit_images_find(void *blob, int os) uintptr_t spl_fit_images_get_entry(void *blob, int node) { ulong val; + int ret; - val = fdt_getprop_u32(blob, node, "entry-point"); - if (val == FDT_ERROR) - val = fdt_getprop_u32(blob, node, "load-addr"); + ret = fit_image_get_entry(blob, node, &val); + if (ret) + ret = fit_image_get_load(blob, node, &val); debug("%s: entry point 0x%lx\n", __func__, val); return val; diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c index fd6086a..f5109e8 100644 --- a/common/spl/spl_fit.c +++ b/common/spl/spl_fit.c @@ -332,9 +332,15 @@ static int spl_load_fit_image(struct spl_load_info *info, ulong sector, } if (image_info) { + ulong entry_point; + image_info->load_addr = load_addr; image_info->size = length; - image_info->entry_point = fdt_getprop_u32(fit, node, "entry"); + + if (!fit_image_get_entry(fit, node, &entry_point)) + image_info->entry_point = entry_point; + else + image_info->entry_point = FDT_ERROR; } return 0; diff --git a/common/spl/spl_opensbi.c b/common/spl/spl_opensbi.c index 14f335f..41e0746 100644 --- a/common/spl/spl_opensbi.c +++ b/common/spl/spl_opensbi.c @@ -61,11 +61,9 @@ void spl_invoke_opensbi(struct spl_image_info *spl_image) } /* Get U-Boot entry point */ - uboot_entry = fdt_getprop_u32(spl_image->fdt_addr, uboot_node, - "entry-point"); - if (uboot_entry == FDT_ERROR) - uboot_entry = fdt_getprop_u32(spl_image->fdt_addr, uboot_node, - "load-addr"); + ret = fit_image_get_entry(spl_image->fdt_addr, uboot_node, &uboot_entry); + if (ret) + ret = fit_image_get_load(spl_image->fdt_addr, uboot_node, &uboot_entry); /* Prepare obensbi_info object */ opensbi_info.magic = FW_DYNAMIC_INFO_MAGIC_VALUE; diff --git a/common/update.c b/common/update.c index 36b6b75..808be08 100644 --- a/common/update.c +++ b/common/update.c @@ -29,6 +29,7 @@ #include <errno.h> #include <mtd/cfi_flash.h> +#ifdef CONFIG_DFU_TFTP /* env variable holding the location of the update file */ #define UPDATE_FILE_ENV "updatefile" @@ -98,6 +99,7 @@ static int update_load(char *filename, ulong msec_max, int cnt_max, ulong addr) return rv; } +#endif /* CONFIG_DFU_TFTP */ #ifdef CONFIG_MTD_NOR_FLASH static int update_flash_protect(int prot, ulong addr_first, ulong addr_last) @@ -231,6 +233,7 @@ static int update_fit_getparams(const void *fit, int noffset, ulong *addr, return 0; } +#ifdef CONFIG_DFU_TFTP int update_tftp(ulong addr, char *interface, char *devstring) { char *filename, *env_addr, *fit_image_name; @@ -324,8 +327,10 @@ got_update_file: } } else if (fit_image_check_type(fit, noffset, IH_TYPE_FIRMWARE)) { - ret = dfu_tftp_write(fit_image_name, update_addr, - update_size, interface, devstring); + ret = dfu_write_by_name(fit_image_name, + (void *)update_addr, + update_size, interface, + devstring); if (ret) return ret; } @@ -335,3 +340,71 @@ next_node: return ret; } +#endif /* CONFIG_DFU_UPDATE */ + +#ifdef CONFIG_UPDATE_FIT +/** + * fit_update - update storage with FIT image + * @fit: Pointer to FIT image + * + * Update firmware on storage using FIT image as input. + * The storage area to be update will be identified by the name + * in FIT and matching it to "dfu_alt_info" variable. + * + * Return: 0 - on success, non-zero - otherwise + */ +int fit_update(const void *fit) +{ + char *fit_image_name; + ulong update_addr, update_fladdr, update_size; + int images_noffset, ndepth, noffset; + int ret = 0; + + if (!fit) + return -EINVAL; + + if (!fit_check_format((void *)fit)) { + printf("Bad FIT format of the update file, aborting auto-update\n"); + return -EINVAL; + } + + /* process updates */ + images_noffset = fdt_path_offset(fit, FIT_IMAGES_PATH); + + ndepth = 0; + noffset = fdt_next_node(fit, images_noffset, &ndepth); + while (noffset >= 0 && ndepth > 0) { + if (ndepth != 1) + goto next_node; + + fit_image_name = (char *)fit_get_name(fit, noffset, NULL); + printf("Processing update '%s' :", fit_image_name); + + if (!fit_image_verify(fit, noffset)) { + printf("Error: invalid update hash, aborting\n"); + ret = 1; + goto next_node; + } + + printf("\n"); + if (update_fit_getparams(fit, noffset, &update_addr, + &update_fladdr, &update_size)) { + printf("Error: can't get update parameters, aborting\n"); + ret = 1; + goto next_node; + } + + if (fit_image_check_type(fit, noffset, IH_TYPE_FIRMWARE)) { + ret = dfu_write_by_name(fit_image_name, + (void *)update_addr, + update_size, NULL, NULL); + if (ret) + return ret; + } +next_node: + noffset = fdt_next_node(fit, noffset, &ndepth); + } + + return ret; +} +#endif /* CONFIG_UPDATE_FIT */ diff --git a/configs/aristainetos2_defconfig b/configs/aristainetos2_defconfig index 81863f6..35e4b09 100644 --- a/configs/aristainetos2_defconfig +++ b/configs/aristainetos2_defconfig @@ -58,6 +58,7 @@ CONFIG_DTB_RESELECT=y CONFIG_MULTI_DTB_FIT=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_ENV_SPI_EARLY=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_VERSION_VARIABLE=y diff --git a/configs/aristainetos2b_defconfig b/configs/aristainetos2b_defconfig index 2e59c30..d47a074 100644 --- a/configs/aristainetos2b_defconfig +++ b/configs/aristainetos2b_defconfig @@ -56,6 +56,7 @@ CONFIG_DTB_RESELECT=y CONFIG_MULTI_DTB_FIT=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_ENV_SPI_EARLY=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_VERSION_VARIABLE=y diff --git a/configs/aristainetos2bcsl_defconfig b/configs/aristainetos2bcsl_defconfig index 8e6d299..3013962 100644 --- a/configs/aristainetos2bcsl_defconfig +++ b/configs/aristainetos2bcsl_defconfig @@ -56,6 +56,7 @@ CONFIG_DTB_RESELECT=y CONFIG_MULTI_DTB_FIT=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_ENV_SPI_EARLY=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_VERSION_VARIABLE=y diff --git a/configs/aristainetos2c_defconfig b/configs/aristainetos2c_defconfig index 372d705..50cadb7 100644 --- a/configs/aristainetos2c_defconfig +++ b/configs/aristainetos2c_defconfig @@ -56,6 +56,7 @@ CONFIG_DTB_RESELECT=y CONFIG_MULTI_DTB_FIT=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_ENV_SPI_EARLY=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_VERSION_VARIABLE=y diff --git a/configs/at91sam9261ek_dataflash_cs0_defconfig b/configs/at91sam9261ek_dataflash_cs0_defconfig index 9d4e5b5..e19b97b 100644 --- a/configs/at91sam9261ek_dataflash_cs0_defconfig +++ b/configs/at91sam9261ek_dataflash_cs0_defconfig @@ -17,7 +17,6 @@ CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9261,SYS_USE_DATAFLASH_CS0" CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/mtdblock0 mtdparts=atmel_nand:-(root) rw rootfstype=jffs2" -# CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SYS_PROMPT="U-Boot> " @@ -59,4 +58,3 @@ CONFIG_TIMER=y CONFIG_ATMEL_PIT_TIMER=y CONFIG_USB=y CONFIG_USB_STORAGE=y -# CONFIG_LCD is not set diff --git a/configs/at91sam9261ek_dataflash_cs3_defconfig b/configs/at91sam9261ek_dataflash_cs3_defconfig index 3a0bb10..0ea3d0d 100644 --- a/configs/at91sam9261ek_dataflash_cs3_defconfig +++ b/configs/at91sam9261ek_dataflash_cs3_defconfig @@ -17,7 +17,6 @@ CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9261,SYS_USE_DATAFLASH_CS3" CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/mtdblock0 mtdparts=atmel_nand:-(root) rw rootfstype=jffs2" -# CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SYS_PROMPT="U-Boot> " @@ -59,4 +58,3 @@ CONFIG_TIMER=y CONFIG_ATMEL_PIT_TIMER=y CONFIG_USB=y CONFIG_USB_STORAGE=y -# CONFIG_LCD is not set diff --git a/configs/at91sam9261ek_nandflash_defconfig b/configs/at91sam9261ek_nandflash_defconfig index abdf223..48a8f35 100644 --- a/configs/at91sam9261ek_nandflash_defconfig +++ b/configs/at91sam9261ek_nandflash_defconfig @@ -15,7 +15,6 @@ CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9261,SYS_USE_NANDFLASH" CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro,256k(env),256k(env_redundant),256k(spare),512k(dtb),6M(kernel)ro,-(rootfs) root=/dev/mtdblock7 rw rootfstype=jffs2" -# CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SYS_PROMPT="U-Boot> " @@ -56,4 +55,3 @@ CONFIG_TIMER=y CONFIG_ATMEL_PIT_TIMER=y CONFIG_USB=y CONFIG_USB_STORAGE=y -# CONFIG_LCD is not set diff --git a/configs/at91sam9263ek_dataflash_cs0_defconfig b/configs/at91sam9263ek_dataflash_cs0_defconfig index 564b781..2e0e808 100644 --- a/configs/at91sam9263ek_dataflash_cs0_defconfig +++ b/configs/at91sam9263ek_dataflash_cs0_defconfig @@ -18,7 +18,6 @@ CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_DATAFLASH" CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/mtdblock0 mtdparts=atmel_nand:-(root) rw rootfstype=jffs2" -# CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y @@ -67,4 +66,3 @@ CONFIG_ATMEL_PIT_TIMER=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_STORAGE=y -# CONFIG_LCD is not set diff --git a/configs/at91sam9263ek_dataflash_defconfig b/configs/at91sam9263ek_dataflash_defconfig index 564b781..2e0e808 100644 --- a/configs/at91sam9263ek_dataflash_defconfig +++ b/configs/at91sam9263ek_dataflash_defconfig @@ -18,7 +18,6 @@ CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_DATAFLASH" CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/mtdblock0 mtdparts=atmel_nand:-(root) rw rootfstype=jffs2" -# CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y @@ -67,4 +66,3 @@ CONFIG_ATMEL_PIT_TIMER=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_STORAGE=y -# CONFIG_LCD is not set diff --git a/configs/at91sam9263ek_nandflash_defconfig b/configs/at91sam9263ek_nandflash_defconfig index 32b2fff..aad5e13 100644 --- a/configs/at91sam9263ek_nandflash_defconfig +++ b/configs/at91sam9263ek_nandflash_defconfig @@ -16,7 +16,6 @@ CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_NANDFLASH" CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro,256k(env),256k(env_redundant),256k(spare),512k(dtb),6M(kernel)ro,-(rootfs) root=/dev/mtdblock7 rw rootfstype=jffs2" -# CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y @@ -64,4 +63,3 @@ CONFIG_ATMEL_PIT_TIMER=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_STORAGE=y -# CONFIG_LCD is not set diff --git a/configs/at91sam9263ek_norflash_boot_defconfig b/configs/at91sam9263ek_norflash_boot_defconfig index 2955b05..f1d3575 100644 --- a/configs/at91sam9263ek_norflash_boot_defconfig +++ b/configs/at91sam9263ek_norflash_boot_defconfig @@ -15,7 +15,6 @@ CONFIG_DEFAULT_DEVICE_TREE="at91sam9263ek" CONFIG_DEBUG_UART=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_BOOT_NORFLASH" CONFIG_BOOTDELAY=3 -# CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y @@ -67,4 +66,3 @@ CONFIG_ATMEL_PIT_TIMER=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_STORAGE=y -# CONFIG_LCD is not set diff --git a/configs/at91sam9263ek_norflash_defconfig b/configs/at91sam9263ek_norflash_defconfig index 56355f6..04302f8 100644 --- a/configs/at91sam9263ek_norflash_defconfig +++ b/configs/at91sam9263ek_norflash_defconfig @@ -15,7 +15,6 @@ CONFIG_DEFAULT_DEVICE_TREE="at91sam9263ek" CONFIG_DEBUG_UART=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_NORFLASH" CONFIG_BOOTDELAY=3 -# CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y @@ -67,4 +66,3 @@ CONFIG_ATMEL_PIT_TIMER=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_STORAGE=y -# CONFIG_LCD is not set diff --git a/configs/at91sam9g10ek_dataflash_cs0_defconfig b/configs/at91sam9g10ek_dataflash_cs0_defconfig index a5a493d..2b3469b 100644 --- a/configs/at91sam9g10ek_dataflash_cs0_defconfig +++ b/configs/at91sam9g10ek_dataflash_cs0_defconfig @@ -17,7 +17,6 @@ CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G10,SYS_USE_DATAFLASH_CS0" CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/mtdblock0 mtdparts=atmel_nand:-(root) rw rootfstype=jffs2" -# CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SYS_PROMPT="U-Boot> " @@ -57,4 +56,3 @@ CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -# CONFIG_LCD is not set diff --git a/configs/at91sam9g10ek_dataflash_cs3_defconfig b/configs/at91sam9g10ek_dataflash_cs3_defconfig index 85c4c50..8f5fdd2 100644 --- a/configs/at91sam9g10ek_dataflash_cs3_defconfig +++ b/configs/at91sam9g10ek_dataflash_cs3_defconfig @@ -17,7 +17,6 @@ CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G10,SYS_USE_DATAFLASH_CS3" CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/mtdblock0 mtdparts=atmel_nand:-(root) rw rootfstype=jffs2" -# CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SYS_PROMPT="U-Boot> " @@ -57,4 +56,3 @@ CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -# CONFIG_LCD is not set diff --git a/configs/at91sam9g10ek_nandflash_defconfig b/configs/at91sam9g10ek_nandflash_defconfig index 609b9eb..5bc3cb3 100644 --- a/configs/at91sam9g10ek_nandflash_defconfig +++ b/configs/at91sam9g10ek_nandflash_defconfig @@ -15,7 +15,6 @@ CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G10,SYS_USE_NANDFLASH" CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro,256k(env),256k(env_redundant),256k(spare),512k(dtb),6M(kernel)ro,-(rootfs) root=/dev/mtdblock7 rw rootfstype=jffs2" -# CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SYS_PROMPT="U-Boot> " @@ -54,4 +53,3 @@ CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -# CONFIG_LCD is not set diff --git a/configs/at91sam9m10g45ek_mmc_defconfig b/configs/at91sam9m10g45ek_mmc_defconfig index 2885e12..dd77c8d 100644 --- a/configs/at91sam9m10g45ek_mmc_defconfig +++ b/configs/at91sam9m10g45ek_mmc_defconfig @@ -15,7 +15,6 @@ CONFIG_SD_BOOT=y CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 mtdparts=atmel_nand:8M(bootstrap/uboot/kernel)ro,-(rootfs) root=/dev/mmcblk0p2 rw rootwait" -# CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y @@ -58,4 +57,3 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y -# CONFIG_LCD is not set diff --git a/configs/at91sam9m10g45ek_nandflash_defconfig b/configs/at91sam9m10g45ek_nandflash_defconfig index f89bf1e..e13851d 100644 --- a/configs/at91sam9m10g45ek_nandflash_defconfig +++ b/configs/at91sam9m10g45ek_nandflash_defconfig @@ -15,7 +15,6 @@ CONFIG_NAND_BOOT=y CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro,256k(env),256k(env_redundant),256k(spare),512k(dtb),6M(kernel)ro,-(rootfs) root=/dev/mtdblock7 rw rootfstype=jffs2" -# CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y @@ -58,4 +57,3 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y -# CONFIG_LCD is not set diff --git a/configs/at91sam9n12ek_mmc_defconfig b/configs/at91sam9n12ek_mmc_defconfig index 15a4335..fa802c3 100644 --- a/configs/at91sam9n12ek_mmc_defconfig +++ b/configs/at91sam9n12ek_mmc_defconfig @@ -13,7 +13,6 @@ CONFIG_DEFAULT_DEVICE_TREE="at91sam9n12ek" CONFIG_DEBUG_UART=y CONFIG_SD_BOOT=y CONFIG_BOOTDELAY=3 -# CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y @@ -62,4 +61,3 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_STORAGE=y CONFIG_ATMEL_HLCD=y -# CONFIG_LCD is not set diff --git a/configs/at91sam9n12ek_nandflash_defconfig b/configs/at91sam9n12ek_nandflash_defconfig index 5f3c256..429b140 100644 --- a/configs/at91sam9n12ek_nandflash_defconfig +++ b/configs/at91sam9n12ek_nandflash_defconfig @@ -13,7 +13,6 @@ CONFIG_DEFAULT_DEVICE_TREE="at91sam9n12ek" CONFIG_DEBUG_UART=y CONFIG_NAND_BOOT=y CONFIG_BOOTDELAY=3 -# CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y @@ -63,4 +62,3 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_STORAGE=y CONFIG_ATMEL_HLCD=y -# CONFIG_LCD is not set diff --git a/configs/at91sam9n12ek_spiflash_defconfig b/configs/at91sam9n12ek_spiflash_defconfig index 65c8926..9975947 100644 --- a/configs/at91sam9n12ek_spiflash_defconfig +++ b/configs/at91sam9n12ek_spiflash_defconfig @@ -15,7 +15,6 @@ CONFIG_DEFAULT_DEVICE_TREE="at91sam9n12ek" CONFIG_DEBUG_UART=y CONFIG_SPI_BOOT=y CONFIG_BOOTDELAY=3 -# CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y @@ -64,4 +63,3 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_STORAGE=y CONFIG_ATMEL_HLCD=y -# CONFIG_LCD is not set diff --git a/configs/at91sam9rlek_dataflash_defconfig b/configs/at91sam9rlek_dataflash_defconfig index f037a8d..ea14df9 100644 --- a/configs/at91sam9rlek_dataflash_defconfig +++ b/configs/at91sam9rlek_dataflash_defconfig @@ -18,7 +18,6 @@ CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9RL,SYS_USE_DATAFLASH" CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/mtdblock0 mtdparts=atmel_nand:-(root) rw rootfstype=jffs2" -# CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y @@ -60,4 +59,3 @@ CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_TIMER=y CONFIG_ATMEL_PIT_TIMER=y -# CONFIG_LCD is not set diff --git a/configs/at91sam9rlek_mmc_defconfig b/configs/at91sam9rlek_mmc_defconfig index 3477350..5e62ff3 100644 --- a/configs/at91sam9rlek_mmc_defconfig +++ b/configs/at91sam9rlek_mmc_defconfig @@ -16,7 +16,6 @@ CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9RL,SYS_USE_MMC" CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 mtdparts=atmel_nand:8M(bootstrap/uboot/kernel)ro,-(rootfs) root=/dev/mmcblk0p2 rw rootwait" -# CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y @@ -56,4 +55,3 @@ CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_TIMER=y CONFIG_ATMEL_PIT_TIMER=y -# CONFIG_LCD is not set diff --git a/configs/at91sam9rlek_nandflash_defconfig b/configs/at91sam9rlek_nandflash_defconfig index ad8fcdf..ff32bf5 100644 --- a/configs/at91sam9rlek_nandflash_defconfig +++ b/configs/at91sam9rlek_nandflash_defconfig @@ -16,7 +16,6 @@ CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9RL,SYS_USE_NANDFLASH" CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro,256K(env),256k(env_redundant),256k(spare),512k(dtb),6M(kernel)ro,-(rootfs) rootfstype=ubifs ubi.mtd=7 root=ubi0:rootfs" -# CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y @@ -57,4 +56,3 @@ CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_TIMER=y CONFIG_ATMEL_PIT_TIMER=y -# CONFIG_LCD is not set diff --git a/configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig b/configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig index 25282ba..2426179 100644 --- a/configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig +++ b/configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig @@ -8,6 +8,8 @@ CONFIG_DEBUG_UART_BASE=0xff000000 CONFIG_DEBUG_UART_CLOCK=100000000 CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y +CONFIG_ZYNQ_MAC_IN_EEPROM=y +CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0xfa CONFIG_DEFAULT_DEVICE_TREE="avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0" CONFIG_DEBUG_UART=y CONFIG_DISTRO_DEFAULTS=y @@ -42,7 +44,6 @@ CONFIG_I2C_MUX=y CONFIG_I2C_MUX_PCA954x=y CONFIG_MISC=y CONFIG_I2C_EEPROM=y -CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0xfa CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y CONFIG_SPI_FLASH_BAR=y diff --git a/configs/dms-ba16-1g_defconfig b/configs/dms-ba16-1g_defconfig index eb5ee09..f7b6bc6 100644 --- a/configs/dms-ba16-1g_defconfig +++ b/configs/dms-ba16-1g_defconfig @@ -63,5 +63,4 @@ CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_SPLASH_SCREEN=y CONFIG_SPLASH_SCREEN_ALIGN=y -CONFIG_VIDEO_BMP_RLE8=y CONFIG_OF_LIBFDT=y diff --git a/configs/dms-ba16_defconfig b/configs/dms-ba16_defconfig index fe6d6a5..c708087 100644 --- a/configs/dms-ba16_defconfig +++ b/configs/dms-ba16_defconfig @@ -62,5 +62,4 @@ CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_SPLASH_SCREEN=y CONFIG_SPLASH_SCREEN_ALIGN=y -CONFIG_VIDEO_BMP_RLE8=y CONFIG_OF_LIBFDT=y diff --git a/configs/eb_cpu5282_defconfig b/configs/eb_cpu5282_defconfig index 1f89342..3673010 100644 --- a/configs/eb_cpu5282_defconfig +++ b/configs/eb_cpu5282_defconfig @@ -6,7 +6,6 @@ CONFIG_TARGET_EB_CPU5282=y CONFIG_DEFAULT_DEVICE_TREE="eb_cpu5282" CONFIG_SYS_EXTRA_OPTIONS="SYS_MONITOR_BASE=0xFF000400" CONFIG_BOOTDELAY=5 -# CONFIG_CONSOLE_MUX is not set # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_MISC_INIT_R=y # CONFIG_AUTO_COMPLETE is not set @@ -32,5 +31,5 @@ CONFIG_SYS_FLASH_CFI=y CONFIG_DM_ETH=y CONFIG_MCFFEC=y CONFIG_MII=y -CONFIG_VIDEO_VCXK=y CONFIG_SPLASH_SCREEN=y +CONFIG_VIDEO_VCXK=y diff --git a/configs/eb_cpu5282_internal_defconfig b/configs/eb_cpu5282_internal_defconfig index ad7b7d5..ec38b09 100644 --- a/configs/eb_cpu5282_internal_defconfig +++ b/configs/eb_cpu5282_internal_defconfig @@ -6,7 +6,6 @@ CONFIG_TARGET_EB_CPU5282=y CONFIG_DEFAULT_DEVICE_TREE="eb_cpu5282_internal" CONFIG_SYS_EXTRA_OPTIONS="SYS_MONITOR_BASE=0xF0000418" CONFIG_BOOTDELAY=5 -# CONFIG_CONSOLE_MUX is not set # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_MISC_INIT_R=y # CONFIG_AUTO_COMPLETE is not set @@ -31,5 +30,5 @@ CONFIG_SYS_FLASH_CFI=y CONFIG_DM_ETH=y CONFIG_MCFFEC=y CONFIG_MII=y -CONFIG_VIDEO_VCXK=y CONFIG_SPLASH_SCREEN=y +CONFIG_VIDEO_VCXK=y diff --git a/configs/kontron_sl28_defconfig b/configs/kontron_sl28_defconfig new file mode 100644 index 0000000..c1a0967 --- /dev/null +++ b/configs/kontron_sl28_defconfig @@ -0,0 +1,107 @@ +CONFIG_ARM=y +CONFIG_TARGET_SL28=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x4000 +CONFIG_NR_DRAM_BANKS=2 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0x3e0000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_SYS_SPI_U_BOOT_OFFS=0x230000 +CONFIG_DM_GPIO=y +CONFIG_SPL_DM_SPI=y +CONFIG_SPL_TEXT_BASE=0x18010000 +CONFIG_SYS_FSL_SDHC_CLK_DIV=1 +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SIZE_LIMIT=0x20000 +CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x0 +CONFIG_SPL=y +CONFIG_ENV_OFFSET_REDUND=0x3f0000 +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI_SUPPORT=y +# CONFIG_PSCI_RESET is not set +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1028a-kontron-sl28" +CONFIG_AHCI=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_FIT=y +CONFIG_SPL_LOAD_FIT=y +# CONFIG_USE_SPL_FIT_GENERATOR is not set +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_BOOTDELAY=10 +CONFIG_USE_BOOTARGS=y +CONFIG_BOARD_LATE_INIT=y +CONFIG_PCI_INIT_R=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y +CONFIG_SPL_DM_SPI_FLASH=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_CMD_ASKENV=y +CONFIG_CMD_GREPENV=y +CONFIG_CMD_NVEDIT_EFI=y +CONFIG_CMD_DM=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_USB=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EFIDEBUG=y +CONFIG_CMD_RNG=y +CONFIG_MP=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIST="" +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_NETCONSOLE=y +CONFIG_DM=y +CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SCSI_AHCI=y +CONFIG_FSL_CAAM=y +CONFIG_SYS_FSL_DDR3=y +CONFIG_DM_I2C=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_I2C_DEFAULT_BUS_NUMBER=0 +CONFIG_I2C_MUX=y +CONFIG_DM_MMC=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_ESDHC=y +CONFIG_FSL_ESDHC_SUPPORT_ADMA2=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_WINBOND=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_PHYLIB=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_DM_MDIO=y +CONFIG_PHY_GIGE=y +CONFIG_E1000=y +CONFIG_FSL_ENETC=y +CONFIG_NVME=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_ECAM_GENERIC=y +CONFIG_PCIE_LAYERSCAPE_RC=y +CONFIG_DM_RNG=y +CONFIG_DM_RTC=y +CONFIG_RTC_RV8803=y +CONFIG_SCSI=y +CONFIG_DM_SCSI=y +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_FSL_DSPI=y +CONFIG_NXP_FSPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +# CONFIG_SPL_DM_USB is not set +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_OF_LIBFDT_ASSUME_MASK=0x0 +CONFIG_OF_LIBFDT_OVERLAY=y diff --git a/configs/ls1012afrdm_qspi_defconfig b/configs/ls1012afrdm_qspi_defconfig index 1af77dc..f24f5f3 100644 --- a/configs/ls1012afrdm_qspi_defconfig +++ b/configs/ls1012afrdm_qspi_defconfig @@ -48,6 +48,7 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_FSL_PFE=y CONFIG_DM_ETH=y CONFIG_E1000=y +CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/ls1012afrdm_tfa_defconfig b/configs/ls1012afrdm_tfa_defconfig index a94887d..7b94958 100644 --- a/configs/ls1012afrdm_tfa_defconfig +++ b/configs/ls1012afrdm_tfa_defconfig @@ -48,6 +48,7 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_FSL_PFE=y CONFIG_DM_ETH=y CONFIG_E1000=y +CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig b/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig index 78e1f66..f08d962 100644 --- a/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig @@ -46,6 +46,7 @@ CONFIG_SPI_FLASH_WINBOND=y CONFIG_FSL_PFE=y CONFIG_DM_ETH=y CONFIG_E1000=y +CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/ls1012afrwy_qspi_defconfig b/configs/ls1012afrwy_qspi_defconfig index bdd4dbe..ff041bf 100644 --- a/configs/ls1012afrwy_qspi_defconfig +++ b/configs/ls1012afrwy_qspi_defconfig @@ -50,6 +50,7 @@ CONFIG_SPI_FLASH_WINBOND=y CONFIG_FSL_PFE=y CONFIG_DM_ETH=y CONFIG_E1000=y +CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig b/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig index 5a58f7c..6048618 100644 --- a/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig @@ -46,6 +46,7 @@ CONFIG_SPI_FLASH_WINBOND=y CONFIG_FSL_PFE=y CONFIG_DM_ETH=y CONFIG_E1000=y +CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/ls1012afrwy_tfa_defconfig b/configs/ls1012afrwy_tfa_defconfig index 7a15c8f..c8b02da 100644 --- a/configs/ls1012afrwy_tfa_defconfig +++ b/configs/ls1012afrwy_tfa_defconfig @@ -50,6 +50,7 @@ CONFIG_SPI_FLASH_WINBOND=y CONFIG_FSL_PFE=y CONFIG_DM_ETH=y CONFIG_E1000=y +CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/ls1012aqds_qspi_defconfig b/configs/ls1012aqds_qspi_defconfig index 1e8e311..c56d04e 100644 --- a/configs/ls1012aqds_qspi_defconfig +++ b/configs/ls1012aqds_qspi_defconfig @@ -67,6 +67,7 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_FSL_PFE=y CONFIG_DM_ETH=y CONFIG_E1000=y +CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig index dc405c7..9144003 100644 --- a/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig @@ -56,6 +56,7 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_FSL_PFE=y CONFIG_DM_ETH=y CONFIG_E1000=y +CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/ls1012aqds_tfa_defconfig b/configs/ls1012aqds_tfa_defconfig index bf03216..a6a44fe 100644 --- a/configs/ls1012aqds_tfa_defconfig +++ b/configs/ls1012aqds_tfa_defconfig @@ -67,6 +67,7 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_FSL_PFE=y CONFIG_DM_ETH=y CONFIG_E1000=y +CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig index 552364a..3c3376b 100644 --- a/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig @@ -49,6 +49,7 @@ CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_SPANSION=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_E1000=y +CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/ls1012ardb_qspi_defconfig b/configs/ls1012ardb_qspi_defconfig index f500479..6675cef 100644 --- a/configs/ls1012ardb_qspi_defconfig +++ b/configs/ls1012ardb_qspi_defconfig @@ -53,6 +53,7 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_FSL_PFE=y CONFIG_DM_ETH=y CONFIG_E1000=y +CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig index cf43243..5edbdc8 100644 --- a/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig @@ -50,6 +50,7 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_FSL_PFE=y CONFIG_DM_ETH=y CONFIG_E1000=y +CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/ls1012ardb_tfa_defconfig b/configs/ls1012ardb_tfa_defconfig index 1bcf80c..b56f813 100644 --- a/configs/ls1012ardb_tfa_defconfig +++ b/configs/ls1012ardb_tfa_defconfig @@ -52,6 +52,7 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_FSL_PFE=y CONFIG_DM_ETH=y CONFIG_E1000=y +CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/ls1021aiot_qspi_defconfig b/configs/ls1021aiot_qspi_defconfig index 78c4d61..31209e4 100644 --- a/configs/ls1021aiot_qspi_defconfig +++ b/configs/ls1021aiot_qspi_defconfig @@ -41,6 +41,7 @@ CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/ls1021aiot_sdcard_defconfig b/configs/ls1021aiot_sdcard_defconfig index bb4b9dd..e541c9c 100644 --- a/configs/ls1021aiot_sdcard_defconfig +++ b/configs/ls1021aiot_sdcard_defconfig @@ -47,6 +47,7 @@ CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/ls1021aqds_ddr4_nor_defconfig b/configs/ls1021aqds_ddr4_nor_defconfig index b6ac523..ee2213d 100644 --- a/configs/ls1021aqds_ddr4_nor_defconfig +++ b/configs/ls1021aqds_ddr4_nor_defconfig @@ -13,7 +13,6 @@ CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=3 CONFIG_SILENT_CONSOLE=y -# CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_MISC_INIT_R=y CONFIG_HUSH_PARSER=y @@ -33,7 +32,6 @@ CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y -CONFIG_CMD_BMP=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y @@ -57,6 +55,7 @@ CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y @@ -70,6 +69,3 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y -# CONFIG_VIDEO_FSL_DCU_FB is not set -# CONFIG_VIDEO is not set -# CONFIG_VIDEO_SW_CURSOR is not set diff --git a/configs/ls1021aqds_ddr4_nor_lpuart_defconfig b/configs/ls1021aqds_ddr4_nor_lpuart_defconfig index 1bb657d..49783e3 100644 --- a/configs/ls1021aqds_ddr4_nor_lpuart_defconfig +++ b/configs/ls1021aqds_ddr4_nor_lpuart_defconfig @@ -14,7 +14,6 @@ CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="LPUART" CONFIG_BOOTDELAY=3 CONFIG_SILENT_CONSOLE=y -# CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_MISC_INIT_R=y CONFIG_HUSH_PARSER=y @@ -34,7 +33,6 @@ CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y -CONFIG_CMD_BMP=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y @@ -58,6 +56,7 @@ CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y @@ -70,6 +69,3 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y -# CONFIG_VIDEO_FSL_DCU_FB is not set -# CONFIG_VIDEO is not set -# CONFIG_VIDEO_SW_CURSOR is not set diff --git a/configs/ls1021aqds_nand_defconfig b/configs/ls1021aqds_nand_defconfig index f0d49ba..f76ce19 100644 --- a/configs/ls1021aqds_nand_defconfig +++ b/configs/ls1021aqds_nand_defconfig @@ -21,7 +21,6 @@ CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND_BOOT" CONFIG_NAND_BOOT=y CONFIG_BOOTDELAY=3 CONFIG_SILENT_CONSOLE=y -# CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_MISC_INIT_R=y CONFIG_SPL_FSL_PBL=y @@ -49,7 +48,6 @@ CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y -CONFIG_CMD_BMP=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y # CONFIG_SPL_EFI_PARTITION is not set @@ -74,6 +72,7 @@ CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y @@ -85,6 +84,3 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y -# CONFIG_VIDEO_FSL_DCU_FB is not set -# CONFIG_VIDEO is not set -# CONFIG_VIDEO_SW_CURSOR is not set diff --git a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig index 0ba4124..bb226bb 100644 --- a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig +++ b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig @@ -14,7 +14,6 @@ CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=3 CONFIG_SILENT_CONSOLE=y -# CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_MISC_INIT_R=y CONFIG_HUSH_PARSER=y @@ -34,7 +33,6 @@ CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y -CONFIG_CMD_BMP=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y @@ -56,6 +54,7 @@ CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y @@ -67,8 +66,5 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y -# CONFIG_VIDEO_FSL_DCU_FB is not set -# CONFIG_VIDEO is not set -# CONFIG_VIDEO_SW_CURSOR is not set CONFIG_RSA=y CONFIG_SPL_RSA=y diff --git a/configs/ls1021aqds_nor_defconfig b/configs/ls1021aqds_nor_defconfig index da2a761..ebcd77c 100644 --- a/configs/ls1021aqds_nor_defconfig +++ b/configs/ls1021aqds_nor_defconfig @@ -13,7 +13,6 @@ CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=3 CONFIG_SILENT_CONSOLE=y -# CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_MISC_INIT_R=y CONFIG_HUSH_PARSER=y @@ -33,7 +32,6 @@ CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y -CONFIG_CMD_BMP=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y @@ -58,6 +56,7 @@ CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y @@ -71,6 +70,3 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y -# CONFIG_VIDEO_FSL_DCU_FB is not set -# CONFIG_VIDEO is not set -# CONFIG_VIDEO_SW_CURSOR is not set diff --git a/configs/ls1021aqds_nor_lpuart_defconfig b/configs/ls1021aqds_nor_lpuart_defconfig index d3d8fcb..ddd7523 100644 --- a/configs/ls1021aqds_nor_lpuart_defconfig +++ b/configs/ls1021aqds_nor_lpuart_defconfig @@ -14,7 +14,6 @@ CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="LPUART" CONFIG_BOOTDELAY=3 CONFIG_SILENT_CONSOLE=y -# CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_MISC_INIT_R=y CONFIG_HUSH_PARSER=y @@ -34,7 +33,6 @@ CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y -CONFIG_CMD_BMP=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y @@ -59,6 +57,7 @@ CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y @@ -71,6 +70,3 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y -# CONFIG_VIDEO_FSL_DCU_FB is not set -# CONFIG_VIDEO is not set -# CONFIG_VIDEO_SW_CURSOR is not set diff --git a/configs/ls1021aqds_qspi_defconfig b/configs/ls1021aqds_qspi_defconfig index 08b9ec2..f44783c 100644 --- a/configs/ls1021aqds_qspi_defconfig +++ b/configs/ls1021aqds_qspi_defconfig @@ -16,7 +16,6 @@ CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT" CONFIG_QSPI_BOOT=y CONFIG_BOOTDELAY=3 CONFIG_SILENT_CONSOLE=y -# CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_MISC_INIT_R=y CONFIG_HUSH_PARSER=y @@ -34,7 +33,6 @@ CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y -CONFIG_CMD_BMP=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y @@ -55,6 +53,7 @@ CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y @@ -70,6 +69,3 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y -# CONFIG_VIDEO_FSL_DCU_FB is not set -# CONFIG_VIDEO is not set -# CONFIG_VIDEO_SW_CURSOR is not set diff --git a/configs/ls1021aqds_sdcard_ifc_defconfig b/configs/ls1021aqds_sdcard_ifc_defconfig index ef194df..ea3844d 100644 --- a/configs/ls1021aqds_sdcard_ifc_defconfig +++ b/configs/ls1021aqds_sdcard_ifc_defconfig @@ -20,7 +20,6 @@ CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SD_BOOT" CONFIG_SD_BOOT=y CONFIG_BOOTDELAY=3 CONFIG_SILENT_CONSOLE=y -# CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_MISC_INIT_R=y CONFIG_SPL_FSL_PBL=y @@ -47,7 +46,6 @@ CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y -CONFIG_CMD_BMP=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y # CONFIG_SPL_EFI_PARTITION is not set @@ -73,6 +71,7 @@ CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y @@ -84,6 +83,3 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y -# CONFIG_VIDEO_FSL_DCU_FB is not set -# CONFIG_VIDEO is not set -# CONFIG_VIDEO_SW_CURSOR is not set diff --git a/configs/ls1021aqds_sdcard_qspi_defconfig b/configs/ls1021aqds_sdcard_qspi_defconfig index e64cb38..8a6cb2a 100644 --- a/configs/ls1021aqds_sdcard_qspi_defconfig +++ b/configs/ls1021aqds_sdcard_qspi_defconfig @@ -20,7 +20,6 @@ CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SD_BOOT,SD_BOOT_QSPI" CONFIG_SD_BOOT=y CONFIG_BOOTDELAY=3 CONFIG_SILENT_CONSOLE=y -# CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_MISC_INIT_R=y CONFIG_SPL_FSL_PBL=y @@ -45,7 +44,6 @@ CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y -CONFIG_CMD_BMP=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y # CONFIG_SPL_EFI_PARTITION is not set @@ -67,6 +65,7 @@ CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y @@ -82,6 +81,3 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y -# CONFIG_VIDEO_FSL_DCU_FB is not set -# CONFIG_VIDEO is not set -# CONFIG_VIDEO_SW_CURSOR is not set diff --git a/configs/ls1021atsn_qspi_defconfig b/configs/ls1021atsn_qspi_defconfig index 43f9e51..17f7eea 100644 --- a/configs/ls1021atsn_qspi_defconfig +++ b/configs/ls1021atsn_qspi_defconfig @@ -48,6 +48,7 @@ CONFIG_DM_MDIO=y CONFIG_PHY_GIGE=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/ls1021atsn_sdcard_defconfig b/configs/ls1021atsn_sdcard_defconfig index 49197ee..a434530 100644 --- a/configs/ls1021atsn_sdcard_defconfig +++ b/configs/ls1021atsn_sdcard_defconfig @@ -59,6 +59,7 @@ CONFIG_DM_MDIO=y CONFIG_PHY_GIGE=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig index df99a75..73d0074 100644 --- a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig +++ b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig @@ -17,7 +17,6 @@ CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0" CONFIG_SILENT_CONSOLE=y -# CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_MISC_INIT_R=y CONFIG_CMD_IMLS=y @@ -31,7 +30,6 @@ CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_BMP=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_DM=y @@ -51,6 +49,7 @@ CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y @@ -61,8 +60,5 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y -# CONFIG_VIDEO_FSL_DCU_FB is not set -# CONFIG_VIDEO is not set -# CONFIG_VIDEO_SW_CURSOR is not set CONFIG_RSA=y CONFIG_SPL_RSA=y diff --git a/configs/ls1021atwr_nor_defconfig b/configs/ls1021atwr_nor_defconfig index a71f7b3..11a981a 100644 --- a/configs/ls1021atwr_nor_defconfig +++ b/configs/ls1021atwr_nor_defconfig @@ -16,7 +16,6 @@ CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0" CONFIG_SILENT_CONSOLE=y -# CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_MISC_INIT_R=y CONFIG_CMD_IMLS=y @@ -30,7 +29,6 @@ CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_BMP=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_FLASH=y @@ -53,6 +51,7 @@ CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y @@ -65,6 +64,3 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y -# CONFIG_VIDEO_FSL_DCU_FB is not set -# CONFIG_VIDEO is not set -# CONFIG_VIDEO_SW_CURSOR is not set diff --git a/configs/ls1021atwr_nor_lpuart_defconfig b/configs/ls1021atwr_nor_lpuart_defconfig index d24b368..0946f8f 100644 --- a/configs/ls1021atwr_nor_lpuart_defconfig +++ b/configs/ls1021atwr_nor_lpuart_defconfig @@ -18,7 +18,6 @@ CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0" # CONFIG_USE_BOOTCOMMAND is not set CONFIG_SILENT_CONSOLE=y -# CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_MISC_INIT_R=y CONFIG_CMD_IMLS=y @@ -32,7 +31,6 @@ CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_BMP=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_FLASH=y @@ -55,6 +53,7 @@ CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y @@ -66,6 +65,3 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y -# CONFIG_VIDEO_FSL_DCU_FB is not set -# CONFIG_VIDEO is not set -# CONFIG_VIDEO_SW_CURSOR is not set diff --git a/configs/ls1021atwr_qspi_defconfig b/configs/ls1021atwr_qspi_defconfig index 2b11730..a764714 100644 --- a/configs/ls1021atwr_qspi_defconfig +++ b/configs/ls1021atwr_qspi_defconfig @@ -20,7 +20,6 @@ CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0" # CONFIG_USE_BOOTCOMMAND is not set CONFIG_SILENT_CONSOLE=y -# CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_MISC_INIT_R=y CONFIG_CMD_GREPENV=y @@ -33,7 +32,6 @@ CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_BMP=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y @@ -54,6 +52,7 @@ CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y @@ -68,6 +67,3 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y -# CONFIG_VIDEO_FSL_DCU_FB is not set -# CONFIG_VIDEO is not set -# CONFIG_VIDEO_SW_CURSOR is not set diff --git a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig index 70154bc..3d3e093 100644 --- a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig +++ b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig @@ -23,7 +23,6 @@ CONFIG_BOOTDELAY=0 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0" CONFIG_SILENT_CONSOLE=y -# CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_MISC_INIT_R=y CONFIG_SPL_FSL_PBL=y @@ -45,7 +44,6 @@ CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y -CONFIG_CMD_BMP=y # CONFIG_SPL_EFI_PARTITION is not set CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y @@ -75,8 +73,5 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y -# CONFIG_VIDEO_FSL_DCU_FB is not set -# CONFIG_VIDEO is not set -# CONFIG_VIDEO_SW_CURSOR is not set CONFIG_RSA=y CONFIG_SPL_RSA=y diff --git a/configs/ls1021atwr_sdcard_ifc_defconfig b/configs/ls1021atwr_sdcard_ifc_defconfig index af2b5aa..f96514a 100644 --- a/configs/ls1021atwr_sdcard_ifc_defconfig +++ b/configs/ls1021atwr_sdcard_ifc_defconfig @@ -24,7 +24,6 @@ CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0" CONFIG_SILENT_CONSOLE=y -# CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_MISC_INIT_R=y CONFIG_SPL_FSL_PBL=y @@ -44,7 +43,6 @@ CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y -CONFIG_CMD_BMP=y # CONFIG_SPL_EFI_PARTITION is not set CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y @@ -68,6 +66,7 @@ CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y @@ -78,6 +77,3 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y -# CONFIG_VIDEO_FSL_DCU_FB is not set -# CONFIG_VIDEO is not set -# CONFIG_VIDEO_SW_CURSOR is not set diff --git a/configs/ls1021atwr_sdcard_qspi_defconfig b/configs/ls1021atwr_sdcard_qspi_defconfig index dd80eb4..3b9cef0 100644 --- a/configs/ls1021atwr_sdcard_qspi_defconfig +++ b/configs/ls1021atwr_sdcard_qspi_defconfig @@ -24,7 +24,6 @@ CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0" CONFIG_SILENT_CONSOLE=y -# CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_MISC_INIT_R=y CONFIG_SPL_FSL_PBL=y @@ -43,7 +42,6 @@ CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y -CONFIG_CMD_BMP=y # CONFIG_SPL_EFI_PARTITION is not set CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y @@ -65,6 +63,7 @@ CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y @@ -79,6 +78,3 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y -# CONFIG_VIDEO_FSL_DCU_FB is not set -# CONFIG_VIDEO is not set -# CONFIG_VIDEO_SW_CURSOR is not set diff --git a/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig index 1dc9d31..4d255ac 100644 --- a/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig @@ -61,6 +61,7 @@ CONFIG_DM_MDIO_MUX=y CONFIG_E1000=y CONFIG_FSL_ENETC=y CONFIG_MDIO_MUX_I2CREG=y +CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/ls1028aqds_tfa_defconfig b/configs/ls1028aqds_tfa_defconfig index bf9fee9..55dd931 100644 --- a/configs/ls1028aqds_tfa_defconfig +++ b/configs/ls1028aqds_tfa_defconfig @@ -67,6 +67,7 @@ CONFIG_DM_MDIO_MUX=y CONFIG_E1000=y CONFIG_FSL_ENETC=y CONFIG_MDIO_MUX_I2CREG=y +CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/ls1028aqds_tfa_lpuart_defconfig b/configs/ls1028aqds_tfa_lpuart_defconfig index 3fccd4b..01d51ac 100644 --- a/configs/ls1028aqds_tfa_lpuart_defconfig +++ b/configs/ls1028aqds_tfa_lpuart_defconfig @@ -67,6 +67,7 @@ CONFIG_DM_MDIO_MUX=y CONFIG_E1000=y CONFIG_FSL_ENETC=y CONFIG_MDIO_MUX_I2CREG=y +CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig index 5257080..166d0f2 100644 --- a/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig @@ -58,6 +58,7 @@ CONFIG_DM_MDIO=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_FSL_ENETC=y +CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/ls1028ardb_tfa_defconfig b/configs/ls1028ardb_tfa_defconfig index 9435e70..85b1e0e 100644 --- a/configs/ls1028ardb_tfa_defconfig +++ b/configs/ls1028ardb_tfa_defconfig @@ -64,6 +64,7 @@ CONFIG_DM_MDIO=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_FSL_ENETC=y +CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/ls1043aqds_defconfig b/configs/ls1043aqds_defconfig index 4846ddd..77993f8 100644 --- a/configs/ls1043aqds_defconfig +++ b/configs/ls1043aqds_defconfig @@ -54,6 +54,7 @@ CONFIG_PHY_REALTEK=y CONFIG_PHY_VITESSE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y +CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/ls1043aqds_lpuart_defconfig b/configs/ls1043aqds_lpuart_defconfig index 6d8b6f3..8b486ef 100644 --- a/configs/ls1043aqds_lpuart_defconfig +++ b/configs/ls1043aqds_lpuart_defconfig @@ -55,6 +55,7 @@ CONFIG_PHY_REALTEK=y CONFIG_PHY_VITESSE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y +CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/ls1043aqds_nand_defconfig b/configs/ls1043aqds_nand_defconfig index 98a9af5..060dd19 100644 --- a/configs/ls1043aqds_nand_defconfig +++ b/configs/ls1043aqds_nand_defconfig @@ -70,6 +70,7 @@ CONFIG_PHY_REALTEK=y CONFIG_PHY_VITESSE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y +CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/ls1043aqds_nor_ddr3_defconfig b/configs/ls1043aqds_nor_ddr3_defconfig index 87651a7..a6d3d13 100644 --- a/configs/ls1043aqds_nor_ddr3_defconfig +++ b/configs/ls1043aqds_nor_ddr3_defconfig @@ -55,6 +55,7 @@ CONFIG_PHY_REALTEK=y CONFIG_PHY_VITESSE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y +CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/ls1043aqds_qspi_defconfig b/configs/ls1043aqds_qspi_defconfig index 2e2d4db..aa4b14c 100644 --- a/configs/ls1043aqds_qspi_defconfig +++ b/configs/ls1043aqds_qspi_defconfig @@ -50,6 +50,7 @@ CONFIG_PHY_REALTEK=y CONFIG_PHY_VITESSE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y +CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/ls1043aqds_sdcard_ifc_defconfig b/configs/ls1043aqds_sdcard_ifc_defconfig index ca825d7..eb1929b 100644 --- a/configs/ls1043aqds_sdcard_ifc_defconfig +++ b/configs/ls1043aqds_sdcard_ifc_defconfig @@ -71,6 +71,7 @@ CONFIG_PHY_REALTEK=y CONFIG_PHY_VITESSE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y +CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/ls1043aqds_sdcard_qspi_defconfig b/configs/ls1043aqds_sdcard_qspi_defconfig index 3b24e19..6bde77c 100644 --- a/configs/ls1043aqds_sdcard_qspi_defconfig +++ b/configs/ls1043aqds_sdcard_qspi_defconfig @@ -64,6 +64,7 @@ CONFIG_PHY_REALTEK=y CONFIG_PHY_VITESSE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y +CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig index 1aa657a..59e468f 100644 --- a/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig @@ -54,6 +54,7 @@ CONFIG_PHY_REALTEK=y CONFIG_PHY_VITESSE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y +CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/ls1043aqds_tfa_defconfig b/configs/ls1043aqds_tfa_defconfig index d306773..5f8611a 100644 --- a/configs/ls1043aqds_tfa_defconfig +++ b/configs/ls1043aqds_tfa_defconfig @@ -64,6 +64,7 @@ CONFIG_PHY_REALTEK=y CONFIG_PHY_VITESSE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y +CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/ls1043ardb_SECURE_BOOT_defconfig b/configs/ls1043ardb_SECURE_BOOT_defconfig index bd723a5..22277a8 100644 --- a/configs/ls1043ardb_SECURE_BOOT_defconfig +++ b/configs/ls1043ardb_SECURE_BOOT_defconfig @@ -45,6 +45,7 @@ CONFIG_DM_MDIO=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y +CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/ls1043ardb_defconfig b/configs/ls1043ardb_defconfig index 59e88fd..f32573d 100644 --- a/configs/ls1043ardb_defconfig +++ b/configs/ls1043ardb_defconfig @@ -48,6 +48,7 @@ CONFIG_DM_ETH=y CONFIG_DM_MDIO=y CONFIG_E1000=y CONFIG_FMAN_ENET=y +CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/ls1043ardb_nand_SECURE_BOOT_defconfig b/configs/ls1043ardb_nand_SECURE_BOOT_defconfig index a535109..84b2950 100644 --- a/configs/ls1043ardb_nand_SECURE_BOOT_defconfig +++ b/configs/ls1043ardb_nand_SECURE_BOOT_defconfig @@ -65,6 +65,7 @@ CONFIG_DM_ETH=y CONFIG_DM_MDIO=y CONFIG_E1000=y CONFIG_FMAN_ENET=y +CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/ls1043ardb_nand_defconfig b/configs/ls1043ardb_nand_defconfig index 9a43ea8..bb0e2bf 100644 --- a/configs/ls1043ardb_nand_defconfig +++ b/configs/ls1043ardb_nand_defconfig @@ -66,6 +66,7 @@ CONFIG_DM_ETH=y CONFIG_DM_MDIO=y CONFIG_E1000=y CONFIG_FMAN_ENET=y +CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/ls1043ardb_sdcard_defconfig b/configs/ls1043ardb_sdcard_defconfig index cf5b597..ff2e669 100644 --- a/configs/ls1043ardb_sdcard_defconfig +++ b/configs/ls1043ardb_sdcard_defconfig @@ -66,6 +66,7 @@ CONFIG_DM_ETH=y CONFIG_DM_MDIO=y CONFIG_E1000=y CONFIG_FMAN_ENET=y +CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig index aac3175..93f9b9a 100644 --- a/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig @@ -47,6 +47,7 @@ CONFIG_DM_MDIO=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y +CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/ls1043ardb_tfa_defconfig b/configs/ls1043ardb_tfa_defconfig index d15869f..a74f124 100644 --- a/configs/ls1043ardb_tfa_defconfig +++ b/configs/ls1043ardb_tfa_defconfig @@ -53,6 +53,7 @@ CONFIG_DM_ETH=y CONFIG_DM_MDIO=y CONFIG_E1000=y CONFIG_FMAN_ENET=y +CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/ls1046afrwy_tfa_defconfig b/configs/ls1046afrwy_tfa_defconfig index 2d76b35..add3001 100644 --- a/configs/ls1046afrwy_tfa_defconfig +++ b/configs/ls1046afrwy_tfa_defconfig @@ -50,6 +50,7 @@ CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y +CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/ls1046aqds_SECURE_BOOT_defconfig b/configs/ls1046aqds_SECURE_BOOT_defconfig index 26b42fa..2141e66 100644 --- a/configs/ls1046aqds_SECURE_BOOT_defconfig +++ b/configs/ls1046aqds_SECURE_BOOT_defconfig @@ -52,6 +52,7 @@ CONFIG_PHY_REALTEK=y CONFIG_PHY_VITESSE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y +CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/ls1046aqds_defconfig b/configs/ls1046aqds_defconfig index dfa1882..5b7e028 100644 --- a/configs/ls1046aqds_defconfig +++ b/configs/ls1046aqds_defconfig @@ -55,6 +55,7 @@ CONFIG_PHY_REALTEK=y CONFIG_PHY_VITESSE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y +CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/ls1046aqds_lpuart_defconfig b/configs/ls1046aqds_lpuart_defconfig index f37cdf7..7d07efe 100644 --- a/configs/ls1046aqds_lpuart_defconfig +++ b/configs/ls1046aqds_lpuart_defconfig @@ -56,6 +56,7 @@ CONFIG_PHY_REALTEK=y CONFIG_PHY_VITESSE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y +CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/ls1046aqds_nand_defconfig b/configs/ls1046aqds_nand_defconfig index 5256f30..1bf2460 100644 --- a/configs/ls1046aqds_nand_defconfig +++ b/configs/ls1046aqds_nand_defconfig @@ -63,6 +63,7 @@ CONFIG_PHY_REALTEK=y CONFIG_PHY_VITESSE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y +CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/ls1046aqds_qspi_defconfig b/configs/ls1046aqds_qspi_defconfig index 466d7ca..3183523 100644 --- a/configs/ls1046aqds_qspi_defconfig +++ b/configs/ls1046aqds_qspi_defconfig @@ -52,6 +52,7 @@ CONFIG_PHY_REALTEK=y CONFIG_PHY_VITESSE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y +CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/ls1046aqds_sdcard_ifc_defconfig b/configs/ls1046aqds_sdcard_ifc_defconfig index 959b8ff..705986f 100644 --- a/configs/ls1046aqds_sdcard_ifc_defconfig +++ b/configs/ls1046aqds_sdcard_ifc_defconfig @@ -73,6 +73,7 @@ CONFIG_PHY_REALTEK=y CONFIG_PHY_VITESSE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y +CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/ls1046aqds_sdcard_qspi_defconfig b/configs/ls1046aqds_sdcard_qspi_defconfig index 527eb08..47c6176 100644 --- a/configs/ls1046aqds_sdcard_qspi_defconfig +++ b/configs/ls1046aqds_sdcard_qspi_defconfig @@ -67,6 +67,7 @@ CONFIG_PHY_REALTEK=y CONFIG_PHY_VITESSE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y +CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig index 6860e48..7b8b540 100644 --- a/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig @@ -55,6 +55,7 @@ CONFIG_PHY_REALTEK=y CONFIG_PHY_VITESSE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y +CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/ls1046aqds_tfa_defconfig b/configs/ls1046aqds_tfa_defconfig index f481add..08d6869 100644 --- a/configs/ls1046aqds_tfa_defconfig +++ b/configs/ls1046aqds_tfa_defconfig @@ -65,6 +65,7 @@ CONFIG_PHY_REALTEK=y CONFIG_PHY_VITESSE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y +CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/ls1046ardb_emmc_defconfig b/configs/ls1046ardb_emmc_defconfig index cd0ba8f..efb88d0 100644 --- a/configs/ls1046ardb_emmc_defconfig +++ b/configs/ls1046ardb_emmc_defconfig @@ -65,6 +65,7 @@ CONFIG_DM_ETH=y CONFIG_DM_MDIO=y CONFIG_E1000=y CONFIG_FMAN_ENET=y +CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig index d7ee89c..50356dc 100644 --- a/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig @@ -47,6 +47,7 @@ CONFIG_DM_ETH=y CONFIG_DM_MDIO=y CONFIG_E1000=y CONFIG_FMAN_ENET=y +CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/ls1046ardb_qspi_defconfig b/configs/ls1046ardb_qspi_defconfig index 481c42c..ac1d5ab 100644 --- a/configs/ls1046ardb_qspi_defconfig +++ b/configs/ls1046ardb_qspi_defconfig @@ -51,6 +51,7 @@ CONFIG_DM_ETH=y CONFIG_DM_MDIO=y CONFIG_E1000=y CONFIG_FMAN_ENET=y +CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/ls1046ardb_qspi_spl_defconfig b/configs/ls1046ardb_qspi_spl_defconfig index 3270286..b1ac6e0a 100644 --- a/configs/ls1046ardb_qspi_spl_defconfig +++ b/configs/ls1046ardb_qspi_spl_defconfig @@ -69,6 +69,7 @@ CONFIG_DM_MDIO=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y +CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/ls1046ardb_sdcard_defconfig b/configs/ls1046ardb_sdcard_defconfig index d5e519f..069b228 100644 --- a/configs/ls1046ardb_sdcard_defconfig +++ b/configs/ls1046ardb_sdcard_defconfig @@ -64,6 +64,7 @@ CONFIG_DM_ETH=y CONFIG_DM_MDIO=y CONFIG_E1000=y CONFIG_FMAN_ENET=y +CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig index 6ef4e24..a4b67a5 100644 --- a/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig @@ -47,6 +47,7 @@ CONFIG_DM_ETH=y CONFIG_DM_MDIO=y CONFIG_E1000=y CONFIG_FMAN_ENET=y +CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/ls1046ardb_tfa_defconfig b/configs/ls1046ardb_tfa_defconfig index d123a8d..4ed3317 100644 --- a/configs/ls1046ardb_tfa_defconfig +++ b/configs/ls1046ardb_tfa_defconfig @@ -53,6 +53,7 @@ CONFIG_DM_ETH=y CONFIG_DM_MDIO=y CONFIG_E1000=y CONFIG_FMAN_ENET=y +CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/ls1088aqds_defconfig b/configs/ls1088aqds_defconfig index 9642de2..90c59a5 100644 --- a/configs/ls1088aqds_defconfig +++ b/configs/ls1088aqds_defconfig @@ -57,6 +57,7 @@ CONFIG_PHY_TERANETICS=y CONFIG_PHY_VITESSE=y CONFIG_E1000=y CONFIG_MII=y +CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig b/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig index 0d35e91..5cbe406 100644 --- a/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig @@ -31,7 +31,6 @@ CONFIG_CMD_NAND=y CONFIG_CMD_PCI=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_MDIO is not set CONFIG_CMD_CACHE=y CONFIG_MP=y CONFIG_OF_CONTROL=y @@ -55,6 +54,7 @@ CONFIG_PHY_TERANETICS=y CONFIG_PHY_VITESSE=y CONFIG_E1000=y CONFIG_MII=y +CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/ls1088aqds_qspi_defconfig b/configs/ls1088aqds_qspi_defconfig index fcb7678..97b60c0 100644 --- a/configs/ls1088aqds_qspi_defconfig +++ b/configs/ls1088aqds_qspi_defconfig @@ -32,7 +32,6 @@ CONFIG_CMD_NAND=y CONFIG_CMD_PCI=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_MDIO is not set CONFIG_CMD_CACHE=y CONFIG_MP=y CONFIG_OF_CONTROL=y @@ -58,6 +57,7 @@ CONFIG_PHY_TERANETICS=y CONFIG_PHY_VITESSE=y CONFIG_E1000=y CONFIG_MII=y +CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/ls1088aqds_sdcard_ifc_defconfig b/configs/ls1088aqds_sdcard_ifc_defconfig index 1f8398c..240bcb2 100644 --- a/configs/ls1088aqds_sdcard_ifc_defconfig +++ b/configs/ls1088aqds_sdcard_ifc_defconfig @@ -67,6 +67,7 @@ CONFIG_PHY_TERANETICS=y CONFIG_PHY_VITESSE=y CONFIG_E1000=y CONFIG_MII=y +CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/ls1088aqds_sdcard_qspi_defconfig b/configs/ls1088aqds_sdcard_qspi_defconfig index 6558c16..051bc3b 100644 --- a/configs/ls1088aqds_sdcard_qspi_defconfig +++ b/configs/ls1088aqds_sdcard_qspi_defconfig @@ -42,7 +42,6 @@ CONFIG_CMD_NAND=y CONFIG_CMD_PCI=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_MDIO is not set CONFIG_CMD_CACHE=y CONFIG_MP=y CONFIG_OF_CONTROL=y @@ -68,6 +67,7 @@ CONFIG_PHY_TERANETICS=y CONFIG_PHY_VITESSE=y CONFIG_E1000=y CONFIG_MII=y +CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/ls1088aqds_tfa_defconfig b/configs/ls1088aqds_tfa_defconfig index 582cd85..99fb3c0 100644 --- a/configs/ls1088aqds_tfa_defconfig +++ b/configs/ls1088aqds_tfa_defconfig @@ -36,7 +36,6 @@ CONFIG_CMD_NAND=y CONFIG_CMD_PCI=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_MDIO is not set CONFIG_CMD_CACHE=y CONFIG_MP=y CONFIG_OF_CONTROL=y @@ -81,6 +80,7 @@ CONFIG_E1000=y CONFIG_MII=y CONFIG_MDIO_MUX_I2CREG=y CONFIG_FSL_LS_MDIO=y +CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig index 40f66fa..c45442c 100644 --- a/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig @@ -33,7 +33,6 @@ CONFIG_CMD_NAND=y CONFIG_CMD_PCI=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_MDIO is not set CONFIG_CMD_CACHE=y CONFIG_MP=y CONFIG_OF_CONTROL=y @@ -57,6 +56,7 @@ CONFIG_DM_MDIO=y CONFIG_E1000=y CONFIG_MII=y CONFIG_FSL_LS_MDIO=y +CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/ls1088ardb_qspi_defconfig b/configs/ls1088ardb_qspi_defconfig index d7ecff2..84aa85f 100644 --- a/configs/ls1088ardb_qspi_defconfig +++ b/configs/ls1088ardb_qspi_defconfig @@ -34,7 +34,6 @@ CONFIG_CMD_NAND=y CONFIG_CMD_PCI=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_MDIO is not set CONFIG_CMD_CACHE=y CONFIG_MP=y CONFIG_OF_CONTROL=y @@ -60,6 +59,7 @@ CONFIG_DM_MDIO=y CONFIG_E1000=y CONFIG_MII=y CONFIG_FSL_LS_MDIO=y +CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig b/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig index ffc4588..d55a5c5 100644 --- a/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig @@ -45,7 +45,6 @@ CONFIG_CMD_NAND=y CONFIG_CMD_PCI=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_MDIO is not set CONFIG_CMD_CACHE=y CONFIG_MP=y CONFIG_OF_CONTROL=y diff --git a/configs/ls1088ardb_sdcard_qspi_defconfig b/configs/ls1088ardb_sdcard_qspi_defconfig index 6adfadf..6caf595 100644 --- a/configs/ls1088ardb_sdcard_qspi_defconfig +++ b/configs/ls1088ardb_sdcard_qspi_defconfig @@ -44,7 +44,6 @@ CONFIG_CMD_NAND=y CONFIG_CMD_PCI=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_MDIO is not set CONFIG_CMD_CACHE=y CONFIG_MP=y CONFIG_OF_CONTROL=y @@ -70,6 +69,7 @@ CONFIG_DM_MDIO=y CONFIG_E1000=y CONFIG_MII=y CONFIG_FSL_LS_MDIO=y +CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig index 7677159..f7a40b2 100644 --- a/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig @@ -35,7 +35,6 @@ CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y CONFIG_CMD_PCI=y CONFIG_CMD_USB=y -# CONFIG_CMD_MDIO is not set CONFIG_CMD_CACHE=y CONFIG_MP=y CONFIG_OF_CONTROL=y @@ -64,6 +63,7 @@ CONFIG_DM_MDIO=y CONFIG_E1000=y CONFIG_MII=y CONFIG_FSL_LS_MDIO=y +CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/ls1088ardb_tfa_defconfig b/configs/ls1088ardb_tfa_defconfig index c6c860c..efbe177 100644 --- a/configs/ls1088ardb_tfa_defconfig +++ b/configs/ls1088ardb_tfa_defconfig @@ -37,7 +37,6 @@ CONFIG_CMD_NAND=y CONFIG_CMD_PCI=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_MDIO is not set CONFIG_CMD_CACHE=y CONFIG_MP=y CONFIG_OF_CONTROL=y @@ -69,6 +68,7 @@ CONFIG_DM_MDIO=y CONFIG_E1000=y CONFIG_MII=y CONFIG_FSL_LS_MDIO=y +CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/ls2080aqds_SECURE_BOOT_defconfig b/configs/ls2080aqds_SECURE_BOOT_defconfig index bb421db..e6ff8b8 100644 --- a/configs/ls2080aqds_SECURE_BOOT_defconfig +++ b/configs/ls2080aqds_SECURE_BOOT_defconfig @@ -52,6 +52,7 @@ CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y +CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/ls2080aqds_defconfig b/configs/ls2080aqds_defconfig index 76ee054..31d79cc 100644 --- a/configs/ls2080aqds_defconfig +++ b/configs/ls2080aqds_defconfig @@ -55,6 +55,7 @@ CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y +CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/ls2080aqds_nand_defconfig b/configs/ls2080aqds_nand_defconfig index abc16a2..2016606 100644 --- a/configs/ls2080aqds_nand_defconfig +++ b/configs/ls2080aqds_nand_defconfig @@ -62,6 +62,7 @@ CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y +CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/ls2080aqds_qspi_defconfig b/configs/ls2080aqds_qspi_defconfig index 2604ac2..c1e49b5 100644 --- a/configs/ls2080aqds_qspi_defconfig +++ b/configs/ls2080aqds_qspi_defconfig @@ -54,6 +54,7 @@ CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y +CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/ls2080aqds_sdcard_defconfig b/configs/ls2080aqds_sdcard_defconfig index 908a548..d866966 100644 --- a/configs/ls2080aqds_sdcard_defconfig +++ b/configs/ls2080aqds_sdcard_defconfig @@ -61,6 +61,7 @@ CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y +CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/ls2080ardb_SECURE_BOOT_defconfig b/configs/ls2080ardb_SECURE_BOOT_defconfig index 4341e61..be3b5ab 100644 --- a/configs/ls2080ardb_SECURE_BOOT_defconfig +++ b/configs/ls2080ardb_SECURE_BOOT_defconfig @@ -49,6 +49,7 @@ CONFIG_PHY_AQUANTIA=y CONFIG_PHY_CORTINA=y CONFIG_E1000=y CONFIG_MII=y +CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/ls2080ardb_defconfig b/configs/ls2080ardb_defconfig index 4cf27d1..dd77b4a 100644 --- a/configs/ls2080ardb_defconfig +++ b/configs/ls2080ardb_defconfig @@ -52,6 +52,7 @@ CONFIG_PHY_AQUANTIA=y CONFIG_PHY_CORTINA=y CONFIG_E1000=y CONFIG_MII=y +CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/ls2080ardb_nand_defconfig b/configs/ls2080ardb_nand_defconfig index 19436bd..50ac69b 100644 --- a/configs/ls2080ardb_nand_defconfig +++ b/configs/ls2080ardb_nand_defconfig @@ -60,6 +60,7 @@ CONFIG_PHY_AQUANTIA=y CONFIG_PHY_CORTINA=y CONFIG_E1000=y CONFIG_MII=y +CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/ls2081ardb_defconfig b/configs/ls2081ardb_defconfig index 39e5d7d..1bcfcde 100644 --- a/configs/ls2081ardb_defconfig +++ b/configs/ls2081ardb_defconfig @@ -47,6 +47,7 @@ CONFIG_PHY_AQUANTIA=y CONFIG_PHY_CORTINA=y CONFIG_E1000=y CONFIG_MII=y +CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/ls2088aqds_tfa_defconfig b/configs/ls2088aqds_tfa_defconfig index 6127e98..9e6e9f6 100644 --- a/configs/ls2088aqds_tfa_defconfig +++ b/configs/ls2088aqds_tfa_defconfig @@ -74,6 +74,7 @@ CONFIG_E1000=y CONFIG_MII=y CONFIG_MDIO_MUX_I2CREG=y CONFIG_FSL_LS_MDIO=y +CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig b/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig index d3f8d53..4dbdc1f 100644 --- a/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig +++ b/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig @@ -47,6 +47,7 @@ CONFIG_DM_MDIO=y CONFIG_E1000=y CONFIG_MII=y CONFIG_FSL_LS_MDIO=y +CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/ls2088ardb_qspi_defconfig b/configs/ls2088ardb_qspi_defconfig index 972e7f8..f81e2ae 100644 --- a/configs/ls2088ardb_qspi_defconfig +++ b/configs/ls2088ardb_qspi_defconfig @@ -54,6 +54,7 @@ CONFIG_DM_MDIO=y CONFIG_E1000=y CONFIG_MII=y CONFIG_FSL_LS_MDIO=y +CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig b/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig index c5da5a3..ccf79c1 100644 --- a/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig @@ -62,6 +62,7 @@ CONFIG_DM_MDIO=y CONFIG_E1000=y CONFIG_MII=y CONFIG_FSL_LS_MDIO=y +CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/ls2088ardb_tfa_defconfig b/configs/ls2088ardb_tfa_defconfig index faecc7b..4277f9c 100644 --- a/configs/ls2088ardb_tfa_defconfig +++ b/configs/ls2088ardb_tfa_defconfig @@ -70,6 +70,7 @@ CONFIG_DM_MDIO=y CONFIG_E1000=y CONFIG_MII=y CONFIG_FSL_LS_MDIO=y +CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig b/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig index 461d719d..a6a3feb 100644 --- a/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig @@ -64,6 +64,7 @@ CONFIG_DM_MDIO_MUX=y CONFIG_E1000=y CONFIG_MDIO_MUX_I2CREG=y CONFIG_FSL_LS_MDIO=y +CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/lx2160aqds_tfa_defconfig b/configs/lx2160aqds_tfa_defconfig index 6dde093..d96c3b1 100644 --- a/configs/lx2160aqds_tfa_defconfig +++ b/configs/lx2160aqds_tfa_defconfig @@ -71,6 +71,7 @@ CONFIG_DM_MDIO_MUX=y CONFIG_E1000=y CONFIG_MDIO_MUX_I2CREG=y CONFIG_FSL_LS_MDIO=y +CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig b/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig index 159ae9d..b2912e4 100644 --- a/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig @@ -56,6 +56,7 @@ CONFIG_DM_ETH=y CONFIG_DM_MDIO=y CONFIG_E1000=y CONFIG_FSL_LS_MDIO=y +CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/lx2160ardb_tfa_defconfig b/configs/lx2160ardb_tfa_defconfig index 8a4e6ef..5a9e2e7 100644 --- a/configs/lx2160ardb_tfa_defconfig +++ b/configs/lx2160ardb_tfa_defconfig @@ -30,6 +30,7 @@ CONFIG_CMD_DM=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_OPTEE_RPMB=y CONFIG_CMD_PCI=y CONFIG_CMD_USB=y CONFIG_CMD_WDT=y @@ -48,6 +49,7 @@ CONFIG_DM_I2C=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y CONFIG_I2C_DEFAULT_BUS_NUMBER=0 CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_RPMB=y CONFIG_MMC_HS400_SUPPORT=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y @@ -63,6 +65,7 @@ CONFIG_DM_ETH=y CONFIG_DM_MDIO=y CONFIG_E1000=y CONFIG_FSL_LS_MDIO=y +CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y @@ -74,6 +77,8 @@ CONFIG_DM_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_NXP_FSPI=y +CONFIG_TEE=y +CONFIG_OPTEE=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/lx2160ardb_tfa_stmm_defconfig b/configs/lx2160ardb_tfa_stmm_defconfig index bd9c1e9..2d7b4af 100644 --- a/configs/lx2160ardb_tfa_stmm_defconfig +++ b/configs/lx2160ardb_tfa_stmm_defconfig @@ -49,8 +49,8 @@ CONFIG_DM_I2C=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y CONFIG_I2C_DEFAULT_BUS_NUMBER=0 CONFIG_DM_MMC=y -CONFIG_MMC_HS400_SUPPORT=y CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_HS400_SUPPORT=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y @@ -65,6 +65,7 @@ CONFIG_DM_ETH=y CONFIG_DM_MDIO=y CONFIG_E1000=y CONFIG_FSL_LS_MDIO=y +CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/microblaze-generic_defconfig b/configs/microblaze-generic_defconfig index bfbdb49..08c8885 100644 --- a/configs/microblaze-generic_defconfig +++ b/configs/microblaze-generic_defconfig @@ -12,6 +12,7 @@ CONFIG_XILINX_MICROBLAZE0_USE_BARREL=1 CONFIG_XILINX_MICROBLAZE0_USE_DIV=1 CONFIG_XILINX_MICROBLAZE0_USE_HW_MUL=1 CONFIG_DEFAULT_DEVICE_TREE="microblaze-generic" +CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_BOOTDELAY=-1 @@ -21,13 +22,12 @@ CONFIG_USE_PREBOOT=y CONFIG_PREBOOT="echo U-BOOT for ${hostname};setenv preboot;echo" CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_DISPLAY_BOARDINFO=y +CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_NOR_SUPPORT=y CONFIG_SPL_OS_BOOT=y CONFIG_SYS_OS_BASE=0x2c060000 -CONFIG_HUSH_PARSER=y -# CONFIG_AUTO_COMPLETE is not set CONFIG_SYS_PROMPT="U-Boot-mONStR> " CONFIG_CMD_IMLS=y CONFIG_CMD_SPL=y @@ -35,10 +35,7 @@ CONFIG_CMD_ASKENV=y CONFIG_CMD_GPIO=y CONFIG_CMD_SAVES=y # CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y CONFIG_CMD_TFTPPUT=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y CONFIG_CMD_JFFS2=y CONFIG_SPL_OF_CONTROL=y @@ -47,6 +44,7 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_NETCONSOLE=y CONFIG_SPL_DM=y CONFIG_XILINX_GPIO=y +CONFIG_DM_I2C=y CONFIG_LED=y CONFIG_LED_GPIO=y CONFIG_MTD=y @@ -56,6 +54,12 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_FLASH_CFI_MTD=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y +CONFIG_SPI_FLASH_ISSI=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_WINBOND=y CONFIG_PHY_ATHEROS=y CONFIG_PHY_BROADCOM=y CONFIG_PHY_DAVICOM=y @@ -71,6 +75,7 @@ CONFIG_XILINX_AXIEMAC=y CONFIG_XILINX_EMACLITE=y CONFIG_SYS_NS16550=y CONFIG_XILINX_UARTLITE=y +CONFIG_XILINX_SPI=y CONFIG_SYSRESET_GPIO=y CONFIG_SYSRESET_MICROBLAZE=y CONFIG_WDT=y diff --git a/configs/mt8512_bm1_emmc_defconfig b/configs/mt8512_bm1_emmc_defconfig index aaf59f5..c6b3ee4 100644 --- a/configs/mt8512_bm1_emmc_defconfig +++ b/configs/mt8512_bm1_emmc_defconfig @@ -9,7 +9,6 @@ CONFIG_DM_GPIO=y CONFIG_TARGET_MT8512=y CONFIG_DEFAULT_DEVICE_TREE="mt8512-bm1-emmc" CONFIG_FIT=y -CONFIG_EFI_PARTITION=y CONFIG_FIT_SIGNATURE=y CONFIG_DEFAULT_FDT_FILE="mt8512-bm1-emmc.dtb" CONFIG_SYS_PROMPT="MT8512> " @@ -19,43 +18,43 @@ CONFIG_CMD_USB=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y # CONFIG_DOS_PARTITION is not set +CONFIG_EFI_PARTITION=y CONFIG_ENV_OVERWRITE=y CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_CLK=y -CONFIG_DM_MMC=y -CONFIG_MMC_HS200_SUPPORT=y -CONFIG_MMC_MTK=y -CONFIG_PINCTRL=y -CONFIG_PINCONF=y -CONFIG_PINCTRL_MT8512=y -CONFIG_RAM=y -CONFIG_BAUDRATE=921600 CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x56000000 CONFIG_FASTBOOT_BUF_SIZE=0x1e00000 CONFIG_FASTBOOT_FLASH=y CONFIG_FASTBOOT_FLASH_MMC_DEV=0 CONFIG_FASTBOOT_MMC_BOOT1_SUPPORT=y +CONFIG_DM_MMC=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_MMC_MTK=y CONFIG_PHY=y CONFIG_PHY_MTK_TPHY=y +CONFIG_PINCTRL=y +CONFIG_PINCONF=y +CONFIG_PINCTRL_MT8512=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y +CONFIG_RAM=y +CONFIG_BAUDRATE=921600 CONFIG_DM_SERIAL=y CONFIG_MTK_SERIAL=y CONFIG_TIMER=y CONFIG_MTK_TIMER=y -CONFIG_WDT=y -CONFIG_WDT_MTK=y -CONFIG_LZO=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_DM_USB_GADGET=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_MTU3=y -# CONFIG_USB_MTU3_HOST is not set CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="MediaTek" CONFIG_USB_GADGET_VENDOR_NUM=0x0e8d CONFIG_USB_GADGET_PRODUCT_NUM=0x201c +CONFIG_WDT=y +CONFIG_WDT_MTK=y +CONFIG_LZO=y diff --git a/configs/mvebu_puzzle-m801-88f8040_defconfig b/configs/mvebu_puzzle-m801-88f8040_defconfig index d6fa829..0778149 100644 --- a/configs/mvebu_puzzle-m801-88f8040_defconfig +++ b/configs/mvebu_puzzle-m801-88f8040_defconfig @@ -3,30 +3,30 @@ CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_MVEBU=y CONFIG_SYS_TEXT_BASE=0x00000000 CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_NR_DRAM_BANKS=2 CONFIG_TARGET_MVEBU_ARMADA_8K=y CONFIG_ENV_SIZE=0x10000 -CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_ENV_OFFSET=0x1F0000 -CONFIG_NR_DRAM_BANKS=2 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_DM_GPIO=y CONFIG_DEBUG_UART_BASE=0xf0512000 CONFIG_DEBUG_UART_CLOCK=200000000 +CONFIG_DEFAULT_DEVICE_TREE="armada-8040-puzzle-m801" CONFIG_DEBUG_UART=y CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_PROMPT="Autoboot in %d seconds, to stop use 's' key\n" +CONFIG_AUTOBOOT_STOP_STR="s" +CONFIG_AUTOBOOT_KEYED_CTRLC=y CONFIG_USE_PREBOOT=y CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_AUTOBOOT_KEYED=y -CONFIG_AUTOBOOT_PROMPT="Autoboot in %d seconds, to stop use 's' key\n" -CONFIG_AUTOBOOT_STOP_STR="s" -CONFIG_AUTOBOOT_KEYED_CTRLC=y CONFIG_ARCH_EARLY_INIT_R=y CONFIG_BOARD_EARLY_INIT_F=y -# CONFIG_EFI_LOADER is not set -# CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y @@ -41,30 +41,22 @@ CONFIG_CMD_MVEBU_BUBT=y CONFIG_CMD_REGULATOR=y CONFIG_CMD_EXT4_WRITE=y CONFIG_MAC_PARTITION=y -CONFIG_DEFAULT_DEVICE_TREE="armada-8040-puzzle-m801" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_AHCI_MVEBU=y -CONFIG_DM_GPIO=y CONFIG_DM_PCA953X=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_I2C_MUX=y CONFIG_I2C_MUX_PCA954x=y -CONFIG_DM_RTC=y -CONFIG_RTC_RX8010SJ=y CONFIG_MISC=y CONFIG_DM_MMC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_XENON=y CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SPI_FLASH_SFDP_SUPPORT=y CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_MACRONIX=y -# CONFIG_SPI_FLASH_SPANSION is not set -# CONFIG_SPI_FLASH_STMICRO is not set -# CONFIG_SPI_FLASH_WINBOND is not set CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_MVPP2=y @@ -76,6 +68,8 @@ CONFIG_MVEBU_COMPHY_SUPPORT=y CONFIG_PINCTRL=y CONFIG_PINCTRL_ARMADA_8K=y CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_RTC=y +CONFIG_RTC_RX8010SJ=y CONFIG_DEBUG_UART_SHIFT=2 CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_SYS_NS16550=y @@ -84,8 +78,4 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_EHCI_HCD=y -# CONFIG_USB_HOST_ETHER is not set -# CONFIG_USB_ETHER_ASIX is not set -# CONFIG_USB_ETHER_MCS7830 is not set -# CONFIG_USB_ETHER_RTL8152 is not set -# CONFIG_USB_ETHER_SMSC95XX is not set +# CONFIG_EFI_LOADER is not set diff --git a/configs/mx23evk_defconfig b/configs/mx23evk_defconfig index 73d7e9b..0e3d977 100644 --- a/configs/mx23evk_defconfig +++ b/configs/mx23evk_defconfig @@ -11,7 +11,6 @@ CONFIG_SPL_TEXT_BASE=0x00001000 CONFIG_TARGET_MX23EVK=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL=y -# CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_ARCH_MISC_INIT=y @@ -22,7 +21,6 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_BMP=y CONFIG_CMD_CACHE=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y @@ -37,8 +35,6 @@ CONFIG_CONS_INDEX=0 CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y -# CONFIG_VIDEO is not set CONFIG_SPLASH_SCREEN=y CONFIG_VIDEO_BMP_GZIP=y -CONFIG_VIDEO_BMP_RLE8=y CONFIG_OF_LIBFDT=y diff --git a/configs/mx51evk_defconfig b/configs/mx51evk_defconfig index 72b1417..343816f 100644 --- a/configs/mx51evk_defconfig +++ b/configs/mx51evk_defconfig @@ -39,5 +39,4 @@ CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_SMSC95XX=y CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_SPLASH_SCREEN=y -CONFIG_VIDEO_BMP_RLE8=y CONFIG_OF_LIBFDT=y diff --git a/configs/mx53loco_defconfig b/configs/mx53loco_defconfig index a97c750..a1096a7 100644 --- a/configs/mx53loco_defconfig +++ b/configs/mx53loco_defconfig @@ -40,5 +40,4 @@ CONFIG_USB_ETHER_MCS7830=y CONFIG_USB_ETHER_SMSC95XX=y CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_SPLASH_SCREEN=y -CONFIG_VIDEO_BMP_RLE8=y CONFIG_OF_LIBFDT=y diff --git a/configs/mx6sxsabresd_defconfig b/configs/mx6sxsabresd_defconfig index a33ec49..0e672ef 100644 --- a/configs/mx6sxsabresd_defconfig +++ b/configs/mx6sxsabresd_defconfig @@ -12,7 +12,6 @@ CONFIG_NXP_BOARD_REVISION=y CONFIG_DEFAULT_DEVICE_TREE="imx6sx-sdb" CONFIG_SUPPORT_RAW_INITRD=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sxsabresd/imximage.cfg" -# CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y @@ -27,7 +26,6 @@ CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y -CONFIG_CMD_BMP=y CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y CONFIG_CMD_EXT2=y @@ -73,7 +71,5 @@ CONFIG_DM_USB=y CONFIG_USB_STORAGE=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y -# CONFIG_VIDEO is not set CONFIG_SPLASH_SCREEN=y CONFIG_SPLASH_SCREEN_ALIGN=y -CONFIG_VIDEO_BMP_RLE8=y diff --git a/configs/mx7dsabresd_defconfig b/configs/mx7dsabresd_defconfig index 9b4bbf3..29f3afd 100644 --- a/configs/mx7dsabresd_defconfig +++ b/configs/mx7dsabresd_defconfig @@ -12,7 +12,6 @@ CONFIG_DEFAULT_DEVICE_TREE="imx7d-sdb" CONFIG_DISTRO_DEFAULTS=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7dsabresd/imximage.cfg" CONFIG_BOOTCOMMAND="run finduuid; run distro_bootcmd" -# CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y # CONFIG_CMD_BOOTD is not set # CONFIG_BOOTM_NETBSD is not set @@ -31,7 +30,6 @@ CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_USB_MASS_STORAGE=y -CONFIG_CMD_BMP=y CONFIG_CMD_CACHE=y CONFIG_CMD_PMIC=y CONFIG_CMD_REGULATOR=y @@ -84,8 +82,6 @@ CONFIG_CI_UDC=y CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y -# CONFIG_VIDEO is not set CONFIG_SPLASH_SCREEN=y CONFIG_SPLASH_SCREEN_ALIGN=y -CONFIG_VIDEO_BMP_RLE8=y CONFIG_ERRNO_STR=y diff --git a/configs/mx7dsabresd_qspi_defconfig b/configs/mx7dsabresd_qspi_defconfig index fa5deb8..bf0e2ce 100644 --- a/configs/mx7dsabresd_qspi_defconfig +++ b/configs/mx7dsabresd_qspi_defconfig @@ -12,7 +12,6 @@ CONFIG_DEFAULT_DEVICE_TREE="imx7d-sdb-qspi" CONFIG_DISTRO_DEFAULTS=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7dsabresd/imximage.cfg" CONFIG_BOOTCOMMAND="run finduuid; run distro_bootcmd" -# CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y # CONFIG_CMD_BOOTD is not set # CONFIG_BOOTM_NETBSD is not set @@ -31,7 +30,6 @@ CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_USB_MASS_STORAGE=y -CONFIG_CMD_BMP=y CONFIG_CMD_CACHE=y CONFIG_CMD_PMIC=y CONFIG_CMD_REGULATOR=y @@ -91,8 +89,6 @@ CONFIG_CI_UDC=y CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y -# CONFIG_VIDEO is not set CONFIG_SPLASH_SCREEN=y CONFIG_SPLASH_SCREEN_ALIGN=y -CONFIG_VIDEO_BMP_RLE8=y CONFIG_ERRNO_STR=y diff --git a/configs/octeontx2_95xx_defconfig b/configs/octeontx2_95xx_defconfig index e37c837..591caa7 100644 --- a/configs/octeontx2_95xx_defconfig +++ b/configs/octeontx2_95xx_defconfig @@ -86,6 +86,8 @@ CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_DM_ETH=y +CONFIG_NET_OCTEONTX2=y +CONFIG_OCTEONTX_SMI=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/octeontx2_96xx_defconfig b/configs/octeontx2_96xx_defconfig index 403ea51..0a8888a 100644 --- a/configs/octeontx2_96xx_defconfig +++ b/configs/octeontx2_96xx_defconfig @@ -99,6 +99,8 @@ CONFIG_DM_ETH=y CONFIG_E1000=y CONFIG_E1000_SPI=y CONFIG_CMD_E1000=y +CONFIG_NET_OCTEONTX2=y +CONFIG_OCTEONTX_SMI=y CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI=y diff --git a/configs/octeontx_81xx_defconfig b/configs/octeontx_81xx_defconfig index 78efcf5..c006a14 100644 --- a/configs/octeontx_81xx_defconfig +++ b/configs/octeontx_81xx_defconfig @@ -100,6 +100,8 @@ CONFIG_DM_ETH=y CONFIG_E1000=y CONFIG_E1000_SPI=y CONFIG_CMD_E1000=y +CONFIG_NET_OCTEONTX=y +CONFIG_OCTEONTX_SMI=y CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI=y diff --git a/configs/octeontx_83xx_defconfig b/configs/octeontx_83xx_defconfig index f5b0528..86b4bc5 100644 --- a/configs/octeontx_83xx_defconfig +++ b/configs/octeontx_83xx_defconfig @@ -97,6 +97,8 @@ CONFIG_DM_ETH=y CONFIG_E1000=y CONFIG_E1000_SPI=y CONFIG_CMD_E1000=y +CONFIG_NET_OCTEONTX=y +CONFIG_OCTEONTX_SMI=y CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI=y diff --git a/configs/picosam9g45_defconfig b/configs/picosam9g45_defconfig index 081c2a9..915c2ba 100644 --- a/configs/picosam9g45_defconfig +++ b/configs/picosam9g45_defconfig @@ -18,7 +18,6 @@ CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9M10G45,SYS_USE_MMC" CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/mmcblk0p2 rw rootwait" -# CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_BOARD_EARLY_INIT_F=y @@ -44,7 +43,6 @@ CONFIG_ATMEL_USART=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y -# CONFIG_LCD is not set CONFIG_WDT=y CONFIG_WDT_AT91=y CONFIG_OF_LIBFDT=y diff --git a/configs/pine_h64_defconfig b/configs/pine_h64_defconfig index 07ad31e..2fa66f3 100644 --- a/configs/pine_h64_defconfig +++ b/configs/pine_h64_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_SUNXI=y CONFIG_SPL=y CONFIG_MACH_SUN50I_H6=y CONFIG_SUNXI_DRAM_H6_LPDDR3=y +CONFIG_MACPWR="PC16" CONFIG_MMC0_CD_PIN="PF6" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_USB3_VBUS_PIN="PL5" @@ -11,6 +12,5 @@ CONFIG_SPL_SPI_SUNXI=y CONFIG_DEFAULT_DEVICE_TREE="sun50i-h6-pine-h64" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SUN8I_EMAC=y -CONFIG_MACPWR="PC16" CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/px30-core-ctouch2-px30_defconfig b/configs/px30-core-ctouch2-px30_defconfig new file mode 100644 index 0000000..d64f05d --- /dev/null +++ b/configs/px30-core-ctouch2-px30_defconfig @@ -0,0 +1,108 @@ +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SYS_TEXT_BASE=0x00200000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_SPL_TEXT_BASE=0x00000000 +CONFIG_ROCKCHIP_PX30=y +CONFIG_TARGET_PX30_CORE=y +CONFIG_DEBUG_UART_CHANNEL=1 +CONFIG_TPL_LIBGENERIC_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL_STACK_R_ADDR=0x600000 +CONFIG_DEBUG_UART_BASE=0xFF160000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEFAULT_DEVICE_TREE="px30-px30-core-ctouch2" +CONFIG_DEBUG_UART=y +CONFIG_TPL_SYS_MALLOC_F_LEN=0x600 +# CONFIG_ANDROID_BOOT_IMAGE is not set +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_LOAD_FIT=y +# CONFIG_CONSOLE_MUX is not set +CONFIG_DEFAULT_FDT_FILE="rockchip/px30-px30-core-ctouch2.dtb" +CONFIG_MISC_INIT_R=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_BOOTROM_SUPPORT=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_STACK_R=y +# CONFIG_TPL_BANNER_PRINT is not set +CONFIG_SPL_CRC32_SUPPORT=y +CONFIG_SPL_ATF=y +# CONFIG_TPL_FRAMEWORK is not set +# CONFIG_CMD_BOOTD is not set +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_LZMADEC is not set +# CONFIG_CMD_UNZIP is not set +CONFIG_CMD_GPT=y +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +# CONFIG_CMD_ITEST is not set +# CONFIG_CMD_SETEXPR is not set +# CONFIG_CMD_MISC is not set +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_ISO_PARTITION is not set +CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64 +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_FASTBOOT_BUF_ADDR=0x800800 +CONFIG_FASTBOOT_BUF_SIZE=0x04000000 +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y +CONFIG_ROCKCHIP_OTP=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_PINCTRL=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_PWM=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_TPL_RAM=y +CONFIG_ROCKCHIP_SDRAM_COMMON=y +CONFIG_DM_RESET=y +CONFIG_DM_RNG=y +CONFIG_RNG_ROCKCHIP=y +# CONFIG_SPECIFY_CONSOLE_INDEX is not set +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_SOUND=y +CONFIG_SYSRESET=y +CONFIG_DM_THERMAL=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DWC2_OTG=y +CONFIG_DM_VIDEO=y +CONFIG_DISPLAY=y +CONFIG_LCD=y +CONFIG_SPL_TINY_MEMSET=y +CONFIG_TPL_TINY_MEMSET=y +CONFIG_LZO=y +CONFIG_ERRNO_STR=y diff --git a/configs/px30-core-edimm2.2-px30_defconfig b/configs/px30-core-edimm2.2-px30_defconfig new file mode 100644 index 0000000..50a9a15 --- /dev/null +++ b/configs/px30-core-edimm2.2-px30_defconfig @@ -0,0 +1,108 @@ +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SYS_TEXT_BASE=0x00200000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_SPL_TEXT_BASE=0x00000000 +CONFIG_ROCKCHIP_PX30=y +CONFIG_TARGET_PX30_CORE=y +CONFIG_DEBUG_UART_CHANNEL=1 +CONFIG_TPL_LIBGENERIC_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL_STACK_R_ADDR=0x600000 +CONFIG_DEBUG_UART_BASE=0xFF160000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEFAULT_DEVICE_TREE="px30-px30-core-edimm2.2" +CONFIG_DEBUG_UART=y +CONFIG_TPL_SYS_MALLOC_F_LEN=0x600 +# CONFIG_ANDROID_BOOT_IMAGE is not set +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_LOAD_FIT=y +# CONFIG_CONSOLE_MUX is not set +CONFIG_DEFAULT_FDT_FILE="rockchip/px30-px30-core-edimm2.2.dtb" +CONFIG_MISC_INIT_R=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_BOOTROM_SUPPORT=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_STACK_R=y +# CONFIG_TPL_BANNER_PRINT is not set +CONFIG_SPL_CRC32_SUPPORT=y +CONFIG_SPL_ATF=y +# CONFIG_TPL_FRAMEWORK is not set +# CONFIG_CMD_BOOTD is not set +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_LZMADEC is not set +# CONFIG_CMD_UNZIP is not set +CONFIG_CMD_GPT=y +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +# CONFIG_CMD_ITEST is not set +# CONFIG_CMD_SETEXPR is not set +# CONFIG_CMD_MISC is not set +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_ISO_PARTITION is not set +CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64 +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_FASTBOOT_BUF_ADDR=0x800800 +CONFIG_FASTBOOT_BUF_SIZE=0x04000000 +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y +CONFIG_ROCKCHIP_OTP=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_PINCTRL=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_PWM=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_TPL_RAM=y +CONFIG_ROCKCHIP_SDRAM_COMMON=y +CONFIG_DM_RESET=y +CONFIG_DM_RNG=y +CONFIG_RNG_ROCKCHIP=y +# CONFIG_SPECIFY_CONSOLE_INDEX is not set +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_SOUND=y +CONFIG_SYSRESET=y +CONFIG_DM_THERMAL=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DWC2_OTG=y +CONFIG_DM_VIDEO=y +CONFIG_DISPLAY=y +CONFIG_LCD=y +CONFIG_SPL_TINY_MEMSET=y +CONFIG_TPL_TINY_MEMSET=y +CONFIG_LZO=y +CONFIG_ERRNO_STR=y diff --git a/configs/rock-pi-n8-rk3288_defconfig b/configs/rock-pi-n8-rk3288_defconfig index e5bc035..d1d1613 100644 --- a/configs/rock-pi-n8-rk3288_defconfig +++ b/configs/rock-pi-n8-rk3288_defconfig @@ -14,9 +14,7 @@ CONFIG_DEFAULT_DEVICE_TREE="rk3288-rock-pi-n8" CONFIG_DEBUG_UART=y # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_USE_PREBOOT=y -CONFIG_DEFAULT_FDT_FILE="rk3288-rock-pi-n8.dtb" CONFIG_SILENT_CONSOLE=y -# CONFIG_CONSOLE_MUX is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 diff --git a/configs/rock960-rk3399_defconfig b/configs/rock960-rk3399_defconfig index c3ce27e..5d893de 100644 --- a/configs/rock960-rk3399_defconfig +++ b/configs/rock960-rk3399_defconfig @@ -3,12 +3,12 @@ CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_ROCKCHIP_RK3399=y -CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000 CONFIG_TARGET_ROCK960_RK3399=y CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEFAULT_DEVICE_TREE="rk3399-rock960" CONFIG_DEBUG_UART=y +CONFIG_USE_PREBOOT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock960.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_MISC_INIT_R=y @@ -41,6 +41,8 @@ CONFIG_MMC_SDHCI_ROCKCHIP=y CONFIG_DM_ETH=y CONFIG_NVME=y CONFIG_PCI=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_TYPEC=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y CONFIG_REGULATOR_RK8XX=y @@ -54,10 +56,11 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y CONFIG_USB_DWC3=y -CONFIG_ROCKCHIP_USB2_PHY=y +CONFIG_DM_KEYBOARD=y CONFIG_USB_KEYBOARD=y -CONFIG_USB_GADGET=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_ASIX88179=y diff --git a/configs/sandbox64_defconfig b/configs/sandbox64_defconfig index e9928d5..23a47d1 100644 --- a/configs/sandbox64_defconfig +++ b/configs/sandbox64_defconfig @@ -69,6 +69,8 @@ CONFIG_CMD_TIME=y CONFIG_CMD_TIMER=y CONFIG_CMD_SOUND=y CONFIG_CMD_QFW=y +CONFIG_CMD_PSTORE=y +CONFIG_CMD_PSTORE_MEM_ADDR=0x3000000 CONFIG_CMD_BOOTSTAGE=y CONFIG_CMD_PMIC=y CONFIG_CMD_REGULATOR=y @@ -80,8 +82,6 @@ CONFIG_CMD_CBFS=y CONFIG_CMD_CRAMFS=y CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_MTDPARTS=y -CONFIG_CMD_PSTORE=y -CONFIG_CMD_PSTORE_MEM_ADDR=0x3000000 CONFIG_MAC_PARTITION=y CONFIG_AMIGA_PARTITION=y CONFIG_OF_CONTROL=y diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig index 3043208..8e2ef24 100644 --- a/configs/sandbox_defconfig +++ b/configs/sandbox_defconfig @@ -82,6 +82,8 @@ CONFIG_CMD_TIME=y CONFIG_CMD_TIMER=y CONFIG_CMD_SOUND=y CONFIG_CMD_QFW=y +CONFIG_CMD_PSTORE=y +CONFIG_CMD_PSTORE_MEM_ADDR=0x3000000 CONFIG_CMD_BOOTSTAGE=y CONFIG_CMD_PMIC=y CONFIG_CMD_REGULATOR=y @@ -94,8 +96,6 @@ CONFIG_CMD_CRAMFS=y CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_SQUASHFS=y CONFIG_CMD_MTDPARTS=y -CONFIG_CMD_PSTORE=y -CONFIG_CMD_PSTORE_MEM_ADDR=0x3000000 CONFIG_MAC_PARTITION=y CONFIG_AMIGA_PARTITION=y CONFIG_OF_CONTROL=y diff --git a/configs/sandbox_spl_defconfig b/configs/sandbox_spl_defconfig index 1d49e81..d47a625 100644 --- a/configs/sandbox_spl_defconfig +++ b/configs/sandbox_spl_defconfig @@ -22,11 +22,12 @@ CONFIG_BOOTSTAGE_STASH=y CONFIG_BOOTSTAGE_STASH_SIZE=0x4096 CONFIG_CONSOLE_RECORD=y CONFIG_CONSOLE_RECORD_OUT_SIZE=0x1000 -CONFIG_SILENT_CONSOLE=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_HANDOFF=y CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_ENV_SUPPORT=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_RTC_SUPPORT=y CONFIG_CMD_CPU=y CONFIG_CMD_LICENSE=y CONFIG_CMD_BOOTZ=y @@ -105,6 +106,7 @@ CONFIG_ADC_SANDBOX=y CONFIG_AXI=y CONFIG_AXI_SANDBOX=y CONFIG_CLK=y +CONFIG_SPL_CLK=y CONFIG_CPU=y CONFIG_DM_DEMO=y CONFIG_DM_DEMO_SIMPLE=y @@ -120,7 +122,6 @@ CONFIG_I2C_CROS_EC_LDO=y CONFIG_DM_I2C_GPIO=y CONFIG_SYS_I2C_SANDBOX=y CONFIG_I2C_MUX=y -CONFIG_SPL_I2C_MUX=y CONFIG_I2C_ARB_GPIO_CHALLENGE=y CONFIG_CROS_EC_KEYB=y CONFIG_I8042_KEYB=y @@ -187,6 +188,7 @@ CONFIG_REMOTEPROC_SANDBOX=y CONFIG_DM_RESET=y CONFIG_SANDBOX_RESET=y CONFIG_DM_RTC=y +CONFIG_SPL_DM_RTC=y CONFIG_SANDBOX_SERIAL=y CONFIG_SOUND=y CONFIG_SOUND_SANDBOX=y @@ -221,5 +223,6 @@ CONFIG_TPM=y CONFIG_LZ4=y CONFIG_ERRNO_STR=y CONFIG_UNIT_TEST=y +CONFIG_SPL_UNIT_TEST=y CONFIG_UT_TIME=y CONFIG_UT_DM=y diff --git a/configs/sansa_fuze_plus_defconfig b/configs/sansa_fuze_plus_defconfig index 7a41f99..b0b8926 100644 --- a/configs/sansa_fuze_plus_defconfig +++ b/configs/sansa_fuze_plus_defconfig @@ -13,7 +13,6 @@ CONFIG_SPL=y CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyAMA0,115200n8 " -# CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_ARCH_MISC_INIT=y @@ -44,5 +43,4 @@ CONFIG_USB_GADGET=y CONFIG_CI_UDC=y CONFIG_USB_ETHER=y CONFIG_USB_ETH_CDC=y -# CONFIG_VIDEO is not set CONFIG_OF_LIBFDT=y diff --git a/configs/socfpga_agilex_defconfig b/configs/socfpga_agilex_defconfig index 3a9b3b5..95e5fb7 100644 --- a/configs/socfpga_agilex_defconfig +++ b/configs/socfpga_agilex_defconfig @@ -11,8 +11,8 @@ CONFIG_SPL_TEXT_BASE=0xFFE00000 CONFIG_TARGET_SOCFPGA_AGILEX_SOCDK=y CONFIG_IDENT_STRING="socfpga_agilex" CONFIG_SPL_FS_FAT=y -CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex_socdk" # CONFIG_PSCI_RESET is not set +CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex_socdk" CONFIG_BOOTDELAY=5 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="earlycon" diff --git a/configs/socfpga_stratix10_defconfig b/configs/socfpga_stratix10_defconfig index a48388f..e463300 100644 --- a/configs/socfpga_stratix10_defconfig +++ b/configs/socfpga_stratix10_defconfig @@ -11,10 +11,10 @@ CONFIG_SPL_TEXT_BASE=0xFFE00000 CONFIG_TARGET_SOCFPGA_STRATIX10_SOCDK=y CONFIG_IDENT_STRING="socfpga_stratix10" CONFIG_SPL_FS_FAT=y +# CONFIG_PSCI_RESET is not set CONFIG_DEFAULT_DEVICE_TREE="socfpga_stratix10_socdk" CONFIG_OPTIMIZE_INLINING=y CONFIG_SPL_OPTIMIZE_INLINING=y -# CONFIG_PSCI_RESET is not set CONFIG_BOOTDELAY=5 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="earlycon" diff --git a/configs/syzygy_hub_defconfig b/configs/syzygy_hub_defconfig index 8f69006..276c476 100644 --- a/configs/syzygy_hub_defconfig +++ b/configs/syzygy_hub_defconfig @@ -9,6 +9,8 @@ CONFIG_SPL_STACK_R_ADDR=0x200000 CONFIG_SPL=y CONFIG_DEBUG_UART_BASE=0xe0000000 CONFIG_DEBUG_UART_CLOCK=50000000 +CONFIG_ZYNQ_MAC_IN_EEPROM=y +CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0xFA CONFIG_DEFAULT_DEVICE_TREE="zynq-syzygy-hub" CONFIG_DEBUG_UART=y CONFIG_DISTRO_DEFAULTS=y @@ -40,7 +42,6 @@ CONFIG_FPGA_XILINX=y CONFIG_FPGA_ZYNQPL=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_CADENCE=y -CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0xFA CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y CONFIG_PHY_MARVELL=y diff --git a/configs/teres_i_defconfig b/configs/teres_i_defconfig index ee07f86..a5d9fb0 100644 --- a/configs/teres_i_defconfig +++ b/configs/teres_i_defconfig @@ -7,8 +7,8 @@ CONFIG_DRAM_ZQ=3881949 CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_USB1_VBUS_PIN="PL7" CONFIG_I2C0_ENABLE=y -CONFIG_PREBOOT="setenv usb_pgood_delay 2000; usb start" CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-teres-i" +CONFIG_PREBOOT="setenv usb_pgood_delay 2000; usb start" CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_PWM=y diff --git a/configs/xfi3_defconfig b/configs/xfi3_defconfig index 9d895f8..c49319c 100644 --- a/configs/xfi3_defconfig +++ b/configs/xfi3_defconfig @@ -13,7 +13,6 @@ CONFIG_SPL=y CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyAMA0,115200n8 " -# CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_ARCH_MISC_INIT=y @@ -41,5 +40,4 @@ CONFIG_USB_GADGET=y CONFIG_CI_UDC=y CONFIG_USB_ETHER=y CONFIG_USB_ETH_CDC=y -# CONFIG_VIDEO is not set CONFIG_OF_LIBFDT=y diff --git a/configs/xilinx_versal_mini_defconfig b/configs/xilinx_versal_mini_defconfig index e72cef9..427268b 100644 --- a/configs/xilinx_versal_mini_defconfig +++ b/configs/xilinx_versal_mini_defconfig @@ -7,7 +7,7 @@ CONFIG_NR_DRAM_BANKS=3 CONFIG_ENV_SIZE=0x80 CONFIG_SYS_MALLOC_LEN=0x2000 CONFIG_SYS_MEM_RSVD_FOR_MMU=y -CONFIG_COUNTER_FREQUENCY=2720000 +CONFIG_COUNTER_FREQUENCY=100000000 # CONFIG_PSCI_RESET is not set CONFIG_DEFAULT_DEVICE_TREE="versal-mini" # CONFIG_EXPERT is not set diff --git a/configs/xilinx_versal_mini_emmc0_defconfig b/configs/xilinx_versal_mini_emmc0_defconfig index b5c3ae4..8837987 100644 --- a/configs/xilinx_versal_mini_emmc0_defconfig +++ b/configs/xilinx_versal_mini_emmc0_defconfig @@ -6,7 +6,7 @@ CONFIG_SYS_TEXT_BASE=0x10000 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x80 CONFIG_SYS_MALLOC_LEN=0x80000 -CONFIG_COUNTER_FREQUENCY=2720000 +CONFIG_COUNTER_FREQUENCY=100000000 # CONFIG_PSCI_RESET is not set CONFIG_DEFAULT_DEVICE_TREE="versal-mini-emmc0" # CONFIG_EXPERT is not set diff --git a/configs/xilinx_versal_mini_emmc1_defconfig b/configs/xilinx_versal_mini_emmc1_defconfig index 871f8cc..b07dc04 100644 --- a/configs/xilinx_versal_mini_emmc1_defconfig +++ b/configs/xilinx_versal_mini_emmc1_defconfig @@ -6,7 +6,7 @@ CONFIG_SYS_TEXT_BASE=0x10000 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x80 CONFIG_SYS_MALLOC_LEN=0x80000 -CONFIG_COUNTER_FREQUENCY=2720000 +CONFIG_COUNTER_FREQUENCY=100000000 # CONFIG_PSCI_RESET is not set CONFIG_DEFAULT_DEVICE_TREE="versal-mini-emmc1" # CONFIG_EXPERT is not set diff --git a/configs/xilinx_versal_virt_defconfig b/configs/xilinx_versal_virt_defconfig index 5175571..7291c51 100644 --- a/configs/xilinx_versal_virt_defconfig +++ b/configs/xilinx_versal_virt_defconfig @@ -4,8 +4,9 @@ CONFIG_ARCH_VERSAL=y CONFIG_SYS_TEXT_BASE=0x8000000 CONFIG_SYS_MALLOC_F_LEN=0x100000 CONFIG_DM_GPIO=y +CONFIG_CMD_FRU=y CONFIG_DEFINE_TCM_OCM_MMAP=y -CONFIG_COUNTER_FREQUENCY=62500000 +CONFIG_COUNTER_FREQUENCY=100000000 CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -27,6 +28,7 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_MTD=y +CONFIG_CMD_SF_TEST=y CONFIG_CMD_USB=y CONFIG_CMD_TFTPPUT=y CONFIG_CMD_CACHE=y @@ -51,6 +53,7 @@ CONFIG_MISC=y CONFIG_I2C_EEPROM=y CONFIG_SYS_I2C_EEPROM_ADDR=0x0 CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0 +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_IO_VOLTAGE=y CONFIG_MMC_UHS_SUPPORT=y CONFIG_MMC_HS400_SUPPORT=y @@ -83,6 +86,7 @@ CONFIG_PL01X_SERIAL=y CONFIG_XILINX_UARTLITE=y CONFIG_SPI=y CONFIG_DM_SPI=y +CONFIG_ZYNQ_SPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_DM_USB_GADGET=y diff --git a/configs/xilinx_zynq_virt_defconfig b/configs/xilinx_zynq_virt_defconfig index b127945..da84c01 100644 --- a/configs/xilinx_zynq_virt_defconfig +++ b/configs/xilinx_zynq_virt_defconfig @@ -6,6 +6,8 @@ CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000 CONFIG_DM_GPIO=y CONFIG_SPL_STACK_R_ADDR=0x200000 CONFIG_SPL=y +CONFIG_CMD_FRU=y +CONFIG_CMD_ZYNQ_AES=y CONFIG_DEFAULT_DEVICE_TREE="zynq-zc706" CONFIG_DISTRO_DEFAULTS=y CONFIG_SYS_CUSTOM_LDSCRIPT=y @@ -40,6 +42,7 @@ CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_MTD=y CONFIG_CMD_NAND_LOCK_UNLOCK=y +CONFIG_CMD_SF_TEST=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TFTPPUT=y @@ -49,7 +52,7 @@ CONFIG_CMD_MTDPARTS=y CONFIG_CMD_MTDPARTS_SPREAD=y CONFIG_CMD_MTDPARTS_SHOW_NET_SIZES=y CONFIG_CMD_UBI=y -CONFIG_OF_LIST="zynq-zc702 zynq-zc706 zynq-zc770-xm010 zynq-zc770-xm011 zynq-zc770-xm011-x16 zynq-zc770-xm012 zynq-zc770-xm013 zynq-cc108 zynq-microzed zynq-minized zynq-picozed zynq-zed zynq-zturn zynq-zybo zynq-zybo-z7 zynq-dlc20-rev1.0" +CONFIG_OF_LIST="zynq-zc702 zynq-zc706 zynq-zc770-xm010 zynq-zc770-xm011 zynq-zc770-xm011-x16 zynq-zc770-xm012 zynq-zc770-xm013 zynq-cc108 zynq-microzed zynq-minized zynq-picozed zynq-zed zynq-zturn zynq-zturn-v5 zynq-zybo zynq-zybo-z7 zynq-dlc20-rev1.0" CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y @@ -88,6 +91,8 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_SST=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_PHY_MARVELL=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_PHY_REALTEK=y CONFIG_PHY_XILINX=y CONFIG_MII=y diff --git a/configs/xilinx_zynqmp_virt_defconfig b/configs/xilinx_zynqmp_virt_defconfig index 264b662..0c816de 100644 --- a/configs/xilinx_zynqmp_virt_defconfig +++ b/configs/xilinx_zynqmp_virt_defconfig @@ -7,6 +7,9 @@ CONFIG_DM_GPIO=y CONFIG_SPL=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y +CONFIG_ZYNQ_MAC_IN_EEPROM=y +CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0x20 +CONFIG_CMD_FRU=y CONFIG_ZYNQMP_USB=y CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu100-revC" CONFIG_AHCI=y @@ -19,6 +22,7 @@ CONFIG_USE_PREBOOT=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_EARLY_INIT_R=y +CONFIG_SPL_FPGA=y CONFIG_SPL_OS_BOOT=y CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y @@ -45,10 +49,12 @@ CONFIG_CMD_MTD=y CONFIG_CMD_NAND_LOCK_UNLOCK=y CONFIG_CMD_POWEROFF=y CONFIG_CMD_SDRAM=y +CONFIG_CMD_SF_TEST=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y CONFIG_CMD_TIMER=y CONFIG_CMD_EXT4_WRITE=y @@ -58,6 +64,7 @@ CONFIG_CMD_MTDPARTS_SHOW_NET_SIZES=y CONFIG_CMD_UBI=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIST="avnet-ultra96-rev1 zynqmp-a2197-revA zynqmp-e-a2197-00-revA zynqmp-g-a2197-00-revA zynqmp-m-a2197-01-revA zynqmp-m-a2197-02-revA zynqmp-m-a2197-03-revA zynqmp-p-a2197-00-revA zynqmp-zc1232-revA zynqmp-zc1254-revA zynqmp-zc1751-xm015-dc1 zynqmp-zc1751-xm016-dc2 zynqmp-zc1751-xm017-dc3 zynqmp-zc1751-xm018-dc4 zynqmp-zc1751-xm019-dc5 zynqmp-zcu100-revC zynqmp-zcu102-rev1.1 zynqmp-zcu102-rev1.0 zynqmp-zcu102-revA zynqmp-zcu102-revB zynqmp-zcu104-revA zynqmp-zcu104-revC zynqmp-zcu106-revA zynqmp-zcu111-revA zynqmp-zcu1275-revA zynqmp-zcu1275-revB zynqmp-zcu1285-revA zynqmp-zcu208-revA zynqmp-zcu216-revA zynqmp-topic-miamimp-xilinx-xdp-v1r1" +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names interrupt-parent interrupts iommus power-domains" CONFIG_ENV_IS_NOWHERE=y CONFIG_ENV_IS_IN_FAT=y CONFIG_ENV_IS_IN_NAND=y @@ -88,7 +95,6 @@ CONFIG_LED=y CONFIG_LED_GPIO=y CONFIG_MISC=y CONFIG_I2C_EEPROM=y -CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0x20 CONFIG_SYS_I2C_EEPROM_ADDR=0x0 CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0 CONFIG_SUPPORT_EMMC_BOOT=y diff --git a/doc/api/getopt.rst b/doc/api/getopt.rst new file mode 100644 index 0000000..773f79a --- /dev/null +++ b/doc/api/getopt.rst @@ -0,0 +1,8 @@ +.. SPDX-License-Identifier: GPL-2.0+ +.. Copyright (C) 2020 Sean Anderson <seanga2@gmail.com> + +Option Parsing +============== + +.. kernel-doc:: include/getopt.h + :internal: diff --git a/doc/api/index.rst b/doc/api/index.rst index 787b677..ae4a1b6 100644 --- a/doc/api/index.rst +++ b/doc/api/index.rst @@ -8,6 +8,7 @@ U-Boot API documentation dfu efi + getopt linker_lists pinctrl rng diff --git a/doc/board/index.rst b/doc/board/index.rst index 63935ab..4b6a996 100644 --- a/doc/board/index.rst +++ b/doc/board/index.rst @@ -15,6 +15,7 @@ Board-specific doc freescale/index google/index intel/index + kontron/index renesas/index rockchip/index sifive/index diff --git a/doc/board/kontron/index.rst b/doc/board/kontron/index.rst new file mode 100644 index 0000000..543b22e --- /dev/null +++ b/doc/board/kontron/index.rst @@ -0,0 +1,9 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Kontron +======= + +.. toctree:: + :maxdepth: 2 + + sl28 diff --git a/doc/board/kontron/sl28.rst b/doc/board/kontron/sl28.rst new file mode 100644 index 0000000..e458fbc --- /dev/null +++ b/doc/board/kontron/sl28.rst @@ -0,0 +1,160 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Summary +======= + +The Kontron SMARC-sAL28 board is a TSN-enabled dual-core ARM A72 +processor module with an on-chip 6-port TSN switch and a 3D GPU. + + +Quickstart +========== + +Compile U-Boot +-------------- + +Configure and compile the binary:: + + $ make kontron_sl28_defconfig + $ CROSS_COMPILE=aarch64-linux-gnu make + +Copy u-boot.rom to a TFTP server. + +Install the bootloader on the board +----------------------------------- + +Please note, this bootloader doesn't support the builtin watchdog (yet), +therefore you have to disable it, see below. Otherwise you'll end up in +the failsafe bootloader on every reset:: + + > tftp path/to/u-boot.rom + > sf probe 0 + > sf update $fileaddr 0x210000 $filesize + +The board is fully failsafe, you can't break anything. But because you've +disabled the builtin watchdog you might have to manually enter failsafe +mode by asserting the ``FORCE_RECOV#`` line during board reset. + +Disable the builtin watchdog +---------------------------- + +- boot into the failsafe bootloader, either by asserting the + ``FORCE_RECOV#`` line or if you still have the original bootloader + installed you can use the command:: + + > wdt dev cpld_watchdog@4a; wdt expire 1 + +- in the failsafe bootloader use the "sl28 nvm" command to disable + the automatic start of the builtin watchdog:: + + > sl28 nvm 0008 + +- power-cycle the board + + +Useful I2C tricks +================= + +The board has a board management controller which is not supported in +u-boot (yet). But you can use the i2c command to access it. + +- reset into failsafe bootloader:: + + > i2c mw 4a 5.1 0; i2c mw 4a 6.1 6b; i2c mw 4a 4.1 42 + +- read board management controller version:: + + > i2c md 4a 3.1 1 + + +Non-volatile Board Configuration Bits +===================================== + +The board has 16 configuration bits which are stored in the CPLD and are +non-volatile. These can be changed by the `sl28 nvm` command. + +=== =============================================================== +Bit Description +=== =============================================================== + 0 Power-on inhibit + 1 Enable eMMC boot + 2 Enable watchdog by default + 3 Disable failsafe watchdog by default + 4 Clock generator selection bit 0 + 5 Clock generator selection bit 1 + 6 Disable CPU SerDes clock #2 and PCIe-A clock output + 7 Disable PCIe-B and PCIe-C clock output + 8 Keep onboard PHYs in reset + 9 Keep USB hub in reset + 10 Keep eDP-to-LVDS converter in reset + 11 Enable I2C stuck recovery on I2C PM and I2C GP busses + 12 Enable automatic onboard PHY H/W reset + 13 reserved + 14 Used by the RCW to determine boot source + 15 Used by the RCW to determine boot source +=== =============================================================== + +Please note, that if the board is in failsafe mode, the bits will have the +factory defaults, ie. all bits are off. + +Power-On Inhibit +---------------- + +If this is set, the board doesn't automatically turn on when power is +applied. Instead, the user has to either toggle the ``PWR_BTN#`` line or +use any other wake-up source such as RTC alarm or Wake-on-LAN. + +eMMC Boot +--------- + +If this is set, the RCW will be fetched from the on-board eMMC at offset +1MiB. For further details, have a look at the `Reset Configuration Word +Documentation`_. + +Watchdog +-------- + +By default, the CPLD watchdog is enabled in failsafe mode. Using bits 2 and +3, the user can change its mode or disable it altogether. + +===== ===== =============================== +Bit 2 Bit 3 Description +===== ===== =============================== + 0 0 Watchdog enabled, failsafe mode + 0 1 Watchdog disabled + 1 0 Watchdog enabled, failsafe mode + 1 1 Watchdog enabled, normal mode +===== ===== =============================== + +Clock Generator Select +---------------------- + +The board is prepared to supply different SerDes clock speeds. But for now, +only setting 0 is supported, otherwise the CPU will hang because the PLL +will not lock. + +Clock Output Disable And Keep Devices In Reset +---------------------------------------------- + +To safe power, the user might disable different devices and clock output of +the board. It is not supported to disable the "CPU SerDes clock #2" for +now, otherwise the CPU will hang because the PLL will not lock. + +Automatic reset of the onboard PHYs +----------------------------------- + +By default, there is no hardware reset of the onboard PHY. This is because +for Wake-on-LAN, some registers have to retain their values. If you don't +use the WOL feature and a soft reset of the PHY is not enough you can +enable the hardware reset. The onboard PHY hardware reset follows the +power-on reset. + + +Further documentation +===================== + +- `Vendor Documentation`_ +- `Reset Configuration Word Documentation`_ + +.. _Reset Configuration Word Documentation: https://raw.githubusercontent.com/kontron/rcw-smarc-sal28/master/README.md +.. _Vendor Documentation: https://raw.githubusercontent.com/kontron/u-boot-smarc-sal28/master/board/kontron/sl28/README.md diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst index 8c92de0..955e685 100644 --- a/doc/board/rockchip/rockchip.rst +++ b/doc/board/rockchip/rockchip.rst @@ -123,6 +123,9 @@ To build rk3399 boards:: Flashing -------- +1. Package the image with U-Boot TPL/SPL +----------------------------------------- + SD Card ^^^^^^^ @@ -187,6 +190,39 @@ Copy SPI boot images into SD card and boot from SD:: sf erase 0x60000 +$filesize sf write $kernel_addr_r 0x60000 ${filesize} +2. Package the image with Rockchip miniloader +--------------------------------------------- + +Image package with Rockchip miniloader requires robin [1]. + +Create idbloader.img + +.. code-block:: none + + cd u-boot + ./tools/mkimage -n px30 -T rksd -d rkbin/bin/rk33/px30_ddr_333MHz_v1.15.bin idbloader.img + cat rkbin/bin/rk33/px30_miniloader_v1.22.bin >> idbloader.img + sudo dd if=idbloader.img of=/dev/sda seek=64 + +Create trust.img + +.. code-block:: none + + cd rkbin + ./tools/trust_merger RKTRUST/PX30TRUST.ini + sudo dd if=trust.img of=/dev/sda seek=24576 + +Create uboot.img + +.. code-block:: none + + rbink/tools/loaderimage --pack --uboot u-boot-dtb.bin uboot.img 0x200000 + sudo dd if=uboot.img of=/dev/sda seek=16384 + +Note: +1. 0x200000 is load address and it's an optional in some platforms. +2. rkbin binaries are kept on updating, so would recommend to use the latest versions. + TODO ---- @@ -195,5 +231,7 @@ TODO - Document SPI flash boot - Add missing SoC's with it boards list +[1] https://github.com/rockchip-linux/rkbin + .. Jagan Teki <jagan@amarulasolutions.com> -.. Tuesday 02 June 2020 12:18:57 AM IST +.. Wednesday 28 October 2020 06:47:26 PM IST diff --git a/doc/board/xilinx/index.rst b/doc/board/xilinx/index.rst index 47f0929..2e31fe3 100644 --- a/doc/board/xilinx/index.rst +++ b/doc/board/xilinx/index.rst @@ -8,3 +8,5 @@ Xilinx xilinx zynq + zynqmp + zynqmp-r5 diff --git a/doc/board/xilinx/xilinx.rst b/doc/board/xilinx/xilinx.rst index f6ea5db..8c9afb4 100644 --- a/doc/board/xilinx/xilinx.rst +++ b/doc/board/xilinx/xilinx.rst @@ -10,18 +10,28 @@ kernel. * ata - Documentation/devicetree/bindings/ata/ahci-ceva.txt +* clock + - Documentation/devicetree/bindings/clock/xlnx,zynqmp-clk.txt +* firmware + - Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.txt +* fpga + - Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt * gpio - Documentation/devicetree/bindings/gpio/gpio-xilinx.txt - Documentation/devicetree/bindings/gpio/gpio-zynq.txt * i2c - - Documentation/devicetree/bindings/i2c/i2c-xiic.txt - - Documentation/devicetree/bindings/i2c/i2c-cadence.txt + - Documentation/devicetree/bindings/i2c/xlnx,xps-iic-2.00.a.yaml + - Documentation/devicetree/bindings/i2c/cdns,i2c-r1p10.yaml * mmc - - Documentation/devicetree/bindings/mmc/arasan,sdhci.txt + - Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml * net - Documentation/devicetree/bindings/net/macb.txt - Documentation/devicetree/bindings/net/xilinx_axienet.txt - Documentation/devicetree/bindings/net/xilinx_emaclite.txt +* nvmem + - Documentation/devicetree/bindings/nvmem/xlnx,zynqmp-nvmem.txt +* power + - Documentation/devicetree/bindings/power/reset/xlnx,zynqmp-power.txt * serial - Documentation/devicetree/bindings/serial/cdns,uart.txt - Documentation/devicetree/bindings/serial/xlnx,opb-uartlite.txt diff --git a/doc/board/xilinx/zynq.rst b/doc/board/xilinx/zynq.rst index f564434..438912f 100644 --- a/doc/board/xilinx/zynq.rst +++ b/doc/board/xilinx/zynq.rst @@ -83,7 +83,7 @@ Mainline status --------------- - Added basic board configurations support. -- Added zynq u-boot bsp code - arch/arm/cpu/armv7/zynq +- Added zynq u-boot bsp code - arch/arm/mach-zynq - Added zynq boards named - zc70x, zed, microzed, zc770_xm010/xm011/xm012/xm013 - Added zynq drivers: @@ -99,11 +99,6 @@ Mainline status - Added basic FDT support for zynq boards - d-cache support for zynq_gem.c -TODO ----- - -Add FDT support on individual drivers - * [1] http://www.xilinx.com/products/boards-and-kits/EK-Z7-ZC702-G.htm * [2] http://www.xilinx.com/products/boards-and-kits/EK-Z7-ZC706-G.htm * [3] http://zedboard.org/product/zedboard diff --git a/doc/board/xilinx/zynqmp-r5.rst b/doc/board/xilinx/zynqmp-r5.rst new file mode 100644 index 0000000..2cd368b --- /dev/null +++ b/doc/board/xilinx/zynqmp-r5.rst @@ -0,0 +1,137 @@ +.. SPDX-License-Identifier: GPL-2.0 +.. (C) Copyright 2020 Xilinx, Inc. + +ZYNQMP-R5 +========= + +About this +---------- + +This document describes the information about Xilinx Zynq UltraScale+ MPSOC +U-Boot Cortex R5 support. + +ZynqMP R5 boards +---------------- + +* zynqmp-r5 - U-Boot running on RPU Cortex-R5 + +Building +-------- + +configure and build armv7 toolchain:: + + $ make xilinx_zynqmp_r5_defconfig + $ make + +Notes +^^^^^ + +Output fragment is u-boot. + +Loading +------- + +ZynqMP R5 U-Boot was created for supporting loading OS on RPU. There are two +ways how to start U-Boot on R5. + +Bootgen +^^^^^^^ + +The first way is to use Xilinx FSBL (First stage +bootloader) to load u-boot and start it. The following bif can be used for boot +image generation via Xilinx bootgen utility:: + + + the_ROM_image: + { + [bootloader,destination_cpu=r5-0] fsbl_rpu.elf + [destination_cpu=r5-0]u-boot.elf + } + +Bootgen command for building boot.bin:: + + bootgen -image <bif>.bif -r -w -o i boot.bin + + +U-Boot cpu command +^^^^^^^^^^^^^^^^^^ + +The second way to load U-Boot to Cortex R5 is from U-Boot running on A53 as is +visible from the following log:: + + U-Boot SPL 2020.10-rc4-00090-g801b3d5c5757 (Sep 15 2020 - 14:07:24 +0200) + PMUFW: v1.1 + Loading new PMUFW cfg obj (2024 bytes) + EL Level: EL3 + Multiboot: 0 + Trying to boot from MMC2 + spl: could not initialize mmc. error: -19 + Trying to boot from MMC1 + spl_load_image_fat_os: error reading image u-boot.bin, err - -2 + NOTICE: ATF running on XCZU7EG/EV/silicon v4/RTL5.1 at 0xfffea000 + NOTICE: BL31: v2.2(release):v2.2-614-ged9dc512fb9c + NOTICE: BL31: Built : 09:32:09, Mar 13 2020 + + + U-Boot 2020.10-rc4-00090-g801b3d5c5757 (Sep 15 2020 - 14:07:24 +0200) + + Model: ZynqMP ZCU104 RevC + Board: Xilinx ZynqMP + DRAM: 2 GiB + PMUFW: v1.1 + EL Level: EL2 + Chip ID: zu7e + WDT: Started with servicing (60s timeout) + NAND: 0 MiB + MMC: mmc@ff170000: 0 + Loading Environment from FAT... *** Warning - bad CRC, using default environment + + In: serial + Out: serial + Err: serial + Bootmode: LVL_SHFT_SD_MODE1 + Reset reason: SOFT + Net: + ZYNQ GEM: ff0e0000, mdio bus ff0e0000, phyaddr 12, interface rgmii-id + eth0: ethernet@ff0e0000 + Hit any key to stop autoboot: 0 + ZynqMP> setenv autoload no + ZynqMP> dhcp + BOOTP broadcast 1 + DHCP client bound to address 192.168.0.167 (8 ms) + ZynqMP> tftpboot 20000000 192.168.0.105:u-boot-r5-2.elf + Using ethernet@ff0e0000 device + TFTP from server 192.168.0.105; our IP address is 192.168.0.167 + Filename 'u-boot-r5-2.elf'. + Load address: 0x20000000 + Loading: ################################################################# + ################################################################# + ################################################################# + ################################################################# + ################################################################# + ################################################################# + ################ + 376 KiB/s + done + Bytes transferred = 2075464 (1fab48 hex) + ZynqMP> setenv autostart no + ZynqMP> bootelf -p 20000000 + ZynqMP> cpu 4 release 10000000 lockstep + Using TCM jump trampoline for address 0x10000000 + R5 lockstep mode + ZynqMP> + +Then on second uart you can see U-Boot up and running on R5:: + + U-Boot 2020.10-rc4-00071-g7045622cc9ba (Sep 16 2020 - 13:38:53 +0200) + + Model: Xilinx ZynqMP R5 + DRAM: 512 MiB + MMC: + In: serial@ff010000 + Out: serial@ff010000 + Err: serial@ff010000 + Net: No ethernet found. + ZynqMP r5> + +Please make sure MIO pins for uart are properly configured to see output. diff --git a/doc/board/xilinx/zynqmp.rst b/doc/board/xilinx/zynqmp.rst new file mode 100644 index 0000000..a035cff --- /dev/null +++ b/doc/board/xilinx/zynqmp.rst @@ -0,0 +1,115 @@ +.. SPDX-License-Identifier: GPL-2.0 +.. (C) Copyright 2020 Xilinx, Inc. + +ZYNQMP +====== + +About this +---------- + +This document describes the information about Xilinx Zynq UltraScale+ MPSOC +U-Boot support. Core support is available in arch/arm/mach-zynqmp folder. + +ZynqMP boards +------------- + +* zcu100 (ultra96 v1), zcu102, zcu104, zcu106 - Evaluation boards +* zc1232 - Characterization boards +* zcu111, zcu208, zcu216 - RFSOC evaluation boards +* zcu1254, zcu1275, zcu1285 - RFSOC characterization boards +* a2197 - System Controller on Versal boards +* mini - Mini U-Boot running out of OCM +* zc1751 - Characterization Processor boards + - zc1751-xm015-dc1 + - zc1751-xm016-dc2 + - zc1751-xm017-dc3 + - zc1751-xm018-dc4 + - zc1751-xm019-dc5 + +Building +-------- + +Configure and build for zcu102 board:: + + $ source arm64 toolchain + $ export DEVICE_TREE=zynqmp-zcu102-revA + $ make xilinx_zynqmp_virt_defconfig + $ make + +U-Boot SPL flow +--------------- + +For getting U-Boot SPL flow up and running it is necessary to do some additional +steps because booting device requires external images which are not the part of +U-Boot repository. + +PMU firmware +^^^^^^^^^^^^ +The Platform Management Unit (PMU) RAM can be loaded with a firmware (PMU +Firmware) at run-time and can be used to extend or customize the functionality +of PMU. The PMU firmware is the part of boot image (boot.bin) and it is +automatically loaded by BootROM. boot.bin can be directly generated by mkimage +tool as the part of make. If you want to create boot.bin with PMU Firmware +include please point CONFIG_PMUFW_INIT_FILE to PMU firmware binary. For example::: + + CONFIG_PMUFW_INIT_FILE="<path>/pmu.bin" + +If you see below message you need to load PMU Firmware:: + + PMUFW is not found - Please load it! + +The second external blob is PMU Configuration object which is object which is +passed from U-Boot SPL to PMU Firmware for initial system configuration. PMU +configuration object is the part of U-Boot SPL image. For pointing to this +object please use CONFIG_ZYNQMP_SPL_PM_CFG_OBJ_FILE symbol. For example::: + + CONFIG_ZYNQMP_SPL_PM_CFG_OBJ_FILE="<path>/pmu_obj.bin" + + +PMU configuration object +^^^^^^^^^^^^^^^^^^^^^^^^ + +Object can be obtain in several ways. The easiest way is to take pm_cfg_obj.c +from SDK/Vitis design and build it::: + + $ git clone https://github.com/Xilinx/embeddedsw.git + $ export EMBEDDED_SW=$PWD/embeddedsw + $ gcc -c pm_cfg_obj.c -I ${EMBEDDED_SW}/lib/bsp/standalone/src/common/ -I ${EMBEDDED_SW}/lib/sw_services/xilpm/src/zynqmp/client/common/ + $ objcopy -O binary pm_cfg_obj.o pmu_obj.bin + +The second way is to use tools/zynqmp_pm_cfg_obj_convert.py. For more +information about this tool please run it with -h parameter. + +The third way is to extract it from Xilinx FSBL elf file. Object is starting at +XPm_ConfigObject symbol. + + +Arm Trusted Firmware (ATF) +^^^^^^^^^^^^^^^^^^^^^^^^^^ + +U-Boot itself can run from EL3 to EL1. Without ATF U-Boot runs in EL3. Boot flow +is U-Boot SPL->U-Boot in EL3. When ATF is used U-Boot normally runs in EL2. Boot +flow is U-Boot SPL->ATF->U-Boot in EL2. As the part of build process u-boot.itb +is generated. When BL31 shell variable is present u-boot.itb is generated with +ATF included. You can point to it by::: + + $ export BL31=<path>/bl31.bin + +Flashing +-------- + +SD Card +^^^^^^^ + +To write an image that boots from a SD card first create a FAT32 partition +and a FAT32 filesystem on the SD card:: + + sudo fdisk /dev/sdx + sudo mkfs.vfat -F 32 /dev/sdx1 + +Mount the SD card and copy the SPL and U-Boot to the root directory of the +SD card:: + + sudo mount -t vfat /dev/sdx1 /mnt + sudo cp spl/boot.bin /mnt + sudo cp u-boot.itb /mnt diff --git a/doc/develop/logging.rst b/doc/develop/logging.rst index 528280c..7fdd113 100644 --- a/doc/develop/logging.rst +++ b/doc/develop/logging.rst @@ -21,26 +21,13 @@ is visible from the basic console output. U-Boot's logging feature aims to satisfy this goal for both users and developers. - Logging levels -------------- -There are a number logging levels available, in increasing order of verbosity: - -* LOGL_EMERG - Printed before U-Boot halts -* LOGL_ALERT - Indicates action must be taken immediate or U-Boot will crash -* LOGL_CRIT - Indicates a critical error that will cause boot failure -* LOGL_ERR - Indicates an error that may cause boot failure -* LOGL_WARNING - Warning about an unexpected condition -* LOGL_NOTE - Important information about progress -* LOGL_INFO - Information about normal boot progress -* LOGL_DEBUG - Debug information (useful for debugging a driver or subsystem) -* LOGL_DEBUG_CONTENT - Debug message showing full message content -* LOGL_DEBUG_IO - Debug message showing hardware I/O access +There are a number logging levels available. -To continue a log message in a separate call of function log() use - -* LOGL_CONT - Use same log level as in previous call +.. kernel-doc:: include/log.h + :identifiers: log_level_t Logging category ---------------- @@ -49,19 +36,8 @@ Logging can come from a wide variety of places within U-Boot. Each log message has a category which is intended to allow messages to be filtered according to their source. -The following main categories are defined: - -* LOGC_NONE - Unknown category (e.g. a debug() statement) -* UCLASS\_... - Related to a particular uclass (e.g. UCLASS_USB) -* LOGC_ARCH - Related to architecture-specific code -* LOGC_BOARD - Related to board-specific code -* LOGC_CORE - Related to core driver-model support -* LOGC_DT - Related to device tree control -* LOGC_EFI - Related to EFI implementation - -To continue a log message in a separate call of function log() use - -* LOGC_CONT - Use same category as in previous call +.. kernel-doc:: include/log.h + :identifiers: log_category_t Enabling logging ---------------- @@ -78,7 +54,6 @@ If CONFIG_LOG is not set, then no logging will be available. The above have SPL and TPL versions also, e.g. CONFIG_SPL_LOG_MAX_LEVEL and CONFIG_TPL_LOG_MAX_LEVEL. - Temporary logging within a single file -------------------------------------- @@ -89,12 +64,52 @@ Sometimes it is useful to turn on logging just in one file. You can use this #define LOG_DEBUG to enable building in of all logging statements in a single file. Put it at -the top of the file, before any #includes. This overrides any log-level setting -in U-Boot, including CONFIG_LOG_DEFAULT_LEVEL, but just for that file. +the top of the file, before any #includes. + +To actually get U-Boot to output this you need to also set the default logging +level - e.g. set CONFIG_LOG_DEFAULT_LEVEL to 7 (:c:type:`LOGL_DEBUG`) or more. +Otherwise debug output is suppressed and will not be generated. + +Using DEBUG +----------- + +U-Boot has traditionally used a #define called DEBUG to enable debugging on a +file-by-file basis. The debug() macro compiles to a printf() statement if +DEBUG is enabled, and an empty statement if not. + +With logging enabled, debug() statements are interpreted as logging output +with a level of LOGL_DEBUG and a category of LOGC_NONE. + +The logging facilities are intended to replace DEBUG, but if DEBUG is defined +at the top of a file, then it takes precedence. This means that debug() +statements will result in output to the console and this output will not be +logged. + +Logging statements +------------------ + +The main logging function is: +.. code-block:: c + + log(category, level, format_string, ...) + +Also debug() and error() will generate log records - these use LOG_CATEGORY +as the category, so you should #define this right at the top of the source +file to ensure the category is correct. + +You can also define CONFIG_LOG_ERROR_RETURN to enable the log_ret() macro. This +can be used whenever your function returns an error value: + +.. code-block:: c + + return log_ret(uclass_first_device(UCLASS_MMC, &dev)); + +This will write a log record when an error code is detected (a value < 0). This +can make it easier to trace errors that are generated deep in the call stack. Convenience functions ---------------------- +~~~~~~~~~~~~~~~~~~~~~ A number of convenience functions are available to shorten the code needed for logging: @@ -122,36 +137,6 @@ or Remember that all uclasses IDs are log categories too. - -Log command ------------ - -The 'log' command provides access to several features: - -* level - access the default log level -* format - access the console log format -* rec - output a log record -* test - run tests - -Type 'help log' for details. - - -Using DEBUG ------------ - -U-Boot has traditionally used a #define called DEBUG to enable debugging on a -file-by-file basis. The debug() macro compiles to a printf() statement if -DEBUG is enabled, and an empty statement if not. - -With logging enabled, debug() statements are interpreted as logging output -with a level of LOGL_DEBUG and a category of LOGC_NONE. - -The logging facilities are intended to replace DEBUG, but if DEBUG is defined -at the top of a file, then it takes precedence. This means that debug() -statements will result in output to the console and this output will not be -logged. - - Logging destinations -------------------- @@ -165,60 +150,84 @@ enabled or disabled independently: The syslog driver sends the value of environmental variable 'log_hostname' as HOSTNAME if available. - -Log format ----------- - -You can control the log format using the 'log format' command. The basic -format is:: - - LEVEL.category,file.c:123-func() message - -In the above, file.c:123 is the filename where the log record was generated and -func() is the function name. By default ('log format default') only the -function name and message are displayed on the console. You can control which -fields are present, but not the field order. - - Filters ------- -Filters are attached to log drivers to control what those drivers emit. Only -records that pass through the filter make it to the driver. +Filters are attached to log drivers to control what those drivers emit. FIlters +can either allow or deny a log message when they match it. Only records which +are allowed by a filter make it to the driver. Filters can be based on several criteria: -* maximum log level +* minimum or maximum log level * in a set of categories * in a set of files If no filters are attached to a driver then a default filter is used, which limits output to records with a level less than CONFIG_MAX_LOG_LEVEL. +Log command +----------- -Logging statements ------------------- +The 'log' command provides access to several features: -The main logging function is: +* level - list log levels or set the default log level +* categories - list log categories +* drivers - list log drivers +* filter-list - list filters +* filter-add - add a new filter +* filter-remove - remove filters +* format - access the console log format +* rec - output a log record -.. code-block:: c +Type 'help log' for details. - log(category, level, format_string, ...) +Log format +~~~~~~~~~~ -Also debug() and error() will generate log records - these use LOG_CATEGORY -as the category, so you should #define this right at the top of the source -file to ensure the category is correct. +You can control the log format using the 'log format' command. The basic +format is:: -You can also define CONFIG_LOG_ERROR_RETURN to enable the log_ret() macro. This -can be used whenever your function returns an error value: + LEVEL.category,file.c:123-func() message -.. code-block:: c +In the above, file.c:123 is the filename where the log record was generated and +func() is the function name. By default ('log format default') only the message +is displayed on the console. You can control which fields are present, but not +the field order. - return log_ret(uclass_first_device(UCLASS_MMC, &dev)); +Adding Filters +~~~~~~~~~~~~~~ -This will write a log record when an error code is detected (a value < 0). This -can make it easier to trace errors that are generated deep in the call stack. +To add new filters at runtime, use the 'log filter-add' command. For example, to +suppress messages from the SPI and MMC subsystems, run:: + + log filter-add -D -c spi -c mmc +You will also need to add another filter to allow other messages (because the +default filter no longer applies):: + + log filter-add -A -l info + +Log levels may be either symbolic names (like above) or numbers. For example, to +disable all debug and above (log level 7) messages from ``drivers/core/lists.c`` +and ``drivers/core/ofnode.c``, run:: + + log filter-add -D -f drivers/core/lists.c,drivers/core/ofnode.c -L 7 + +To view active filters, use the 'log filter-list' command. Some example output +is:: + + => log filter-list + num policy level categories files + 2 deny >= DEBUG drivers/core/lists.c,drivers/core/ofnode.c + 0 deny <= IO spi + mmc + 1 allow <= INFO + +Note that filters are processed in-order from top to bottom, not in the order of +their filter number. Filters are added to the top of the list if they deny when +they match, and to the bottom if they allow when they match. For more +information, consult the usage of the 'log' command, by running 'help log'. Code size --------- @@ -235,13 +244,12 @@ The last option turns every debug() statement into a logging call, which bloats the code hugely. The advantage is that it is then possible to enable all logging within U-Boot. - To Do ----- There are lots of useful additions that could be made. None of the below is -implemented! If you do one, please add a test in test/py/tests/test_log.py - +implemented! If you do one, please add a test in test/log/log_test.c +log filter-add -D -f drivers/core/lists.c,drivers/core/ofnode.c -l 6 Convenience functions to support setting the category: * log_arch(level, format_string, ...) - category LOGC_ARCH @@ -262,25 +270,15 @@ Convert error() statements in the code to log() statements Figure out what to do with BUG(), BUG_ON() and warn_non_spl() -Figure out what to do with assert() - Add a way to browse log records Add a way to record log records for browsing using an external tool -Add commands to add and remove filters - Add commands to add and remove log devices Allow sharing of printf format strings in log records to reduce storage size for large numbers of log records -Add a command-line option to sandbox to set the default logging level - -Convert core driver model code to use logging - -Convert uclasses to use logging with the correct category - Consider making log() calls emit an automatic newline, perhaps with a logn() function to avoid that @@ -291,9 +289,9 @@ number dropped due to them being generated before the log system was ready. Add a printf() format string pragma so that log statements are checked properly -Enhance the log console driver to show level / category / file / line -information - -Add a command to add new log records and delete existing records. +Add a command to delete existing log records. -Provide additional log() functions - e.g. logc() to specify the category +Logging API +----------- +.. kernel-doc:: include/log.h + :internal: diff --git a/doc/driver-model/of-plat.rst b/doc/driver-model/of-plat.rst index 1e3fad1..5848166 100644 --- a/doc/driver-model/of-plat.rst +++ b/doc/driver-model/of-plat.rst @@ -66,12 +66,6 @@ strictly necessary. Notable problems include: normally also supports device tree it must use #ifdef to separate out this code, since the structures are only available in SPL. - - Correct relations between nodes are not implemented. This means that - parent/child relations (like bus device iteration) do not work yet. - Some phandles (those that are recognised as such) are converted into - a pointer to struct driver_info. This pointer can be used to access - the referenced device. - How it works ------------ @@ -134,10 +128,14 @@ the following C struct declaration: fdt32_t vmmc_supply; }; -and the following device declaration: +and the following device declarations: .. code-block:: c + /* Node /clock-controller@ff760000 index 0 */ + ... + + /* Node /dwmmc@ff0c0000 index 2 */ static struct dtd_rockchip_rk3288_dw_mshc dtv_dwmmc_at_ff0c0000 = { .fifo_depth = 0x100, .cap_sd_highspeed = true, @@ -145,10 +143,10 @@ and the following device declaration: .clock_freq_min_max = {0x61a80, 0x8f0d180}, .vmmc_supply = 0xb, .num_slots = 0x1, - .clocks = {{NULL, 456}, - {NULL, 68}, - {NULL, 114}, - {NULL, 118}}, + .clocks = {{0, 456}, + {0, 68}, + {0, 114}, + {0, 118}}, .cap_mmc_highspeed = true, .disable_wp = true, .bus_width = 0x4, @@ -161,13 +159,10 @@ and the following device declaration: .name = "rockchip_rk3288_dw_mshc", .platdata = &dtv_dwmmc_at_ff0c0000, .platdata_size = sizeof(dtv_dwmmc_at_ff0c0000), + .parent_idx = -1, }; void dm_populate_phandle_data(void) { - dtv_dwmmc_at_ff0c0000.clocks[0].node = DM_GET_DEVICE(clock_controller_at_ff760000); - dtv_dwmmc_at_ff0c0000.clocks[1].node = DM_GET_DEVICE(clock_controller_at_ff760000); - dtv_dwmmc_at_ff0c0000.clocks[2].node = DM_GET_DEVICE(clock_controller_at_ff760000); - dtv_dwmmc_at_ff0c0000.clocks[3].node = DM_GET_DEVICE(clock_controller_at_ff760000); } The device is then instantiated at run-time and the platform data can be @@ -193,6 +188,13 @@ In order to make this a bit more flexible U_BOOT_DRIVER_ALIAS macro can be used to declare an alias for a driver name, typically a 'compatible' string. This macro produces no code, but it is by dtoc tool. +The parent_idx is the index of the parent driver_info structure within its +linker list (instantiated by the U_BOOT_DEVICE() macro). This is used to support +dev_get_parent(). The dm_populate_phandle_data() is included to allow for +fix-ups required by dtoc. It is not currently used. The values in 'clocks' are +the index of the driver_info for the target device followed by any phandle +arguments. This is used to support device_get_by_driver_info_idx(). + During the build process dtoc parses both U_BOOT_DRIVER and U_BOOT_DRIVER_ALIAS to build a list of valid driver names and driver aliases. If the 'compatible' string used for a device does not not match a valid driver name, it will be @@ -339,12 +341,7 @@ spl/dt-platdata.c. It additionally contains the definition of dm_populate_phandle_data() which is responsible of filling the phandle information by adding references to U_BOOT_DEVICE by using DM_GET_DEVICE -The beginnings of a libfdt Python module are provided. So far this only -implements a subset of the features. - -The 'swig' tool is needed to build the libfdt Python module. If this is not -found then the Python model is not used and a fallback is used instead, which -makes use of fdtget. +The pylibfdt Python module is used to access the devicetree. Credits @@ -357,11 +354,10 @@ Future work ----------- - Consider programmatically reading binding files instead of device tree contents -- Complete the phandle feature -- Move to using a full Python libfdt module .. Simon Glass <sjg@chromium.org> .. Google, Inc .. 6/6/16 .. Updated Independence Day 2016 +.. Updated 1st October 2020 diff --git a/doc/git-mailrc b/doc/git-mailrc index bbca3a9..f520ff8 100644 --- a/doc/git-mailrc +++ b/doc/git-mailrc @@ -18,6 +18,7 @@ alias agraf Alexander Graf <agraf@csgraf.de> alias alexnemirovsky Alex Nemirovsky <alex.nemirovsky@cortina-access.com> alias alisonwang Alison Wang <alison.wang@nxp.com> alias angelo_ts Angelo Dureghello <angelo@sysam.it> +alias apritzel Andre Przywara <andre.przywara@arm.com> alias bmeng Bin Meng <bmeng.cn@gmail.com> alias danielschwierzeck Daniel Schwierzeck <daniel.schwierzeck@gmail.com> alias dinh Dinh Nguyen <dinguyen@kernel.org> @@ -36,7 +37,6 @@ alias marex Marek Vasut <marex@denx.de> alias mariosix Mario Six <mario.six@gdsys.cc> alias masahiro Masahiro Yamada <yamada.masahiro@socionext.com> alias mateusz Mateusz Kulikowski <mateusz.kulikowski@gmail.com> -alias maxime Maxime Ripard <mripard@kernel.org> alias mbrugger Matthias Brugger <mbrugger@suse.com> alias monstr Michal Simek <monstr@monstr.eu> alias prom Minkyu Kang <mk7.kang@samsung.com> @@ -70,7 +70,7 @@ alias s5pc samsung alias samsung uboot, prom alias snapdragon uboot, mateusz alias socfpga uboot, marex, dinh, simongoldschmidt, leyfoon -alias sunxi uboot, jagan, maxime +alias sunxi uboot, jagan, apritzel alias tegra uboot, sjg, Tom Warren <twarren@nvidia.com>, Stephen Warren <swarren@nvidia.com> alias tegra2 tegra alias ti uboot, lokeshvutla diff --git a/doc/uImage.FIT/howto.txt b/doc/uImage.FIT/howto.txt index 8592719..019dda2 100644 --- a/doc/uImage.FIT/howto.txt +++ b/doc/uImage.FIT/howto.txt @@ -66,6 +66,90 @@ can point to a script which generates this image source file during the build process. It gets passed a list of device tree files (taken from the CONFIG_OF_LIST symbol). +The SPL also records to a DT all additional images (called loadables) which are +loaded. The information about loadables locations is passed via the DT node with +fit-images name. + +Loadables Example +----------------- +Consider the following case for an ARM64 platform where U-Boot runs in EL2 +started by ATF where SPL is loading U-Boot (as loadables) and ATF (as firmware). + +/dts-v1/; + +/ { + description = "Configuration to load ATF before U-Boot"; + + images { + uboot { + description = "U-Boot (64-bit)"; + data = /incbin/("u-boot-nodtb.bin"); + type = "firmware"; + os = "u-boot"; + arch = "arm64"; + compression = "none"; + load = <0x8 0x8000000>; + entry = <0x8 0x8000000>; + hash { + algo = "md5"; + }; + }; + atf { + description = "ARM Trusted Firmware"; + data = /incbin/("bl31.bin"); + type = "firmware"; + os = "arm-trusted-firmware"; + arch = "arm64"; + compression = "none"; + load = <0xfffea000>; + entry = <0xfffea000>; + hash { + algo = "md5"; + }; + }; + fdt_1 { + description = "zynqmp-zcu102-revA"; + data = /incbin/("arch/arm/dts/zynqmp-zcu102-revA.dtb"); + type = "flat_dt"; + arch = "arm64"; + compression = "none"; + load = <0x100000>; + hash { + algo = "md5"; + }; + }; + }; + configurations { + default = "config_1"; + + config_1 { + description = "zynqmp-zcu102-revA"; + firmware = "atf"; + loadables = "uboot"; + fdt = "fdt_1"; + }; + }; +}; + +In this case the SPL records via fit-images DT node the information about +loadables U-Boot image. + +ZynqMP> fdt addr $fdtcontroladdr +ZynqMP> fdt print /fit-images +fit-images { + uboot { + os = "u-boot"; + type = "firmware"; + size = <0x001017c8>; + entry = <0x00000008 0x08000000>; + load = <0x00000008 0x08000000>; + }; +}; + +As you can see entry and load properties are 64bit wide to support loading +images above 4GB (in past entry and load properties where just 32bit). + + Example 1 -- old-style (non-FDT) kernel booting ----------------------------------------------- diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c index 31c5997..ac954a3 100644 --- a/drivers/clk/clk-uclass.c +++ b/drivers/clk/clk-uclass.c @@ -38,8 +38,7 @@ int clk_get_by_driver_info(struct udevice *dev, struct phandle_1_arg *cells, { int ret; - ret = device_get_by_driver_info((struct driver_info *)cells->node, - &clk->dev); + ret = device_get_by_driver_info_idx(cells->idx, &clk->dev); if (ret) return ret; clk->id = cells->arg[0]; diff --git a/drivers/clk/clk_fixed_rate.c b/drivers/clk/clk_fixed_rate.c index 55e1f8c..f86b4a0 100644 --- a/drivers/clk/clk_fixed_rate.c +++ b/drivers/clk/clk_fixed_rate.c @@ -46,8 +46,8 @@ static const struct udevice_id clk_fixed_rate_match[] = { { /* sentinel */ } }; -U_BOOT_DRIVER(clk_fixed_rate) = { - .name = "fixed_rate_clock", +U_BOOT_DRIVER(fixed_clock) = { + .name = "fixed_clock", .id = UCLASS_CLK, .of_match = clk_fixed_rate_match, .ofdata_to_platdata = clk_fixed_rate_ofdata_to_platdata, diff --git a/drivers/clk/clk_sandbox.c b/drivers/clk/clk_sandbox.c index 768fbb7..0ff1b49 100644 --- a/drivers/clk/clk_sandbox.c +++ b/drivers/clk/clk_sandbox.c @@ -124,8 +124,8 @@ static const struct udevice_id sandbox_clk_ids[] = { { } }; -U_BOOT_DRIVER(clk_sandbox) = { - .name = "clk_sandbox", +U_BOOT_DRIVER(sandbox_clk) = { + .name = "sandbox_clk", .id = UCLASS_CLK, .of_match = sandbox_clk_ids, .ops = &sandbox_clk_ops, diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c index 1ea41f3..478d76d 100644 --- a/drivers/clk/rockchip/clk_rk3399.c +++ b/drivers/clk/rockchip/clk_rk3399.c @@ -233,6 +233,10 @@ enum { DCLK_VOP_DIV_CON_MASK = 0xff, DCLK_VOP_DIV_CON_SHIFT = 0, + /* CLKSEL_CON57 */ + PCLK_ALIVE_DIV_CON_SHIFT = 0, + PCLK_ALIVE_DIV_CON_MASK = 0x1f << PCLK_ALIVE_DIV_CON_SHIFT, + /* CLKSEL_CON58 */ CLK_SPI_PLL_SEL_WIDTH = 1, CLK_SPI_PLL_SEL_MASK = ((1 < CLK_SPI_PLL_SEL_WIDTH) - 1), @@ -867,6 +871,17 @@ static ulong rk3399_ddr_set_clk(struct rockchip_cru *cru, return set_rate; } +static ulong rk3399_alive_get_clk(struct rockchip_cru *cru) +{ + u32 div, val; + + val = readl(&cru->clksel_con[57]); + div = (val & PCLK_ALIVE_DIV_CON_MASK) >> + PCLK_ALIVE_DIV_CON_SHIFT; + + return DIV_TO_RATE(GPLL_HZ, div); +} + static ulong rk3399_saradc_get_clk(struct rockchip_cru *cru) { u32 div, val; @@ -936,6 +951,10 @@ static ulong rk3399_clk_get_rate(struct clk *clk) case ACLK_GIC_PRE: case PCLK_DDR: break; + case PCLK_ALIVE: + case PCLK_WDT: + rate = rk3399_alive_get_clk(priv->cru); + break; default: log_debug("Unknown clock %lu\n", clk->id); return -ENOENT; @@ -1502,6 +1521,7 @@ static ulong rk3399_pmuclk_get_rate(struct clk *clk) case PLL_PPLL: return PPLL_HZ; case PCLK_RKPWM_PMU: + case PCLK_WDT_M0_PMU: rate = rk3399_pwm_get_clk(priv->pmucru); break; case SCLK_I2C0_PMU: diff --git a/drivers/core/Kconfig b/drivers/core/Kconfig index 07d3a6a..ffae6f9 100644 --- a/drivers/core/Kconfig +++ b/drivers/core/Kconfig @@ -40,10 +40,24 @@ config DM_WARN depends on DM default y help + Enable this to see warnings related to driver model. + + Warnings may help with debugging, such as when expected devices do + not bind correctly. If the option is disabled, dm_warn() is compiled + out - it will do nothing when called. + +config SPL_DM_WARN + bool "Enable warnings in driver model wuth SPL" + depends on SPL_DM + help + Enable this to see warnings related to driver model in SPL + The dm_warn() function can use up quite a bit of space for its strings. By default this is disabled for SPL builds to save space. - This will cause dm_warn() to be compiled out - it will do nothing - when called. + + Warnings may help with debugging, such as when expected devices do + not bind correctly. If the option is disabled, dm_warn() is compiled + out - it will do nothing when called. config DM_DEBUG bool "Enable debug messages in driver model core" diff --git a/drivers/core/Makefile b/drivers/core/Makefile index 10f4bec..5edd4e4 100644 --- a/drivers/core/Makefile +++ b/drivers/core/Makefile @@ -11,7 +11,7 @@ obj-$(CONFIG_SIMPLE_PM_BUS) += simple-pm-bus.o obj-$(CONFIG_DM) += dump.o obj-$(CONFIG_$(SPL_TPL_)REGMAP) += regmap.o obj-$(CONFIG_$(SPL_TPL_)SYSCON) += syscon-uclass.o -obj-$(CONFIG_OF_LIVE) += of_access.o of_addr.o +obj-$(CONFIG_$(SPL_)OF_LIVE) += of_access.o of_addr.o ifndef CONFIG_DM_DEV_READ_INLINE obj-$(CONFIG_OF_CONTROL) += read.o endif diff --git a/drivers/core/device.c b/drivers/core/device.c index e90d701..4b3dcb3 100644 --- a/drivers/core/device.c +++ b/drivers/core/device.c @@ -249,7 +249,7 @@ int device_bind_ofnode(struct udevice *parent, const struct driver *drv, } int device_bind_by_name(struct udevice *parent, bool pre_reloc_only, - struct driver_info *info, struct udevice **devp) + const struct driver_info *info, struct udevice **devp) { struct driver *drv; uint platdata_size = 0; @@ -269,9 +269,6 @@ int device_bind_by_name(struct udevice *parent, bool pre_reloc_only, platdata_size, devp); if (ret) return ret; -#if CONFIG_IS_ENABLED(OF_PLATDATA) - info->dev = *devp; -#endif return ret; } @@ -764,9 +761,25 @@ int device_get_global_by_ofnode(ofnode ofnode, struct udevice **devp) int device_get_by_driver_info(const struct driver_info *info, struct udevice **devp) { + struct driver_info *info_base = + ll_entry_start(struct driver_info, driver_info); + int idx = info - info_base; + struct driver_rt *drt = gd_dm_driver_rt() + idx; struct udevice *dev; - dev = info->dev; + dev = drt->dev; + *devp = NULL; + + return device_get_device_tail(dev, dev ? 0 : -ENOENT, devp); +} + +int device_get_by_driver_info_idx(uint idx, struct udevice **devp) +{ + struct driver_rt *drt = gd_dm_driver_rt() + idx; + struct udevice *dev; + + dev = drt->dev; + *devp = NULL; return device_get_device_tail(dev, dev ? 0 : -ENOENT, devp); } diff --git a/drivers/core/lists.c b/drivers/core/lists.c index 5beba91..b23ee30 100644 --- a/drivers/core/lists.c +++ b/drivers/core/lists.c @@ -51,25 +51,81 @@ struct uclass_driver *lists_uclass_lookup(enum uclass_id id) return NULL; } -int lists_bind_drivers(struct udevice *parent, bool pre_reloc_only) +static int bind_drivers_pass(struct udevice *parent, bool pre_reloc_only) { struct driver_info *info = ll_entry_start(struct driver_info, driver_info); const int n_ents = ll_entry_count(struct driver_info, driver_info); - struct driver_info *entry; - struct udevice *dev; + bool missing_parent = false; int result = 0; - int ret; + uint idx; + + /* + * Do one iteration through the driver_info records. For of-platdata, + * bind only devices whose parent is already bound. If we find any + * device we can't bind, set missing_parent to true, which will cause + * this function to be called again. + */ + for (idx = 0; idx < n_ents; idx++) { + struct udevice *par = parent; + const struct driver_info *entry = info + idx; + struct driver_rt *drt = gd_dm_driver_rt() + idx; + struct udevice *dev; + int ret; - for (entry = info; entry != info + n_ents; entry++) { - ret = device_bind_by_name(parent, pre_reloc_only, entry, &dev); - if (ret && ret != -EPERM) { + if (CONFIG_IS_ENABLED(OF_PLATDATA)) { + int parent_idx = driver_info_parent_id(entry); + + if (drt->dev) + continue; + + if (CONFIG_IS_ENABLED(OF_PLATDATA_PARENT) && + parent_idx != -1) { + struct driver_rt *parent_drt; + + parent_drt = gd_dm_driver_rt() + parent_idx; + if (!parent_drt->dev) { + missing_parent = true; + continue; + } + + par = parent_drt->dev; + } + } + ret = device_bind_by_name(par, pre_reloc_only, entry, &dev); + if (!ret) { + if (CONFIG_IS_ENABLED(OF_PLATDATA)) + drt->dev = dev; + } else if (ret != -EPERM) { dm_warn("No match for driver '%s'\n", entry->name); if (!result || ret != -ENOENT) result = ret; } } + return result ? result : missing_parent ? -EAGAIN : 0; +} + +int lists_bind_drivers(struct udevice *parent, bool pre_reloc_only) +{ + int result = 0; + int pass; + + /* + * 10 passes is 10 levels deep in the devicetree, which is plenty. If + * OF_PLATDATA_PARENT is not enabled, then bind_drivers_pass() will + * always succeed on the first pass. + */ + for (pass = 0; pass < 10; pass++) { + int ret; + + ret = bind_drivers_pass(parent, pre_reloc_only); + if (!ret) + break; + if (ret != -EAGAIN && !result) + result = ret; + } + return result; } diff --git a/drivers/core/ofnode.c b/drivers/core/ofnode.c index 7d1b895..a68076b 100644 --- a/drivers/core/ofnode.c +++ b/drivers/core/ofnode.c @@ -476,6 +476,28 @@ ofnode ofnode_get_chosen_node(const char *name) return ofnode_path(prop); } +const void *ofnode_read_aliases_prop(const char *propname, int *sizep) +{ + ofnode node; + + node = ofnode_path("/aliases"); + + return ofnode_read_prop(node, propname, sizep); +} + +ofnode ofnode_get_aliases_node(const char *name) +{ + const char *prop; + + prop = ofnode_read_aliases_prop(name, NULL); + if (!prop) + return ofnode_null(); + + debug("%s: node_path: %s\n", __func__, prop); + + return ofnode_path(prop); +} + int ofnode_get_child_count(ofnode parent) { ofnode child; diff --git a/drivers/core/root.c b/drivers/core/root.c index 0726be6..5f10d7a 100644 --- a/drivers/core/root.c +++ b/drivers/core/root.c @@ -50,7 +50,6 @@ void dm_fixup_for_gd_move(struct global_data *new_gd) } } -#if defined(CONFIG_NEEDS_MANUAL_RELOC) void fix_drivers(void) { struct driver *drv = @@ -61,7 +60,7 @@ void fix_drivers(void) for (entry = drv; entry != drv + n_ents; entry++) { if (entry->of_match) entry->of_match = (const struct udevice_id *) - ((u32)entry->of_match + gd->reloc_off); + ((ulong)entry->of_match + gd->reloc_off); if (entry->bind) entry->bind += gd->reloc_off; if (entry->probe) @@ -129,8 +128,6 @@ void fix_devices(void) } } -#endif - int dm_init(bool of_live) { int ret; @@ -141,21 +138,19 @@ int dm_init(bool of_live) } INIT_LIST_HEAD(&DM_UCLASS_ROOT_NON_CONST); -#if defined(CONFIG_NEEDS_MANUAL_RELOC) - fix_drivers(); - fix_uclass(); - fix_devices(); -#endif + if (IS_ENABLED(CONFIG_NEEDS_MANUAL_RELOC)) { + fix_drivers(); + fix_uclass(); + fix_devices(); + } ret = device_bind_by_name(NULL, false, &root_info, &DM_ROOT_NON_CONST); if (ret) return ret; #if CONFIG_IS_ENABLED(OF_CONTROL) -# if CONFIG_IS_ENABLED(OF_LIVE) - if (of_live) - DM_ROOT_NON_CONST->node = np_to_ofnode(gd->of_root); + if (CONFIG_IS_ENABLED(OF_LIVE) && of_live) + DM_ROOT_NON_CONST->node = np_to_ofnode(gd_of_root()); else -#endif DM_ROOT_NON_CONST->node = offset_to_ofnode(0); #endif ret = device_probe(DM_ROOT_NON_CONST); @@ -187,6 +182,17 @@ int dm_scan_platdata(bool pre_reloc_only) { int ret; + if (CONFIG_IS_ENABLED(OF_PLATDATA)) { + struct driver_rt *dyn; + int n_ents; + + n_ents = ll_entry_count(struct driver_info, driver_info); + dyn = calloc(n_ents, sizeof(struct driver_rt)); + if (!dyn) + return -ENOMEM; + gd_set_dm_driver_rt(dyn); + } + ret = lists_bind_drivers(DM_ROOT_NON_CONST, pre_reloc_only); if (ret == -ENOENT) { dm_warn("Some drivers were not found\n"); @@ -196,7 +202,7 @@ int dm_scan_platdata(bool pre_reloc_only) return ret; } -#if CONFIG_IS_ENABLED(OF_LIVE) +#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) static int dm_scan_fdt_live(struct udevice *parent, const struct device_node *node_parent, bool pre_reloc_only) @@ -223,9 +229,7 @@ static int dm_scan_fdt_live(struct udevice *parent, return ret; } -#endif /* CONFIG_IS_ENABLED(OF_LIVE) */ -#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) /** * dm_scan_fdt_node() - Scan the device tree and bind drivers for a node * @@ -272,24 +276,20 @@ int dm_scan_fdt_dev(struct udevice *dev) if (!dev_of_valid(dev)) return 0; -#if CONFIG_IS_ENABLED(OF_LIVE) if (of_live_active()) return dm_scan_fdt_live(dev, dev_np(dev), gd->flags & GD_FLG_RELOC ? false : true); - else -#endif + return dm_scan_fdt_node(dev, gd->fdt_blob, dev_of_offset(dev), gd->flags & GD_FLG_RELOC ? false : true); } int dm_scan_fdt(const void *blob, bool pre_reloc_only) { -#if CONFIG_IS_ENABLED(OF_LIVE) if (of_live_active()) - return dm_scan_fdt_live(gd->dm_root, gd->of_root, + return dm_scan_fdt_live(gd->dm_root, gd_of_root(), pre_reloc_only); - else -#endif + return dm_scan_fdt_node(gd->dm_root, blob, 0, pre_reloc_only); } @@ -302,10 +302,9 @@ static int dm_scan_fdt_ofnode_path(const void *blob, const char *path, if (!ofnode_valid(node)) return 0; -#if CONFIG_IS_ENABLED(OF_LIVE) if (of_live_active()) return dm_scan_fdt_live(gd->dm_root, node.np, pre_reloc_only); -#endif + return dm_scan_fdt_node(gd->dm_root, blob, node.of_offset, pre_reloc_only); } @@ -348,11 +347,10 @@ int dm_init_and_scan(bool pre_reloc_only) { int ret; -#if CONFIG_IS_ENABLED(OF_PLATDATA) - dm_populate_phandle_data(); -#endif + if (CONFIG_IS_ENABLED(OF_PLATDATA)) + dm_populate_phandle_data(); - ret = dm_init(IS_ENABLED(CONFIG_OF_LIVE)); + ret = dm_init(CONFIG_IS_ENABLED(OF_LIVE)); if (ret) { debug("dm_init() failed: %d\n", ret); return ret; diff --git a/drivers/core/util.c b/drivers/core/util.c index 25b0d76..91e93b0 100644 --- a/drivers/core/util.c +++ b/drivers/core/util.c @@ -11,7 +11,7 @@ #include <linux/libfdt.h> #include <vsprintf.h> -#ifdef CONFIG_DM_WARN +#if CONFIG_IS_ENABLED(DM_WARN) void dm_warn(const char *fmt, ...) { va_list args; diff --git a/drivers/dfu/Kconfig b/drivers/dfu/Kconfig index 0eec00b..b7427fc 100644 --- a/drivers/dfu/Kconfig +++ b/drivers/dfu/Kconfig @@ -14,9 +14,15 @@ config DFU_OVER_TFTP depends on NET if DFU +config DFU_WRITE_ALT + bool + default n + config DFU_TFTP bool "DFU via TFTP" + select DFU_WRITE_ALT select DFU_OVER_TFTP + select UPDATE_COMMON help This option allows performing update of DFU-managed medium with data sent via TFTP boot. diff --git a/drivers/dfu/Makefile b/drivers/dfu/Makefile index 0d7925c..dfbf64d 100644 --- a/drivers/dfu/Makefile +++ b/drivers/dfu/Makefile @@ -9,5 +9,5 @@ obj-$(CONFIG_$(SPL_)DFU_MTD) += dfu_mtd.o obj-$(CONFIG_$(SPL_)DFU_NAND) += dfu_nand.o obj-$(CONFIG_$(SPL_)DFU_RAM) += dfu_ram.o obj-$(CONFIG_$(SPL_)DFU_SF) += dfu_sf.o -obj-$(CONFIG_$(SPL_)DFU_TFTP) += dfu_tftp.o +obj-$(CONFIG_$(SPL_)DFU_WRITE_ALT) += dfu_alt.o obj-$(CONFIG_$(SPL_)DFU_VIRT) += dfu_virt.o diff --git a/drivers/dfu/dfu.c b/drivers/dfu/dfu.c index a298c2c..501a60b 100644 --- a/drivers/dfu/dfu.c +++ b/drivers/dfu/dfu.c @@ -18,7 +18,7 @@ #include <linux/list.h> #include <linux/compiler.h> -static LIST_HEAD(dfu_list); +LIST_HEAD(dfu_list); static int dfu_alt_num; static int alt_num_cnt; static struct hash_algo *dfu_hash_algo; diff --git a/drivers/dfu/dfu_alt.c b/drivers/dfu/dfu_alt.c new file mode 100644 index 0000000..ece3d22 --- /dev/null +++ b/drivers/dfu/dfu_alt.c @@ -0,0 +1,125 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2015 + * Lukasz Majewski <l.majewski@majess.pl> + */ + +#include <common.h> +#include <log.h> +#include <malloc.h> +#include <errno.h> +#include <dfu.h> + +/** + * dfu_write_by_name() - write data to DFU medium + * @dfu_entity_name: Name of DFU entity to write + * @addr: Address of data buffer to write + * @len: Number of bytes + * @interface: Destination DFU medium (e.g. "mmc") + * @devstring: Instance number of destination DFU medium (e.g. "1") + * + * This function is storing data received on DFU supported medium which + * is specified by @dfu_entity_name. + * + * Return: 0 - on success, error code - otherwise + */ +int dfu_write_by_name(char *dfu_entity_name, void *addr, + unsigned int len, char *interface, char *devstring) +{ + char *s, *sb; + int alt_setting_num, ret; + struct dfu_entity *dfu; + + debug("%s: name: %s addr: 0x%p len: %d device: %s:%s\n", __func__, + dfu_entity_name, addr, len, interface, devstring); + + ret = dfu_init_env_entities(interface, devstring); + if (ret) + goto done; + + /* + * We need to copy name pointed by *dfu_entity_name since this text + * is the integral part of the FDT image. + * Any implicit modification (i.e. done by strsep()) will corrupt + * the FDT image and prevent other images to be stored. + */ + s = strdup(dfu_entity_name); + sb = s; + if (!s) { + ret = -ENOMEM; + goto done; + } + + strsep(&s, "@"); + debug("%s: image name: %s strlen: %zd\n", __func__, sb, strlen(sb)); + + alt_setting_num = dfu_get_alt(sb); + free(sb); + if (alt_setting_num < 0) { + pr_err("Alt setting [%d] to write not found!", + alt_setting_num); + ret = -ENODEV; + goto done; + } + + dfu = dfu_get_entity(alt_setting_num); + if (!dfu) { + pr_err("DFU entity for alt: %d not found!", alt_setting_num); + ret = -ENODEV; + goto done; + } + + ret = dfu_write_from_mem_addr(dfu, (void *)addr, len); + +done: + dfu_free_entities(); + + return ret; +} + +/** + * dfu_write_by_alt() - write data to DFU medium + * @dfu_alt_num: DFU alt setting number + * @addr: Address of data buffer to write + * @len: Number of bytes + * @interface: Destination DFU medium (e.g. "mmc") + * @devstring: Instance number of destination DFU medium (e.g. "1") + * + * This function is storing data received on DFU supported medium which + * is specified by @dfu_alt_name. + * + * Return: 0 - on success, error code - otherwise + */ +int dfu_write_by_alt(int dfu_alt_num, void *addr, unsigned int len, + char *interface, char *devstring) +{ + struct dfu_entity *dfu; + int ret; + + debug("%s: alt: %d addr: 0x%p len: %d device: %s:%s\n", __func__, + dfu_alt_num, addr, len, interface, devstring); + + ret = dfu_init_env_entities(interface, devstring); + if (ret) + goto done; + + if (dfu_alt_num < 0) { + pr_err("Invalid alt number: %d", dfu_alt_num); + ret = -ENODEV; + goto done; + } + + dfu = dfu_get_entity(dfu_alt_num); + if (!dfu) { + pr_err("DFU entity for alt: %d not found!", dfu_alt_num); + ret = -ENODEV; + goto done; + } + + ret = dfu_write_from_mem_addr(dfu, (void *)(uintptr_t)addr, len); + +done: + dfu_free_entities(); + + return ret; +} diff --git a/drivers/dfu/dfu_tftp.c b/drivers/dfu/dfu_tftp.c deleted file mode 100644 index ffae4bb..0000000 --- a/drivers/dfu/dfu_tftp.c +++ /dev/null @@ -1,65 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2015 - * Lukasz Majewski <l.majewski@majess.pl> - */ - -#include <common.h> -#include <log.h> -#include <malloc.h> -#include <errno.h> -#include <dfu.h> - -int dfu_tftp_write(char *dfu_entity_name, unsigned int addr, unsigned int len, - char *interface, char *devstring) -{ - char *s, *sb; - int alt_setting_num, ret; - struct dfu_entity *dfu; - - debug("%s: name: %s addr: 0x%x len: %d device: %s:%s\n", __func__, - dfu_entity_name, addr, len, interface, devstring); - - ret = dfu_init_env_entities(interface, devstring); - if (ret) - goto done; - - /* - * We need to copy name pointed by *dfu_entity_name since this text - * is the integral part of the FDT image. - * Any implicit modification (i.e. done by strsep()) will corrupt - * the FDT image and prevent other images to be stored. - */ - s = strdup(dfu_entity_name); - sb = s; - if (!s) { - ret = -ENOMEM; - goto done; - } - - strsep(&s, "@"); - debug("%s: image name: %s strlen: %zd\n", __func__, sb, strlen(sb)); - - alt_setting_num = dfu_get_alt(sb); - free(sb); - if (alt_setting_num < 0) { - pr_err("Alt setting [%d] to write not found!", - alt_setting_num); - ret = -ENODEV; - goto done; - } - - dfu = dfu_get_entity(alt_setting_num); - if (!dfu) { - pr_err("DFU entity for alt: %d not found!", alt_setting_num); - ret = -ENODEV; - goto done; - } - - ret = dfu_write_from_mem_addr(dfu, (void *)(uintptr_t)addr, len); - -done: - dfu_free_entities(); - - return ret; -} diff --git a/drivers/firmware/firmware-zynqmp.c b/drivers/firmware/firmware-zynqmp.c index 7583f24a..d4dc856 100644 --- a/drivers/firmware/firmware-zynqmp.c +++ b/drivers/firmware/firmware-zynqmp.c @@ -165,6 +165,14 @@ int __maybe_unused xilinx_pm_request(u32 api_id, u32 arg0, u32 arg1, u32 arg2, */ u32 regs[] = {api_id, arg0, arg1, arg2, arg3}; + if (api_id == PM_FPGA_LOAD) { + /* Swap addr_hi/low because of incompatibility */ + u32 temp = regs[1]; + + regs[1] = regs[2]; + regs[2] = temp; + } + ipi_req(regs, PAYLOAD_ARG_CNT, ret_payload, PAYLOAD_ARG_CNT); #else return -EPERM; diff --git a/drivers/gpio/mpc8xxx_gpio.c b/drivers/gpio/mpc8xxx_gpio.c index 1dfd225..27881a7 100644 --- a/drivers/gpio/mpc8xxx_gpio.c +++ b/drivers/gpio/mpc8xxx_gpio.c @@ -6,12 +6,15 @@ * based on arch/powerpc/include/asm/mpc85xx_gpio.h, which is * * Copyright 2010 eXMeritus, A Boeing Company + * Copyright 2020 NXP */ #include <common.h> #include <dm.h> #include <mapmem.h> #include <asm/gpio.h> +#include <asm/io.h> +#include <dm/of_access.h> struct ccsr_gpio { u32 gpdir; @@ -20,6 +23,7 @@ struct ccsr_gpio { u32 gpier; u32 gpimr; u32 gpicr; + u32 gpibe; }; struct mpc8xxx_gpio_data { @@ -35,6 +39,7 @@ struct mpc8xxx_gpio_data { */ u32 dat_shadow; ulong type; + bool little_endian; }; enum { @@ -47,33 +52,56 @@ inline u32 gpio_mask(uint gpio) return (1U << (31 - (gpio))); } -static inline u32 mpc8xxx_gpio_get_val(struct ccsr_gpio *base, u32 mask) +static inline u32 mpc8xxx_gpio_get_val(struct udevice *dev, u32 mask) { - return in_be32(&base->gpdat) & mask; + struct mpc8xxx_gpio_data *data = dev_get_priv(dev); + + if (data->little_endian) + return in_le32(&data->base->gpdat) & mask; + else + return in_be32(&data->base->gpdat) & mask; } -static inline u32 mpc8xxx_gpio_get_dir(struct ccsr_gpio *base, u32 mask) +static inline u32 mpc8xxx_gpio_get_dir(struct udevice *dev, u32 mask) { - return in_be32(&base->gpdir) & mask; + struct mpc8xxx_gpio_data *data = dev_get_priv(dev); + + if (data->little_endian) + return in_le32(&data->base->gpdir) & mask; + else + return in_be32(&data->base->gpdir) & mask; } -static inline int mpc8xxx_gpio_open_drain_val(struct ccsr_gpio *base, u32 mask) +static inline int mpc8xxx_gpio_open_drain_val(struct udevice *dev, u32 mask) { - return in_be32(&base->gpodr) & mask; + struct mpc8xxx_gpio_data *data = dev_get_priv(dev); + + if (data->little_endian) + return in_le32(&data->base->gpodr) & mask; + else + return in_be32(&data->base->gpodr) & mask; } -static inline void mpc8xxx_gpio_open_drain_on(struct ccsr_gpio *base, u32 +static inline void mpc8xxx_gpio_open_drain_on(struct udevice *dev, u32 gpios) { + struct mpc8xxx_gpio_data *data = dev_get_priv(dev); /* GPODR register 1 -> open drain on */ - setbits_be32(&base->gpodr, gpios); + if (data->little_endian) + setbits_le32(&data->base->gpodr, gpios); + else + setbits_be32(&data->base->gpodr, gpios); } -static inline void mpc8xxx_gpio_open_drain_off(struct ccsr_gpio *base, +static inline void mpc8xxx_gpio_open_drain_off(struct udevice *dev, u32 gpios) { + struct mpc8xxx_gpio_data *data = dev_get_priv(dev); /* GPODR register 0 -> open drain off (actively driven) */ - clrbits_be32(&base->gpodr, gpios); + if (data->little_endian) + clrbits_le32(&data->base->gpodr, gpios); + else + clrbits_be32(&data->base->gpodr, gpios); } static int mpc8xxx_gpio_direction_input(struct udevice *dev, uint gpio) @@ -82,7 +110,10 @@ static int mpc8xxx_gpio_direction_input(struct udevice *dev, uint gpio) u32 mask = gpio_mask(gpio); /* GPDIR register 0 -> input */ - clrbits_be32(&data->base->gpdir, mask); + if (data->little_endian) + clrbits_le32(&data->base->gpdir, mask); + else + clrbits_be32(&data->base->gpdir, mask); return 0; } @@ -100,10 +131,20 @@ static int mpc8xxx_gpio_set_value(struct udevice *dev, uint gpio, int value) data->dat_shadow &= ~mask; } - gpdir = in_be32(&base->gpdir); + if (data->little_endian) + gpdir = in_le32(&base->gpdir); + else + gpdir = in_be32(&base->gpdir); + gpdir |= gpio_mask(gpio); - out_be32(&base->gpdat, gpdir & data->dat_shadow); - out_be32(&base->gpdir, gpdir); + + if (data->little_endian) { + out_le32(&base->gpdat, gpdir & data->dat_shadow); + out_le32(&base->gpdir, gpdir); + } else { + out_be32(&base->gpdat, gpdir & data->dat_shadow); + out_be32(&base->gpdir, gpdir); + } return 0; } @@ -124,21 +165,20 @@ static int mpc8xxx_gpio_get_value(struct udevice *dev, uint gpio) { struct mpc8xxx_gpio_data *data = dev_get_priv(dev); - if (!!mpc8xxx_gpio_get_dir(data->base, gpio_mask(gpio))) { + if (!!mpc8xxx_gpio_get_dir(dev, gpio_mask(gpio))) { /* Output -> use shadowed value */ return !!(data->dat_shadow & gpio_mask(gpio)); } /* Input -> read value from GPDAT register */ - return !!mpc8xxx_gpio_get_val(data->base, gpio_mask(gpio)); + return !!mpc8xxx_gpio_get_val(dev, gpio_mask(gpio)); } static int mpc8xxx_gpio_get_function(struct udevice *dev, uint gpio) { - struct mpc8xxx_gpio_data *data = dev_get_priv(dev); int dir; - dir = !!mpc8xxx_gpio_get_dir(data->base, gpio_mask(gpio)); + dir = !!mpc8xxx_gpio_get_dir(dev, gpio_mask(gpio)); return dir ? GPIOF_OUTPUT : GPIOF_INPUT; } @@ -146,14 +186,33 @@ static int mpc8xxx_gpio_get_function(struct udevice *dev, uint gpio) static int mpc8xxx_gpio_ofdata_to_platdata(struct udevice *dev) { struct mpc8xxx_gpio_plat *plat = dev_get_platdata(dev); + struct mpc8xxx_gpio_data *data = dev_get_priv(dev); fdt_addr_t addr; - u32 reg[2]; + u32 i; + u32 reg[4]; + + if (ofnode_read_bool(dev->node, "little-endian")) + data->little_endian = true; + + if (data->little_endian) + dev_read_u32_array(dev, "reg", reg, 4); + else + dev_read_u32_array(dev, "reg", reg, 2); + + if (data->little_endian) { + for (i = 0; i < 2; i++) + reg[i] = be32_to_cpu(reg[i]); + } - dev_read_u32_array(dev, "reg", reg, 2); addr = dev_translate_address(dev, reg); plat->addr = addr; - plat->size = reg[1]; + + if (data->little_endian) + plat->size = reg[3]; + else + plat->size = reg[1]; + plat->ngpios = dev_read_u32_default(dev, "ngpios", 32); return 0; @@ -198,6 +257,13 @@ static int mpc8xxx_gpio_probe(struct udevice *dev) if (!str) return -ENOMEM; + if (ofnode_device_is_compatible(dev->node, "fsl,qoriq-gpio")) { + unsigned long gpibe = data->addr + sizeof(struct ccsr_gpio) + - sizeof(u32); + + out_be32((unsigned int *)gpibe, 0xffffffff); + } + uc_priv->bank_name = str; uc_priv->gpio_count = data->gpio_count; diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index bd248cb..b371980 100644 --- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -6,7 +6,7 @@ obj-$(CONFIG_DM_I2C) += i2c-uclass.o ifdef CONFIG_ACPIGEN obj-$(CONFIG_DM_I2C) += acpi_i2c.o endif -obj-$(CONFIG_DM_I2C_GPIO) += i2c-gpio.o +obj-$(CONFIG_$(SPL_)DM_I2C_GPIO) += i2c-gpio.o obj-$(CONFIG_$(SPL_)I2C_CROS_EC_TUNNEL) += cros_ec_tunnel.o obj-$(CONFIG_$(SPL_)I2C_CROS_EC_LDO) += cros_ec_ldo.o diff --git a/drivers/i2c/i2c-emul-uclass.c b/drivers/i2c/i2c-emul-uclass.c index 1b70e14..84b6a21 100644 --- a/drivers/i2c/i2c-emul-uclass.c +++ b/drivers/i2c/i2c-emul-uclass.c @@ -76,7 +76,9 @@ UCLASS_DRIVER(i2c_emul) = { UCLASS_DRIVER(i2c_emul_parent) = { .id = UCLASS_I2C_EMUL_PARENT, .name = "i2c_emul_parent", +#if !CONFIG_IS_ENABLED(OF_PLATDATA) .post_bind = dm_scan_fdt_dev, +#endif }; static const struct udevice_id i2c_emul_parent_ids[] = { diff --git a/drivers/i2c/sandbox_i2c.c b/drivers/i2c/sandbox_i2c.c index 57b1c60..2cbdaf9 100644 --- a/drivers/i2c/sandbox_i2c.c +++ b/drivers/i2c/sandbox_i2c.c @@ -93,8 +93,8 @@ static const struct udevice_id sandbox_i2c_ids[] = { { } }; -U_BOOT_DRIVER(i2c_sandbox) = { - .name = "i2c_sandbox", +U_BOOT_DRIVER(sandbox_i2c) = { + .name = "sandbox_i2c", .id = UCLASS_I2C, .of_match = sandbox_i2c_ids, .ops = &sandbox_i2c_ops, diff --git a/drivers/mailbox/zynqmp-ipi.c b/drivers/mailbox/zynqmp-ipi.c index 9483ed9..847a036 100644 --- a/drivers/mailbox/zynqmp-ipi.c +++ b/drivers/mailbox/zynqmp-ipi.c @@ -56,7 +56,7 @@ static int zynqmp_ipi_send(struct mbox_chan *chan, const void *data) /* Wait until observation bit is cleared */ ret = wait_for_bit_le32(&ipi_int_apu->obs, IPI_BIT_MASK_PMU0, false, - 100, false); + 1000, false); debug("%s, send %ld bytes\n", __func__, msg->len); return ret; diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index b67e906..29432ae 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -376,13 +376,6 @@ config SPL_I2C_EEPROM This option is an SPL-variant of the I2C_EEPROM option. See the help of I2C_EEPROM for details. -config ZYNQ_GEM_I2C_MAC_OFFSET - hex "Set the I2C MAC offset" - default 0x0 - depends on DM_I2C - help - Set the MAC offset for i2C. - if I2C_EEPROM config SYS_I2C_EEPROM_ADDR diff --git a/drivers/misc/irq-uclass.c b/drivers/misc/irq-uclass.c index 94fa233..24b2796 100644 --- a/drivers/misc/irq-uclass.c +++ b/drivers/misc/irq-uclass.c @@ -69,7 +69,7 @@ int irq_get_by_driver_info(struct udevice *dev, { int ret; - ret = device_get_by_driver_info(cells->node, &irq->dev); + ret = device_get_by_driver_info_idx(cells->idx, &irq->dev); if (ret) return ret; irq->id = cells->arg[0]; diff --git a/drivers/misc/p2sb-uclass.c b/drivers/misc/p2sb-uclass.c index b5219df..12abcff 100644 --- a/drivers/misc/p2sb-uclass.c +++ b/drivers/misc/p2sb-uclass.c @@ -174,19 +174,20 @@ int p2sb_set_port_id(struct udevice *dev, int portid) if (!CONFIG_IS_ENABLED(OF_PLATDATA)) return -ENOSYS; - uclass_find_first_device(UCLASS_P2SB, &ps2b); - if (!ps2b) - return -EDEADLK; - dev->parent = ps2b; - - /* - * We must allocate this, since when the device was bound it did not - * have a parent. - * TODO(sjg@chromium.org): Add a parent pointer to child devices in dtoc - */ - dev->parent_platdata = malloc(sizeof(*pplat)); - if (!dev->parent_platdata) - return -ENOMEM; + if (!CONFIG_IS_ENABLED(OF_PLATDATA_PARENT)) { + uclass_find_first_device(UCLASS_P2SB, &ps2b); + if (!ps2b) + return -EDEADLK; + dev->parent = ps2b; + + /* + * We must allocate this, since when the device was bound it did + * not have a parent. + */ + dev->parent_platdata = malloc(sizeof(*pplat)); + if (!dev->parent_platdata) + return -ENOMEM; + } pplat = dev_get_parent_platdata(dev); pplat->pid = portid; diff --git a/drivers/misc/spltest_sandbox.c b/drivers/misc/spltest_sandbox.c index 9990316..3ae6707 100644 --- a/drivers/misc/spltest_sandbox.c +++ b/drivers/misc/spltest_sandbox.c @@ -8,43 +8,8 @@ #include <dm.h> #include <dt-structs.h> -static int sandbox_spl_probe(struct udevice *dev) -{ - struct dtd_sandbox_spl_test *plat = dev_get_platdata(dev); - int i; - - printf("of-platdata probe:\n"); - printf("bool %d\n", plat->boolval); - - printf("byte %02x\n", plat->byteval); - printf("bytearray"); - for (i = 0; i < sizeof(plat->bytearray); i++) - printf(" %02x", plat->bytearray[i]); - printf("\n"); - - printf("int %d\n", plat->intval); - printf("intarray"); - for (i = 0; i < ARRAY_SIZE(plat->intarray); i++) - printf(" %d", plat->intarray[i]); - printf("\n"); - - printf("longbytearray"); - for (i = 0; i < sizeof(plat->longbytearray); i++) - printf(" %02x", plat->longbytearray[i]); - printf("\n"); - - printf("string %s\n", plat->stringval); - printf("stringarray"); - for (i = 0; i < ARRAY_SIZE(plat->stringarray); i++) - printf(" \"%s\"", plat->stringarray[i]); - printf("\n"); - - return 0; -} - U_BOOT_DRIVER(sandbox_spl_test) = { .name = "sandbox_spl_test", .id = UCLASS_MISC, .flags = DM_FLAG_PRE_RELOC, - .probe = sandbox_spl_probe, }; diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c index 1c015ab..22040c6 100644 --- a/drivers/mmc/fsl_esdhc_imx.c +++ b/drivers/mmc/fsl_esdhc_imx.c @@ -1504,12 +1504,9 @@ static int fsl_esdhc_probe(struct udevice *dev) if (CONFIG_IS_ENABLED(DM_GPIO) && !priv->non_removable) { struct udevice *gpiodev; - struct driver_info *info; - - info = (struct driver_info *)dtplat->cd_gpios->node; - - ret = device_get_by_driver_info(info, &gpiodev); + ret = device_get_by_driver_info_idx(dtplat->cd_gpios->idx, + &gpiodev); if (ret) return ret; diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c index d549a26..0628934 100644 --- a/drivers/mmc/sdhci.c +++ b/drivers/mmc/sdhci.c @@ -812,7 +812,8 @@ int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host, cfg->host_caps &= ~MMC_MODE_HS_52MHz; } - if (!(cfg->voltages & MMC_VDD_165_195)) + if (!(cfg->voltages & MMC_VDD_165_195) || + (host->quirks & SDHCI_QUIRK_NO_1_8_V)) caps_1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_DDR50); diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c index 775c17b..147ecc0 100644 --- a/drivers/mmc/zynq_sdhci.c +++ b/drivers/mmc/zynq_sdhci.c @@ -19,6 +19,20 @@ #include <sdhci.h> #include <zynqmp_tap_delay.h> +#define SDHCI_ARASAN_ITAPDLY_REGISTER 0xF0F8 +#define SDHCI_ARASAN_OTAPDLY_REGISTER 0xF0FC +#define SDHCI_ITAPDLY_CHGWIN 0x200 +#define SDHCI_ITAPDLY_ENABLE 0x100 +#define SDHCI_OTAPDLY_ENABLE 0x40 + +#define SDHCI_TUNING_LOOP_COUNT 40 +#define MMC_BANK2 0x2 + +struct arasan_sdhci_clk_data { + int clk_phase_in[MMC_TIMING_MMC_HS400 + 1]; + int clk_phase_out[MMC_TIMING_MMC_HS400 + 1]; +}; + struct arasan_sdhci_plat { struct mmc_config cfg; struct mmc mmc; @@ -26,29 +40,35 @@ struct arasan_sdhci_plat { struct arasan_sdhci_priv { struct sdhci_host *host; + struct arasan_sdhci_clk_data clk_data; u8 deviceid; u8 bank; + u8 no_1p8; }; -#if defined(CONFIG_ARCH_ZYNQMP) -#define MMC_HS200_BUS_SPEED 5 +#if defined(CONFIG_ARCH_ZYNQMP) || defined(CONFIG_ARCH_VERSAL) +/* Default settings for ZynqMP Clock Phases */ +const u32 zynqmp_iclk_phases[] = {0, 63, 63, 0, 63, 0, 0, 183, 54, 0, 0}; +const u32 zynqmp_oclk_phases[] = {0, 72, 60, 0, 60, 72, 135, 48, 72, 135, 0}; + +/* Default settings for Versal Clock Phases */ +const u32 versal_iclk_phases[] = {0, 132, 132, 0, 132, 0, 0, 162, 90, 0, 0}; +const u32 versal_oclk_phases[] = {0, 60, 48, 0, 48, 72, 90, 36, 60, 90, 0}; static const u8 mode2timing[] = { - [MMC_LEGACY] = UHS_SDR12_BUS_SPEED, - [MMC_HS] = HIGH_SPEED_BUS_SPEED, - [SD_HS] = HIGH_SPEED_BUS_SPEED, - [MMC_HS_52] = HIGH_SPEED_BUS_SPEED, - [MMC_DDR_52] = HIGH_SPEED_BUS_SPEED, - [UHS_SDR12] = UHS_SDR12_BUS_SPEED, - [UHS_SDR25] = UHS_SDR25_BUS_SPEED, - [UHS_SDR50] = UHS_SDR50_BUS_SPEED, - [UHS_DDR50] = UHS_DDR50_BUS_SPEED, - [UHS_SDR104] = UHS_SDR104_BUS_SPEED, - [MMC_HS_200] = MMC_HS200_BUS_SPEED, + [MMC_LEGACY] = MMC_TIMING_LEGACY, + [MMC_HS] = MMC_TIMING_MMC_HS, + [SD_HS] = MMC_TIMING_SD_HS, + [MMC_HS_52] = MMC_TIMING_UHS_SDR50, + [MMC_DDR_52] = MMC_TIMING_UHS_DDR50, + [UHS_SDR12] = MMC_TIMING_UHS_SDR12, + [UHS_SDR25] = MMC_TIMING_UHS_SDR25, + [UHS_SDR50] = MMC_TIMING_UHS_SDR50, + [UHS_DDR50] = MMC_TIMING_UHS_DDR50, + [UHS_SDR104] = MMC_TIMING_UHS_SDR104, + [MMC_HS_200] = MMC_TIMING_MMC_HS200, }; -#define SDHCI_TUNING_LOOP_COUNT 40 - static void arasan_zynqmp_dll_reset(struct sdhci_host *host, u8 deviceid) { u16 clk; @@ -156,17 +176,352 @@ static int arasan_sdhci_execute_tuning(struct mmc *mmc, u8 opcode) return 0; } +/** + * sdhci_zynqmp_sdcardclk_set_phase - Set the SD Output Clock Tap Delays + * + * Set the SD Output Clock Tap Delays for Output path + * + * @host: Pointer to the sdhci_host structure. + * @degrees: The clock phase shift between 0 - 359. + * Return: 0 on success and error value on error + */ +static int sdhci_zynqmp_sdcardclk_set_phase(struct sdhci_host *host, + int degrees) +{ + struct arasan_sdhci_priv *priv = dev_get_priv(host->mmc->dev); + struct mmc *mmc = (struct mmc *)host->mmc; + u8 tap_delay, tap_max = 0; + int ret; + int timing = mode2timing[mmc->selected_mode]; + + /* + * This is applicable for SDHCI_SPEC_300 and above + * ZynqMP does not set phase for <=25MHz clock. + * If degrees is zero, no need to do anything. + */ + if (SDHCI_GET_VERSION(host) < SDHCI_SPEC_300 || + timing == MMC_TIMING_LEGACY || + timing == MMC_TIMING_UHS_SDR12 || !degrees) + return 0; + + switch (timing) { + case MMC_TIMING_MMC_HS: + case MMC_TIMING_SD_HS: + case MMC_TIMING_UHS_SDR25: + case MMC_TIMING_UHS_DDR50: + case MMC_TIMING_MMC_DDR52: + /* For 50MHz clock, 30 Taps are available */ + tap_max = 30; + break; + case MMC_TIMING_UHS_SDR50: + /* For 100MHz clock, 15 Taps are available */ + tap_max = 15; + break; + case MMC_TIMING_UHS_SDR104: + case MMC_TIMING_MMC_HS200: + /* For 200MHz clock, 8 Taps are available */ + tap_max = 8; + default: + break; + } + + tap_delay = (degrees * tap_max) / 360; + + arasan_zynqmp_set_tapdelay(priv->deviceid, 0, tap_delay); + + return ret; +} + +/** + * sdhci_zynqmp_sampleclk_set_phase - Set the SD Input Clock Tap Delays + * + * Set the SD Input Clock Tap Delays for Input path + * + * @host: Pointer to the sdhci_host structure. + * @degrees: The clock phase shift between 0 - 359. + * Return: 0 on success and error value on error + */ +static int sdhci_zynqmp_sampleclk_set_phase(struct sdhci_host *host, + int degrees) +{ + struct arasan_sdhci_priv *priv = dev_get_priv(host->mmc->dev); + struct mmc *mmc = (struct mmc *)host->mmc; + u8 tap_delay, tap_max = 0; + int ret; + int timing = mode2timing[mmc->selected_mode]; + + /* + * This is applicable for SDHCI_SPEC_300 and above + * ZynqMP does not set phase for <=25MHz clock. + * If degrees is zero, no need to do anything. + */ + if (SDHCI_GET_VERSION(host) < SDHCI_SPEC_300 || + timing == MMC_TIMING_LEGACY || + timing == MMC_TIMING_UHS_SDR12 || !degrees) + return 0; + + switch (timing) { + case MMC_TIMING_MMC_HS: + case MMC_TIMING_SD_HS: + case MMC_TIMING_UHS_SDR25: + case MMC_TIMING_UHS_DDR50: + case MMC_TIMING_MMC_DDR52: + /* For 50MHz clock, 120 Taps are available */ + tap_max = 120; + break; + case MMC_TIMING_UHS_SDR50: + /* For 100MHz clock, 60 Taps are available */ + tap_max = 60; + break; + case MMC_TIMING_UHS_SDR104: + case MMC_TIMING_MMC_HS200: + /* For 200MHz clock, 30 Taps are available */ + tap_max = 30; + default: + break; + } + + tap_delay = (degrees * tap_max) / 360; + + arasan_zynqmp_set_tapdelay(priv->deviceid, tap_delay, 0); + + return ret; +} + +/** + * sdhci_versal_sdcardclk_set_phase - Set the SD Output Clock Tap Delays + * + * Set the SD Output Clock Tap Delays for Output path + * + * @host: Pointer to the sdhci_host structure. + * @degrees The clock phase shift between 0 - 359. + * Return: 0 on success and error value on error + */ +static int sdhci_versal_sdcardclk_set_phase(struct sdhci_host *host, + int degrees) +{ + struct mmc *mmc = (struct mmc *)host->mmc; + u8 tap_delay, tap_max = 0; + int ret; + int timing = mode2timing[mmc->selected_mode]; + + /* + * This is applicable for SDHCI_SPEC_300 and above + * Versal does not set phase for <=25MHz clock. + * If degrees is zero, no need to do anything. + */ + if (SDHCI_GET_VERSION(host) < SDHCI_SPEC_300 || + timing == MMC_TIMING_LEGACY || + timing == MMC_TIMING_UHS_SDR12 || !degrees) + return 0; + + switch (timing) { + case MMC_TIMING_MMC_HS: + case MMC_TIMING_SD_HS: + case MMC_TIMING_UHS_SDR25: + case MMC_TIMING_UHS_DDR50: + case MMC_TIMING_MMC_DDR52: + /* For 50MHz clock, 30 Taps are available */ + tap_max = 30; + break; + case MMC_TIMING_UHS_SDR50: + /* For 100MHz clock, 15 Taps are available */ + tap_max = 15; + break; + case MMC_TIMING_UHS_SDR104: + case MMC_TIMING_MMC_HS200: + /* For 200MHz clock, 8 Taps are available */ + tap_max = 8; + default: + break; + } + + tap_delay = (degrees * tap_max) / 360; + + /* Set the Clock Phase */ + if (tap_delay) { + u32 regval; + + regval = sdhci_readl(host, SDHCI_ARASAN_OTAPDLY_REGISTER); + regval |= SDHCI_OTAPDLY_ENABLE; + sdhci_writel(host, regval, SDHCI_ARASAN_OTAPDLY_REGISTER); + regval |= tap_delay; + sdhci_writel(host, regval, SDHCI_ARASAN_OTAPDLY_REGISTER); + } + + return ret; +} + +/** + * sdhci_versal_sampleclk_set_phase - Set the SD Input Clock Tap Delays + * + * Set the SD Input Clock Tap Delays for Input path + * + * @host: Pointer to the sdhci_host structure. + * @degrees The clock phase shift between 0 - 359. + * Return: 0 on success and error value on error + */ +static int sdhci_versal_sampleclk_set_phase(struct sdhci_host *host, + int degrees) +{ + struct mmc *mmc = (struct mmc *)host->mmc; + u8 tap_delay, tap_max = 0; + int ret; + int timing = mode2timing[mmc->selected_mode]; + + /* + * This is applicable for SDHCI_SPEC_300 and above + * Versal does not set phase for <=25MHz clock. + * If degrees is zero, no need to do anything. + */ + if (SDHCI_GET_VERSION(host) < SDHCI_SPEC_300 || + timing == MMC_TIMING_LEGACY || + timing == MMC_TIMING_UHS_SDR12 || !degrees) + return 0; + + switch (timing) { + case MMC_TIMING_MMC_HS: + case MMC_TIMING_SD_HS: + case MMC_TIMING_UHS_SDR25: + case MMC_TIMING_UHS_DDR50: + case MMC_TIMING_MMC_DDR52: + /* For 50MHz clock, 120 Taps are available */ + tap_max = 120; + break; + case MMC_TIMING_UHS_SDR50: + /* For 100MHz clock, 60 Taps are available */ + tap_max = 60; + break; + case MMC_TIMING_UHS_SDR104: + case MMC_TIMING_MMC_HS200: + /* For 200MHz clock, 30 Taps are available */ + tap_max = 30; + default: + break; + } + + tap_delay = (degrees * tap_max) / 360; + + /* Set the Clock Phase */ + if (tap_delay) { + u32 regval; + + regval = sdhci_readl(host, SDHCI_ARASAN_ITAPDLY_REGISTER); + regval |= SDHCI_ITAPDLY_CHGWIN; + sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER); + regval |= SDHCI_ITAPDLY_ENABLE; + sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER); + regval |= tap_delay; + sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER); + regval &= ~SDHCI_ITAPDLY_CHGWIN; + sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER); + } + + return ret; +} + static void arasan_sdhci_set_tapdelay(struct sdhci_host *host) { struct arasan_sdhci_priv *priv = dev_get_priv(host->mmc->dev); + struct arasan_sdhci_clk_data *clk_data = &priv->clk_data; struct mmc *mmc = (struct mmc *)host->mmc; - u8 uhsmode; + struct udevice *dev = mmc->dev; + u8 timing = mode2timing[mmc->selected_mode]; + u32 iclk_phase = clk_data->clk_phase_in[timing]; + u32 oclk_phase = clk_data->clk_phase_out[timing]; + + dev_dbg(dev, "%s, host:%s, mode:%d\n", __func__, host->name, timing); + + if (IS_ENABLED(CONFIG_ARCH_ZYNQMP) && + device_is_compatible(dev, "xlnx,zynqmp-8.9a")) { + sdhci_zynqmp_sampleclk_set_phase(host, iclk_phase); + sdhci_zynqmp_sdcardclk_set_phase(host, oclk_phase); + } else if (IS_ENABLED(CONFIG_ARCH_VERSAL) && + device_is_compatible(dev, "xlnx,versal-8.9a")) { + sdhci_versal_sampleclk_set_phase(host, iclk_phase); + sdhci_versal_sdcardclk_set_phase(host, oclk_phase); + } +} - uhsmode = mode2timing[mmc->selected_mode]; +static void arasan_dt_read_clk_phase(struct udevice *dev, unsigned char timing, + const char *prop) +{ + struct arasan_sdhci_priv *priv = dev_get_priv(dev); + struct arasan_sdhci_clk_data *clk_data = &priv->clk_data; + u32 clk_phase[2] = {0}; + + /* + * Read Tap Delay values from DT, if the DT does not contain the + * Tap Values then use the pre-defined values + */ + if (dev_read_u32_array(dev, prop, &clk_phase[0], 2)) { + dev_dbg(dev, "Using predefined clock phase for %s = %d %d\n", + prop, clk_data->clk_phase_in[timing], + clk_data->clk_phase_out[timing]); + return; + } - if (uhsmode >= UHS_SDR25_BUS_SPEED) - arasan_zynqmp_set_tapdelay(priv->deviceid, uhsmode, - priv->bank); + /* The values read are Input and Output Clock Delays in order */ + clk_data->clk_phase_in[timing] = clk_phase[0]; + clk_data->clk_phase_out[timing] = clk_phase[1]; +} + +/** + * arasan_dt_parse_clk_phases - Read Tap Delay values from DT + * + * Called at initialization to parse the values of Tap Delays. + * + * @dev: Pointer to our struct udevice. + */ +static void arasan_dt_parse_clk_phases(struct udevice *dev) +{ + struct arasan_sdhci_priv *priv = dev_get_priv(dev); + struct arasan_sdhci_clk_data *clk_data = &priv->clk_data; + int i; + + if (IS_ENABLED(CONFIG_ARCH_ZYNQMP) && + device_is_compatible(dev, "xlnx,zynqmp-8.9a")) { + for (i = 0; i <= MMC_TIMING_MMC_HS400; i++) { + clk_data->clk_phase_in[i] = zynqmp_iclk_phases[i]; + clk_data->clk_phase_out[i] = zynqmp_oclk_phases[i]; + } + + if (priv->bank == MMC_BANK2) { + clk_data->clk_phase_out[MMC_TIMING_UHS_SDR104] = 90; + clk_data->clk_phase_out[MMC_TIMING_MMC_HS200] = 90; + } + } + + if (IS_ENABLED(CONFIG_ARCH_VERSAL) && + device_is_compatible(dev, "xlnx,versal-8.9a")) { + for (i = 0; i <= MMC_TIMING_MMC_HS400; i++) { + clk_data->clk_phase_in[i] = versal_iclk_phases[i]; + clk_data->clk_phase_out[i] = versal_oclk_phases[i]; + } + } + + arasan_dt_read_clk_phase(dev, MMC_TIMING_LEGACY, + "clk-phase-legacy"); + arasan_dt_read_clk_phase(dev, MMC_TIMING_MMC_HS, + "clk-phase-mmc-hs"); + arasan_dt_read_clk_phase(dev, MMC_TIMING_SD_HS, + "clk-phase-sd-hs"); + arasan_dt_read_clk_phase(dev, MMC_TIMING_UHS_SDR12, + "clk-phase-uhs-sdr12"); + arasan_dt_read_clk_phase(dev, MMC_TIMING_UHS_SDR25, + "clk-phase-uhs-sdr25"); + arasan_dt_read_clk_phase(dev, MMC_TIMING_UHS_SDR50, + "clk-phase-uhs-sdr50"); + arasan_dt_read_clk_phase(dev, MMC_TIMING_UHS_SDR104, + "clk-phase-uhs-sdr104"); + arasan_dt_read_clk_phase(dev, MMC_TIMING_UHS_DDR50, + "clk-phase-uhs-ddr50"); + arasan_dt_read_clk_phase(dev, MMC_TIMING_MMC_DDR52, + "clk-phase-mmc-ddr52"); + arasan_dt_read_clk_phase(dev, MMC_TIMING_MMC_HS200, + "clk-phase-mmc-hs200"); + arasan_dt_read_clk_phase(dev, MMC_TIMING_MMC_HS400, + "clk-phase-mmc-hs400"); } static void arasan_sdhci_set_control_reg(struct sdhci_host *host) @@ -184,12 +539,10 @@ static void arasan_sdhci_set_control_reg(struct sdhci_host *host) } if (mmc->selected_mode > SD_HS && - mmc->selected_mode <= UHS_DDR50) + mmc->selected_mode <= MMC_HS_200) sdhci_set_uhs_timing(host); } -#endif -#if defined(CONFIG_ARCH_ZYNQMP) const struct sdhci_ops arasan_ops = { .platform_execute_tuning = &arasan_sdhci_execute_tuning, .set_delay = &arasan_sdhci_set_tapdelay, @@ -236,6 +589,9 @@ static int arasan_sdhci_probe(struct udevice *dev) host->quirks |= SDHCI_QUIRK_BROKEN_HISPD_MODE; #endif + if (priv->no_1p8) + host->quirks |= SDHCI_QUIRK_NO_1_8_V; + plat->cfg.f_max = CONFIG_ZYNQ_SDHCI_MAX_FREQ; ret = mmc_of_parse(dev, &plat->cfg); @@ -267,8 +623,9 @@ static int arasan_sdhci_ofdata_to_platdata(struct udevice *dev) priv->host->name = dev->name; -#if defined(CONFIG_ARCH_ZYNQMP) +#if defined(CONFIG_ARCH_ZYNQMP) || defined(CONFIG_ARCH_VERSAL) priv->host->ops = &arasan_ops; + arasan_dt_parse_clk_phases(dev); #endif priv->host->ioaddr = (void *)dev_read_addr(dev); @@ -277,6 +634,7 @@ static int arasan_sdhci_ofdata_to_platdata(struct udevice *dev) priv->deviceid = dev_read_u32_default(dev, "xlnx,device_id", -1); priv->bank = dev_read_u32_default(dev, "xlnx,mio-bank", 0); + priv->no_1p8 = dev_read_bool(dev, "no-1-8-v"); return 0; } diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index cd7e598..3cf3b14 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -195,6 +195,9 @@ endif config NAND_PXA3XX bool "Support for NAND on PXA3xx and Armada 370/XP/38x" select SYS_NAND_SELF_INIT + select DM_MTD + select REGMAP + select SYSCON imply CMD_NAND help This enables the driver for the NAND flash device found on diff --git a/drivers/mtd/nand/raw/pxa3xx_nand.c b/drivers/mtd/nand/raw/pxa3xx_nand.c index 5fb3081..361a9e3 100644 --- a/drivers/mtd/nand/raw/pxa3xx_nand.c +++ b/drivers/mtd/nand/raw/pxa3xx_nand.c @@ -22,6 +22,10 @@ #include <linux/mtd/mtd.h> #include <linux/mtd/rawnand.h> #include <linux/types.h> +#include <syscon.h> +#include <regmap.h> +#include <dm/uclass.h> +#include <dm/read.h> #include "pxa3xx_nand.h" @@ -117,6 +121,10 @@ DECLARE_GLOBAL_DATA_PTR; #define EXT_CMD_TYPE_LAST_RW 1 /* Last naked read/write */ #define EXT_CMD_TYPE_MONO 0 /* Monolithic read/write */ +/* System control register and bit to enable NAND on some SoCs */ +#define GENCONF_SOC_DEVICE_MUX 0x208 +#define GENCONF_SOC_DEVICE_MUX_NFC_EN BIT(0) + /* * This should be large enough to read 'ONFI' and 'JEDEC'. * Let's use 7 bytes, which is the maximum ID count supported @@ -157,6 +165,7 @@ enum { enum pxa3xx_nand_variant { PXA3XX_NAND_VARIANT_PXA, PXA3XX_NAND_VARIANT_ARMADA370, + PXA3XX_NAND_VARIANT_ARMADA_8K, }; struct pxa3xx_nand_host { @@ -417,10 +426,21 @@ static struct nand_ecclayout ecc_layout_8KB_bch8bit = { /* convert nano-seconds to nand flash controller clock cycles */ #define ns2cycle(ns, clk) (int)((ns) * (clk / 1000000) / 1000) -static enum pxa3xx_nand_variant pxa3xx_nand_get_variant(void) +static const struct udevice_id pxa3xx_nand_dt_ids[] = { + { + .compatible = "marvell,mvebu-pxa3xx-nand", + .data = PXA3XX_NAND_VARIANT_ARMADA370, + }, + { + .compatible = "marvell,armada-8k-nand-controller", + .data = PXA3XX_NAND_VARIANT_ARMADA_8K, + }, + {} +}; + +static enum pxa3xx_nand_variant pxa3xx_nand_get_variant(struct udevice *dev) { - /* We only support the Armada 370/XP/38x for now */ - return PXA3XX_NAND_VARIANT_ARMADA370; + return dev_get_driver_data(dev); } static void pxa3xx_nand_set_timing(struct pxa3xx_nand_host *host, @@ -697,7 +717,8 @@ static irqreturn_t pxa3xx_nand_irq(struct pxa3xx_nand_info *info) info->retcode = ERR_UNCORERR; if (status & NDSR_CORERR) { info->retcode = ERR_CORERR; - if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370 && + if ((info->variant == PXA3XX_NAND_VARIANT_ARMADA370 || + info->variant == PXA3XX_NAND_VARIANT_ARMADA_8K) && info->ecc_bch) info->ecc_err_cnt = NDSR_ERR_CNT(status); else @@ -752,7 +773,8 @@ static irqreturn_t pxa3xx_nand_irq(struct pxa3xx_nand_info *info) nand_writel(info, NDCB0, info->ndcb2); /* NDCB3 register is available in NFCv2 (Armada 370/XP SoC) */ - if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370) + if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370 || + info->variant == PXA3XX_NAND_VARIANT_ARMADA_8K) nand_writel(info, NDCB0, info->ndcb3); } @@ -1666,7 +1688,8 @@ static int pxa3xx_nand_scan(struct mtd_info *mtd) } /* Device detection must be done with ECC disabled */ - if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370) + if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370 || + info->variant == PXA3XX_NAND_VARIANT_ARMADA_8K) nand_writel(info, NDECCCTRL, 0x0); if (nand_scan_ident(mtd, 1, NULL)) @@ -1716,7 +1739,8 @@ static int pxa3xx_nand_scan(struct mtd_info *mtd) * (aka split) command handling, */ if (mtd->writesize > info->chunk_size) { - if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370) { + if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370 || + info->variant == PXA3XX_NAND_VARIANT_ARMADA_8K) { chip->cmdfunc = nand_cmdfunc_extended; } else { dev_err(mtd->dev, @@ -1752,19 +1776,19 @@ static int pxa3xx_nand_scan(struct mtd_info *mtd) return nand_scan_tail(mtd); } -static int alloc_nand_resource(struct pxa3xx_nand_info *info) +static int alloc_nand_resource(struct udevice *dev, struct pxa3xx_nand_info *info) { struct pxa3xx_nand_platform_data *pdata; struct pxa3xx_nand_host *host; struct nand_chip *chip = NULL; struct mtd_info *mtd; - int ret, cs; + int cs; pdata = info->pdata; if (pdata->num_cs <= 0) return -ENODEV; - info->variant = pxa3xx_nand_get_variant(); + info->variant = pxa3xx_nand_get_variant(dev); for (cs = 0; cs < pdata->num_cs; cs++) { chip = (struct nand_chip *) ((u8 *)&info[1] + sizeof(*host) * cs); @@ -1794,97 +1818,87 @@ static int alloc_nand_resource(struct pxa3xx_nand_info *info) /* Allocate a buffer to allow flash detection */ info->buf_size = INIT_BUFFER_SIZE; info->data_buff = kmalloc(info->buf_size, GFP_KERNEL); - if (info->data_buff == NULL) { - ret = -ENOMEM; - goto fail_disable_clk; - } + if (info->data_buff == NULL) + return -ENOMEM; /* initialize all interrupts to be disabled */ disable_int(info, NDSR_MASK); - return 0; + /* + * Some SoCs like A7k/A8k need to enable manually the NAND + * controller to avoid being bootloader dependent. This is done + * through the use of a single bit in the System Functions registers. + */ + if (pxa3xx_nand_get_variant(dev) == PXA3XX_NAND_VARIANT_ARMADA_8K) { + struct regmap *sysctrl_base = syscon_regmap_lookup_by_phandle( + dev, "marvell,system-controller"); + u32 reg; - kfree(info->data_buff); -fail_disable_clk: - return ret; + if (IS_ERR(sysctrl_base)) + return PTR_ERR(sysctrl_base); + + regmap_read(sysctrl_base, GENCONF_SOC_DEVICE_MUX, ®); + reg |= GENCONF_SOC_DEVICE_MUX_NFC_EN; + regmap_write(sysctrl_base, GENCONF_SOC_DEVICE_MUX, reg); + } + + return 0; } -static int pxa3xx_nand_probe_dt(struct pxa3xx_nand_info *info) +static int pxa3xx_nand_probe_dt(struct udevice *dev, struct pxa3xx_nand_info *info) { struct pxa3xx_nand_platform_data *pdata; - const void *blob = gd->fdt_blob; - int node = -1; pdata = kzalloc(sizeof(*pdata), GFP_KERNEL); if (!pdata) return -ENOMEM; - /* Get address decoding nodes from the FDT blob */ - do { - node = fdt_node_offset_by_compatible(blob, node, - "marvell,mvebu-pxa3xx-nand"); - if (node < 0) - break; - - /* Bypass disabeld nodes */ - if (!fdtdec_get_is_enabled(blob, node)) - continue; - - /* Get the first enabled NAND controler base address */ - info->mmio_base = - (void __iomem *)fdtdec_get_addr_size_auto_noparent( - blob, node, "reg", 0, NULL, true); + info->mmio_base = dev_read_addr_ptr(dev); - pdata->num_cs = fdtdec_get_int(blob, node, "num-cs", 1); - if (pdata->num_cs != 1) { - pr_err("pxa3xx driver supports single CS only\n"); - break; - } - - if (fdtdec_get_bool(blob, node, "nand-enable-arbiter")) - pdata->enable_arbiter = 1; - - if (fdtdec_get_bool(blob, node, "nand-keep-config")) - pdata->keep_config = 1; + pdata->num_cs = dev_read_u32_default(dev, "num-cs", 1); + if (pdata->num_cs != 1) { + pr_err("pxa3xx driver supports single CS only\n"); + return -EINVAL; + } - /* - * ECC parameters. - * If these are not set, they will be selected according - * to the detected flash type. - */ - /* ECC strength */ - pdata->ecc_strength = fdtdec_get_int(blob, node, - "nand-ecc-strength", 0); + if (dev_read_bool(dev, "nand-enable-arbiter")) + pdata->enable_arbiter = 1; - /* ECC step size */ - pdata->ecc_step_size = fdtdec_get_int(blob, node, - "nand-ecc-step-size", 0); + if (dev_read_bool(dev, "nand-keep-config")) + pdata->keep_config = 1; - info->pdata = pdata; + /* + * ECC parameters. + * If these are not set, they will be selected according + * to the detected flash type. + */ + /* ECC strength */ + pdata->ecc_strength = dev_read_u32_default(dev, "nand-ecc-strength", 0); - /* Currently support only a single NAND controller */ - return 0; + /* ECC step size */ + pdata->ecc_step_size = dev_read_u32_default(dev, "nand-ecc-step-size", + 0); - } while (node >= 0); + info->pdata = pdata; - return -EINVAL; + return 0; } -static int pxa3xx_nand_probe(struct pxa3xx_nand_info *info) +static int pxa3xx_nand_probe(struct udevice *dev) { - struct mtd_info *mtd = &info->controller.active->mtd; struct pxa3xx_nand_platform_data *pdata; int ret, cs, probe_success; + struct pxa3xx_nand_info *info = dev_get_priv(dev); - ret = pxa3xx_nand_probe_dt(info); + ret = pxa3xx_nand_probe_dt(dev, info); if (ret) return ret; pdata = info->pdata; - ret = alloc_nand_resource(info); + ret = alloc_nand_resource(dev, info); if (ret) { - dev_err(mtd->dev, "alloc nand resource failed\n"); + dev_err(dev, "alloc nand resource failed\n"); return ret; } @@ -1918,22 +1932,24 @@ static int pxa3xx_nand_probe(struct pxa3xx_nand_info *info) return 0; } -/* - * Main initialization routine - */ +U_BOOT_DRIVER(pxa3xx_nand) = { + .name = "pxa3xx-nand", + .id = UCLASS_MTD, + .of_match = pxa3xx_nand_dt_ids, + .probe = pxa3xx_nand_probe, + .priv_auto_alloc_size = sizeof(struct pxa3xx_nand_info) + + sizeof(struct pxa3xx_nand_host) * CONFIG_SYS_MAX_NAND_DEVICE, +}; + void board_nand_init(void) { - struct pxa3xx_nand_info *info; - struct pxa3xx_nand_host *host; + struct udevice *dev; int ret; - info = kzalloc(sizeof(*info) + - sizeof(*host) * CONFIG_SYS_MAX_NAND_DEVICE, - GFP_KERNEL); - if (!info) - return; - - ret = pxa3xx_nand_probe(info); - if (ret) - return; + ret = uclass_get_device_by_driver(UCLASS_MTD, + DM_GET_DRIVER(pxa3xx_nand), &dev); + if (ret && ret != -ENODEV) { + pr_err("Failed to initialize %s. (error %d)\n", dev->name, + ret); + } } diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h index dabd40a..9ceff0e 100644 --- a/drivers/mtd/spi/sf_internal.h +++ b/drivers/mtd/spi/sf_internal.h @@ -67,7 +67,7 @@ struct flash_info { #define SPI_NOR_SKIP_SFDP BIT(13) /* Skip parsing of SFDP tables */ #define USE_CLSR BIT(14) /* use CLSR command */ #define SPI_NOR_HAS_SST26LOCK BIT(15) /* Flash supports lock/unlock via BPR */ -#define SPI_NOR_OCTAL_READ BIT(16) /* Flash supports Octal Read */ +#define SPI_NOR_OCTAL_READ BIT(16) /* Flash supports Octal Read */ }; extern const struct flash_info spi_nor_ids[]; diff --git a/drivers/net/ldpaa_eth/lx2160a.c b/drivers/net/ldpaa_eth/lx2160a.c index 1e62c64..e57f1a1 100644 --- a/drivers/net/ldpaa_eth/lx2160a.c +++ b/drivers/net/ldpaa_eth/lx2160a.c @@ -92,7 +92,7 @@ void fsl_rgmii_init(void) & FSL_CHASSIS3_EC1_REGSR_PRTCL_MASK; ec >>= FSL_CHASSIS3_EC1_REGSR_PRTCL_SHIFT; - if (!ec && (wriop_is_enabled_dpmac(17) == -ENODEV)) + if (!ec) wriop_init_dpmac_enet_if(17, PHY_INTERFACE_MODE_RGMII_ID); #endif @@ -101,7 +101,7 @@ void fsl_rgmii_init(void) & FSL_CHASSIS3_EC2_REGSR_PRTCL_MASK; ec >>= FSL_CHASSIS3_EC2_REGSR_PRTCL_SHIFT; - if (!ec && (wriop_is_enabled_dpmac(18) == -ENODEV)) + if (!ec) wriop_init_dpmac_enet_if(18, PHY_INTERFACE_MODE_RGMII_ID); #endif } diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig index dd1cc65..af92784 100644 --- a/drivers/pci/Kconfig +++ b/drivers/pci/Kconfig @@ -179,6 +179,18 @@ config PCIE_LAYERSCAPE_RC configured to Root Complex mode by clearing the corresponding bit of RCW[HOST_AGT_PEX]. +config PCI_IOMMU_EXTRA_MAPPINGS + bool "Support for specifying extra IOMMU mappings for PCI" + depends on PCIE_LAYERSCAPE_RC + help + Enable support for specifying extra IOMMU mappings for PCI + controllers through a special env var called "pci_iommu_extra" or + through a device tree property named "pci-iommu-extra" placed in + the node describing the PCI controller. + The intent is to cover SR-IOV scenarios which need mappings for VFs + and PCI hot-plug scenarios. More documentation can be found under: + arch/arm/cpu/armv8/fsl-layerscape/doc/README.pci_iommu_extra + config PCIE_LAYERSCAPE_EP bool "Layerscape PCIe Endpoint mode support" depends on DM_PCI diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c index ab33459..fb50b8f 100644 --- a/drivers/pci/pcie_fsl.c +++ b/drivers/pci/pcie_fsl.c @@ -396,6 +396,19 @@ static int fsl_pcie_init_atmu(struct fsl_pcie *pcie) return 0; } +static void fsl_pcie_dbi_read_only_reg_write_enable(struct fsl_pcie *pcie, + bool enable) +{ + u32 val; + + fsl_pcie_hose_read_config_dword(pcie, DBI_RO_WR_EN, &val); + if (enable) + val |= 1; + else + val &= ~1; + fsl_pcie_hose_write_config_dword(pcie, DBI_RO_WR_EN, val); +} + static int fsl_pcie_init_port(struct fsl_pcie *pcie) { ccsr_fsl_pci_t *regs = pcie->regs; @@ -470,7 +483,7 @@ static int fsl_pcie_init_port(struct fsl_pcie *pcie) * Set to 0 to protect the read-only registers. */ #ifdef CONFIG_SYS_FSL_ERRATUM_A007815 - clrbits_be32(®s->dbi_ro_wr_en, 0x01); + fsl_pcie_dbi_read_only_reg_write_enable(pcie, false); #endif /* @@ -504,13 +517,12 @@ static int fsl_pcie_init_port(struct fsl_pcie *pcie) static int fsl_pcie_fixup_classcode(struct fsl_pcie *pcie) { - ccsr_fsl_pci_t *regs = pcie->regs; u32 classcode_reg; u32 val; if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) { classcode_reg = PCI_CLASS_REVISION; - setbits_be32(®s->dbi_ro_wr_en, 0x01); + fsl_pcie_dbi_read_only_reg_write_enable(pcie, true); } else { classcode_reg = CSR_CLASSCODE; } @@ -521,7 +533,7 @@ static int fsl_pcie_fixup_classcode(struct fsl_pcie *pcie) fsl_pcie_hose_write_config_dword(pcie, classcode_reg, val); if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) - clrbits_be32(®s->dbi_ro_wr_en, 0x01); + fsl_pcie_dbi_read_only_reg_write_enable(pcie, false); return 0; } diff --git a/drivers/pci/pcie_fsl.h b/drivers/pci/pcie_fsl.h index dc8368d..70c5f4e 100644 --- a/drivers/pci/pcie_fsl.h +++ b/drivers/pci/pcie_fsl.h @@ -26,6 +26,8 @@ /* PCIe Link Status Register */ #define PCI_LSR (FSL_PCIE_CAP_ID + 0x12) +#define DBI_RO_WR_EN 0x8bc + #ifndef CONFIG_SYS_PCI_MEMORY_BUS #define CONFIG_SYS_PCI_MEMORY_BUS 0 #endif diff --git a/drivers/pci/pcie_layerscape_fixup.c b/drivers/pci/pcie_layerscape_fixup.c index 1709cd3..c75cf26 100644 --- a/drivers/pci/pcie_layerscape_fixup.c +++ b/drivers/pci/pcie_layerscape_fixup.c @@ -19,9 +19,39 @@ #ifdef CONFIG_ARM #include <asm/arch/clock.h> #endif +#include <malloc.h> +#include <env.h> #include "pcie_layerscape.h" #include "pcie_layerscape_fixup_common.h" +static int fdt_pcie_get_nodeoffset(void *blob, struct ls_pcie_rc *pcie_rc) +{ + int nodeoffset; + uint svr; + char *compat = NULL; + + /* find pci controller node */ + nodeoffset = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie", + pcie_rc->dbi_res.start); + if (nodeoffset < 0) { +#ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */ + svr = (get_svr() >> SVR_VAR_PER_SHIFT) & 0xFFFFFE; + if (svr == SVR_LS2088A || svr == SVR_LS2084A || + svr == SVR_LS2048A || svr == SVR_LS2044A || + svr == SVR_LS2081A || svr == SVR_LS2041A) + compat = "fsl,ls2088a-pcie"; + else + compat = CONFIG_FSL_PCIE_COMPAT; + + nodeoffset = + fdt_node_offset_by_compat_reg(blob, compat, + pcie_rc->dbi_res.start); +#endif + } + + return nodeoffset; +} + #if defined(CONFIG_FSL_LSCH3) || defined(CONFIG_FSL_LSCH2) /* * Return next available LUT index. @@ -127,30 +157,11 @@ static void fdt_pcie_set_iommu_map_entry_ls(void *blob, u32 iommu_map[4]; int nodeoffset; int lenp; - uint svr; - char *compat = NULL; struct ls_pcie *pcie = pcie_rc->pcie; - /* find pci controller node */ - nodeoffset = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie", - pcie_rc->dbi_res.start); - if (nodeoffset < 0) { -#ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */ - svr = (get_svr() >> SVR_VAR_PER_SHIFT) & 0xFFFFFE; - if (svr == SVR_LS2088A || svr == SVR_LS2084A || - svr == SVR_LS2048A || svr == SVR_LS2044A || - svr == SVR_LS2081A || svr == SVR_LS2041A) - compat = "fsl,ls2088a-pcie"; - else - compat = CONFIG_FSL_PCIE_COMPAT; - - if (compat) - nodeoffset = fdt_node_offset_by_compat_reg(blob, - compat, pcie_rc->dbi_res.start); -#endif - if (nodeoffset < 0) - return; - } + nodeoffset = fdt_pcie_get_nodeoffset(blob, pcie_rc); + if (nodeoffset < 0) + return; /* get phandle to iommu controller */ prop = fdt_getprop_w(blob, nodeoffset, "iommu-map", &lenp); @@ -174,13 +185,323 @@ static void fdt_pcie_set_iommu_map_entry_ls(void *blob, } } +static int fdt_fixup_pcie_device_ls(void *blob, pci_dev_t bdf, + struct ls_pcie_rc *pcie_rc) +{ + int streamid, index; + + streamid = pcie_next_streamid(pcie_rc->stream_id_cur, + pcie_rc->pcie->idx); + if (streamid < 0) { + printf("ERROR: out of stream ids for BDF %d.%d.%d\n", + PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf)); + return -ENOENT; + } + pcie_rc->stream_id_cur++; + + index = ls_pcie_next_lut_index(pcie_rc); + if (index < 0) { + printf("ERROR: out of LUT indexes for BDF %d.%d.%d\n", + PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf)); + return -ENOENT; + } + + /* map PCI b.d.f to streamID in LUT */ + ls_pcie_lut_set_mapping(pcie_rc, index, bdf >> 8, streamid); + /* update msi-map in device tree */ + fdt_pcie_set_msi_map_entry_ls(blob, pcie_rc, bdf >> 8, streamid); + /* update iommu-map in device tree */ + fdt_pcie_set_iommu_map_entry_ls(blob, pcie_rc, bdf >> 8, streamid); + + return 0; +} + +struct extra_iommu_entry { + int action; + pci_dev_t bdf; + int num_vfs; + bool noari; +}; + +#define EXTRA_IOMMU_ENTRY_HOTPLUG 1 +#define EXTRA_IOMMU_ENTRY_VFS 2 + +static struct extra_iommu_entry *get_extra_iommu_ents(void *blob, + int nodeoffset, + phys_addr_t addr, + int *cnt) +{ + const char *s, *p, *tok; + struct extra_iommu_entry *entries; + int i = 0, b, d, f; + + /* + * Retrieve extra IOMMU configuration from env var or from device tree. + * Env var is given priority. + */ + s = env_get("pci_iommu_extra"); + if (!s) { + s = fdt_getprop(blob, nodeoffset, "pci-iommu-extra", NULL); + } else { + phys_addr_t pci_base; + char *endp; + + /* + * In env var case the config string has "pci@0x..." in + * addition. Parse this part and match it by address against + * the input pci controller's registers base address. + */ + tok = s; + p = strchrnul(s + 1, ','); + s = NULL; + do { + if (!strncmp(tok, "pci", 3)) { + pci_base = simple_strtoul(tok + 4, &endp, 0); + if (pci_base == addr) { + s = endp + 1; + break; + } + } + p = strchrnul(p + 1, ','); + tok = p + 1; + } while (*p); + } + + /* + * If no env var or device tree property found or pci register base + * address mismatches, bail out + */ + if (!s) + return NULL; + + /* + * In order to find how many action entries to allocate, count number + * of actions by interating through the pairs of bdfs and actions. + */ + *cnt = 0; + p = s; + while (*p && strncmp(p, "pci", 3)) { + if (*p == ',') + (*cnt)++; + p++; + } + if (!(*p)) + (*cnt)++; + + if (!(*cnt) || (*cnt) % 2) { + printf("ERROR: invalid or odd extra iommu token count %d\n", + *cnt); + return NULL; + } + *cnt = (*cnt) / 2; + + entries = malloc((*cnt) * sizeof(*entries)); + if (!entries) { + printf("ERROR: fail to allocate extra iommu entries\n"); + return NULL; + } + + /* + * Parse action entries one by one and store the information in the + * newly allocated actions array. + */ + p = s; + while (p) { + /* Extract BDF */ + b = simple_strtoul(p, (char **)&p, 0); p++; + d = simple_strtoul(p, (char **)&p, 0); p++; + f = simple_strtoul(p, (char **)&p, 0); p++; + entries[i].bdf = PCI_BDF(b, d, f); + + /* Parse action */ + if (!strncmp(p, "hp", 2)) { + /* Hot-plug entry */ + entries[i].action = EXTRA_IOMMU_ENTRY_HOTPLUG; + p += 2; + } else if (!strncmp(p, "vfs", 3) || + !strncmp(p, "noari_vfs", 9)) { + /* VFs or VFs with ARI disabled entry */ + entries[i].action = EXTRA_IOMMU_ENTRY_VFS; + entries[i].noari = !strncmp(p, "noari_vfs", 9); + + /* + * Parse and store total number of VFs to allocate + * IOMMU entries for. + */ + p = strchr(p, '='); + entries[i].num_vfs = simple_strtoul(p + 1, (char **)&p, + 0); + if (*p) + p++; + } else { + printf("ERROR: invalid action in extra iommu entry\n"); + free(entries); + + return NULL; + } + + if (!(*p) || !strncmp(p, "pci", 3)) + break; + + i++; + } + + return entries; +} + +static void get_vf_offset_and_stride(struct udevice *dev, int sriov_pos, + struct extra_iommu_entry *entry, + u16 *offset, u16 *stride) +{ + u16 tmp16; + u32 tmp32; + bool have_ari = false; + int pos; + struct udevice *pf_dev; + + dm_pci_read_config16(dev, sriov_pos + PCI_SRIOV_TOTAL_VF, &tmp16); + if (entry->num_vfs > tmp16) { + printf("WARN: requested no. of VFs %d exceeds total of %d\n", + entry->num_vfs, tmp16); + } + + /* + * The code below implements the VF Discovery recomandations specified + * in PCIe base spec "9.2.1.2 VF Discovery", quoted below: + * + * VF Discovery + * + * The First VF Offset and VF Stride fields in the SR-IOV extended + * capability are 16-bit Routing ID offsets. These offsets are used to + * compute the Routing IDs for the VFs with the following restrictions: + * - The value in NumVFs in a PF (Section 9.3.3.7) may affect the + * values in First VF Offset (Section 9.3.3.9) and VF Stride + * (Section 9.3.3.10) of that PF. + * - The value in ARI Capable Hierarchy (Section 9.3.3.3.5) in the + * lowest-numbered PF of the Device (for example PF0) may affect + * the values in First VF Offset and VF Stride in all PFs of the + * Device. + * - NumVFs of a PF may only be changed when VF Enable + * (Section 9.3.3.3.1) of that PF is Clear. + * - ARI Capable Hierarchy (Section 9.3.3.3.5) may only be changed + * when VF Enable is Clear in all PFs of a Device. + */ + + /* Clear VF enable for all PFs */ + device_foreach_child(pf_dev, dev->parent) { + dm_pci_read_config16(pf_dev, sriov_pos + PCI_SRIOV_CTRL, + &tmp16); + tmp16 &= ~PCI_SRIOV_CTRL_VFE; + dm_pci_write_config16(pf_dev, sriov_pos + PCI_SRIOV_CTRL, + tmp16); + } + + /* Obtain a reference to PF0 device */ + if (dm_pci_bus_find_bdf(PCI_BDF(PCI_BUS(entry->bdf), + PCI_DEV(entry->bdf), 0), &pf_dev)) { + printf("WARN: failed to get PF0\n"); + } + + if (entry->noari) + goto skip_ari; + + /* Check that connected downstream port supports ARI Forwarding */ + pos = dm_pci_find_capability(dev->parent, PCI_CAP_ID_EXP); + dm_pci_read_config32(dev->parent, pos + PCI_EXP_DEVCAP2, &tmp32); + if (!(tmp32 & PCI_EXP_DEVCAP2_ARI)) + goto skip_ari; + + /* Check that PF supports Alternate Routing ID */ + if (!dm_pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI)) + goto skip_ari; + + /* Set ARI Capable Hierarcy for PF0 */ + dm_pci_read_config16(pf_dev, sriov_pos + PCI_SRIOV_CTRL, &tmp16); + tmp16 |= PCI_SRIOV_CTRL_ARI; + dm_pci_write_config16(pf_dev, sriov_pos + PCI_SRIOV_CTRL, tmp16); + have_ari = true; + +skip_ari: + if (!have_ari) { + /* + * No ARI support or disabled so clear ARI Capable Hierarcy + * for PF0 + */ + dm_pci_read_config16(pf_dev, sriov_pos + PCI_SRIOV_CTRL, + &tmp16); + tmp16 &= ~PCI_SRIOV_CTRL_ARI; + dm_pci_write_config16(pf_dev, sriov_pos + PCI_SRIOV_CTRL, + tmp16); + } + + /* Set requested number of VFs */ + dm_pci_write_config16(dev, sriov_pos + PCI_SRIOV_NUM_VF, + entry->num_vfs); + + /* Read VF stride and offset with the configs just made */ + dm_pci_read_config16(dev, sriov_pos + PCI_SRIOV_VF_OFFSET, offset); + dm_pci_read_config16(dev, sriov_pos + PCI_SRIOV_VF_STRIDE, stride); + + if (have_ari) { + /* Reset to default ARI Capable Hierarcy bit for PF0 */ + dm_pci_read_config16(pf_dev, sriov_pos + PCI_SRIOV_CTRL, + &tmp16); + tmp16 &= ~PCI_SRIOV_CTRL_ARI; + dm_pci_write_config16(pf_dev, sriov_pos + PCI_SRIOV_CTRL, + tmp16); + } + /* Reset to default the number of VFs */ + dm_pci_write_config16(dev, sriov_pos + PCI_SRIOV_NUM_VF, 0); +} + +static int fdt_fixup_pci_vfs(void *blob, struct extra_iommu_entry *entry, + struct ls_pcie_rc *pcie_rc) +{ + struct udevice *dev, *bus; + u16 vf_offset, vf_stride; + int i, sriov_pos; + pci_dev_t bdf; + + if (dm_pci_bus_find_bdf(entry->bdf, &dev)) { + printf("ERROR: BDF %d.%d.%d not found\n", PCI_BUS(entry->bdf), + PCI_DEV(entry->bdf), PCI_FUNC(entry->bdf)); + return 0; + } + + sriov_pos = dm_pci_find_ext_capability(dev, PCI_EXT_CAP_ID_SRIOV); + if (!sriov_pos) { + printf("WARN: trying to set VFs on non-SRIOV dev\n"); + return 0; + } + + get_vf_offset_and_stride(dev, sriov_pos, entry, &vf_offset, &vf_stride); + + for (bus = dev; device_is_on_pci_bus(bus);) + bus = bus->parent; + + bdf = entry->bdf - PCI_BDF(bus->seq, 0, 0) + (vf_offset << 8); + + for (i = 0; i < entry->num_vfs; i++) { + if (fdt_fixup_pcie_device_ls(blob, bdf, pcie_rc) < 0) + return -1; + bdf += vf_stride << 8; + } + + printf("Added %d iommu VF mappings for PF %d.%d.%d\n", + entry->num_vfs, PCI_BUS(entry->bdf), + PCI_DEV(entry->bdf), PCI_FUNC(entry->bdf)); + + return 0; +} + static void fdt_fixup_pcie_ls(void *blob) { struct udevice *dev, *bus; struct ls_pcie_rc *pcie_rc; - int streamid; - int index; pci_dev_t bdf; + struct extra_iommu_entry *entries; + int i, cnt, nodeoffset; + /* Scan all known buses */ for (pci_find_first_device(&dev); @@ -196,33 +517,57 @@ static void fdt_fixup_pcie_ls(void *blob) pcie_rc = dev_get_priv(bus); - streamid = pcie_next_streamid(pcie_rc->stream_id_cur, - pcie_rc->pcie->idx); - if (streamid < 0) { - debug("ERROR: no stream ids free\n"); + /* the DT fixup must be relative to the hose first_busno */ + bdf = dm_pci_get_bdf(dev) - PCI_BDF(bus->seq, 0, 0); + + if (fdt_fixup_pcie_device_ls(blob, bdf, pcie_rc) < 0) + break; + } + + if (!IS_ENABLED(CONFIG_PCI_IOMMU_EXTRA_MAPPINGS)) + goto skip; + + list_for_each_entry(pcie_rc, &ls_pcie_list, list) { + nodeoffset = fdt_pcie_get_nodeoffset(blob, pcie_rc); + if (nodeoffset < 0) { + printf("ERROR: couldn't find pci node\n"); continue; - } else { - pcie_rc->stream_id_cur++; } - index = ls_pcie_next_lut_index(pcie_rc); - if (index < 0) { - debug("ERROR: no LUT indexes free\n"); + entries = get_extra_iommu_ents(blob, nodeoffset, + pcie_rc->dbi_res.start, &cnt); + if (!entries) continue; - } - /* the DT fixup must be relative to the hose first_busno */ - bdf = dm_pci_get_bdf(dev) - PCI_BDF(bus->seq, 0, 0); - /* map PCI b.d.f to streamID in LUT */ - ls_pcie_lut_set_mapping(pcie_rc, index, bdf >> 8, - streamid); - /* update msi-map in device tree */ - fdt_pcie_set_msi_map_entry_ls(blob, pcie_rc, bdf >> 8, - streamid); - /* update iommu-map in device tree */ - fdt_pcie_set_iommu_map_entry_ls(blob, pcie_rc, bdf >> 8, - streamid); + for (i = 0; i < cnt; i++) { + if (entries[i].action == EXTRA_IOMMU_ENTRY_HOTPLUG) { + bdf = entries[i].bdf; + printf("Added iommu map for hotplug %d.%d.%d\n", + PCI_BUS(bdf), PCI_DEV(bdf), + PCI_FUNC(bdf)); + if (fdt_fixup_pcie_device_ls(blob, bdf, + pcie_rc) < 0) { + free(entries); + return; + } + } else if (entries[i].action == EXTRA_IOMMU_ENTRY_VFS) { + if (fdt_fixup_pci_vfs(blob, &entries[i], + pcie_rc) < 0) { + free(entries); + return; + } + } else { + printf("Invalid action %d for BDF %d.%d.%d\n", + entries[i].action, + PCI_BUS(entries[i].bdf), + PCI_DEV(entries[i].bdf), + PCI_FUNC(entries[i].bdf)); + } + } + free(entries); } + +skip: pcie_board_fix_fdt(blob); } #endif @@ -230,28 +575,11 @@ static void fdt_fixup_pcie_ls(void *blob) static void ft_pcie_rc_fix(void *blob, struct ls_pcie_rc *pcie_rc) { int off; - uint svr; - char *compat = NULL; struct ls_pcie *pcie = pcie_rc->pcie; - off = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie", - pcie_rc->dbi_res.start); - if (off < 0) { -#ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */ - svr = (get_svr() >> SVR_VAR_PER_SHIFT) & 0xFFFFFE; - if (svr == SVR_LS2088A || svr == SVR_LS2084A || - svr == SVR_LS2048A || svr == SVR_LS2044A || - svr == SVR_LS2081A || svr == SVR_LS2041A) - compat = "fsl,ls2088a-pcie"; - else - compat = CONFIG_FSL_PCIE_COMPAT; - if (compat) - off = fdt_node_offset_by_compat_reg(blob, - compat, pcie_rc->dbi_res.start); -#endif - if (off < 0) - return; - } + off = fdt_pcie_get_nodeoffset(blob, pcie_rc); + if (off < 0) + return; if (pcie_rc->enabled && pcie->mode == PCI_HEADER_TYPE_BRIDGE) fdt_set_node_status(blob, off, FDT_STATUS_OKAY, 0); diff --git a/drivers/phy/marvell/comphy_cp110.c b/drivers/phy/marvell/comphy_cp110.c index 15e8004..b0fcb13 100644 --- a/drivers/phy/marvell/comphy_cp110.c +++ b/drivers/phy/marvell/comphy_cp110.c @@ -7,6 +7,7 @@ #include <fdtdec.h> #include <log.h> #include <asm/io.h> +#include <asm/ptrace.h> #include <asm/arch/cpu.h> #include <asm/arch/soc.h> #include <linux/delay.h> @@ -22,6 +23,40 @@ DECLARE_GLOBAL_DATA_PTR; #define HPIPE_ADDR(base, lane) (SD_ADDR(base, lane) + 0x800) #define COMPHY_ADDR(base, lane) (base + 0x28 * lane) +/* Firmware related definitions used for SMC calls */ +#define MV_SIP_COMPHY_POWER_ON 0x82000001 +#define MV_SIP_COMPHY_POWER_OFF 0x82000002 +#define MV_SIP_COMPHY_PLL_LOCK 0x82000003 + +/* Used to distinguish between different possible callers (U-boot/Linux) */ +#define COMPHY_CALLER_UBOOT (0x1 << 21) + +#define COMPHY_FW_MODE_FORMAT(mode) ((mode) << 12) +#define COMPHY_FW_FORMAT(mode, idx, speeds) \ + (((mode) << 12) | ((idx) << 8) | ((speeds) << 2)) + +#define COMPHY_FW_PCIE_FORMAT(pcie_width, clk_src, mode, speeds) \ + (COMPHY_CALLER_UBOOT | ((pcie_width) << 18) | \ + ((clk_src) << 17) | COMPHY_FW_FORMAT(mode, 0, speeds)) + +#define COMPHY_SATA_MODE 0x1 +#define COMPHY_SGMII_MODE 0x2 /* SGMII 1G */ +#define COMPHY_HS_SGMII_MODE 0x3 /* SGMII 2.5G */ +#define COMPHY_USB3H_MODE 0x4 +#define COMPHY_USB3D_MODE 0x5 +#define COMPHY_PCIE_MODE 0x6 +#define COMPHY_RXAUI_MODE 0x7 +#define COMPHY_XFI_MODE 0x8 +#define COMPHY_SFI_MODE 0x9 +#define COMPHY_USB3_MODE 0xa +#define COMPHY_AP_MODE 0xb + +/* Comphy unit index macro */ +#define COMPHY_UNIT_ID0 0 +#define COMPHY_UNIT_ID1 1 +#define COMPHY_UNIT_ID2 2 +#define COMPHY_UNIT_ID3 3 + struct utmi_phy_data { void __iomem *utmi_base_addr; void __iomem *usb_cfg_addr; @@ -85,441 +120,6 @@ static u32 polling_with_timeout(void __iomem *addr, u32 val, return 0; } -static int comphy_pcie_power_up(u32 lane, u32 pcie_width, bool clk_src, - bool is_end_point, void __iomem *hpipe_base, - void __iomem *comphy_base) -{ - u32 mask, data, ret = 1; - void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base, lane); - void __iomem *comphy_addr = COMPHY_ADDR(comphy_base, lane); - void __iomem *addr; - u32 pcie_clk = 0; /* set input by default */ - - debug_enter(); - - /* - * ToDo: - * Add SAR (Sample-At-Reset) configuration for the PCIe clock - * direction. SAR code is currently not ported from Marvell - * U-Boot to mainline version. - * - * SerDes Lane 4/5 got the PCIe ref-clock #1, - * and SerDes Lane 0 got PCIe ref-clock #0 - */ - debug("PCIe clock = %x\n", pcie_clk); - debug("PCIe RC = %d\n", !is_end_point); - debug("PCIe width = %d\n", pcie_width); - - /* enable PCIe by4 and by2 */ - if (lane == 0) { - if (pcie_width == 4) { - reg_set(comphy_base + COMMON_PHY_SD_CTRL1, - 0x1 << COMMON_PHY_SD_CTRL1_PCIE_X4_EN_OFFSET, - COMMON_PHY_SD_CTRL1_PCIE_X4_EN_MASK); - } else if (pcie_width == 2) { - reg_set(comphy_base + COMMON_PHY_SD_CTRL1, - 0x1 << COMMON_PHY_SD_CTRL1_PCIE_X2_EN_OFFSET, - COMMON_PHY_SD_CTRL1_PCIE_X2_EN_MASK); - } - } - - /* - * If PCIe clock is output and clock source from SerDes lane 5, - * we need to configure the clock-source MUX. - * By default, the clock source is from lane 4 - */ - if (pcie_clk && clk_src && (lane == 5)) { - reg_set((void __iomem *)DFX_DEV_GEN_CTRL12, - 0x3 << DFX_DEV_GEN_PCIE_CLK_SRC_OFFSET, - DFX_DEV_GEN_PCIE_CLK_SRC_MASK); - } - - debug("stage: RFU configurations - hard reset comphy\n"); - /* RFU configurations - hard reset comphy */ - mask = COMMON_PHY_CFG1_PWR_UP_MASK; - data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET; - mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK; - data |= 0x1 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET; - mask |= COMMON_PHY_CFG1_PWR_ON_RESET_MASK; - data |= 0x0 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET; - mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK; - data |= 0x0 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET; - mask |= COMMON_PHY_PHY_MODE_MASK; - data |= 0x0 << COMMON_PHY_PHY_MODE_OFFSET; - reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); - - /* release from hard reset */ - mask = COMMON_PHY_CFG1_PWR_ON_RESET_MASK; - data = 0x1 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET; - mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK; - data |= 0x1 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET; - reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); - - /* Wait 1ms - until band gap and ref clock ready */ - mdelay(1); - /* Start comphy Configuration */ - debug("stage: Comphy configuration\n"); - /* Set PIPE soft reset */ - mask = HPIPE_RST_CLK_CTRL_PIPE_RST_MASK; - data = 0x1 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET; - /* Set PHY datapath width mode for V0 */ - mask |= HPIPE_RST_CLK_CTRL_FIXED_PCLK_MASK; - data |= 0x1 << HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET; - /* Set Data bus width USB mode for V0 */ - mask |= HPIPE_RST_CLK_CTRL_PIPE_WIDTH_MASK; - data |= 0x0 << HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET; - /* Set CORE_CLK output frequency for 250Mhz */ - mask |= HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_MASK; - data |= 0x0 << HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET; - reg_set(hpipe_addr + HPIPE_RST_CLK_CTRL_REG, data, mask); - /* Set PLL ready delay for 0x2 */ - data = 0x2 << HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET; - mask = HPIPE_CLK_SRC_LO_PLL_RDY_DL_MASK; - if (pcie_width != 1) { - data |= 0x1 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_OFFSET; - mask |= HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_MASK; - data |= 0x1 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_OFFSET; - mask |= HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_MASK; - } - reg_set(hpipe_addr + HPIPE_CLK_SRC_LO_REG, data, mask); - - /* Set PIPE mode interface to PCIe3 - 0x1 & set lane order */ - data = 0x1 << HPIPE_CLK_SRC_HI_MODE_PIPE_OFFSET; - mask = HPIPE_CLK_SRC_HI_MODE_PIPE_MASK; - if (pcie_width != 1) { - mask |= HPIPE_CLK_SRC_HI_LANE_STRT_MASK; - mask |= HPIPE_CLK_SRC_HI_LANE_MASTER_MASK; - mask |= HPIPE_CLK_SRC_HI_LANE_BREAK_MASK; - if (lane == 0) { - data |= 0x1 << HPIPE_CLK_SRC_HI_LANE_STRT_OFFSET; - data |= 0x1 << HPIPE_CLK_SRC_HI_LANE_MASTER_OFFSET; - } else if (lane == (pcie_width - 1)) { - data |= 0x1 << HPIPE_CLK_SRC_HI_LANE_BREAK_OFFSET; - } - } - reg_set(hpipe_addr + HPIPE_CLK_SRC_HI_REG, data, mask); - /* Config update polarity equalization */ - reg_set(hpipe_addr + HPIPE_LANE_EQ_CFG1_REG, - 0x1 << HPIPE_CFG_UPDATE_POLARITY_OFFSET, - HPIPE_CFG_UPDATE_POLARITY_MASK); - /* Set PIPE version 4 to mode enable */ - reg_set(hpipe_addr + HPIPE_DFE_CTRL_28_REG, - 0x1 << HPIPE_DFE_CTRL_28_PIPE4_OFFSET, - HPIPE_DFE_CTRL_28_PIPE4_MASK); - /* TODO: check if pcie clock is output/input - for bringup use input*/ - /* Enable PIN clock 100M_125M */ - mask = 0; - data = 0; - /* Only if clock is output, configure the clock-source mux */ - if (pcie_clk) { - mask |= HPIPE_MISC_CLK100M_125M_MASK; - data |= 0x1 << HPIPE_MISC_CLK100M_125M_OFFSET; - } - /* - * Set PIN_TXDCLK_2X Clock Frequency Selection for outputs 500MHz - * clock - */ - mask |= HPIPE_MISC_TXDCLK_2X_MASK; - data |= 0x0 << HPIPE_MISC_TXDCLK_2X_OFFSET; - /* Enable 500MHz Clock */ - mask |= HPIPE_MISC_CLK500_EN_MASK; - data |= 0x1 << HPIPE_MISC_CLK500_EN_OFFSET; - if (pcie_clk) { /* output */ - /* Set reference clock comes from group 1 */ - mask |= HPIPE_MISC_REFCLK_SEL_MASK; - data |= 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET; - } else { - /* Set reference clock comes from group 2 */ - mask |= HPIPE_MISC_REFCLK_SEL_MASK; - data |= 0x1 << HPIPE_MISC_REFCLK_SEL_OFFSET; - } - mask |= HPIPE_MISC_ICP_FORCE_MASK; - data |= 0x1 << HPIPE_MISC_ICP_FORCE_OFFSET; - reg_set(hpipe_addr + HPIPE_MISC_REG, data, mask); - if (pcie_clk) { /* output */ - /* Set reference frequcency select - 0x2 for 25MHz*/ - mask = HPIPE_PWR_PLL_REF_FREQ_MASK; - data = 0x2 << HPIPE_PWR_PLL_REF_FREQ_OFFSET; - } else { - /* Set reference frequcency select - 0x0 for 100MHz*/ - mask = HPIPE_PWR_PLL_REF_FREQ_MASK; - data = 0x0 << HPIPE_PWR_PLL_REF_FREQ_OFFSET; - } - /* Set PHY mode to PCIe */ - mask |= HPIPE_PWR_PLL_PHY_MODE_MASK; - data |= 0x3 << HPIPE_PWR_PLL_PHY_MODE_OFFSET; - reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask); - - /* ref clock alignment */ - if (pcie_width != 1) { - mask = HPIPE_LANE_ALIGN_OFF_MASK; - data = 0x0 << HPIPE_LANE_ALIGN_OFF_OFFSET; - reg_set(hpipe_addr + HPIPE_LANE_ALIGN_REG, data, mask); - } - - /* - * Set the amount of time spent in the LoZ state - set for 0x7 only if - * the PCIe clock is output - */ - if (pcie_clk) { - reg_set(hpipe_addr + HPIPE_GLOBAL_PM_CTRL, - 0x7 << HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET, - HPIPE_GLOBAL_PM_RXDLOZ_WAIT_MASK); - } - - /* Set Maximal PHY Generation Setting(8Gbps) */ - mask = HPIPE_INTERFACE_GEN_MAX_MASK; - data = 0x2 << HPIPE_INTERFACE_GEN_MAX_OFFSET; - /* Bypass frame detection and sync detection for RX DATA */ - mask = HPIPE_INTERFACE_DET_BYPASS_MASK; - data = 0x1 << HPIPE_INTERFACE_DET_BYPASS_OFFSET; - /* Set Link Train Mode (Tx training control pins are used) */ - mask |= HPIPE_INTERFACE_LINK_TRAIN_MASK; - data |= 0x1 << HPIPE_INTERFACE_LINK_TRAIN_OFFSET; - reg_set(hpipe_addr + HPIPE_INTERFACE_REG, data, mask); - - /* Set Idle_sync enable */ - mask = HPIPE_PCIE_IDLE_SYNC_MASK; - data = 0x1 << HPIPE_PCIE_IDLE_SYNC_OFFSET; - /* Select bits for PCIE Gen3(32bit) */ - mask |= HPIPE_PCIE_SEL_BITS_MASK; - data |= 0x2 << HPIPE_PCIE_SEL_BITS_OFFSET; - reg_set(hpipe_addr + HPIPE_PCIE_REG0, data, mask); - - /* Enable Tx_adapt_g1 */ - mask = HPIPE_TX_TRAIN_CTRL_G1_MASK; - data = 0x1 << HPIPE_TX_TRAIN_CTRL_G1_OFFSET; - /* Enable Tx_adapt_gn1 */ - mask |= HPIPE_TX_TRAIN_CTRL_GN1_MASK; - data |= 0x1 << HPIPE_TX_TRAIN_CTRL_GN1_OFFSET; - /* Disable Tx_adapt_g0 */ - mask |= HPIPE_TX_TRAIN_CTRL_G0_MASK; - data |= 0x0 << HPIPE_TX_TRAIN_CTRL_G0_OFFSET; - reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_REG, data, mask); - - /* Set reg_tx_train_chk_init */ - mask = HPIPE_TX_TRAIN_CHK_INIT_MASK; - data = 0x0 << HPIPE_TX_TRAIN_CHK_INIT_OFFSET; - /* Enable TX_COE_FM_PIN_PCIE3_EN */ - mask |= HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_MASK; - data |= 0x1 << HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET; - reg_set(hpipe_addr + HPIPE_TX_TRAIN_REG, data, mask); - - debug("stage: TRx training parameters\n"); - /* Set Preset sweep configurations */ - mask = HPIPE_TX_TX_STATUS_CHECK_MODE_MASK; - data = 0x1 << HPIPE_TX_STATUS_CHECK_MODE_OFFSET; - - mask |= HPIPE_TX_NUM_OF_PRESET_MASK; - data |= 0x7 << HPIPE_TX_NUM_OF_PRESET_OFFSET; - - mask |= HPIPE_TX_SWEEP_PRESET_EN_MASK; - data |= 0x1 << HPIPE_TX_SWEEP_PRESET_EN_OFFSET; - reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_11_REG, data, mask); - - /* Tx train start configuration */ - mask = HPIPE_TX_TRAIN_START_SQ_EN_MASK; - data = 0x1 << HPIPE_TX_TRAIN_START_SQ_EN_OFFSET; - - mask |= HPIPE_TX_TRAIN_START_FRM_DET_EN_MASK; - data |= 0x0 << HPIPE_TX_TRAIN_START_FRM_DET_EN_OFFSET; - - mask |= HPIPE_TX_TRAIN_START_FRM_LOCK_EN_MASK; - data |= 0x0 << HPIPE_TX_TRAIN_START_FRM_LOCK_EN_OFFSET; - - mask |= HPIPE_TX_TRAIN_WAIT_TIME_EN_MASK; - data |= 0x1 << HPIPE_TX_TRAIN_WAIT_TIME_EN_OFFSET; - reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_5_REG, data, mask); - - /* Enable Tx train P2P */ - mask = HPIPE_TX_TRAIN_P2P_HOLD_MASK; - data = 0x1 << HPIPE_TX_TRAIN_P2P_HOLD_OFFSET; - reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_0_REG, data, mask); - - /* Configure Tx train timeout */ - mask = HPIPE_TRX_TRAIN_TIMER_MASK; - data = 0x17 << HPIPE_TRX_TRAIN_TIMER_OFFSET; - reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_4_REG, data, mask); - - /* Disable G0/G1/GN1 adaptation */ - mask = HPIPE_TX_TRAIN_CTRL_G1_MASK | HPIPE_TX_TRAIN_CTRL_GN1_MASK - | HPIPE_TX_TRAIN_CTRL_G0_OFFSET; - data = 0; - reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_REG, data, mask); - - /* Disable DTL frequency loop */ - mask = HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK; - data = 0x0 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET; - reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG, data, mask); - - /* Configure G3 DFE */ - mask = HPIPE_G3_DFE_RES_MASK; - data = 0x3 << HPIPE_G3_DFE_RES_OFFSET; - reg_set(hpipe_addr + HPIPE_G3_SETTING_4_REG, data, mask); - - /* Use TX/RX training result for DFE */ - mask = HPIPE_DFE_RES_FORCE_MASK; - data = 0x0 << HPIPE_DFE_RES_FORCE_OFFSET; - reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask); - - /* Configure initial and final coefficient value for receiver */ - mask = HPIPE_G3_SET_1_G3_RX_SELMUPI_MASK; - data = 0x1 << HPIPE_G3_SET_1_G3_RX_SELMUPI_OFFSET; - - mask |= HPIPE_G3_SET_1_G3_RX_SELMUPF_MASK; - data |= 0x1 << HPIPE_G3_SET_1_G3_RX_SELMUPF_OFFSET; - - mask |= HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_MASK; - data |= 0x0 << HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_OFFSET; - reg_set(hpipe_addr + HPIPE_G3_SET_1_REG, data, mask); - - /* Trigger sampler enable pulse */ - mask = HPIPE_SMAPLER_MASK; - data = 0x1 << HPIPE_SMAPLER_OFFSET; - reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask); - udelay(5); - reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, 0, mask); - - /* FFE resistor tuning for different bandwidth */ - mask = HPIPE_G3_FFE_DEG_RES_LEVEL_MASK; - data = 0x1 << HPIPE_G3_FFE_DEG_RES_LEVEL_OFFSET; - - mask |= HPIPE_G3_FFE_LOAD_RES_LEVEL_MASK; - data |= 0x3 << HPIPE_G3_FFE_LOAD_RES_LEVEL_OFFSET; - reg_set(hpipe_addr + HPIPE_G3_SETTING_3_REG, data, mask); - - /* Pattern lock lost timeout disable */ - mask = HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_MASK; - data = 0x0 << HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_OFFSET; - reg_set(hpipe_addr + HPIPE_FRAME_DETECT_CTRL_3_REG, data, mask); - - /* Configure DFE adaptations */ - mask = HPIPE_CDR_MAX_DFE_ADAPT_1_MASK; - data = 0x1 << HPIPE_CDR_MAX_DFE_ADAPT_1_OFFSET; - mask |= HPIPE_CDR_MAX_DFE_ADAPT_0_MASK; - data |= 0x0 << HPIPE_CDR_MAX_DFE_ADAPT_0_OFFSET; - mask |= HPIPE_CDR_RX_MAX_DFE_ADAPT_1_MASK; - data |= 0x0 << HPIPE_CDR_RX_MAX_DFE_ADAPT_1_OFFSET; - reg_set(hpipe_addr + HPIPE_CDR_CONTROL_REG, data, mask); - mask = HPIPE_DFE_TX_MAX_DFE_ADAPT_MASK; - data = 0x0 << HPIPE_DFE_TX_MAX_DFE_ADAPT_OFFSET; - reg_set(hpipe_addr + HPIPE_DFE_CONTROL_REG, data, mask); - - /* Genration 2 setting 1*/ - mask = HPIPE_G2_SET_1_G2_RX_SELMUPI_MASK; - data = 0x0 << HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET; - mask |= HPIPE_G2_SET_1_G2_RX_SELMUPP_MASK; - data |= 0x1 << HPIPE_G2_SET_1_G2_RX_SELMUPP_OFFSET; - mask |= HPIPE_G2_SET_1_G2_RX_SELMUFI_MASK; - data |= 0x0 << HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET; - reg_set(hpipe_addr + HPIPE_G2_SET_1_REG, data, mask); - - /* DFE enable */ - mask = HPIPE_G2_DFE_RES_MASK; - data = 0x3 << HPIPE_G2_DFE_RES_OFFSET; - reg_set(hpipe_addr + HPIPE_G2_SETTINGS_4_REG, data, mask); - - /* Configure DFE Resolution */ - mask = HPIPE_LANE_CFG4_DFE_EN_SEL_MASK; - data = 0x1 << HPIPE_LANE_CFG4_DFE_EN_SEL_OFFSET; - reg_set(hpipe_addr + HPIPE_LANE_CFG4_REG, data, mask); - - /* VDD calibration control */ - mask = HPIPE_EXT_SELLV_RXSAMPL_MASK; - data = 0x16 << HPIPE_EXT_SELLV_RXSAMPL_OFFSET; - reg_set(hpipe_addr + HPIPE_VDD_CAL_CTRL_REG, data, mask); - - /* Set PLL Charge-pump Current Control */ - mask = HPIPE_G3_SETTING_5_G3_ICP_MASK; - data = 0x4 << HPIPE_G3_SETTING_5_G3_ICP_OFFSET; - reg_set(hpipe_addr + HPIPE_G3_SETTING_5_REG, data, mask); - - /* Set lane rqualization remote setting */ - mask = HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_MASK; - data = 0x1 << HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_OFFSET; - mask |= HPIPE_LANE_CFG_FOM_ONLY_MODE_MASK; - data |= 0x1 << HPIPE_LANE_CFG_FOM_ONLY_MODE_OFFFSET; - mask |= HPIPE_LANE_CFG_FOM_PRESET_VECTOR_MASK; - data |= 0x2 << HPIPE_LANE_CFG_FOM_PRESET_VECTOR_OFFSET; - reg_set(hpipe_addr + HPIPE_LANE_EQ_REMOTE_SETTING_REG, data, mask); - - if (!is_end_point) { - /* Set phy in root complex mode */ - mask = HPIPE_CFG_PHY_RC_EP_MASK; - data = 0x1 << HPIPE_CFG_PHY_RC_EP_OFFSET; - reg_set(hpipe_addr + HPIPE_LANE_EQU_CONFIG_0_REG, data, mask); - } - - debug("stage: Comphy power up\n"); - - /* - * For PCIe by4 or by2 - release from reset only after finish to - * configure all lanes - */ - if ((pcie_width == 1) || (lane == (pcie_width - 1))) { - u32 i, start_lane, end_lane; - - if (pcie_width != 1) { - /* allows writing to all lanes in one write */ - reg_set(comphy_base + COMMON_PHY_SD_CTRL1, - 0x0 << - COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_OFFSET, - COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_MASK); - start_lane = 0; - end_lane = pcie_width; - - /* - * Release from PIPE soft reset - * for PCIe by4 or by2 - release from soft reset - * all lanes - can't use read modify write - */ - reg_set(HPIPE_ADDR(hpipe_base, 0) + - HPIPE_RST_CLK_CTRL_REG, 0x24, 0xffffffff); - } else { - start_lane = lane; - end_lane = lane + 1; - - /* - * Release from PIPE soft reset - * for PCIe by4 or by2 - release from soft reset - * all lanes - */ - reg_set(hpipe_addr + HPIPE_RST_CLK_CTRL_REG, - 0x0 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET, - HPIPE_RST_CLK_CTRL_PIPE_RST_MASK); - } - - - if (pcie_width != 1) { - /* disable writing to all lanes with one write */ - reg_set(comphy_base + COMMON_PHY_SD_CTRL1, - 0x3210 << - COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_OFFSET, - COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_MASK); - } - - debug("stage: Check PLL\n"); - /* Read lane status */ - for (i = start_lane; i < end_lane; i++) { - addr = HPIPE_ADDR(hpipe_base, i) + - HPIPE_LANE_STATUS1_REG; - data = HPIPE_LANE_STATUS1_PCLK_EN_MASK; - mask = data; - data = polling_with_timeout(addr, data, mask, 15000); - if (data != 0) { - debug("Read from reg = %p - value = 0x%x\n", - hpipe_addr + HPIPE_LANE_STATUS1_REG, - data); - pr_err("HPIPE_LANE_STATUS1_PCLK_EN_MASK is 0\n"); - ret = 0; - } - } - } - - debug_exit(); - return ret; -} - static int comphy_usb3_power_up(u32 lane, void __iomem *hpipe_base, void __iomem *comphy_base) { @@ -642,15 +242,31 @@ static int comphy_usb3_power_up(u32 lane, void __iomem *hpipe_base, return ret; } +static int comphy_smc(u32 function_id, void __iomem *comphy_base_addr, + u32 lane, u32 mode) +{ + struct pt_regs pregs = {0}; + + pregs.regs[0] = function_id; + pregs.regs[1] = (unsigned long)comphy_base_addr; + pregs.regs[2] = lane; + pregs.regs[3] = mode; + + smc_call(&pregs); + + /* + * TODO: Firmware return 0 on success, temporary map it to u-boot + * convention, but after all comphy will be reworked the convention in + * u-boot should be change and this conversion removed + */ + return pregs.regs[0] ? 0 : 1; +} + static int comphy_sata_power_up(u32 lane, void __iomem *hpipe_base, - void __iomem *comphy_base, int cp_index, - u32 invert) + void __iomem *comphy_base_addr, int cp_index, + u32 type) { u32 mask, data, i, ret = 1; - void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base, lane); - void __iomem *sd_ip_addr = SD_ADDR(hpipe_base, lane); - void __iomem *comphy_addr = COMPHY_ADDR(comphy_base, lane); - void __iomem *addr; void __iomem *sata_base = NULL; int sata_node = -1; /* Set to -1 in order to read the first sata node */ @@ -703,255 +319,8 @@ static int comphy_sata_power_up(u32 lane, void __iomem *hpipe_base, data |= 0x0 << SATA3_CTRL_SATA_SSU_OFFSET; reg_set(sata_base + SATA3_VENDOR_DATA, data, mask); - debug("stage: RFU configurations - hard reset comphy\n"); - /* RFU configurations - hard reset comphy */ - mask = COMMON_PHY_CFG1_PWR_UP_MASK; - data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET; - mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK; - data |= 0x0 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET; - mask |= COMMON_PHY_CFG1_PWR_ON_RESET_MASK; - data |= 0x0 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET; - mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK; - data |= 0x0 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET; - reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); - - /* Set select data width 40Bit - SATA mode only */ - reg_set(comphy_addr + COMMON_PHY_CFG6_REG, - 0x1 << COMMON_PHY_CFG6_IF_40_SEL_OFFSET, - COMMON_PHY_CFG6_IF_40_SEL_MASK); - - /* release from hard reset in SD external */ - mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK; - data = 0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET; - mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK; - data |= 0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET; - reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); - - /* Wait 1ms - until band gap and ref clock ready */ - mdelay(1); + ret = comphy_smc(MV_SIP_COMPHY_POWER_ON, comphy_base_addr, lane, type); - debug("stage: Comphy configuration\n"); - /* Start comphy Configuration */ - /* Set reference clock to comes from group 1 - choose 25Mhz */ - reg_set(hpipe_addr + HPIPE_MISC_REG, - 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET, - HPIPE_MISC_REFCLK_SEL_MASK); - /* Reference frequency select set 1 (for SATA = 25Mhz) */ - mask = HPIPE_PWR_PLL_REF_FREQ_MASK; - data = 0x1 << HPIPE_PWR_PLL_REF_FREQ_OFFSET; - /* PHY mode select (set SATA = 0x0 */ - mask |= HPIPE_PWR_PLL_PHY_MODE_MASK; - data |= 0x0 << HPIPE_PWR_PLL_PHY_MODE_OFFSET; - reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask); - /* Set max PHY generation setting - 6Gbps */ - reg_set(hpipe_addr + HPIPE_INTERFACE_REG, - 0x2 << HPIPE_INTERFACE_GEN_MAX_OFFSET, - HPIPE_INTERFACE_GEN_MAX_MASK); - /* Set select data width 40Bit (SEL_BITS[2:0]) */ - reg_set(hpipe_addr + HPIPE_LOOPBACK_REG, - 0x2 << HPIPE_LOOPBACK_SEL_OFFSET, HPIPE_LOOPBACK_SEL_MASK); - - debug("stage: Analog paramters from ETP(HW)\n"); - /* Set analog parameters from ETP(HW) */ - /* G1 settings */ - mask = HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK; - data = 0x0 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET; - mask |= HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK; - data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET; - mask |= HPIPE_G1_SET_1_G1_RX_SELMUFI_MASK; - data |= 0x0 << HPIPE_G1_SET_1_G1_RX_SELMUFI_OFFSET; - mask |= HPIPE_G1_SET_1_G1_RX_SELMUFF_MASK; - data |= 0x3 << HPIPE_G1_SET_1_G1_RX_SELMUFF_OFFSET; - mask |= HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_MASK; - data |= 0x1 << HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_OFFSET; - reg_set(hpipe_addr + HPIPE_G1_SET_1_REG, data, mask); - - mask = HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_MASK; - data = 0xf << HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_OFFSET; - mask |= HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_MASK; - data |= 0x2 << HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_OFFSET; - mask |= HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_MASK; - data |= 0x1 << HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_OFFSET; - mask |= HPIPE_G1_SETTINGS_3_G1_FFE_DEG_RES_LEVEL_MASK; - data |= 0x1 << HPIPE_G1_SETTINGS_3_G1_FFE_DEG_RES_LEVEL_OFFSET; - mask |= HPIPE_G1_SETTINGS_3_G1_FFE_LOAD_RES_LEVEL_MASK; - data |= 0x1 << HPIPE_G1_SETTINGS_3_G1_FFE_LOAD_RES_LEVEL_OFFSET; - reg_set(hpipe_addr + HPIPE_G1_SETTINGS_3_REG, data, mask); - - /* G2 settings */ - mask = HPIPE_G2_SET_1_G2_RX_SELMUPI_MASK; - data = 0x0 << HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET; - mask |= HPIPE_G2_SET_1_G2_RX_SELMUPP_MASK; - data |= 0x1 << HPIPE_G2_SET_1_G2_RX_SELMUPP_OFFSET; - mask |= HPIPE_G2_SET_1_G2_RX_SELMUFI_MASK; - data |= 0x0 << HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET; - mask |= HPIPE_G2_SET_1_G2_RX_SELMUFF_MASK; - data |= 0x3 << HPIPE_G2_SET_1_G2_RX_SELMUFF_OFFSET; - mask |= HPIPE_G2_SET_1_G2_RX_DIGCK_DIV_MASK; - data |= 0x1 << HPIPE_G2_SET_1_G2_RX_DIGCK_DIV_OFFSET; - reg_set(hpipe_addr + HPIPE_G2_SET_1_REG, data, mask); - - /* G3 settings */ - mask = HPIPE_G3_SET_1_G3_RX_SELMUPI_MASK; - data = 0x2 << HPIPE_G3_SET_1_G3_RX_SELMUPI_OFFSET; - mask |= HPIPE_G3_SET_1_G3_RX_SELMUPF_MASK; - data |= 0x2 << HPIPE_G3_SET_1_G3_RX_SELMUPF_OFFSET; - mask |= HPIPE_G3_SET_1_G3_RX_SELMUFI_MASK; - data |= 0x3 << HPIPE_G3_SET_1_G3_RX_SELMUFI_OFFSET; - mask |= HPIPE_G3_SET_1_G3_RX_SELMUFF_MASK; - data |= 0x3 << HPIPE_G3_SET_1_G3_RX_SELMUFF_OFFSET; - mask |= HPIPE_G3_SET_1_G3_RX_DFE_EN_MASK; - data |= 0x1 << HPIPE_G3_SET_1_G3_RX_DFE_EN_OFFSET; - mask |= HPIPE_G3_SET_1_G3_RX_DIGCK_DIV_MASK; - data |= 0x2 << HPIPE_G3_SET_1_G3_RX_DIGCK_DIV_OFFSET; - mask |= HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_MASK; - data |= 0x0 << HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_OFFSET; - reg_set(hpipe_addr + HPIPE_G3_SET_1_REG, data, mask); - - /* DTL Control */ - mask = HPIPE_PWR_CTR_DTL_SQ_DET_EN_MASK; - data = 0x1 << HPIPE_PWR_CTR_DTL_SQ_DET_EN_OFFSET; - mask |= HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_MASK; - data |= 0x1 << HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_OFFSET; - mask |= HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK; - data |= 0x1 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET; - mask |= HPIPE_PWR_CTR_DTL_CLAMPING_SEL_MASK; - data |= 0x1 << HPIPE_PWR_CTR_DTL_CLAMPING_SEL_OFFSET; - mask |= HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_MASK; - data |= 0x1 << HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_OFFSET; - mask |= HPIPE_PWR_CTR_DTL_CLK_MODE_MASK; - data |= 0x1 << HPIPE_PWR_CTR_DTL_CLK_MODE_OFFSET; - mask |= HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_MASK; - data |= 0x1 << HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_OFFSET; - reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG, data, mask); - - /* Trigger sampler enable pulse (by toggleing the bit) */ - mask = HPIPE_SMAPLER_MASK; - data = 0x1 << HPIPE_SMAPLER_OFFSET; - reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask); - mask = HPIPE_SMAPLER_MASK; - data = 0x0 << HPIPE_SMAPLER_OFFSET; - reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask); - - /* VDD Calibration Control 3 */ - mask = HPIPE_EXT_SELLV_RXSAMPL_MASK; - data = 0x10 << HPIPE_EXT_SELLV_RXSAMPL_OFFSET; - reg_set(hpipe_addr + HPIPE_VDD_CAL_CTRL_REG, data, mask); - - /* DFE Resolution Control */ - mask = HPIPE_DFE_RES_FORCE_MASK; - data = 0x1 << HPIPE_DFE_RES_FORCE_OFFSET; - reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask); - - /* DFE F3-F5 Coefficient Control */ - mask = HPIPE_DFE_F3_F5_DFE_EN_MASK; - data = 0x0 << HPIPE_DFE_F3_F5_DFE_EN_OFFSET; - mask |= HPIPE_DFE_F3_F5_DFE_CTRL_MASK; - data = 0x0 << HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET; - reg_set(hpipe_addr + HPIPE_DFE_F3_F5_REG, data, mask); - - /* G3 Setting 3 */ - mask = HPIPE_G3_FFE_CAP_SEL_MASK; - data = 0xf << HPIPE_G3_FFE_CAP_SEL_OFFSET; - mask |= HPIPE_G3_FFE_RES_SEL_MASK; - data |= 0x4 << HPIPE_G3_FFE_RES_SEL_OFFSET; - mask |= HPIPE_G3_FFE_SETTING_FORCE_MASK; - data |= 0x1 << HPIPE_G3_FFE_SETTING_FORCE_OFFSET; - mask |= HPIPE_G3_FFE_DEG_RES_LEVEL_MASK; - data |= 0x1 << HPIPE_G3_FFE_DEG_RES_LEVEL_OFFSET; - mask |= HPIPE_G3_FFE_LOAD_RES_LEVEL_MASK; - data |= 0x3 << HPIPE_G3_FFE_LOAD_RES_LEVEL_OFFSET; - reg_set(hpipe_addr + HPIPE_G3_SETTING_3_REG, data, mask); - - /* G3 Setting 4 */ - mask = HPIPE_G3_DFE_RES_MASK; - data = 0x2 << HPIPE_G3_DFE_RES_OFFSET; - reg_set(hpipe_addr + HPIPE_G3_SETTING_4_REG, data, mask); - - /* Offset Phase Control */ - mask = HPIPE_OS_PH_OFFSET_MASK; - data = 0x5c << HPIPE_OS_PH_OFFSET_OFFSET; - mask |= HPIPE_OS_PH_OFFSET_FORCE_MASK; - data |= 0x1 << HPIPE_OS_PH_OFFSET_FORCE_OFFSET; - reg_set(hpipe_addr + HPIPE_PHASE_CONTROL_REG, data, mask); - mask = HPIPE_OS_PH_VALID_MASK; - data = 0x1 << HPIPE_OS_PH_VALID_OFFSET; - reg_set(hpipe_addr + HPIPE_PHASE_CONTROL_REG, data, mask); - mask = HPIPE_OS_PH_VALID_MASK; - data = 0x0 << HPIPE_OS_PH_VALID_OFFSET; - reg_set(hpipe_addr + HPIPE_PHASE_CONTROL_REG, data, mask); - - /* Set G1 TX amplitude and TX post emphasis value */ - mask = HPIPE_G1_SET_0_G1_TX_AMP_MASK; - data = 0x8 << HPIPE_G1_SET_0_G1_TX_AMP_OFFSET; - mask |= HPIPE_G1_SET_0_G1_TX_AMP_ADJ_MASK; - data |= 0x1 << HPIPE_G1_SET_0_G1_TX_AMP_ADJ_OFFSET; - mask |= HPIPE_G1_SET_0_G1_TX_EMPH1_MASK; - data |= 0x1 << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET; - mask |= HPIPE_G1_SET_0_G1_TX_EMPH1_EN_MASK; - data |= 0x1 << HPIPE_G1_SET_0_G1_TX_EMPH1_EN_OFFSET; - reg_set(hpipe_addr + HPIPE_G1_SET_0_REG, data, mask); - - /* Set G2 TX amplitude and TX post emphasis value */ - mask = HPIPE_G2_SET_0_G2_TX_AMP_MASK; - data = 0xa << HPIPE_G2_SET_0_G2_TX_AMP_OFFSET; - mask |= HPIPE_G2_SET_0_G2_TX_AMP_ADJ_MASK; - data |= 0x1 << HPIPE_G2_SET_0_G2_TX_AMP_ADJ_OFFSET; - mask |= HPIPE_G2_SET_0_G2_TX_EMPH1_MASK; - data |= 0x2 << HPIPE_G2_SET_0_G2_TX_EMPH1_OFFSET; - mask |= HPIPE_G2_SET_0_G2_TX_EMPH1_EN_MASK; - data |= 0x1 << HPIPE_G2_SET_0_G2_TX_EMPH1_EN_OFFSET; - reg_set(hpipe_addr + HPIPE_G2_SET_0_REG, data, mask); - - /* Set G3 TX amplitude and TX post emphasis value */ - mask = HPIPE_G3_SET_0_G3_TX_AMP_MASK; - data = 0xe << HPIPE_G3_SET_0_G3_TX_AMP_OFFSET; - mask |= HPIPE_G3_SET_0_G3_TX_AMP_ADJ_MASK; - data |= 0x1 << HPIPE_G3_SET_0_G3_TX_AMP_ADJ_OFFSET; - mask |= HPIPE_G3_SET_0_G3_TX_EMPH1_MASK; - data |= 0x6 << HPIPE_G3_SET_0_G3_TX_EMPH1_OFFSET; - mask |= HPIPE_G3_SET_0_G3_TX_EMPH1_EN_MASK; - data |= 0x1 << HPIPE_G3_SET_0_G3_TX_EMPH1_EN_OFFSET; - mask |= HPIPE_G3_SET_0_G3_TX_SLEW_RATE_SEL_MASK; - data |= 0x4 << HPIPE_G3_SET_0_G3_TX_SLEW_RATE_SEL_OFFSET; - mask |= HPIPE_G3_SET_0_G3_TX_SLEW_CTRL_EN_MASK; - data |= 0x0 << HPIPE_G3_SET_0_G3_TX_SLEW_CTRL_EN_OFFSET; - reg_set(hpipe_addr + HPIPE_G3_SET_0_REG, data, mask); - - /* SERDES External Configuration 2 register */ - mask = SD_EXTERNAL_CONFIG2_SSC_ENABLE_MASK; - data = 0x1 << SD_EXTERNAL_CONFIG2_SSC_ENABLE_OFFSET; - reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG2_REG, data, mask); - - /* DFE reset sequence */ - reg_set(hpipe_addr + HPIPE_PWR_CTR_REG, - 0x1 << HPIPE_PWR_CTR_RST_DFE_OFFSET, - HPIPE_PWR_CTR_RST_DFE_MASK); - reg_set(hpipe_addr + HPIPE_PWR_CTR_REG, - 0x0 << HPIPE_PWR_CTR_RST_DFE_OFFSET, - HPIPE_PWR_CTR_RST_DFE_MASK); - - /* Set RX / TX swaps */ - data = mask = 0; - if (invert & PHY_POLARITY_TXD_INVERT) { - data |= (1 << HPIPE_SYNC_PATTERN_TXD_SWAP_OFFSET); - mask |= HPIPE_SYNC_PATTERN_TXD_SWAP_MASK; - } - if (invert & PHY_POLARITY_RXD_INVERT) { - data |= (1 << HPIPE_SYNC_PATTERN_RXD_SWAP_OFFSET); - mask |= HPIPE_SYNC_PATTERN_RXD_SWAP_MASK; - } - reg_set(hpipe_addr + HPIPE_SYNC_PATTERN_REG, data, mask); - - /* SW reset for interupt logic */ - reg_set(hpipe_addr + HPIPE_PWR_CTR_REG, - 0x1 << HPIPE_PWR_CTR_SFT_RST_OFFSET, - HPIPE_PWR_CTR_SFT_RST_MASK); - reg_set(hpipe_addr + HPIPE_PWR_CTR_REG, - 0x0 << HPIPE_PWR_CTR_SFT_RST_OFFSET, - HPIPE_PWR_CTR_SFT_RST_MASK); - - debug("stage: Comphy power up\n"); /* * MAC configuration power up comphy - power up PLL/TX/RX * use indirect address for vendor spesific SATA control register @@ -981,469 +350,7 @@ static int comphy_sata_power_up(u32 lane, void __iomem *hpipe_base, reg_set(sata_base + SATA3_VENDOR_DATA, 0x1 << SATA_MBUS_REGRET_EN_OFFSET, SATA_MBUS_REGRET_EN_MASK); - debug("stage: Check PLL\n"); - - addr = sd_ip_addr + SD_EXTERNAL_STATUS0_REG; - data = SD_EXTERNAL_STATUS0_PLL_TX_MASK & - SD_EXTERNAL_STATUS0_PLL_RX_MASK; - mask = data; - data = polling_with_timeout(addr, data, mask, 15000); - if (data != 0) { - debug("Read from reg = %p - value = 0x%x\n", - hpipe_addr + HPIPE_LANE_STATUS1_REG, data); - pr_err("SD_EXTERNAL_STATUS0_PLL_TX is %d, SD_EXTERNAL_STATUS0_PLL_RX is %d\n", - (data & SD_EXTERNAL_STATUS0_PLL_TX_MASK), - (data & SD_EXTERNAL_STATUS0_PLL_RX_MASK)); - ret = 0; - } - - debug_exit(); - return ret; -} - -static int comphy_sgmii_power_up(u32 lane, u32 sgmii_speed, - void __iomem *hpipe_base, - void __iomem *comphy_base) -{ - u32 mask, data, ret = 1; - void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base, lane); - void __iomem *sd_ip_addr = SD_ADDR(hpipe_base, lane); - void __iomem *comphy_addr = COMPHY_ADDR(comphy_base, lane); - void __iomem *addr; - - debug_enter(); - debug("stage: RFU configurations - hard reset comphy\n"); - /* RFU configurations - hard reset comphy */ - mask = COMMON_PHY_CFG1_PWR_UP_MASK; - data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET; - mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK; - data |= 0x0 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET; - reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); - - /* Select Baud Rate of Comphy And PD_PLL/Tx/Rx */ - mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK; - data = 0x0 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET; - mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_MASK; - mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_MASK; - if (sgmii_speed == PHY_SPEED_1_25G) { - data |= 0x6 << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET; - data |= 0x6 << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET; - } else { - /* 3.125G */ - data |= 0x8 << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET; - data |= 0x8 << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET; - } - mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK; - data |= 0 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET; - mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK; - data |= 0 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET; - mask |= SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_MASK; - data |= 1 << SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET; - reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask); - - /* release from hard reset */ - mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK; - data = 0x0 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET; - mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK; - data |= 0x0 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET; - mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK; - data |= 0x0 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET; - reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); - - /* release from hard reset */ - mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK; - data = 0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET; - mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK; - data |= 0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET; - reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); - - - /* Wait 1ms - until band gap and ref clock ready */ - mdelay(1); - - /* Start comphy Configuration */ - debug("stage: Comphy configuration\n"); - /* set reference clock */ - mask = HPIPE_MISC_REFCLK_SEL_MASK; - data = 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET; - reg_set(hpipe_addr + HPIPE_MISC_REG, data, mask); - /* Power and PLL Control */ - mask = HPIPE_PWR_PLL_REF_FREQ_MASK; - data = 0x1 << HPIPE_PWR_PLL_REF_FREQ_OFFSET; - mask |= HPIPE_PWR_PLL_PHY_MODE_MASK; - data |= 0x4 << HPIPE_PWR_PLL_PHY_MODE_OFFSET; - reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask); - /* Loopback register */ - mask = HPIPE_LOOPBACK_SEL_MASK; - data = 0x1 << HPIPE_LOOPBACK_SEL_OFFSET; - reg_set(hpipe_addr + HPIPE_LOOPBACK_REG, data, mask); - /* rx control 1 */ - mask = HPIPE_RX_CONTROL_1_RXCLK2X_SEL_MASK; - data = 0x1 << HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET; - mask |= HPIPE_RX_CONTROL_1_CLK8T_EN_MASK; - data |= 0x0 << HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET; - reg_set(hpipe_addr + HPIPE_RX_CONTROL_1_REG, data, mask); - /* DTL Control */ - mask = HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK; - data = 0x0 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET; - reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG, data, mask); - - /* Set analog paramters from ETP(HW) - for now use the default datas */ - debug("stage: Analog paramters from ETP(HW)\n"); - - reg_set(hpipe_addr + HPIPE_G1_SET_0_REG, - 0x1 << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET, - HPIPE_G1_SET_0_G1_TX_EMPH1_MASK); - - debug("stage: RFU configurations- Power Up PLL,Tx,Rx\n"); - /* SERDES External Configuration */ - mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK; - data = 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET; - mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK; - data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET; - mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK; - data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET; - reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask); - - /* check PLL rx & tx ready */ - addr = sd_ip_addr + SD_EXTERNAL_STATUS0_REG; - data = SD_EXTERNAL_STATUS0_PLL_RX_MASK | - SD_EXTERNAL_STATUS0_PLL_TX_MASK; - mask = data; - data = polling_with_timeout(addr, data, mask, 15000); - if (data != 0) { - debug("Read from reg = %p - value = 0x%x\n", - sd_ip_addr + SD_EXTERNAL_STATUS0_REG, data); - pr_err("SD_EXTERNAL_STATUS0_PLL_RX is %d, SD_EXTERNAL_STATUS0_PLL_TX is %d\n", - (data & SD_EXTERNAL_STATUS0_PLL_RX_MASK), - (data & SD_EXTERNAL_STATUS0_PLL_TX_MASK)); - ret = 0; - } - - /* RX init */ - mask = SD_EXTERNAL_CONFIG1_RX_INIT_MASK; - data = 0x1 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET; - reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); - - /* check that RX init done */ - addr = sd_ip_addr + SD_EXTERNAL_STATUS0_REG; - data = SD_EXTERNAL_STATUS0_RX_INIT_MASK; - mask = data; - data = polling_with_timeout(addr, data, mask, 100); - if (data != 0) { - debug("Read from reg = %p - value = 0x%x\n", sd_ip_addr + SD_EXTERNAL_STATUS0_REG, data); - pr_err("SD_EXTERNAL_STATUS0_RX_INIT is 0\n"); - ret = 0; - } - - debug("stage: RF Reset\n"); - /* RF Reset */ - mask = SD_EXTERNAL_CONFIG1_RX_INIT_MASK; - data = 0x0 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET; - mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK; - data |= 0x1 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET; - reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); - - debug_exit(); - return ret; -} - -static int comphy_sfi_power_up(u32 lane, void __iomem *hpipe_base, - void __iomem *comphy_base, u32 speed) -{ - u32 mask, data, ret = 1; - void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base, lane); - void __iomem *sd_ip_addr = SD_ADDR(hpipe_base, lane); - void __iomem *comphy_addr = COMPHY_ADDR(comphy_base, lane); - void __iomem *addr; - - debug_enter(); - debug("stage: RFU configurations - hard reset comphy\n"); - /* RFU configurations - hard reset comphy */ - mask = COMMON_PHY_CFG1_PWR_UP_MASK; - data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET; - mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK; - data |= 0x0 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET; - reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); - - /* Select Baud Rate of Comphy And PD_PLL/Tx/Rx */ - mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK; - data = 0x0 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET; - mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_MASK; - data |= 0xE << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET; - mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_MASK; - data |= 0xE << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET; - mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK; - data |= 0 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET; - mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK; - data |= 0 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET; - mask |= SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_MASK; - data |= 0 << SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET; - reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask); - - /* release from hard reset */ - mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK; - data = 0x0 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET; - mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK; - data |= 0x0 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET; - mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK; - data |= 0x0 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET; - reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); - - mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK; - data = 0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET; - mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK; - data |= 0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET; - reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); - - - /* Wait 1ms - until band gap and ref clock ready */ - mdelay(1); - - /* Start comphy Configuration */ - debug("stage: Comphy configuration\n"); - /* set reference clock */ - mask = HPIPE_MISC_ICP_FORCE_MASK; - data = (speed == PHY_SPEED_5_15625G) ? - (0x0 << HPIPE_MISC_ICP_FORCE_OFFSET) : - (0x1 << HPIPE_MISC_ICP_FORCE_OFFSET); - mask |= HPIPE_MISC_REFCLK_SEL_MASK; - data |= 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET; - reg_set(hpipe_addr + HPIPE_MISC_REG, data, mask); - /* Power and PLL Control */ - mask = HPIPE_PWR_PLL_REF_FREQ_MASK; - data = 0x1 << HPIPE_PWR_PLL_REF_FREQ_OFFSET; - mask |= HPIPE_PWR_PLL_PHY_MODE_MASK; - data |= 0x4 << HPIPE_PWR_PLL_PHY_MODE_OFFSET; - reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask); - /* Loopback register */ - mask = HPIPE_LOOPBACK_SEL_MASK; - data = 0x1 << HPIPE_LOOPBACK_SEL_OFFSET; - reg_set(hpipe_addr + HPIPE_LOOPBACK_REG, data, mask); - /* rx control 1 */ - mask = HPIPE_RX_CONTROL_1_RXCLK2X_SEL_MASK; - data = 0x1 << HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET; - mask |= HPIPE_RX_CONTROL_1_CLK8T_EN_MASK; - data |= 0x1 << HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET; - reg_set(hpipe_addr + HPIPE_RX_CONTROL_1_REG, data, mask); - /* DTL Control */ - mask = HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK; - data = 0x1 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET; - reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG, data, mask); - - /* Transmitter/Receiver Speed Divider Force */ - if (speed == PHY_SPEED_5_15625G) { - mask = HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_MASK; - data = 1 << HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_OFFSET; - mask |= HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_FORCE_MASK; - data |= 1 << HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_FORCE_OFFSET; - mask |= HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_MASK; - data |= 1 << HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_OFFSET; - mask |= HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_MASK; - data |= 1 << HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_OFFSET; - } else { - mask = HPIPE_TXDIGCK_DIV_FORCE_MASK; - data = 0x1 << HPIPE_TXDIGCK_DIV_FORCE_OFFSET; - } - reg_set(hpipe_addr + HPIPE_SPD_DIV_FORCE_REG, data, mask); - - /* Set analog paramters from ETP(HW) */ - debug("stage: Analog paramters from ETP(HW)\n"); - /* SERDES External Configuration 2 */ - mask = SD_EXTERNAL_CONFIG2_PIN_DFE_EN_MASK; - data = 0x1 << SD_EXTERNAL_CONFIG2_PIN_DFE_EN_OFFSET; - reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG2_REG, data, mask); - /* 0x7-DFE Resolution control */ - mask = HPIPE_DFE_RES_FORCE_MASK; - data = 0x1 << HPIPE_DFE_RES_FORCE_OFFSET; - reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask); - /* 0xd-G1_Setting_0 */ - if (speed == PHY_SPEED_5_15625G) { - mask = HPIPE_G1_SET_0_G1_TX_EMPH1_MASK; - data = 0x6 << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET; - } else { - mask = HPIPE_G1_SET_0_G1_TX_AMP_MASK; - data = 0x1c << HPIPE_G1_SET_0_G1_TX_AMP_OFFSET; - mask |= HPIPE_G1_SET_0_G1_TX_EMPH1_MASK; - data |= 0xe << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET; - } - reg_set(hpipe_addr + HPIPE_G1_SET_0_REG, data, mask); - /* Genration 1 setting 2 (G1_Setting_2) */ - mask = HPIPE_G1_SET_2_G1_TX_EMPH0_MASK; - data = 0x0 << HPIPE_G1_SET_2_G1_TX_EMPH0_OFFSET; - mask |= HPIPE_G1_SET_2_G1_TX_EMPH0_EN_MASK; - data |= 0x1 << HPIPE_G1_SET_2_G1_TX_EMPH0_EN_OFFSET; - reg_set(hpipe_addr + HPIPE_G1_SET_2_REG, data, mask); - /* Transmitter Slew Rate Control register (tx_reg1) */ - mask = HPIPE_TX_REG1_TX_EMPH_RES_MASK; - data = 0x3 << HPIPE_TX_REG1_TX_EMPH_RES_OFFSET; - mask |= HPIPE_TX_REG1_SLC_EN_MASK; - data |= 0x3f << HPIPE_TX_REG1_SLC_EN_OFFSET; - reg_set(hpipe_addr + HPIPE_TX_REG1_REG, data, mask); - /* Impedance Calibration Control register (cal_reg1) */ - mask = HPIPE_CAL_REG_1_EXT_TXIMP_MASK; - data = 0xe << HPIPE_CAL_REG_1_EXT_TXIMP_OFFSET; - mask |= HPIPE_CAL_REG_1_EXT_TXIMP_EN_MASK; - data |= 0x1 << HPIPE_CAL_REG_1_EXT_TXIMP_EN_OFFSET; - reg_set(hpipe_addr + HPIPE_CAL_REG1_REG, data, mask); - /* Generation 1 Setting 5 (g1_setting_5) */ - mask = HPIPE_G1_SETTING_5_G1_ICP_MASK; - data = 0 << HPIPE_CAL_REG_1_EXT_TXIMP_OFFSET; - reg_set(hpipe_addr + HPIPE_G1_SETTING_5_REG, data, mask); - /* 0xE-G1_Setting_1 */ - mask = HPIPE_G1_SET_1_G1_RX_DFE_EN_MASK; - data = 0x1 << HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET; - if (speed == PHY_SPEED_5_15625G) { - mask |= HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK; - data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET; - mask |= HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK; - data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET; - } else { - mask |= HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK; - data |= 0x2 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET; - mask |= HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK; - data |= 0x2 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET; - mask |= HPIPE_G1_SET_1_G1_RX_SELMUFI_MASK; - data |= 0x0 << HPIPE_G1_SET_1_G1_RX_SELMUFI_OFFSET; - mask |= HPIPE_G1_SET_1_G1_RX_SELMUFF_MASK; - data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUFF_OFFSET; - mask |= HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_MASK; - data |= 0x3 << HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_OFFSET; - } - reg_set(hpipe_addr + HPIPE_G1_SET_1_REG, data, mask); - - /* 0xA-DFE_Reg3 */ - mask = HPIPE_DFE_F3_F5_DFE_EN_MASK; - data = 0x0 << HPIPE_DFE_F3_F5_DFE_EN_OFFSET; - mask |= HPIPE_DFE_F3_F5_DFE_CTRL_MASK; - data |= 0x0 << HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET; - reg_set(hpipe_addr + HPIPE_DFE_F3_F5_REG, data, mask); - - /* 0x111-G1_Setting_4 */ - mask = HPIPE_G1_SETTINGS_4_G1_DFE_RES_MASK; - data = 0x1 << HPIPE_G1_SETTINGS_4_G1_DFE_RES_OFFSET; - reg_set(hpipe_addr + HPIPE_G1_SETTINGS_4_REG, data, mask); - /* Genration 1 setting 3 (G1_Setting_3) */ - mask = HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_MASK; - data = 0x1 << HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_OFFSET; - if (speed == PHY_SPEED_5_15625G) { - /* Force FFE (Feed Forward Equalization) to 5G */ - mask |= HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_MASK; - data |= 0xf << HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_OFFSET; - mask |= HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_MASK; - data |= 0x4 << HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_OFFSET; - mask |= HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_MASK; - data |= 0x1 << HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_OFFSET; - } - reg_set(hpipe_addr + HPIPE_G1_SETTINGS_3_REG, data, mask); - - /* Connfigure RX training timer */ - mask = HPIPE_RX_TRAIN_TIMER_MASK; - data = 0x13 << HPIPE_RX_TRAIN_TIMER_OFFSET; - reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_5_REG, data, mask); - - /* Enable TX train peak to peak hold */ - mask = HPIPE_TX_TRAIN_P2P_HOLD_MASK; - data = 0x1 << HPIPE_TX_TRAIN_P2P_HOLD_OFFSET; - reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_0_REG, data, mask); - - /* Configure TX preset index */ - mask = HPIPE_TX_PRESET_INDEX_MASK; - data = 0x2 << HPIPE_TX_PRESET_INDEX_OFFSET; - reg_set(hpipe_addr + HPIPE_TX_PRESET_INDEX_REG, data, mask); - - /* Disable pattern lock lost timeout */ - mask = HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_MASK; - data = 0x0 << HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_OFFSET; - reg_set(hpipe_addr + HPIPE_FRAME_DETECT_CTRL_3_REG, data, mask); - - /* Configure TX training pattern and TX training 16bit auto */ - mask = HPIPE_TX_TRAIN_16BIT_AUTO_EN_MASK; - data = 0x1 << HPIPE_TX_TRAIN_16BIT_AUTO_EN_OFFSET; - mask |= HPIPE_TX_TRAIN_PAT_SEL_MASK; - data |= 0x1 << HPIPE_TX_TRAIN_PAT_SEL_OFFSET; - reg_set(hpipe_addr + HPIPE_TX_TRAIN_REG, data, mask); - - /* Configure Training patten number */ - mask = HPIPE_TRAIN_PAT_NUM_MASK; - data = 0x88 << HPIPE_TRAIN_PAT_NUM_OFFSET; - reg_set(hpipe_addr + HPIPE_FRAME_DETECT_CTRL_0_REG, data, mask); - - /* Configure differencial manchester encoter to ethernet mode */ - mask = HPIPE_DME_ETHERNET_MODE_MASK; - data = 0x1 << HPIPE_DME_ETHERNET_MODE_OFFSET; - reg_set(hpipe_addr + HPIPE_DME_REG, data, mask); - - /* Configure VDD Continuous Calibration */ - mask = HPIPE_CAL_VDD_CONT_MODE_MASK; - data = 0x1 << HPIPE_CAL_VDD_CONT_MODE_OFFSET; - reg_set(hpipe_addr + HPIPE_VDD_CAL_0_REG, data, mask); - - /* Trigger sampler enable pulse (by toggleing the bit) */ - mask = HPIPE_RX_SAMPLER_OS_GAIN_MASK; - data = 0x3 << HPIPE_RX_SAMPLER_OS_GAIN_OFFSET; - mask |= HPIPE_SMAPLER_MASK; - data |= 0x1 << HPIPE_SMAPLER_OFFSET; - reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask); - mask = HPIPE_SMAPLER_MASK; - data = 0x0 << HPIPE_SMAPLER_OFFSET; - reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask); - - /* Set External RX Regulator Control */ - mask = HPIPE_EXT_SELLV_RXSAMPL_MASK; - data = 0x1A << HPIPE_EXT_SELLV_RXSAMPL_OFFSET; - reg_set(hpipe_addr + HPIPE_VDD_CAL_CTRL_REG, data, mask); - - debug("stage: RFU configurations- Power Up PLL,Tx,Rx\n"); - /* SERDES External Configuration */ - mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK; - data = 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET; - mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK; - data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET; - mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK; - data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET; - reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask); - - - /* check PLL rx & tx ready */ - addr = sd_ip_addr + SD_EXTERNAL_STATUS0_REG; - data = SD_EXTERNAL_STATUS0_PLL_RX_MASK | - SD_EXTERNAL_STATUS0_PLL_TX_MASK; - mask = data; - data = polling_with_timeout(addr, data, mask, 15000); - if (data != 0) { - debug("Read from reg = %p - value = 0x%x\n", sd_ip_addr + SD_EXTERNAL_STATUS0_REG, data); - pr_err("SD_EXTERNAL_STATUS0_PLL_RX is %d, SD_EXTERNAL_STATUS0_PLL_TX is %d\n", - (data & SD_EXTERNAL_STATUS0_PLL_RX_MASK), - (data & SD_EXTERNAL_STATUS0_PLL_TX_MASK)); - ret = 0; - } - - /* RX init */ - mask = SD_EXTERNAL_CONFIG1_RX_INIT_MASK; - data = 0x1 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET; - reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); - - - /* check that RX init done */ - addr = sd_ip_addr + SD_EXTERNAL_STATUS0_REG; - data = SD_EXTERNAL_STATUS0_RX_INIT_MASK; - mask = data; - data = polling_with_timeout(addr, data, mask, 100); - if (data != 0) { - debug("Read from reg = %p - value = 0x%x\n", - sd_ip_addr + SD_EXTERNAL_STATUS0_REG, data); - pr_err("SD_EXTERNAL_STATUS0_RX_INIT is 0\n"); - ret = 0; - } - - debug("stage: RF Reset\n"); - /* RF Reset */ - mask = SD_EXTERNAL_CONFIG1_RX_INIT_MASK; - data = 0x0 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET; - mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK; - data |= 0x1 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET; - reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); + ret = comphy_smc(MV_SIP_COMPHY_PLL_LOCK, comphy_base_addr, lane, type); debug_exit(); return ret; @@ -1973,6 +880,7 @@ int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg, void __iomem *comphy_base_addr, *hpipe_base_addr; u32 comphy_max_count, lane, ret = 0; u32 pcie_width = 0; + u32 mode; debug_enter(); @@ -2011,19 +919,23 @@ int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg, case PHY_TYPE_PEX1: case PHY_TYPE_PEX2: case PHY_TYPE_PEX3: - ret = comphy_pcie_power_up( - lane, pcie_width, ptr_comphy_map->clk_src, - serdes_map->end_point, - hpipe_base_addr, comphy_base_addr); + mode = COMPHY_FW_PCIE_FORMAT(pcie_width, + ptr_comphy_map->clk_src, + COMPHY_PCIE_MODE, + ptr_comphy_map->speed); + ret = comphy_smc(MV_SIP_COMPHY_POWER_ON, + ptr_chip_cfg->comphy_base_addr, lane, + mode); break; case PHY_TYPE_SATA0: case PHY_TYPE_SATA1: case PHY_TYPE_SATA2: case PHY_TYPE_SATA3: - ret = comphy_sata_power_up( - lane, hpipe_base_addr, comphy_base_addr, - ptr_chip_cfg->cp_index, - serdes_map[lane].invert); + mode = COMPHY_FW_MODE_FORMAT(COMPHY_SATA_MODE); + ret = comphy_sata_power_up(lane, hpipe_base_addr, + comphy_base_addr, + ptr_chip_cfg->cp_index, + mode); break; case PHY_TYPE_USB3_HOST0: case PHY_TYPE_USB3_HOST1: @@ -2033,6 +945,25 @@ int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg, break; case PHY_TYPE_SGMII0: case PHY_TYPE_SGMII1: + if (ptr_comphy_map->speed == PHY_SPEED_INVALID) { + debug("Warning: "); + debug("SGMII PHY speed in lane %d is invalid,", + lane); + debug(" set PHY speed to 1.25G\n"); + ptr_comphy_map->speed = PHY_SPEED_1_25G; + } + + /* + * UINIT_ID not relevant for SGMII0 and SGMII1 - will be + * ignored by firmware + */ + mode = COMPHY_FW_FORMAT(COMPHY_SGMII_MODE, + COMPHY_UNIT_ID0, + ptr_comphy_map->speed); + ret = comphy_smc(MV_SIP_COMPHY_POWER_ON, + ptr_chip_cfg->comphy_base_addr, lane, + mode); + break; case PHY_TYPE_SGMII2: case PHY_TYPE_SGMII3: if (ptr_comphy_map->speed == PHY_SPEED_INVALID) { @@ -2040,14 +971,21 @@ int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg, lane); ptr_comphy_map->speed = PHY_SPEED_1_25G; } - ret = comphy_sgmii_power_up( - lane, ptr_comphy_map->speed, hpipe_base_addr, - comphy_base_addr); + + mode = COMPHY_FW_FORMAT(COMPHY_SGMII_MODE, + COMPHY_UNIT_ID2, + ptr_comphy_map->speed); + ret = comphy_smc(MV_SIP_COMPHY_POWER_ON, + ptr_chip_cfg->comphy_base_addr, lane, + mode); break; case PHY_TYPE_SFI: - ret = comphy_sfi_power_up(lane, hpipe_base_addr, - comphy_base_addr, - ptr_comphy_map->speed); + mode = COMPHY_FW_FORMAT(COMPHY_SFI_MODE, + COMPHY_UNIT_ID0, + ptr_comphy_map->speed); + ret = comphy_smc(MV_SIP_COMPHY_POWER_ON, + ptr_chip_cfg->comphy_base_addr, lane, + mode); break; case PHY_TYPE_RXAUI0: case PHY_TYPE_RXAUI1: diff --git a/drivers/ram/rockchip/Kconfig b/drivers/ram/rockchip/Kconfig index 8e97c2f..c459bbf 100644 --- a/drivers/ram/rockchip/Kconfig +++ b/drivers/ram/rockchip/Kconfig @@ -22,6 +22,27 @@ config RAM_ROCKCHIP_DEBUG This is an option for developers to understand the ram drivers initialization, configurations and etc. +config RAM_PX30_DDR4 + bool "DDR3 support for Rockchip PX30" + depends on RAM_ROCKCHIP && ROCKCHIP_PX30 + help + This enables DDR4 sdram support instead of the default DDR3 support + on Rockchip PC30 SoCs. + +config RAM_PX30_LPDDR2 + bool "LPDDR2 support for Rockchip PX30" + depends on RAM_ROCKCHIP && ROCKCHIP_PX30 + help + This enables LPDDR2 sdram support instead of the default DDR3 support + on Rockchip PC30 SoCs. + +config RAM_PX30_LPDDR3 + bool "LPDDR3 support for Rockchip PX30" + depends on RAM_ROCKCHIP && ROCKCHIP_PX30 + help + This enables LPDDR3 sdram support instead of the default DDR3 support + on Rockchip PC30 SoCs. + config RAM_RK3399_LPDDR4 bool "LPDDR4 support for Rockchip RK3399" depends on RAM_ROCKCHIP && ROCKCHIP_RK3399 diff --git a/drivers/ram/rockchip/sdram_px30.c b/drivers/ram/rockchip/sdram_px30.c index fd5763d..2f1f6e9 100644 --- a/drivers/ram/rockchip/sdram_px30.c +++ b/drivers/ram/rockchip/sdram_px30.c @@ -125,7 +125,15 @@ u32 addrmap[][8] = { struct dram_info dram_info; struct px30_sdram_params sdram_configs[] = { +#if defined(CONFIG_RAM_PX30_DDR4) +#include "sdram-px30-ddr4-detect-333.inc" +#elif defined(CONFIG_RAM_PX30_LPDDR2) +#include "sdram-px30-lpddr2-detect-333.inc" +#elif defined(CONFIG_RAM_PX30_LPDDR3) +#include "sdram-px30-lpddr3-detect-333.inc" +#else #include "sdram-px30-ddr3-detect-333.inc" +#endif }; struct ddr_phy_skew skew = { diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig index d06d272..cad667a 100644 --- a/drivers/rtc/Kconfig +++ b/drivers/rtc/Kconfig @@ -68,11 +68,14 @@ config RTC_EMULATION depends on DM_RTC help On a board without hardware clock this software real time clock can be - used. The build time is used to initialize the RTC. So you will have - to adjust the time either manually using the 'date' command or use - the 'sntp' to update the RTC with the time from a network time server. - See CONFIG_CMD_SNTP and CONFIG_BOOTP_NTPSERVER. The RTC time is - advanced according to CPU ticks. + used. The initial time may be provided via the environment variable + 'rtc_emul_epoch' as a decimal string indicating seconds since + 1970-01-01. If the environment variable is missing, the build time is + used to initialize the RTC. The time can be adjusted manually via the + 'date' command or the 'sntp' command can be used to update the RTC + with the time from a network time server. See CONFIG_CMD_SNTP and + CONFIG_BOOTP_NTPSERVER. The RTC time is advanced according to CPU + ticks. config RTC_ISL1208 bool "Enable ISL1208 driver" diff --git a/drivers/rtc/emul_rtc.c b/drivers/rtc/emul_rtc.c index c98c24b..7e52210 100644 --- a/drivers/rtc/emul_rtc.c +++ b/drivers/rtc/emul_rtc.c @@ -8,6 +8,7 @@ #include <common.h> #include <div64.h> #include <dm.h> +#include <env.h> #include <generated/timestamp_autogenerated.h> #include <rtc.h> @@ -30,12 +31,6 @@ static int emul_rtc_get(struct udevice *dev, struct rtc_time *time) struct emul_rtc *priv = dev_get_priv(dev); u64 now; - if (!priv->offset_us) { - /* Use the build date as initial time */ - priv->offset_us = U_BOOT_EPOCH * 1000000ULL - timer_get_us(); - priv->isdst = -1; - } - now = timer_get_us() + priv->offset_us; do_div(now, 1000000); rtc_to_tm(now, time); @@ -63,6 +58,26 @@ static int emul_rtc_set(struct udevice *dev, const struct rtc_time *time) return 0; } +int emul_rtc_probe(struct udevice *dev) +{ + struct emul_rtc *priv = dev_get_priv(dev); + const char *epoch_str; + u64 epoch; + + epoch_str = env_get("rtc_emul_epoch"); + + if (epoch_str) { + epoch = simple_strtoull(epoch_str, NULL, 10); + } else { + /* Use the build date as initial time */ + epoch = U_BOOT_EPOCH; + } + priv->offset_us = epoch * 1000000ULL - timer_get_us(); + priv->isdst = -1; + + return 0; +} + static const struct rtc_ops emul_rtc_ops = { .get = emul_rtc_get, .set = emul_rtc_set, @@ -72,6 +87,7 @@ U_BOOT_DRIVER(rtc_emul) = { .name = "rtc_emul", .id = UCLASS_RTC, .ops = &emul_rtc_ops, + .probe = emul_rtc_probe, .priv_auto_alloc_size = sizeof(struct emul_rtc), }; diff --git a/drivers/rtc/rtc-uclass.c b/drivers/rtc/rtc-uclass.c index 8035f7f..b406bab 100644 --- a/drivers/rtc/rtc-uclass.c +++ b/drivers/rtc/rtc-uclass.c @@ -174,5 +174,7 @@ int rtc_write32(struct udevice *dev, unsigned int reg, u32 value) UCLASS_DRIVER(rtc) = { .name = "rtc", .id = UCLASS_RTC, +#if !CONFIG_IS_ENABLED(OF_PLATDATA) .post_bind = dm_scan_fdt_dev, +#endif }; diff --git a/drivers/rtc/sandbox_rtc.c b/drivers/rtc/sandbox_rtc.c index 852770a..d0864b1 100644 --- a/drivers/rtc/sandbox_rtc.c +++ b/drivers/rtc/sandbox_rtc.c @@ -92,8 +92,8 @@ static const struct udevice_id sandbox_rtc_ids[] = { { } }; -U_BOOT_DRIVER(rtc_sandbox) = { - .name = "rtc-sandbox", +U_BOOT_DRIVER(sandbox_rtc) = { + .name = "sandbox_rtc", .id = UCLASS_RTC, .of_match = sandbox_rtc_ids, .ops = &sandbox_rtc_ops, diff --git a/drivers/serial/sandbox.c b/drivers/serial/sandbox.c index f09d291..db2fbac 100644 --- a/drivers/serial/sandbox.c +++ b/drivers/serial/sandbox.c @@ -267,6 +267,7 @@ U_BOOT_DRIVER(sandbox_serial) = { .flags = DM_FLAG_PRE_RELOC, }; +#if !CONFIG_IS_ENABLED(OF_PLATDATA) static const struct sandbox_serial_platdata platdata_non_fdt = { .colour = -1, }; @@ -275,4 +276,6 @@ U_BOOT_DEVICE(serial_sandbox_non_fdt) = { .name = "sandbox_serial", .platdata = &platdata_non_fdt, }; +#endif + #endif /* CONFIG_IS_ENABLED(OF_CONTROL) */ diff --git a/drivers/serial/serial_pl01x.c b/drivers/serial/serial_pl01x.c index 2772c25..d9e35c6 100644 --- a/drivers/serial/serial_pl01x.c +++ b/drivers/serial/serial_pl01x.c @@ -19,6 +19,7 @@ #include <watchdog.h> #include <asm/io.h> #include <serial.h> +#include <dm/device_compat.h> #include <dm/platform_data/serial_pl01x.h> #include <linux/compiler.h> #include "serial_pl01x_internal.h" @@ -362,8 +363,18 @@ int pl01x_serial_ofdata_to_platdata(struct udevice *dev) plat->clock = dev_read_u32_default(dev, "clock", CONFIG_PL011_CLOCK); ret = clk_get_by_index(dev, 0, &clk); if (!ret) { - clk_enable(&clk); + ret = clk_enable(&clk); + if (ret && ret != -ENOSYS) { + dev_err(dev, "failed to enable clock\n"); + return ret; + } + plat->clock = clk_get_rate(&clk); + if (IS_ERR_VALUE(plat->clock)) { + dev_err(dev, "failed to get rate\n"); + return plat->clock; + } + debug("%s: CLK %d\n", __func__, plat->clock); } plat->type = dev_get_driver_data(dev); plat->skip_init = dev_read_bool(dev, "skip-init"); diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c index e1336b8..a91cb78 100644 --- a/drivers/spi/ich.c +++ b/drivers/spi/ich.c @@ -615,6 +615,7 @@ static int ich_spi_exec_op(struct spi_slave *slave, const struct spi_mem_op *op) return ret; } +#if !CONFIG_IS_ENABLED(OF_PLATDATA) /** * ich_spi_get_basics() - Get basic information about the ICH device * @@ -657,6 +658,7 @@ static int ich_spi_get_basics(struct udevice *bus, bool can_probe, return ret; } +#endif /** * ich_get_mmap_bus() - Handle the get_mmap() method for a bus @@ -946,10 +948,10 @@ static int ich_spi_child_pre_probe(struct udevice *dev) static int ich_spi_ofdata_to_platdata(struct udevice *dev) { struct ich_spi_platdata *plat = dev_get_platdata(dev); - int ret; #if !CONFIG_IS_ENABLED(OF_PLATDATA) struct ich_spi_priv *priv = dev_get_priv(dev); + int ret; ret = ich_spi_get_basics(dev, true, &priv->pch, &plat->ich_version, &plat->mmio_base); diff --git a/drivers/spi/xilinx_spi.c b/drivers/spi/xilinx_spi.c index 348630f..47a5571 100644 --- a/drivers/spi/xilinx_spi.c +++ b/drivers/spi/xilinx_spi.c @@ -214,7 +214,7 @@ static void xilinx_spi_startup_block(struct udevice *dev, unsigned int bytes, struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); const unsigned char *txp = dout; unsigned char *rxp = din; - u32 reg, count; + u32 reg; u32 txbytes = bytes; u32 rxbytes = bytes; @@ -224,10 +224,10 @@ static void xilinx_spi_startup_block(struct udevice *dev, unsigned int bytes, * it sets txp to the initial value for the normal operation. */ for ( ; priv->startup < 2; priv->startup++) { - count = xilinx_spi_fill_txfifo(bus, txp, txbytes); + xilinx_spi_fill_txfifo(bus, txp, txbytes); reg = readl(®s->spicr) & ~SPICR_MASTER_INHIBIT; writel(reg, ®s->spicr); - count = xilinx_spi_read_rxfifo(bus, rxp, rxbytes); + xilinx_spi_read_rxfifo(bus, rxp, rxbytes); txp = din; if (priv->startup) { @@ -251,7 +251,7 @@ static int xilinx_spi_xfer(struct udevice *dev, unsigned int bitlen, unsigned char *rxp = din; u32 txbytes = bytes; u32 rxbytes = bytes; - u32 reg, count, timeout; + u32 reg, count; int ret; debug("spi_xfer: bus:%i cs:%i bitlen:%i bytes:%i flags:%lx\n", diff --git a/drivers/spi/zynq_qspi.c b/drivers/spi/zynq_qspi.c index 3f39ef0..f2eddec 100644 --- a/drivers/spi/zynq_qspi.c +++ b/drivers/spi/zynq_qspi.c @@ -6,8 +6,10 @@ * Xilinx Zynq Quad-SPI(QSPI) controller driver (master mode only) */ +#include <clk.h> #include <common.h> #include <dm.h> +#include <dm/device_compat.h> #include <log.h> #include <malloc.h> #include <spi.h> @@ -105,17 +107,29 @@ static int zynq_qspi_ofdata_to_platdata(struct udevice *bus) plat->regs = (struct zynq_qspi_regs *)fdtdec_get_addr(blob, node, "reg"); - /* FIXME: Use 166MHz as a suitable default */ - plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency", - 166666666); - plat->speed_hz = plat->frequency / 2; - - debug("%s: regs=%p max-frequency=%d\n", __func__, - plat->regs, plat->frequency); - return 0; } +/** + * zynq_qspi_init_hw - Initialize the hardware + * @priv: Pointer to the zynq_qspi_priv structure + * + * The default settings of the QSPI controller's configurable parameters on + * reset are + * - Master mode + * - Baud rate divisor is set to 2 + * - Threshold value for TX FIFO not full interrupt is set to 1 + * - Flash memory interface mode enabled + * - Size of the word to be transferred as 8 bit + * This function performs the following actions + * - Disable and clear all the interrupts + * - Enable manual slave select + * - Enable auto start + * - Deselect all the chip select lines + * - Set the size of the word to be transferred as 32 bit + * - Set the little endian mode of TX FIFO and + * - Enable the QSPI controller + */ static void zynq_qspi_init_hw(struct zynq_qspi_priv *priv) { struct zynq_qspi_regs *regs = priv->regs; @@ -159,19 +173,45 @@ static int zynq_qspi_probe(struct udevice *bus) { struct zynq_qspi_platdata *plat = dev_get_platdata(bus); struct zynq_qspi_priv *priv = dev_get_priv(bus); + struct clk clk; + unsigned long clock; + int ret; priv->regs = plat->regs; priv->fifo_depth = ZYNQ_QSPI_FIFO_DEPTH; + ret = clk_get_by_name(bus, "ref_clk", &clk); + if (ret < 0) { + dev_err(bus, "failed to get clock\n"); + return ret; + } + + clock = clk_get_rate(&clk); + if (IS_ERR_VALUE(clock)) { + dev_err(bus, "failed to get rate\n"); + return clock; + } + + ret = clk_enable(&clk); + if (ret && ret != -ENOSYS) { + dev_err(bus, "failed to enable clock\n"); + return ret; + } + /* init the zynq spi hw */ zynq_qspi_init_hw(priv); + plat->frequency = clock; + plat->speed_hz = plat->frequency / 2; + + debug("%s: max-frequency=%d\n", __func__, plat->speed_hz); + return 0; } -/* +/** * zynq_qspi_read_data - Copy data to RX buffer - * @zqspi: Pointer to the zynq_qspi structure + * @priv: Pointer to the zynq_qspi_priv structure * @data: The 32 bit variable where data is stored * @size: Number of bytes to be copied from data to RX buffer */ @@ -214,9 +254,9 @@ static void zynq_qspi_read_data(struct zynq_qspi_priv *priv, u32 data, u8 size) priv->bytes_to_receive = 0; } -/* +/** * zynq_qspi_write_data - Copy data from TX buffer - * @zqspi: Pointer to the zynq_qspi structure + * @priv: Pointer to the zynq_qspi_priv structure * @data: Pointer to the 32 bit variable where data is to be copied * @size: Number of bytes to be copied from TX buffer to data */ @@ -263,6 +303,11 @@ static void zynq_qspi_write_data(struct zynq_qspi_priv *priv, priv->bytes_to_transfer = 0; } +/** + * zynq_qspi_chipselect - Select or deselect the chip select line + * @priv: Pointer to the zynq_qspi_priv structure + * @is_on: Select(1) or deselect (0) the chip select line + */ static void zynq_qspi_chipselect(struct zynq_qspi_priv *priv, int is_on) { u32 confr; @@ -282,9 +327,10 @@ static void zynq_qspi_chipselect(struct zynq_qspi_priv *priv, int is_on) writel(confr, ®s->cr); } -/* +/** * zynq_qspi_fill_tx_fifo - Fills the TX FIFO with as many bytes as possible - * @zqspi: Pointer to the zynq_qspi structure + * @priv: Pointer to the zynq_qspi_priv structure + * @size: Number of bytes to be copied to fifo */ static void zynq_qspi_fill_tx_fifo(struct zynq_qspi_priv *priv, u32 size) { @@ -322,9 +368,9 @@ static void zynq_qspi_fill_tx_fifo(struct zynq_qspi_priv *priv, u32 size) } } -/* +/** * zynq_qspi_irq_poll - Interrupt service routine of the QSPI controller - * @zqspi: Pointer to the zynq_qspi structure + * @priv: Pointer to the zynq_qspi structure * * This function handles TX empty and Mode Fault interrupts only. * On TX empty interrupt this function reads the received data from RX FIFO and @@ -410,11 +456,9 @@ static int zynq_qspi_irq_poll(struct zynq_qspi_priv *priv) return 0; } -/* +/** * zynq_qspi_start_transfer - Initiates the QSPI transfer - * @qspi: Pointer to the spi_device structure - * @transfer: Pointer to the spi_transfer structure which provide information - * about next transfer parameters + * @priv: Pointer to the zynq_qspi_priv structure * * This function fills the TX FIFO, starts the QSPI transfer, and waits for the * transfer to be completed. diff --git a/drivers/spi/zynq_spi.c b/drivers/spi/zynq_spi.c index 9923931..cb911c3 100644 --- a/drivers/spi/zynq_spi.c +++ b/drivers/spi/zynq_spi.c @@ -8,10 +8,12 @@ #include <common.h> #include <dm.h> +#include <dm/device_compat.h> #include <log.h> #include <malloc.h> #include <spi.h> #include <time.h> +#include <clk.h> #include <asm/io.h> #include <linux/bitops.h> #include <linux/delay.h> @@ -79,17 +81,10 @@ static int zynq_spi_ofdata_to_platdata(struct udevice *bus) plat->regs = dev_read_addr_ptr(bus); - /* FIXME: Use 250MHz as a suitable default */ - plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency", - 250000000); plat->deactivate_delay_us = fdtdec_get_int(blob, node, "spi-deactivate-delay", 0); plat->activate_delay_us = fdtdec_get_int(blob, node, "spi-activate-delay", 0); - plat->speed_hz = plat->frequency / 2; - - debug("%s: regs=%p max-frequency=%d\n", __func__, - plat->regs, plat->frequency); return 0; } @@ -128,13 +123,39 @@ static int zynq_spi_probe(struct udevice *bus) { struct zynq_spi_platdata *plat = dev_get_platdata(bus); struct zynq_spi_priv *priv = dev_get_priv(bus); + struct clk clk; + unsigned long clock; + int ret; priv->regs = plat->regs; priv->fifo_depth = ZYNQ_SPI_FIFO_DEPTH; + ret = clk_get_by_name(bus, "ref_clk", &clk); + if (ret < 0) { + dev_err(bus, "failed to get clock\n"); + return ret; + } + + clock = clk_get_rate(&clk); + if (IS_ERR_VALUE(clock)) { + dev_err(bus, "failed to get rate\n"); + return clock; + } + + ret = clk_enable(&clk); + if (ret && ret != -ENOSYS) { + dev_err(bus, "failed to enable clock\n"); + return ret; + } + /* init the zynq spi hw */ zynq_spi_init_hw(priv); + plat->frequency = clock; + plat->speed_hz = plat->frequency / 2; + + debug("%s: max-frequency=%d\n", __func__, plat->speed_hz); + return 0; } diff --git a/drivers/sysreset/sysreset_sandbox.c b/drivers/sysreset/sysreset_sandbox.c index 69c22a7..71cabd1 100644 --- a/drivers/sysreset/sysreset_sandbox.c +++ b/drivers/sysreset/sysreset_sandbox.c @@ -130,7 +130,9 @@ U_BOOT_DRIVER(warm_sysreset_sandbox) = { .ops = &sandbox_warm_sysreset_ops, }; +#if !CONFIG_IS_ENABLED(OF_PLATDATA) /* This is here in case we don't have a device tree */ U_BOOT_DEVICE(sysreset_sandbox_non_fdt) = { .name = "sysreset_sandbox", }; +#endif diff --git a/drivers/video/rockchip/Kconfig b/drivers/video/rockchip/Kconfig index 5215a71..0ade631 100644 --- a/drivers/video/rockchip/Kconfig +++ b/drivers/video/rockchip/Kconfig @@ -22,7 +22,7 @@ menuconfig VIDEO_ROCKCHIP config VIDEO_ROCKCHIP_MAX_XRES int "Maximum horizontal resolution (for memory allocation purposes)" depends on VIDEO_ROCKCHIP - default 3840 if ROCKCHIP_RK3399 && DISPLAY_ROCKCHIP_HDMI + default 3840 if DISPLAY_ROCKCHIP_HDMI default 1920 help The maximum horizontal resolution to support for the framebuffer. @@ -32,7 +32,7 @@ config VIDEO_ROCKCHIP_MAX_XRES config VIDEO_ROCKCHIP_MAX_YRES int "Maximum vertical resolution (for memory allocation purposes)" depends on VIDEO_ROCKCHIP - default 2160 if ROCKCHIP_RK3399 && DISPLAY_ROCKCHIP_HDMI + default 2160 if DISPLAY_ROCKCHIP_HDMI default 1080 help The maximum vertical resolution to support for the framebuffer. diff --git a/drivers/video/rockchip/rk_edp.c b/drivers/video/rockchip/rk_edp.c index 000bd48..a032eb6 100644 --- a/drivers/video/rockchip/rk_edp.c +++ b/drivers/video/rockchip/rk_edp.c @@ -559,6 +559,12 @@ static int rk_edp_link_train_ce(struct rk_edp_priv *edp) channel_eq = 0; for (tries = 0; tries < 5; tries++) { rk_edp_set_link_training(edp, edp->train_set); + ret = rk_edp_dpcd_write(regs, DPCD_TRAINING_LANE0_SET, + edp->train_set, + edp->link_train.lane_count); + if (ret) + return ret; + udelay(400); if (rk_edp_dpcd_read_link_status(edp, status) < 0) { diff --git a/dts/Kconfig b/dts/Kconfig index 86ea8ce..aeda542 100644 --- a/dts/Kconfig +++ b/dts/Kconfig @@ -355,6 +355,15 @@ config SPL_OF_PLATDATA compatible string, then adding platform data and U_BOOT_DEVICE declarations for each node. See of-plat.txt for more information. +config SPL_OF_PLATDATA_PARENT + bool "Support parent information in devices" + depends on SPL_OF_PLATDATA + default y + help + Generally it is useful to be able to access the parent of a device + with of-platdata. To save space this can be disabled, but in that + case dev_get_parent() will always return NULL; + config TPL_OF_PLATDATA bool "Generate platform data for use in TPL" depends on TPL_OF_CONTROL @@ -376,4 +385,13 @@ config TPL_OF_PLATDATA compatible string, then adding platform data and U_BOOT_DEVICE declarations for each node. See of-plat.txt for more information. +config TPL_OF_PLATDATA_PARENT + bool "Support parent information in devices" + depends on TPL_OF_PLATDATA + default y + help + Generally it is useful to be able to access the parent of a device + with of-platdata. To save space this can be disabled, but in that + case dev_get_parent() will always return NULL; + endmenu diff --git a/env/Kconfig b/env/Kconfig index aa63fae..67ce930 100644 --- a/env/Kconfig +++ b/env/Kconfig @@ -376,6 +376,14 @@ config ENV_SPI_MODE Value of the SPI work mode for environment. See include/spi.h for value. +config ENV_SPI_EARLY + bool "Access Environment in SPI flashes before relocation" + depends on ENV_IS_IN_SPI_FLASH + help + Enable this if you want to use Environment in SPI flash + before relocation. Call env_init() and than you can use + env_get_f() for accessing Environment variables. + config ENV_IS_IN_UBI bool "Environment in a UBI volume" depends on !CHAIN_OF_TRUST diff --git a/env/common.c b/env/common.c index ed18378..6c32a9b4 100644 --- a/env/common.c +++ b/env/common.c @@ -141,12 +141,11 @@ int env_import(const char *buf, int check, int flags) #ifdef CONFIG_SYS_REDUNDAND_ENVIRONMENT static unsigned char env_flags; -int env_import_redund(const char *buf1, int buf1_read_fail, - const char *buf2, int buf2_read_fail, - int flags) +int env_check_redund(const char *buf1, int buf1_read_fail, + const char *buf2, int buf2_read_fail) { int crc1_ok, crc2_ok; - env_t *ep, *tmp_env1, *tmp_env2; + env_t *tmp_env1, *tmp_env2; tmp_env1 = (env_t *)buf1; tmp_env2 = (env_t *)buf2; @@ -159,14 +158,13 @@ int env_import_redund(const char *buf1, int buf1_read_fail, } if (buf1_read_fail && buf2_read_fail) { - env_set_default("bad env area", 0); return -EIO; } else if (!buf1_read_fail && buf2_read_fail) { gd->env_valid = ENV_VALID; - return env_import((char *)tmp_env1, 1, flags); + return -EINVAL; } else if (buf1_read_fail && !buf2_read_fail) { gd->env_valid = ENV_REDUND; - return env_import((char *)tmp_env2, 1, flags); + return -ENOENT; } crc1_ok = crc32(0, tmp_env1->data, ENV_SIZE) == @@ -175,7 +173,6 @@ int env_import_redund(const char *buf1, int buf1_read_fail, tmp_env2->crc; if (!crc1_ok && !crc2_ok) { - env_set_default("bad CRC", 0); return -ENOMSG; /* needed for env_load() */ } else if (crc1_ok && !crc2_ok) { gd->env_valid = ENV_VALID; @@ -195,12 +192,37 @@ int env_import_redund(const char *buf1, int buf1_read_fail, gd->env_valid = ENV_VALID; } + return 0; +} + +int env_import_redund(const char *buf1, int buf1_read_fail, + const char *buf2, int buf2_read_fail, + int flags) +{ + env_t *ep; + int ret; + + ret = env_check_redund(buf1, buf1_read_fail, buf2, buf2_read_fail); + + if (ret == -EIO) { + env_set_default("bad env area", 0); + return -EIO; + } else if (ret == -EINVAL) { + return env_import((char *)buf1, 1, flags); + } else if (ret == -ENOENT) { + return env_import((char *)buf2, 1, flags); + } else if (ret == -ENOMSG) { + env_set_default("bad CRC", 0); + return -ENOMSG; + } + if (gd->env_valid == ENV_VALID) - ep = tmp_env1; + ep = (env_t *)buf1; else - ep = tmp_env2; + ep = (env_t *)buf2; env_flags = ep->flags; + return env_import((char *)ep, 0, flags); } #endif /* CONFIG_SYS_REDUNDAND_ENVIRONMENT */ @@ -287,7 +287,10 @@ __weak void *env_sf_get_env_addr(void) #endif #if defined(INITENV) && (CONFIG_ENV_ADDR != 0x0) -static int env_sf_init(void) +/* + * check if Environment on CONFIG_ENV_ADDR is valid. + */ +static int env_sf_init_addr(void) { env_t *env_ptr = (env_t *)env_sf_get_env_addr(); @@ -303,12 +306,103 @@ static int env_sf_init(void) } #endif +#if defined(CONFIG_ENV_SPI_EARLY) +/* + * early load environment from SPI flash (before relocation) + * and check if it is valid. + */ +static int env_sf_init_early(void) +{ + int ret; + int read1_fail; + int read2_fail; + int crc1_ok; + env_t *tmp_env2 = NULL; + env_t *tmp_env1; + + /* + * if malloc is not ready yet, we cannot use + * this part yet. + */ + if (!gd->malloc_limit) + return -ENOENT; + + tmp_env1 = (env_t *)memalign(ARCH_DMA_MINALIGN, + CONFIG_ENV_SIZE); + if (IS_ENABLED(CONFIG_SYS_REDUNDAND_ENVIRONMENT)) + tmp_env2 = (env_t *)memalign(ARCH_DMA_MINALIGN, + CONFIG_ENV_SIZE); + + if (!tmp_env1 || !tmp_env2) + goto out; + + ret = setup_flash_device(); + if (ret) + goto out; + + read1_fail = spi_flash_read(env_flash, CONFIG_ENV_OFFSET, + CONFIG_ENV_SIZE, tmp_env1); + + if (IS_ENABLED(CONFIG_SYS_REDUNDAND_ENVIRONMENT)) { + read2_fail = spi_flash_read(env_flash, + CONFIG_ENV_OFFSET_REDUND, + CONFIG_ENV_SIZE, tmp_env2); + ret = env_check_redund((char *)tmp_env1, read1_fail, + (char *)tmp_env2, read2_fail); + + if (ret == -EIO || ret == -ENOMSG) + goto err_read; + + if (gd->env_valid == ENV_VALID) + gd->env_addr = (unsigned long)&tmp_env1->data; + else + gd->env_addr = (unsigned long)&tmp_env2->data; + } else { + if (read1_fail) + goto err_read; + + crc1_ok = crc32(0, tmp_env1->data, ENV_SIZE) == + tmp_env1->crc; + if (!crc1_ok) + goto err_read; + + /* if valid -> this is our env */ + gd->env_valid = ENV_VALID; + gd->env_addr = (unsigned long)&tmp_env1->data; + } + + return 0; +err_read: + spi_flash_free(env_flash); + env_flash = NULL; + free(tmp_env1); + if (IS_ENABLED(CONFIG_SYS_REDUNDAND_ENVIRONMENT)) + free(tmp_env2); +out: + /* env is not valid. always return 0 */ + gd->env_valid = ENV_INVALID; + return 0; +} +#endif + +static int env_sf_init(void) +{ +#if defined(INITENV) && (CONFIG_ENV_ADDR != 0x0) + return env_sf_init_addr(); +#elif defined(CONFIG_ENV_SPI_EARLY) + return env_sf_init_early(); +#endif + /* + * we must return with 0 if there is nothing done, + * else env_set_inited() get not called in env_init() + */ + return 0; +} + U_BOOT_ENV_LOCATION(sf) = { .location = ENVL_SPI_FLASH, ENV_NAME("SPIFlash") .load = env_sf_load, .save = CONFIG_IS_ENABLED(SAVEENV) ? ENV_SAVE_PTR(env_sf_save) : NULL, -#if defined(INITENV) && (CONFIG_ENV_ADDR != 0x0) .init = env_sf_init, -#endif }; diff --git a/include/asm-generic/global_data.h b/include/asm-generic/global_data.h index 0157af1..f392043 100644 --- a/include/asm-generic/global_data.h +++ b/include/asm-generic/global_data.h @@ -24,6 +24,8 @@ #include <membuff.h> #include <linux/list.h> +struct driver_rt; + typedef struct global_data gd_t; /** @@ -192,6 +194,10 @@ struct global_data { * @uclass_root: head of core tree */ struct list_head uclass_root; +# if CONFIG_IS_ENABLED(OF_PLATDATA) + /** Dynamic info about the driver */ + struct driver_rt *dm_driver_rt; +# endif #endif #ifdef CONFIG_TIMER /** @@ -211,7 +217,7 @@ struct global_data { * @fdt_size: space reserved for relocated device space */ unsigned long fdt_size; -#ifdef CONFIG_OF_LIVE +#if CONFIG_IS_ENABLED(OF_LIVE) /** * @of_root: root node of the live tree */ @@ -378,7 +384,7 @@ struct global_data { */ int logc_prev; /** - * @logl_pref: logging level of the previous message + * @logl_prev: logging level of the previous message * * This value is used as logging level for continuation messages. */ @@ -427,6 +433,25 @@ struct global_data { #define gd_board_type() 0 #endif +/* These macros help avoid #ifdefs in the code */ +#if CONFIG_IS_ENABLED(OF_LIVE) +#define gd_of_root() gd->of_root +#define gd_of_root_ptr() &gd->of_root +#define gd_set_of_root(_root) gd->of_root = (_root) +#else +#define gd_of_root() NULL +#define gd_of_root_ptr() NULL +#define gd_set_of_root(_root) +#endif + +#if CONFIG_IS_ENABLED(OF_PLATDATA) +#define gd_set_dm_driver_rt(dyn) gd->dm_driver_rt = dyn +#define gd_dm_driver_rt() gd->dm_driver_rt +#else +#define gd_set_dm_driver_rt(dyn) +#define gd_dm_driver_rt() NULL +#endif + /** * enum gd_flags - global data flags * diff --git a/include/binman.h b/include/binman.h index e0b9207..8b89a96 100644 --- a/include/binman.h +++ b/include/binman.h @@ -43,6 +43,13 @@ int binman_entry_map(ofnode parent, const char *name, void **bufp, int *sizep); void binman_set_rom_offset(int rom_offset); /** + * binman_get_rom_offset() - Get the ROM memory-map offset + * + * @returns offset from an image_pos to the memory-mapped address + */ +int binman_get_rom_offset(void); + +/** * binman_entry_find() - Find a binman symbol * * This searches the binman information in the device tree for a symbol of the diff --git a/include/charset.h b/include/charset.h index 5564f3b..cc650a2 100644 --- a/include/charset.h +++ b/include/charset.h @@ -219,7 +219,7 @@ size_t u16_strlen(const void *in); size_t u16_strsize(const void *in); /** - * u16_strlen - count non-zero words + * u16_strnlen() - count non-zero words * * This function matches wscnlen_s() if the -fshort-wchar compiler flag is set. * In the EFI context we explicitly need a function handling u16 strings. diff --git a/include/config_uncmd_spl.h b/include/config_uncmd_spl.h index 31da621..af7e3e4 100644 --- a/include/config_uncmd_spl.h +++ b/include/config_uncmd_spl.h @@ -16,7 +16,6 @@ #undef CONFIG_DM_SPI #endif -#undef CONFIG_DM_WARN #undef CONFIG_DM_STDIO #endif /* CONFIG_SPL_BUILD */ diff --git a/include/configs/kontron_sl28.h b/include/configs/kontron_sl28.h new file mode 100644 index 0000000..afe512a --- /dev/null +++ b/include/configs/kontron_sl28.h @@ -0,0 +1,108 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef __SL28_H +#define __SL28_H + +#include <asm/arch/stream_id_lsch3.h> +#include <asm/arch/config.h> +#include <asm/arch/soc.h> + +/* we don't use hwconfig but this has to be defined.. */ +#define HWCONFIG_BUFFER_SIZE 256 + +/* we don't have secure memory unless we have a BL31 */ +#ifndef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT +#undef CONFIG_SYS_MEM_RESERVE_SECURE +#endif + +/* DDR */ +#define CONFIG_DDR_ECC +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER +#define CONFIG_MEM_INIT_VALUE 0xdeadbeef + +#define CONFIG_VERY_BIG_RAM +#define CONFIG_CHIP_SELECTS_PER_CTRL 4 +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 +#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CONFIG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL +#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 1 + +/* early stack pointer */ +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xeff0) + +/* memtest command */ +#define CONFIG_SYS_MEMTEST_START 0x80000000 +#define CONFIG_SYS_MEMTEST_END 0x9fffffff + +/* SMP */ +#define CPU_RELEASE_ADDR secondary_boot_addr + +/* generic timer */ +#define COUNTER_FREQUENCY 25000000 + +/* size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024) + +/* early heap for SPL DM */ +#define CONFIG_MALLOC_F_ADDR CONFIG_SYS_FSL_OCRAM_BASE + +/* serial port */ +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2) +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +#define CONFIG_SYS_CLK_FREQ 100000000 +#define CONFIG_DDR_CLK_FREQ 100000000 +#define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ / 4) + +/* MMC */ +#ifdef CONFIG_MMC +#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 +#endif + +/* ethernet */ +#define CONFIG_SYS_RX_ETH_BUFFER 8 + +/* SPL */ +#define CONFIG_SPL_BSS_START_ADDR 0x80100000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x00100000 +#define CONFIG_SPL_MAX_SIZE 0x20000 +#define CONFIG_SPL_STACK (CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0) + +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000 +#define CONFIG_SYS_SPL_MALLOC_START 0x80200000 +#define CONFIG_SYS_MONITOR_LEN (1024 * 1024) + +/* environment */ +/* see include/configs/ti_armv7_common.h */ +#define CONFIG_SYS_LOAD_ADDR 0x82000000 +#define ENV_MEM_LAYOUT_SETTINGS \ + "loadaddr=0x82000000\0" \ + "kernel_addr_r=0x82000000\0" \ + "fdt_addr_r=0x88000000\0" \ + "bootm_size=0x10000000\0" \ + "pxefile_addr_r=0x80100000\0" \ + "scriptaddr=0x80000000\0" \ + "ramdisk_addr_r=0x88080000\0" + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 1) \ + func(MMC, mmc, 0) \ + func(NVME, nvme, 0) \ + func(USB, usb, 0) \ + func(DHCP, dhcp, 0) \ + func(PXE, pxe, 0) +#include <config_distro_bootcmd.h> + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "env_addr=0x203e0004\0" \ + "envload=env import -d -b ${env_addr}\0" \ + "install_rcw=source 20200000\0" \ + "fdtfile=freescale/fsl-ls1028a-kontron-sl28.dtb\0" \ + ENV_MEM_LAYOUT_SETTINGS \ + BOOTENV + +#endif /* __SL28_H */ diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h index 8ca0e83..2b41242 100644 --- a/include/configs/microblaze-generic.h +++ b/include/configs/microblaze-generic.h @@ -125,21 +125,67 @@ #define CONFIG_SYS_LOAD_ADDR 0 #define CONFIG_HOSTNAME "microblaze-generic" -#define CONFIG_BOOTCOMMAND "base 0;tftp 11000000 image.img;bootm" /* architecture dependent code */ #define CONFIG_SYS_USR_EXCEP /* user exception */ +#if defined(CONFIG_CMD_PXE) && defined(CONFIG_CMD_DHCP) +#define BOOT_TARGET_DEVICES_PXE(func) func(PXE, pxe, na) +#else +#define BOOT_TARGET_DEVICES_PXE(func) +#endif + +#if defined(CONFIG_CMD_DHCP) +#define BOOT_TARGET_DEVICES_DHCP(func) func(DHCP, dhcp, na) +#else +#define BOOT_TARGET_DEVICES_DHCP(func) +#endif + +#if defined(CONFIG_SPI_FLASH) +# define BOOT_TARGET_DEVICES_QSPI(func) func(QSPI, qspi, na) +#else +# define BOOT_TARGET_DEVICES_QSPI(func) +#endif + +#define BOOTENV_DEV_QSPI(devtypeu, devtypel, instance) \ + "bootcmd_qspi=sf probe 0 0 0 && " \ + "sf read ${scriptaddr} ${script_offset_f} ${script_size_f} && " \ + "echo QSPI: Trying to boot script at ${scriptaddr} && " \ + "source ${scriptaddr}; echo QSPI: SCRIPT FAILED: continuing...;\0" + +#define BOOTENV_DEV_NAME_QSPI(devtypeu, devtypel, instance) \ + "qspi " + +#define BOOT_TARGET_DEVICES_JTAG(func) func(JTAG, jtag, na) + +#define BOOTENV_DEV_JTAG(devtypeu, devtypel, instance) \ + "bootcmd_jtag=echo JTAG: Trying to boot script at ${scriptaddr} && " \ + "source ${scriptaddr}; echo JTAG: SCRIPT FAILED: continuing...;\0" + +#define BOOTENV_DEV_NAME_JTAG(devtypeu, devtypel, instance) \ + "jtag " + +#define BOOT_TARGET_DEVICES(func) \ + BOOT_TARGET_DEVICES_JTAG(func) \ + BOOT_TARGET_DEVICES_QSPI(func) \ + BOOT_TARGET_DEVICES_DHCP(func) \ + BOOT_TARGET_DEVICES_PXE(func) + +#include <config_distro_bootcmd.h> + #ifndef CONFIG_EXTRA_ENV_SETTINGS -#define CONFIG_EXTRA_ENV_SETTINGS "unlock=yes\0" \ - "nor0=flash-0\0"\ - "mtdparts=mtdparts=flash-0:"\ - "256k(u-boot),256k(env),3m(kernel),"\ - "1m(romfs),1m(cramfs),-(jffs2)\0"\ - "nc=setenv stdout nc;"\ - "setenv stdin nc\0" \ - "serial=setenv stdout serial;"\ - "setenv stdin serial\0" +#define CONFIG_EXTRA_ENV_SETTINGS \ + "unlock=yes\0"\ + "nor0=flash-0\0"\ + "mtdparts=mtdparts=flash-0:"\ + "256k(u-boot),256k(env),3m(kernel),"\ + "1m(romfs),1m(cramfs),-(jffs2)\0"\ + "nc=setenv stdout nc;"\ + "setenv stdin nc\0" \ + "serial=setenv stdout serial;"\ + "setenv stdin serial\0"\ + "script_size_f=0x40000\0"\ + BOOTENV #endif #if defined(CONFIG_XILINX_AXIEMAC) @@ -167,8 +213,7 @@ #define CONFIG_SYS_INIT_RAM_SIZE 0x100000 # define CONFIG_SPL_STACK_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - \ - CONFIG_SYS_MALLOC_F_LEN) + CONFIG_SYS_INIT_RAM_SIZE) /* Just for sure that there is a space for stack */ #define CONFIG_SPL_STACK_SIZE 0x100 diff --git a/include/configs/px30_core.h b/include/configs/px30_core.h new file mode 100644 index 0000000..01b4995 --- /dev/null +++ b/include/configs/px30_core.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2020 Amarula Solutions(India) + */ + +#ifndef __PX30_CORE_H +#define __PX30_CORE_H + +#include <configs/px30_common.h> + +#define ROCKCHIP_DEVICE_SETTINGS \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" + +#endif /* __PX30_CORE_H */ diff --git a/include/configs/rock960_rk3399.h b/include/configs/rock960_rk3399.h index c6f9122..2edad71 100644 --- a/include/configs/rock960_rk3399.h +++ b/include/configs/rock960_rk3399.h @@ -15,4 +15,6 @@ #define SDRAM_BANK_SIZE (2UL << 30) +#define CONFIG_USB_OHCI_NEW +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 #endif diff --git a/include/configs/xilinx_versal.h b/include/configs/xilinx_versal.h index 8b41632..f1d2594 100644 --- a/include/configs/xilinx_versal.h +++ b/include/configs/xilinx_versal.h @@ -18,7 +18,6 @@ #define GICD_BASE 0xF9000000 #define GICR_BASE 0xF9080000 - #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE /* Generic Timer Definitions - setup in EL3. Setup by ATF for other cases */ diff --git a/include/configs/xilinx_versal_mini.h b/include/configs/xilinx_versal_mini.h index 0b201a2..00c9718 100644 --- a/include/configs/xilinx_versal_mini.h +++ b/include/configs/xilinx_versal_mini.h @@ -10,7 +10,6 @@ #ifndef __CONFIG_VERSAL_MINI_H #define __CONFIG_VERSAL_MINI_H - #define CONFIG_EXTRA_ENV_SETTINGS #include <configs/xilinx_versal.h> diff --git a/include/configs/xilinx_zynqmp_mini.h b/include/configs/xilinx_zynqmp_mini.h index 3f57423b..ef9c768 100644 --- a/include/configs/xilinx_zynqmp_mini.h +++ b/include/configs/xilinx_zynqmp_mini.h @@ -10,7 +10,6 @@ #ifndef __CONFIG_ZYNQMP_MINI_H #define __CONFIG_ZYNQMP_MINI_H - #define CONFIG_EXTRA_ENV_SETTINGS #include <configs/xilinx_zynqmp.h> diff --git a/include/dfu.h b/include/dfu.h index 84abdc7..a767ade 100644 --- a/include/dfu.h +++ b/include/dfu.h @@ -158,6 +158,9 @@ struct dfu_entity { unsigned int inited:1; }; +struct list_head; +extern struct list_head dfu_list; + #ifdef CONFIG_SET_DFU_ALT_INFO /** * set_dfu_alt_info() - set dfu_alt_info environment variable @@ -493,28 +496,52 @@ static inline int dfu_fill_entity_virt(struct dfu_entity *dfu, char *devstr, } #endif +#if CONFIG_IS_ENABLED(DFU_WRITE_ALT) /** - * dfu_tftp_write() - write TFTP data to DFU medium + * dfu_write_by_name() - write data to DFU medium + * @dfu_entity_name: Name of DFU entity to write + * @addr: Address of data buffer to write + * @len: Number of bytes + * @interface: Destination DFU medium (e.g. "mmc") + * @devstring: Instance number of destination DFU medium (e.g. "1") + * + * This function is storing data received on DFU supported medium which + * is specified by @dfu_entity_name. * - * This function is storing data received via TFTP on DFU supported medium. + * Return: 0 - on success, error code - otherwise + */ +int dfu_write_by_name(char *dfu_entity_name, void *addr, + unsigned int len, char *interface, char *devstring); + +/** + * dfu_write_by_alt() - write data to DFU medium + * @dfu_alt_num: DFU alt setting number + * @addr: Address of data buffer to write + * @len: Number of bytes + * @interface: Destination DFU medium (e.g. "mmc") + * @devstring: Instance number of destination DFU medium (e.g. "1") * - * @dfu_entity_name: name of DFU entity to write - * @addr: address of data buffer to write - * @len: number of bytes - * @interface: destination DFU medium (e.g. "mmc") - * @devstring: instance number of destination DFU medium (e.g. "1") + * This function is storing data received on DFU supported medium which + * is specified by @dfu_alt_name. * - * Return: 0 on success, otherwise error code + * Return: 0 - on success, error code - otherwise */ -#if CONFIG_IS_ENABLED(DFU_TFTP) -int dfu_tftp_write(char *dfu_entity_name, unsigned int addr, unsigned int len, - char *interface, char *devstring); +int dfu_write_by_alt(int dfu_alt_num, void *addr, unsigned int len, + char *interface, char *devstring); #else -static inline int dfu_tftp_write(char *dfu_entity_name, unsigned int addr, - unsigned int len, char *interface, - char *devstring) +static inline int dfu_write_by_name(char *dfu_entity_name, void *addr, + unsigned int len, char *interface, + char *devstring) +{ + puts("write support for DFU not available!\n"); + return -ENOSYS; +} + +static inline int dfu_write_by_alt(int dfu_alt_num, void *addr, + unsigned int len, char *interface, + char *devstring) { - puts("TFTP write support for DFU not available!\n"); + puts("write support for DFU not available!\n"); return -ENOSYS; } #endif diff --git a/include/dm/device-internal.h b/include/dm/device-internal.h index 1dcc22f..c5d7ec0 100644 --- a/include/dm/device-internal.h +++ b/include/dm/device-internal.h @@ -81,7 +81,7 @@ int device_bind_with_driver_data(struct udevice *parent, * @return 0 if OK, -ve on error */ int device_bind_by_name(struct udevice *parent, bool pre_reloc_only, - struct driver_info *info, struct udevice **devp); + const struct driver_info *info, struct udevice **devp); /** * device_reparent: reparent the device to a new parent diff --git a/include/dm/device.h b/include/dm/device.h index ac3b6c1..5bef484 100644 --- a/include/dm/device.h +++ b/include/dm/device.h @@ -554,6 +554,20 @@ int device_get_by_driver_info(const struct driver_info *info, struct udevice **devp); /** + * device_get_by_driver_info_idx() - Get a device based on driver_info index + * + * Locates a device by its struct driver_info, by using its index number which + * is written into the idx field of struct phandle_1_arg, etc. + * + * The device is probed to activate it ready for use. + * + * @idx: Index number of the driver_info structure (0=first) + * @devp: Returns pointer to device if found, otherwise this is set to NULL + * @return 0 if OK, -ve on error + */ +int device_get_by_driver_info_idx(uint idx, struct udevice **devp); + +/** * device_find_first_child() - Find the first child of a device * * @parent: Parent device to search @@ -823,7 +837,7 @@ static inline bool device_is_on_pci_bus(const struct udevice *dev) _ret = device_next_child_err(&dev)) /** - * dm_scan_fdt_dev() - Bind child device in a the device tree + * dm_scan_fdt_dev() - Bind child device in the device tree * * This handles device which have sub-nodes in the device tree. It scans all * sub-nodes and binds drivers for each node where a driver can be found. diff --git a/include/dm/of.h b/include/dm/of.h index 6bef73b..5cb6f44 100644 --- a/include/dm/of.h +++ b/include/dm/of.h @@ -90,17 +90,10 @@ DECLARE_GLOBAL_DATA_PTR; * * @returns true if livetree is active, false it not */ -#ifdef CONFIG_OF_LIVE static inline bool of_live_active(void) { - return gd->of_root != NULL; + return gd_of_root() != NULL; } -#else -static inline bool of_live_active(void) -{ - return false; -} -#endif #define OF_BAD_ADDR ((u64)-1) diff --git a/include/dm/ofnode.h b/include/dm/ofnode.h index 4b7af37..ced7f6f 100644 --- a/include/dm/ofnode.h +++ b/include/dm/ofnode.h @@ -605,6 +605,28 @@ const char *ofnode_read_chosen_string(const char *propname); */ ofnode ofnode_get_chosen_node(const char *propname); +/** + * ofnode_read_aliases_prop() - get the value of a aliases property + * + * This looks for a property within the /aliases node and returns its value + * + * @propname: Property name to look for + * @sizep: Returns size of property, or FDT_ERR_... error code if function + * returns NULL + * @return property value if found, else NULL + */ +const void *ofnode_read_aliases_prop(const char *propname, int *sizep); + +/** + * ofnode_get_aliases_node() - get a referenced node from the aliases node + * + * This looks up a named property in the aliases node and uses that as a path to + * look up a code. + * + * @return the referenced node if present, else ofnode_null() + */ +ofnode ofnode_get_aliases_node(const char *propname); + struct display_timing; /** * ofnode_decode_display_timing() - decode display timings diff --git a/include/dm/platdata.h b/include/dm/platdata.h index cab93b0..216efa8 100644 --- a/include/dm/platdata.h +++ b/include/dm/platdata.h @@ -22,30 +22,71 @@ * @name: Driver name * @platdata: Driver-specific platform data * @platdata_size: Size of platform data structure - * @dev: Device created from this structure data + * @parent_idx: Index of the parent driver_info structure */ struct driver_info { const char *name; const void *platdata; #if CONFIG_IS_ENABLED(OF_PLATDATA) - uint platdata_size; - struct udevice *dev; + unsigned short platdata_size; + short parent_idx; #endif }; +#if CONFIG_IS_ENABLED(OF_PLATDATA) +#define driver_info_parent_id(driver_info) driver_info->parent_idx +#else +#define driver_info_parent_id(driver_info) (-1) +#endif + +/** + * driver_rt - runtime information set up by U-Boot + * + * There is one of these for every driver_info in the linker list, indexed by + * the driver_info idx value. + * + * @dev: Device created from this idx + */ +struct driver_rt { + struct udevice *dev; +}; + /** * NOTE: Avoid using these except in extreme circumstances, where device tree * is not feasible (e.g. serial driver in SPL where <8KB of SRAM is * available). U-Boot's driver model uses device tree for configuration. + * + * When of-platdata is in use, U_BOOT_DEVICE() cannot be used outside of the + * dt-platdata.c file created by dtoc */ +#if CONFIG_IS_ENABLED(OF_PLATDATA) && !defined(DT_PLATDATA_C) +#define U_BOOT_DEVICE(__name) _Static_assert(false, \ + "Cannot use U_BOOT_DEVICE with of-platdata. Please use devicetree instead") +#else #define U_BOOT_DEVICE(__name) \ ll_entry_declare(struct driver_info, __name, driver_info) +#endif /* Declare a list of devices. The argument is a driver_info[] array */ #define U_BOOT_DEVICES(__name) \ ll_entry_declare_list(struct driver_info, __name, driver_info) -/* Get a pointer to a given driver */ +/** + * Get a pointer to a given device info given its name + * + * With the declaration U_BOOT_DEVICE(name), DM_GET_DEVICE(name) will return a + * pointer to the struct driver_info created by that declaration. + * + * if OF_PLATDATA is enabled, from this it is possible to use the @dev member of + * struct driver_info to find the device pointer itself. + * + * TODO(sjg@chromium.org): U_BOOT_DEVICE() tells U-Boot to create a device, so + * the naming seems sensible, but DM_GET_DEVICE() is a bit of misnomer, since it + * finds the driver_info record, not the device. + * + * @__name: Driver name (C identifier, not a string. E.g. gpio7_at_ff7e0000) + * @return struct driver_info * to the driver that created the device + */ #define DM_GET_DEVICE(__name) \ ll_entry_get(struct driver_info, __name, driver_info) diff --git a/include/dm/util.h b/include/dm/util.h index 9773db6..01a0449 100644 --- a/include/dm/util.h +++ b/include/dm/util.h @@ -6,7 +6,7 @@ #ifndef __DM_UTIL_H #define __DM_UTIL_H -#ifdef CONFIG_DM_WARN +#if CONFIG_IS_ENABLED(DM_WARN) void dm_warn(const char *fmt, ...); #else static inline void dm_warn(const char *fmt, ...) diff --git a/include/dt-bindings/clock/xlnx-versal-clk.h b/include/dt-bindings/clock/xlnx-versal-clk.h new file mode 100644 index 0000000..264d634 --- /dev/null +++ b/include/dt-bindings/clock/xlnx-versal-clk.h @@ -0,0 +1,123 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2019 Xilinx Inc. + * + */ + +#ifndef _DT_BINDINGS_CLK_VERSAL_H +#define _DT_BINDINGS_CLK_VERSAL_H + +#define PMC_PLL 1 +#define APU_PLL 2 +#define RPU_PLL 3 +#define CPM_PLL 4 +#define NOC_PLL 5 +#define PLL_MAX 6 +#define PMC_PRESRC 7 +#define PMC_POSTCLK 8 +#define PMC_PLL_OUT 9 +#define PPLL 10 +#define NOC_PRESRC 11 +#define NOC_POSTCLK 12 +#define NOC_PLL_OUT 13 +#define NPLL 14 +#define APU_PRESRC 15 +#define APU_POSTCLK 16 +#define APU_PLL_OUT 17 +#define APLL 18 +#define RPU_PRESRC 19 +#define RPU_POSTCLK 20 +#define RPU_PLL_OUT 21 +#define RPLL 22 +#define CPM_PRESRC 23 +#define CPM_POSTCLK 24 +#define CPM_PLL_OUT 25 +#define CPLL 26 +#define PPLL_TO_XPD 27 +#define NPLL_TO_XPD 28 +#define APLL_TO_XPD 29 +#define RPLL_TO_XPD 30 +#define EFUSE_REF 31 +#define SYSMON_REF 32 +#define IRO_SUSPEND_REF 33 +#define USB_SUSPEND 34 +#define SWITCH_TIMEOUT 35 +#define RCLK_PMC 36 +#define RCLK_LPD 37 +#define WDT 38 +#define TTC0 39 +#define TTC1 40 +#define TTC2 41 +#define TTC3 42 +#define GEM_TSU 43 +#define GEM_TSU_LB 44 +#define MUXED_IRO_DIV2 45 +#define MUXED_IRO_DIV4 46 +#define PSM_REF 47 +#define GEM0_RX 48 +#define GEM0_TX 49 +#define GEM1_RX 50 +#define GEM1_TX 51 +#define CPM_CORE_REF 52 +#define CPM_LSBUS_REF 53 +#define CPM_DBG_REF 54 +#define CPM_AUX0_REF 55 +#define CPM_AUX1_REF 56 +#define QSPI_REF 57 +#define OSPI_REF 58 +#define SDIO0_REF 59 +#define SDIO1_REF 60 +#define PMC_LSBUS_REF 61 +#define I2C_REF 62 +#define TEST_PATTERN_REF 63 +#define DFT_OSC_REF 64 +#define PMC_PL0_REF 65 +#define PMC_PL1_REF 66 +#define PMC_PL2_REF 67 +#define PMC_PL3_REF 68 +#define CFU_REF 69 +#define SPARE_REF 70 +#define NPI_REF 71 +#define HSM0_REF 72 +#define HSM1_REF 73 +#define SD_DLL_REF 74 +#define FPD_TOP_SWITCH 75 +#define FPD_LSBUS 76 +#define ACPU 77 +#define DBG_TRACE 78 +#define DBG_FPD 79 +#define LPD_TOP_SWITCH 80 +#define ADMA 81 +#define LPD_LSBUS 82 +#define CPU_R5 83 +#define CPU_R5_CORE 84 +#define CPU_R5_OCM 85 +#define CPU_R5_OCM2 86 +#define IOU_SWITCH 87 +#define GEM0_REF 88 +#define GEM1_REF 89 +#define GEM_TSU_REF 90 +#define USB0_BUS_REF 91 +#define UART0_REF 92 +#define UART1_REF 93 +#define SPI0_REF 94 +#define SPI1_REF 95 +#define CAN0_REF 96 +#define CAN1_REF 97 +#define I2C0_REF 98 +#define I2C1_REF 99 +#define DBG_LPD 100 +#define TIMESTAMP_REF 101 +#define DBG_TSTMP 102 +#define CPM_TOPSW_REF 103 +#define USB3_DUAL_REF 104 +#define OUTCLK_MAX 105 +#define REF_CLK 106 +#define PL_ALT_REF_CLK 107 +#define MUXED_IRO 108 +#define PL_EXT 109 +#define PL_LB 110 +#define MIO_50_OR_51 111 +#define MIO_24_OR_25 112 + +#endif diff --git a/include/dt-bindings/power/xlnx-versal-power.h b/include/dt-bindings/power/xlnx-versal-power.h new file mode 100644 index 0000000..1b75175 --- /dev/null +++ b/include/dt-bindings/power/xlnx-versal-power.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2019 - 2020 Xilinx, Inc. + */ + +#ifndef _DT_BINDINGS_VERSAL_POWER_H +#define _DT_BINDINGS_VERSAL_POWER_H + +#define PM_DEV_USB_0 (0x18224018U) +#define PM_DEV_GEM_0 (0x18224019U) +#define PM_DEV_GEM_1 (0x1822401aU) +#define PM_DEV_SPI_0 (0x1822401bU) +#define PM_DEV_SPI_1 (0x1822401cU) +#define PM_DEV_I2C_0 (0x1822401dU) +#define PM_DEV_I2C_1 (0x1822401eU) +#define PM_DEV_CAN_FD_0 (0x1822401fU) +#define PM_DEV_CAN_FD_1 (0x18224020U) +#define PM_DEV_UART_0 (0x18224021U) +#define PM_DEV_UART_1 (0x18224022U) +#define PM_DEV_GPIO (0x18224023U) +#define PM_DEV_TTC_0 (0x18224024U) +#define PM_DEV_TTC_1 (0x18224025U) +#define PM_DEV_TTC_2 (0x18224026U) +#define PM_DEV_TTC_3 (0x18224027U) +#define PM_DEV_SWDT_FPD (0x18224029U) +#define PM_DEV_OSPI (0x1822402aU) +#define PM_DEV_QSPI (0x1822402bU) +#define PM_DEV_GPIO_PMC (0x1822402cU) +#define PM_DEV_SDIO_0 (0x1822402eU) +#define PM_DEV_SDIO_1 (0x1822402fU) +#define PM_DEV_RTC (0x18224034U) +#define PM_DEV_ADMA_0 (0x18224035U) +#define PM_DEV_ADMA_1 (0x18224036U) +#define PM_DEV_ADMA_2 (0x18224037U) +#define PM_DEV_ADMA_3 (0x18224038U) +#define PM_DEV_ADMA_4 (0x18224039U) +#define PM_DEV_ADMA_5 (0x1822403aU) +#define PM_DEV_ADMA_6 (0x1822403bU) +#define PM_DEV_ADMA_7 (0x1822403cU) +#define PM_DEV_AI (0x18224072U) + +#endif diff --git a/include/dt-structs.h b/include/dt-structs.h index 924d51f..f0e1c9c 100644 --- a/include/dt-structs.h +++ b/include/dt-structs.h @@ -8,18 +8,20 @@ /* These structures may only be used in SPL */ #if CONFIG_IS_ENABLED(OF_PLATDATA) +struct driver_info; + struct phandle_0_arg { - const void *node; + uint idx; int arg[0]; }; struct phandle_1_arg { - const void *node; + uint idx; int arg[1]; }; struct phandle_2_arg { - const void *node; + uint idx; int arg[2]; }; #include <generated/dt-structs-gen.h> diff --git a/include/efi_loader.h b/include/efi_loader.h index 7eea556..f550ced 100644 --- a/include/efi_loader.h +++ b/include/efi_loader.h @@ -804,6 +804,9 @@ bool efi_image_parse(void *efi, size_t len, struct efi_image_regions **regp, /* runtime implementation of memcpy() */ void efi_memcpy_runtime(void *dest, const void *src, size_t n); +/* commonly used helper function */ +u16 *efi_create_indexed_name(u16 *buffer, const char *name, unsigned int index); + #else /* CONFIG_IS_ENABLED(EFI_LOADER) */ /* Without CONFIG_EFI_LOADER we don't have a runtime section, stub it out */ diff --git a/include/env.h b/include/env.h index af40595..c15339a 100644 --- a/include/env.h +++ b/include/env.h @@ -319,6 +319,24 @@ int env_import(const char *buf, int check, int flags); int env_export(struct environment_s *env_out); /** + * env_check_redund() - check the two redundant environments + * and find out, which is the valid one. + * + * @buf1: First environment (struct environemnt_s *) + * @buf1_read_fail: 0 if buf1 is valid, non-zero if invalid + * @buf2: Second environment (struct environemnt_s *) + * @buf2_read_fail: 0 if buf2 is valid, non-zero if invalid + * @return 0 if OK, + * -EIO if no environment is valid, + * -EINVAL if read of second entry is good + * -ENOENT if read of first entry is good + * -ENOMSG if the CRC was bad + */ + +int env_check_redund(const char *buf1, int buf1_read_fail, + const char *buf2, int buf2_read_fail); + +/** * env_import_redund() - Select and import one of two redundant environments * * @buf1: First environment (struct environemnt_s *) diff --git a/include/getopt.h b/include/getopt.h new file mode 100644 index 0000000..6f5811e --- /dev/null +++ b/include/getopt.h @@ -0,0 +1,130 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * getopt.h - a simple getopt(3) implementation. + * + * Copyright (C) 2020 Sean Anderson <seanga2@gmail.com> + * Copyright (c) 2007 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix + */ + +#ifndef __GETOPT_H +#define __GETOPT_H + +/** + * struct getopt_state - Saved state across getopt() calls + */ +struct getopt_state { + /** + * @index: Index of the next unparsed argument of @argv. If getopt() has + * parsed all of @argv, then @index will equal @argc. + */ + int index; + /* private: */ + /** @arg_index: Index within the current argument */ + int arg_index; + union { + /* public: */ + /** + * @opt: Option being parsed when an error occurs. @opt is only + * valid when getopt() returns ``?`` or ``:``. + */ + int opt; + /** + * @arg: The argument to an option, NULL if there is none. @arg + * is only valid when getopt() returns an option character. + */ + char *arg; + /* private: */ + }; +}; + +/** + * getopt_init_state() - Initialize a &struct getopt_state + * @gs: The state to initialize + * + * This must be called before using @gs with getopt(). + */ +void getopt_init_state(struct getopt_state *gs); + +int __getopt(struct getopt_state *gs, int argc, char *const argv[], + const char *optstring, bool silent); + +/** + * getopt() - Parse short command-line options + * @gs: Internal state and out-of-band return arguments. This must be + * initialized with getopt_init_context() beforehand. + * @argc: Number of arguments, not including the %NULL terminator + * @argv: Argument list, terminated by %NULL + * @optstring: Option specification, as described below + * + * getopt() parses short options. Short options are single characters. They may + * be followed by a required argument or an optional argument. Arguments to + * options may occur in the same argument as an option (like ``-larg``), or + * in the following argument (like ``-l arg``). An argument containing + * options begins with a ``-``. If an option expects no arguments, then it may + * be immediately followed by another option (like ``ls -alR``). + * + * @optstring is a list of accepted options. If an option is followed by ``:`` + * in @optstring, then it expects a mandatory argument. If an option is followed + * by ``::`` in @optstring, it expects an optional argument. @gs.arg points + * to the argument, if one is parsed. + * + * getopt() stops parsing options when it encounters the first non-option + * argument, when it encounters the argument ``--``, or when it runs out of + * arguments. For example, in ``ls -l foo -R``, option parsing will stop when + * getopt() encounters ``foo``, if ``l`` does not expect an argument. However, + * the whole list of arguments would be parsed if ``l`` expects an argument. + * + * An example invocation of getopt() might look like:: + * + * char *argv[] = { "program", "-cbx", "-a", "foo", "bar", 0 }; + * int opt, argc = ARRAY_SIZE(argv) - 1; + * struct getopt_state gs; + * + * getopt_init_state(&gs); + * while ((opt = getopt(&gs, argc, argv, "a::b:c")) != -1) + * printf("opt = %c, index = %d, arg = \"%s\"\n", opt, gs.index, gs.arg); + * printf("%d argument(s) left\n", argc - gs.index); + * + * and would produce an output of:: + * + * opt = c, index = 1, arg = "<NULL>" + * opt = b, index = 2, arg = "x" + * opt = a, index = 4, arg = "foo" + * 1 argument(s) left + * + * For further information, refer to the getopt(3) man page. + * + * Return: + * * An option character if an option is found. @gs.arg is set to the + * argument if there is one, otherwise it is set to ``NULL``. + * * ``-1`` if there are no more options, if a non-option argument is + * encountered, or if an ``--`` argument is encountered. + * * ``'?'`` if we encounter an option not in @optstring. @gs.opt is set to + * the unknown option. + * * ``':'`` if an argument is required, but no argument follows the + * option. @gs.opt is set to the option missing its argument. + * + * @gs.index is always set to the index of the next unparsed argument in @argv. + */ +static inline int getopt(struct getopt_state *gs, int argc, + char *const argv[], const char *optstring) +{ + return __getopt(gs, argc, argv, optstring, false); +} + +/** + * getopt_silent() - Parse short command-line options silently + * @gs: State + * @argc: Argument count + * @argv: Argument list + * @optstring: Option specification + * + * Same as getopt(), except no error messages are printed. + */ +static inline int getopt_silent(struct getopt_state *gs, int argc, + char *const argv[], const char *optstring) +{ + return __getopt(gs, argc, argv, optstring, true); +} + +#endif /* __GETOPT_H */ diff --git a/include/image.h b/include/image.h index 4094ee5..00bc03b 100644 --- a/include/image.h +++ b/include/image.h @@ -1602,4 +1602,16 @@ struct fit_loadable_tbl { .handler = _handler, \ } +/** + * fit_update - update storage with FIT image + * @fit: Pointer to FIT image + * + * Update firmware on storage using FIT image as input. + * The storage area to be update will be identified by the name + * in FIT and matching it to "dfu_alt_info" variable. + * + * Return: 0 on success, non-zero otherwise + */ +int fit_update(const void *fit); + #endif /* __IMAGE_H__ */ diff --git a/include/log.h b/include/log.h index 58787a3..4d0692f 100644 --- a/include/log.h +++ b/include/log.h @@ -17,56 +17,92 @@ struct cmd_tbl; -/** Log levels supported, ranging from most to least important */ +/** + * enum log_level_t - Log levels supported, ranging from most to least important + */ enum log_level_t { - LOGL_EMERG = 0, /* U-Boot is unstable */ - LOGL_ALERT, /* Action must be taken immediately */ - LOGL_CRIT, /* Critical conditions */ - LOGL_ERR, /* Error that prevents something from working */ - LOGL_WARNING, /* Warning may prevent optimial operation */ - LOGL_NOTICE, /* Normal but significant condition, printf() */ - LOGL_INFO, /* General information message */ - LOGL_DEBUG, /* Basic debug-level message */ - LOGL_DEBUG_CONTENT, /* Debug message showing full message content */ - LOGL_DEBUG_IO, /* Debug message showing hardware I/O access */ - + /** @LOGL_EMERG: U-Boot is unstable */ + LOGL_EMERG = 0, + /** @LOGL_ALERT: Action must be taken immediately */ + LOGL_ALERT, + /** @LOGL_CRIT: Critical conditions */ + LOGL_CRIT, + /** @LOGL_ERR: Error that prevents something from working */ + LOGL_ERR, + /** @LOGL_WARNING: Warning may prevent optimial operation */ + LOGL_WARNING, + /** @LOGL_NOTICE: Normal but significant condition, printf() */ + LOGL_NOTICE, + /** @LOGL_INFO: General information message */ + LOGL_INFO, + /** @LOGL_DEBUG: Basic debug-level message */ + LOGL_DEBUG, + /** @LOGL_DEBUG_CONTENT: Debug message showing full message content */ + LOGL_DEBUG_CONTENT, + /** @LOGL_DEBUG_IO: Debug message showing hardware I/O access */ + LOGL_DEBUG_IO, + + /** @LOGL_COUNT: Total number of valid log levels */ LOGL_COUNT, + /** @LOGL_NONE: Used to indicate that there is no valid log level */ LOGL_NONE, - LOGL_LEVEL_MASK = 0xf, /* Mask for valid log levels */ - LOGL_FORCE_DEBUG = 0x10, /* Mask to force output due to LOG_DEBUG */ + /** @LOGL_LEVEL_MASK: Mask for valid log levels */ + LOGL_LEVEL_MASK = 0xf, + /** @LOGL_FORCE_DEBUG: Mask to force output due to LOG_DEBUG */ + LOGL_FORCE_DEBUG = 0x10, + /** @LOGL_FIRST: The first, most-important log level */ LOGL_FIRST = LOGL_EMERG, + /** @LOGL_MAX: The last, least-important log level */ LOGL_MAX = LOGL_DEBUG_IO, - LOGL_CONT = -1, /* Use same log level as in previous call */ + /** @LOGL_CONT: Use same log level as in previous call */ + LOGL_CONT = -1, }; /** - * Log categories supported. Most of these correspond to uclasses (i.e. - * enum uclass_id) but there are also some more generic categories. + * enum log_category_t - Log categories supported. + * + * Log categories between %LOGC_FIRST and %LOGC_NONE correspond to uclasses + * (i.e. &enum uclass_id), but there are also some more generic categories. * * Remember to update log_cat_name[] after adding a new category. */ enum log_category_t { + /** @LOGC_FIRST: First log category */ LOGC_FIRST = 0, /* First part mirrors UCLASS_... */ + /** @LOGC_NONE: Default log category */ LOGC_NONE = UCLASS_COUNT, /* First number is after all uclasses */ - LOGC_ARCH, /* Related to arch-specific code */ - LOGC_BOARD, /* Related to board-specific code */ - LOGC_CORE, /* Related to core features (non-driver-model) */ - LOGC_DM, /* Core driver-model */ - LOGC_DT, /* Device-tree */ - LOGC_EFI, /* EFI implementation */ - LOGC_ALLOC, /* Memory allocation */ - LOGC_SANDBOX, /* Related to the sandbox board */ - LOGC_BLOBLIST, /* Bloblist */ - LOGC_DEVRES, /* Device resources (devres_... functions) */ - /* Advanced Configuration and Power Interface (ACPI) */ + /** @LOGC_ARCH: Related to arch-specific code */ + LOGC_ARCH, + /** @LOGC_BOARD: Related to board-specific code */ + LOGC_BOARD, + /** @LOGC_CORE: Related to core features (non-driver-model) */ + LOGC_CORE, + /** @LOGC_DM: Core driver-model */ + LOGC_DM, + /** @LOGC_DT: Device-tree */ + LOGC_DT, + /** @LOGC_EFI: EFI implementation */ + LOGC_EFI, + /** @LOGC_ALLOC: Memory allocation */ + LOGC_ALLOC, + /** @LOGC_SANDBOX: Related to the sandbox board */ + LOGC_SANDBOX, + /** @LOGC_BLOBLIST: Bloblist */ + LOGC_BLOBLIST, + /** @LOGC_DEVRES: Device resources (``devres_...`` functions) */ + LOGC_DEVRES, + /** @LOGC_ACPI: Advanced Configuration and Power Interface (ACPI) */ LOGC_ACPI, - LOGC_COUNT, /* Number of log categories */ - LOGC_END, /* Sentinel value for a list of log categories */ - LOGC_CONT = -1, /* Use same category as in previous call */ + /** @LOGC_COUNT: Number of log categories */ + LOGC_COUNT, + /** @LOGC_END: Sentinel value for lists of log categories */ + LOGC_END, + /** @LOGC_CONT: Use same category as in previous call */ + LOGC_CONT = -1, }; /* Helper to cast a uclass ID to a log category */ @@ -85,7 +121,7 @@ static inline int log_uc_cat(enum uclass_id id) * @func: Function where log record was generated * @fmt: printf() format string for log record * @...: Optional parameters, according to the format string @fmt - * @return 0 if log record was emitted, -ve on error + * Return: 0 if log record was emitted, -ve on error */ int _log(enum log_category_t cat, enum log_level_t level, const char *file, int line, const char *func, const char *fmt, ...) @@ -240,7 +276,7 @@ void __assert_fail(const char *assertion, const char *file, unsigned int line, * full pathname as it may be huge. Only use this when the user should be * warning, similar to BUG_ON() in linux. * - * @return true if assertion succeeded (condition is true), else false + * Return: true if assertion succeeded (condition is true), else false */ #define assert_noisy(x) \ ({ bool _val = (x); \ @@ -324,8 +360,9 @@ enum log_device_flags { */ struct log_driver { const char *name; + /** - * emit() - emit a log record + * @emit: emit a log record * * Called by the log system to pass a log record to a particular driver * for processing. The filter is checked before calling this function. @@ -361,21 +398,32 @@ enum { LOGF_MAX_CATEGORIES = 5, /* maximum categories per filter */ }; +/** + * enum log_filter_flags - Flags which modify a filter + */ enum log_filter_flags { - LOGFF_HAS_CAT = 1 << 0, /* Filter has a category list */ + /** @LOGFF_HAS_CAT: Filter has a category list */ + LOGFF_HAS_CAT = 1 << 0, + /** @LOGFF_DENY: Filter denies matching messages */ + LOGFF_DENY = 1 << 1, + /** @LOGFF_LEVEL_MIN: Filter's level is a minimum, not a maximum */ + LOGFF_LEVEL_MIN = 1 << 2, }; /** * struct log_filter - criterial to filter out log messages * + * If a message matches all criteria, then it is allowed. If LOGFF_DENY is set, + * then it is denied instead. + * * @filter_num: Sequence number of this filter. This is returned when adding a * new filter, and must be provided when removing a previously added * filter. - * @flags: Flags for this filter (LOGFF_...) - * @cat_list: List of categories to allow (terminated by LOGC_none). If empty - * then all categories are permitted. Up to LOGF_MAX_CATEGORIES entries + * @flags: Flags for this filter (``LOGFF_...``) + * @cat_list: List of categories to allow (terminated by %LOGC_END). If empty + * then all categories are permitted. Up to %LOGF_MAX_CATEGORIES entries * can be provided - * @max_level: Maximum log level to allow + * @level: Maximum (or minimum, if %LOGFF_MIN_LEVEL) log level to allow * @file_list: List of files to allow, separated by comma. If NULL then all * files are permitted * @sibling_node: Next filter in the list of filters for this log device @@ -384,7 +432,7 @@ struct log_filter { int filter_num; int flags; enum log_category_t cat_list[LOGF_MAX_CATEGORIES]; - enum log_level_t max_level; + enum log_level_t level; const char *file_list; struct list_head sibling_node; }; @@ -400,8 +448,9 @@ struct log_filter { * log_get_cat_name() - Get the name of a category * * @cat: Category to look up - * @return category name (which may be a uclass driver name) if found, or - * "<invalid>" if invalid, or "<missing>" if not found + * Return: category name (which may be a uclass driver name) if found, or + * "<invalid>" if invalid, or "<missing>" if not found. All error + * responses begin with '<'. */ const char *log_get_cat_name(enum log_category_t cat); @@ -409,7 +458,7 @@ const char *log_get_cat_name(enum log_category_t cat); * log_get_cat_by_name() - Look up a category by name * * @name: Name to look up - * @return category ID, or LOGC_NONE if not found + * Return: Category, or %LOGC_NONE if not found */ enum log_category_t log_get_cat_by_name(const char *name); @@ -417,7 +466,7 @@ enum log_category_t log_get_cat_by_name(const char *name); * log_get_level_name() - Get the name of a log level * * @level: Log level to look up - * @return log level name (in ALL CAPS) + * Return: Log level name (in ALL CAPS) */ const char *log_get_level_name(enum log_level_t level); @@ -425,10 +474,41 @@ const char *log_get_level_name(enum log_level_t level); * log_get_level_by_name() - Look up a log level by name * * @name: Name to look up - * @return log level ID, or LOGL_NONE if not found + * Return: Log level, or %LOGL_NONE if not found */ enum log_level_t log_get_level_by_name(const char *name); +/** + * log_device_find_by_name() - Look up a log device by its driver's name + * + * @drv_name: Name of the driver + * Return: the log device, or %NULL if not found + */ +struct log_device *log_device_find_by_name(const char *drv_name); + +/** + * log_has_cat() - check if a log category exists within a list + * + * @cat_list: List of categories to check, at most %LOGF_MAX_CATEGORIES entries + * long, terminated by %LC_END if fewer + * @cat: Category to search for + * + * Return: ``true`` if @cat is in @cat_list, else ``false`` + */ +bool log_has_cat(enum log_category_t cat_list[], enum log_category_t cat); + +/** + * log_has_file() - check if a file is with a list + * + * @file_list: List of files to check, separated by comma + * @file: File to check for. This string is matched against the end of each + * file in the list, i.e. ignoring any preceding path. The list is + * intended to consist of relative pathnames, e.g. common/main.c,cmd/log.c + * + * Return: ``true`` if @file is in @file_list, else ``false`` + */ +bool log_has_file(const char *file_list, const char *file); + /* Log format flags (bit numbers) for gd->log_fmt. See log_fmt_chars */ enum log_fmt { LOGF_CAT = 0, @@ -446,21 +526,48 @@ enum log_fmt { int do_log_test(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]); /** + * log_add_filter_flags() - Add a new filter to a log device, specifying flags + * + * @drv_name: Driver name to add the filter to (since each driver only has a + * single device) + * @flags: Flags for this filter (``LOGFF_...``) + * @cat_list: List of categories to allow (terminated by %LOGC_END). If empty + * then all categories are permitted. Up to %LOGF_MAX_CATEGORIES entries + * can be provided + * @level: Maximum (or minimum, if %LOGFF_LEVEL_MIN) log level to allow + * @file_list: List of files to allow, separated by comma. If NULL then all + * files are permitted + * Return: + * the sequence number of the new filter (>=0) if the filter was added, or a + * -ve value on error + */ +int log_add_filter_flags(const char *drv_name, enum log_category_t cat_list[], + enum log_level_t level, const char *file_list, + int flags); + +/** * log_add_filter() - Add a new filter to a log device * * @drv_name: Driver name to add the filter to (since each driver only has a * single device) - * @cat_list: List of categories to allow (terminated by LOGC_none). If empty - * then all categories are permitted. Up to LOGF_MAX_CATEGORIES entries + * @cat_list: List of categories to allow (terminated by %LOGC_END). If empty + * then all categories are permitted. Up to %LOGF_MAX_CATEGORIES entries * can be provided * @max_level: Maximum log level to allow - * @file_list: List of files to allow, separated by comma. If NULL then all + * @file_list: List of files to allow, separated by comma. If %NULL then all * files are permitted - * @return the sequence number of the new filter (>=0) if the filter was added, - * or a -ve value on error + * Return: + * the sequence number of the new filter (>=0) if the filter was added, or a + * -ve value on error */ -int log_add_filter(const char *drv_name, enum log_category_t cat_list[], - enum log_level_t max_level, const char *file_list); +static inline int log_add_filter(const char *drv_name, + enum log_category_t cat_list[], + enum log_level_t max_level, + const char *file_list) +{ + return log_add_filter_flags(drv_name, cat_list, max_level, file_list, + 0); +} /** * log_remove_filter() - Remove a filter from a log device @@ -468,8 +575,9 @@ int log_add_filter(const char *drv_name, enum log_category_t cat_list[], * @drv_name: Driver name to remove the filter from (since each driver only has * a single device) * @filter_num: Filter number to remove (as returned by log_add_filter()) - * @return 0 if the filter was removed, -ENOENT if either the driver or the - * filter number was not found + * Return: + * 0 if the filter was removed, -%ENOENT if either the driver or the filter + * number was not found */ int log_remove_filter(const char *drv_name, int filter_num); @@ -490,7 +598,7 @@ int log_device_set_enable(struct log_driver *drv, bool enable); /** * log_init() - Set up the log system ready for use * - * @return 0 if OK, -ENOMEM if out of memory + * Return: 0 if OK, -%ENOMEM if out of memory */ int log_init(void); #else @@ -504,7 +612,7 @@ static inline int log_init(void) * log_get_default_format() - get default log format * * The default log format is configurable via - * CONFIG_LOGF_FILE, CONFIG_LOGF_LINE, CONFIG_LOGF_FUNC. + * %CONFIG_LOGF_FILE, %CONFIG_LOGF_LINE, and %CONFIG_LOGF_FUNC. * * Return: default log format */ diff --git a/include/mmc.h b/include/mmc.h index ac7b54f..1d377e0 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -360,6 +360,19 @@ enum mmc_voltage { #define MMC_NUM_BOOT_PARTITION 2 #define MMC_PART_RPMB 3 /* RPMB partition number */ +/* timing specification used */ +#define MMC_TIMING_LEGACY 0 +#define MMC_TIMING_MMC_HS 1 +#define MMC_TIMING_SD_HS 2 +#define MMC_TIMING_UHS_SDR12 3 +#define MMC_TIMING_UHS_SDR25 4 +#define MMC_TIMING_UHS_SDR50 5 +#define MMC_TIMING_UHS_SDR104 6 +#define MMC_TIMING_UHS_DDR50 7 +#define MMC_TIMING_MMC_DDR52 8 +#define MMC_TIMING_MMC_HS200 9 +#define MMC_TIMING_MMC_HS400 10 + /* Driver model support */ /** diff --git a/include/pci.h b/include/pci.h index 1c5b366..d1ccf6c 100644 --- a/include/pci.h +++ b/include/pci.h @@ -495,12 +495,18 @@ #define PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */ #define PCI_EXP_SLTCAP 20 /* Slot Capabilities */ #define PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */ +#define PCI_EXP_DEVCAP2 36 /* Device Capabilities 2 */ +#define PCI_EXP_DEVCAP2_ARI 0x00000020 /* ARI Forwarding Supported */ +#define PCI_EXP_DEVCTL2 40 /* Device Control 2 */ +#define PCI_EXP_DEVCTL2_ARI 0x0020 /* Alternative Routing-ID */ + #define PCI_EXP_LNKCTL2 48 /* Link Control 2 */ /* Single Root I/O Virtualization Registers */ #define PCI_SRIOV_CAP 0x04 /* SR-IOV Capabilities */ #define PCI_SRIOV_CTRL 0x08 /* SR-IOV Control */ #define PCI_SRIOV_CTRL_VFE 0x01 /* VF Enable */ #define PCI_SRIOV_CTRL_MSE 0x08 /* VF Memory Space Enable */ +#define PCI_SRIOV_CTRL_ARI 0x10 /* ARI Capable Hierarchy */ #define PCI_SRIOV_INITIAL_VF 0x0c /* Initial VFs */ #define PCI_SRIOV_TOTAL_VF 0x0e /* Total VFs */ #define PCI_SRIOV_NUM_VF 0x10 /* Number of VFs */ diff --git a/include/sdhci.h b/include/sdhci.h index f69d5f8..1fd20ec 100644 --- a/include/sdhci.h +++ b/include/sdhci.h @@ -244,6 +244,7 @@ #define SDHCI_QUIRK_BROKEN_HISPD_MODE BIT(5) #define SDHCI_QUIRK_WAIT_SEND_CMD (1 << 6) #define SDHCI_QUIRK_USE_WIDE8 (1 << 8) +#define SDHCI_QUIRK_NO_1_8_V (1 << 9) /* to make gcc happy */ struct sdhci_host; diff --git a/include/test/log.h b/include/test/log.h index c661cde..e902891 100644 --- a/include/test/log.h +++ b/include/test/log.h @@ -10,7 +10,10 @@ #include <test/test.h> +#define LOGF_TEST (BIT(LOGF_FUNC) | BIT(LOGF_MSG)) + /* Declare a new logging test */ #define LOG_TEST(_name) UNIT_TEST(_name, 0, log_test) +#define LOG_TEST_FLAGS(_name, _flags) UNIT_TEST(_name, _flags, log_test) #endif /* __TEST_LOG_H__ */ diff --git a/include/test/test.h b/include/test/test.h index 67c7d69..03e2929 100644 --- a/include/test/test.h +++ b/include/test/test.h @@ -94,4 +94,15 @@ enum { TEST_DEVRES_SIZE3 = 37, }; +/** + * dm_test_main() - Run driver model tests + * + * Run all the available driver model tests, or a selection + * + * @test_name: Name of single test to run (e.g. "dm_test_fdt_pre_reloc" or just + * "fdt_pre_reloc"), or NULL to run all + * @return 0 if all tests passed, 1 if not + */ +int dm_test_main(const char *test_name); + #endif /* __TEST_TEST_H */ diff --git a/include/u-boot/rsa-mod-exp.h b/include/u-boot/rsa-mod-exp.h index 1da8af1..7b7c291 100644 --- a/include/u-boot/rsa-mod-exp.h +++ b/include/u-boot/rsa-mod-exp.h @@ -66,7 +66,7 @@ int rsa_mod_exp(struct udevice *dev, const uint8_t *sig, uint32_t sig_len, struct key_prop *node, uint8_t *out); #if defined(CONFIG_CMD_ZYNQ_RSA) -int zynq_pow_mod(u32 *keyptr, u32 *inout); +int zynq_pow_mod(uint32_t *keyptr, uint32_t *inout); #endif /** diff --git a/include/zynqmp_tap_delay.h b/include/zynqmp_tap_delay.h index b07e3e0..7b71343 100644 --- a/include/zynqmp_tap_delay.h +++ b/include/zynqmp_tap_delay.h @@ -10,10 +10,11 @@ #ifdef CONFIG_ARCH_ZYNQMP void zynqmp_dll_reset(u8 deviceid); -void arasan_zynqmp_set_tapdelay(u8 device_id, u8 uhsmode, u8 bank); +void arasan_zynqmp_set_tapdelay(u8 device_id, u32 itap_delay, u32 otap_delay); #else inline void zynqmp_dll_reset(u8 deviceid) {} -inline void arasan_zynqmp_set_tapdelay(u8 device_id, u8 uhsmode, u8 bank) {} +inline void arasan_zynqmp_set_tapdelay(u8 device_id, u32 itap_delay, + u32 otap_delay) {} #endif #endif diff --git a/lib/Kconfig b/lib/Kconfig index 37aae73..79651ea 100644 --- a/lib/Kconfig +++ b/lib/Kconfig @@ -550,6 +550,11 @@ config SPL_HEXDUMP This enables functions for printing dumps of binary data in SPL. +config GETOPT + bool "Enable getopt" + help + This enables functions for parsing command-line options. + config OF_LIBFDT bool "Enable the FDT library" default y if OF_CONTROL diff --git a/lib/Makefile b/lib/Makefile index 0cd7bea..7c7fb9a 100644 --- a/lib/Makefile +++ b/lib/Makefile @@ -106,6 +106,7 @@ obj-y += string.o obj-y += tables_csum.o obj-y += time.o obj-y += hexdump.o +obj-$(CONFIG_GETOPT) += getopt.o obj-$(CONFIG_TRACE) += trace.o obj-$(CONFIG_LIB_UUID) += uuid.o obj-$(CONFIG_LIB_RAND) += rand.o diff --git a/lib/binman.c b/lib/binman.c index 7a8ad62..e71c1b9 100644 --- a/lib/binman.c +++ b/lib/binman.c @@ -43,7 +43,7 @@ static int binman_entry_find_internal(ofnode node, const char *name, ret = ofnode_read_u32(node, "image-pos", &entry->image_pos); if (ret) - return log_msg_ret("import-pos", ret); + return log_msg_ret("image-pos", ret); ret = ofnode_read_u32(node, "size", &entry->size); if (ret) return log_msg_ret("size", ret); @@ -83,6 +83,11 @@ void binman_set_rom_offset(int rom_offset) binman->rom_offset = rom_offset; } +int binman_get_rom_offset(void) +{ + return binman->rom_offset; +} + int binman_init(void) { binman = malloc(sizeof(struct binman_info)); @@ -91,6 +96,13 @@ int binman_init(void) binman->image = ofnode_path("/binman"); if (!ofnode_valid(binman->image)) return log_msg_ret("binman node", -EINVAL); + if (ofnode_read_bool(binman->image, "multiple-images")) { + ofnode node = ofnode_first_subnode(binman->image); + + if (!ofnode_valid(node)) + return log_msg_ret("first image", -ENOENT); + binman->image = node; + } binman->rom_offset = ROM_OFFSET_NONE; return 0; diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig index ab42f3b..0754814 100644 --- a/lib/efi_loader/Kconfig +++ b/lib/efi_loader/Kconfig @@ -27,6 +27,10 @@ config EFI_LOADER if EFI_LOADER +config EFI_SETUP_EARLY + bool + default n + choice prompt "Store for non-volatile UEFI variables" default EFI_VARIABLE_FILE_STORE diff --git a/lib/efi_loader/Makefile b/lib/efi_loader/Makefile index 9bad1d1..8892fb0 100644 --- a/lib/efi_loader/Makefile +++ b/lib/efi_loader/Makefile @@ -34,6 +34,7 @@ obj-y += efi_memory.o obj-y += efi_root_node.o obj-y += efi_runtime.o obj-y += efi_setup.o +obj-y += efi_string.o obj-$(CONFIG_EFI_UNICODE_COLLATION_PROTOCOL2) += efi_unicode_collation.o obj-y += efi_var_common.o obj-y += efi_var_mem.o diff --git a/lib/efi_loader/efi_boottime.c b/lib/efi_loader/efi_boottime.c index b26ac9f..dfa71b1 100644 --- a/lib/efi_loader/efi_boottime.c +++ b/lib/efi_loader/efi_boottime.c @@ -3523,6 +3523,7 @@ static efi_status_t EFIAPI efi_disconnect_controller( size_t number_of_children = 0; efi_status_t r; struct efi_object *efiobj; + bool sole_child; EFI_ENTRY("%p, %p, %p", controller_handle, driver_image_handle, child_handle); @@ -3545,16 +3546,18 @@ static efi_status_t EFIAPI efi_disconnect_controller( } /* Create list of child handles */ + r = efi_get_child_controllers(efiobj, + driver_image_handle, + &number_of_children, + &child_handle_buffer); + if (r != EFI_SUCCESS) + return r; + sole_child = (number_of_children == 1); + if (child_handle) { number_of_children = 1; + free(child_handle_buffer); child_handle_buffer = &child_handle; - } else { - r = efi_get_child_controllers(efiobj, - driver_image_handle, - &number_of_children, - &child_handle_buffer); - if (r != EFI_SUCCESS) - return r; } /* Get the driver binding protocol */ @@ -3579,7 +3582,7 @@ static efi_status_t EFIAPI efi_disconnect_controller( } } /* Remove the driver */ - if (!child_handle) { + if (!child_handle || sole_child) { r = EFI_CALL(binding_protocol->stop(binding_protocol, controller_handle, 0, NULL)); diff --git a/lib/efi_loader/efi_string.c b/lib/efi_loader/efi_string.c new file mode 100644 index 0000000..3de721f --- /dev/null +++ b/lib/efi_loader/efi_string.c @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * String functions + * + * Copyright (c) 2020 AKASHI Takahiro, Linaro Limited + */ + +#include <common.h> +#include <charset.h> + +/** + * efi_create_indexed_name - create a string name with an index + * @buffer: Buffer + * @name: Name string + * @index: Index + * + * Create a utf-16 string with @name, appending @index. + * For example, L"Capsule0001" + * + * The caller must ensure that the buffer has enough space for the resulting + * string including the trailing L'\0'. + * + * Return: A pointer to the next position after the created string + * in @buffer, or NULL otherwise + */ +u16 *efi_create_indexed_name(u16 *buffer, const char *name, unsigned int index) +{ + u16 *p = buffer; + char index_buf[5]; + + utf8_utf16_strcpy(&p, name); + sprintf(index_buf, "%04X", index); + utf8_utf16_strcpy(&p, index_buf); + + return p; +} diff --git a/lib/getopt.c b/lib/getopt.c new file mode 100644 index 0000000..8b4515d --- /dev/null +++ b/lib/getopt.c @@ -0,0 +1,125 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * getopt.c - a simple getopt(3) implementation. See getopt.h for explanation. + * + * Copyright (C) 2020 Sean Anderson <seanga2@gmail.com> + * Copyright (c) 2007 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix + */ + +#define LOG_CATEGORY LOGC_CORE + +#include <common.h> +#include <getopt.h> +#include <log.h> + +void getopt_init_state(struct getopt_state *gs) +{ + gs->index = 1; + gs->arg_index = 1; +} + +int __getopt(struct getopt_state *gs, int argc, char *const argv[], + const char *optstring, bool silent) +{ + char curopt; /* current option character */ + const char *curoptp; /* pointer to the current option in optstring */ + + while (1) { + log_debug("arg_index: %d index: %d\n", gs->arg_index, + gs->index); + + /* `--` indicates the end of options */ + if (gs->arg_index == 1 && argv[gs->index] && + !strcmp(argv[gs->index], "--")) { + gs->index++; + return -1; + } + + /* Out of arguments */ + if (gs->index >= argc) + return -1; + + /* Can't parse non-options */ + if (*argv[gs->index] != '-') + return -1; + + /* We have found an option */ + curopt = argv[gs->index][gs->arg_index]; + if (curopt) + break; + /* + * no more options in current argv[] element; try the next one + */ + gs->index++; + gs->arg_index = 1; + } + + /* look up current option in optstring */ + curoptp = strchr(optstring, curopt); + + if (!curoptp) { + if (!silent) + printf("%s: invalid option -- %c\n", argv[0], curopt); + gs->opt = curopt; + gs->arg_index++; + return '?'; + } + + if (*(curoptp + 1) != ':') { + /* option with no argument. Just return it */ + gs->arg = NULL; + gs->arg_index++; + return curopt; + } + + if (*(curoptp + 1) && *(curoptp + 2) == ':') { + /* optional argument */ + if (argv[gs->index][gs->arg_index + 1]) { + /* optional argument with directly following arg */ + gs->arg = argv[gs->index++] + gs->arg_index + 1; + gs->arg_index = 1; + return curopt; + } + if (gs->index + 1 == argc) { + /* We are at the last argv[] element */ + gs->arg = NULL; + gs->index++; + return curopt; + } + if (*argv[gs->index + 1] != '-') { + /* + * optional argument with arg in next argv[] element + */ + gs->index++; + gs->arg = argv[gs->index++]; + gs->arg_index = 1; + return curopt; + } + + /* no optional argument found */ + gs->arg = NULL; + gs->arg_index = 1; + gs->index++; + return curopt; + } + + if (argv[gs->index][gs->arg_index + 1]) { + /* required argument with directly following arg */ + gs->arg = argv[gs->index++] + gs->arg_index + 1; + gs->arg_index = 1; + return curopt; + } + + gs->index++; + gs->arg_index = 1; + + if (gs->index >= argc || argv[gs->index][0] == '-') { + if (!silent) + printf("option requires an argument -- %c\n", curopt); + gs->opt = curopt; + return ':'; + } + + gs->arg = argv[gs->index++]; + return curopt; +} diff --git a/lib/rsa/rsa-mod-exp.c b/lib/rsa/rsa-mod-exp.c index 78c688d..74f9eb1 100644 --- a/lib/rsa/rsa-mod-exp.c +++ b/lib/rsa/rsa-mod-exp.c @@ -321,7 +321,7 @@ int rsa_mod_exp_sw(const uint8_t *sig, uint32_t sig_len, * pow_mod calculation required for zynq is bit different from * pw_mod above here, hence defined zynq specific routine. */ -int zynq_pow_mod(u32 *keyptr, u32 *inout) +int zynq_pow_mod(uint32_t *keyptr, uint32_t *inout) { u32 *result, *ptr; uint i; diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl index d528c99..9f1f744 100644 --- a/scripts/Makefile.spl +++ b/scripts/Makefile.spl @@ -99,6 +99,7 @@ libs-y += dts/ libs-y += fs/ libs-$(CONFIG_SPL_POST_MEM_SUPPORT) += post/drivers/ libs-$(CONFIG_SPL_NET_SUPPORT) += net/ +libs-$(CONFIG_SPL_UNIT_TEST) += test/ head-y := $(addprefix $(obj)/,$(head-y)) libs-y := $(addprefix $(obj)/,$(libs-y)) @@ -213,7 +214,7 @@ spl/boot.bin: $(obj)/$(SPL_BIN)-align.bin FORCE $(call if_changed,mkimage) endif -INPUTS-y += $(obj)/$(SPL_BIN).bin +INPUTS-y += $(obj)/$(SPL_BIN).bin $(obj)/$(SPL_BIN).sym ifdef CONFIG_SAMSUNG INPUTS-y += $(obj)/$(BOARD)-spl.bin @@ -407,6 +408,11 @@ MKIMAGEFLAGS_u-boot-spl-mtk.bin = -T mtk_image \ $(obj)/u-boot-spl-mtk.bin: $(obj)/u-boot-spl.bin FORCE $(call if_changed,mkimage) +quiet_cmd_sym ?= SYM $@ + cmd_sym ?= $(OBJDUMP) -t $< > $@ +$(obj)/$(SPL_BIN).sym: $(obj)/$(SPL_BIN) FORCE + $(call if_changed,sym) + # Rule to link u-boot-spl # May be overridden by arch/$(ARCH)/config.mk quiet_cmd_u-boot-spl ?= LD $@ diff --git a/test/Kconfig b/test/Kconfig index 28704a2..2646e7d 100644 --- a/test/Kconfig +++ b/test/Kconfig @@ -6,6 +6,16 @@ menuconfig UNIT_TEST This does not require sandbox to be included, but it is most often used there. +config SPL_UNIT_TEST + bool "Unit tests in SPL" + # We need to be able to unbind devices for tests to work + select SPL_DM_DEVICE_REMOVE + help + Select this to enable unit tests in SPL. Most test are designed for + running in U-Boot proper, but some are intended for SPL, such as + of-platdata and SPL handover. To run these tests with the sandbox_spl + board, use the -u (unit test) option. + config UT_LIB bool "Unit tests for library functions" depends on UNIT_TEST diff --git a/test/Makefile b/test/Makefile index 7c40399..1c930b3 100644 --- a/test/Makefile +++ b/test/Makefile @@ -2,15 +2,19 @@ # # (C) Copyright 2012 The Chromium Authors -obj-$(CONFIG_SANDBOX) += bloblist.o -obj-$(CONFIG_CMDLINE) += cmd/ -obj-$(CONFIG_UNIT_TEST) += cmd_ut.o -obj-$(CONFIG_UNIT_TEST) += ut.o -obj-$(CONFIG_SANDBOX) += command_ut.o -obj-$(CONFIG_SANDBOX) += compression.o -obj-$(CONFIG_SANDBOX) += print_ut.o -obj-$(CONFIG_SANDBOX) += str_ut.o +obj-$(CONFIG_$(SPL_)CMDLINE) += bloblist.o +obj-$(CONFIG_$(SPL_)CMDLINE) += cmd/ +obj-$(CONFIG_$(SPL_)CMDLINE) += cmd_ut.o +obj-$(CONFIG_$(SPL_)CMDLINE) += command_ut.o +obj-$(CONFIG_$(SPL_)CMDLINE) += compression.o +obj-y += dm/ +obj-$(CONFIG_$(SPL_)CMDLINE) += print_ut.o +obj-$(CONFIG_$(SPL_)CMDLINE) += str_ut.o obj-$(CONFIG_UT_TIME) += time_ut.o -obj-$(CONFIG_UT_UNICODE) += unicode_ut.o -obj-y += log/ +obj-y += ut.o + +ifeq ($(CONFIG_SPL_BUILD),) obj-$(CONFIG_UNIT_TEST) += lib/ +obj-y += log/ +obj-$(CONFIG_$(SPL_)UT_UNICODE) += unicode_ut.o +endif diff --git a/test/dm/Makefile b/test/dm/Makefile index 8b3d77e..57e13ad 100644 --- a/test/dm/Makefile +++ b/test/dm/Makefile @@ -2,15 +2,18 @@ # # Copyright (c) 2013 Google, Inc +obj-$(CONFIG_UT_DM) += test-main.o + +# Tests for particular subsystems - when enabling driver model for a new +# subsystem you must add sandbox tests here. +ifeq ($(CONFIG_SPL_BUILD),y) +obj-$(CONFIG_SPL_OF_PLATDATA) += of_platdata.o +else obj-$(CONFIG_UT_DM) += bus.o -obj-$(CONFIG_UT_DM) += nop.o obj-$(CONFIG_UT_DM) += test-driver.o obj-$(CONFIG_UT_DM) += test-fdt.o -obj-$(CONFIG_UT_DM) += test-main.o obj-$(CONFIG_UT_DM) += test-uclass.o -# Tests for particular subsystems - when enabling driver model for a new -# subsystem you must add sandbox tests here. obj-$(CONFIG_UT_DM) += core.o ifneq ($(CONFIG_SANDBOX),) obj-$(CONFIG_ACPIGEN) += acpi.o @@ -36,6 +39,7 @@ obj-$(CONFIG_DM_MAILBOX) += mailbox.o obj-$(CONFIG_DM_MMC) += mmc.o obj-$(CONFIG_CMD_MUX) += mux-cmd.o obj-y += fdtdec.o +obj-$(CONFIG_UT_DM) += nop.o obj-y += ofnode.o obj-y += ofread.o obj-$(CONFIG_OSD) += osd.o @@ -88,3 +92,4 @@ ifneq ($(CONFIG_PINMUX),) obj-$(CONFIG_PINCONF) += pinmux.o endif endif +endif # !SPL diff --git a/test/dm/of_platdata.c b/test/dm/of_platdata.c new file mode 100644 index 0000000..4f3cc15 --- /dev/null +++ b/test/dm/of_platdata.c @@ -0,0 +1,222 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include <common.h> +#include <dm.h> +#include <dt-structs.h> +#include <dm/test.h> +#include <test/test.h> +#include <test/ut.h> + +/* Test that we can find a device using of-platdata */ +static int dm_test_of_platdata_base(struct unit_test_state *uts) +{ + struct udevice *dev; + + ut_assertok(uclass_first_device_err(UCLASS_SERIAL, &dev)); + ut_asserteq_str("sandbox_serial", dev->name); + + return 0; +} +DM_TEST(dm_test_of_platdata_base, UT_TESTF_SCAN_PDATA); + +/* Test that we can read properties from a device */ +static int dm_test_of_platdata_props(struct unit_test_state *uts) +{ + struct dtd_sandbox_spl_test *plat; + struct udevice *dev; + int i; + + /* Skip the clock */ + ut_assertok(uclass_first_device_err(UCLASS_MISC, &dev)); + ut_asserteq_str("sandbox_clk_test", dev->name); + + ut_assertok(uclass_next_device_err(&dev)); + plat = dev_get_platdata(dev); + ut_assert(plat->boolval); + ut_asserteq(1, plat->intval); + ut_asserteq(4, ARRAY_SIZE(plat->intarray)); + ut_asserteq(2, plat->intarray[0]); + ut_asserteq(3, plat->intarray[1]); + ut_asserteq(4, plat->intarray[2]); + ut_asserteq(0, plat->intarray[3]); + ut_asserteq(5, plat->byteval); + ut_asserteq(3, ARRAY_SIZE(plat->bytearray)); + ut_asserteq(6, plat->bytearray[0]); + ut_asserteq(0, plat->bytearray[1]); + ut_asserteq(0, plat->bytearray[2]); + ut_asserteq(9, ARRAY_SIZE(plat->longbytearray)); + for (i = 0; i < ARRAY_SIZE(plat->longbytearray); i++) + ut_asserteq(9 + i, plat->longbytearray[i]); + ut_asserteq_str("message", plat->stringval); + ut_asserteq(3, ARRAY_SIZE(plat->stringarray)); + ut_asserteq_str("multi-word", plat->stringarray[0]); + ut_asserteq_str("message", plat->stringarray[1]); + ut_asserteq_str("", plat->stringarray[2]); + + ut_assertok(uclass_next_device_err(&dev)); + plat = dev_get_platdata(dev); + ut_assert(!plat->boolval); + ut_asserteq(3, plat->intval); + ut_asserteq(5, plat->intarray[0]); + ut_asserteq(0, plat->intarray[1]); + ut_asserteq(0, plat->intarray[2]); + ut_asserteq(0, plat->intarray[3]); + ut_asserteq(8, plat->byteval); + ut_asserteq(3, ARRAY_SIZE(plat->bytearray)); + ut_asserteq(1, plat->bytearray[0]); + ut_asserteq(0x23, plat->bytearray[1]); + ut_asserteq(0x34, plat->bytearray[2]); + for (i = 0; i < ARRAY_SIZE(plat->longbytearray); i++) + ut_asserteq(i < 4 ? 9 + i : 0, plat->longbytearray[i]); + ut_asserteq_str("message2", plat->stringval); + ut_asserteq_str("another", plat->stringarray[0]); + ut_asserteq_str("multi-word", plat->stringarray[1]); + ut_asserteq_str("message", plat->stringarray[2]); + + ut_assertok(uclass_next_device_err(&dev)); + plat = dev_get_platdata(dev); + ut_assert(!plat->boolval); + ut_asserteq_str("one", plat->stringarray[0]); + ut_asserteq_str("", plat->stringarray[1]); + ut_asserteq_str("", plat->stringarray[2]); + + ut_assertok(uclass_next_device_err(&dev)); + plat = dev_get_platdata(dev); + ut_assert(!plat->boolval); + ut_asserteq_str("spl", plat->stringarray[0]); + + ut_asserteq(-ENODEV, uclass_next_device_err(&dev)); + + return 0; +} +DM_TEST(dm_test_of_platdata_props, UT_TESTF_SCAN_PDATA); + +/* + * find_driver_info - recursively find the driver_info for a device + * + * This sets found[idx] to true when it finds the driver_info record for a + * device, where idx is the index in the driver_info linker list. + * + * @uts: Test state + * @parent: Parent to search + * @found: bool array to update + * @return 0 if OK, non-zero on error + */ +static int find_driver_info(struct unit_test_state *uts, struct udevice *parent, + bool found[]) +{ + struct udevice *dev; + + /* If not the root device, find the entry that caused it to be bound */ + if (parent->parent) { + const int n_ents = + ll_entry_count(struct driver_info, driver_info); + int idx = -1; + int i; + + for (i = 0; i < n_ents; i++) { + const struct driver_rt *drt = gd_dm_driver_rt() + i; + + if (drt->dev == parent) { + idx = i; + found[idx] = true; + break; + } + } + + ut_assert(idx != -1); + } + + device_foreach_child(dev, parent) { + int ret; + + ret = find_driver_info(uts, dev, found); + if (ret < 0) + return ret; + } + + return 0; +} + +/* Check that every device is recorded in its driver_info struct */ +static int dm_test_of_platdata_dev(struct unit_test_state *uts) +{ + const struct driver_info *info = + ll_entry_start(struct driver_info, driver_info); + const int n_ents = ll_entry_count(struct driver_info, driver_info); + bool found[n_ents]; + uint i; + + /* Record the indexes that are found */ + memset(found, '\0', sizeof(found)); + ut_assertok(find_driver_info(uts, gd->dm_root, found)); + + /* Make sure that the driver entries without devices have no ->dev */ + for (i = 0; i < n_ents; i++) { + const struct driver_rt *drt = gd_dm_driver_rt() + i; + const struct driver_info *entry = info + i; + struct udevice *dev; + + if (found[i]) { + /* Make sure we can find it */ + ut_assertnonnull(drt->dev); + ut_assertok(device_get_by_driver_info(entry, &dev)); + ut_asserteq_ptr(dev, drt->dev); + } else { + ut_assertnull(drt->dev); + ut_asserteq(-ENOENT, + device_get_by_driver_info(entry, &dev)); + } + } + + return 0; +} +DM_TEST(dm_test_of_platdata_dev, UT_TESTF_SCAN_PDATA); + +/* Test handling of phandles that point to other devices */ +static int dm_test_of_platdata_phandle(struct unit_test_state *uts) +{ + struct dtd_sandbox_clk_test *plat; + struct udevice *dev, *clk; + + ut_assertok(uclass_first_device_err(UCLASS_MISC, &dev)); + ut_asserteq_str("sandbox_clk_test", dev->name); + plat = dev_get_platdata(dev); + + ut_assertok(device_get_by_driver_info_idx(plat->clocks[0].idx, &clk)); + ut_asserteq_str("fixed_clock", clk->name); + + ut_assertok(device_get_by_driver_info_idx(plat->clocks[1].idx, &clk)); + ut_asserteq_str("sandbox_clk", clk->name); + ut_asserteq(1, plat->clocks[1].arg[0]); + + ut_assertok(device_get_by_driver_info_idx(plat->clocks[2].idx, &clk)); + ut_asserteq_str("sandbox_clk", clk->name); + ut_asserteq(0, plat->clocks[2].arg[0]); + + ut_assertok(device_get_by_driver_info_idx(plat->clocks[3].idx, &clk)); + ut_asserteq_str("sandbox_clk", clk->name); + ut_asserteq(3, plat->clocks[3].arg[0]); + + ut_assertok(device_get_by_driver_info_idx(plat->clocks[4].idx, &clk)); + ut_asserteq_str("sandbox_clk", clk->name); + ut_asserteq(2, plat->clocks[4].arg[0]); + + return 0; +} +DM_TEST(dm_test_of_platdata_phandle, UT_TESTF_SCAN_PDATA); + +#if CONFIG_IS_ENABLED(OF_PLATDATA_PARENT) +/* Test that device parents are correctly set up */ +static int dm_test_of_platdata_parent(struct unit_test_state *uts) +{ + struct udevice *rtc, *i2c; + + ut_assertok(uclass_first_device_err(UCLASS_RTC, &rtc)); + ut_assertok(uclass_first_device_err(UCLASS_I2C, &i2c)); + ut_asserteq_ptr(i2c, dev_get_parent(rtc)); + + return 0; +} +DM_TEST(dm_test_of_platdata_parent, UT_TESTF_SCAN_PDATA); +#endif diff --git a/test/dm/ofnode.c b/test/dm/ofnode.c index 01ac3c2..fb1ceb1 100644 --- a/test/dm/ofnode.c +++ b/test/dm/ofnode.c @@ -207,6 +207,28 @@ static int dm_test_ofnode_read_chosen(struct unit_test_state *uts) } DM_TEST(dm_test_ofnode_read_chosen, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT); +static int dm_test_ofnode_read_aliases(struct unit_test_state *uts) +{ + const void *val; + ofnode node; + int size; + + node = ofnode_get_aliases_node("eth3"); + ut_assert(ofnode_valid(node)); + ut_asserteq_str("sbe5", ofnode_get_name(node)); + + node = ofnode_get_aliases_node("unknown"); + ut_assert(!ofnode_valid(node)); + + val = ofnode_read_aliases_prop("spi0", &size); + ut_assertnonnull(val); + ut_asserteq(7, size); + ut_asserteq_str("/spi@0", (const char *)val); + + return 0; +} +DM_TEST(dm_test_ofnode_read_aliases, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT); + static int dm_test_ofnode_get_child_count(struct unit_test_state *uts) { ofnode node, child_node; diff --git a/test/dm/test-main.c b/test/dm/test-main.c index 38b7b148..fd24635 100644 --- a/test/dm/test-main.c +++ b/test/dm/test-main.c @@ -30,13 +30,12 @@ static int dm_test_init(struct unit_test_state *uts, bool of_live) memset(dms, '\0', sizeof(*dms)); gd->dm_root = NULL; - memset(dm_testdrv_op_count, '\0', sizeof(dm_testdrv_op_count)); + if (!CONFIG_IS_ENABLED(OF_PLATDATA)) + memset(dm_testdrv_op_count, '\0', sizeof(dm_testdrv_op_count)); state_reset_for_test(state_get_current()); -#ifdef CONFIG_OF_LIVE /* Determine whether to make the live tree available */ - gd->of_root = of_live ? uts->of_root : NULL; -#endif + gd_set_of_root(of_live ? uts->of_root : NULL); ut_assertok(dm_init(of_live)); dms->root = dm_root(); @@ -93,7 +92,8 @@ static int dm_do_test(struct unit_test_state *uts, struct unit_test *test, ut_assertok(dm_scan_platdata(false)); if (test->flags & UT_TESTF_PROBE_TEST) ut_assertok(do_autoprobe(uts)); - if (test->flags & UT_TESTF_SCAN_FDT) + if (!CONFIG_IS_ENABLED(OF_PLATDATA) && + (test->flags & UT_TESTF_SCAN_FDT)) ut_assertok(dm_extended_scan_fdt(gd->fdt_blob, false)); /* @@ -127,7 +127,25 @@ static bool dm_test_run_on_flattree(struct unit_test *test) return !strstr(fname, "video") || strstr(test->name, "video_base"); } -static int dm_test_main(const char *test_name) +static bool test_matches(const char *test_name, const char *find_name) +{ + if (!find_name) + return true; + + if (!strcmp(test_name, find_name)) + return true; + + /* All tests have this prefix */ + if (!strncmp(test_name, "dm_test_", 8)) + test_name += 8; + + if (!strcmp(test_name, find_name)) + return true; + + return false; +} + +int dm_test_main(const char *test_name) { struct unit_test *tests = ll_entry_start(struct unit_test, dm_test); const int n_ents = ll_entry_count(struct unit_test, dm_test); @@ -138,36 +156,34 @@ static int dm_test_main(const char *test_name) uts->priv = &_global_priv_dm_test_state; uts->fail_count = 0; - /* - * If we have no device tree, or it only has a root node, then these - * tests clearly aren't going to work... - */ - if (!gd->fdt_blob || fdt_next_node(gd->fdt_blob, 0, NULL) < 0) { - puts("Please run with test device tree:\n" - " ./u-boot -d arch/sandbox/dts/test.dtb\n"); - ut_assert(gd->fdt_blob); + if (!CONFIG_IS_ENABLED(OF_PLATDATA)) { + /* + * If we have no device tree, or it only has a root node, then + * these * tests clearly aren't going to work... + */ + if (!gd->fdt_blob || fdt_next_node(gd->fdt_blob, 0, NULL) < 0) { + puts("Please run with test device tree:\n" + " ./u-boot -d arch/sandbox/dts/test.dtb\n"); + ut_assert(gd->fdt_blob); + } } if (!test_name) printf("Running %d driver model tests\n", n_ents); + else found = 0; -#ifdef CONFIG_OF_LIVE - uts->of_root = gd->of_root; -#endif + uts->of_root = gd_of_root(); for (test = tests; test < tests + n_ents; test++) { const char *name = test->name; int runs; - /* All tests have this prefix */ - if (!strncmp(name, "dm_test_", 8)) - name += 8; - if (test_name && strcmp(test_name, name)) + if (!test_matches(name, test_name)) continue; /* Run with the live tree if possible */ runs = 0; - if (IS_ENABLED(CONFIG_OF_LIVE)) { + if (CONFIG_IS_ENABLED(OF_LIVE)) { if (!(test->flags & UT_TESTF_FLAT_TREE)) { ut_assertok(dm_do_test(uts, test, true)); runs++; @@ -192,13 +208,12 @@ static int dm_test_main(const char *test_name) printf("Failures: %d\n", uts->fail_count); /* Put everything back to normal so that sandbox works as expected */ -#ifdef CONFIG_OF_LIVE - gd->of_root = uts->of_root; -#endif + gd_set_of_root(uts->of_root); gd->dm_root = NULL; - ut_assertok(dm_init(IS_ENABLED(CONFIG_OF_LIVE))); + ut_assertok(dm_init(CONFIG_IS_ENABLED(OF_LIVE))); dm_scan_platdata(false); - dm_scan_fdt(gd->fdt_blob, false); + if (!CONFIG_IS_ENABLED(OF_PLATDATA)) + dm_scan_fdt(gd->fdt_blob, false); return uts->fail_count ? CMD_RET_FAILURE : 0; } diff --git a/test/lib/Makefile b/test/lib/Makefile index 15cd512..98a9abf 100644 --- a/test/lib/Makefile +++ b/test/lib/Makefile @@ -14,3 +14,4 @@ obj-$(CONFIG_ERRNO_STR) += test_errno_str.o obj-$(CONFIG_UT_LIB_ASN1) += asn1.o obj-$(CONFIG_UT_LIB_RSA) += rsa.o obj-$(CONFIG_AES) += test_aes.o +obj-$(CONFIG_GETOPT) += getopt.o diff --git a/test/lib/getopt.c b/test/lib/getopt.c new file mode 100644 index 0000000..3c68b93 --- /dev/null +++ b/test/lib/getopt.c @@ -0,0 +1,123 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2020 Sean Anderson <seanga2@gmail.com> + * + * Portions of these tests were inspired by glibc's posix/bug-getopt1.c and + * posix/tst-getopt-cancel.c + */ + +#include <common.h> +#include <getopt.h> +#include <test/lib.h> +#include <test/test.h> +#include <test/ut.h> + +static int do_test_getopt(struct unit_test_state *uts, int line, + struct getopt_state *gs, const char *optstring, + int args, char *argv[], int expected_count, + int expected[]) +{ + int opt; + + getopt_init_state(gs); + for (int i = 0; i < expected_count; i++) { + opt = getopt_silent(gs, args, argv, optstring); + if (expected[i] != opt) { + /* + * Fudge the line number so we can tell which test + * failed + */ + ut_failf(uts, __FILE__, line, __func__, + "expected[i] == getopt()", + "Expected '%c' (%d) with i=%d, got '%c' (%d)", + expected[i], expected[i], i, opt, opt); + return CMD_RET_FAILURE; + } + } + + opt = getopt_silent(gs, args, argv, optstring); + if (opt != -1) { + ut_failf(uts, __FILE__, line, __func__, + "getopt() != -1", + "Expected -1, got '%c' (%d)", opt, opt); + return CMD_RET_FAILURE; + } + + return 0; +} + +#define test_getopt(optstring, argv, expected) do { \ + int ret = do_test_getopt(uts, __LINE__, &gs, optstring, \ + ARRAY_SIZE(argv) - 1, argv, \ + ARRAY_SIZE(expected), expected); \ + if (ret) \ + return ret; \ +} while (0) + +static int lib_test_getopt(struct unit_test_state *uts) +{ + struct getopt_state gs; + + /* Happy path */ + test_getopt("ab:c", + ((char *[]){ "program", "-cb", "x", "-a", "foo", 0 }), + ((int []){ 'c', 'b', 'a' })); + ut_asserteq(4, gs.index); + + /* Make sure we pick up the optional argument */ + test_getopt("a::b:c", + ((char *[]){ "program", "-cbx", "-a", "foo", 0 }), + ((int []){ 'c', 'b', 'a' })); + ut_asserteq(4, gs.index); + + /* Test required arguments */ + test_getopt("a:b", ((char *[]){ "program", "-a", 0 }), + ((int []){ ':' })); + ut_asserteq('a', gs.opt); + test_getopt("a:b", ((char *[]){ "program", "-b", "-a", 0 }), + ((int []){ 'b', ':' })); + ut_asserteq('a', gs.opt); + + /* Test invalid arguments */ + test_getopt("ab:c", ((char *[]){ "program", "-d", 0 }), + ((int []){ '?' })); + ut_asserteq('d', gs.opt); + + /* Test arg */ + test_getopt("a::b:c", + ((char *[]){ "program", "-a", 0 }), + ((int []){ 'a' })); + ut_asserteq(2, gs.index); + ut_assertnull(gs.arg); + + test_getopt("a::b:c", + ((char *[]){ "program", "-afoo", 0 }), + ((int []){ 'a' })); + ut_asserteq(2, gs.index); + ut_assertnonnull(gs.arg); + ut_asserteq_str("foo", gs.arg); + + test_getopt("a::b:c", + ((char *[]){ "program", "-a", "foo", 0 }), + ((int []){ 'a' })); + ut_asserteq(3, gs.index); + ut_assertnonnull(gs.arg); + ut_asserteq_str("foo", gs.arg); + + test_getopt("a::b:c", + ((char *[]){ "program", "-bfoo", 0 }), + ((int []){ 'b' })); + ut_asserteq(2, gs.index); + ut_assertnonnull(gs.arg); + ut_asserteq_str("foo", gs.arg); + + test_getopt("a::b:c", + ((char *[]){ "program", "-b", "foo", 0 }), + ((int []){ 'b' })); + ut_asserteq(3, gs.index); + ut_assertnonnull(gs.arg); + ut_asserteq_str("foo", gs.arg); + + return 0; +} +LIB_TEST(lib_test_getopt, 0); diff --git a/test/log/Makefile b/test/log/Makefile index fdf5295..88bc573 100644 --- a/test/log/Makefile +++ b/test/log/Makefile @@ -3,6 +3,7 @@ # Copyright (c) 2017 Google, Inc obj-$(CONFIG_LOG_TEST) += log_test.o +obj-$(CONFIG_CMD_LOG) += log_filter.o ifdef CONFIG_UT_LOG diff --git a/test/log/log_filter.c b/test/log/log_filter.c new file mode 100644 index 0000000..e8a6e01 --- /dev/null +++ b/test/log/log_filter.c @@ -0,0 +1,108 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2020 Sean Anderson <seanga2@gmail.com> + */ + +#include <common.h> +#include <console.h> +#include <log.h> +#include <test/log.h> +#include <test/ut.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* Test invalid options */ +static int log_test_filter_invalid(struct unit_test_state *uts) +{ + ut_asserteq(1, run_command("log filter-add -AD", 0)); + ut_asserteq(1, run_command("log filter-add -l1 -L1", 0)); + ut_asserteq(1, run_command("log filter-add -l1 -L1", 0)); + ut_asserteq(1, run_command("log filter-add -lfoo", 0)); + ut_asserteq(1, run_command("log filter-add -cfoo", 0)); + ut_asserteq(1, run_command("log filter-add -ccore -ccore -ccore -ccore " + "-ccore -ccore", 0)); + + return 0; +} +LOG_TEST_FLAGS(log_test_filter_invalid, UT_TESTF_CONSOLE_REC); + +/* Test adding and removing filters */ +static int log_test_filter(struct unit_test_state *uts) +{ + bool any_found = false; + bool filt1_found = false; + bool filt2_found = false; + char cmd[32]; + struct log_filter *filt; + struct log_device *ldev; + ulong filt1, filt2; + +#define create_filter(args, filter_num) do {\ + ut_assertok(console_record_reset_enable()); \ + ut_assertok(run_command("log filter-add -p " args, 0)); \ + ut_assert_skipline(); \ + ut_assertok(strict_strtoul(uts->actual_str, 10, &(filter_num))); \ + ut_assert_console_end(); \ +} while (0) + + create_filter("", filt1); + create_filter("-DL warning -cmmc -cspi -ffile", filt2); + + ldev = log_device_find_by_name("console"); + ut_assertnonnull(ldev); + list_for_each_entry(filt, &ldev->filter_head, sibling_node) { + if (filt->filter_num == filt1) { + filt1_found = true; + ut_asserteq(0, filt->flags); + ut_asserteq(LOGL_MAX, filt->level); + ut_assertnull(filt->file_list); + } else if (filt->filter_num == filt2) { + filt2_found = true; + ut_asserteq(LOGFF_HAS_CAT | LOGFF_DENY | + LOGFF_LEVEL_MIN, filt->flags); + ut_asserteq(true, log_has_cat(filt->cat_list, + log_uc_cat(UCLASS_MMC))); + ut_asserteq(true, log_has_cat(filt->cat_list, + log_uc_cat(UCLASS_SPI))); + ut_asserteq(LOGL_WARNING, filt->level); + ut_asserteq_str("file", filt->file_list); + } + } + ut_asserteq(true, filt1_found); + ut_asserteq(true, filt2_found); + +#define remove_filter(filter_num) do { \ + ut_assertok(console_record_reset_enable()); \ + snprintf(cmd, sizeof(cmd), "log filter-remove %lu", filter_num); \ + ut_assertok(run_command(cmd, 0)); \ + ut_assert_console_end(); \ +} while (0) + + remove_filter(filt1); + remove_filter(filt2); + + filt1_found = false; + filt2_found = false; + list_for_each_entry(filt, &ldev->filter_head, sibling_node) { + if (filt->filter_num == filt1) + filt1_found = true; + else if (filt->filter_num == filt2) + filt2_found = true; + } + ut_asserteq(false, filt1_found); + ut_asserteq(false, filt2_found); + + create_filter("", filt1); + create_filter("", filt2); + + ut_assertok(console_record_reset_enable()); + ut_assertok(run_command("log filter-remove -a", 0)); + ut_assert_console_end(); + + list_for_each_entry(filt, &ldev->filter_head, sibling_node) + any_found = true; + ut_asserteq(false, any_found); + + return 0; +} +LOG_TEST_FLAGS(log_test_filter, UT_TESTF_CONSOLE_REC); diff --git a/test/log/log_test.c b/test/log/log_test.c index 6a60ff6..ea4fc6b 100644 --- a/test/log/log_test.c +++ b/test/log/log_test.c @@ -9,12 +9,17 @@ #include <common.h> #include <command.h> #include <log.h> +#include <test/log.h> +#include <test/ut.h> + +DECLARE_GLOBAL_DATA_PTR; /* emit some sample log records in different ways, for testing */ -static int log_run(enum uclass_id cat, const char *file) +static int do_log_run(int cat, const char *file) { int i; + gd->log_fmt = LOGF_TEST; debug("debug\n"); for (i = LOGL_FIRST; i < LOGL_COUNT; i++) { log(cat, i, "log %d\n", i); @@ -22,203 +27,358 @@ static int log_run(enum uclass_id cat, const char *file) i); } + gd->log_fmt = log_get_default_format(); return 0; } -static int log_test(int testnum) +#define log_run_cat(cat) do_log_run(cat, "file") +#define log_run_file(file) do_log_run(UCLASS_SPI, file) +#define log_run() do_log_run(UCLASS_SPI, "file") + +#define EXPECT_LOG BIT(0) +#define EXPECT_DIRECT BIT(1) +#define EXPECT_EXTRA BIT(2) + +static int do_check_log_entries(struct unit_test_state *uts, int flags, int min, + int max) { - int ret; + int i; - printf("test %d\n", testnum); - switch (testnum) { - case 0: { - /* Check a category filter using the first category */ - enum log_category_t cat_list[] = { - log_uc_cat(UCLASS_MMC), log_uc_cat(UCLASS_SPI), - LOGC_NONE, LOGC_END - }; - - ret = log_add_filter("console", cat_list, LOGL_MAX, NULL); - if (ret < 0) - return ret; - log_run(UCLASS_MMC, "file"); - ret = log_remove_filter("console", ret); - if (ret < 0) - return ret; - break; - } - case 1: { - /* Check a category filter using the second category */ - enum log_category_t cat_list[] = { - log_uc_cat(UCLASS_MMC), log_uc_cat(UCLASS_SPI), LOGC_END - }; - - ret = log_add_filter("console", cat_list, LOGL_MAX, NULL); - if (ret < 0) - return ret; - log_run(UCLASS_SPI, "file"); - ret = log_remove_filter("console", ret); - if (ret < 0) - return ret; - break; - } - case 2: { - /* Check a category filter that should block log entries */ - enum log_category_t cat_list[] = { - log_uc_cat(UCLASS_MMC), LOGC_NONE, LOGC_END - }; - - ret = log_add_filter("console", cat_list, LOGL_MAX, NULL); - if (ret < 0) - return ret; - log_run(UCLASS_SPI, "file"); - ret = log_remove_filter("console", ret); - if (ret < 0) - return ret; - break; - } - case 3: { - /* Check a passing file filter */ - ret = log_add_filter("console", NULL, LOGL_MAX, "file"); - if (ret < 0) - return ret; - log_run(UCLASS_SPI, "file"); - ret = log_remove_filter("console", ret); - if (ret < 0) - return ret; - break; - } - case 4: { - /* Check a failing file filter */ - ret = log_add_filter("console", NULL, LOGL_MAX, "file"); - if (ret < 0) - return ret; - log_run(UCLASS_SPI, "file2"); - ret = log_remove_filter("console", ret); - if (ret < 0) - return ret; - break; - } - case 5: { - /* Check a passing file filter (second in list) */ - ret = log_add_filter("console", NULL, LOGL_MAX, "file,file2"); - if (ret < 0) - return ret; - log_run(UCLASS_SPI, "file2"); - ret = log_remove_filter("console", ret); - if (ret < 0) - return ret; - break; - } - case 6: { - /* Check a passing file filter */ - ret = log_add_filter("console", NULL, LOGL_MAX, - "file,file2,log/log_test.c"); - if (ret < 0) - return ret; - log_run(UCLASS_SPI, "file2"); - ret = log_remove_filter("console", ret); - if (ret < 0) - return ret; - break; - } - case 7: { - /* Check a log level filter */ - ret = log_add_filter("console", NULL, LOGL_WARNING, NULL); - if (ret < 0) - return ret; - log_run(UCLASS_SPI, "file"); - ret = log_remove_filter("console", ret); - if (ret < 0) - return ret; - break; - } - case 8: { - /* Check two filters, one of which passes everything */ - int filt1, filt2; - - ret = log_add_filter("console", NULL, LOGL_WARNING, NULL); - if (ret < 0) - return ret; - filt1 = ret; - ret = log_add_filter("console", NULL, LOGL_MAX, NULL); - if (ret < 0) - return ret; - filt2 = ret; - log_run(UCLASS_SPI, "file"); - ret = log_remove_filter("console", filt1); - if (ret < 0) - return ret; - ret = log_remove_filter("console", filt2); - if (ret < 0) - return ret; - break; - } - case 9: { - /* Check three filters, which together pass everything */ - int filt1, filt2, filt3; - - ret = log_add_filter("console", NULL, LOGL_MAX, "file)"); - if (ret < 0) - return ret; - filt1 = ret; - ret = log_add_filter("console", NULL, LOGL_MAX, "file2"); - if (ret < 0) - return ret; - filt2 = ret; - ret = log_add_filter("console", NULL, LOGL_MAX, - "log/log_test.c"); - if (ret < 0) - return ret; - filt3 = ret; - log_run(UCLASS_SPI, "file2"); - ret = log_remove_filter("console", filt1); - if (ret < 0) - return ret; - ret = log_remove_filter("console", filt2); - if (ret < 0) - return ret; - ret = log_remove_filter("console", filt3); - if (ret < 0) - return ret; - break; - } - case 10: { - log_err("level %d\n", LOGL_EMERG); - log_err("level %d\n", LOGL_ALERT); - log_err("level %d\n", LOGL_CRIT); - log_err("level %d\n", LOGL_ERR); - log_warning("level %d\n", LOGL_WARNING); - log_notice("level %d\n", LOGL_NOTICE); - log_info("level %d\n", LOGL_INFO); - log_debug("level %d\n", LOGL_DEBUG); - log_content("level %d\n", LOGL_DEBUG_CONTENT); - log_io("level %d\n", LOGL_DEBUG_IO); - break; - } - case 11: - log_err("default\n"); - ret = log_device_set_enable(LOG_GET_DRIVER(console), false); - log_err("disabled\n"); - ret = log_device_set_enable(LOG_GET_DRIVER(console), true); - log_err("enabled\n"); - break; + for (i = min; i <= max; i++) { + if (flags & EXPECT_LOG) + ut_assert_nextline("do_log_run() log %d", i); + if (flags & EXPECT_DIRECT) + ut_assert_nextline("func() _log %d", i); } + if (flags & EXPECT_EXTRA) + for (; i <= LOGL_MAX ; i++) + ut_assert_nextline("func() _log %d", i); + + ut_assert_console_end(); + return 0; +} + +#define check_log_entries_flags_levels(flags, min, max) do {\ + int ret = do_check_log_entries(uts, flags, min, max); \ + if (ret) \ + return ret; \ +} while (0) + +#define check_log_entries_flags(flags) \ + check_log_entries_flags_levels(flags, LOGL_FIRST, _LOG_MAX_LEVEL) +#define check_log_entries() check_log_entries_flags(EXPECT_LOG | EXPECT_DIRECT) +#define check_log_entries_extra() \ + check_log_entries_flags(EXPECT_LOG | EXPECT_DIRECT | EXPECT_EXTRA) +#define check_log_entries_none() check_log_entries_flags(0) + +/* Check a category filter using the first category */ +int log_test_cat_allow(struct unit_test_state *uts) +{ + enum log_category_t cat_list[] = { + log_uc_cat(UCLASS_MMC), log_uc_cat(UCLASS_SPI), + LOGC_NONE, LOGC_END + }; + int filt; + + filt = log_add_filter("console", cat_list, LOGL_MAX, NULL); + ut_assert(filt >= 0); + + ut_assertok(console_record_reset_enable()); + log_run_cat(UCLASS_MMC); + check_log_entries_extra(); + + ut_assertok(console_record_reset_enable()); + log_run_cat(UCLASS_SPI); + check_log_entries_extra(); + + ut_assertok(log_remove_filter("console", filt)); + return 0; +} +LOG_TEST_FLAGS(log_test_cat_allow, UT_TESTF_CONSOLE_REC); + +/* Check a category filter that should block log entries */ +int log_test_cat_deny_implicit(struct unit_test_state *uts) +{ + enum log_category_t cat_list[] = { + log_uc_cat(UCLASS_MMC), LOGC_NONE, LOGC_END + }; + int filt; + + filt = log_add_filter("console", cat_list, LOGL_MAX, NULL); + ut_assert(filt >= 0); + + ut_assertok(console_record_reset_enable()); + log_run_cat(UCLASS_SPI); + check_log_entries_none(); + + ut_assertok(log_remove_filter("console", filt)); + return 0; +} +LOG_TEST_FLAGS(log_test_cat_deny_implicit, UT_TESTF_CONSOLE_REC); + +/* Check passing and failing file filters */ +int log_test_file(struct unit_test_state *uts) +{ + int filt; + + filt = log_add_filter("console", NULL, LOGL_MAX, "file"); + ut_assert(filt >= 0); + + ut_assertok(console_record_reset_enable()); + log_run_file("file"); + check_log_entries_flags(EXPECT_DIRECT | EXPECT_EXTRA); + + ut_assertok(console_record_reset_enable()); + log_run_file("file2"); + check_log_entries_none(); + + ut_assertok(log_remove_filter("console", filt)); + return 0; +} +LOG_TEST_FLAGS(log_test_file, UT_TESTF_CONSOLE_REC); + +/* Check a passing file filter (second in list) */ +int log_test_file_second(struct unit_test_state *uts) +{ + int filt; + + filt = log_add_filter("console", NULL, LOGL_MAX, "file,file2"); + ut_assert(filt >= 0); + + ut_assertok(console_record_reset_enable()); + log_run_file("file2"); + check_log_entries_flags(EXPECT_DIRECT | EXPECT_EXTRA); + + ut_assertok(log_remove_filter("console", filt)); + return 0; +} +LOG_TEST_FLAGS(log_test_file_second, UT_TESTF_CONSOLE_REC); + +/* Check a passing file filter (middle of list) */ +int log_test_file_mid(struct unit_test_state *uts) +{ + int filt; + + filt = log_add_filter("console", NULL, LOGL_MAX, + "file,file2,log/log_test.c"); + ut_assert(filt >= 0); + + ut_assertok(console_record_reset_enable()); + log_run_file("file2"); + check_log_entries_extra(); + + ut_assertok(log_remove_filter("console", filt)); + return 0; +} +LOG_TEST_FLAGS(log_test_file_mid, UT_TESTF_CONSOLE_REC); + +/* Check a log level filter */ +int log_test_level(struct unit_test_state *uts) +{ + int filt; + filt = log_add_filter("console", NULL, LOGL_WARNING, NULL); + ut_assert(filt >= 0); + + ut_assertok(console_record_reset_enable()); + log_run(); + check_log_entries_flags_levels(EXPECT_LOG | EXPECT_DIRECT, LOGL_FIRST, + LOGL_WARNING); + + ut_assertok(log_remove_filter("console", filt)); + return 0; +} +LOG_TEST_FLAGS(log_test_level, UT_TESTF_CONSOLE_REC); + +/* Check two filters, one of which passes everything */ +int log_test_double(struct unit_test_state *uts) +{ + int filt1, filt2; + + filt1 = log_add_filter("console", NULL, LOGL_WARNING, NULL); + ut_assert(filt1 >= 0); + filt2 = log_add_filter("console", NULL, LOGL_MAX, NULL); + ut_assert(filt2 >= 0); + + ut_assertok(console_record_reset_enable()); + log_run(); + check_log_entries_extra(); + + ut_assertok(log_remove_filter("console", filt1)); + ut_assertok(log_remove_filter("console", filt2)); + return 0; +} +LOG_TEST_FLAGS(log_test_double, UT_TESTF_CONSOLE_REC); + +/* Check three filters, which together pass everything */ +int log_test_triple(struct unit_test_state *uts) +{ + int filt1, filt2, filt3; + + filt1 = log_add_filter("console", NULL, LOGL_MAX, "file)"); + ut_assert(filt1 >= 0); + filt2 = log_add_filter("console", NULL, LOGL_MAX, "file2"); + ut_assert(filt2 >= 0); + filt3 = log_add_filter("console", NULL, LOGL_MAX, "log/log_test.c"); + ut_assert(filt3 >= 0); + + ut_assertok(console_record_reset_enable()); + log_run_file("file2"); + check_log_entries_extra(); + + ut_assertok(log_remove_filter("console", filt1)); + ut_assertok(log_remove_filter("console", filt2)); + ut_assertok(log_remove_filter("console", filt3)); + return 0; +} +LOG_TEST_FLAGS(log_test_triple, UT_TESTF_CONSOLE_REC); + +int do_log_test_helpers(struct unit_test_state *uts) +{ + int i; + + ut_assertok(console_record_reset_enable()); + log_err("level %d\n", LOGL_EMERG); + log_err("level %d\n", LOGL_ALERT); + log_err("level %d\n", LOGL_CRIT); + log_err("level %d\n", LOGL_ERR); + log_warning("level %d\n", LOGL_WARNING); + log_notice("level %d\n", LOGL_NOTICE); + log_info("level %d\n", LOGL_INFO); + log_debug("level %d\n", LOGL_DEBUG); + log_content("level %d\n", LOGL_DEBUG_CONTENT); + log_io("level %d\n", LOGL_DEBUG_IO); + + for (i = LOGL_EMERG; i <= _LOG_MAX_LEVEL; i++) + ut_assert_nextline("%s() level %d", __func__, i); + ut_assert_console_end(); + return 0; +} + +int log_test_helpers(struct unit_test_state *uts) +{ + int ret; + + gd->log_fmt = LOGF_TEST; + ret = do_log_test_helpers(uts); + gd->log_fmt = log_get_default_format(); + return ret; +} +LOG_TEST_FLAGS(log_test_helpers, UT_TESTF_CONSOLE_REC); + +int do_log_test_disable(struct unit_test_state *uts) +{ + ut_assertok(console_record_reset_enable()); + log_err("default\n"); + ut_assert_nextline("%s() default", __func__); + + ut_assertok(log_device_set_enable(LOG_GET_DRIVER(console), false)); + log_err("disabled\n"); + + ut_assertok(log_device_set_enable(LOG_GET_DRIVER(console), true)); + log_err("enabled\n"); + ut_assert_nextline("%s() enabled", __func__); + ut_assert_console_end(); return 0; } -int do_log_test(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) +int log_test_disable(struct unit_test_state *uts) { - int testnum = 0; int ret; - if (argc > 1) - testnum = simple_strtoul(argv[1], NULL, 10); + gd->log_fmt = LOGF_TEST; + ret = do_log_test_disable(uts); + gd->log_fmt = log_get_default_format(); + return ret; +} +LOG_TEST_FLAGS(log_test_disable, UT_TESTF_CONSOLE_REC); + +/* Check denying based on category */ +int log_test_cat_deny(struct unit_test_state *uts) +{ + int filt1, filt2; + enum log_category_t cat_list[] = { + log_uc_cat(UCLASS_SPI), LOGC_END + }; + + filt1 = log_add_filter("console", cat_list, LOGL_MAX, NULL); + ut_assert(filt1 >= 0); + filt2 = log_add_filter_flags("console", cat_list, LOGL_MAX, NULL, + LOGFF_DENY); + ut_assert(filt2 >= 0); + + ut_assertok(console_record_reset_enable()); + log_run_cat(UCLASS_SPI); + check_log_entries_none(); + + ut_assertok(log_remove_filter("console", filt1)); + ut_assertok(log_remove_filter("console", filt2)); + return 0; +} +LOG_TEST_FLAGS(log_test_cat_deny, UT_TESTF_CONSOLE_REC); + +/* Check denying based on file */ +int log_test_file_deny(struct unit_test_state *uts) +{ + int filt1, filt2; + + filt1 = log_add_filter("console", NULL, LOGL_MAX, "file"); + ut_assert(filt1 >= 0); + filt2 = log_add_filter_flags("console", NULL, LOGL_MAX, "file", + LOGFF_DENY); + ut_assert(filt2 >= 0); - ret = log_test(testnum); - if (ret) - printf("Test failure (err=%d)\n", ret); + ut_assertok(console_record_reset_enable()); + log_run_file("file"); + check_log_entries_none(); - return ret ? CMD_RET_FAILURE : 0; + ut_assertok(log_remove_filter("console", filt1)); + ut_assertok(log_remove_filter("console", filt2)); + return 0; +} +LOG_TEST_FLAGS(log_test_file_deny, UT_TESTF_CONSOLE_REC); + +/* Check denying based on level */ +int log_test_level_deny(struct unit_test_state *uts) +{ + int filt1, filt2; + + filt1 = log_add_filter("console", NULL, LOGL_INFO, NULL); + ut_assert(filt1 >= 0); + filt2 = log_add_filter_flags("console", NULL, LOGL_WARNING, NULL, + LOGFF_DENY); + ut_assert(filt2 >= 0); + + ut_assertok(console_record_reset_enable()); + log_run(); + check_log_entries_flags_levels(EXPECT_LOG | EXPECT_DIRECT, + LOGL_WARNING + 1, _LOG_MAX_LEVEL); + + ut_assertok(log_remove_filter("console", filt1)); + ut_assertok(log_remove_filter("console", filt2)); + return 0; +} +LOG_TEST_FLAGS(log_test_level_deny, UT_TESTF_CONSOLE_REC); + +/* Check matching based on minimum level */ +int log_test_min(struct unit_test_state *uts) +{ + int filt1, filt2; + + filt1 = log_add_filter_flags("console", NULL, LOGL_WARNING, NULL, + LOGFF_LEVEL_MIN); + ut_assert(filt1 >= 0); + filt2 = log_add_filter_flags("console", NULL, LOGL_INFO, NULL, + LOGFF_DENY | LOGFF_LEVEL_MIN); + ut_assert(filt2 >= 0); + + ut_assertok(console_record_reset_enable()); + log_run(); + check_log_entries_flags_levels(EXPECT_LOG | EXPECT_DIRECT, + LOGL_WARNING, LOGL_INFO - 1); + + ut_assertok(log_remove_filter("console", filt1)); + ut_assertok(log_remove_filter("console", filt2)); + return 0; } +LOG_TEST_FLAGS(log_test_min, UT_TESTF_CONSOLE_REC); diff --git a/test/log/syslog_test.h b/test/log/syslog_test.h index 1310257..bfaa6da 100644 --- a/test/log/syslog_test.h +++ b/test/log/syslog_test.h @@ -8,8 +8,6 @@ #ifndef __SYSLOG_TEST_H #define __SYSLOG_TEST_H -#define LOGF_TEST (BIT(LOGF_FUNC) | BIT(LOGF_MSG)) - /** * struct sb_log_env - private data for sandbox ethernet driver * diff --git a/test/py/conftest.py b/test/py/conftest.py index 3092047..dc92c0b 100644 --- a/test/py/conftest.py +++ b/test/py/conftest.py @@ -227,7 +227,7 @@ def pytest_configure(config): console = u_boot_console_exec_attach.ConsoleExecAttach(log, ubconfig) re_ut_test_list = re.compile(r'_u_boot_list_2_(.*)_test_2_\1_test_(.*)\s*$') -def generate_ut_subtest(metafunc, fixture_name): +def generate_ut_subtest(metafunc, fixture_name, sym_path): """Provide parametrization for a ut_subtest fixture. Determines the set of unit tests built into a U-Boot binary by parsing the @@ -237,12 +237,13 @@ def generate_ut_subtest(metafunc, fixture_name): Args: metafunc: The pytest test function. fixture_name: The fixture name to test. + sym_path: Relative path to the symbol file with preceding '/' + (e.g. '/u-boot.sym') Returns: Nothing. """ - - fn = console.config.build_dir + '/u-boot.sym' + fn = console.config.build_dir + sym_path try: with open(fn, 'rt') as f: lines = f.readlines() @@ -317,10 +318,12 @@ def pytest_generate_tests(metafunc): Returns: Nothing. """ - for fn in metafunc.fixturenames: if fn == 'ut_subtest': - generate_ut_subtest(metafunc, fn) + generate_ut_subtest(metafunc, fn, '/u-boot.sym') + continue + if fn == 'ut_spl_subtest': + generate_ut_subtest(metafunc, fn, '/spl/u-boot-spl.sym') continue generate_config(metafunc, fn) diff --git a/test/py/tests/test_log.py b/test/py/tests/test_log.py index 275f938..387b392 100644 --- a/test/py/tests/test_log.py +++ b/test/py/tests/test_log.py @@ -10,110 +10,6 @@ and checks that the output is correct. import pytest -LOGL_FIRST, LOGL_WARNING, LOGL_INFO = (0, 4, 6) - -@pytest.mark.buildconfigspec('cmd_log') -def test_log(u_boot_console): - """Test that U-Boot logging works correctly.""" - def check_log_entries(lines, mask, max_level=LOGL_INFO): - """Check that the expected log records appear in the output - - Args: - lines: iterator containing lines to check - mask: bit mask to select which lines to check for: - bit 0: standard log line - bit 1: _log line - max_level: maximum log level to expect in the output - """ - for i in range(max_level): - if mask & 1: - assert 'log_run() log %d' % i == next(lines) - if mask & 3: - assert 'func() _log %d' % i == next(lines) - - def run_test(testnum): - """Run a particular test number (the 'log test' command) - - Args: - testnum: Test number to run - Returns: - iterator containing the lines output from the command - """ - output = u_boot_console.run_command('log format fm') - assert output == '' - with cons.log.section('basic'): - output = u_boot_console.run_command('log test %d' % testnum) - split = output.replace('\r', '').splitlines() - lines = iter(split) - assert 'test %d' % testnum == next(lines) - return lines - - def test0(): - lines = run_test(0) - check_log_entries(lines, 3) - - def test1(): - lines = run_test(1) - check_log_entries(lines, 3) - - def test2(): - lines = run_test(2) - - def test3(): - lines = run_test(3) - check_log_entries(lines, 2) - - def test4(): - lines = run_test(4) - assert next(lines, None) == None - - def test5(): - lines = run_test(5) - check_log_entries(lines, 2) - - def test6(): - lines = run_test(6) - check_log_entries(lines, 3) - - def test7(): - lines = run_test(7) - check_log_entries(lines, 3, LOGL_WARNING) - - def test8(): - lines = run_test(8) - check_log_entries(lines, 3) - - def test9(): - lines = run_test(9) - check_log_entries(lines, 3) - - def test10(): - lines = run_test(10) - for i in range(7): - assert 'log_test() level %d' % i == next(lines) - - def test11(): - """Test use of log_device_set_enable()""" - lines = run_test(11) - assert 'log_test() default' - # disabled should not be displayed - assert 'log_test() enabled' - - # TODO(sjg@chromium.org): Consider structuring this as separate tests - cons = u_boot_console - test0() - test1() - test2() - test3() - test4() - test5() - test6() - test7() - test8() - test9() - test10() - test11() - @pytest.mark.buildconfigspec('cmd_log') def test_log_format(u_boot_console): """Test the 'log format' and 'log rec' commands""" diff --git a/test/py/tests/test_ofplatdata.py b/test/py/tests/test_ofplatdata.py index 263334b..78837a3 100644 --- a/test/py/tests/test_ofplatdata.py +++ b/test/py/tests/test_ofplatdata.py @@ -4,53 +4,6 @@ import pytest import u_boot_utils as util -OF_PLATDATA_OUTPUT = ''' -of-platdata probe: -bool 1 -byte 05 -bytearray 06 00 00 -int 1 -intarray 2 3 4 0 -longbytearray 09 0a 0b 0c 0d 0e 0f 10 11 -string message -stringarray "multi-word" "message" "" -of-platdata probe: -bool 0 -byte 08 -bytearray 01 23 34 -int 3 -intarray 5 0 0 0 -longbytearray 09 00 00 00 00 00 00 00 00 -string message2 -stringarray "another" "multi-word" "message" -of-platdata probe: -bool 0 -byte 00 -bytearray 00 00 00 -int 0 -intarray 0 0 0 0 -longbytearray 00 00 00 00 00 00 00 00 00 -string <NULL> -stringarray "one" "" "" -of-platdata probe: -bool 0 -byte 00 -bytearray 00 00 00 -int 0 -intarray 0 0 0 0 -longbytearray 00 00 00 00 00 00 00 00 00 -string <NULL> -stringarray "spl" "" "" -''' - -@pytest.mark.buildconfigspec('spl_of_platdata') -def test_ofplatdata(u_boot_console): - """Test that of-platdata can be generated and used in sandbox""" - cons = u_boot_console - cons.restart_uboot_with_flags(['--show_of_platdata']) - output = cons.get_spawn_output().replace('\r', '') - assert OF_PLATDATA_OUTPUT in output - @pytest.mark.buildconfigspec('spl_of_platdata') def test_spl_devicetree(u_boot_console): """Test content of spl device-tree""" diff --git a/test/py/tests/test_spl.py b/test/py/tests/test_spl.py new file mode 100644 index 0000000..bd273da --- /dev/null +++ b/test/py/tests/test_spl.py @@ -0,0 +1,34 @@ +# SPDX-License-Identifier: GPL-2.0 +# Copyright 2020 Google LLC +# Written by Simon Glass <sjg@chromium.org> + +import os.path +import pytest + +def test_spl(u_boot_console, ut_spl_subtest): + """Execute a "ut" subtest. + + The subtests are collected in function generate_ut_subtest() from linker + generated lists by applying a regular expression to the lines of file + spl/u-boot-spl.sym. The list entries are created using the C macro + UNIT_TEST(). + + Strict naming conventions have to be followed to match the regular + expression. Use UNIT_TEST(foo_test_bar, _flags, foo_test) for a test bar in + test suite foo that can be executed via command 'ut foo bar' and is + implemented in C function foo_test_bar(). + + Args: + u_boot_console (ConsoleBase): U-Boot console + ut_subtest (str): SPL test to be executed (e.g. 'dm platdata_phandle') + """ + try: + cons = u_boot_console + cons.restart_uboot_with_flags(['-u', '-k', ut_spl_subtest.split()[1]]) + output = cons.get_spawn_output().replace('\r', '') + assert 'Failures: 0' in output + finally: + # Restart afterward in case a non-SPL test is run next. This should not + # happen since SPL tests are run in their own invocation of test.py, but + # the cost of doing this is not too great at present. + u_boot_console.restart_uboot() @@ -28,7 +28,7 @@ fi # Run tests which require sandbox_spl run_test "sandbox_spl" ./test/py/test.py --bd sandbox_spl --build \ - -k 'test_ofplatdata or test_handoff' + -k 'test_ofplatdata or test_handoff or test_spl' if [ -z "$tools_only" ]; then # Run tests for the flat-device-tree version of sandbox. This is a special diff --git a/test/unicode_ut.c b/test/unicode_ut.c index 26d9633..33fc8b0 100644 --- a/test/unicode_ut.c +++ b/test/unicode_ut.c @@ -8,6 +8,7 @@ #include <common.h> #include <charset.h> #include <command.h> +#include <efi_loader.h> #include <errno.h> #include <log.h> #include <malloc.h> @@ -594,6 +595,24 @@ static int unicode_test_u16_strsize(struct unit_test_state *uts) } UNICODE_TEST(unicode_test_u16_strsize); +#ifdef CONFIG_EFI_LOADER +static int unicode_test_efi_create_indexed_name(struct unit_test_state *uts) +{ + u16 buf[16]; + u16 const expected[] = L"Capsule0AF9"; + u16 *pos; + + memset(buf, 0xeb, sizeof(buf)); + pos = efi_create_indexed_name(buf, "Capsule", 0x0af9); + + ut_asserteq_mem(expected, buf, sizeof(expected)); + ut_asserteq(pos - buf, u16_strnlen(buf, SIZE_MAX)); + + return 0; +} +UNICODE_TEST(unicode_test_efi_create_indexed_name); +#endif + int do_ut_unicode(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { struct unit_test *tests = ll_entry_start(struct unit_test, unicode_test); diff --git a/tools/binman/README b/tools/binman/README index fbcfdc7..de1eedf 100644 --- a/tools/binman/README +++ b/tools/binman/README @@ -278,9 +278,12 @@ offset: align: This sets the alignment of the entry. The entry offset is adjusted - so that the entry starts on an aligned boundary within the image. For - example 'align = <16>' means that the entry will start on a 16-byte - boundary. Alignment shold be a power of 2. If 'align' is not + so that the entry starts on an aligned boundary within the containing + section or image. For example 'align = <16>' means that the entry will + start on a 16-byte boundary. This may mean that padding is added before + the entry. The padding is part of the containing section but is not + included in the entry, meaning that an empty space may be created before + the entry starts. Alignment should be a power of 2. If 'align' is not provided, no alignment is performed. size: @@ -290,26 +293,40 @@ size: pad-before: Padding before the contents of the entry. Normally this is 0, meaning - that the contents start at the beginning of the entry. This can be - offset the entry contents a little. Defaults to 0. + that the contents start at the beginning of the entry. This can be used + to offset the entry contents a little. While this does not affect the + contents of the entry within binman itself (the padding is performed + only when its parent section is assembled), the end result will be that + the entry starts with the padding bytes, so may grow. Defaults to 0. pad-after: Padding after the contents of the entry. Normally this is 0, meaning that the entry ends at the last byte of content (unless adjusted by other properties). This allows room to be created in the image for - this entry to expand later. Defaults to 0. + this entry to expand later. While this does not affect the contents of + the entry within binman itself (the padding is performed only when its + parent section is assembled), the end result will be that the entry ends + with the padding bytes, so may grow. Defaults to 0. align-size: This sets the alignment of the entry size. For example, to ensure that the size of an entry is a multiple of 64 bytes, set this to 64. - If 'align-size' is not provided, no alignment is performed. + While this does not affect the contents of the entry within binman + itself (the padding is performed only when its parent section is + assembled), the end result is that the entry ends with the padding + bytes, so may grow. If 'align-size' is not provided, no alignment is + performed. align-end: - This sets the alignment of the end of an entry. Some entries require - that they end on an alignment boundary, regardless of where they - start. This does not move the start of the entry, so the contents of - the entry will still start at the beginning. But there may be padding - at the end. If 'align-end' is not provided, no alignment is performed. + This sets the alignment of the end of an entry with respect to the + containing section. Some entries require that they end on an alignment + boundary, regardless of where they start. This does not move the start + of the entry, so the contents of the entry will still start at the + beginning. But there may be padding at the end. While this does not + affect the contents of the entry within binman itself (the padding is + performed only when its parent section is assembled), the end result + is that the entry ends with the padding bytes, so may grow. + If 'align-end' is not provided, no alignment is performed. filename: For 'blob' types this provides the filename containing the binary to @@ -695,41 +712,38 @@ size of an entry. The 'current' image offset is passed in, and the function returns the offset immediately after the entry being packed. The default implementation of Pack() is usually sufficient. -6. CheckSize() - checks that the contents of all the entries fits within -the image size. If the image does not have a defined size, the size is set -large enough to hold all the entries. - -7. CheckEntries() - checks that the entries do not overlap, nor extend -outside the image. +Note: for sections, this also checks that the entries do not overlap, nor extend +outside the section. If the section does not have a defined size, the size is +set large enough to hold all the entries. -8. SetImagePos() - sets the image position of every entry. This is the absolute +6. SetImagePos() - sets the image position of every entry. This is the absolute position 'image-pos', as opposed to 'offset' which is relative to the containing section. This must be done after all offsets are known, which is why it is quite late in the ordering. -9. SetCalculatedProperties() - update any calculated properties in the device +7. SetCalculatedProperties() - update any calculated properties in the device tree. This sets the correct 'offset' and 'size' vaues, for example. -10. ProcessEntryContents() - this calls Entry.ProcessContents() on each entry. +8. ProcessEntryContents() - this calls Entry.ProcessContents() on each entry. The default implementatoin does nothing. This can be overriden to adjust the contents of an entry in some way. For example, it would be possible to create an entry containing a hash of the contents of some other entries. At this stage the offset and size of entries should not be adjusted unless absolutely necessary, since it requires a repack (going back to PackEntries()). -11. ResetForPack() - if the ProcessEntryContents() step failed, in that an entry +9. ResetForPack() - if the ProcessEntryContents() step failed, in that an entry has changed its size, then there is no alternative but to go back to step 5 and try again, repacking the entries with the updated size. ResetForPack() removes the fixed offset/size values added by binman, so that the packing can start from scratch. -12. WriteSymbols() - write the value of symbols into the U-Boot SPL binary. +10. WriteSymbols() - write the value of symbols into the U-Boot SPL binary. See 'Access to binman entry offsets at run time' below for a description of what happens in this stage. -13. BuildImage() - builds the image and writes it to a file +11. BuildImage() - builds the image and writes it to a file -14. WriteMap() - writes a text file containing a map of the image. This is the +12. WriteMap() - writes a text file containing a map of the image. This is the final step. @@ -839,6 +853,14 @@ The entry will then contain the compressed data, using the 'lz4' compression algorithm. Currently this is the only one that is supported. The uncompressed size is written to the node in an 'uncomp-size' property, if -u is used. +Compression is also supported for sections. In that case the entire section is +compressed in one block, including all its contents. This means that accessing +an entry from the section required decompressing the entire section. Also, the +size of a section indicates the space that it consumes in its parent section +(and typically the image). With compression, the section may contain more data, +and the uncomp-size property indicates that, as above. The contents of the +section is compressed first, before any padding is added. This ensures that the +padding itself is not compressed, which would be a waste of time. Map files diff --git a/tools/binman/README.entries b/tools/binman/README.entries index bdb4fd6..999b776 100644 --- a/tools/binman/README.entries +++ b/tools/binman/README.entries @@ -299,7 +299,7 @@ Entry: files: Entry containing a set of files Properties / Entry arguments: - pattern: Filename pattern to match the files to include - - compress: Compression algorithm to use: + - files-compress: Compression algorithm to use: none: No compression lz4: Use lz4 compression (via 'lz4' command-line utility) @@ -406,6 +406,10 @@ The 'default' property, if present, will be automatically set to the name if of configuration whose devicetree matches the 'default-dt' entry argument, e.g. with '-a default-dt=sun50i-a64-pine64-lts'. +Available substitutions for '@' property values are: + + DEFAULT-SEQ Sequence number of the default fdt,as provided by the + 'default-dt' entry argument Properties (in the 'fit' node itself): fit,external-offset: Indicates that the contents of the FIT are external @@ -739,6 +743,16 @@ placed at offset 'RESET_VECTOR_ADDRESS - 0xffc'. +Entry: scp: Entry containing a System Control Processor (SCP) firmware blob +--------------------------------------------------------------------------- + +Properties / Entry arguments: + - scp-path: Filename of file to read into the entry, typically scp.bin + +This entry holds firmware for an external platform-specific coprocessor. + + + Entry: section: Entry that contains other entries ------------------------------------------------- @@ -878,6 +892,15 @@ relocated to any address for execution. +Entry: u-boot-env: An entry which contains a U-Boot environment +--------------------------------------------------------------- + +Properties / Entry arguments: + - filename: File containing the environment text, with each line in the + form var=value + + + Entry: u-boot-img: U-Boot legacy image -------------------------------------- diff --git a/tools/binman/cmdline.py b/tools/binman/cmdline.py index bb4d9d1..c007d0a 100644 --- a/tools/binman/cmdline.py +++ b/tools/binman/cmdline.py @@ -37,6 +37,7 @@ controlled by a description in the board device tree.''' '3=info, 4=detail, 5=debug') subparsers = parser.add_subparsers(dest='cmd') + subparsers.required = True build_parser = subparsers.add_parser('build', help='Build firmware image') build_parser.add_argument('-a', '--entry-arg', type=str, action='append', diff --git a/tools/binman/control.py b/tools/binman/control.py index ee5771e..072417f 100644 --- a/tools/binman/control.py +++ b/tools/binman/control.py @@ -462,7 +462,7 @@ def PrepareImagesAndDtbs(dtb_fname, select_images, update_fdt): for image in images.values(): image.ExpandEntries() if update_fdt: - image.AddMissingProperties() + image.AddMissingProperties(True) image.ProcessFdt(dtb) for dtb_item in state.GetAllFdts(): @@ -513,8 +513,6 @@ def ProcessImage(image, update_fdt, write_map, get_contents=True, for pack_pass in range(passes): try: image.PackEntries() - image.CheckSize() - image.CheckEntries() except Exception as e: if write_map: fname = image.WriteMap() diff --git a/tools/binman/entry.py b/tools/binman/entry.py index f7adc3b..8946d2b 100644 --- a/tools/binman/entry.py +++ b/tools/binman/entry.py @@ -48,12 +48,22 @@ class Entry(object): uncomp_size: Size of uncompressed data in bytes, if the entry is compressed, else None contents_size: Size of contents in bytes, 0 by default - align: Entry start offset alignment, or None + align: Entry start offset alignment relative to the start of the + containing section, or None align_size: Entry size alignment, or None - align_end: Entry end offset alignment, or None - pad_before: Number of pad bytes before the contents, 0 if none - pad_after: Number of pad bytes after the contents, 0 if none - data: Contents of entry (string of bytes) + align_end: Entry end offset alignment relative to the start of the + containing section, or None + pad_before: Number of pad bytes before the contents when it is placed + in the containing section, 0 if none. The pad bytes become part of + the entry. + pad_after: Number of pad bytes after the contents when it is placed in + the containing section, 0 if none. The pad bytes become part of + the entry. + data: Contents of entry (string of bytes). This does not include + padding created by pad_before or pad_after. If the entry is + compressed, this contains the compressed data. + uncomp_data: Original uncompressed data, if this entry is compressed, + else None compress: Compression algoithm used (e.g. 'lz4'), 'none' if none orig_offset: Original offset value read from node orig_size: Original size value read from node @@ -76,6 +86,7 @@ class Entry(object): self.pre_reset_size = None self.uncomp_size = None self.data = None + self.uncomp_data = None self.contents_size = 0 self.align = None self.align_size = None @@ -180,6 +191,9 @@ class Entry(object): self.expand_size = fdt_util.GetBool(self._node, 'expand-size') self.missing_msg = fdt_util.GetString(self._node, 'missing-msg') + # This is only supported by blobs and sections at present + self.compress = fdt_util.GetString(self._node, 'compress', 'none') + def GetDefaultFilename(self): return None @@ -199,11 +213,20 @@ class Entry(object): def ExpandEntries(self): pass - def AddMissingProperties(self): - """Add new properties to the device tree as needed for this entry""" - for prop in ['offset', 'size', 'image-pos']: + def AddMissingProperties(self, have_image_pos): + """Add new properties to the device tree as needed for this entry + + Args: + have_image_pos: True if this entry has an image position. This can + be False if its parent section is compressed, since compression + groups all entries together into a compressed block of data, + obscuring the start of each individual child entry + """ + for prop in ['offset', 'size']: if not prop in self._node.props: state.AddZeroProp(self._node, prop) + if have_image_pos and 'image-pos' not in self._node.props: + state.AddZeroProp(self._node, 'image-pos') if self.GetImage().allow_repack: if self.orig_offset is not None: state.AddZeroProp(self._node, 'orig-offset', True) @@ -221,7 +244,8 @@ class Entry(object): state.SetInt(self._node, 'offset', self.offset) state.SetInt(self._node, 'size', self.size) base = self.section.GetRootSkipAtStart() if self.section else 0 - state.SetInt(self._node, 'image-pos', self.image_pos - base) + if self.image_pos is not None: + state.SetInt(self._node, 'image-pos', self.image_pos) if self.GetImage().allow_repack: if self.orig_offset is not None: state.SetInt(self._node, 'orig-offset', self.orig_offset, True) @@ -423,6 +447,12 @@ class Entry(object): return self._node.path def GetData(self): + """Get the contents of an entry + + Returns: + bytes content of the entry, excluding any padding. If the entry is + compressed, the compressed data is returned + """ self.Detail('GetData: size %s' % ToHexSize(self.data)) return self.data @@ -490,7 +520,7 @@ class Entry(object): """ pass - def CheckOffset(self): + def CheckEntries(self): """Check that the entry offsets are correct This is used for entries which have extra offset requirements (other @@ -836,3 +866,18 @@ features to produce new behaviours. list of possible tags, most desirable first """ return list(filter(None, [self.missing_msg, self.name, self.etype])) + + def CompressData(self, indata): + """Compress data according to the entry's compression method + + Args: + indata: Data to compress + + Returns: + Compressed data (first word is the compressed size) + """ + self.uncomp_data = indata + if self.compress != 'none': + self.uncomp_size = len(indata) + data = tools.Compress(indata, self.compress) + return data diff --git a/tools/binman/etype/blob.py b/tools/binman/etype/blob.py index ecfb1e4..301ac55 100644 --- a/tools/binman/etype/blob.py +++ b/tools/binman/etype/blob.py @@ -33,7 +33,6 @@ class Entry_blob(Entry): def __init__(self, section, etype, node): super().__init__(section, etype, node) self._filename = fdt_util.GetString(self._node, 'filename', self.etype) - self.compress = fdt_util.GetString(self._node, 'compress', 'none') def ObtainContents(self): self._filename = self.GetDefaultFilename() @@ -48,12 +47,6 @@ class Entry_blob(Entry): self.ReadBlobContents() return True - def CompressData(self, indata): - if self.compress != 'none': - self.uncomp_size = len(indata) - data = tools.Compress(indata, self.compress) - return data - def ReadBlobContents(self): """Read blob contents into memory diff --git a/tools/binman/etype/cbfs.py b/tools/binman/etype/cbfs.py index 650ab2c..6cdbaa0 100644 --- a/tools/binman/etype/cbfs.py +++ b/tools/binman/etype/cbfs.py @@ -237,10 +237,10 @@ class Entry_cbfs(Entry): if entry._cbfs_compress: entry.uncomp_size = cfile.memlen - def AddMissingProperties(self): - super().AddMissingProperties() + def AddMissingProperties(self, have_image_pos): + super().AddMissingProperties(have_image_pos) for entry in self._cbfs_entries.values(): - entry.AddMissingProperties() + entry.AddMissingProperties(have_image_pos) if entry._cbfs_compress: state.AddZeroProp(entry._node, 'uncomp-size') # Store the 'compress' property, since we don't look at diff --git a/tools/binman/etype/files.py b/tools/binman/etype/files.py index 9adb3af..ce3832e 100644 --- a/tools/binman/etype/files.py +++ b/tools/binman/etype/files.py @@ -19,7 +19,7 @@ class Entry_files(Entry_section): Properties / Entry arguments: - pattern: Filename pattern to match the files to include - - compress: Compression algorithm to use: + - files-compress: Compression algorithm to use: none: No compression lz4: Use lz4 compression (via 'lz4' command-line utility) @@ -36,7 +36,8 @@ class Entry_files(Entry_section): self._pattern = fdt_util.GetString(self._node, 'pattern') if not self._pattern: self.Raise("Missing 'pattern' property") - self._compress = fdt_util.GetString(self._node, 'compress', 'none') + self._files_compress = fdt_util.GetString(self._node, 'files-compress', + 'none') self._require_matches = fdt_util.GetBool(self._node, 'require-matches') @@ -53,7 +54,7 @@ class Entry_files(Entry_section): subnode = state.AddSubnode(self._node, name) state.AddString(subnode, 'type', 'blob') state.AddString(subnode, 'filename', fname) - state.AddString(subnode, 'compress', self._compress) + state.AddString(subnode, 'compress', self._files_compress) # Read entries again, now that we have some self._ReadEntries() diff --git a/tools/binman/etype/section.py b/tools/binman/etype/section.py index 515c97f..3dd5f58 100644 --- a/tools/binman/etype/section.py +++ b/tools/binman/etype/section.py @@ -16,6 +16,7 @@ from binman.entry import Entry from dtoc import fdt_util from patman import tools from patman import tout +from patman.tools import ToHexSize class Entry_section(Entry): @@ -56,7 +57,7 @@ class Entry_section(Entry): self._end_4gb = False def ReadNode(self): - """Read properties from the image node""" + """Read properties from the section node""" super().ReadNode() self._pad_byte = fdt_util.GetInt(self._node, 'pad-byte', 0) self._sort = fdt_util.GetBool(self._node, 'sort-by-offset') @@ -135,32 +136,113 @@ class Entry_section(Entry): for entry in self._entries.values(): entry.ExpandEntries() - def AddMissingProperties(self): + def AddMissingProperties(self, have_image_pos): """Add new properties to the device tree as needed for this entry""" - super().AddMissingProperties() + super().AddMissingProperties(have_image_pos) + if self.compress != 'none': + have_image_pos = False for entry in self._entries.values(): - entry.AddMissingProperties() + entry.AddMissingProperties(have_image_pos) def ObtainContents(self): return self.GetEntryContents() - def GetData(self): + def GetPaddedDataForEntry(self, entry, entry_data): + """Get the data for an entry including any padding + + Gets the entry data and uses the section pad-byte value to add padding + before and after as defined by the pad-before and pad-after properties. + This does not consider alignment. + + Args: + entry: Entry to check + + Returns: + Contents of the entry along with any pad bytes before and + after it (bytes) + """ + pad_byte = (entry._pad_byte if isinstance(entry, Entry_section) + else self._pad_byte) + + data = b'' + # Handle padding before the entry + if entry.pad_before: + data += tools.GetBytes(self._pad_byte, entry.pad_before) + + # Add in the actual entry data + data += entry_data + + # Handle padding after the entry + if entry.pad_after: + data += tools.GetBytes(self._pad_byte, entry.pad_after) + + if entry.size: + data += tools.GetBytes(pad_byte, entry.size - len(data)) + + self.Detail('GetPaddedDataForEntry: size %s' % ToHexSize(self.data)) + + return data + + def _BuildSectionData(self): + """Build the contents of a section + + This places all entries at the right place, dealing with padding before + and after entries. It does not do padding for the section itself (the + pad-before and pad-after properties in the section items) since that is + handled by the parent section. + + Returns: + Contents of the section (bytes) + """ section_data = b'' for entry in self._entries.values(): - data = entry.GetData() - base = self.pad_before + (entry.offset or 0) - self._skip_at_start - pad = base - len(section_data) + (entry.pad_before or 0) + data = self.GetPaddedDataForEntry(entry, entry.GetData()) + # Handle empty space before the entry + pad = (entry.offset or 0) - self._skip_at_start - len(section_data) if pad > 0: section_data += tools.GetBytes(self._pad_byte, pad) + + # Add in the actual entry data section_data += data - if self.size: - pad = self.size - len(section_data) - if pad > 0: - section_data += tools.GetBytes(self._pad_byte, pad) + self.Detail('GetData: %d entries, total size %#x' % (len(self._entries), len(section_data))) - return section_data + return self.CompressData(section_data) + + def GetPaddedData(self, data=None): + """Get the data for a section including any padding + + Gets the section data and uses the parent section's pad-byte value to + add padding before and after as defined by the pad-before and pad-after + properties. If this is a top-level section (i.e. an image), this is the + same as GetData(), since padding is not supported. + + This does not consider alignment. + + Returns: + Contents of the section along with any pad bytes before and + after it (bytes) + """ + section = self.section or self + if data is None: + data = self.GetData() + return section.GetPaddedDataForEntry(self, data) + + def GetData(self): + """Get the contents of an entry + + This builds the contents of the section, stores this as the contents of + the section and returns it + + Returns: + bytes content of the section, made up for all all of its subentries. + This excludes any padding. If the section is compressed, the + compressed data is returned + """ + data = self._BuildSectionData() + self.SetContents(data) + return data def GetOffsets(self): """Handle entries that want to set the offset/size of other entries @@ -180,14 +262,25 @@ class Entry_section(Entry): def Pack(self, offset): """Pack all entries into the section""" self._PackEntries() - return super().Pack(offset) + if self._sort: + self._SortEntries() + self._ExpandEntries() + + data = self._BuildSectionData() + self.SetContents(data) + + self.CheckSize() + + offset = super().Pack(offset) + self.CheckEntries() + return offset def _PackEntries(self): - """Pack all entries into the image""" + """Pack all entries into the section""" offset = self._skip_at_start for entry in self._entries.values(): offset = entry.Pack(offset) - self.size = self.CheckSize() + return offset def _ExpandEntries(self): """Expand any entries that are permitted to""" @@ -209,21 +302,22 @@ class Entry_section(Entry): self._entries[entry._node.name] = entry def CheckEntries(self): - """Check that entries do not overlap or extend outside the image""" - if self._sort: - self._SortEntries() - self._ExpandEntries() + """Check that entries do not overlap or extend outside the section""" + max_size = self.size if self.uncomp_size is None else self.uncomp_size + offset = 0 prev_name = 'None' for entry in self._entries.values(): - entry.CheckOffset() + entry.CheckEntries() if (entry.offset < self._skip_at_start or entry.offset + entry.size > self._skip_at_start + - self.size): - entry.Raise("Offset %#x (%d) is outside the section starting " - "at %#x (%d)" % - (entry.offset, entry.offset, self._skip_at_start, - self._skip_at_start)) + max_size): + entry.Raise('Offset %#x (%d) size %#x (%d) is outside the ' + "section '%s' starting at %#x (%d) " + 'of size %#x (%d)' % + (entry.offset, entry.offset, entry.size, entry.size, + self._node.path, self._skip_at_start, + self._skip_at_start, max_size, max_size)) if entry.offset < offset and entry.size: entry.Raise("Offset %#x (%d) overlaps with previous entry '%s' " "ending at %#x (%d)" % @@ -243,8 +337,9 @@ class Entry_section(Entry): def SetImagePos(self, image_pos): super().SetImagePos(image_pos) - for entry in self._entries.values(): - entry.SetImagePos(image_pos + self.offset) + if self.compress == 'none': + for entry in self._entries.values(): + entry.SetImagePos(image_pos + self.offset) def ProcessContents(self): sizes_ok_base = super(Entry_section, self).ProcessContents() @@ -254,9 +349,6 @@ class Entry_section(Entry): sizes_ok = False return sizes_ok and sizes_ok_base - def CheckOffset(self): - self.CheckEntries() - def WriteMap(self, fd, indent): """Write a map of the section to a .map file @@ -412,7 +504,7 @@ class Entry_section(Entry): return None def GetEntryContents(self): - """Call ObtainContents() for the section + """Call ObtainContents() for each entry in the section """ todo = self._entries.values() for passnum in range(3): @@ -454,18 +546,13 @@ class Entry_section(Entry): for name, info in offset_dict.items(): self._SetEntryOffsetSize(name, *info) - def CheckSize(self): - """Check that the image contents does not exceed its size, etc.""" - contents_size = 0 - for entry in self._entries.values(): - contents_size = max(contents_size, entry.offset + entry.size) - - contents_size -= self._skip_at_start + contents_size = len(self.data) size = self.size if not size: - size = self.pad_before + contents_size + self.pad_after + data = self.GetPaddedData(self.data) + size = len(data) size = tools.Align(size, self.align_size) if self.size and contents_size > self.size: diff --git a/tools/binman/etype/u_boot_ucode.py b/tools/binman/etype/u_boot_ucode.py index 4462293..b4cb8cd 100644 --- a/tools/binman/etype/u_boot_ucode.py +++ b/tools/binman/etype/u_boot_ucode.py @@ -81,6 +81,7 @@ class Entry_u_boot_ucode(Entry_blob): if fdt_entry: break if not fdt_entry: + self.data = b'' return True if not fdt_entry.ready: return False diff --git a/tools/binman/ftest.py b/tools/binman/ftest.py index 75f6ca3..e753a34 100644 --- a/tools/binman/ftest.py +++ b/tools/binman/ftest.py @@ -70,6 +70,7 @@ VBLOCK_DATA = b'vblk' FILES_DATA = (b"sorry I'm late\nOh, don't bother apologising, I'm " + b"sorry you're alive\n") COMPRESS_DATA = b'compress xxxxxxxxxxxxxxxxxxxxxx data' +COMPRESS_DATA_BIG = COMPRESS_DATA * 2 REFCODE_DATA = b'refcode' FSP_M_DATA = b'fsp_m' FSP_S_DATA = b'fsp_s' @@ -175,6 +176,7 @@ class TestFunctional(unittest.TestCase): os.path.join(cls._indir, 'files')) TestFunctional._MakeInputFile('compress', COMPRESS_DATA) + TestFunctional._MakeInputFile('compress_big', COMPRESS_DATA_BIG) TestFunctional._MakeInputFile('bl31.bin', ATF_BL31_DATA) TestFunctional._MakeInputFile('scp.bin', SCP_DATA) @@ -785,9 +787,9 @@ class TestFunctional(unittest.TestCase): def testPackExtra(self): """Test that extra packing feature works as expected""" - retcode = self._DoTestFile('009_pack_extra.dts') + data, _, _, out_dtb_fname = self._DoReadFileDtb('009_pack_extra.dts', + update_dtb=True) - self.assertEqual(0, retcode) self.assertIn('image', control.images) image = control.images['image'] entries = image.GetEntries() @@ -799,34 +801,82 @@ class TestFunctional(unittest.TestCase): self.assertEqual(0, entry.offset) self.assertEqual(3, entry.pad_before) self.assertEqual(3 + 5 + len(U_BOOT_DATA), entry.size) + self.assertEqual(U_BOOT_DATA, entry.data) + self.assertEqual(tools.GetBytes(0, 3) + U_BOOT_DATA + + tools.GetBytes(0, 5), data[:entry.size]) + pos = entry.size # Second u-boot has an aligned size, but it has no effect self.assertIn('u-boot-align-size-nop', entries) entry = entries['u-boot-align-size-nop'] - self.assertEqual(12, entry.offset) - self.assertEqual(4, entry.size) + self.assertEqual(pos, entry.offset) + self.assertEqual(len(U_BOOT_DATA), entry.size) + self.assertEqual(U_BOOT_DATA, entry.data) + self.assertEqual(U_BOOT_DATA, data[pos:pos + entry.size]) + pos += entry.size # Third u-boot has an aligned size too self.assertIn('u-boot-align-size', entries) entry = entries['u-boot-align-size'] - self.assertEqual(16, entry.offset) + self.assertEqual(pos, entry.offset) self.assertEqual(32, entry.size) + self.assertEqual(U_BOOT_DATA, entry.data) + self.assertEqual(U_BOOT_DATA + tools.GetBytes(0, 32 - len(U_BOOT_DATA)), + data[pos:pos + entry.size]) + pos += entry.size # Fourth u-boot has an aligned end self.assertIn('u-boot-align-end', entries) entry = entries['u-boot-align-end'] self.assertEqual(48, entry.offset) self.assertEqual(16, entry.size) + self.assertEqual(U_BOOT_DATA, entry.data[:len(U_BOOT_DATA)]) + self.assertEqual(U_BOOT_DATA + tools.GetBytes(0, 16 - len(U_BOOT_DATA)), + data[pos:pos + entry.size]) + pos += entry.size # Fifth u-boot immediately afterwards self.assertIn('u-boot-align-both', entries) entry = entries['u-boot-align-both'] self.assertEqual(64, entry.offset) self.assertEqual(64, entry.size) + self.assertEqual(U_BOOT_DATA, entry.data[:len(U_BOOT_DATA)]) + self.assertEqual(U_BOOT_DATA + tools.GetBytes(0, 64 - len(U_BOOT_DATA)), + data[pos:pos + entry.size]) self.CheckNoGaps(entries) self.assertEqual(128, image.size) + dtb = fdt.Fdt(out_dtb_fname) + dtb.Scan() + props = self._GetPropTree(dtb, ['size', 'offset', 'image-pos']) + expected = { + 'image-pos': 0, + 'offset': 0, + 'size': 128, + + 'u-boot:image-pos': 0, + 'u-boot:offset': 0, + 'u-boot:size': 3 + 5 + len(U_BOOT_DATA), + + 'u-boot-align-size-nop:image-pos': 12, + 'u-boot-align-size-nop:offset': 12, + 'u-boot-align-size-nop:size': 4, + + 'u-boot-align-size:image-pos': 16, + 'u-boot-align-size:offset': 16, + 'u-boot-align-size:size': 32, + + 'u-boot-align-end:image-pos': 48, + 'u-boot-align-end:offset': 48, + 'u-boot-align-end:size': 16, + + 'u-boot-align-both:image-pos': 64, + 'u-boot-align-both:offset': 64, + 'u-boot-align-both:size': 64, + } + self.assertEqual(expected, props) + def testPackAlignPowerOf2(self): """Test that invalid entry alignment is detected""" with self.assertRaises(ValueError) as e: @@ -970,8 +1020,9 @@ class TestFunctional(unittest.TestCase): """Test that the end-at-4gb property checks for offset boundaries""" with self.assertRaises(ValueError) as e: self._DoTestFile('028_pack_4gb_outside.dts') - self.assertIn("Node '/binman/u-boot': Offset 0x0 (0) is outside " - "the section starting at 0xffffffe0 (4294967264)", + self.assertIn("Node '/binman/u-boot': Offset 0x0 (0) size 0x4 (4) " + "is outside the section '/binman' starting at " + '0xffffffe0 (4294967264) of size 0x20 (32)', str(e.exception)) def testPackX86Rom(self): @@ -1761,6 +1812,20 @@ class TestFunctional(unittest.TestCase): props = self._GetPropTree(dtb, ['size', 'uncomp-size']) orig = self._decompress(data) self.assertEquals(COMPRESS_DATA, orig) + + # Do a sanity check on various fields + image = control.images['image'] + entries = image.GetEntries() + self.assertEqual(1, len(entries)) + + entry = entries['blob'] + self.assertEqual(COMPRESS_DATA, entry.uncomp_data) + self.assertEqual(len(COMPRESS_DATA), entry.uncomp_size) + orig = self._decompress(entry.data) + self.assertEqual(orig, entry.uncomp_data) + + self.assertEqual(image.data, entry.data) + expected = { 'blob:uncomp-size': len(COMPRESS_DATA), 'blob:size': len(data), @@ -1961,7 +2026,7 @@ class TestFunctional(unittest.TestCase): self.assertTrue(os.path.exists(map_fname)) map_data = tools.ReadFile(map_fname, binary=False) self.assertEqual('''ImagePos Offset Size Name -<none> 00000000 00000007 main-section +<none> 00000000 00000008 main-section <none> 00000000 00000004 u-boot <none> 00000003 00000004 u-boot-align ''', map_data) @@ -3530,12 +3595,39 @@ class TestFunctional(unittest.TestCase): def testPadInSections(self): """Test pad-before, pad-after for entries in sections""" - data = self._DoReadFile('166_pad_in_sections.dts') + data, _, _, out_dtb_fname = self._DoReadFileDtb( + '166_pad_in_sections.dts', update_dtb=True) expected = (U_BOOT_DATA + tools.GetBytes(ord('!'), 12) + U_BOOT_DATA + tools.GetBytes(ord('!'), 6) + U_BOOT_DATA) self.assertEqual(expected, data) + dtb = fdt.Fdt(out_dtb_fname) + dtb.Scan() + props = self._GetPropTree(dtb, ['size', 'image-pos', 'offset']) + expected = { + 'image-pos': 0, + 'offset': 0, + 'size': 12 + 6 + 3 * len(U_BOOT_DATA), + + 'section:image-pos': 0, + 'section:offset': 0, + 'section:size': 12 + 6 + 3 * len(U_BOOT_DATA), + + 'section/before:image-pos': 0, + 'section/before:offset': 0, + 'section/before:size': len(U_BOOT_DATA), + + 'section/u-boot:image-pos': 4, + 'section/u-boot:offset': 4, + 'section/u-boot:size': 12 + len(U_BOOT_DATA) + 6, + + 'section/after:image-pos': 26, + 'section/after:offset': 26, + 'section/after:size': len(U_BOOT_DATA), + } + self.assertEqual(expected, props) + def testFitImageSubentryAlignment(self): """Test relative alignability of FIT image subentries""" entry_args = { @@ -3737,14 +3829,14 @@ class TestFunctional(unittest.TestCase): def testEnvironmentNoSize(self): """Test that a missing 'size' property is detected""" with self.assertRaises(ValueError) as e: - data = self._DoTestFile('175_env_no_size.dts') + self._DoTestFile('175_env_no_size.dts') self.assertIn("'u-boot-env' entry must have a size property", str(e.exception)) def testEnvironmentTooSmall(self): """Test handling of an environment that does not fit""" with self.assertRaises(ValueError) as e: - data = self._DoTestFile('176_env_too_small.dts') + self._DoTestFile('176_env_too_small.dts') # checksum, start byte, environment with \0 terminator, final \0 need = 4 + 1 + len(ENV_DATA) + 1 + 1 @@ -3752,6 +3844,301 @@ class TestFunctional(unittest.TestCase): self.assertIn("too small to hold data (need %#x more bytes)" % short, str(e.exception)) + def testSkipAtStart(self): + """Test handling of skip-at-start section""" + data = self._DoReadFile('177_skip_at_start.dts') + self.assertEqual(U_BOOT_DATA, data) + + image = control.images['image'] + entries = image.GetEntries() + section = entries['section'] + self.assertEqual(0, section.offset) + self.assertEqual(len(U_BOOT_DATA), section.size) + self.assertEqual(U_BOOT_DATA, section.GetData()) + + entry = section.GetEntries()['u-boot'] + self.assertEqual(16, entry.offset) + self.assertEqual(len(U_BOOT_DATA), entry.size) + self.assertEqual(U_BOOT_DATA, entry.data) + + def testSkipAtStartPad(self): + """Test handling of skip-at-start section with padded entry""" + data = self._DoReadFile('178_skip_at_start_pad.dts') + before = tools.GetBytes(0, 8) + after = tools.GetBytes(0, 4) + all = before + U_BOOT_DATA + after + self.assertEqual(all, data) + + image = control.images['image'] + entries = image.GetEntries() + section = entries['section'] + self.assertEqual(0, section.offset) + self.assertEqual(len(all), section.size) + self.assertEqual(all, section.GetData()) + + entry = section.GetEntries()['u-boot'] + self.assertEqual(16, entry.offset) + self.assertEqual(len(all), entry.size) + self.assertEqual(U_BOOT_DATA, entry.data) + + def testSkipAtStartSectionPad(self): + """Test handling of skip-at-start section with padding""" + data = self._DoReadFile('179_skip_at_start_section_pad.dts') + before = tools.GetBytes(0, 8) + after = tools.GetBytes(0, 4) + all = before + U_BOOT_DATA + after + self.assertEqual(all, data) + + image = control.images['image'] + entries = image.GetEntries() + section = entries['section'] + self.assertEqual(0, section.offset) + self.assertEqual(len(all), section.size) + self.assertEqual(U_BOOT_DATA, section.data) + self.assertEqual(all, section.GetPaddedData()) + + entry = section.GetEntries()['u-boot'] + self.assertEqual(16, entry.offset) + self.assertEqual(len(U_BOOT_DATA), entry.size) + self.assertEqual(U_BOOT_DATA, entry.data) + + def testSectionPad(self): + """Testing padding with sections""" + data = self._DoReadFile('180_section_pad.dts') + expected = (tools.GetBytes(ord('&'), 3) + + tools.GetBytes(ord('!'), 5) + + U_BOOT_DATA + + tools.GetBytes(ord('!'), 1) + + tools.GetBytes(ord('&'), 2)) + self.assertEqual(expected, data) + + def testSectionAlign(self): + """Testing alignment with sections""" + data = self._DoReadFileDtb('181_section_align.dts', map=True)[0] + expected = (b'\0' + # fill section + tools.GetBytes(ord('&'), 1) + # padding to section align + b'\0' + # fill section + tools.GetBytes(ord('!'), 3) + # padding to u-boot align + U_BOOT_DATA + + tools.GetBytes(ord('!'), 4) + # padding to u-boot size + tools.GetBytes(ord('!'), 4)) # padding to section size + self.assertEqual(expected, data) + + def testCompressImage(self): + """Test compression of the entire image""" + self._CheckLz4() + data, _, _, out_dtb_fname = self._DoReadFileDtb( + '182_compress_image.dts', use_real_dtb=True, update_dtb=True) + dtb = fdt.Fdt(out_dtb_fname) + dtb.Scan() + props = self._GetPropTree(dtb, ['offset', 'image-pos', 'size', + 'uncomp-size']) + orig = self._decompress(data) + self.assertEquals(COMPRESS_DATA + U_BOOT_DATA, orig) + + # Do a sanity check on various fields + image = control.images['image'] + entries = image.GetEntries() + self.assertEqual(2, len(entries)) + + entry = entries['blob'] + self.assertEqual(COMPRESS_DATA, entry.data) + self.assertEqual(len(COMPRESS_DATA), entry.size) + + entry = entries['u-boot'] + self.assertEqual(U_BOOT_DATA, entry.data) + self.assertEqual(len(U_BOOT_DATA), entry.size) + + self.assertEqual(len(data), image.size) + self.assertEqual(COMPRESS_DATA + U_BOOT_DATA, image.uncomp_data) + self.assertEqual(len(COMPRESS_DATA + U_BOOT_DATA), image.uncomp_size) + orig = self._decompress(image.data) + self.assertEqual(orig, image.uncomp_data) + + expected = { + 'blob:offset': 0, + 'blob:size': len(COMPRESS_DATA), + 'u-boot:offset': len(COMPRESS_DATA), + 'u-boot:size': len(U_BOOT_DATA), + 'uncomp-size': len(COMPRESS_DATA + U_BOOT_DATA), + 'offset': 0, + 'image-pos': 0, + 'size': len(data), + } + self.assertEqual(expected, props) + + def testCompressImageLess(self): + """Test compression where compression reduces the image size""" + self._CheckLz4() + data, _, _, out_dtb_fname = self._DoReadFileDtb( + '183_compress_image_less.dts', use_real_dtb=True, update_dtb=True) + dtb = fdt.Fdt(out_dtb_fname) + dtb.Scan() + props = self._GetPropTree(dtb, ['offset', 'image-pos', 'size', + 'uncomp-size']) + orig = self._decompress(data) + + self.assertEquals(COMPRESS_DATA + COMPRESS_DATA + U_BOOT_DATA, orig) + + # Do a sanity check on various fields + image = control.images['image'] + entries = image.GetEntries() + self.assertEqual(2, len(entries)) + + entry = entries['blob'] + self.assertEqual(COMPRESS_DATA_BIG, entry.data) + self.assertEqual(len(COMPRESS_DATA_BIG), entry.size) + + entry = entries['u-boot'] + self.assertEqual(U_BOOT_DATA, entry.data) + self.assertEqual(len(U_BOOT_DATA), entry.size) + + self.assertEqual(len(data), image.size) + self.assertEqual(COMPRESS_DATA_BIG + U_BOOT_DATA, image.uncomp_data) + self.assertEqual(len(COMPRESS_DATA_BIG + U_BOOT_DATA), + image.uncomp_size) + orig = self._decompress(image.data) + self.assertEqual(orig, image.uncomp_data) + + expected = { + 'blob:offset': 0, + 'blob:size': len(COMPRESS_DATA_BIG), + 'u-boot:offset': len(COMPRESS_DATA_BIG), + 'u-boot:size': len(U_BOOT_DATA), + 'uncomp-size': len(COMPRESS_DATA_BIG + U_BOOT_DATA), + 'offset': 0, + 'image-pos': 0, + 'size': len(data), + } + self.assertEqual(expected, props) + + def testCompressSectionSize(self): + """Test compression of a section with a fixed size""" + self._CheckLz4() + data, _, _, out_dtb_fname = self._DoReadFileDtb( + '184_compress_section_size.dts', use_real_dtb=True, update_dtb=True) + dtb = fdt.Fdt(out_dtb_fname) + dtb.Scan() + props = self._GetPropTree(dtb, ['offset', 'image-pos', 'size', + 'uncomp-size']) + orig = self._decompress(data) + self.assertEquals(COMPRESS_DATA + U_BOOT_DATA, orig) + expected = { + 'section/blob:offset': 0, + 'section/blob:size': len(COMPRESS_DATA), + 'section/u-boot:offset': len(COMPRESS_DATA), + 'section/u-boot:size': len(U_BOOT_DATA), + 'section:offset': 0, + 'section:image-pos': 0, + 'section:uncomp-size': len(COMPRESS_DATA + U_BOOT_DATA), + 'section:size': 0x30, + 'offset': 0, + 'image-pos': 0, + 'size': 0x30, + } + self.assertEqual(expected, props) + + def testCompressSection(self): + """Test compression of a section with no fixed size""" + self._CheckLz4() + data, _, _, out_dtb_fname = self._DoReadFileDtb( + '185_compress_section.dts', use_real_dtb=True, update_dtb=True) + dtb = fdt.Fdt(out_dtb_fname) + dtb.Scan() + props = self._GetPropTree(dtb, ['offset', 'image-pos', 'size', + 'uncomp-size']) + orig = self._decompress(data) + self.assertEquals(COMPRESS_DATA + U_BOOT_DATA, orig) + expected = { + 'section/blob:offset': 0, + 'section/blob:size': len(COMPRESS_DATA), + 'section/u-boot:offset': len(COMPRESS_DATA), + 'section/u-boot:size': len(U_BOOT_DATA), + 'section:offset': 0, + 'section:image-pos': 0, + 'section:uncomp-size': len(COMPRESS_DATA + U_BOOT_DATA), + 'section:size': len(data), + 'offset': 0, + 'image-pos': 0, + 'size': len(data), + } + self.assertEqual(expected, props) + + def testCompressExtra(self): + """Test compression of a section with no fixed size""" + self._CheckLz4() + data, _, _, out_dtb_fname = self._DoReadFileDtb( + '186_compress_extra.dts', use_real_dtb=True, update_dtb=True) + dtb = fdt.Fdt(out_dtb_fname) + dtb.Scan() + props = self._GetPropTree(dtb, ['offset', 'image-pos', 'size', + 'uncomp-size']) + + base = data[len(U_BOOT_DATA):] + self.assertEquals(U_BOOT_DATA, base[:len(U_BOOT_DATA)]) + rest = base[len(U_BOOT_DATA):] + + # Check compressed data + section1 = self._decompress(rest) + expect1 = tools.Compress(COMPRESS_DATA + U_BOOT_DATA, 'lz4') + self.assertEquals(expect1, rest[:len(expect1)]) + self.assertEquals(COMPRESS_DATA + U_BOOT_DATA, section1) + rest1 = rest[len(expect1):] + + section2 = self._decompress(rest1) + expect2 = tools.Compress(COMPRESS_DATA + COMPRESS_DATA, 'lz4') + self.assertEquals(expect2, rest1[:len(expect2)]) + self.assertEquals(COMPRESS_DATA + COMPRESS_DATA, section2) + rest2 = rest1[len(expect2):] + + expect_size = (len(U_BOOT_DATA) + len(U_BOOT_DATA) + len(expect1) + + len(expect2) + len(U_BOOT_DATA)) + #self.assertEquals(expect_size, len(data)) + + #self.assertEquals(U_BOOT_DATA, rest2) + + self.maxDiff = None + expected = { + 'u-boot:offset': 0, + 'u-boot:image-pos': 0, + 'u-boot:size': len(U_BOOT_DATA), + + 'base:offset': len(U_BOOT_DATA), + 'base:image-pos': len(U_BOOT_DATA), + 'base:size': len(data) - len(U_BOOT_DATA), + 'base/u-boot:offset': 0, + 'base/u-boot:image-pos': len(U_BOOT_DATA), + 'base/u-boot:size': len(U_BOOT_DATA), + 'base/u-boot2:offset': len(U_BOOT_DATA) + len(expect1) + + len(expect2), + 'base/u-boot2:image-pos': len(U_BOOT_DATA) * 2 + len(expect1) + + len(expect2), + 'base/u-boot2:size': len(U_BOOT_DATA), + + 'base/section:offset': len(U_BOOT_DATA), + 'base/section:image-pos': len(U_BOOT_DATA) * 2, + 'base/section:size': len(expect1), + 'base/section:uncomp-size': len(COMPRESS_DATA + U_BOOT_DATA), + 'base/section/blob:offset': 0, + 'base/section/blob:size': len(COMPRESS_DATA), + 'base/section/u-boot:offset': len(COMPRESS_DATA), + 'base/section/u-boot:size': len(U_BOOT_DATA), + + 'base/section2:offset': len(U_BOOT_DATA) + len(expect1), + 'base/section2:image-pos': len(U_BOOT_DATA) * 2 + len(expect1), + 'base/section2:size': len(expect2), + 'base/section2:uncomp-size': len(COMPRESS_DATA + COMPRESS_DATA), + 'base/section2/blob:offset': 0, + 'base/section2/blob:size': len(COMPRESS_DATA), + 'base/section2/blob2:offset': len(COMPRESS_DATA), + 'base/section2/blob2:size': len(COMPRESS_DATA), + + 'offset': 0, + 'image-pos': 0, + 'size': len(data), + } + self.assertEqual(expected, props) + if __name__ == "__main__": unittest.main() diff --git a/tools/binman/image.py b/tools/binman/image.py index a8772c3..d65ab88 100644 --- a/tools/binman/image.py +++ b/tools/binman/image.py @@ -146,7 +146,7 @@ class Image(section.Entry_section): fname = tools.GetOutputFilename(self._filename) tout.Info("Writing image to '%s'" % fname) with open(fname, 'wb') as fd: - data = self.GetData() + data = self.GetPaddedData() fd.write(data) tout.Info("Wrote %#x bytes" % len(data)) diff --git a/tools/binman/test/009_pack_extra.dts b/tools/binman/test/009_pack_extra.dts index 0765707..1b31555 100644 --- a/tools/binman/test/009_pack_extra.dts +++ b/tools/binman/test/009_pack_extra.dts @@ -28,7 +28,7 @@ u-boot-align-both { type = "u-boot"; - align= <64>; + align = <64>; align-end = <128>; }; }; diff --git a/tools/binman/test/085_files_compress.dts b/tools/binman/test/085_files_compress.dts index 847b398..5aeead2 100644 --- a/tools/binman/test/085_files_compress.dts +++ b/tools/binman/test/085_files_compress.dts @@ -5,7 +5,7 @@ binman { files { pattern = "files/*.dat"; - compress = "lz4"; + files-compress = "lz4"; }; }; }; diff --git a/tools/binman/test/177_skip_at_start.dts b/tools/binman/test/177_skip_at_start.dts new file mode 100644 index 0000000..021460b --- /dev/null +++ b/tools/binman/test/177_skip_at_start.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ + +/dts-v1/; + +/ { + #address-cells = <1>; + #size-cells = <1>; + + binman { + section { + skip-at-start = <16>; + u-boot { + }; + }; + }; +}; diff --git a/tools/binman/test/178_skip_at_start_pad.dts b/tools/binman/test/178_skip_at_start_pad.dts new file mode 100644 index 0000000..deda3c8 --- /dev/null +++ b/tools/binman/test/178_skip_at_start_pad.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ + +/dts-v1/; + +/ { + #address-cells = <1>; + #size-cells = <1>; + + binman { + section { + skip-at-start = <16>; + u-boot { + pad-before = <8>; + pad-after = <4>; + }; + }; + }; +}; diff --git a/tools/binman/test/179_skip_at_start_section_pad.dts b/tools/binman/test/179_skip_at_start_section_pad.dts new file mode 100644 index 0000000..bf2f8f6 --- /dev/null +++ b/tools/binman/test/179_skip_at_start_section_pad.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ + +/dts-v1/; + +/ { + #address-cells = <1>; + #size-cells = <1>; + + binman { + section { + skip-at-start = <16>; + pad-before = <8>; + pad-after = <4>; + + u-boot { + }; + }; + }; +}; diff --git a/tools/binman/test/180_section_pad.dts b/tools/binman/test/180_section_pad.dts new file mode 100644 index 0000000..7e4ebf2 --- /dev/null +++ b/tools/binman/test/180_section_pad.dts @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/dts-v1/; + +/ { + #address-cells = <1>; + #size-cells = <1>; + + binman { + pad-byte = <0x26>; + section@0 { + read-only; + + /* Padding for the section uses the 0x26 pad byte */ + pad-before = <3>; + pad-after = <2>; + + /* Set the padding byte for entries, i.e. u-boot */ + pad-byte = <0x21>; + + u-boot { + pad-before = <5>; + pad-after = <1>; + }; + }; + }; +}; diff --git a/tools/binman/test/181_section_align.dts b/tools/binman/test/181_section_align.dts new file mode 100644 index 0000000..90795d1 --- /dev/null +++ b/tools/binman/test/181_section_align.dts @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/dts-v1/; + +/ { + #address-cells = <1>; + #size-cells = <1>; + + binman { + pad-byte = <0x26>; + fill { + size = <1>; + }; + section@1 { + read-only; + + /* Padding for the section uses the 0x26 pad byte */ + align = <2>; + align-size = <0x10>; + + /* Set the padding byte for entries, i.e. u-boot */ + pad-byte = <0x21>; + + fill { + size = <1>; + }; + + u-boot { + align = <4>; + align-size = <8>; + }; + }; + }; +}; diff --git a/tools/binman/test/182_compress_image.dts b/tools/binman/test/182_compress_image.dts new file mode 100644 index 0000000..4176b7f --- /dev/null +++ b/tools/binman/test/182_compress_image.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0+ +/dts-v1/; + +/ { + binman { + compress = "lz4"; + blob { + filename = "compress"; + }; + + u-boot { + }; + }; +}; diff --git a/tools/binman/test/183_compress_image_less.dts b/tools/binman/test/183_compress_image_less.dts new file mode 100644 index 0000000..1d9d57b --- /dev/null +++ b/tools/binman/test/183_compress_image_less.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0+ +/dts-v1/; + +/ { + binman { + compress = "lz4"; + blob { + filename = "compress_big"; + }; + + u-boot { + }; + }; +}; diff --git a/tools/binman/test/184_compress_section_size.dts b/tools/binman/test/184_compress_section_size.dts new file mode 100644 index 0000000..95ed30a --- /dev/null +++ b/tools/binman/test/184_compress_section_size.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ +/dts-v1/; + +/ { + binman { + section { + size = <0x30>; + compress = "lz4"; + blob { + filename = "compress"; + }; + + u-boot { + }; + }; + }; +}; diff --git a/tools/binman/test/185_compress_section.dts b/tools/binman/test/185_compress_section.dts new file mode 100644 index 0000000..dc3e340 --- /dev/null +++ b/tools/binman/test/185_compress_section.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ +/dts-v1/; + +/ { + binman { + section { + compress = "lz4"; + blob { + filename = "compress"; + }; + + u-boot { + }; + }; + }; +}; diff --git a/tools/binman/test/186_compress_extra.dts b/tools/binman/test/186_compress_extra.dts new file mode 100644 index 0000000..59aae82 --- /dev/null +++ b/tools/binman/test/186_compress_extra.dts @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: GPL-2.0+ +/dts-v1/; + +/ { + binman { + u-boot { + }; + base { + type = "section"; + u-boot { + }; + section { + compress = "lz4"; + blob { + filename = "compress"; + }; + + u-boot { + }; + }; + section2 { + type = "section"; + compress = "lz4"; + blob { + filename = "compress"; + }; + blob2 { + type = "blob"; + filename = "compress"; + }; + }; + u-boot2 { + type = "u-boot"; + }; + }; + }; +}; diff --git a/tools/dtoc/dtb_platdata.py b/tools/dtoc/dtb_platdata.py index 579a674..9b27aec 100644 --- a/tools/dtoc/dtb_platdata.py +++ b/tools/dtoc/dtb_platdata.py @@ -54,6 +54,13 @@ VAL_PREFIX = 'dtv_' # phandles is len(args). This is a list of integers. PhandleInfo = collections.namedtuple('PhandleInfo', ['max_args', 'args']) +# Holds a single phandle link, allowing a C struct value to be assigned to point +# to a device +# +# var_node: C variable to assign (e.g. 'dtv_mmc.clocks[0].node') +# dev_name: Name of device to assign to (e.g. 'clock') +PhandleLink = collections.namedtuple('PhandleLink', ['var_node', 'dev_name']) + def conv_name_to_c(name): """Convert a device-tree name to a C identifier @@ -136,7 +143,8 @@ class DtbPlatdata(object): Properties: _fdt: Fdt object, referencing the device tree _dtb_fname: Filename of the input device tree binary file - _valid_nodes: A list of Node object with compatible strings + _valid_nodes: A list of Node object with compatible strings. The list + is ordered by conv_name_to_c(node.name) _include_disabled: true to include nodes marked status = "disabled" _outfile: The current output file (sys.stdout or a real file) _warning_disabled: true to disable warnings about driver names not found @@ -146,7 +154,6 @@ class DtbPlatdata(object): key: Driver alias declared with U_BOOT_DRIVER_ALIAS(driver_alias, driver_name) value: Driver name declared with U_BOOT_DRIVER(driver_name) - _links: List of links to be included in dm_populate_phandle_data() _drivers_additional: List of additional drivers to use during scanning """ def __init__(self, dtb_fname, include_disabled, warning_disabled, @@ -160,7 +167,6 @@ class DtbPlatdata(object): self._lines = [] self._drivers = [] self._driver_aliases = {} - self._links = [] self._drivers_additional = drivers_additional def get_normalized_compat_name(self, node): @@ -359,23 +365,24 @@ class DtbPlatdata(object): """ self._fdt = fdt.FdtScan(self._dtb_fname) - def scan_node(self, root): + def scan_node(self, root, valid_nodes): """Scan a node and subnodes to build a tree of node and phandle info This adds each node to self._valid_nodes. Args: root: Root node for scan + valid_nodes: List of Node objects to add to """ for node in root.subnodes: if 'compatible' in node.props: status = node.props.get('status') if (not self._include_disabled and not status or status.value != 'disabled'): - self._valid_nodes.append(node) + valid_nodes.append(node) # recurse to handle any subnodes - self.scan_node(node) + self.scan_node(node, valid_nodes) def scan_tree(self): """Scan the device tree for useful information @@ -384,8 +391,12 @@ class DtbPlatdata(object): _valid_nodes: A list of nodes we wish to consider include in the platform data """ - self._valid_nodes = [] - return self.scan_node(self._fdt.GetRoot()) + valid_nodes = [] + self.scan_node(self._fdt.GetRoot(), valid_nodes) + self._valid_nodes = sorted(valid_nodes, + key=lambda x: conv_name_to_c(x.name)) + for idx, node in enumerate(self._valid_nodes): + node.idx = idx @staticmethod def get_num_cells(node): @@ -458,8 +469,15 @@ class DtbPlatdata(object): Once the widest property is determined, all other properties are updated to match that width. + + Returns: + dict containing structures: + key (str): Node name, as a C identifier + value: dict containing structure fields: + key (str): Field name + value: Prop object with field information """ - structs = {} + structs = collections.OrderedDict() for node in self._valid_nodes: node_name, _ = self.get_normalized_compat_name(node) fields = {} @@ -528,6 +546,14 @@ class DtbPlatdata(object): This writes out the body of a header file consisting of structure definitions for node in self._valid_nodes. See the documentation in doc/driver-model/of-plat.rst for more information. + + Args: + structs: dict containing structures: + key (str): Node name, as a C identifier + value: dict containing structure fields: + key (str): Field name + value: Prop object with field information + """ self.out_header() self.out('#include <stdbool.h>\n') @@ -560,8 +586,51 @@ class DtbPlatdata(object): Args: node: node to output """ + def _output_list(node, prop): + """Output the C code for a devicetree property that holds a list + + Args: + node (fdt.Node): Node to output + prop (fdt.Prop): Prop to output + """ + self.buf('{') + vals = [] + # For phandles, output a reference to the platform data + # of the target node. + info = self.get_phandle_argc(prop, node.name) + if info: + # Process the list as pairs of (phandle, id) + pos = 0 + item = 0 + for args in info.args: + phandle_cell = prop.value[pos] + phandle = fdt_util.fdt32_to_cpu(phandle_cell) + target_node = self._fdt.phandle_to_node[phandle] + name = conv_name_to_c(target_node.name) + arg_values = [] + for i in range(args): + arg_values.append( + str(fdt_util.fdt32_to_cpu(prop.value[pos + 1 + i]))) + pos += 1 + args + vals.append('\t{%d, {%s}}' % (target_node.idx, + ', '.join(arg_values))) + item += 1 + for val in vals: + self.buf('\n\t\t%s,' % val) + else: + for val in prop.value: + vals.append(get_value(prop.type, val)) + + # Put 8 values per line to avoid very long lines. + for i in range(0, len(vals), 8): + if i: + self.buf(',\n\t\t') + self.buf(', '.join(vals[i:i + 8])) + self.buf('}') + struct_name, _ = self.get_normalized_compat_name(node) var_name = conv_name_to_c(node.name) + self.buf('/* Node %s index %d */\n' % (node.path, node.idx)) self.buf('static struct %s%s %s%s = {\n' % (STRUCT_PREFIX, struct_name, VAL_PREFIX, var_name)) for pname in sorted(node.props): @@ -573,46 +642,7 @@ class DtbPlatdata(object): # Special handling for lists if isinstance(prop.value, list): - self.buf('{') - vals = [] - # For phandles, output a reference to the platform data - # of the target node. - info = self.get_phandle_argc(prop, node.name) - if info: - # Process the list as pairs of (phandle, id) - pos = 0 - item = 0 - for args in info.args: - phandle_cell = prop.value[pos] - phandle = fdt_util.fdt32_to_cpu(phandle_cell) - target_node = self._fdt.phandle_to_node[phandle] - name = conv_name_to_c(target_node.name) - arg_values = [] - for i in range(args): - arg_values.append(str(fdt_util.fdt32_to_cpu(prop.value[pos + 1 + i]))) - pos += 1 + args - # node member is filled with NULL as the real value - # will be update at run-time during dm_init_and_scan() - # by dm_populate_phandle_data() - vals.append('\t{NULL, {%s}}' % (', '.join(arg_values))) - var_node = '%s%s.%s[%d].node' % \ - (VAL_PREFIX, var_name, member_name, item) - # Save the the link information to be use to define - # dm_populate_phandle_data() - self._links.append({'var_node': var_node, 'dev_name': name}) - item += 1 - for val in vals: - self.buf('\n\t\t%s,' % val) - else: - for val in prop.value: - vals.append(get_value(prop.type, val)) - - # Put 8 values per line to avoid very long lines. - for i in range(0, len(vals), 8): - if i: - self.buf(',\n\t\t') - self.buf(', '.join(vals[i:i + 8])) - self.buf('}') + _output_list(node, prop) else: self.buf(get_value(prop.type, prop.value)) self.buf(',\n') @@ -623,6 +653,10 @@ class DtbPlatdata(object): self.buf('\t.name\t\t= "%s",\n' % struct_name) self.buf('\t.platdata\t= &%s%s,\n' % (VAL_PREFIX, var_name)) self.buf('\t.platdata_size\t= sizeof(%s%s),\n' % (VAL_PREFIX, var_name)) + idx = -1 + if node.parent and node.parent in self._valid_nodes: + idx = node.parent.idx + self.buf('\t.parent_idx\t= %d,\n' % idx) self.buf('};\n') self.buf('\n') @@ -639,6 +673,9 @@ class DtbPlatdata(object): information. """ self.out_header() + self.out('/* Allow use of U_BOOT_DEVICE() in this file */\n') + self.out('#define DT_PLATDATA_C\n') + self.out('\n') self.out('#include <common.h>\n') self.out('#include <dm.h>\n') self.out('#include <dt-structs.h>\n') @@ -660,9 +697,6 @@ class DtbPlatdata(object): # nodes using DM_GET_DEVICE # dtv_dmc_at_xxx.clocks[0].node = DM_GET_DEVICE(clock_controller_at_xxx) self.buf('void dm_populate_phandle_data(void) {\n') - for l in self._links: - self.buf('\t%s = DM_GET_DEVICE(%s);\n' % - (l['var_node'], l['dev_name'])) self.buf('}\n') self.out(''.join(self.get_buf())) diff --git a/tools/dtoc/dtoc_test_simple.dts b/tools/dtoc/dtoc_test_simple.dts index 11bfc4c..fd168cb 100644 --- a/tools/dtoc/dtoc_test_simple.dts +++ b/tools/dtoc/dtoc_test_simple.dts @@ -41,6 +41,7 @@ u-boot,dm-pre-reloc; compatible = "sandbox,spl-test"; stringarray = "one"; + longbytearray = [09 0a 0b 0c 0d 0e 0f 10]; }; spl-test4 { diff --git a/tools/dtoc/fdt.py b/tools/dtoc/fdt.py index d058c59..03b8677 100644 --- a/tools/dtoc/fdt.py +++ b/tools/dtoc/fdt.py @@ -129,6 +129,15 @@ class Prop: specific. """ if newprop.type < self.type: + # Special handling to convert an int into bytes + if self.type == TYPE_INT and newprop.type == TYPE_BYTE: + if type(self.value) == list: + new_value = [] + for val in self.value: + new_value += [tools.ToChar(by) for by in val] + else: + new_value = [tools.ToChar(by) for by in self.value] + self.value = new_value self.type = newprop.type if type(newprop.value) == list and type(self.value) != list: diff --git a/tools/dtoc/test_dtoc.py b/tools/dtoc/test_dtoc.py index c2ff267..a5836e0 100755 --- a/tools/dtoc/test_dtoc.py +++ b/tools/dtoc/test_dtoc.py @@ -44,6 +44,9 @@ C_HEADER = '''/* * This file was generated by dtoc from a .dtb (device tree binary) file. */ +/* Allow use of U_BOOT_DEVICE() in this file */ +#define DT_PLATDATA_C + #include <common.h> #include <dm.h> #include <dt-structs.h> @@ -209,6 +212,29 @@ struct dtd_sandbox_spl_test_2 { with open(output) as infile: data = infile.read() self._CheckStrings(C_HEADER + ''' +/* Node /i2c@0 index 0 */ +static struct dtd_sandbox_i2c_test dtv_i2c_at_0 = { +}; +U_BOOT_DEVICE(i2c_at_0) = { +\t.name\t\t= "sandbox_i2c_test", +\t.platdata\t= &dtv_i2c_at_0, +\t.platdata_size\t= sizeof(dtv_i2c_at_0), +\t.parent_idx\t= -1, +}; + +/* Node /i2c@0/pmic@9 index 1 */ +static struct dtd_sandbox_pmic_test dtv_pmic_at_9 = { +\t.low_power\t\t= true, +\t.reg\t\t\t= {0x9, 0x0}, +}; +U_BOOT_DEVICE(pmic_at_9) = { +\t.name\t\t= "sandbox_pmic_test", +\t.platdata\t= &dtv_pmic_at_9, +\t.platdata_size\t= sizeof(dtv_pmic_at_9), +\t.parent_idx\t= 0, +}; + +/* Node /spl-test index 2 */ static struct dtd_sandbox_spl_test dtv_spl_test = { \t.boolval\t\t= true, \t.bytearray\t\t= {0x6, 0x0, 0x0}, @@ -225,15 +251,17 @@ U_BOOT_DEVICE(spl_test) = { \t.name\t\t= "sandbox_spl_test", \t.platdata\t= &dtv_spl_test, \t.platdata_size\t= sizeof(dtv_spl_test), +\t.parent_idx\t= -1, }; +/* Node /spl-test2 index 3 */ static struct dtd_sandbox_spl_test dtv_spl_test2 = { \t.acpi_name\t\t= "\\\\_SB.GPO0", \t.bytearray\t\t= {0x1, 0x23, 0x34}, \t.byteval\t\t= 0x8, \t.intarray\t\t= {0x5, 0x0, 0x0, 0x0}, \t.intval\t\t\t= 0x3, -\t.longbytearray\t\t= {0x9, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, +\t.longbytearray\t\t= {0x9, 0xa, 0xb, 0xc, 0x0, 0x0, 0x0, 0x0, \t\t0x0}, \t.stringarray\t\t= {"another", "multi-word", "message"}, \t.stringval\t\t= "message2", @@ -242,41 +270,30 @@ U_BOOT_DEVICE(spl_test2) = { \t.name\t\t= "sandbox_spl_test", \t.platdata\t= &dtv_spl_test2, \t.platdata_size\t= sizeof(dtv_spl_test2), +\t.parent_idx\t= -1, }; +/* Node /spl-test3 index 4 */ static struct dtd_sandbox_spl_test dtv_spl_test3 = { +\t.longbytearray\t\t= {0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf, 0x10, +\t\t0x0}, \t.stringarray\t\t= {"one", "", ""}, }; U_BOOT_DEVICE(spl_test3) = { \t.name\t\t= "sandbox_spl_test", \t.platdata\t= &dtv_spl_test3, \t.platdata_size\t= sizeof(dtv_spl_test3), +\t.parent_idx\t= -1, }; +/* Node /spl-test4 index 5 */ static struct dtd_sandbox_spl_test_2 dtv_spl_test4 = { }; U_BOOT_DEVICE(spl_test4) = { \t.name\t\t= "sandbox_spl_test_2", \t.platdata\t= &dtv_spl_test4, \t.platdata_size\t= sizeof(dtv_spl_test4), -}; - -static struct dtd_sandbox_i2c_test dtv_i2c_at_0 = { -}; -U_BOOT_DEVICE(i2c_at_0) = { -\t.name\t\t= "sandbox_i2c_test", -\t.platdata\t= &dtv_i2c_at_0, -\t.platdata_size\t= sizeof(dtv_i2c_at_0), -}; - -static struct dtd_sandbox_pmic_test dtv_pmic_at_9 = { -\t.low_power\t\t= true, -\t.reg\t\t\t= {0x9, 0x0}, -}; -U_BOOT_DEVICE(pmic_at_9) = { -\t.name\t\t= "sandbox_pmic_test", -\t.platdata\t= &dtv_pmic_at_9, -\t.platdata_size\t= sizeof(dtv_pmic_at_9), +\t.parent_idx\t= -1, }; ''' + C_EMPTY_POPULATE_PHANDLE_DATA, data) @@ -300,6 +317,7 @@ struct dtd_sandbox_gpio { with open(output) as infile: data = infile.read() self._CheckStrings(C_HEADER + ''' +/* Node /gpios@0 index 0 */ static struct dtd_sandbox_gpio dtv_gpios_at_0 = { \t.gpio_bank_name\t\t= "a", \t.gpio_controller\t= true, @@ -309,6 +327,7 @@ U_BOOT_DEVICE(gpios_at_0) = { \t.name\t\t= "sandbox_gpio", \t.platdata\t= &dtv_gpios_at_0, \t.platdata_size\t= sizeof(dtv_gpios_at_0), +\t.parent_idx\t= -1, }; void dm_populate_phandle_data(void) { @@ -333,12 +352,14 @@ struct dtd_invalid { with open(output) as infile: data = infile.read() self._CheckStrings(C_HEADER + ''' +/* Node /spl-test index 0 */ static struct dtd_invalid dtv_spl_test = { }; U_BOOT_DEVICE(spl_test) = { \t.name\t\t= "invalid", \t.platdata\t= &dtv_spl_test, \t.platdata_size\t= sizeof(dtv_spl_test), +\t.parent_idx\t= -1, }; void dm_populate_phandle_data(void) { @@ -365,15 +386,7 @@ struct dtd_target { with open(output) as infile: data = infile.read() self._CheckStrings(C_HEADER + ''' -static struct dtd_target dtv_phandle_target = { -\t.intval\t\t\t= 0x0, -}; -U_BOOT_DEVICE(phandle_target) = { -\t.name\t\t= "target", -\t.platdata\t= &dtv_phandle_target, -\t.platdata_size\t= sizeof(dtv_phandle_target), -}; - +/* Node /phandle2-target index 0 */ static struct dtd_target dtv_phandle2_target = { \t.intval\t\t\t= 0x1, }; @@ -381,8 +394,10 @@ U_BOOT_DEVICE(phandle2_target) = { \t.name\t\t= "target", \t.platdata\t= &dtv_phandle2_target, \t.platdata_size\t= sizeof(dtv_phandle2_target), +\t.parent_idx\t= -1, }; +/* Node /phandle3-target index 1 */ static struct dtd_target dtv_phandle3_target = { \t.intval\t\t\t= 0x2, }; @@ -390,37 +405,48 @@ U_BOOT_DEVICE(phandle3_target) = { \t.name\t\t= "target", \t.platdata\t= &dtv_phandle3_target, \t.platdata_size\t= sizeof(dtv_phandle3_target), +\t.parent_idx\t= -1, +}; + +/* Node /phandle-target index 4 */ +static struct dtd_target dtv_phandle_target = { +\t.intval\t\t\t= 0x0, +}; +U_BOOT_DEVICE(phandle_target) = { +\t.name\t\t= "target", +\t.platdata\t= &dtv_phandle_target, +\t.platdata_size\t= sizeof(dtv_phandle_target), +\t.parent_idx\t= -1, }; +/* Node /phandle-source index 2 */ static struct dtd_source dtv_phandle_source = { \t.clocks\t\t\t= { -\t\t\t{NULL, {}}, -\t\t\t{NULL, {11}}, -\t\t\t{NULL, {12, 13}}, -\t\t\t{NULL, {}},}, +\t\t\t{4, {}}, +\t\t\t{0, {11}}, +\t\t\t{1, {12, 13}}, +\t\t\t{4, {}},}, }; U_BOOT_DEVICE(phandle_source) = { \t.name\t\t= "source", \t.platdata\t= &dtv_phandle_source, \t.platdata_size\t= sizeof(dtv_phandle_source), +\t.parent_idx\t= -1, }; +/* Node /phandle-source2 index 3 */ static struct dtd_source dtv_phandle_source2 = { \t.clocks\t\t\t= { -\t\t\t{NULL, {}},}, +\t\t\t{4, {}},}, }; U_BOOT_DEVICE(phandle_source2) = { \t.name\t\t= "source", \t.platdata\t= &dtv_phandle_source2, \t.platdata_size\t= sizeof(dtv_phandle_source2), +\t.parent_idx\t= -1, }; void dm_populate_phandle_data(void) { -\tdtv_phandle_source.clocks[0].node = DM_GET_DEVICE(phandle_target); -\tdtv_phandle_source.clocks[1].node = DM_GET_DEVICE(phandle2_target); -\tdtv_phandle_source.clocks[2].node = DM_GET_DEVICE(phandle3_target); -\tdtv_phandle_source.clocks[3].node = DM_GET_DEVICE(phandle_target); -\tdtv_phandle_source2.clocks[0].node = DM_GET_DEVICE(phandle_target); } ''', data) @@ -448,26 +474,29 @@ struct dtd_target { with open(output) as infile: data = infile.read() self._CheckStrings(C_HEADER + ''' +/* Node /phandle-target index 1 */ static struct dtd_target dtv_phandle_target = { }; U_BOOT_DEVICE(phandle_target) = { \t.name\t\t= "target", \t.platdata\t= &dtv_phandle_target, \t.platdata_size\t= sizeof(dtv_phandle_target), +\t.parent_idx\t= -1, }; +/* Node /phandle-source2 index 0 */ static struct dtd_source dtv_phandle_source2 = { \t.clocks\t\t\t= { -\t\t\t{NULL, {}},}, +\t\t\t{1, {}},}, }; U_BOOT_DEVICE(phandle_source2) = { \t.name\t\t= "source", \t.platdata\t= &dtv_phandle_source2, \t.platdata_size\t= sizeof(dtv_phandle_source2), +\t.parent_idx\t= -1, }; void dm_populate_phandle_data(void) { -\tdtv_phandle_source2.clocks[0].node = DM_GET_DEVICE(phandle_target); } ''', data) @@ -479,15 +508,7 @@ void dm_populate_phandle_data(void) { with open(output) as infile: data = infile.read() self._CheckStrings(C_HEADER + ''' -static struct dtd_target dtv_phandle_target = { -\t.intval\t\t\t= 0x0, -}; -U_BOOT_DEVICE(phandle_target) = { -\t.name\t\t= "target", -\t.platdata\t= &dtv_phandle_target, -\t.platdata_size\t= sizeof(dtv_phandle_target), -}; - +/* Node /phandle2-target index 0 */ static struct dtd_target dtv_phandle2_target = { \t.intval\t\t\t= 0x1, }; @@ -495,8 +516,10 @@ U_BOOT_DEVICE(phandle2_target) = { \t.name\t\t= "target", \t.platdata\t= &dtv_phandle2_target, \t.platdata_size\t= sizeof(dtv_phandle2_target), +\t.parent_idx\t= -1, }; +/* Node /phandle3-target index 1 */ static struct dtd_target dtv_phandle3_target = { \t.intval\t\t\t= 0x2, }; @@ -504,37 +527,48 @@ U_BOOT_DEVICE(phandle3_target) = { \t.name\t\t= "target", \t.platdata\t= &dtv_phandle3_target, \t.platdata_size\t= sizeof(dtv_phandle3_target), +\t.parent_idx\t= -1, +}; + +/* Node /phandle-target index 4 */ +static struct dtd_target dtv_phandle_target = { +\t.intval\t\t\t= 0x0, +}; +U_BOOT_DEVICE(phandle_target) = { +\t.name\t\t= "target", +\t.platdata\t= &dtv_phandle_target, +\t.platdata_size\t= sizeof(dtv_phandle_target), +\t.parent_idx\t= -1, }; +/* Node /phandle-source index 2 */ static struct dtd_source dtv_phandle_source = { \t.cd_gpios\t\t= { -\t\t\t{NULL, {}}, -\t\t\t{NULL, {11}}, -\t\t\t{NULL, {12, 13}}, -\t\t\t{NULL, {}},}, +\t\t\t{4, {}}, +\t\t\t{0, {11}}, +\t\t\t{1, {12, 13}}, +\t\t\t{4, {}},}, }; U_BOOT_DEVICE(phandle_source) = { \t.name\t\t= "source", \t.platdata\t= &dtv_phandle_source, \t.platdata_size\t= sizeof(dtv_phandle_source), +\t.parent_idx\t= -1, }; +/* Node /phandle-source2 index 3 */ static struct dtd_source dtv_phandle_source2 = { \t.cd_gpios\t\t= { -\t\t\t{NULL, {}},}, +\t\t\t{4, {}},}, }; U_BOOT_DEVICE(phandle_source2) = { \t.name\t\t= "source", \t.platdata\t= &dtv_phandle_source2, \t.platdata_size\t= sizeof(dtv_phandle_source2), +\t.parent_idx\t= -1, }; void dm_populate_phandle_data(void) { -\tdtv_phandle_source.cd_gpios[0].node = DM_GET_DEVICE(phandle_target); -\tdtv_phandle_source.cd_gpios[1].node = DM_GET_DEVICE(phandle2_target); -\tdtv_phandle_source.cd_gpios[2].node = DM_GET_DEVICE(phandle3_target); -\tdtv_phandle_source.cd_gpios[3].node = DM_GET_DEVICE(phandle_target); -\tdtv_phandle_source2.cd_gpios[0].node = DM_GET_DEVICE(phandle_target); } ''', data) @@ -581,6 +615,7 @@ struct dtd_test3 { with open(output) as infile: data = infile.read() self._CheckStrings(C_HEADER + ''' +/* Node /test1 index 0 */ static struct dtd_test1 dtv_test1 = { \t.reg\t\t\t= {0x1234, 0x5678}, }; @@ -588,8 +623,10 @@ U_BOOT_DEVICE(test1) = { \t.name\t\t= "test1", \t.platdata\t= &dtv_test1, \t.platdata_size\t= sizeof(dtv_test1), +\t.parent_idx\t= -1, }; +/* Node /test2 index 1 */ static struct dtd_test2 dtv_test2 = { \t.reg\t\t\t= {0x1234567890123456, 0x9876543210987654}, }; @@ -597,8 +634,10 @@ U_BOOT_DEVICE(test2) = { \t.name\t\t= "test2", \t.platdata\t= &dtv_test2, \t.platdata_size\t= sizeof(dtv_test2), +\t.parent_idx\t= -1, }; +/* Node /test3 index 2 */ static struct dtd_test3 dtv_test3 = { \t.reg\t\t\t= {0x1234567890123456, 0x9876543210987654, 0x2, 0x3}, }; @@ -606,6 +645,7 @@ U_BOOT_DEVICE(test3) = { \t.name\t\t= "test3", \t.platdata\t= &dtv_test3, \t.platdata_size\t= sizeof(dtv_test3), +\t.parent_idx\t= -1, }; ''' + C_EMPTY_POPULATE_PHANDLE_DATA, data) @@ -630,6 +670,7 @@ struct dtd_test2 { with open(output) as infile: data = infile.read() self._CheckStrings(C_HEADER + ''' +/* Node /test1 index 0 */ static struct dtd_test1 dtv_test1 = { \t.reg\t\t\t= {0x1234, 0x5678}, }; @@ -637,8 +678,10 @@ U_BOOT_DEVICE(test1) = { \t.name\t\t= "test1", \t.platdata\t= &dtv_test1, \t.platdata_size\t= sizeof(dtv_test1), +\t.parent_idx\t= -1, }; +/* Node /test2 index 1 */ static struct dtd_test2 dtv_test2 = { \t.reg\t\t\t= {0x12345678, 0x98765432, 0x2, 0x3}, }; @@ -646,6 +689,7 @@ U_BOOT_DEVICE(test2) = { \t.name\t\t= "test2", \t.platdata\t= &dtv_test2, \t.platdata_size\t= sizeof(dtv_test2), +\t.parent_idx\t= -1, }; ''' + C_EMPTY_POPULATE_PHANDLE_DATA, data) @@ -673,6 +717,7 @@ struct dtd_test3 { with open(output) as infile: data = infile.read() self._CheckStrings(C_HEADER + ''' +/* Node /test1 index 0 */ static struct dtd_test1 dtv_test1 = { \t.reg\t\t\t= {0x123400000000, 0x5678}, }; @@ -680,8 +725,10 @@ U_BOOT_DEVICE(test1) = { \t.name\t\t= "test1", \t.platdata\t= &dtv_test1, \t.platdata_size\t= sizeof(dtv_test1), +\t.parent_idx\t= -1, }; +/* Node /test2 index 1 */ static struct dtd_test2 dtv_test2 = { \t.reg\t\t\t= {0x1234567890123456, 0x98765432}, }; @@ -689,8 +736,10 @@ U_BOOT_DEVICE(test2) = { \t.name\t\t= "test2", \t.platdata\t= &dtv_test2, \t.platdata_size\t= sizeof(dtv_test2), +\t.parent_idx\t= -1, }; +/* Node /test3 index 2 */ static struct dtd_test3 dtv_test3 = { \t.reg\t\t\t= {0x1234567890123456, 0x98765432, 0x2, 0x3}, }; @@ -698,6 +747,7 @@ U_BOOT_DEVICE(test3) = { \t.name\t\t= "test3", \t.platdata\t= &dtv_test3, \t.platdata_size\t= sizeof(dtv_test3), +\t.parent_idx\t= -1, }; ''' + C_EMPTY_POPULATE_PHANDLE_DATA, data) @@ -725,6 +775,7 @@ struct dtd_test3 { with open(output) as infile: data = infile.read() self._CheckStrings(C_HEADER + ''' +/* Node /test1 index 0 */ static struct dtd_test1 dtv_test1 = { \t.reg\t\t\t= {0x1234, 0x567800000000}, }; @@ -732,8 +783,10 @@ U_BOOT_DEVICE(test1) = { \t.name\t\t= "test1", \t.platdata\t= &dtv_test1, \t.platdata_size\t= sizeof(dtv_test1), +\t.parent_idx\t= -1, }; +/* Node /test2 index 1 */ static struct dtd_test2 dtv_test2 = { \t.reg\t\t\t= {0x12345678, 0x9876543210987654}, }; @@ -741,8 +794,10 @@ U_BOOT_DEVICE(test2) = { \t.name\t\t= "test2", \t.platdata\t= &dtv_test2, \t.platdata_size\t= sizeof(dtv_test2), +\t.parent_idx\t= -1, }; +/* Node /test3 index 2 */ static struct dtd_test3 dtv_test3 = { \t.reg\t\t\t= {0x12345678, 0x9876543210987654, 0x2, 0x3}, }; @@ -750,6 +805,7 @@ U_BOOT_DEVICE(test3) = { \t.name\t\t= "test3", \t.platdata\t= &dtv_test3, \t.platdata_size\t= sizeof(dtv_test3), +\t.parent_idx\t= -1, }; ''' + C_EMPTY_POPULATE_PHANDLE_DATA, data) @@ -792,6 +848,7 @@ struct dtd_sandbox_spl_test { with open(output) as infile: data = infile.read() self._CheckStrings(C_HEADER + ''' +/* Node /spl-test index 0 */ static struct dtd_sandbox_spl_test dtv_spl_test = { \t.intval\t\t\t= 0x1, }; @@ -799,8 +856,10 @@ U_BOOT_DEVICE(spl_test) = { \t.name\t\t= "sandbox_spl_test", \t.platdata\t= &dtv_spl_test, \t.platdata_size\t= sizeof(dtv_spl_test), +\t.parent_idx\t= -1, }; +/* Node /spl-test2 index 1 */ static struct dtd_sandbox_spl_test dtv_spl_test2 = { \t.intarray\t\t= 0x5, }; @@ -808,6 +867,7 @@ U_BOOT_DEVICE(spl_test2) = { \t.name\t\t= "sandbox_spl_test", \t.platdata\t= &dtv_spl_test2, \t.platdata_size\t= sizeof(dtv_spl_test2), +\t.parent_idx\t= -1, }; ''' + C_EMPTY_POPULATE_PHANDLE_DATA, data) diff --git a/tools/dtoc/test_fdt.py b/tools/dtoc/test_fdt.py index b4f9b7f..cfe3e04 100755 --- a/tools/dtoc/test_fdt.py +++ b/tools/dtoc/test_fdt.py @@ -298,6 +298,7 @@ class TestProp(unittest.TestCase): def testWiden(self): """Test widening of values""" node2 = self.dtb.GetNode('/spl-test2') + node3 = self.dtb.GetNode('/spl-test3') prop = self.node.props['intval'] # No action @@ -316,11 +317,20 @@ class TestProp(unittest.TestCase): # byte array, it should turn into an array. prop = self.node.props['longbytearray'] prop2 = node2.props['longbytearray'] + prop3 = node3.props['longbytearray'] self.assertFalse(isinstance(prop2.value, list)) self.assertEqual(4, len(prop2.value)) + self.assertEqual(b'\x09\x0a\x0b\x0c', prop2.value) prop2.Widen(prop) self.assertTrue(isinstance(prop2.value, list)) self.assertEqual(9, len(prop2.value)) + self.assertEqual(['\x09', '\x0a', '\x0b', '\x0c', '\0', + '\0', '\0', '\0', '\0'], prop2.value) + prop3.Widen(prop) + self.assertTrue(isinstance(prop3.value, list)) + self.assertEqual(9, len(prop3.value)) + self.assertEqual(['\x09', '\x0a', '\x0b', '\x0c', '\x0d', + '\x0e', '\x0f', '\x10', '\0'], prop3.value) # Similarly for a string array prop = self.node.props['stringval'] diff --git a/tools/rkcommon.c b/tools/rkcommon.c index 61c392e..d55cd2c 100644 --- a/tools/rkcommon.c +++ b/tools/rkcommon.c @@ -221,12 +221,13 @@ bool rkcommon_need_rc4_spl(struct image_tool_params *params) static void rkcommon_set_header0(void *buf, struct image_tool_params *params) { struct header0_info *hdr = buf; + uint32_t init_boot_size; memset(buf, '\0', RK_INIT_OFFSET * RK_BLK_SIZE); - hdr->signature = RK_SIGNATURE; - hdr->disable_rc4 = !rkcommon_need_rc4_spl(params); - hdr->init_offset = RK_INIT_OFFSET; - hdr->init_size = spl_params.init_size / RK_BLK_SIZE; + hdr->signature = cpu_to_le32(RK_SIGNATURE); + hdr->disable_rc4 = cpu_to_le32(!rkcommon_need_rc4_spl(params)); + hdr->init_offset = cpu_to_le16(RK_INIT_OFFSET); + hdr->init_size = cpu_to_le16(spl_params.init_size / RK_BLK_SIZE); /* * init_boot_size needs to be set, as it is read by the BootROM @@ -237,11 +238,10 @@ static void rkcommon_set_header0(void *buf, struct image_tool_params *params) * for a more detailed explanation by Andy Yan */ if (spl_params.boot_file) - hdr->init_boot_size = - hdr->init_size + spl_params.boot_size / RK_BLK_SIZE; + init_boot_size = spl_params.init_size + spl_params.boot_size; else - hdr->init_boot_size = - hdr->init_size + RK_MAX_BOOT_SIZE / RK_BLK_SIZE; + init_boot_size = spl_params.init_size + RK_MAX_BOOT_SIZE; + hdr->init_boot_size = cpu_to_le16(init_boot_size / RK_BLK_SIZE); rc4_encode(buf, RK_BLK_SIZE, rc4_key); } @@ -294,14 +294,14 @@ static int rkcommon_parse_header(const void *buf, struct header0_info *header0, memcpy((void *)header0, buf, sizeof(struct header0_info)); rc4_encode((void *)header0, sizeof(struct header0_info), rc4_key); - if (header0->signature != RK_SIGNATURE) + if (le32_to_cpu(header0->signature) != RK_SIGNATURE) return -EPROTO; /* We don't support RC4 encoded image payloads here, yet... */ - if (header0->disable_rc4 == 0) + if (le32_to_cpu(header0->disable_rc4) == 0) return -ENOSYS; - hdr1_offset = header0->init_offset * RK_BLK_SIZE; + hdr1_offset = le16_to_cpu(header0->init_offset) * RK_BLK_SIZE; hdr1_sdmmc = (struct header1_info *)(buf + hdr1_offset); hdr1_spi = (struct header1_info *)(buf + rkcommon_offset_to_spi(hdr1_offset)); @@ -359,7 +359,7 @@ void rkcommon_print_header(const void *buf) struct header0_info header0; struct spl_info *spl_info; uint8_t image_type; - int ret, boot_size; + int ret, boot_size, init_size; ret = rkcommon_parse_header(buf, &header0, &spl_info); @@ -377,9 +377,10 @@ void rkcommon_print_header(const void *buf) printf("Image Type: Rockchip %s (%s) boot image\n", spl_info->spl_hdr, (image_type == IH_TYPE_RKSD) ? "SD/MMC" : "SPI"); - printf("Init Data Size: %d bytes\n", header0.init_size * RK_BLK_SIZE); + init_size = le16_to_cpu(header0.init_size) * RK_BLK_SIZE; + printf("Init Data Size: %d bytes\n", init_size); - boot_size = (header0.init_boot_size - header0.init_size) * RK_BLK_SIZE; + boot_size = le16_to_cpu(header0.init_boot_size) * RK_BLK_SIZE - init_size; if (boot_size != RK_MAX_BOOT_SIZE) printf("Boot Data Size: %d bytes\n", boot_size); } |