diff options
| -rw-r--r-- | arch/arm/mach-k3/am6_init.c | 26 | ||||
| -rw-r--r-- | arch/arm/mach-k3/common.c | 30 | ||||
| -rw-r--r-- | arch/arm/mach-k3/common.h | 7 | ||||
| -rw-r--r-- | arch/arm/mach-k3/j721e_init.c | 52 |
4 files changed, 115 insertions, 0 deletions
diff --git a/arch/arm/mach-k3/am6_init.c b/arch/arm/mach-k3/am6_init.c index c5da965..8d107b8 100644 --- a/arch/arm/mach-k3/am6_init.c +++ b/arch/arm/mach-k3/am6_init.c @@ -19,6 +19,26 @@ #include <linux/soc/ti/ti_sci_protocol.h> #ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_K3_LOAD_SYSFW +#ifdef CONFIG_TI_SECURE_DEVICE +struct fwl_data main_cbass_fwls[] = { + { "MMCSD1_CFG", 2057, 1 }, + { "MMCSD0_CFG", 2058, 1 }, + { "USB3SS0_SLV0", 2176, 2 }, + { "PCIE0_SLV", 2336, 8 }, + { "PCIE1_SLV", 2337, 8 }, + { "PCIE0_CFG", 2688, 1 }, + { "PCIE1_CFG", 2689, 1 }, +}, mcu_cbass_fwls[] = { + { "MCU_ARMSS0_CORE0_SLV", 1024, 1 }, + { "MCU_ARMSS0_CORE1_SLV", 1028, 1 }, + { "MCU_FSS0_S1", 1033, 8 }, + { "MCU_FSS0_S0", 1036, 8 }, + { "MCU_CPSW0", 1220, 1 }, +}; +#endif +#endif + static void mmr_unlock(u32 base, u32 partition) { /* Translate the base address */ @@ -109,6 +129,12 @@ void board_init_f(ulong dummy) * output. */ k3_sysfw_loader(preloader_console_init); + + /* Disable ROM configured firewalls right after loading sysfw */ +#ifdef CONFIG_TI_SECURE_DEVICE + remove_fwl_configs(main_cbass_fwls, ARRAY_SIZE(main_cbass_fwls)); + remove_fwl_configs(mcu_cbass_fwls, ARRAY_SIZE(mcu_cbass_fwls)); +#endif #else /* Prepare console output */ preloader_console_init(); diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c index e8b7d70..8d15290 100644 --- a/arch/arm/mach-k3/common.c +++ b/arch/arm/mach-k3/common.c @@ -269,3 +269,33 @@ void disable_linefill_optimization(void) asm("mcr p15, 0, %0, c1, c0, 1" : : "r" (actlr)); } #endif + +void remove_fwl_configs(struct fwl_data *fwl_data, size_t fwl_data_size) +{ + struct ti_sci_msg_fwl_region region; + struct ti_sci_fwl_ops *fwl_ops; + struct ti_sci_handle *ti_sci; + size_t i, j; + + ti_sci = get_ti_sci_handle(); + fwl_ops = &ti_sci->ops.fwl_ops; + for (i = 0; i < fwl_data_size; i++) { + for (j = 0; j < fwl_data[i].regions; j++) { + region.fwl_id = fwl_data[i].fwl_id; + region.region = j; + region.n_permission_regs = 3; + + fwl_ops->get_fwl_region(ti_sci, ®ion); + + if (region.control != 0) { + pr_debug("Attempting to disable firewall %5d (%25s)\n", + region.fwl_id, fwl_data[i].name); + region.control = 0; + + if (fwl_ops->set_fwl_region(ti_sci, ®ion)) + pr_err("Could not disable firewall %5d (%25s)\n", + region.fwl_id, fwl_data[i].name); + } + } + } +} diff --git a/arch/arm/mach-k3/common.h b/arch/arm/mach-k3/common.h index 35d1609..d8b34fe 100644 --- a/arch/arm/mach-k3/common.h +++ b/arch/arm/mach-k3/common.h @@ -14,6 +14,13 @@ #define REV_PG1_0 0 #define REV_PG2_0 1 +struct fwl_data { + const char *name; + u16 fwl_id; + u16 regions; +}; + void setup_k3_mpu_regions(void); int early_console_init(void); void disable_linefill_optimization(void); +void remove_fwl_configs(struct fwl_data *fwl_data, size_t fwl_data_size); diff --git a/arch/arm/mach-k3/j721e_init.c b/arch/arm/mach-k3/j721e_init.c index 8d562e4..f7f7398 100644 --- a/arch/arm/mach-k3/j721e_init.c +++ b/arch/arm/mach-k3/j721e_init.c @@ -20,6 +20,47 @@ #include <dm/pinctrl.h> #ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_K3_LOAD_SYSFW +#ifdef CONFIG_TI_SECURE_DEVICE +struct fwl_data cbass_hc_cfg0_fwls[] = { + { "PCIE0_CFG", 2560, 8 }, + { "PCIE1_CFG", 2561, 8 }, + { "USB3SS0_CORE", 2568, 4 }, + { "USB3SS1_CORE", 2570, 4 }, + { "EMMC8SS0_CFG", 2576, 4 }, + { "UFS_HCI0_CFG", 2580, 4 }, + { "SERDES0", 2584, 1 }, + { "SERDES1", 2585, 1 }, +}, cbass_hc0_fwls[] = { + { "PCIE0_HP", 2528, 24 }, + { "PCIE0_LP", 2529, 24 }, + { "PCIE1_HP", 2530, 24 }, + { "PCIE1_LP", 2531, 24 }, +}, cbass_rc_cfg0_fwls[] = { + { "EMMCSD4SS0_CFG", 2380, 4 }, +}, cbass_rc0_fwls[] = { + { "GPMC0", 2310, 8 }, +}, infra_cbass0_fwls[] = { + { "PLL_MMR0", 8, 26 }, + { "CTRL_MMR0", 9, 16 }, +}, mcu_cbass0_fwls[] = { + { "MCU_R5FSS0_CORE0", 1024, 4 }, + { "MCU_R5FSS0_CORE0_CFG", 1025, 2 }, + { "MCU_R5FSS0_CORE1", 1028, 4 }, + { "MCU_FSS0_CFG", 1032, 12 }, + { "MCU_FSS0_S1", 1033, 8 }, + { "MCU_FSS0_S0", 1036, 8 }, + { "MCU_PSROM49152X32", 1048, 1 }, + { "MCU_MSRAM128KX64", 1050, 8 }, + { "MCU_CTRL_MMR0", 1200, 8 }, + { "MCU_PLL_MMR0", 1201, 3 }, + { "MCU_CPSW0", 1220, 2 }, +}, wkup_cbass0_fwls[] = { + { "WKUP_CTRL_MMR0", 131, 16 }, +}; +#endif +#endif + static void mmr_unlock(u32 base, u32 partition) { /* Translate the base address */ @@ -114,6 +155,17 @@ void board_init_f(ulong dummy) * output. */ k3_sysfw_loader(preloader_console_init); + + /* Disable ROM configured firewalls right after loading sysfw */ +#ifdef CONFIG_TI_SECURE_DEVICE + remove_fwl_configs(cbass_hc_cfg0_fwls, ARRAY_SIZE(cbass_hc_cfg0_fwls)); + remove_fwl_configs(cbass_hc0_fwls, ARRAY_SIZE(cbass_hc0_fwls)); + remove_fwl_configs(cbass_rc_cfg0_fwls, ARRAY_SIZE(cbass_rc_cfg0_fwls)); + remove_fwl_configs(cbass_rc0_fwls, ARRAY_SIZE(cbass_rc0_fwls)); + remove_fwl_configs(infra_cbass0_fwls, ARRAY_SIZE(infra_cbass0_fwls)); + remove_fwl_configs(mcu_cbass0_fwls, ARRAY_SIZE(mcu_cbass0_fwls)); + remove_fwl_configs(wkup_cbass0_fwls, ARRAY_SIZE(wkup_cbass0_fwls)); +#endif #else /* Prepare console output */ preloader_console_init(); |