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| author | Icenowy Zheng <icenowy@aosc.io> | 2021-10-14 20:53:06 -0500 |
|---|---|---|
| committer | Andre Przywara <andre.przywara@arm.com> | 2022-04-04 23:24:17 +0100 |
| commit | 78ac2c0fd0662f021fc99e8ee066525ed115a8e2 (patch) | |
| tree | 589f7dbe91e2c1000529e315911b22214112dc40 /tools | |
| parent | 82ae151aeefed596196b6163ac23d97141931b64 (diff) | |
| download | u-boot-78ac2c0fd0662f021fc99e8ee066525ed115a8e2.zip u-boot-78ac2c0fd0662f021fc99e8ee066525ed115a8e2.tar.gz u-boot-78ac2c0fd0662f021fc99e8ee066525ed115a8e2.tar.bz2 | |
mkimage: sunxi_egon: add support for riscv
There's now a sun20i family in sunxi, which uses RISC-V CPU.
Add support for making eGON.BT0 image for RISC-V.
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Diffstat (limited to 'tools')
| -rw-r--r-- | tools/sunxi_egon.c | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/tools/sunxi_egon.c b/tools/sunxi_egon.c index 0c4540c..d45b6f5 100644 --- a/tools/sunxi_egon.c +++ b/tools/sunxi_egon.c @@ -31,6 +31,7 @@ static int egon_check_params(struct image_tool_params *params) */ switch (egon_get_arch(params)) { case IH_ARCH_ARM: + case IH_ARCH_RISCV: break; default: return EXIT_FAILURE; @@ -55,6 +56,10 @@ static int egon_verify_header(unsigned char *ptr, int image_size, if ((le32_to_cpu(header->b_instruction) & 0xff000000) != 0xea000000) return EXIT_FAILURE; break; + case IH_ARCH_RISCV: + if ((le32_to_cpu(header->b_instruction) & 0x00000fff) != 0x0000006f) + return EXIT_FAILURE; + break; default: return EXIT_FAILURE; /* Unknown architecture */ } @@ -116,6 +121,24 @@ static void egon_set_header(void *buf, struct stat *sbuf, int infd, value = 0xea000000 | (sizeof(struct boot_file_head) / 4 - 2); header->b_instruction = cpu_to_le32(value); break; + case IH_ARCH_RISCV: + /* + * Generate a RISC-V JAL instruction with rd=x0 + * (pseudo instruction J, jump without side effects). + * + * The following weird bit operation maps imm[20] + * to inst[31], imm[10:1] to inst[30:21], + * imm[11] to inst[20], imm[19:12] to inst[19:12], + * and imm[0] is dropped (because 1-byte RISC-V instruction + * is not allowed). + */ + value = 0x0000006f | + ((sizeof(struct boot_file_head) & 0x00100000) << 11) | + ((sizeof(struct boot_file_head) & 0x000007fe) << 20) | + ((sizeof(struct boot_file_head) & 0x00000800) << 9) | + ((sizeof(struct boot_file_head) & 0x000ff000) << 0); + header->b_instruction = cpu_to_le32(value); + break; } memcpy(header->magic, BOOT0_MAGIC, sizeof(header->magic)); |