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| author | Ley Foon Tan <ley.foon.tan@intel.com> | 2020-09-09 11:34:30 +0800 |
|---|---|---|
| committer | Ley Foon Tan <ley.foon.tan@intel.com> | 2020-10-09 17:53:15 +0800 |
| commit | 963e17ab466a1f317a0839912c67d488a2aac801 (patch) | |
| tree | 2a77c75b7300b410432a5925ad0aa2a442854d36 /tools | |
| parent | 98c28a79b44ef7b008091f7a5aa4f1a76e1d602b (diff) | |
| download | u-boot-963e17ab466a1f317a0839912c67d488a2aac801.zip u-boot-963e17ab466a1f317a0839912c67d488a2aac801.tar.gz u-boot-963e17ab466a1f317a0839912c67d488a2aac801.tar.bz2 | |
tools: socfpgaimage: Add check params function for Arria 10 (v1)
Add check params function for Arria 10 (header v1).
From [1] page 42, entry point offset should be 4 bytes aligned and
any value smaller than 0x14 is invalid.
Rename existing socfpgaimage_check_params() for v0.
[1]: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_soc_eds.pdf
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Diffstat (limited to 'tools')
| -rw-r--r-- | tools/socfpgaimage.c | 29 |
1 files changed, 26 insertions, 3 deletions
diff --git a/tools/socfpgaimage.c b/tools/socfpgaimage.c index 6dfd64e..f71b3d5 100644 --- a/tools/socfpgaimage.c +++ b/tools/socfpgaimage.c @@ -62,6 +62,9 @@ #define HEADER_OFFSET 0x40 #define VALIDATION_WORD 0x31305341 +/* Minimum and default entry point offset */ +#define ENTRY_POINT_OFFSET 0x14 + static uint8_t buffer_v0[0x10000]; static uint8_t buffer_v1[0x40000]; @@ -275,7 +278,7 @@ static void socfpgaimage_print_header(const void *ptr) printf("Not a sane SOCFPGA preloader\n"); } -static int socfpgaimage_check_params(struct image_tool_params *params) +static int socfpgaimage_check_params_v0(struct image_tool_params *params) { /* Not sure if we should be accepting fflags */ return (params->dflag && (params->fflag || params->lflag)) || @@ -283,6 +286,26 @@ static int socfpgaimage_check_params(struct image_tool_params *params) (params->lflag && (params->dflag || params->fflag)); } +static int socfpgaimage_check_params_v1(struct image_tool_params *params) +{ + /* + * If the entry point is specified, ensure it is >= ENTRY_POINT_OFFSET + * and it is 4 bytes aligned. + */ + if (params->eflag && (params->ep < ENTRY_POINT_OFFSET || + params->ep % 4 != 0)) { + fprintf(stderr, + "Error: Entry point must be greater than 0x%x.\n", + ENTRY_POINT_OFFSET); + return -1; + } + + /* Not sure if we should be accepting fflags */ + return (params->dflag && (params->fflag || params->lflag)) || + (params->fflag && (params->dflag || params->lflag)) || + (params->lflag && (params->dflag || params->fflag)); +} + static int socfpgaimage_check_image_types_v0(uint8_t type) { if (type == IH_TYPE_SOCFPGAIMAGE) @@ -377,7 +400,7 @@ U_BOOT_IMAGE_TYPE( "Altera SoCFPGA Cyclone V / Arria V image support", 0, /* This will be modified by vrec_header() */ (void *)buffer_v0, - socfpgaimage_check_params, + socfpgaimage_check_params_v0, socfpgaimage_verify_header, socfpgaimage_print_header, socfpgaimage_set_header_v0, @@ -392,7 +415,7 @@ U_BOOT_IMAGE_TYPE( "Altera SoCFPGA Arria10 image support", 0, /* This will be modified by vrec_header() */ (void *)buffer_v1, - socfpgaimage_check_params, + socfpgaimage_check_params_v1, socfpgaimage_verify_header, socfpgaimage_print_header, socfpgaimage_set_header_v1, |