diff options
| author | Tom Rini <trini@konsulko.com> | 2021-02-23 10:45:55 -0500 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2021-02-23 10:45:55 -0500 |
| commit | cbe607b920bc0827d8fe379ed4f5ae4e2058513e (patch) | |
| tree | b8cdbb8856766675f37bb92f27ab9c662fa647f9 /tools/jtagconsole | |
| parent | 8f7a16aac36c2a38956bd04b53cb7b94b7a70180 (diff) | |
| parent | d9aa19efa8a6c20d51b7884de0a7f8dae3f835d2 (diff) | |
| download | u-boot-WIP/23Feb2021.zip u-boot-WIP/23Feb2021.tar.gz u-boot-WIP/23Feb2021.tar.bz2 | |
Merge tag 'xilinx-for-v2021.04-rc3' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblazeWIP/23Feb2021
Xilinx changes for v2021.04-rc3
qspi:
- Support for dual/quad mode
- Fix speed handling
clk:
- Add clock enable function for zynq/zynqmp/versal
gem:
- Enable clock for Versal
- Fix error path
- Fix mdio deregistration path
fpga:
- Fix buffer alignment for ZynqMP
xilinx:
- Fix reset reason clearing in ZynqMP
- Show silicon version in SPL for Zynq/ZynqMP
- Fix DTB selection for ZynqMP
- Rename zc1275 to zcu1275 to match DT name
Diffstat (limited to 'tools/jtagconsole')
0 files changed, 0 insertions, 0 deletions