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| author | Suneel Garapati <sgarapati@marvell.com> | 2019-10-19 17:10:20 -0700 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2020-08-25 08:01:16 +0200 |
| commit | 4cf56ec07f673f99c87862dbb7e72bc077685474 (patch) | |
| tree | d40e8b752e61d666aab70f047b008e6ef30634c3 /test | |
| parent | bc30140d20d041a6ed5d52175e9953c36f8f5473 (diff) | |
| download | u-boot-4cf56ec07f673f99c87862dbb7e72bc077685474.zip u-boot-4cf56ec07f673f99c87862dbb7e72bc077685474.tar.gz u-boot-4cf56ec07f673f99c87862dbb7e72bc077685474.tar.bz2 | |
pci: pci-uclass: Add multi entry support for memory regions
Enable PCI memory regions in ranges property to be of multiple entry.
This helps to add support for SoC's like OcteonTX/TX2 where every
peripheral is on PCI bus.
Signed-off-by: Suneel Garapati <sgarapati@marvell.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Diffstat (limited to 'test')
| -rw-r--r-- | test/dm/pci.c | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/test/dm/pci.c b/test/dm/pci.c index fd66ed7..76490be 100644 --- a/test/dm/pci.c +++ b/test/dm/pci.c @@ -354,3 +354,25 @@ static int dm_test_pci_on_bus(struct unit_test_state *uts) return 0; } DM_TEST(dm_test_pci_on_bus, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT); + +/* + * Test support for multiple memory regions enabled via + * CONFIG_PCI_REGION_MULTI_ENTRY. When this feature is not enabled, + * only the last region of one type is stored. In this test-case, + * we have 2 memory regions, the first at 0x3000.0000 and the 2nd + * at 0x3100.0000. A correct test results now in BAR1 located at + * 0x3000.0000. + */ +static int dm_test_pci_region_multi(struct unit_test_state *uts) +{ + struct udevice *dev; + ulong mem_addr; + + /* Test memory BAR1 on bus#1 */ + ut_assertok(dm_pci_bus_find_bdf(PCI_BDF(1, 0x08, 0), &dev)); + mem_addr = dm_pci_read_bar32(dev, 1); + ut_asserteq(mem_addr, 0x30000000); + + return 0; +} +DM_TEST(dm_test_pci_region_multi, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT); |