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| author | Vikas Manocha <vikas.manocha@st.com> | 2014-11-21 10:34:20 -0800 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2014-12-08 09:35:44 -0500 |
| commit | 2df810717e8737b9c4a7d2a93b0100fcd7eae84f (patch) | |
| tree | 8f67fc9aab3b18c3b04de0dfea7fe436b08c4543 /test/image | |
| parent | a7deea691c5e85bdf8bc456dd41d5aadc1e49450 (diff) | |
| download | u-boot-2df810717e8737b9c4a7d2a93b0100fcd7eae84f.zip u-boot-2df810717e8737b9c4a7d2a93b0100fcd7eae84f.tar.gz u-boot-2df810717e8737b9c4a7d2a93b0100fcd7eae84f.tar.bz2 | |
serial: pl01x: fix pl011 baud rate configuration
UART_IBRD, UART_FBRD, and UART_LCR_H form a single 30-bit wide register which
is updated on a single write strobe generated by a UART_LCR_H write. So, to
internally update the content of UART_IBRD or UART_FBRD, a write to UART_LCR_H
must always be performed at the end.
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Acked-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'test/image')
0 files changed, 0 insertions, 0 deletions