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author | Tom Rini <trini@konsulko.com> | 2024-05-20 09:54:58 -0600 |
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committer | Tom Rini <trini@konsulko.com> | 2024-05-20 09:54:58 -0600 |
commit | 6bb92fcf7d2fea2314d616e5e2391a8bf2b0fdfa (patch) | |
tree | 53b9f3b37ca3b10c9642a03a61345c34d84eea48 /src/arm64/ti | |
parent | 93743d241c64bc1f7ecbf3262d1683176551e11f (diff) | |
download | u-boot-6bb92fcf7d2fea2314d616e5e2391a8bf2b0fdfa.zip u-boot-6bb92fcf7d2fea2314d616e5e2391a8bf2b0fdfa.tar.gz u-boot-6bb92fcf7d2fea2314d616e5e2391a8bf2b0fdfa.tar.bz2 |
Squashed 'dts/upstream/' changes from b35b9bd1d4ee..7e08733c96c8
7e08733c96c8 Merge tag 'v6.9-dts-raw'
ccdce3340fc5 Merge tag 'net-6.9-rc8' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
cb4ccb79bf49 dt-bindings: net: mediatek: remove wrongly added clocks and SerDes
6bd14595bb37 Merge tag 'soc-fixes-6.9-3' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
a6d12fb4ba6f Merge tag 'qcom-arm64-fixes-for-6.9-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/fixes
71c2fe626e53 Merge tag 'v6.9-rc7-dts-raw'
62d74bd1c58f Merge tag 'char-misc-6.9-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc
bdc631c5b7eb arm64: dts: mediatek: mt8183-pico6: Fix bluetooth node
9818a367c6b8 Merge tag 'sound-6.9-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound
c861ae2b0770 Merge tag 'pinctrl-v6.9-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
c9551dbd4ea4 Merge tag 'v6.9-rc6-dts-raw'
17c632b49122 Merge tag 'i2c-for-6.9-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux
a1bf8545a7b4 Merge tag 'soc-fixes-6.9-2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
d13e05c0fe9b Merge tag 'arc-6.9-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc
83b7bf1bdd47 Merge tag 'imx-fixes-6.9-2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into for-next
3a940d011934 Merge tag 'mtk-dts64-fixes-for-v6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux into for-next
6eeb1be299fc Merge tag 'at91-fixes-6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into for-next
733db5273cb7 Merge tag 'qcom-arm64-fixes-for-6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into for-next
76a235f6ef02 Merge branch 'v6.9-armsoc/dtsfixes' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into for-next
a4916498fb4a Merge tag 'at24-fixes-for-v6.9-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux into i2c/for-current
6ee8c2d34ea8 ARM: dts: imx6ull-tarragon: fix USB over-current polarity
c3ee365cb940 Merge tag 'iio-fixes-for-6.9a' of https://git.kernel.org/pub/scm/linux/kernel/git/jic23/iio into char-misc-linus
bb3b0f6bb688 Merge tag 'v6.9-rc5-dts-raw'
ca2b45c908c0 arm64: dts: imx8mp: Fix assigned-clocks for second CSI2
b91b30ccdb82 Merge tag 'tty-6.9-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty
9e347843c73f ARM: dts: microchip: at91-sama7g54_curiosity: Replace regulator-suspend-voltage with the valid property
a6e3d2cb9d6d ARM: dts: microchip: at91-sama7g5ek: Replace regulator-suspend-voltage with the valid property
01c2febb3cdb arm64: dts: qcom: sa8155p-adp: fix SDHC2 CD pin configuration
460856d18366 arm64: dts: rockchip: Fix USB interface compatible string on kobol-helios64
e91f447c8573 Merge tag 'pwm/for-6.9-rc5-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/ukleinek/linux
b362458a0941 dt-bindings: eeprom: at24: Fix ST M24C64-D compatible schema
4c77f098d193 ARC: [plat-hsdk]: Remove misplaced interrupt-cells property
bc5665bd550f dt-bindings: pwm: mediatek,pwm-disp: Document power-domains property
bdb049c4d14f Merge tag 'v6.9-rc4-dts-raw'
ea20dda12f5b Merge tag 'soc-fixes-6.9-1' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
c43f5bbe57fe arm64: dts: qcom: sc8180x: Fix ss_phy_irq for secondary USB controller
09bbdcd84ac2 arm64: dts: qcom: sm8650: Fix the msi-map entries
864783541376 arm64: dts: qcom: sm8550: Fix the msi-map entries
ddedda592d70 arm64: dts: qcom: sm8450: Fix the msi-map entries
960336e0e880 arm64: dts: qcom: sc8280xp: add missing PCIe minimum OPP
eb57b8e07fd7 arm64: dts: qcom: x1e80100: Fix the compatible for cluster idle states
64b22344a08d arm64: dts: qcom: Fix type of "wdog" IRQs for remoteprocs
3d4da9353d8a Merge tag 'drm-fixes-2024-04-12' of https://gitlab.freedesktop.org/drm/kernel
94d5ae8ffd5b Merge tag 'drm-msm-next-2024-04-11' of https://gitlab.freedesktop.org/drm/msm into drm-fixes
45ab49b70c99 LoongArch: Update dts for Loongson-2K2000 to support GMAC/GNET
e5f2765cdef5 LoongArch: Update dts for Loongson-2K2000 to support PCI-MSI
65d54f215c81 LoongArch: Update dts for Loongson-2K2000 to support ISA/LPC
05bddcf85f2c LoongArch: Update dts for Loongson-2K1000 to support ISA/LPC
e32b794a9062 arm64: dts: rockchip: regulator for sd needs to be always on for BPI-R2Pro
cf90790de0b2 dt-bindings: rockchip: grf: Add missing type to 'pcie-phy' node
ad6402eb7acc arm64: dts: rockchip: drop redundant disable-gpios in Lubancat 2
ace753017ab4 arm64: dts: rockchip: drop redundant disable-gpios in Lubancat 1
24eae3d76a2b arm64: dts: rockchip: drop redundant pcie-reset-suspend in Scarlet Dumo
6ddbc8e4f612 arm64: dts: rockchip: mark system power controller and fix typo on orangepi-5-plus
7d1e92c191e5 arm64: dts: rockchip: Designate the system power controller on QuartzPro64
b2f8ee07aa8e ASoC: dt-bindings: rt5645: add cbj sleeve gpio property
39841e784daa MAINTAINERS: mailmap: update Richard Genoud's email address
10c6631c86d1 Merge tag 'v6.9-rc3-dts-raw'
4ea847a91dd6 Merge tag 'devicetree-fixes-for-6.9-1' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux
446b3564a952 arm64: dts: mediatek: mt2712: fix validation errors
65d0eb62f0f1 arm64: dts: mediatek: mt7986: prefix BPI-R3 cooling maps with "map-"
a2ac24e9a4dc arm64: dts: mediatek: mt7986: drop invalid thermal block clock
7d65b24f6c7b arm64: dts: mediatek: mt7986: drop "#reset-cells" from Ethernet controller
6674a5ba09ef arm64: dts: mediatek: mt7986: drop invalid properties from ethsys
fb0a8e849646 dt-bindings: timer: narrow regex for unit address to hex numbers
cb1b6952348f dt-bindings: soc: fsl: narrow regex for unit address to hex numbers
27c8017d28c8 dt-bindings: remoteproc: ti,davinci: remove unstable remark
9095a10d281f dt-bindings: clock: ti: remove unstable remark
3f61301c1488 dt-bindings: clock: keystone: remove unstable remark
31b1ce263042 arm64: dts: imx8qm-ss-dma: fix can lpcg indices
743b20b5d4db arm64: dts: imx8-ss-dma: fix can lpcg indices
d8f0818c58bc arm64: dts: imx8-ss-dma: fix adc lpcg indices
2349133feee2 arm64: dts: imx8-ss-dma: fix pwm lpcg indices
a18420af419e arm64: dts: imx8-ss-dma: fix spi lpcg indices
d6d2add292ae arm64: dts: imx8-ss-conn: fix usb lpcg indices
fc19a9596662 arm64: dts: imx8-ss-lsio: fix pwm lpcg indices
64a1c4a72a08 arm64: dts: mediatek: mt7622: drop "reset-names" from thermal block
f91467bb0e7c arm64: dts: mediatek: mt7622: fix ethernet controller "compatible"
8e632e3e98df arm64: dts: mediatek: mt7622: fix IR nodename
1472eb8a5653 arm64: dts: mediatek: mt7622: fix clock controllers
5802f95e74db arm64: dts: mediatek: mt8186-corsola: Update min voltage constraint for Vgpu
6cb73d686d58 arm64: dts: mediatek: mt8183-kukui: Use default min voltage for MT6358
cd3a14e0479e arm64: dts: mediatek: mt8195-cherry: Update min voltage constraint for MT6315
2814659a8a80 arm64: dts: mediatek: mt8192-asurada: Update min voltage constraint for MT6315
3ea180fa00c5 arm64: dts: mediatek: cherry: Describe CPU supplies
c452106eb835 arm64: dts: mediatek: mt8195: Add missing gce-client-reg to mutex1
5893bd804364 arm64: dts: mediatek: mt8195: Add missing gce-client-reg to mutex
ad1660ce46c3 arm64: dts: mediatek: mt8195: Add missing gce-client-reg to vpp/vdosys
744724419d4c arm64: dts: mediatek: mt8192: Add missing gce-client-reg to mutex
902cad91425f arm64: dts: mediatek: mt8183: Add power-domains properity to mfgcfg
7b49bc388147 ARM: dts: imx7s-warp: Pass OV2680 link-frequencies
bd5623d08b6c ARM: dts: imx7-mba7: Use 'no-mmc' property
51b8028c7925 arm64: dts: imx8-ss-conn: fix usdhc wrong lpcg clock order
6beeed742637 dt-bindings: display/msm: sm8150-mdss: add DP node
954f369b81da ARC: Fix typos
3d2c4d764916 arm64: dts: rockchip: drop panel port unit address in GRU Scarlet
fa6ab1a0c8a1 arm64: dts: rockchip: Remove unsupported node from the Pinebook Pro dts
7f80622495d4 arm64: dts: qcom: sc7180-trogdor: mark bluetooth address as broken
92953647265f dt-bindings: bluetooth: add 'qcom,local-bd-address-broken'
6421f94d75f4 arm64: dts: freescale: imx8mp-venice-gw73xx-2x: fix USB vbus regulator
4bb321df9164 arm64: dts: freescale: imx8mp-venice-gw72xx-2x: fix USB vbus regulator
f37161a9cf0c dt-bindings: ufs: qcom: document SM6125 UFS
b2a26b71ae7d dt-bindings: ufs: qcom: document SC7180 UFS
1cb1e2605d33 dt-bindings: ufs: qcom: document SC8180X UFS
6bd77a407d2e dt-bindings: pinctrl: renesas,rzg2l-pinctrl: Allow 'input' and 'output-enable' properties
2639a0e2fdbd Merge tag 'v6.9-rc1-dts-raw'
15eca7b21493 docs: dt-bindings: add missing address/size-cells to example
9ace491cae40 arm64: dts: rockchip: Fix the i2c address of es8316 on Cool Pi CM5
d8bdab44b3fe arm64: dts: rockchip: add regulators for PCIe on RK3399 Puma Haikou
1331876fe9c8 arm64: dts: rockchip: enable internal pull-up on PCIE_WAKE# for RK3399 Puma
57878497676a arm64: dts: rockchip: enable internal pull-up on Q7_USB_ID for RK3399 Puma
a9686a9d2878 arm64: dts: rockchip: fix alphabetical ordering RK3399 puma
6125abd98f94 arm64: dts: rockchip: enable internal pull-up for Q7_THRM# on RK3399 Puma
e51b8871e6a8 arm64: dts: rockchip: set PHY address of MT7531 switch to 0x1f
8c7a1135d13d dt-bindings: iio: health: maxim,max30102: fix compatible check
7eea89692b5a Merge tag 'timers-core-2024-03-23' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
665795c05a77 Merge tag 'riscv-for-linus-6.9-mw2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux
9497bb8a116e Merge tag 'spi-fix-v6.9-merge-window' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi
6aef9b1ef737 Merge tag 'sound-fix2-6.9-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound
17cde028ffcc Merge tag 'i2c-for-6.9-rc1-part2' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux
7bbd20ac15d0 Merge tag 'rtc-6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/abelloni/linux
b2bb86451efb Merge tag 'ubifs-for-linus-6.9-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rw/ubifs
203aa834e5f2 Merge tag 'char-misc-6.9-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc
9125147fa946 Merge tag 'tty-6.9-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty
e5738ce51174 Merge tag 'usb-6.9-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb
d4a1391985cc Merge tag 'rproc-v6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/remoteproc/linux
b3632b121e0d Merge tag 'asoc-fix-v6.9-merge-window' of https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound into for-linus
4a7dcd8c3a18 dt-bindings: i2c: qcom,i2c-cci: Fix OV7251 'data-lanes' entries
f76fa412f9a8 Merge tag 'i2c-host-6.9-part2' of git://git.kernel.org/pub/scm/linux/kernel/git/andi.shyti/linux into i2c/for-mergewindow
8cd35b85c4b0 Merge tag 'soc-late-6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
f6c32d4a4ede Merge tag 'thermal-6.9-rc1-2' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm
6630f47c5f9a spi: Merge up v6.8 release
ec2e44a038f5 Merge tag 'timers-v6.9-rc1' of https://git.linaro.org/people/daniel.lezcano/linux into timers/core
ef0c6b10c2da Merge tag 'i3c/for-6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/i3c/linux
6defc064e93e Merge tag 'linux-watchdog-6.9-rc1' of git://www.linux-watchdog.org/linux-watchdog
72fe2cde7b8a Merge tag 'input-for-v6.9-rc0' of git://git.kernel.org/pub/scm/linux/kernel/git/dtor/input
a546e7273d2d Merge tag 'phy-for-6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy
3972e256bfa2 Merge tag 'v6.9-p1' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6
a355cc2d4dcb Merge tag 'mips_6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux
aefedca6e1b1 Merge tag 'devicetree-for-6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux
8eb838e35ade Merge tag 'mtd/for-6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux
7497080a0eda Merge tag 'dmaengine-6.9-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine
571f27ef129d Merge tag 'i2c-for-6.9-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux
fb60e6d58b2d dt-bindings: input: samsung,s3c6410-keypad: convert to DT Schema
34598dab4724 Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
9d67b3ce96cb Merge tag 'media/v6.9-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-media
3fe3426bca72 dt-bindings: soc: imx: fsl,imx-anatop: add imx6q regulators
7311bc58c158 Merge tag 'nand/for-6.9' into mtd/next
146d9a6f3ded dt-bindings: atmel-nand: add microchip,sam9x7-pmecc
e2a5c7c3959b arm64: dts: broadcom: bcmbca: Update router boards
1bd13f3b7695 arm64: dts: broadcom: bcmbca: Add NAND controller node
cc519333e3cf ARM: dts: broadcom: bcmbca: Add NAND controller node
c1e4264b6d55 Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux
6371c24fe180 Merge tag 'sound-6.9-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound
98c06b3a9483 Merge tag 'pci-v6.9-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci
7fa73443a89b Merge tag 'platform-drivers-x86-v6.9-1' of git://git.kernel.org/pub/scm/linux/kernel/git/pdx86/platform-drivers-x86
e76bc30ffbd6 Merge tag 'leds-next-6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/leds
19186d59b259 Merge tag 'backlight-next-6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/backlight
75c5518e62b1 Merge tag 'mfd-next-6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd
099699809967 Merge tag 'pinctrl-v6.9-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
8e49bd3cbb58 Merge tag 'auxdisplay-v6.9-1' of git://git.kernel.org/pub/scm/linux/kernel/git/andy/linux-auxdisplay
a775511def90 Merge tag 'drm-next-2024-03-13' of https://gitlab.freedesktop.org/drm/kernel
4d3acb15ed8a Merge tag 'spi-nor/for-6.9' into mtd/next
51591c70d1ca Merge branches 'clk-samsung', 'clk-imx', 'clk-rockchip', 'clk-clkdev' and 'clk-rate-exclusive' into clk-next
0c05d2bca0f7 Merge tag 'thermal-v6.9-rc1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/thermal/linux
a55648d846e7 Merge branches 'clk-remove', 'clk-amlogic', 'clk-qcom', 'clk-parent' and 'clk-microchip' into clk-next
749f625e4547 Merge branches 'clk-aspeed', 'clk-keystone', 'clk-mobileye' and 'clk-allwinner' into clk-next
82d0f90167fc Merge branches 'clk-renesas', 'clk-cleanup', 'clk-hisilicon', 'clk-mediatek' and 'clk-bulk' into clk-next
6526c4a4b4e5 Merge tag 'tpmdd-v6.9-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/jarkko/linux-tpmdd
1da1a2503cbc Merge tag 'mailbox-v6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/jassibrar/mailbox
cecb3b4fdac3 Merge tag 'pm-6.9-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm
49c8db52641c Merge tag 'pmdomain-v6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/linux-pm
b15efb2ec6a3 Merge tag 'hwmon-for-v6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/groeck/linux-staging
51da5c0be9f6 ASoC: Merge up release
82088fb378a1 Merge tag 'gpio-updates-for-v6.9-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux
08aa0ae1911b Merge tag 'spi-v6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi
4a3bf9f36d1e Merge tag 'regulator-v6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/regulator
c77ca2066932 Merge tag 'mmc-v6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc
c5d224537c1b Merge tag 'pwm/for-6.9-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/ukleinek/linux
4915b8cd98b1 Merge tag 'ata-6.9-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/libata/linux
087aaa6a3b72 Merge tag 'iommu-updates-v6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu
8a195fe51ba1 Merge tag 'net-next-6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next
80731b204b02 Merge tag 'soc-drivers-6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
ba13a7bc46d2 Merge tag 'soc-dt-6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
8bdef0681554 Merge branch 'pci/controller/qcom'
5ad36cd7e767 riscv: dts: renesas: Add Andes PMU extension for r9a07g043f
8ecbb51f81c3 dt-bindings: riscv: Add Andes PMU extension description
9b464e19669d riscv: dts: renesas: r9a07g043f: Update compatible string to use Andes INTC
7d51e7e2e08f dt-bindings: riscv: Add Andes interrupt controller compatible string
9ff0305a8ca8 ASoC: dt-bindings: cirrus,cs42l43: Fix 'gpio-ranges' schema
9527f40e46b6 Input: allocate keycode for Display refresh rate toggle
62e63d55bebc Merge tag 'i2c-host-6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/andi.shyti/linux into i2c/for-mergewindow
9570e92757ae dt-bindings: tpm: Add compatible string atmel,attpm20p
7cfac8b79d64 Merge tag 'irq-core-2024-03-10' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
432d7edb5952 dt-bindings: thermal: rcar-gen3-thermal: Add r8a779h0 support
338820b14493 dt-bindings: thermal-zones: Don't require polling-delay(-passive)
586ddb37a9a4 dt-bindings: thermal: sun8i: Add H616 THS controller
167b4b5a2247 dt-bindings: thermal: qoriq-thermal: Adjust fsl,tmu-range min/maxItems
97f8ab2a1af7 Merge tag 'opp-updates-6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/vireshk/pm into pm
6478cc89c8f9 Merge tag 'asoc-v6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound into for-linus
ac6125bb95c2 mips: dts: ralink: mt7621: add cell count properties to usb
c5bb691ccc3e mips: dts: ralink: mt7621: add serial1 and serial2 nodes
7b09814959b2 mips: dts: ralink: mt7621: reorder serial0 properties
ec836787ded4 mips: dts: ralink: mt7621: associate uart1_pins with serial0
7d9359e47208 Merge tag 'riscv-dt-fixes-for-v6.8-final' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/dt
078fe0b4bda8 Merge tag 'arm-soc/for-6.9/drivers' of https://github.com/Broadcom/stblinux into soc/late
a851536f7d1f Merge tag 'arm-soc/for-6.9/devicetree-arm64' of https://github.com/Broadcom/stblinux into soc/late
63fbbfa8e739 dt-bindings: opp: drop maxItems from inner items
54c13b3c325d dt-bindings: mailbox: fsl,mu: add i.MX95 Generic/ELE/V2X MU compatible
4950062963d6 dt-bindings: input: imagis: Document touch keys
cfb6e7e4aab8 dt-bindings: PCI: qcom: Document the X1E80100 PCIe Controller
c779c938fb22 dt-bindings: pinctrl: qcom: update compatible name for match with driver
98b8ca8bcb74 dt-bindings: input: atmel,captouch: convert bindings to YAML
f4627ef4c35c dt-bindings: i2c: nomadik: add mobileye,eyeq5-i2c bindings and example
e6a7453cf514 Merge tag 'wireless-next-2024-03-08' of git://git.kernel.org/pub/scm/linux/kernel/git/wireless/wireless-next
826587e76776 dt-bindings: PCI: qcom: Do not require 'msi-map-mask'
e776ecb01509 dt-bindings: PCI: qcom: Allow 'required-opps'
41c94df7b508 dt-bindings: auxdisplay: Add bindings for generic 7-segment LED
51ec88485bd0 dt-bindings: rtc: zynqmp: Add support for Versal/Versal NET SoCs
4a0688c342c5 dt-bindings: rtc: abx80x: Improve checks on trickle charger constraints
09ed5b86a7c0 Merge branches 'arm/mediatek', 'arm/renesas', 'arm/smmu', 'x86/vt-d', 'x86/amd' and 'core' into next
1ca49df08091 dt-bindings: net: dp83822: change ti,rmii-mode description
9e691f2ca146 Merge tag 'drm-msm-next-2024-03-07' of https://gitlab.freedesktop.org/drm/msm into drm-next
cfe04ff5f8c9 dt-bindings: serial: stm32: add power-domains property
b072a75f7faf dt-bindings: nvmem: add common definition of nvmem-cell-cells
be64edb74cf7 dt-bindings: nvmem: Convert xlnx,zynqmp-nvmem.txt to yaml
baca151add1c nvmem: fixed-cell: Simplify nested if/then schema
1c0b231f57e0 dt-bindings: hwmon: Support Aspeed g6 PWM TACH Control
a0c034ed370f dt-bindings: hwmon: fan: Add fan binding to schema
5f3df8a26d1e dt-bindings: hwmon: tda38640: Add interrupt & regulator properties
ea5fd00e7566 Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
1cd0ddec1f0e dt-bindings: timer: mediatek: Convert to json-schema
4a513c9ee434 ASoC: codecs: ES8326: change support for ES8326
9428855666bf dt-bindings: backlight: qcom-wled: Fix bouncing email addresses
ded680d1011e dt-bindings: leds: Add NCP5623 multi-LED Controller
36c053ec1940 dt-bindings: leds: qcom-lpg: Narrow nvmem for other variants
86d79b6e9034 dt-bindings: leds: qcom-lpg: Drop redundant qcom,pm8550-pwm in if:then:
0d9351b5397b dt-bindings: leds: Add LED_FUNCTION_WAN_ONLINE for Internet access
00b899276322 dt-bindings: leds: Add FUNCTION defines for per-band WLANs
0d85184c07f6 dt-bindings: leds: leds-qcom-lpg: Add support for LPG PPG
b4ab63101636 Merge branches 'ib-qcom-leds-6.9' and 'ib-leds-backlight-6.9' into ibs-for-leds-merged
3555e8d0b9fc dt-bindings: backlight: Add Kinetic KTD2801 binding
a8c949969077 Merge branch 'ib-nomadik-gpio' into devel
62c3262f7fe3 dt-bindings: net: renesas,etheravb: Add support for R-Car V4M
918ae23afab4 dt-bindings: interrupt-controller: fsl,intmux: Include power-domains support
e53ec66488c1 Merge tag 'icc-6.9-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/djakov/icc into char-misc-next
1f0e4fc46ee7 Merge tag 'qcom-arm64-for-6.9-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt
ea75705aeacc Merge tag 'riscv-dt-for-v6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/late
584c83fce20d dt-bindings: remoteproc: qcom,sm8550-pas: document the X1E80100 aDSP & cDSP
c04e94fc3b79 dt-bindings: remoteproc: do not override firmware-name $ref
4b39a7e1c39f dt-bindings: remoteproc: qcom,glink-rpm-edge: drop redundant type from label
e6ec88170ffc dt-bindings: pinctrl: Add bindings for Awinic AW9523/AW9523B
fc76e2ec0af9 spi: dt-bindings: introduce FIFO depth properties
649423f8a081 ASoC: dt-bindings: rt1015: Convert to dtschema
7a4e8175bafb riscv: dts: starfive: jh7100: fix root clock names
eed1e7dce0c5 Merge tag 'ath-next-20240305' of git://git.kernel.org/pub/scm/linux/kernel/git/kvalo/ath
b77c6d6ecd26 Merge tag 'v6.8-rc7' into gpio/for-next
b6f4257e837d dt-bindings: input: allwinner,sun4i-a10-lrad: drop redundant type from label
ab13fd756619 dt-bindings: fsl-imx-sdma: fix HDMI audio index
8183e8af3de8 dt-bindings: soc: imx: fsl,imx-iomuxc-gpr: add imx6
364eb93f21bc dt-bindings: soc: imx: fsl,imx-anatop: add binding
0d6b9633b62c dt-bindings: input: touchscreen: fsl,imx6ul-tsc convert to YAML
e24d180df3e3 dt-bindings: pinctrl: fsl,imx6ul-pinctrl: convert to YAML
c6cb9528755c Merge tag 'v6.9-rockchip-drivers1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt
1541b5f7169a dt-bindings: usb: typec-tcpci: add tcpci fallback binding
30cfb408e45f dt-bindings: usb: Add downstream facing ports to realtek binding
ba19f225f401 dt-bindings: usb: Add binding for TI USB8020B hub controller
c3251302f8d3 dt-bindings: usb: analogix,anx7411: drop redundant connector properties
c6425032f69e dt-bindings: usb: add hisilicon,hi3798mv200-dwc3
a1bd84637b96 dt-bindings: mmc: hisilicon,hi3798cv200-dw-mshc: add Hi3798MV200 binding
7fc53b04c1ea dt-bindings: mmc: dw-mshc-hi3798cv200: convert to YAML
f1338ec7ac44 dt-bindings: i2c: mpc: use proper binding for transfer timeouts
78ad26b5f48f dt-bindings: interrupt-controller: Convert Atmel AIC to json-schema
99d17f43c09c Merge tag 'reset-for-v6.9' of git://git.pengutronix.de/pza/linux into soc/late
14c572ddf1f9 Merge tag 'omap-for-v6.9/dt-warnings-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into soc/late
04cdefa63030 Merge tag 'vexpress-update-6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into soc/dt
8100aecad25e ARM: dts: samsung: exynos4412: decrease memory to account for unusable region
44ffff36c17a Merge tag 'ti-keystone-dt-for-v6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux into soc/dt
38d2af77456f Merge tag 'memory-controller-drv-6.9-2' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl into soc/drivers
4b3d3727fe21 Merge tag 'qcom-drivers-for-6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/drivers
1390bca92db4 spi: dt-bindings: samsung: make dma properties not required
f3f062800bf5 dt-bindings: perf: starfive: Add JH8100 StarLink PMU
8ade2ed03067 dt-bindings: usb: qcom,pmic-typec: add support for the PM4125 block
ffd54b03300e dt-bindings: leds: pwm-multicolour: re-allow active-low
2bd3e3e38b19 dt-bindings: imx6q-pcie: Add iMX95 pcie endpoint compatible string
a1a33ad5df89 dt-bindings: imx6q-pcie: Add imx95 pcie compatible string
d5b3866ee39c dt-bindings: imx6q-pcie: Restruct reg and reg-name
17964120885e dt-bindings: imx6q-pcie: Clean up duplicate clocks check
b2e87666166c Merge tag 'qcom-arm32-for-6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt
d6f0d6fbd771 Merge tag 'v6.9-rockchip-dts32-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt
9beae6e4f5b2 Merge tag 'v6.9-rockchip-dts64-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt
bfa16e672f23 Merge tag 'riscv-sophgo-dt-for-v6.9' of https://github.com/sophgo/linux into soc/dt
b9a523277cff Merge tag 'mvebu-dt64-6.9-1' of git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu into soc/dt
472acadc4b85 Merge tag 'mvebu-dt-6.9-1' of git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu into soc/dt
a1c9c09fe4c6 Merge tag 'renesas-dt-bindings-for-v6.9-tag3' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt
ed9768f823d1 Merge tag 'stm32-dt-for-v6.9-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into soc/dt
a93afb6c68a1 arm64: dts: qcom: sm8250-xiaomi-elish: set rotation
c1d25c9b315c arm64: dts: qcom: sm8650: Fix SPMI channels size
f203c283f5bb arm64: dts: qcom: sm8550: Fix SPMI channels size
6b3cdc5e247c Merge tag 'drm-misc-next-2024-02-29' into msm-next
0ccaa0050371 dt-bindings: input/touchscreen: imagis: add compatible for IST3032C
f4cd9022dce6 dt-bindings: input/touchscreen: Add compatible for IST3038B
147eff3c7cff dt-bindings: watchdog: sama5d4-wdt: add compatible for sam9x7-wdt
3a9200687cf7 dt-bindings: watchdog: sprd,sp9860-wdt: convert to YAML
cbe08f41aa59 dt-bindings: watchdog: starfive,jh7100-wdt: Add compatible for JH8100
be02d67086d9 dt-bindings: watchdog: arm,sp805: document the reset signal
201c69876dc6 dt-bindings: watchdog: renesas-wdt: Add support for R-Car V4M
653594df87d5 dt-bindings: serial: convert st,asc to DT schema
1a0b7e8acef8 powerpc: dts: akebono: Harmonize EHCI/OHCI DT nodes name
8d179c0b54fb dt-bindings: usb: qcom,dwc3: fix a typo in interrupts' description
c630e9b5a72f arm64: dts: qcom: pm6150: define USB-C related blocks
da1d13674619 dt-bindings: usb: qcom,pmic-typec: Add support for the PM6150 PMIC
d3864961a639 Merge tag 'w1-drv-6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-w1 into tty-next
8f130bd54c7b Merge tag 'iio-for-6.9b' of https://git.kernel.org/pub/scm/linux/kernel/git/jic23/iio into char-misc-next
20d54e06e2a3 Merge tag 'coresight-next-v6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/coresight/linux into char-misc-next
c326cc675c68 arm64: dts: rockchip: Fix name for UART pin header on qnap-ts433
3965a283125e dt-bindings: pwm: amlogic: Add a new binding for meson8 pwm types
d397107f4e3a dt-bindings: pwm: amlogic: fix s4 bindings
6d25cc8fd5da dt-bindings: i2c: Remove obsolete i2c.txt
59488a1b3652 dt-bindings: arm: syna: remove unstable remark
1d325ff1ed92 dt-bindings: net: bluetooth: qualcomm: Fix bouncing @codeaurora
9f1d679268ba dt-bindings: watchdog: drop obsolete brcm,bcm2835-pm-wdt bindings
090fc268fac4 dt-bindings: watchdog: qcom-wdt: Update maintainer to Rajendra Nayak
0451b0796a61 dt-bindings: hwmon: lm75: use common hwmon schema
371142306400 Merge tag 'amlogic-arm64-dt-for-v6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux into soc/dt
0e7fe10bc9e6 Merge tag 'amlogic-arm-dt-for-v6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux into soc/dt
d0cb807cfef4 Merge tag 'omap-for-v6.9/dt-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into soc/dt
3578f1b6dbed Merge tag 'ti-k3-dt-for-v6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux into soc/dt
d68c28418b67 riscv: dts: starfive: jh7110: Add camera subsystem nodes
aa86c303373a arm: dts: marvell: clearfog-gtr-l8: align port numbers with enclosure
ae315320f5d1 arm: dts: marvell: clearfog-gtr-l8: add support for second sfp connector
6330d58dd4fe dt-bindings: soc: renesas: renesas-soc: Add pattern for gray-hawk
1a4325f9d215 Merge tag 'arm-smmu-updates' of git://git.kernel.org/pub/scm/linux/kernel/git/will/linux into arm/smmu
6d23cfa8897b Merge tag 'at91-dt-6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into soc/dt
7632a364f33e Merge tag 'zynqmp-dt-for-6.9' of https://github.com/Xilinx/linux-xlnx into soc/dt
02eba1b4512a Merge tag 'sgx-for-v6.9-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into soc/dt
c0d63be31667 Merge tag 'imx-dt64-6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into soc/dt
0d1bd814646e Merge tag 'imx-dt-6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into soc/dt
fcd3ba0ec7e6 Merge tag 'imx-bindings-6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into soc/dt
911a0e5da311 Merge tag 'socfpga_dts_updates_for_v6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into soc/dt
fec957a967a1 dt-bindings: rng: atmel,at91-trng: add sam9x7 TRNG
f25a9445fef8 dt-bindings: crypto: add sam9x7 in Atmel TDES
8790f16edade dt-bindings: crypto: add sam9x7 in Atmel SHA
44266f1d25b2 dt-bindings: crypto: add sam9x7 in Atmel AES
2b1ebc6d769d Merge tag 'qcom-arm64-for-6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt
43a56bf3bdaf Merge tag 'sunxi-dt-for-6.9-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into soc/dt
e19434848bd8 Merge tag 'drm-msm-next-2024-02-29' of https://gitlab.freedesktop.org/drm/msm into drm-next
01321d44f1ec dt-bindings: net: brcm,asp-v2.0: Add asp-v2.2
d5a543a359ce dt-bindings: net: brcm,unimac-mdio: Add asp-v2.2
089e8a0b0394 dt-bindings: gpio: aspeed,ast2400-gpio: Convert to DT schema
925e183d1d3e Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
c44ea78dc972 dt-bindings: rtc: abx80x: convert to yaml
3a25f24b71ce dt-bindings: at91rm9260-rtt: add sam9x7 compatible
6ae5f27fcef7 dt-bindings: rtc: convert MT7622 RTC to the json-schema
8e6eb376128e dt-bindings: rtc: convert MT2717 RTC to the json-schema
dffd03e7b3c3 Merge branch 'icc-sm7150' into icc-next
f8afb1ebc676 dt-bindings: interconnect: Add Qualcomm SM7150 DT bindings
253a470f5420 dt-bindings: mfd: syscon: Add ti,am62-usb-phy-ctrl compatible
f689de1b40f9 dt-bindings: mfd: dlg,da9063: Make #interrupt-cells required
a029ec8c35c4 Merge tag 'tegra-for-6.9-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/dt
cbda1f9ca478 Merge tag 'tegra-for-6.9-arm-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/dt
061a7ef8ce88 Merge tag 'tegra-for-6.9-dt-bindings' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/dt
2788cdbbf836 Merge tag 'renesas-dts-for-v6.9-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt
af467f28aa2e Merge tag 'renesas-dt-bindings-for-v6.9-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt
e422e34ebe7a Merge tag 'v6.9-rockchip-dts32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt
15643f4b8b71 Merge tag 'v6.9-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt
3b71bcf355d9 Merge tag 'versatile-dts-v6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator into soc/dt
d73cece0601b Merge tag 'gemini-dts-v6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator into soc/dt
d5e822510e6a Merge tag 'mtk-dts64-for-v6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux into soc/dt
88c6586d8ddc Merge tag 'dt-cleanup-6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-dt into soc/dt
485c27391cf2 Merge tag 'samsung-dt-6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into soc/dt
9a55de21e5e8 Merge tag 'samsung-dt64-6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into soc/dt
7fe0c3cf50e7 Merge tag 'renesas-dts-for-v6.9-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt
a28ccc2c8a1e Merge tag 'renesas-dt-bindings-for-v6.9-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt
3a1d10b8a7ea dt-bindings: pinctrl: at91: add sam9x7
25fa45a7091a arm64: dts: st: add video encoder support to stm32mp255
374df3f7a69d arm64: dts: st: add video decoder support to stm32mp255
f1523e3d07c3 dt-bindings: gpio: nomadik: add optional reset property
7c456af0e520 dt-bindings: gpio: nomadik: add mobileye,eyeq5-gpio compatible
6412671654fb dt-bindings: gpio: nomadik: add optional ngpios property
33796ff4220d dt-bindings: gpio: nomadik: convert into yaml format
e5443d45c0ec ARM: dts: stm32: enable crypto accelerator on stm32mp135f-dk
fdf13e6831f2 ARM: dts: stm32: enable CRC on stm32mp135f-dk
b5c98471fd1a ARM: dts: stm32: add CRC on stm32mp131
f454b7a85920 dt-bindings: pinctrl: mobileye,eyeq5-pinctrl: add bindings
e03c12f18d62 ARM: dts: add stm32f769-disco-mb1166-reva09
690f4c3b681a ARM: dts: stm32: add display support on stm32f769-disco
4cb81b91ac87 ARM: dts: stm32: rename mmc_vcard to vcc-3v3 on stm32f769-disco
82d1ed24df95 ARM: dts: stm32: add DSI support on stm32f769
c8114c09da2c dt-bindings: mfd: stm32f7: Add binding definition for DSI
363d4a9715e5 dt-bindings: nt35510: document 'port' property
9059c18b6d10 dt-bindings: iio: gyroscope: bosch,bmg160: add spi-max-frequency
ebcb39d7a66e dt-bindings: iio: adc: imx93: drop the 4th interrupt
2f1ec66e6c94 dt-bindings: iio: adc: drop redundant type from label
d24619ffe43c dt-bindings: iio: ti,tmp117: add optional label property
633fffb7c377 dt-bindings: iio: magnetometer: Add Voltafield AF8133J
a36a9e62abdf dt-bindings: vendor-prefix: Add prefix for Voltafield
2ef6443e1743 dt-bindings: iio: light: vishay,veml6075: make vdd-supply required
c9c055c5470f dt-bindings: iio: adc: adding support for PAC193X
a288cab1e5a6 dt-bindings: iio: hmc425a: add entry for LTC6373
43172d694644 dt-bindings: iio: hmc425a: add conditional GPIO array size constraints
42707bcbabe0 dt-bindings: iio: humidity: hdc20x0: add optional interrupts property
49676274cbd7 dt-bindings: iio: ti,tmp117: add vcc supply binding
6dafe28e7298 dt-bindings: mmc: fsl-imx-mmc: Document the required clocks
620fcff9d53c spi: dt-bindings: atmel,at91rm9200-spi: remove 9x60 compatible from list
22502bd8725d dt-bindings: mmc: fsl-imx-esdhc: add default and 100mhz state
a3da0bec1dd6 arm64: dts: rockchip: Add basic support for QNAP TS-433
e5d58e2bc9d5 dt-bindings: arm: rockchip: Add QNAP TS-433
78b9bf1a6128 arm64: dts: rockchip: add Haikou baseboard with RK3588-Q7 SoM
2ffa10c5e5ad arm64: dts: rockchip: add RK3588-Q7 (Tiger) SoM
7009dfbb88d7 dt-bindings: arm: rockchip: Add Theobroma-Systems RK3588 Q7 with baseboard
2516daa7bde5 arm64: dts: rockchip: drop rockchip,trcm-sync-tx-only from rk3588 i2s
fc876128d301 dt-bindings: net: ethernet-controller: drop redundant type from label
13ab34ef0793 arm64: dts: rockchip: fix reset-names for rk356x i2s2 controller
883bb3a0ffc9 arm64: dts: rockchip: add missing interrupt-names for rk356x vdpu
eec8be52f681 arm64: dts: rockchip: add clock to vo1-grf syscon on rk3588
103ec967103c dt-bindings: net: dsa: realtek: add reset controller
3018a826c97d dt-bindings: net: dsa: realtek: reset-gpios is not required
6dc9f167486c dt-bindings: arm: rockchip: Add Toybrick TB-RK3588X
a181bc600877 arm64: dts: rockchip: Add devicetree support for TB-RK3588X board
cc35d14ce704 ARM: dts: rockchip: Wifi improvements for Sonoff iHost
d3e564c6f34a ARM: dts: rockchip: mmc aliases for Sonoff iHost
ca5df862ea65 arm64: dts: rockchip: adjust vendor on orangepi rk3399 board
ed51c83e418c arm64: dts: rockchip: adjust vendor on Banana Pi R2 Pro board
cff456e5f266 dt-bindings: arm: rockchip: Correct vendor for Banana Pi R2 Pro
3522950a8c39 dt-bindings: arm: rockchip: Correct vendor for Orange Pi RK3399 board
82a17c8827d1 arm64: dts: rockchip: Add HDMI0 PHY to rk3588
e66d1e81aed1 arm64: dts: armada-ap807: update thermal compatible
1d32f2a19cc3 arm64: dts: marvell: reorder crypto interrupts on Armada SoCs
35290ca22165 arm64: dts: ac5: add mmc node and clock
f5ba7df64a26 arm: dts: marvell: clearfog-gtr: add missing pinctrl for all used gpios
a64c072c8b1d arm: dts: marvell: clearfog-gtr: sort pinctrl nodes alphabetically
57a80269cb6c arm: dts: marvell: clearfog-gtr: add board-specific compatible strings
9f7d319ef30b arm: dts: marvell: clearfog: add pro variant compatible in legacy dts
ee29a2404550 dt-bindings: marvell: a38x: add solidrun armada 385 clearfog gtr boards
a94644e247d1 dt-bindings: marvell: a38x: add kobol helios-4 board
977f211a8ee3 dt-bindings: marvell: a38x: add solidrun armada 388 clearfog boards
6fe97bf74341 dt-bindings: marvell: a38x: convert soc compatibles to yaml
313957b8c112 Merge branch 'v6.9-shared/clkids' into v6.9-armsoc/dts64
e0f54133c394 dt-bindings: clock: rk3588: add missing PCLK_VO1GRF
e32d677022ca dt-bindings: clock: rk3588: drop CLK_NR_CLKS
4b58a7ccfd97 Merge tag 'mt76-for-kvalo-2024-02-22' of https://github.com/nbd168/wireless
479c5ca5c8ae dt-bindings: arm: amlogic: add Neil, Martin and Jerome as maintainers
39d812837cdd dt-bindings: arm: amlogic: remove unstable remark
54469d99a2af dt-bindings: mmc: sdhci-of-dwcmhsc: Add Sophgo CV1800B and SG2002 support
f4bffe85d2e7 dt-bindings: arm: qcom,coresight-tpdm: Rename qcom,dsb-element-size
7c2c6922effb dt-bindings: memory-controller: st,stm32: add MP25 support
b3f6be88f1f5 Merge 6.8-rc6 into tty-next
f4288db518a8 dt-bindings: net: cdns,macb: add sam9x7 ethernet interface
5315d5ea1db7 dt-bindings: i2c: at91: Add sam9x7 compatible string
b99dd7ccd5b8 dt-bindings: i2c: imx-lpi2c: add i.MX95 LPI2C
d377e1b8336c Convert some regulator drivers to GPIO descriptors
d5220c4662fe dt-bindings: auxdisplay: Add Maxim MAX6958/6959
2f25ffe9d998 dt-bindings: arm-smmu: Document SM8650 GPU SMMU
b4c3aaf580d9 dt-bindings: arm-smmu: fix SM8[45]50 GPU SMMU if condition
0abc1ff2be4e dt-bindings: display/msm/gmu: Document Adreno 750 GMU
ec4f0c02c1ec dt-bindings: display/msm: gpu: Allow multiple digits for patchid
49915776f063 dt-bindings: lcdif: Do not require power-domains for i.MX6ULL
a2a81ebc850d dt-bindings: timer: Add support for cadence TTC PWM
0a54c5eb5a02 Merge tag 'renesas-pinctrl-for-v6.9-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel
f12177200edc dt-bindings: interrupt-controller: Add starfive,jh8100-intc
99b3211ce73c regulator: dt-bindings: gpio-regulator: Fix "gpios-states" and "states" array bounds
ca5cca640867 ARM: dts: omap4-panda-common: Enable powering off the device
6b4a8eca637d ARM: dts: omap-embt2ws: system-power-controller for bt200
87c4cebd8708 ARM: dts: omap: Switch over to https:// url
80adf5afe7f6 ARM: dts: ti: omap: add missing abb_{mpu,ivahd,dspeve,gpu} unit addresses for dra7 SoC
a446d52725b5 ARM: dts: ti: omap: add missing sys_32k_ck unit address for dra7 SoC
4d96b742cb3e ARM: dts: ti: omap: add missing phy_gmii_sel unit address for dra7 SoC
7f22c5d06f8d dt-bindings: net: dp83822: support configuring RMII master/slave mode
5a411c0575cc ARM: dts: omap3: Update clksel clocks to use reg instead of ti,bit-shift
43768eba3fa4 ARM: dts: am3: Update clksel clocks to use reg instead of ti,bit-shift
0f8d14846135 Merge v6.8-rc6 into drm-next
5ac99b57e27a dt-bindings: mtd: brcmnand: Add ecc strap property
d973f6e60329 dt-bindings: mtd: brcmnand: Add WP pin connection property
e8cf96a62e99 dt-bindings: mtd: brcmnand: Updates for bcmbca SoCs
4284b95c3a7d dt-bindings: mtd: st,stm32: add MP25 support
5ffc0c6588e1 dt-bindings: mtd: update references from partition.txt to mtd.yaml
079feabfa500 arm64: dts: ti: hummingboard-t: add overlays for m.2 pci-e and usb-3
77aac4df148c arm64: dts: add description for solidrun am642 som and evaluation board
bab419b95c2c dt-bindings: arm: ti: Add bindings for SolidRun AM642 HummingBoard-T
bc85817742eb dt-bindings: mtd: spi-nor: add optional interrupts property
201ac0128678 dt-bindings: pwm: opencores: Add compatible for StarFive JH8100
c0aae9685a91 dt-bindings: riscv: cpus: reg matches hart ID
8e0b9c610742 dt-bindings: bus: imx-weim: convert to YAML
c622150ed65c Merge v6.8-rc6 into usb-next
09994ac519e2 arm64: dts: imx8mm-kontron-bl-osm-s: Fix Ethernet PHY compatible
c8b82b8dd480 arm64: dts: imx8-apalis-v1.1: Remove reset-names from ethernet-phy
20cdb2916423 ARM: dts: nxp: imx: fix weim node name
064185347fff ARM: dts: nxp: imx6ul: fix touchscreen node name
42a236fd930d ARM: dts: nxp: imx6ul: xnur-gpio -> xnur-gpios
d9725dc952ee ARM: dts: imx6ul: Remove fsl,anatop from usbotg1
6cc27853e1c4 ARM: dts: imx6ull: fix pinctrl node name
c23b15b18c81 ARM: dts: imx1-apf9328: Fix Ethernet node name
7c8b8cf4dd15 ARM: dts: imx28-evk: Use 'eeprom' as the node name
102744f8003d ARM: dts: ls1021a: Enable usb3-lpm-capable for usb3 node
4822eab2af53 Merge branch 'icc-cleanup' into icc-next
0b20018b1dbc dt-bindings: mtd: ubi-volume: allow UBI volumes to provide NVMEM
5d1f49b1b6b0 dt-bindings: mtd: add basic bindings for UBI
9a35e12f4b1a dt-bindings: hwmon: reference common hwmon schema
3d36f23ac624 dt-bindings: hwmon: lltc,ltc4286: use common hwmon schema
798f72d666b8 dt-bindings: hwmon: adi,adm1275: use common hwmon schema
809baabdec34 dt-bindings: hwmon: ti,ina2xx: use common hwmon schema
42d06958b709 dt-bindings: hwmon: add common properties
f567e7a0ce93 regulator: dt-bindings: promote infineon buck converters to their own binding
b1715c2bbc33 dt-bindings: hwmon/pmbus: ti,lm25066: document regulators
0c5601d53cce dt-bindings: hwmon: nuvoton,nct6775: Add compatible value for NCT6799
fb5eada36609 dt-bindings: trivial-devices: add Astera Labs PT5161L
7d3134823476 dt-bindings: vendor-prefixes: add asteralabs
c75f1a591ccd dt-bindings: hwmon: Add Amphenol ChipCap 2
737f7b7c7c23 dt-bindings: vendor-prefixes: add Amphenol
380e45011084 dt-bindings: Add MPQ8785 voltage regulator device
adb144c788f3 dt-bindings: clock: exynos850: Add CMU_CPUCLK0 and CMU_CPUCL1
77ced3f45487 dt-bindings: arm: add UNI-T UTi260B
521023b8972b dt-bindings: vendor-prefixes: add UNI-T
10a08d63eb50 arm64: dts: imx8mp-evk: Fix hdmi@3d node
96099eef1a2c arm64: dts: imx93-var-som: Remove phy-supply from eqos
0ee187cdb35f Merge tag 'iio-for-6.9a' of http://git.kernel.org/pub/scm/linux/kernel/git/jic23/iio into char-misc-next
9aa0ba8c3e6a arm64: dts: imx8mp-phyboard-pollux: Disable pull-up for CD GPIO
195bcec93c44 arm64: dts: imx8mp-phyboard-pollux: Reduce drive strength for eqos tx lines
adb0eb622cec arm64: dts: imx8mp-phyboard-pollux: Set debug uart muxing to 0x140
8032acfdf1a8 arm64: dts: imx8mp-phyboard-pollux: Add and update rtc devicetree node
9ffab265f1ac arm64: dts: imx8mm-evk: Add spdif sound card support
3f1b2e8d9e29 arm64: dts: mba8xx: Add missing #interrupt-cells
dd5af1f60a28 arm64: dts: imx8mp: Set SPI NOR to max 40 MHz on Data Modul i.MX8M Plus eDM SBC
f461418b3107 ARM: dts: imx6dl-yapp4: Move the internal switch PHYs under the switch node
dbaddd2cc383 ARM: dts: imx6dl-yapp4: Fix typo in the QCA switch register address
6a28d56cd75a arm64: dts: imx8mn: tqma8mqnl-mba8mx: Add USB DR overlay
68f02dd7e55f arm64: dts: imx8mq: tqma8mq-mba8mx: Add missing USB vbus supply
06e63f07db24 arm64: dts: freescale: imx8mm/imx8mq: mba8mx: Use PCIe clock generator
65f27cc9ca1b arm64: dts: imx8mn-beacon: Remove unnecessary clock configuration
ec091103f662 arm64: dts: imx8mn: Slow default video_pll clock rate
f3ed68d12445 arm64: dts: imx8mp-beacon: Configure multiple queues on eqos
825a35212289 arm64: dts: imx8mp-beacon: Enable Bluetooth
e32a570a61aa ARM: dts: imx6ul: Set macaddress location in ocotp
48b05a3282bd arm64: dts: freescale: minor whitespace cleanup
4b0cf920e774 arm64: dts: allwinner: h616: Add thermal sensor and zones
d0665f60cec0 ARM: dts: sun8i: Open FETA40i-C regulator aldo1
f0c099b60ae3 arm64: dts: allwinner: h616: Add Sipeed Longan SoM 3H and Pi 3H board support
01ae6c03a880 dt-bindings: arm: sunxi: Add Sipeed Longan Module 3H and Longan Pi 3H
c763b1cf0ca7 arm64: dts: allwinner: h616: minor whitespace cleanup
fba9e58bbd03 arm64: dts: allwinner: use capital "OR" for multiple licenses in SPDX
c6b7cf5d4b69 arm64: dts: allwinner: Transpeed 8K618-T: add WiFi nodes
13d73fcac8c9 arm64: dts: allwinner: h616: Add 32K fanout pin
05bdbb1eb3fd arm64: dts: allwinner: Add Jide Remix Mini PC support
0df51b232403 dt-bindings: arm: sunxi: document Remix Mini PC name
898b36322bb2 dt-bindings: vendor-prefixes: add Jide
70e735bb236e arm64: dts: allwinner: h616: Add SPDIF device node
10969c04cb6e arm64: dts: allwinner: h616: Add DMA controller and DMA channels
c5182cdc0aa8 arm64: dts: allwinner: h6: Add RX DMA channel for SPDIF
e31d5ca612d6 dt-bindings: sram: narrow regex for unit address to hex numbers
013b1096017d ARM: dts: microchip: sama7g5: add sama7g5 compatible
782f527e1b30 ARM: dts: microchip: sam9x60: align dmas to the opening '<'
d08950521775 ARM: dts: microchip: sama7g5: align dmas to the opening '<'
c9cdb533541e ARM: dts: microchip: sama7g54_curiosity: Add initial device tree of the board
28a13f689e75 ARM: dts: microchip: sama7g5: Add flexcom 10 node
57fb3296fc2d ASoC: dt-bindings: microchip: add sam9x7
81a8f19d991d ASoC: dt-bindings: atmel-classd: add sam9x7 compatible
c1e8427eb3df dt-bindings: ARM: at91: Document Microchip SAMA7G54 Curiosity
708077cf30a4 arm64: tegra: Remove Jetson Orin NX and Jetson Orin Nano DTSI
14b1c490371e arm64: tegra: Add audio support for Jetson Orin NX and Jetson Orin Nano
5bdc0a8fed68 arm64: tegra: Define missing IO ports
8ff1bf770a0c arm64: tegra: Move AHUB ports to SoC DTSI
9fd53de0ed30 arm64: tegra: Add USB Type-C controller for Jetson AGX Xavier
6c9a92242095 arm64: tegra: Add USB device support for Jetson AGX Xavier
495a87da7a47 arm64: tegra: Add current monitors for Jetson Xavier
426c1ddbd76b arm64: tegra: Add AXI configuration for Tegra234 MGBE
134b7a20eea2 dt-bindings: mfd: Convert atmel-flexcom to json-schema
7268c6969288 dt-bindings: mfd: cros-ec: Add properties for GPIO controller
a5c0c33c25f1 dt-bindings: mfd: ti,twl: Document system-power-controller
507cf9210c91 dt-bindings: net: wireless: qcom: Update maintainers
a9219f105d93 dt-bindings: mfd: syscon: Add ti,am654-serdes-ctrl compatible
37c3dbbbca5d dt-bindings: mfd: syscon: Add ti,j784s4-pcie-ctrl compatible
ef9712ce90c9 dt-bindings: mfd: atmel,hlcdc: Convert to DT schema format
fc3911fb624f dt-bindings: mfd: qcom,tcsr: Add compatibles for QCM2290 and SM6115
bcc7a549de96 dt-bindings: mfd: iqs62x: Do not override firmware-name $ref
e3889bfdf9d5 dt-bindings: media: rkisp1: Add i.MX8MP ISP to compatible
e7d16b884c9d dt-bindings: timer: add Ralink SoCs system tick counter
f4535baea464 dt-bindings: PCI: qcom,pcie-sa8775p: Move SA8775p to dedicated schema
169fa31aecaa dt-bindings: PCI: qcom,pcie-sc7280: Move SC7280 to dedicated schema
9a6e22b46113 dt-bindings: PCI: qcom,pcie-sc8180x: Move SC8180X to dedicated schema
e114fb24a186 dt-bindings: PCI: qcom,pcie-sc8280xp: Move SC8280XP to dedicated schema
88e9e05efe99 dt-bindings: PCI: qcom,pcie-sm8350: Move SM8350 to dedicated schema
977832dca6ab dt-bindings: PCI: qcom,pcie-sm8150: Move SM8150 to dedicated schema
53908f6ff54c dt-bindings: PCI: qcom,pcie-sm8250: Move SM8250 to dedicated schema
96931e6b08ab dt-bindings: PCI: qcom,pcie-sm8450: Move SM8450 to dedicated schema
3c9f28bcffc2 dt-bindings: PCI: qcom,pcie-sm8550: Move SM8550 to dedicated schema
c2f1d4a9447a arm64: dts: renesas: rzg2l-smarc: Enable DU and link with DSI
b39f9a0e920d arm64: dts: renesas: r9a07g054: Add DU node
3ecd2f1980c9 arm64: dts: renesas: r9a07g044: Add DU node
93d319ea783c arm64: dts: lx2160a: Fix DTS for full PL011 UART
8365edf2f65e arm64: dts: ls1088a: Add the PME interrupt for PCIe EP node
084a47a95058 arm64: dts: imx8qm: add i2c1 for imx8qm-mek board
d84b45a3c712 arm64: dts: imx8qm: add i2c4 and i2c4_lpcg node
9d3bb1c53622 ASoC: Revert "ASoC: dt-bindings: Update example for enabling USB offload on SM8250"
7ada2cb724f2 riscv: dts: add resets property for uart node
a034d20d33af riscv: dts: add reset generator for Sophgo SG2042 SoC
b312f7c28451 ARM: dts: imx53-qsb: add support for the HDMI expander
65d763356aad arm64: dts: imx8mp: Enable SAI audio on Data Modul i.MX8M Plus eDM SBC
c3b757a52529 arm64: dts: imx8: Fix lpuart DMA channel order
a9c570888e1c arm64: dts: freescale: imx8-ss-dma: Fix edma3's location
1880684dfc18 arm64: dts: imx8dxl update edma0 information
95a51114540e arm64: dts: imx8dxl: add fsl-dma.h dt-binding header file
87cc839ce871 Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
595539769055 dt-bindings: vendor-prefixes: Add missing prefixes used in compatibles
2b8f61f2af78 dt-bindings: display: convert Atmel's HLCDC to DT schema
d4e9fb508b98 dt-bindings: display/msm: Document MDSS on X1E80100
26ae54a934e7 dt-bindings: display/msm: Document the DPU for X1E80100
eec4611e4fa5 dt-bindings: arm-smmu: Document SM8650 GPU SMMU
011fc2593f52 dt-bindings: arm-smmu: Fix SM8[45]50 GPU SMMU 'if' condition
f45f80911a1e ARM: tegra: Add device-tree for LG Optimus 4X HD (P880)
c99ab6147bdd ARM: tegra: Add device-tree for LG Optimus Vu (P895)
9668ead0c4a9 ARM: tegra: nexus7: Add missing clock binding into sound node
1a7c7ca1209d dt-bindings: arm: tegra: Add LG Optimus Vu P895 and Optimus 4X P880
55fa85648879 arm64: dts: Add gpio_intc node for Amlogic-T7 SoCs
3040579f9058 dt-bindings: interrupt-controller: Add support for Amlogic-T7 SoCs
ac30a4ade02e dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Update interrupts
cf713971ea71 dt-bindings: arm-smmu: Add QCM2290 GPU SMMU
cfbcf932a683 arm64: dts: renesas: gray-hawk-single: Add QSPI FLASH support
7b0d1d64e101 arm64: dts: renesas: r8a779h0: Add RPC node
cf8ea631a9d7 arm64: dts: renesas: r8a779h0: Add DMA support
44de0122e321 arm64: dts: renesas: gray-hawk-single: Add eMMC support
697c226a4355 arm64: dts: renesas: r8a779h0: Add SD/MMC node
bc3ce3810946 ARM: dts: renesas: r8a7778: Add missing reg-names to sound node
59d2898af1c8 arm64: dts: renesas: rzg2ul-smarc: Enable CRU, CSI support
e4684cc943fe arm64: dts: renesas: gray-hawk-single: Add Ethernet support
08896ba8e650 arm64: dts: renesas: r8a779h0: Add Ethernet-AVB support
fe2d22e4ae91 arm64: dts: renesas: r8a779g0: Correct avb[01] reg sizes
4c2e92819772 arm64: dts: renesas: r8a779a0: Correct avb[01] reg sizes
d857aea85b27 arm64: dts: renesas: r9a08g045: Add PSCI support
ac45f97b1f9c arm64: dts: renesas: rzg3s-smarc-som: Guard Ethernet IRQ GPIO hogs
aef97a58051b arm64: dts: renesas: r9a08g045: Add missing interrupts to IRQC node
68b5a3b20687 arm64: dts: renesas: rzg2l: Add missing interrupts to IRQC nodes
5a4108c215f6 arm64: dts: renesas: r8a779h0: Add CA76 operating points
bd25260cfef9 arm64: dts: renesas: r8a779h0: Add CPU core clocks
291552f30777 arm64: dts: renesas: r8a779h0: Add CPUIdle support
20170eff3c40 arm64: dts: renesas: r8a779h0: Add secondary CA76 CPU cores
4c3851d7302a arm64: dts: renesas: r8a779h0: Add L3 cache controller
149125c48481 arm64: dts: renesas: r8a779h0: Add GPIO nodes
e6842397bea1 arm64: dts: renesas: gray-hawk-single: Add I2C0 and EEPROMs
4ab7a0fae505 arm64: dts: renesas: r8a779h0: Add I2C nodes
4f678406736f arm64: dts: renesas: ulcb-kf: Adapt sound 5v regulator to schematics
ab5123a5fcbb arm64: dts: renesas: ulcb-kf: Adapt 1.8V HDMI regulator to schematics
36bd3f79100c arm64: dts: renesas: ulcb-kf: Add regulators for PCIe ch1
d79c233e5296 arm64: dts: renesas: gray-hawk-single: Add serial console pin control
adb055f45503 arm64: dts: renesas: r8a779h0: Add pinctrl device node
393149daa9ec dt-bindings: net: wireless: mt76: allow all 4 interrupts for MT7981
abc93201d108 dt-bindings: net: wireless: mt76: add interrupts description for MT7986
6ff46183ee46 dt-bindings: memory: renesas,rpc-if: Document R-Car V4M support
caaf33bab010 dt-bindings: reset: mobileye,eyeq5-reset: add bindings
d627a28b5d6f dt-bindings: clock: mobileye,eyeq5-clk: add bindings
ebd3bcd073ce dt-bindings: clock: ast2600: Add FSI clock
d19d06cdbb21 dt-bindings: reset: mediatek: add MT7988 infracfg reset IDs
f907dd749888 dt-bindings: clock: mediatek: convert SSUSBSYS to the json-schema clock
77f559281267 dt-bindings: clock: mediatek: convert PCIESYS to the json-schema clock
5776acd8f40b dt-bindings: clock: mediatek: convert hifsys to the json-schema clock
2b71a4051c65 dt-bindings: arm: realview: Spelling s/ARM 11/Arm11/, s/Cortex A-/Cortex-A/
d5d9be3159cd ARM: dts: integrator: Fix up VGA connector
e7ff0fa9dc10 ARM: dts: versatile: Fix up VGA connector
5cc0ca358e86 ARM: dts: arm: realview: Fix development chip ROM compatible value
17690d898c6b arm64: dts: ti: k3-am62p: Add Wave5 Video Encoder/Decoder Node
1a04d9e2ea04 arm64: dts: ti: k3-j721s2-main: Add Wave5 Video Encoder/Decoder Node
037f82133c88 arm64: dts: ti: k3-j784s4: Add Wave5 Video Encoder/Decoder Node
b9b4934fd72d arm64: dts: ti: k3-am69-sk: Add support for OSPI flash
54bdd26cd110 arm64: dts: ti: k3-am69-sk: Enable CAN interfaces for AM69 SK board
5ddb529be866 arm64: dts: ti: k3-am62p: Add nodes for CSI-RX
2bc64591456d arm64: dts: ti: k3-am62p: Add DMASS1 for CSI
fb6e8cb37b07 arm64: dts: ti: k3-am62p: Fix memory ranges for DMSS
4a664d32a079 arm64: dts: ti: k3-j722s-evm: Enable OSPI NOR support
0a3c08b6205b arm64: dts: ti: k3-j722s-evm: Enable CPSW3G RGMII1
6d9068d2f3e7 arm64: dts: ti: k3-j784s4-main: Fix mux-reg-masks in serdes_ln_ctrl
8f04b7849578 arm64: dts: ti: k3-j721e: Fix mux-reg-masks in hbmc_mux
c3982938ea86 dt-bindings: display: renesas,rzg2l-du: Document RZ/V2L DU bindings
62d59754ec63 dt-bindings: display: Document Renesas RZ/G2L DU bindings
b9138e8af159 arm64: tegra: Use consistent SD/MMC aliases on Tegra234
dcff839661ba arm64: dts: amlogic: add fbx8am DT overlays
0d16b6bd5803 ARM: dts: gemini: Fix switch node names on Vitesse switches
81e1d1cfd2f9 ARM: dts: gemini: Map reset keys to KEY_RESTART
915ebb1bf1e0 ARM: dts: gemini: Fix wiligear compatible strings
d8869f38c863 ARM: dts: gemini: Fix switch node names in the DIR-685
4466332a360b ASoC: dt-bindings: qcom,wsa8840: Add reset-gpios for shared line
8d8332ce62c5 dt-bindings: reset: sophgo: support SG2042
357d5bbac5af ASoC: Intel: avs: Fixes and new platforms support
ed4851e1d924 regulator: dt-bindings: qcom,usb-vbus-regulator: add support for PM4125
bcf5ae8600f6 regulator: dt-bindings: qcom,usb-vbus-regulator: add support for PM4125
90ad8fbfa7f9 Merge tag 'memory-controller-drv-6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl into soc/drivers
6a8fb7b89e73 arm64: dts: qcom: sm6115: fix USB PHY configuration
0dc3ecab7183 Merge tag 'linux-can-next-for-6.9-20240220' of git://git.kernel.org/pub/scm/linux/kernel/git/mkl/linux-can-next
f923d17647b5 MIPS: mobileye: Add EPM5 device tree
885d1e731299 MIPS: mobileye: Add EyeQ5 dtsi
7fb9ce7c1dde dt-bindings: mips: Add bindings for Mobileye SoCs
e3797e6a3708 dt-bindings: mips: cpu: Add I-Class I6500 Multiprocessor Core
9a705909b63d dt-bindings: mips: cpus: Sort the entries
e0340332869b dt-bindings: Add vendor prefix for Mobileye Vision Technologies Ltd.
011bf078c7bc dt-bindings: pinctrl: renesas,pfc: Document R-Car V4M support
49888873d596 dt-bindings: net: fec: add iommus property
80733980e6ba dt-bindings: iio: adc: ti-ads1298: Add bindings
26a3005ca5c0 dt-bindings: iio: pressure: honeywell,hsc030pa.yaml add spi props
d64846638639 dt-bindings: adc: axi-adc: update bindings for backend framework
a3fc6ec1428b dt-bindings: adc: ad9467: add new io-backend property
c0d436471a5f regulator: Merge up v6.8-rc5
52dcafce5828 dt-bindings: regulator: qcom,usb-vbus-regulator: Add PM6150 compatible
66f7b7966dfc arm64: dts: ti: Add common1 register space for AM62A SoC
6b911cea73bb arm64: dts: ti: Add common1 register space for AM62x SoC
bb6e999b30ab arm64: dts: ti: Add common1 register space for AM65x SoC
2a98a4ff884d arm64: dts: mt8195-cherry-tomato: change watchdog reset boot flow
b5c66885729f dt-bindings: display: simple: Add boe,bp082wx1-100 8.2" panel
0b9a359a81b7 dt-bindings: display: ti,am65x-dss: Add support for common1 region
0033e16adcd4 dt-bindings: renesas: Document preferred compatible naming
1771fa16d31e dt-bindings: ata: convert MediaTek controller to the json-schema
127ae13f4e5e arm64: dts: mt7986: add port@5 as CPU port
57f255ff84ed arm64: dts: mt7622: add port@5 as CPU port
1e471beb8eea ARM: dts: meson8b: fix &hwrng node compatible string
320da6153b8a ARM: dts: meson8: fix &hwrng node compatible string
9625cfa0c727 ARM: dts: meson: fix bus node names
f496b04c1652 arm64: dts: amlogic: add fbx8am board
686e2be425fd dt-bindings: arm: amlogic: add fbx8am binding
48371b0670ac dt-bindings: vendor-prefixes: add freebox
471f9b9dd5e2 arm64: dts: amlogic: replace underscores in node names
6e0fb3cc9b68 arm64: dts: ti: k3-am642-evm: add overlay for ICSSG1 2nd port
7526121625ee dt-bindings: interconnect: qcom,rpmh: Fix bouncing @codeaurora address
fcda7c3e7ef7 Merge 6.8-rc5 into usb-next
670cbcdfbb09 arm64: dts: ti: k3-am642-evm: add ICSSG1 Ethernet support
cea3277e3b5e arm64: dts: ti: k3-am64-main: Add ICSSG IEP nodes
eb0aea3a7c5a Merge 6.8-rc5 into tty-next
c07c11c8be59 arm64: dts: ti: k3-am6*: Add bootph-all property in MMC node
59d465b82cb4 arm64: dts: ti: k3-am6*: Fix bus-width property in MMC nodes
16af8c673aff arm64: dts: ti: k3-am6*: Fix ti,clkbuf-sel property in MMC nodes
87f154491e63 arm64: dts: ti: k3-am6*: Remove DLL properties for soft PHYs
722bd88c8fab arm64: dts: ti: k3-am62p: Add ITAP/OTAP values for MMC
18c8263c1ec1 arm64: dts: ti: k3-am64-main: Fix ITAP/OTAP values for MMC
73f1cbbcb198 arm64: dts: ti: k3-am62a7-sk: Enable eMMC support
973681d9002a arm64: dts: ti: k3-am62a-main: Add sdhci2 instance
4430a5c5a0ec arm64: dts: ti: k3-am62a-main: Add sdhci0 instance
be340f86aaf1 arm64: dts: sm8650: Add msi-map-mask for PCIe nodes
49cf8bb8b63f arm64: dts: qcom: replace underscores in node names
8f9d0aa368d0 ARM: dts: qcom: samsung-matisse-common: Add UART
ce30f2d31d9c ARM: dts: qcom: Add support for Samsung Galaxy Tab 4 10.1 LTE (SM-T535)
afbdd6233c4a ARM: dts: qcom: samsung-matisse-common: Add initial common device tree
6a80ca4b242a dt-bindings: arm: qcom: Add Samsung Galaxy Tab 4 10.1 LTE
3cef33d6916c dt-bindings: soc: qcom: qcom,saw2: add msm8226 l2 compatible
e4d2d663cf96 arm64: dts: ti: k3-j784s4-evm: Remove Pinmux for CTS and RTS in wkup_uart0
d43ac341179d arm64: dts: ti: k3-j721s2-common-proc-board: Remove Pinmux for CTS and RTS in wkup_uart0
80e20b3b69c9 arm64: dts: ti: k3-j7200-common-proc-board: Remove clock-frequency from mcu_uart0
35877fcaea3a arm64: dts: ti: k3-j7200-common-proc-board: Modify Pinmux for wkup_uart0 and mcu_uart0
cac67785c0a6 arm64: dts: ti: k3-j721e-sk: Add overlay for IMX219
b1d7814ca372 arm64: dts: ti: k3-j784s4-main: Add CSI2RX capture nodes
b6b2d86e2411 arm64: dts: ti: k3-j721s2-main: Add CSI2RX capture nodes
58403c60add6 arm64: dts: ti: k3-j721e-main: Add CSI2RX capture nodes
4796014c5f92 arm64: dts: ti: k3-j721e-sk: Model CSI2RX connector mux
b599ef1ba8ff arm64: dts: ti: k3-am69-sk: Enable camera peripherals
248c870c7bd6 arm64: dts: ti: k3-am68-sk-base-board: Enable camera peripherals
a5f6b550f77b arm64: dts: ti: k3-j784s4-evm: Enable camera peripherals
f70c4ae50ecf arm64: dts: ti: k3-j721s2-common-proc-board: Enable camera peripherals
4141c6b09a96 dt-bindings: i3c: drop "master" node name suffix
f3ca3a16bd19 dt-bindings: timer: nxp,sysctr-timer: support i.MX95
19b1a141c8dd dt-bindings: usb: qcom,pmic-typec: add support for the PMI632 block
15c348192cc2 dt-bindings: regulator: qcom,usb-vbus-regulator: add support for PMI632
3c201cdbc89a dt-bindings: iio: humidity: hdc3020: add interrupt bindings in example
0fc77339f456 dt-bindings: iio: afe: voltage-divider: Add io-channel-cells
7adf6f669393 dt-bindings: iio: imu: st_lsm6dsx: add asm330lhhxg1
bd37e5428ced dt-bindings: iio: frequency: add admfm2000
f6c7124a3d91 dt-bindings: usb/ti,am62-usb.yaml: Add PHY2 register space
3102faf7d698 dt-bindings: usb: microchip,usb5744: Remove peer-hub as requirement
d403cb0d5128 arm64: dts: qcom: qcm6490-fairphone-fp5: Add PMIC GLINK
7ab947b60396 dt-bindings: usb: dwc3: drop 'snps,host-vbus-glitches-quirk'
e007ca0c7920 ASoC: dt-bindings: Update example for enabling USB offload on SM8250
14bd5c629408 ASoC: dt-bindings: Add Q6USB backend
86b2f37571d9 arm64: dts: ti: Add reserved memory for watchdog
0ffb30594139 arm64: dts: qcom: pm4125: define USB-C related blocks
437f7c2c748a arm64: dts: qcom: sa8540p-ride: disable pcie2a node
ddc97b021a4f arm64: dts: qcom: sc7280: add slimbus DT node
174b19d0a453 dt-bindings: display: ltk500hd1829: add variant compatible for ltk101b4029w
9990fd362767 dt-bindings: display: panel-lvds: Add compatible for admatec 9904370 panel
3a9936a295c2 dt-bindings: vendor-prefixes: add prefix for admatec GmbH
11b2a690403f arm64: dts: qcom: sc7280: Add capacity and DPC properties
23437543023d ARM: dts: qcom: ipq8064: drop 'regulator' property from SAW2 devices
cabc075cf325 ARM: dts: qcom: ipq4019: drop 'regulator' property from SAW2 devices
484c003d94ab ARM: dts: qcom: msm8974: drop 'regulator' property from SAW2 device
6445cb8886be ARM: dts: qcom: apq8084: drop 'regulator' property from SAW2 device
98ba5545146c ARM: dts: qcom: msm8960: declare SAW2 regulators
b54dea12770f ARM: dts: qcom: apq8064: declare SAW2 regulators
4dce2cf9f83d ARM: dts: qcom: ipq8064: rename SAW nodes to power-manager
5b13a9611268 ARM: dts: qcom: ipq4019: rename SAW nodes to power-manager
0ec0f547bc86 ARM: dts: qcom: msm8974: rename SAW nodes to power-manager
9c6828f9c895 ARM: dts: qcom: msm8960: rename SAW nodes to power-manager
d5acf25ed148 ARM: dts: qcom: apq8084: rename SAW nodes to power-manager
643db1cecca9 ARM: dts: qcom: apq8064: rename SAW nodes to power-manager
4de620145e88 ARM: dts: qcom: ipq8064: use SoC-specific compatibles for SAW2 devices
c44fb47e47a5 ARM: dts: qcom: ipq4019: use SoC-specific compatibles for SAW2 devices
5e99522aa387 ARM: dts: qcom: msm8960: use SoC-specific compatibles for SAW2 devices
75a6d010f715 ARM: dts: qcom: msm8974: use new compat string for L2 SAW2 unit
9eb4395e3cbc ARM: dts: qcom: apq8084: use new compat string for L2 SAW2 unit
0cc21b045573 arm64: dts: qcom: pmi632: Add PBS client and use in LPG node
adaff156bd89 arm64: dts: qcom: sm8550: Use GIC-ITS for PCIe0 and PCIe1
567a4e2c1bfd arm64: dts: qcom: sm8150: correct PCIe wake-gpios
aff4851c71af arm64: dts: qcom: sdm845-db845c: correct PCIe wake-gpios
d12e2e81b378 dt-bindings: soc: qcom: qcom,saw2: define optional regulator node
87cb0efb080c dt-bindings: soc: qcom: qcom,saw2: add missing compatible strings
78779d5162e9 dt-bindings: soc: qcom: merge qcom,saw2.txt into qcom,spm.yaml
90689200835c arm64: dts: qcom: sm7225-fairphone-fp4: Enable display and GPU
49fc8baa3dd8 arm64: dts: qcom: sm6350: Remove "disabled" state of GMU
3bb88ee4bafc dt-bindings: clk: qcom: drop the SC7180 Modem subsystem clock controller
08488eb0c95c arm64: dts: qcom: msm8916-samsung-fortuna/rossa: Add fuel gauge
9230383364ef arm64: dts: qcom: sm6350: Add interconnect for MDSS
93d1070a237b dt-bindings: can: xilinx_can: Add 'xlnx,has-ecc' optional property
09c2905a6449 dt-bindings: renesas,rcar-dmac: Add r8a779h0 support
8500691f667d dt-bindings: dma: convert MediaTek High-Speed controller to the json-schema
7b382eea018b arm64: tegra: Enable cros-ec-spi as wake source
73f09474de21 ARM: tegra: Enable cros-ec-spi as wake source
9c3c23577ad9 dt-bindings: tegra: pmc: Update scratch as an optional aperture
296aea7e0f2a dt-bindings: display: panel: Add Himax HX83112A
5b0ce634f06d dt-bindings: phy: Add Rockchip HDMI/eDP Combo PHY schema
01f41446bb7f Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
87dd58b7c6ca dt-bindings: mmc: renesas,sdhi: Document R-Car V4M support
ec136bb18fcc arm64: dts: ti: Add support for TI J722S Evaluation Module
4dd9e11aa40f arm64: dts: ti: Introduce J722S family of SoCs
1339c374a4c1 dt-bindings: arm: ti: Add bindings for J722S SoCs
723c10f0bd63 arm64: dts: ti: iot2050: Support IOT2050-SM variant
4a95da5a5df9 arm64: dts: ti: iot2050: Annotate LED nodes
a2119b7f92bd arm64: dts: ti: iot2050: Factor out DP related bits
a3f672abd86f arm64: dts: ti: iot2050: Factor out enabling of USB3 support
0f7fd425cef9 arm64: dts: ti: iot2050: Factor out arduino connector bits
326a69a3e459 arm64: dts: ti: iot2050: Disable R5 lockstep for all PG2 boards
9f6227cced13 dt-bindings: arm: ti: Add binding for Siemens IOT2050 SM variant
4c8ad6e37e97 arm64: dts: ti: k3-am62-main: disable usb lpm
58003d5a29e5 arm64: dts: ti: verdin-am62: Set VDD CORE minimum voltage to 0.75V
09148e5825bc arm64: dts: ti: k3-am62-wakeup: Configure ti-sysc for wkup_uart0
8d7152a47403 arm64: dts: ti: am62-phyboard-lyra: Add overlay to enable a GPIO fan
16c636f5b152 arm64: dts: ti: k3-j721e-sk: fix PMIC interrupt number
2932b4306805 arm64: dts: ti: k3-am69-sk: fix PMIC interrupt number
f6c375e9f85d arm64: dts: ti: verdin-am62: add support for Verdin USB1 interface
309045be68da arm64: dts: ti: Add DT overlay for PCIe + USB3.0 SERDES personality card
2979217a850f arm64: dts: ti: Add DT overlay for PCIe + USB2.0 SERDES personality card
b70ff6a5d411 dt-bindings: w1: UART 1-Wire bus
21e00d907bfb dt-bindings: serial: allow onewire as child node
1f162c88f711 dt-bindings: pwm: mediatek,mt2712: add compatible for MT7988
b69225cd6653 dt-bindings: atmel,hlcdc: convert pwm bindings to json-schema
4fc4f31db241 dt-bindings: pxa-pwm: Convert to YAML
61f4ac7c5c90 ARM: dts: vexpress: Set stdout-path to serial0 in the chosen node
199bf4b635e6 arm64: dts: mediatek: Replace deprecated extcon-usb-gpio id-gpio/vbus-gpio properties
73d46717fb3d ARM: dts: qcom: msm8226: Add watchdog node
01815a93d9ab dt-bindings: auxdisplay: hit,hd44780: use defines for GPIO flags
41e657a00f9c dt-bindings: auxdisplay: adjust example indentation and use generic node names
81b0dd090434 arm64: dts: qcom: msm8916-samsung-fortuna/rossa: Add initial device trees
3fa556edfd69 arm64: dts: qcom: sm8550: Switch UFS from opp-table-hz to opp-v2
8761bb9477f3 arm64: dts: qcom: sc8180x: describe all PCI MSI interrupts
3419b50ca541 arm64: dts: qcom: minor whitespace cleanup
1a30651d27f6 arm64: dts: qcom: ssm7125-xiaomi: drop incorrect UFS phy max current
8f644a3c370b arm64: dts: qcom: x1e80100-crd: add sound card
22e29ff5c4c3 arm64: dts: x1e80100: correct DMIC2 and DMIC3 pin config node names
b32ccff427b3 arm64: dts: sm8650: correct DMIC2 and DMIC3 pin config node names
8b41c24a5900 arm64: dts: sm8550: correct DMIC2 and DMIC3 pin config node names
d0bad83ec278 arm64: dts: sm8450: correct DMIC2 and DMIC3 pin config node names
736ebb0686f6 arm64: dts: sc8280xp: correct DMIC2 and DMIC3 pin config node names
33ef3b7fb778 dt-bindings: can: tcan4x5x: Document the wakeup-source flag
11322433ed0f dt-bindings: net: dp83826: support TX data voltage tuning
a745442704dd ARM: dts: stm32: lxa-tac: reduce RGMII interface drive strength
bdbd2fbe2a1f arm64: dts: mediatek: replace underscores in node names
bb7b4de1613f pmdomain: Merge branch dt into next
20b8bae8b8eb arm64: dts: ti: k3-am62a: Make the main_conf node a simple-bus
e42f80bc5bcf arm64: dts: ti: k3-am62: Make the main_conf node a simple-bus
8ba7dd15abdd arm64: dts: ti: k3-j7200: Make the FSS node a simple-bus
42ed47d60a80 arm64: dts: ti: k3-j721s2: Convert serdes_ln_ctrl node into reg-mux
bf6f8e6f98e5 arm64: dts: ti: k3-j721s2: Convert usb_serdes_mux node into reg-mux
0167a788d9c5 arm64: dts: ti: k3-j721e: Convert usb_serdes_mux node into reg-mux
124c59a52517 arm64: dts: ti: k3-j721e: Convert serdes_ln_ctrl node into reg-mux
ebb5990bd126 arm64: dts: ti: k3-j7200: Convert usb_serdes_mux node into reg-mux
c0c92c3b24bd arm64: dts: ti: k3-j7200: Convert serdes_ln_ctrl node into reg-mux
8c7e27a256ed arm64: dts: ti: k3-am64: Convert serdes_ln_ctrl node into reg-mux
ecaaf99dee6f arm64: dts: mediatek: mt8186: Add missing xhci clock to usb controllers
546dd2b71775 arm64: dts: mediatek: mt8186: Add missing clocks to ssusb power domains
845392fb2a8c ARM: dts: qcom: msm8960: expressatt: Add mXT224S touchscreen
a5fc0fcda8d3 ARM: dts: qcom: msm8960: Add gsbi3 node
e5357a45e304 ARM: dts: qcom: msm8226: Add CPU and SAW/ACC nodes
df98c13b52f1 ARM: dts: qcom: msm8226: Sort and clean up nodes
4250f1c8ff79 ARM: dts: qcom: msm8974: correct qfprom node size
7d8cff577be7 dt-bindings: arm: qcom,ids: Add IDs for SM8475 family
ee8caed03c87 arm64: dts: qcom: sdm845: Enable cros-ec-spi as wake source
6eef1cbc79c9 arm64: dts: qcom: sc7280: Enable cros-ec-spi as wake source
097f3128d091 arm64: dts: qcom: sc7180: Enable cros-ec-spi as wake source
1a1c9101358c arm64: dts: qcom: sdm845: Use the Low Power Island CX/MX for SLPI
292108e317ec arm64: dts: qcom: msm8996: Define UFS UniPro clock limits
71aab956985a arm64: dts: qcom: qcs6490-rb3gen2: Declare GCC clocks protected
5a7b32324b50 arm64: dts: qcom: sc8280xp-pmics: Define adc for temp-alarms
c7cdefde3890 arm64: dts: qcom: sc8280xp-crd: Add PMIC die-temp vadc channels
fc4657cf641c dt-bindings: net: qca,ar9331: convert to DT schema
f8930a53d1df arm64: dts: rockchip: Add USB3.0 to Indiedroid Nova
5e1a3b5538e5 arm64: dts: rockchip: adjust phy-handle name on rock-pi-e
67a655c02d0c arm64: dts: rockchip: fix rk3399 hdmi ports node
1ce4f570403a arm64: dts: rockchip: fix rk3328 hdmi ports node
fe75fb3e4156 ARM: dts: rockchip: fix rk322x hdmi ports node
d8715fea4366 ARM: dts: rockchip: fix rk3288 hdmi ports node
3693fdfce256 dt-bindings: display: rockchip,dw-hdmi: add power-domains property
a3f511793cc1 dt-bindings: display: rockchip: rockchip,dw-hdmi: remove port property
fdad3ea0d962 arm64: dts: rockchip: remove redundant cd-gpios from rk3588 sdmmc nodes
1619cbd3e975 arm64: dts: rockchip: add rs485 support on uart5 of px30-ringneck-haikou
2134fa3eaa7f arm64: dts: rockchip: add rs485 support on uart2 of rk3399-puma-haikou
7a4285c5d69e arm64: dts: rockchip: Add Powkiddy RGB10MAX3
b9b257004011 dt-bindings: arm: rockchip: Add Powkiddy RGB10MAX3
a3adfa889806 arm64: dts: rockchip: Update powkiddy rk2023 dtsi for RGB10MAX3
8c24e7309a68 dt-bindings: display: rocktech,jh057n00900: Document panel rotation
46ed672258f7 dt-bindings: display: Add Powkiddy RGB10MAX3 panel
01125f93dff3 dt-bindings: soc: rockchip: add rk3588 USB3 syscon
f12733bf8794 dt-bindings: soc: rockchip: add clock to RK3588 VO grf
94e3c5a3f928 docs: dt: writing-schema: document expectations on example DTS
fe91d6f4b5e3 docs: dt: writing-schema: explain additional/unevaluatedProperties
4a3d3359c02d docs: dt: writing-schema: clarify that schema should describe hardware
d91bf686801b dt-bindings: use capital "OR" for multiple licenses in SPDX
496c29b2e9a6 dt-bindings: vendor-prefixes: add smartrg
24ffa3c14c93 dt-bindings: misc: qcom,fastrpc: Compute callbacks can be DMA coherent
0723544f32df dt-bindings: soc: renesas: Preserve the order of SoCs based on their part numbers
a6d969083d23 clk: renesas: r8a779g0: Correct PFC/GPIO parent clocks
1c22386104aa ASoC: dt-bindings: fsl,imx-asrc: convert to YAML
0a4520722599 dt-bindings: timer: renesas: ostm: Document RZ/Five SoC
82515ffc20b0 dt-bindings: mmc: fsl-imx-esdhc: add iommus property
54b4d099b066 dt-bindings: mmc: fsl-imx-esdhc: add i.MX95 compatible string
878060d5ab93 dt-bindings: power: rpmpd: Add MSM8974 power domains
ba7f2dd56d71 arm64: dts: amlogic: t7: minor whitespace cleanup
0e3777330164 Merge tag 'renesas-pinctrl-for-v6.9-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel
2b637c08d90d arm64: dts: amlogic: axg: initialize default SoC capacitance
56b8815ee298 arm64: dts: amlogic: axg: move cpu cooling-cells to common dtsi
38e9d49495a7 arch: arm64: dts: meson: a1: add assigned-clocks for usb node
04303030d8a7 arm64: dts: amlogic: meson-g12-common: Set the rates of the clocks for the NPU
96f1514933cd arm64: dts: amlogic: add reset controller for Amlogic C3 SoC
b6cee0d8e50c dt-bindings: i2c: mux: i2c-demux-pinctrl: Define "i2c-parent" constraints
cbcbd116c3bb dt-bindings: i2c: mux: i2c-demux-pinctrl: Drop i2c-mux.yaml reference
d21de1b0f205 dt-bindings: can: fsl,flexcan: add i.MX95 compatible string
18dd617a729c ASoC: dt-bindings: cs35l45: Add interrupts
d649337cab0d ASoC: dt-bindings: qcom,sm8250: Allow up to 8 codec DAIs
168cf4050131 arm64: dts: fsd: Add fifosize for UART in Device Tree
c49f54ab8258 arm64: dts: exynos: gs101: minor whitespace cleanup
761c7555e3a6 arm64: dts: mediatek: mt7622: add missing "device_type" to memory nodes
feb82cd75ca1 arm64: dts: mediatek: mt7986: reorder nodes
afeb2b683c6a arm64: dts: mediatek: mt7986: reorder properties
1f41c46b7784 arm64: dts: mediatek: Add Acelink EW-7886CAX
a9e4cb01cbbd dt-bindings: arm64: dts: mediatek: Add Acelink EW-7886CAX access point
a0d0e301bacb dt-bindings: vendor-prefixes: add acelink
6355f4d21fe2 arm64: dts: mediatek: Introduce the MT8395 Radxa NIO 12L board
ad8297de07f0 dt-bindings: arm64: mediatek: Add MT8395 Radxa NIO 12L board compatible
c878dc2878b8 arm64: dts: mediatek: mt8186: Add video decoder device nodes
86ae11dcbfb0 arm64: dts: mediatek: mt8195: Add MTU3 nodes and correctly describe USB
a1bccd014f43 arm64: dts: mediatek: Add MT8186 Magneton Chromebooks
f06a044c7c87 arm64: dts: mediatek: Add MT8186 Steelix platform based Rusty
3d00e9da10ee arm64: dts: mediatek: Introduce MT8186 Steelix
2047c128ed63 arm64: dts: mediatek: Add MT8186 Krabby platform based Tentacruel / Tentacool
0526f7bc6fb8 dt-bindings: arm: mediatek: Add MT8186 Magneton Chromebooks
089e49677706 dt-bindings: arm: mediatek: Add MT8186 Rusty Chromebook
f9d037124e77 dt-bindings: arm: mediatek: Add MT8186 Steelix Chromebook
f5956f4a6314 dt-bindings: arm: mediatek: Add MT8186 Tentacruel / Tentacool Chromebooks
38bba08bb5f5 dt-bindings: arm: mediatek: Sort entries by SoC then board compatibles
ae447c85bffd arm64: dts: mediatek: mt8186: Add jpgenc node
2ee45888f0f1 dt-bindings: media: mediatek-jpeg-encoder: change max iommus count
9dd1d78b9108 arm64: dts: mediatek: mt8186: Add venc node
928e533f64ce arm64: dts: mediatek: mt8186: fix VENC power domain clocks
10ccafc6dfc8 dt-bindings: media: mtk-vcodec-encoder: add compatible for mt8186
a26c81acaef4 arm64: dts: mediatek: mt8192: fix vencoder clock name
6d5ecd0c0bf1 dt-bindings: media: mtk-vcodec-encoder: fix non-vp8 clock name
44858bf6309d arm64: dts: mediatek: Add socinfo efuses to MT8173/83/96/92/95 SoCs
87674b38b34a arm64: dts: mediatek: mt8195: Enable cros-ec-spi as wake source
a5e0493deb44 arm64: dts: mediatek: mt8192: Enable cros-ec-spi as wake source
d8de0db07270 arm64: dts: mediatek: mt8183: Enable cros-ec-spi as wake source
e62bf57bf4ce arm64: dts: mediatek: mt8173: Enable cros-ec-spi as wake source
80f419da8e71 arm64: dts: mediatek: mt7988: add clock controllers
0da54052e647 arm64: dts: mediatek: Add initial MT7988A and BPI-R4
17df9b07965f dt-bindings: arm64: mediatek: Add MT7988A and BPI-R4
58b0724c52ef arm64: dts: mediatek: Add initial MT7981B and Xiaomi AX3000T
f2654823e7da dt-bindings: arm64: mediatek: Add MT7981B and Xiaomi AX3000T
ec60c59a2f5a arm64: dts: mediatek: mt8192-asurada: Remove CrosEC base detection node
4cc812e03139 arm64: dts: mediatek: mt7986: add "#reset-cells" to infracfg
a70fe7a32743 arm64: dts: mediatek: mt7986: drop "#clock-cells" from PWM
08e6a51e82bf arm64: dts: mediatek: mt7986: fix SPI nodename
0ce82b652753 arm64: dts: mediatek: mt7986: fix SPI bus width properties
1654679b7b86 arm64: dts: mediatek: mt7986: drop crypto's unneeded/invalid clock name
0db4b3814808 arm64: dts: mediatek: mt7986: fix reference to PWM in fan node
e14ff64a492a arm64: dts: mt8183: Move CrosEC base detection node to kukui-based DTs
5af22a48d387 dt-bindings: net: qcom,ethqos: add binding doc for safety IRQ for sa8775p
f0efaf410576 dt-bindings: arm: qcom,coresight-tpdm: Add support for TPDM CMB MSR register
a31e6ce97f3b dt-bindings: arm: qcom,coresight-tpdm: Add support for CMB element size
42aa700e6b6a Merge tag 'v6.8-rc4' into gpio/for-next
28ff43a9c5cf dt-bindings: hwmon: Add LTC4282 bindings
946976867e95 dt-bindings: hwmon: ina2xx: Describe ina260 chip
60a5255306fa dt-bindings: hwmon: ina2xx: Describe #io-channel-cells property
ccda6b1eb4cb dt-bindings: hwmon: ina2xx: Add label property
29abc2d8cf78 dt-bindings: display: msm: sm8650-mdss: Add missing explicit "additionalProperties"
ca193aa48798 dt-bindings: msm: qcom, mdss: Include ommited fam-b compatible
fb87bba01a93 dt-bindings: dsi-controller-main: Document missing msm8976 compatible
6e32138572e8 dt-bindings: net: Document Qcom QCA807x PHY package
d65891d631e7 dt-bindings: net: document ethernet PHY package nodes
05327165c680 arm64: dts: qcom: qrb4210-rb2: enable USB-C port handling
c48cf2ca774b arm64: dts: qcom: sm6115: drop pipe clock selection
0529c70be68e arm64: dts: qcom: pmi632: define USB-C related blocks
8f3c2d458408 arm64: dts: qcom: qcs6490-rb3gen2: Correct the voltage setting for vph_pwr
f077c9e8cdcc arm64: dts: qcom: qcm6490-idp: Correct the voltage setting for vph_pwr
ed36b9e79976 dt-bindings/perf: Add Arm CoreSight PMU
6bea5f945518 dt-bindings: pinctrl: cy8c95x0: Update gpio-reserved-ranges
ff6ea0429974 dt-bindings: pinctrl: nvidia,tegra234-pinmux: Restructure common schema
f8a5525e9f69 Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
b64c0f80d53a spi: get rid of some legacy macros
adfae82db04a spi: dt-bindings: samsung: add google,gs101-spi compatible
7d4159bca342 dt-bindings: mfd: dlg,da9063: Convert da9062 to json-schema
84465d53e06e dt-bindings: mfd: dlg,da9063: Sort child devices
a5d5c9ca95f6 dt-bindings: thermal: Convert da906{1,2} thermal to json-schema
9491d890e23c dt-bindings: input: Convert da906{1,2,3} onkey to json-schema
bf94a53ad831 dt-bindings: mfd: dlg,da9063: Update watchdog child node
5d2f1ff23c1f dt-bindings: mfd: da9062: Update watchdog description
6d63119dedee dt-bindings: soc: qcom: qcom,pmic-glink: document QCM6490 compatible
eadfdbf7cfd7 dt-bindings: i2c: renesas,rcar-i2c: Add r8a779h0 support
506140c4b36b dt-bindings: i2c: pca954x: Add custom properties for MAX7357
a3cf64f59235 arm64: dts: exynos: gs101: enable i2c bus 12 on gs101-oriole
66fd6a721305 arm64: dts: exynos: gs101: define USI12 with I2C configuration
bc3a8ffe73f6 arm64: dts: exynos: gs101: enable cmu-peric1 clock controller
85f5d68af4a0 Merge tag 'samsung-dt-bindings-clk-6.9-3' into next/dt64
eff597e8d6d7 Merge branch '20240131-ufs-phy-clock-v3-3-58a49d2f4605@linaro.org' into clk-for-6.9
9d58463252f8 Merge branch '20240125-msm8953-mdss-reset-v2-1-fd7824559426@z3ntu.xyz' into clk-for-6.9
53156f9a9b8b dt-bindings: samsung: exynos-sysreg: gs101-peric0/1 require a clock
f0fc02f810bc Merge tag 'samsung-dt-bindings-clk-6.9-3' into next/clk
3a17e325742d dt-bindings: clock: google,gs101-clock: add PERIC1 clock management unit
f8f976624cd6 ASoC: dt-bindings: atmel,asoc-wm8904: Convert to json-schema
e07e6605bd92 ARM: dts: samsung: exynos5420-galaxy-tab-common: add wifi node
833d20d41eff dt-bindings: phy: add mediatek MIPI CD-PHY module v0.5
0aff1be67191 dt-bindings: phy: cadence-torrent: Add a separate compatible for TI J7200
61354e32b738 dt-bindings: phy: cadence-torrent: Add optional input reference clock for PLL1
0ed441cb60fc Merge drm/drm-next into drm-misc-next
fa4e28b76a28 dt-bindings: phy: qmp-ufs: Fix PHY clocks
edf14e92f825 dt-bindings: fsl-dma: fsl-edma: add fsl,imx95-edma5 compatible string
db56af9d1adc dt-bindings: mmp-dma: convert to YAML
69f5e9afcf9a arm64: dts: qcom: sc8280xp: Introduce additional tsens instances
d34aa18b328e arm64: dts: qcom: sm8550-hdk: correct WCD9385 route and port mapping
c5ac3bf2b9e9 arm64: dts: qcom: sm8650: Fix UFS PHY clocks
960dc14fb417 arm64: dts: qcom: sm8550: Fix UFS PHY clocks
5b487a71e59a arm64: dts: qcom: sm8350: Fix UFS PHY clocks
1019d3b3dd76 arm64: dts: qcom: sc8280xp: Fix UFS PHY clocks
d909cc2c57f0 arm64: dts: qcom: sc8180x: Fix UFS PHY clocks
32798a824479 Merge branch '20240131-ufs-phy-clock-v3-3-58a49d2f4605@linaro.org' into HEAD
647fc2ed0999 dt-bindings: trivial-devices: sort entries alphanumerically
d87ada5ab8a5 arm64: dts: qcom: sm8250: Fix UFS PHY clocks
71ea2327fa6f arm64: dts: qcom: sm8150: Fix UFS PHY clocks
64da7648e2cd arm64: dts: qcom: sm6350: Fix UFS PHY clocks
fd0f61fefaf5 arm64: dts: qcom: sm6125: Fix UFS PHY clocks
4d7ec8559332 arm64: dts: qcom: sm6115: Fix UFS PHY clocks
1b77533e4915 arm64: dts: qcom: sdm845: Fix UFS PHY clocks
18872b4ddd5f arm64: dts: qcom: msm8998: Fix UFS PHY clocks
9a197a6489bc arm64: dts: qcom: msm8996: Fix UFS PHY clocks
1c92660aee2a dt-bindings: clock: qcom: Add missing UFS QREF clocks
a20d2718cc23 arm64: dts: qcom: ipq8074: add clock-frequency to MDIO node
6ed4e54f3d0a arm64: dts: qcom: qrb2210-rb1: disable cluster power domains
1816222d14d0 arm64: dts: qcom: msm8953: Add GPU
289d949a2fa0 arm64: dts: qcom: msm8953: Add GPU IOMMU
d8789c7d4887 arm64: dts: qcom: msm8953: add reset for display subsystem
e3e73e0578cb Merge branch '20240125-msm8953-mdss-reset-v2-1-fd7824559426@z3ntu.xyz' into arm64-for-6.9
6beb0be6d4fc dt-bindings: clock: gcc-msm8953: add more resets
f84a5b88e932 arm64: dts: qcom: sm8650-mtp: add Audio sound card node
92c1bbcc400a arm64: dts: qcom: sm8650-qrd: add Audio nodes
b0e0830701c8 arm64: dts: qcom: sm8650: Add dma-coherent property
d16840039a98 arm64: dts: qcom: sm8550: Add dma-coherent property
f515a57656b3 arm64: dts: qcom: sm8650-qrd: add PM8010 regulators
03371084ea86 arm64: dts: qcom: sm8650-mtp: add PM8010 regulators
a5d205597cdb arm64: dts: qcom: ipq6018: add thermal zones
a536a392c199 arm64: dts: qcom: ipq6018: add tsens node
93475982136a arm64: dts: qcom: sm8550-mtp: add correct analogue microphones
94d226438171 arm64: dts: qcom: sm8550-qrd: add correct analogue microphones
da9e6dd17060 arm64: dts: qcom: sm8550-mtp: correct WCD9385 TX port mapping
19f3548ab2ee arm64: dts: qcom: sm8550-qrd: correct WCD9385 TX port mapping
70387c1a6e20 arm64: dts: qcom: sm6350: Add tsens thermal zones
14a45c7e6691 arm64: dts: qcom: sm6115: declare VLS CLAMP register for USB3 PHY
62ceca9a978f arm64: dts: qcom: qcm2290: declare VLS CLAMP register for USB3 PHY
1243c8cd7c3d arm64: dts: qcom: msm8998: declare VLS CLAMP register for USB3 PHY
41b532e3d8fb arm64: dts: qcom: sc7280: Update domain-idle-states for cluster sleep
9067770d28da arm64: dts: qcom: sdm630-nile: Enable and configure PM660L WLED
59950318f199 dt-bindings: arm: qcom: drop the superfluous device compatibility schema
5906b6dbb4b8 arm64: dts: qcom: sm8650: add missing qlink_logging reserved memory for mpss
1a5594201259 arm64: dts: qcom: ipq9574: Enable Inline Crypto Engine for MMC
6c5dcfe50eeb arm64: dts: qcom: x1e80100-crd: add WSA8845 speakers
641aa52f01a1 arm64: dts: qcom: x1e80100-crd: add WCD9385 Audio Codec
adad71a77e32 arm64: dts: qcom: x1e80100: add Soundwire controllers
fcb540f3e31d arm64: dts: qcom: x1e80100: add ADSP audio codec macros
fe7149ac0fe1 arm64: dts: qcom: x1e80100: add LPASS LPI pin controller
89656eaec676 arm64: dts: qcom: x1e80100: add ADSP GPR
a24c8ba00dac dt-bindings: remoteproc: qcom,sm8550-pas: document the SM8650 PAS
552c8b9c51bd riscv: dts: microchip: add specific compatible for mpfs pdma
0359a2873d27 arm64: dts: qcom: ipq6018: add QUP5 I2C node
2109082a047e arm64: dts: qcom: x1e80100-qcp: Fix supplies for LDOs 3E and 2J
ad5e70a893a6 arm64: dts: qcom: x1e80100-qcp: Enable more support
70e1e5caf55a arm64: dts: qcom: x1e80100-crd: Enable more support
e7f823deb502 arm64: dts: qcom: x1e80100: Add display nodes
09888df4cabf arm64: dts: qcom: x1e80100: Add PCIe nodes
113e1447c4b7 arm64: dts: qcom: x1e80100: Add USB nodes
d042016c875e arm64: dts: qcom: x1e80100: Add TCSR node
1e12a915f76a arm64: dts: qcom: x1e80100: Add ADSP/CDSP remoteproc nodes
21784a99d799 arm64: dts: qcom: x1e80100: Add QMP AOSS node
adac34e54b92 arm64: dts: qcom: x1e80100: Add SMP2P nodes
f6ae972c7d7a arm64: dts: qcom: x1e80100: Add IPCC node
f858f5571e59 Merge branch '20240202-x1e80100-clock-controllers-v4-5-7fb08c861c7c@linaro.org' into arm64-for-6.9
16f9c84b0c9a Merge branch '20240202-x1e80100-clock-controllers-v4-5-7fb08c861c7c@linaro.org' into clk-for-6.9
77ff05b89311 dt-bindings: clock: qcom: Document the X1E80100 Camera Clock Controller
9b09558a4d02 dt-bindings: clock: qcom: Document the X1E80100 TCSR Clock Controller
009188ad89c1 dt-bindings: clock: qcom: Document the X1E80100 GPU Clock Controller
619f14d3ee00 dt-bindings: clock: qcom: Document the X1E80100 Display Clock Controller
5c691ea9dfde dt-bindings: clock: Drop the SM8650 DISPCC dedicated schema
fd99a9349fc8 dt-bindings: soc: qcom: qcom,pmic-glink: document X1E80100 compatible
3de725e88fb0 arm64: dts: qcom: sa8775p: Add new memory map updates to SA8775P
62872aebbbd8 dt-bindings: soc: imx: add missing clock and power-domains to imx8mp-hdmi-blk-ctrl
4ff28e3e2d94 ASoC: dt-bindings: atmel,sam9x5-wm8731: Convert to json-schema
906cab843596 riscv: dts: microchip: add missing CAN bus clocks
70bee5f22413 dt-bindings: can: mpfs: add missing required clock
91d53111ca13 dt-bindings: clock: mpfs: add more MSSPLL output definitions
7564dfecdf9e Revert "media: ov08x40: Reduce start streaming time"
230eabe62cac arm64: dts: ti: iot2050*: Clarify GPL-2.0 as GPL-2.0-only
81c25598663e arm64: dts: ti: phycore*: Add MIT license along with GPL-2.0
49ad241d7ba0 arm64: dts: ti: beagle*: Add MIT license along with GPL-2.0
af13011bc32a arm64: dts: ti: k3-serdes: Add MIT license along with GPL-2.0
97f615d94c52 arm64: dts: ti: k3-pinctrl: Add MIT license along with GPL-2.0
fb7c92cfa0d7 arm64: dts: ti: k3-j784s4: Add MIT license along with GPL-2.0
ef720a09d820 arm64: dts: ti: k3-j721s2: Add MIT license along with GPL-2.0
b5d3132ac896 arm64: dts: ti: k3-j721e: Add MIT license along with GPL-2.0
a08b6e3c500d arm64: dts: ti: k3-j7200: Add MIT license along with GPL-2.0
67b92cb4a9b8 arm64: dts: ti: k3-am65: Add MIT license along with GPL-2.0
4270ef124316 arm64: dts: ti: k3-am64: Add MIT license along with GPL-2.0
6bbb88ff7998 arm64: dts: ti: k3-am62p: Add MIT license along with GPL-2.0
0ffeaa9662f1 arm64: dts: ti: k3-am625: Add MIT license along with GPL-2.0
5db4fd731c54 arm64: dts: ti: k3-am62a7: Add MIT license along with GPL-2.0
99e9047746eb arm64: dts: ti: Use https for urls
3fa55a728a3d arm64: dts: imx8mn-evk: Add PDM micphone sound card support
8d8a62fd968d arm64: dts: imx8mm-evk: Add PDM micphone sound card support
151935e24c16 arm64: dts: imx8qm: add smmu stream id information
7ca27214673d arm64: dts: imx8qm: add smmu node
b9f9b709c278 arm64: dts: imx8dxl-evk: add flexcan2 and flecan3
f42aa20f9119 arm64: dts: imx8dxl-evk: add i2c3 and its children nodes
93d6366b8356 arm64: dts: imx8dxl: update flexcan[1-3] interrupt number
c5d90c61def2 arm64: dts: imx8mp-phyboard-pollux-rdk: add etml panel support
16c8d47dc262 arm64: dts: imx8mn-rve-gateway: remove redundant company name
b08765c243bb dt-bindings: arm: fsl: remove redundant company name
65cffffa0551 ARM: dts: samsung: exynos5420-galaxy-tab: decrease available memory
d01b22a61768 dt-bindings: ata: atmel: remove at91 compact flash documentation
d242043d9d60 arm64: dts: renesas: gray-hawk-single: Enable watchdog timer
2e8d8e405f93 arm64: dts: renesas: r8a779h0: Add RWDT node
35665cd38eb8 arm64: dts: renesas: Improve TMU interrupt descriptions
6c5ee3279bcd ARM: dts: renesas: Improve TMU interrupt descriptions
78e358d25cba ARM: dts: imx6ull-dhcom: Remove /omit-if-no-ref/ from node usdhc1-pwrseq
f53c235dce4f arm64: dts: freescale: imx8qm: add apalis eval v1.2 carrier board
c6a20bf4953d dt-bindings: arm: fsl: add imx8qm apalis eval v1.2 carrier board
4a2797e6299b dt-bindings: display: imx: add binding for i.MX8MP HDMI TX
46daefc82714 arm64: dts: exynos: Add SPI nodes for Exynos850
864d0966e626 ARM: dts: imx: Add support for Apalis Evaluation Board v1.2
ab38fa94e38c dt-bindings: arm: fsl: Add toradex,apalis_imx6q-eval-v1.2 board
79c6446e27a7 ARM: dts: imx6: skov: add aliases for all ethernet nodes
00cba1b18156 arm64: dts: imx93: Add phyBOARD-Segin-i.MX93 support
ee42eae10f7a dt-bindings: arm: fsl: Add phyBOARD-Segin-i.MX93
1dcb02c43ac3 arm64: dts: imx8mp: Enable PCIe to Data Modul i.MX8M Plus eDM SBC
c35148dd66cc dt-bindings: firmware: xilinx: Describe soc-nvmem subnode
e4d158a009f2 arm64: dts: ls1012a: fix DWC3 USB VBUS glitch issue
2cc69dbdcc3b arm64: dts: ls1012a: add gpio for i2c bus recovery
86f029cb9916 arm64: dts: ls1012a: add big-endian property for PCIe nodes
1344dd97c94d arm64: dts: ls1012a: correct the size of dcfg block
eebf4e8a4de5 arm64: dts: ti: k3-j7200: use ti,j7200-padconf compatible
b2c927e92eb5 arm64: dts: ti: k3-am62p-mcu/wakeup: Disable MCU and wakeup R5FSS nodes
1ed877819eca arm64: dts: ti: k3-am69-sk: remove assigned-clock-parents for unused VP
b2e13a92bcd3 dt-bindings: drm/bridge: ti-sn65dsi86: Fix bouncing @codeaurora address
5aafe0eb29a5 dt-bindings: mux: restrict node name suffixes
959645b1cb6f ARM: dts: keystone: Replace http urls with https
9c307f485cc5 arm64: dts: ti: k3-am62a7-sk: Add HDMI support
33aa21cb5f84 arm64: dts: ti: k3-am62a-main: Add node for Display SubSystem (DSS)
e197413922a3 arm64: dts: ti: phycore-am64: Add ADC
cbb614f03fe0 arm64: dts: ti: k3-j784s4: Fix power domain for VTM node
4979495296af arm64: dts: ti: k3-j721s2: Fix power domain for VTM node
66f98925474a arm64: dts: ti: k3-am62p5-sk: Enable CPSW MDIO node
8af95677c0a4 arm64: dts: ti: k3-j7200: Add support for multiple CAN instances
3416ecb8c84b arm64: dts: ti: k3-j7200-som-p0: Add support for CAN instance 0 in main domain
b190cdb39a78 arm64: dts: ti: k3-j7200: Add support for CAN nodes
049925dbe4ef arm64: dts: ti: verdin-am62: mallow: add TPM device
d18d4a279eac arm64: dts: ti: k3-am64: Remove PCIe endpoint node
45e8e613d391 arm64: dts: ti: k3-am65: Remove PCIe endpoint nodes
9482566d8484 arm64: dts: ti: k3-j7200: Remove PCIe endpoint node
f2db5b44a21b arm64: dts: ti: k3-j7200: Enable PCIe nodes at the board level
1b1b2953ae47 arm64: dts: ti: k3-j721s2-som-p0: Do not split single items
1ab381b19847 arm64: dts: ti: k3-j721e-som-p0: Do not split single items
3bbf314c8e51 arm64: dts: ti: k3-j721e-sk: Do not split single items
9982ca1fa62d arm64: dts: ti: k3-j721e-beagleboneai64: Do not split single items
685e4624960e arm64: dts: ti: k3-j7200-som-p0: Do not split single items
bb743de0d3fe arm64: dts: ti: k3-am69-sk: Do not split single items
6081c21a3e9b arm64: dts: ti: k3-am68-sk-som: Do not split single items
7aebe586ccdc arm64: dts: ti: k3-am654-base-board: Do not split single items
756750059f96 arm64: dts: ti: iot2050: Do not split single items
83cac2593e26 arm64: dts: ti: k3-am642-sk: Do not split single items
c266381d0608 arm64: dts: ti: k3-am642-evm: Do not split single items
ff6e034104fc arm64: dts: ti: k3-am642-phyboard-electra: Add TPM support
986edbf094b5 arm64: dts: ti: Disable clock output of the ethernet PHY
140c5468b668 arm64: dts: ti: Add phase tags for memory node on J784S4 EVM and AM69 SK
fb6ffd10b764 arm64: dts: ti: k3-am625-beagleplay: Use the builtin mdio bus
abed090f1e99 arm64: dts: ti: k3-am625-beagleplay: Add boot phase tags for USB0
0424a17ecb7a arm64: dts: ti: k3-am625-sk: Add boot phase tags for USB0
ac8143f3b013 dt-bindings: mtd: avoid automatically select from mtd.yaml
828b9467f60f media: dt-bindings: techwell,tw9900: Fix port schema ref
2b2619e4c6c5 dt-bindings: display: imx: add binding for i.MX8MP HDMI PVI
141f2102cc12 ARM: dts: imx6qdl-hummingboard: Add rtc0 and rtc1 aliases to fix hctosys
ffe7dc298435 arm64: dts: imx93: drop "master" I3C node name suffix
99af7a0dae65 ARM: dts: imx6dl: Add support for Sielaff i.MX6 Solo board
ff6929d462c4 dt-bindings: arm: fsl: Add Sielaff i.MX6 Solo board
d3413ad34a12 arm64: dts: freescale: tqma9352: Update I2C eeprom compatible
ad2d1ba26a13 arm64: dts: imx8mp: reparent MEDIA_MIPI_PHY1_REF to CLK_24M
3b589ade448f dt-bindings: gpio: pca9570: Add label property
11eb3d98d38b dt-bindings: gpio: mvebu: Fix "unevaluatedProperties" to be false
9c0a4b40a3ac ARM: dts: imx6ul: Add missing #thermal-sensor-cells to tempmon
fee43501308a arm64: dts: imx8mp-verdin: Label ldo5 and link to usdhc2
b8d7d5f3690b arm64: dts: imx93-var-som: Add Variscite VAR-SOM-MX93
188a8bb94d35 dt-bindings: arm: fsl: Add VAR-SOM-MX93 with Symphony
fecb422bac6a arm64: dts: ls1046a: Remove big-endian from thermal
78343d7acd50 ARM: dts: imx6sl-tolino-shine2hd: fix touchscreen rotation
e57037e98946 ARM: dts: imx6ull-dhcor: Remove 900MHz operating point
31d9e29f0d8e Merge tag 'drm-misc-next-2024-01-11' of git://anongit.freedesktop.org/drm/drm-misc into drm-next
e6d71526460e dt-bindings: misc: xlnx,sd-fec: convert bindings to yaml
01b5de94aa82 Merge 6.8-rc3 into tty-next
7030aa5067b6 Merge 6.8-rc3 into usb-next
5f856030cc8b arm64: dts: rockchip: Add devicetree for Pine64 PineTab2
c87344c32c61 dt-bindings: arm64: rockchip: Add Pine64 PineTab2
6944e5df2f35 arm64: dts: rockchip: Add Touch to Anbernic RG-ARC D
9a90efccd7ee ARM: dts: microchip: gardena-smart-gateway: Use DMA for USART3
9a2b5d99e0ff ARM: dts: microchip: at91sam9x5ek: Use DMA for DBGU serial port
7051d52cf5b9 arm64: dts: imx8mp-venice-gw71xx: add TPM device
4ecbc5946cc5 arm64: dts: imx8mm-venice-gw71xx: add TPM device
3c805459dfd7 arm64: dts: imx8mm-venice-gw71xx: fix USB OTG VBUS
af9118771e3c arm64: dts: imx8mm-venice-gw7901: add TPM device
bcc4aff9ee00 arm64: dts: imx8mm-venice-gw7901: add digital I/O direction control GPIO's
6ea0c6a49b64 ARM: dts: imx7-tqma7: Fix PMIC v33 rail voltage range
2482c75bff8e ARM: dts: imx7-mba7: Add missing vcc supply to i2c devices
4d19ec066c6b ARM: dts: imx7-tqma7: Add missing vcc supply to i2c eeproms
fda2672c8e68 ARM: dts: imx7d-mba7: Remove USB OTG related properties on USB node
f71b70123d20 ARM: dts: imx7-tqma7: rename node for SE97BTP
56382af8168e ARM: dts: imx7-tqma7: mark system data eeprom as read-only
59c9c040a0db ARM: dts: imx7-tqma7: remove superfluous status property
ac9f05a3b8ee ARM: dts: imx7-tqma7: restrict usdhc interface modes
54b93adb1393 ARM: dts: imx7-mba7: restrict usdhc interface modes
6980af2d9f17 ARM: dts: imx7-tqma7: Fix iomuxc node names
efad19cdde77 ARM: dts: imx7-mba7: Fix iomuxc node names
fe330835b74e ARM: dts: imx7-tqma7: fix EEPROM compatible for SE97BTP
77f6e05fdfa1 ARM: dts: imx7-mba7: Add i2c bus recovery
8f9993282d52 ARM: dts: imx7-tqma7: Add i2c bus recovery
4065cdaa82bd ARM: dts: imx7-mba7: Add SPI1_SS0 as chip select 3
10cde7452d93 ARM: dts: imx7-mba7: Add RTC aliases
67c6d0e81520 ARM: dts: imx7-mba7: Enable SNVS power key
2ccae767cb74 ARM: dts: imx7-mba7: Mark gpio-buttons as wakeup-source
235e861d016e ARM: dts: imx7[d]-mba7: hog Mini PCIe signals
cd553893ac90 ARM: dts: imx7[d]-mba7: disable PCIe interface
2faa76d25aef ARM: dts: imx7[d]-mba7: disable USB OC on USB host and USB OTG2
f9152233518d ARM: dts: imx7[d]-mba7: Move ethernet PHY reset into PHY node
0d8f0cba144c ARM: dts: imx7-tqma7/mba7: convert fsl,pins to uint32-matrix
c09e630c5912 arm64: dts: qcom: qcm6490-idp: Include PM7250B
edd0bc8b8d0b arm64: dts: qcom: sm8650: Use GIC-ITS for PCIe0 and PCIe1
4fe52e68f13c arm64: dts: qcom: qcm6490-idp: Add definition for three LEDs
cc592e051541 arm64: dts: qcom: sm8650-qrd: add USB-C Altmode Support
b789944a89fc arm64: dts: qcom: sm8550-qrd: enable Touchscreen
200b0b3875ef dt-bindings: clock: qcom: Fix @codeaurora email in Q6SSTOP
5eaa8712fb96 dt-bindings: visionox-rm69299: Update maintainers
ae0b823f0536 dt-bindings: gpio: renesas,rcar-gpio: Add r8a779h0 support
d4458c6492e6 dt-bindings: net: ti: Update maintainers list
a3fa7f3f82f7 dt-bindings: net: ipq4019-mdio: document now supported clock-frequency
9c3280cd3020 Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
19adc3b90590 Merge branch '20240201204421.16992-2-quic_amelende@quicinc.com' into drivers-for-6.9
b5c560279d08 dt-bindings: soc: qcom: Add qcom,pbs bindings
08d014730db7 regulator: dt-bindings: microchip,mcp16502: convert to YAML
bdef327947f5 arm64: dts: intel: agilex5: drop "master" I3C node name suffix
1c0d4ea255ee media: ov08x40: Reduce start streaming time
7d92af412d2e arm64: dts: exynos: Add PDMA node for Exynos850
1868ee800d4c arm64: dts: exynos: gs101: use correct clocks for usi_uart
5d5769f28954 arm64: dts: exynos: gs101: use correct clocks for usi8
dc00c7274ea6 dt-bindings: net: dsa: Add KSZ8567 switch support
58475bd50ec5 media: arm64: dts: st: add video encoder support to stm32mp255
380408454fb2 media: arm64: dts: st: add video decoder support to stm32mp255
4eea1b53e82e media: dt-bindings: media: Document STM32MP25 VDEC & VENC video codecs
39ecce7ee54a arm64: dts: imx8qxp: add GPU nodes
b206b48e8a91 arm64: dts: imx8qm: Correct edma3 power-domains and interrupt numbers
7a74326b4893 arm64: dts: imx8qm: Align edma3 power-domains resources indentation
0be926d25dbc arm64: dts: imx8qxp: mba8xx: Add analog audio output on MBa8Xx
43aab34e5e0c arm64: dts: imx8qxp: Add mclkout clock gates
8c7666d283be arm64: dts: imx8qxp: Add audio SAI nodes
a12fa3d0c150 arm64: dts: imx8qxp: Add audio clock mux node
6c44f7583fd5 arm64: dts: imx8qxp: Add ACM input clock gates
cf7ea553fe5a arm64: dts: freescale: add initial device tree for TQMa8Xx
98de130e34e4 dt-bindings: arm: add TQMa8Xx boards
dc089f5f4bb0 arm64: dts: imx: add imx8dxp support
a5a40554f207 dt-bindings: net: qcom,ipa: do not override firmware-name $ref
927f00767ef5 arm64: dts: imx8mm-kontron: Refactor devicetree for OSM-S module and board
dc0c1bca1831 arm64: dts: imx8mm-kontron: Add I2C EEPROM on OSM-S Kontron i.MX8MM
071edd561a01 arm64: dts: imx8mm-kontron: Remove useless trickle-diode-disable from RTC node
bc9a25d78a35 arm64: dts: imx8mm-kontron: Disable uneffective PUE bit in SDIO IOMUX
48e6dc42724c arm64: dts: imx8mm-kontron: Fix OSM-S devicetrees to match latest hardware
1749a50ca797 arm64: dts: imx8mm-kontron: Fix interrupt for RTC on OSM-S i.MX8MM module
6985d8cd5c40 arm64: dts: imx8mm-kontron: Disable pull resistors for SD card signals on BL board
688fff06ac4e arm64: dts: imx8mm-kontron: Disable pull resistors for SD card signals on BL OSM-S board
4b8efdb73a46 arm64: dts: imx8mm-kontron: Disable pullups for onboard UART signals on BL board
123efe05e212 arm64: dts: imx8mm-kontron: Disable pullups for onboard UART signals on BL OSM-S board
9f02292756b9 arm64: dts: imx8mm-kontron: Disable pullups for I2C signals on SL/BL i.MX8MM
928dc77f0003 arm64: dts: imx8mm-kontron: Disable pullups for I2C signals on OSM-S i.MX8MM
c2b4ecb58452 dt-bindings: fpga: Convert fpga-region binding to yaml
85d6c583d5f5 MAINTAINERS: Drop my "+dt" sub-address
0f6ed4032e99 dt-bindings: timer: renesas,tmu: Document input capture interrupt
05c9f46083ba arm64: dts: renesas: r9a07g043u: Add CSI and CRU nodes
aa403cfc2a6c arm64: dts: renesas: Add Gray Hawk Single board support
82a8a0a3e608 arm64: dts: renesas: Add Renesas R8A779H0 SoC support
356004f72bd0 Merge tag 'renesas-r8a779h0-dt-binding-defs-tag' into renesas-dts-for-v6.9
1200029387ce arm64: dts: renesas: rzg3s-smarc-som: Enable the watchdog interface
d58eb8846937 arm64: dts: renesas: r9a08g045: Add watchdog node
b1de14ce277c arm64: dts: renesas: r8a779g0: Add missing SCIF_CLK2
fe98cda6e099 dt-bindings: soc: renesas: Document R-Car V4M Gray Hawk Single
bcdc951ea508 dt-bindings: reset: renesas,rst: Document R-Car V4M support
55647b66aba2 pinctrl: renesas: pinctrl-rzg2l: Add the missing port pins P19 to P28
fc9d9f1cfef8 dt-bindings: interconnect: Remove bogus interconnect nodes
47509af4504a soundwire/SOF: add SoundWire Interface support for
f521b204bcd2 dt-bindings: interconnect: Add Qualcomm MSM8909 DT bindings
72ececa06e31 riscv: dts: starfive: beaglev-starlight: Setup phy reset gpio
0279da4a6715 riscv: dts: starfive: visionfive-v1: Setup ethernet phy
19f7725fe372 riscv: dts: starfive: jh7100-common: Setup pinmux and enable gmac
d05053a8b239 riscv: dts: starfive: jh7100: Add sysmain and gmac DT nodes
921e5e1327ef dt-bindings: net: starfive,jh7110-dwmac: Add JH7100 SoC compatible
7020ebc26757 dt-bindings: clock: Add R8A779H0 V4M CPG Core Clock Definitions
35d633af4efc dt-bindings: clock: renesas,cpg-mssr: Document R-Car V4M support
1de76ced2497 dt-bindings: soc: xilinx: Add support for KV260 CC
c9aeb5c33863 dt-bindings: soc: xilinx: Add support for K26 rev2 SOMs
e36f379d8c82 dt-bindings: pinctr: pinctrl-zynq: Fix compatible string
c7a574ba2a6c dt-bindings: pinctrl: nuvoton,npcm845: Drop redundant type for "slew-rate"
da1b37add707 dt-bindings: pinctrl: Unify "input-debounce" schema
234d836b6a1a dt-bindings: input: document Goodix Berlin Touchscreen IC
8df2aa5a1297 arm64: dts: qcom: Add support for Xiaomi Redmi Note 9S
5c09bd2b6ce1 arm64: dts: qcom: sm7125-xiaomi-common: Add UFS nodes
5c38e796a3a1 arm64: dts: qcom: sc7180: Add UFS nodes
307cdcc3f9c2 dt-bindings: arm: qcom: Add Xiaomi Redmi Note 9S
d9eda103eb64 ARM: dts: qcom: apq8026-lg-lenok: Add vibrator support
2590e420cf2c ARM: dts: qcom: msm8960: expressatt: Add gpio-keys
9d906fe262e0 arm64: dts: qcom: sda660-ifc6560: enable USB 3.0 PHY
6b10b59bd1db arm64: dts: qcom: sdm630: add USB QMP PHY support
329fb714e840 arm64: dts: qcom: sc8280xp: camss: Add CAMSS block definition
ca14c11bb9a4 arm64: dts: qcom: sc8280xp: camss: Add CCI definitions
5ce7895c7b2b dt-bindings: clock: qcom: Allow VDD_GFX supply to GX
3a9a9247f661 arm64: dts: qcom: sa8295p-adp: Enable GPU
08f93d65d530 arm64: dts: qcom: sa8295p-adp: add max20411
1129eea99cc1 arm64: dts: qcom: sa8540p: Drop gfx.lvl as power-domain for gpucc
14bc12ecdfe3 dt-bindings: interrupt-controller: convert MediaTek sysirq to the json-schema
77a4323bd64f dt-bindings: dma: allwinner,sun50i-a64-dma: Add compatible for H616
82bf0037e8d8 dt-bindings: power: Add r8a779h0 SYSC power domain definitions
d98d5e6ce56e dt-bindings: power: renesas,rcar-sysc: Document R-Car V4M support
5ee26dab625b dt-bindings: bus: Document Broadcom GISB arbiter 74165 compatible
c6234d82a072 arm64: dts: broadcom: bcmbca: bcm4908: drop invalid switch cells
bc4ef25abdc1 arm64: dts: broadcom: bcmbca: bcm4908: use NVMEM layout for Asus GT-AC5300
b6e08822ed8c arm64: dts: renesas: r8a779g2: Add White Hawk Single support
7e3862db4c62 arm64: dts: renesas: Add Renesas R8A779G2 SoC support
51fc2376ba1d arm64: dts: renesas: white-hawk: Factor out common parts
a248c1746935 arm64: dts: renesas: white-hawk-cpu: Factor out common parts
fdea5d785497 arm64: dts: renesas: white-hawk: Add SoC name to top-level comment
a77e323e0dc2 arm64: dts: renesas: white-hawk: Drop SoC parts from sub boards
3e8f05b2b81d arm64: dts: renesas: white-hawk-cpu: Restore sort order
e90ffb9d53b7 arm64: dts: renesas: r8a779g0: Add standalone White Hawk CPU support
eccddc31dfa9 arm64: dts: renesas: ulcb-kf: Add node for GNSS
3d3e628e12d6 arm64: dts: renesas: ulcb-kf: Drop duplicate 3.3v regulators
bf721e67a7fb Merge drm/drm-next into drm-misc-next
351548ba8841 dt-bindings: soc: renesas: Document R-Car V4H White Hawk Single
ad352af0d46f dt-bindings: nfc: ti,trf7970a: fix usage example
d4d212c5cf34 dt-bindings: display: panel-simple: add ETML1010G3DRA
6aee668021fc arm64: dts: qcom: sm7225-fairphone-fp4: Switch firmware ext to .mbn
aa54779772ae arm64: dts: qcom: rename PM2250 to PM4125
dbcb19ed3275 arm64: dts: qcom: qcm6490-fairphone-fp5: Add PMIC GLINK
dc376fa4a27c arm64: dts: qcom: sdm845-oneplus-common: improve DAI node naming
048423deb9a5 arm64: dts: qcom: qcm6490-fairphone-fp5: Add missing reserved-memory
b4d0c1c61afa arm64: dts: qcom: sc7280: Add static properties to cryptobam
f3f780c01899 arm64: dts: qcom: sa8775p: enable safety IRQ
fd61cbbd53a9 dt-bindings: clock: qcom,gcc-sm8150: Add gcc video resets for sm8150
30e2fa95b585 dt-bindings: arm: qcom,ids: add SoC ID for QCM8550 and QCS8550
27f4e6aa609c dt-bindings: Add reference to rs485.yaml
5e11848e4c98 dt-bindings: serial: renesas,hscif: Document r8a779h0 bindings
c7aaa6160c61 dt-bindings: serial: fsl-lpuart: support i.MX95
3ee8c19304d9 dt-bindings: serial: samsung: do not allow reg-io-width for gs101
d70fdb79f945 arm64: dts: qcom: apq8016-sbc-d3-camera: Use more generic node names
95830229bcb5 ARM: dts: qcom: msm8960: drop 2nd clock frequency from timer
4f433e3e9a04 ARM: dts: qcom: ipq4019-ap.dk01.1: align flash node with bindings
39065990752b ARM: dts: qcom: ipq4019-ap.dk01.1: use existing labels for nodes
a6106c8748a7 arm64: dts: qcom: split PCIe interrupt-names entries per lines
f1ac2340280d arm64: dts: qcom: sm8650: describe all PCI MSI interrupts
653638c9dceb arm64: dts: qcom: sm8550: describe all PCI MSI interrupts
90840a974369 arm64: dts: qcom: sm8450: describe all PCI MSI interrupts
c681c8ad796c arm64: dts: qcom: sm8350: describe all PCI MSI interrupts
9186fa649278 arm64: dts: qcom: sm8250: describe all PCI MSI interrupts
a2e5b5e27b91 arm64: dts: qcom: sm8150: describe all PCI MSI interrupts
ed0b4f3e69ba ARM: dts: qcom: msm8926-htc-memul: Add rmtfs memory node
3556e0895e7a dt-bindings: usb: dwc3: Add snps,host-vbus-glitches-quirk avoid vbus glitch
75bae0c78ef3 dt-bindings: usb: usb-nop-xceiv: Repurpose vbus-regulator
20e5fb946959 dt-bindings: usb: mtu3: Add MT8195 MTU3 ip-sleep support
0145e6824861 dt-bindings: usb: Clean-up "usb-phy" constraints
eb9bdcaff280 dt-bindings: usb: add common Type-C USB Switch schema
a67690a90fb9 dt-bindings: usb: Add Marvell ac5
59434babb8e4 arm64: dts: qcom: sm8450: Add missing interconnects to serial
6b60607aa5cc dt-bindings: usb: Introduce ITE IT5205 Alt. Mode Passive MUX
fe0ce9c54778 dt-bindings: pinctrl: amlogic: narrow regex for unit address to hex numbers
8c58779baca1 dt-bindings: qcom: Document new msm8916-samsung devices
1438aadecf94 arm64: dts: qcom: sm8450-hdk: correct AMIC4 and AMIC5 microphones
b4d502118ad4 arm64: dts: qcom: sm8150: add necessary ref clock to PCIe
018a13d36a57 arm64: dts: qcom: sdm630: Hook up GPU cooling device
2b51fa0934c8 arm64: dts: qcom: sm8550: Hook up GPU cooling device
15018cdc0470 arm64: dts: qcom: sm8450: Hook up GPU cooling device
f5906fc26422 arm64: dts: qcom: sm8350: Hook up GPU cooling device
9df3c73a8511 arm64: dts: qcom: sm8250: Hook up GPU cooling device
257e0300ca3a arm64: dts: qcom: sm8150: Hook up GPU cooling device
b16301e27866 arm64: dts: qcom: sm6115: Mark GPU @ 125C critical
ccc769ffd9fa arm64: dts: qcom: sm6115: Hook up GPU cooling device
cf4e80b514f2 arm64: dts: qcom: sdm845: Hook up GPU cooling device
6ddaa894ac00 arm64: dts: qcom: sc8180x: Hook up GPU cooling device
1a13cc6e08c9 arm64: dts: qcom: msm8939: Hook up GPU cooling device
04962e8ee80d arm64: dts: qcom: msm8916: Hook up GPU cooling device
de58665d5a86 arm64: dts: qcom: x1e80100: Flush RSC sleep & wake votes
5792135ff692 arm64: dts: qcom: x1e80100: Add missing system-wide PSCI power domain
7dddf3cf2c2d dt-bindings: soc/qcom: Add size constraints on "qcom,rpm-msg-ram"
f3e26b603762 arm64: dts: qcom: Add missing interrupts for qcs404/ipq5332
d2eb087d6a3f arm64: dts: qcom: Fix hs_phy_irq for SDM670/SDM845/SM6350
e912f5a885bc arm64: dts: qcom: Fix hs_phy_irq for non-QUSB2 targets
cc58f6b02229 arm64: dts: qcom: Fix hs_phy_irq for QUSB2 targets
ed2747597b2e arm64: dts: qcom: sm8550: add support for the SM8550-HDK board
0beb12a79761 dt-bindings: arm: qcom: Document the HDK8550 board
1182dc50de01 dt-bindings: net: Document QCA808x PHYs
8869fe2b8c59 dt-bindings: net: phy: Document LED inactive high impedance mode
8a5d470f446f dt-bindings: net: phy: Make LED active-low property common
ee170c770dce ASoC: dt-bindings: audio-graph-port: Drop type from "clocks"
52dc7498eed1 ASoC: dt-bindings: samsung,tm2: Correct "audio-codec" constraints
2294f77ec0a5 ARM: dts: sti: minor whitespace cleanup around '='
e8f034522bd8 arm64: dts: exynos: gs101: sysreg_peric0 needs a clock
d7849025c947 ARM: dts: da850: add MMD SDIO interrupts
f831c925b07a ARM: dts: marvell: dove-cubox: fix si5351 node names
70e16db126d5 arm: dts: marvell: Fix maxium->maxim typo in brownstone dts
29fba2976ec3 dt-bindings: crypto: ice: Document SC7180 inline crypto engine
3d331a17e8c9 dt-bindings: qcom-qce: Add compatible for SM6350
4fd1499f0d02 arm64: dts: ti: k3-am654-main: Add device tree entry for SGX GPU
459e64009a83 ARM: dts: DRA7xx: Add device tree entry for SGX GPU
33828a263695 ARM: dts: AM437x: Add device tree entry for SGX GPU
b812a94b3a14 ARM: dts: AM33xx: Add device tree entry for SGX GPU
a43b7f4412c3 ARM: dts: omap5: Add device tree entry for SGX GPU
26a571cb3312 ARM: dts: omap4: Add device tree entry for SGX GPU
0590991057c3 ARM: dts: omap3: Add device tree entry for SGX GPU
6cfc912186fd dt-bindings: gpu: Add PowerVR Series5 SGX GPUs
ecd5e84cb911 dt-bindings: gpu: Rename img,powervr to img,powervr-rogue
674fba836cdb arm64: dts: rockchip: fix nanopc-t6 sdmmc regulator
33b030710624 arm64: dts: rockchip: remove duplicate SPI aliases for helios64
7c0fd87b35a8 arm64: dts: rockchip: add spi controller aliases on rk3399
774db835de8a arm64: dts: rockchip: Add support for NanoPi R6C
245ed9f66edb arm64: dts: rockchip: Add support for NanoPi R6S
7ed25d8d0d24 dt-bindings: arm: rockchip: Add NanoPi R6 series boards
4fc6e0686faf arm64: dts: rockchip: Increase maximum frequency of SPI flash for ROCK Pi 4A/B/C
47aafd8512e1 arm64: dts: rockchip: add sdmmc card detect to the nanopc-t6
5bdf0ecf003d arm64: dts: rockchip: Add cache information to the SoC dtsi for RK3399
3d67b6c2a2af ARM: dts: rockchip: Enable HDMI output for XPI-3128
8ac6f9cf696a ARM: dts: rockchip: Add HDMI node for RK3128
06cbcacf56ad ARM: dts: rockchip: Add display subsystem for RK3128
9a9dc5b9e06a arm64: dts: rockchip: add rfkill node for M.2 Key E WiFi on rock-5b
c7f1c6bb420a arm64: dts: rockchip: enable NanoPC-T6 MiniPCIe power
9604142e6a0d arm64: dts: rockchip: Add LED_GREEN for edgeble-neu6a
cbd461ded362 arm64: dts: rockchip: Add Edgeble NCM6A-IO USB2
051aa218e679 arm64: dts: rockchip: Add Edgeble NCM6A-IO M.2 B-Key, E-Key
e24b6c90f78b arm64: dts: rockchip: Add Edgeble NCM6A-IO M.2 M-Key
c04566174738 arm64: dts: rockchip: Add Edgeble NCM6A-IO 2.5G ETH
1696541973b9 arm64: dts: rockchip: Add vdd_cpu_big reg to rk3588-edgeble-ncm6
fed4b47f48ac arm64: dts: rockchip: Add Edgeble NCM6A WiFi6 Overlay
648060033a16 arm64: dts: rockchip: Add common DT for edgeble-neu6b-io
14b26b2835cb arm64: dts: rockchip: Add edgeble-neu6a-common DT
8360c7a53f95 arm64: dts: rockchip: Drop edgeble-neu6b dcdc-reg4 regulator-init-microvolt
e497dc0158dd arm64: dts: rockchip: add missing definition of pmu io domains 1 and 2 on ringneck
f1cb710d9302 arm64: dts: rockchip: add Anbernic RG-ARC S and RG-ARC D
351c26e7934f dt-bindings: arm: rockchip: Add Anbernic RG-Arc
294dd835c5d0 arm64: dts: rockchip: Move device specific properties
e8f6b6072ce6 dt-bindings: soc: rockchip: Add rk3588 hdptxphy syscon
663d347eb7a7 ARM: dts: stm32: fix DSI peripheral clock on stm32mp15 boards
6e307e6bd72d dt-bindings: memory-controllers: narrow regex for unit address to hex numbers
ef93727c9def spi: dt-bindings: samsung: Add Exynos850 SPI
c714a4c1273b ARM: dts: qcom: use defines for interrupts
7f37d45ff70d ARM: dts: qcom: apq8026-samsung-matissewifi: Configure touch keys
cf76727f86a3 ARM: dts: stm32: lxa-tac: drive powerboard lines as open-drain
19fee3189355 dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Document the X1E80100 QMP PCIe PHYs
899bb26cef2c dt-bindings: iio: adc: rtq6056: add support for the whole RTQ6056 family
09065a127e3c dt-bindings: input: melfas,mms114: add MMS252 compatible
ef76ae751c3c dt-bindings: phy: qcom,msm8998-qmp-usb3-phy: support SDM660
97fd9e67ede2 dt-bindings: phy: qcom,msm8998-qmp-usb3-phy: add TCSR registers
25bfbe442a13 dt-bindings: phy: qcom,msm8998-qmp-usb3-phy: support USB-C data
6ec985dff442 dt-bindings: phy: qcom,msm8998-qmp-usb3-phy: split from sc8280xp PHY schema
8b41b5f06d8a arm64: dts: exynos: gs101: enable eeprom on gs101-oriole
eb43c96a2716 arm64: dts: exynos: gs101: define USI8 with I2C configuration
688d19a4c1d5 arm64: dts: exynos: gs101: update USI UART to use peric0 clocks
c8631c01c9d5 arm64: dts: exynos: gs101: enable cmu-peric0 clock controller
7f078f4efe48 arm64: dts: exynos: gs101: remove reg-io-width from serial
dfa299ac5670 arm64: dts: exynos: gs101: define Multi Core Timer (MCT) node
dd8d6cdb498f dt-bindings: clock: tesla,fsd: Fix spelling mistake
2a50cd8b4cad Merge tag 'samsung-dt-bindings-clk-6.9-2' into next/clk
1308a1709db2 dt-bindings: clock: exynos850: Add PDMA clocks
5f252cf1954d dt-bindings: clock: google,gs101-clock: add PERIC0 clock management unit
b7045107b13d dt-bindings: phy: Add QMP UFS PHY compatible for SC7180
806828c18886 arm64: dts: qcom: sc8180x: Add RPMh sleep stats
8bfa57f18d67 arm64: dts: qcom: sc8180x: Shrink aoss_qmp register space size
39124f597a6a arm64: dts: qcom: sc8180x: Add missing CPU<->MDP_CFG path
076044c5542f arm64: dts: qcom: sc8180x: Require LOW_SVS vote for MMCX if DISPCC is on
76f855a9dca6 arm64: dts: qcom: sc8180x: Don't hold MDP core clock at FMAX
37f3285d146b arm64: dts: qcom: sc8180x: Fix eDP PHY power-domains
5e5b25b16167 arm64: dts: qcom: sc8180x: Add missing CPU off state
a971a001fe6a arm64: dts: qcom: sc8180x: Fix up big CPU idle state entry latency
d43c023044f1 arm64: dts: qcom: sc8180x: Hook up VDD_CX as GCC parent domain
0a90e0fc5c4b dt-bindings: clock: gcc-sc8180x: Add the missing CX power domain
7d930fbfa6d1 riscv: dts: starfive: jh7110: Add PWM node and pins configuration
98729d5d619d riscv: dts: starfive: jh7100: Add PWM node and pins configuration
2613a64bdc5e dt-bindings: spi: nxp-fspi: support i.MX93 and i.MX95
36d4b81404af dt-bindings: spi: fsl-lpspi: support i.MX95 LPSPI
3ff4d525b9f7 ASoC: dt-bindings: fsl-sai: Support Rx-only SAI
fc98068e41fe ASoC: dt-bindings: fsl-sai: Add power-domains
7e4487f7e723 ASoC: Support SAI and MICFIL on i.MX95 platform
170639843215 dt-bindings: iio: pressure: honeywell,mprls0025pa.yaml add spi bus
e06b0404e4ef dt-bindings: iio: pressure: honeywell,mprls0025pa.yaml add pressure-triplet
cb500c9133ee dt-bindings: iio: pressure: honeywell,mprls0025pa.yaml improvements
0c9fbdab661d dt-bindings: iio: light: as73211: add support for as7331
668faa4c00b6 ARM: dts: qcom: ipq4019: correct clock order in DWC3 node
01f571222843 ARM: dts: qcom: sdx65: correct clock order in DWC3 node
f0606dbf1b06 ARM: dts: qcom: ipq8064: drop unused reset-names from DWC3 node
638f430aa2c5 arm64: dts: qcom: qcm6490-fairphone-fp5: Enable venus node
2bf14ff2de89 arm64: dts: qcom: sc7280: Move video-firmware to chrome-common
e694053a2504 arm64: dts: qcom: x1e80100: drop qcom,drv-count
ae0bc4781d25 arm64: dts: qcom: sc7280: Add additional MSI interrupts
fbc40e8570be dt-bindings: pwm: Add bindings for OpenCores PWM Controller
f86a5abc5095 ASoC: codecs: add support for WCD939x Codec
0023860e3cd8 dt-bindings: Add DPS310 as trivial device
4d5cba356b2e docs: dt: submitting-patches: add commit subject prefix in reversed format
86c6d04414f3 docs: dt: submitting-patches: drop outdated points to TXT format
20fea215870b dt-bindings: Turn on undocumented compatible checks
c15bd0d0ea0d arm64: zynqmp: Align usb clock nodes with binding
506404184883 arm64: zynqmp: Comment all smmu entries
702fb0df1a8d arm64: zynqmp: Rename i2c?-gpio to i2c?-gpio-grp
8dae08d3ef0c arm64: zynqmp: Disable Tri-state for MIO38 Pin
08cee7c9acca arm64: zynqmp: Remove incorrect comment from kv260s
c28bc39bcbe4 arm64: zynqmp: Introduce u-boot options node with bootscr-address
346b5266ae26 arm64: zynqmp: Fix comment to be aligned with board name.
69a088e616d5 arm64: zynqmp: Update ECAM size to discover up to 256 buses
c78a834d7d85 arm64: zynqmp: Describe assigned-clocks for uarts
aab3209386cd arm64: zynqmp: Setup default si570 frequency to 156.25MHz
70d8c607c90e arm64: zynqmp: Add resets property for CAN nodes
1e662bbad32e arm64: zynqmp: Add an OP-TEE node to the device tree
b97de3d1f0f1 arm64: zynqmp: Add output-enable pins to SOMs
5149181eb2a0 arm64: zynqmp: Rename zynqmp-power node to power-management
4bbdddd5f137 dt-bindings: firmware: xilinx: Sort node names (clock-controller)
bbe26a5d3a74 dt-bindings: firmware: xilinx: Describe missing child nodes
3bb58ba1f178 dt-bindings: firmware: xilinx: Fix versal-fpga node name
552578beff16 dt-bindings: firmware: versal: add versal-net compatible string
a1e42c2d1feb dt-bindings: timer: exynos4210-mct: Add google,gs101-mct compatible
793923947260 dt-bindings: i2c: exynos5: add google,gs101-hsi2c compatible
e40d0f28e904 ARM: dts: samsung: exynos4412-p4note: add accelerometer and gyro to p4note
b0f7ebf9ebb5 ARM: dts: samsung: exynos5800-peach: Enable cros-ec-spi as wake source
7fb70f62fdc1 ARM: dts: samsung: exynos5420-peach: Enable cros-ec-spi as wake source
69ffe89c1f09 ARM: dts: samsung: exynos5422-odroidxu3: disable thermal polling
efc6740c2555 arm64: dts: renesas: r8a779g0: Restore sort order
4d29837048f1 ARM: dts: renesas: r8a73a4: Fix thermal parent clock
b3b5e2c31a6a ARM: dts: renesas: r8a73a4: Add cp clock
0355cc519d58 ARM: dts: renesas: r8a73a4: Fix external clocks and clock rate
c7faddebe0f9 arm64: dts: renesas: rzg3s-smarc: Add gpio keys
cf58f575cc98 dt-bindings: regulator: Convert ti,tps65132 to YAML
fc588d5d53ae ASoC: dt-bindings: Do not override firmware-name $ref
81002cf24ea5 ASoC: dt-bindings: document WCD939x Audio Codec
f47aa77e7a94 ASoC: dt-bindings: qcom,wcd938x: move out common properties
d7f07526a034 ASoC: dt-bindings: fsl,micfil: Add compatible string for i.MX95 platform
e4fa9d184d78 ASoC: dt-bindings: fsl,sai: Add compatible string for i.MX95 platform
6d65dad20b03 dt-bindings: input: touchscreen: goodix: clarify irq-gpios misleading text
1f08757666ca dt-bindings: input: silead,gsl1680: do not override firmware-name $ref
ffc68c88254b dt-bindings: display: panel: Add Novatek NT36672E LCD DSI
22dafcaa7945 dt-bindings: display: panel: Add BOE TH101MB31IG002-28A panel
29e394c3abcd dt-bindings: nt35510: add compatible for FRIDA FRD400B25025-A-CTK
c378224488e5 dt-bindings: display: Add SSD133x OLED controllers
d4d009fba537 dt-bindings: display: ssd132x: Add vendor prefix to width and height
b74c86bcffbc dt-bindings: display: ssd1307fb: Add vendor prefix to width and height
140b66753a95 dt-bindings: panel: lvds: Append edt,etml0700z9ndha in panel-lvds
git-subtree-dir: dts/upstream
git-subtree-split: 7e08733c96c84eb323f47e9b248c924e2ac6272a
Diffstat (limited to 'src/arm64/ti')
119 files changed, 5190 insertions, 1396 deletions
diff --git a/src/arm64/ti/k3-am62-lp-sk.dts b/src/arm64/ti/k3-am62-lp-sk.dts index 5e6feb8..c414905 100644 --- a/src/arm64/ti/k3-am62-lp-sk.dts +++ b/src/arm64/ti/k3-am62-lp-sk.dts @@ -1,8 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * AM62x LP SK: https://www.ti.com/tool/SK-AM62-LP * - * Copyright (C) 2021-2023 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/src/arm64/ti/k3-am62-main.dtsi b/src/arm64/ti/k3-am62-main.dtsi index 464b756..e9cffca 100644 --- a/src/arm64/ti/k3-am62-main.dtsi +++ b/src/arm64/ti/k3-am62-main.dtsi @@ -1,8 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree Source for AM625 SoC Family Main Domain peripherals * - * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/ */ &cbass_main { @@ -42,9 +42,8 @@ }; }; - main_conf: syscon@100000 { - compatible = "syscon", "simple-mfd"; - reg = <0x00 0x00100000 0x00 0x20000>; + main_conf: bus@100000 { + compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x00 0x00100000 0x20000>; @@ -559,10 +558,9 @@ clock-names = "clk_ahb", "clk_xin"; assigned-clocks = <&k3_clks 57 6>; assigned-clock-parents = <&k3_clks 57 8>; + bus-width = <8>; mmc-ddr-1_8v; mmc-hs200-1_8v; - ti,trm-icp = <0x2>; - bus-width = <8>; ti,clkbuf-sel = <0x7>; ti,otap-del-sel-legacy = <0x0>; ti,otap-del-sel-mmc-hs = <0x0>; @@ -580,7 +578,8 @@ power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 58 5>, <&k3_clks 58 6>; clock-names = "clk_ahb", "clk_xin"; - ti,trm-icp = <0x2>; + bus-width = <4>; + ti,clkbuf-sel = <0x7>; ti,otap-del-sel-legacy = <0x8>; ti,otap-del-sel-sd-hs = <0x0>; ti,otap-del-sel-sdr12 = <0x0>; @@ -592,8 +591,6 @@ ti,itap-del-sel-sd-hs = <0x1>; ti,itap-del-sel-sdr12 = <0xa>; ti,itap-del-sel-sdr25 = <0x1>; - ti,clkbuf-sel = <0x7>; - bus-width = <4>; status = "disabled"; }; @@ -604,7 +601,8 @@ power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 184 5>, <&k3_clks 184 6>; clock-names = "clk_ahb", "clk_xin"; - ti,trm-icp = <0x2>; + bus-width = <4>; + ti,clkbuf-sel = <0x7>; ti,otap-del-sel-legacy = <0x8>; ti,otap-del-sel-sd-hs = <0x0>; ti,otap-del-sel-sdr12 = <0x0>; @@ -616,7 +614,6 @@ ti,itap-del-sel-sd-hs = <0xa>; ti,itap-del-sel-sdr12 = <0xa>; ti,itap-del-sel-sdr25 = <0x1>; - ti,clkbuf-sel = <0x7>; status = "disabled"; }; @@ -640,6 +637,8 @@ interrupt-names = "host", "peripheral"; maximum-speed = "high-speed"; dr_mode = "otg"; + snps,usb2-gadget-lpm-disable; + snps,usb2-lpm-disable; }; }; @@ -663,6 +662,8 @@ interrupt-names = "host", "peripheral"; maximum-speed = "high-speed"; dr_mode = "otg"; + snps,usb2-gadget-lpm-disable; + snps,usb2-lpm-disable; }; }; @@ -779,9 +780,10 @@ <0x00 0x30207000 0x00 0x1000>, /* ovr1 */ <0x00 0x30208000 0x00 0x1000>, /* ovr2 */ <0x00 0x3020a000 0x00 0x1000>, /* vp1: Used for OLDI */ - <0x00 0x3020b000 0x00 0x1000>; /* vp2: Used as DPI Out */ + <0x00 0x3020b000 0x00 0x1000>, /* vp2: Used as DPI Out */ + <0x00 0x30201000 0x00 0x1000>; /* common1 */ reg-names = "common", "vidl1", "vid", - "ovr1", "ovr2", "vp1", "vp2"; + "ovr1", "ovr2", "vp1", "vp2", "common1"; power-domains = <&k3_pds 186 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 186 6>, <&dss_vp1_clk>, diff --git a/src/arm64/ti/k3-am62-mcu.dtsi b/src/arm64/ti/k3-am62-mcu.dtsi index 0e0b234..e66d486 100644 --- a/src/arm64/ti/k3-am62-mcu.dtsi +++ b/src/arm64/ti/k3-am62-mcu.dtsi @@ -1,8 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree Source for AM625 SoC Family MCU Domain peripherals * - * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/ */ &cbass_mcu { diff --git a/src/arm64/ti/k3-am62-phycore-som.dtsi b/src/arm64/ti/k3-am62-phycore-som.dtsi index aa43e74..43488cc 100644 --- a/src/arm64/ti/k3-am62-phycore-som.dtsi +++ b/src/arm64/ti/k3-am62-phycore-som.dtsi @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* - * Copyright (C) 2022 - 2023 PHYTEC Messtechnik GmbH + * Copyright (C) 2022-2024 PHYTEC Messtechnik GmbH * Author: Wadim Egorov <w.egorov@phytec.de> * * Product homepage: @@ -317,7 +317,6 @@ &sdhci0 { pinctrl-names = "default"; pinctrl-0 = <&main_mmc0_pins_default>; - ti,driver-strength-ohm = <50>; disable-wp; non-removable; status = "okay"; diff --git a/src/arm64/ti/k3-am62-thermal.dtsi b/src/arm64/ti/k3-am62-thermal.dtsi index a358757..12ba833 100644 --- a/src/arm64/ti/k3-am62-thermal.dtsi +++ b/src/arm64/ti/k3-am62-thermal.dtsi @@ -1,4 +1,7 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ + */ #include <dt-bindings/thermal/thermal.h> diff --git a/src/arm64/ti/k3-am62-verdin-dahlia.dtsi b/src/arm64/ti/k3-am62-verdin-dahlia.dtsi index bf6d27e..6c4cec8 100644 --- a/src/arm64/ti/k3-am62-verdin-dahlia.dtsi +++ b/src/arm64/ti/k3-am62-verdin-dahlia.dtsi @@ -185,7 +185,6 @@ /* Verdin SD_1 */ &sdhci1 { - ti,driver-strength-ohm = <33>; status = "okay"; }; diff --git a/src/arm64/ti/k3-am62-verdin-dev.dtsi b/src/arm64/ti/k3-am62-verdin-dev.dtsi index 6800716..be62648 100644 --- a/src/arm64/ti/k3-am62-verdin-dev.dtsi +++ b/src/arm64/ti/k3-am62-verdin-dev.dtsi @@ -206,7 +206,6 @@ /* Verdin SD_1 */ &sdhci1 { - ti,driver-strength-ohm = <33>; status = "okay"; }; diff --git a/src/arm64/ti/k3-am62-verdin-mallow.dtsi b/src/arm64/ti/k3-am62-verdin-mallow.dtsi index 17b9353..77b1beb 100644 --- a/src/arm64/ti/k3-am62-verdin-mallow.dtsi +++ b/src/arm64/ti/k3-am62-verdin-mallow.dtsi @@ -127,6 +127,16 @@ <&pinctrl_qspi1_cs2_gpio>; cs-gpios = <0>, <&main_gpio0 12 GPIO_ACTIVE_LOW>; status = "okay"; + + tpm@1 { + compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; + reg = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi1_dqs_gpio>; + interrupt-parent = <&main_gpio1>; + interrupts = <18 IRQ_TYPE_EDGE_FALLING>; + spi-max-frequency = <18500000>; + }; }; /* Verdin UART_3 */ diff --git a/src/arm64/ti/k3-am62-verdin-wifi.dtsi b/src/arm64/ti/k3-am62-verdin-wifi.dtsi index a6808b1..4768ef4 100644 --- a/src/arm64/ti/k3-am62-verdin-wifi.dtsi +++ b/src/arm64/ti/k3-am62-verdin-wifi.dtsi @@ -26,7 +26,6 @@ mmc-pwrseq = <&wifi_pwrseq>; non-removable; ti,fails-without-test-cd; - ti,driver-strength-ohm = <50>; vmmc-supply = <®_3v3>; status = "okay"; }; diff --git a/src/arm64/ti/k3-am62-verdin.dtsi b/src/arm64/ti/k3-am62-verdin.dtsi index 6a06724..e8d8857 100644 --- a/src/arm64/ti/k3-am62-verdin.dtsi +++ b/src/arm64/ti/k3-am62-verdin.dtsi @@ -42,6 +42,22 @@ usb1 = &usb1; }; + connector { + compatible = "gpio-usb-b-connector", "usb-b-connector"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0_id>; + id-gpios = <&main_gpio1 19 GPIO_ACTIVE_HIGH>; + label = "USB_1"; + self-powered; + vbus-supply = <®_usb0_vbus>; + + port { + usb_dr_connector: endpoint { + remote-endpoint = <&usb0_ep>; + }; + }; + }; + verdin_gpio_keys: gpio-keys { compatible = "gpio-keys"; pinctrl-names = "default"; @@ -151,6 +167,18 @@ vin-supply = <®_sd_3v3_1v8>; }; + reg_usb0_vbus: regulator-usb0-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0_en>; + enable-active-high; + /* Verdin USB_1_EN (SODIMM 155) */ + gpio = <&main_gpio1 50 GPIO_ACTIVE_HIGH>; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "USB_1_EN"; + }; + reserved-memory { #address-cells = <2>; #size-cells = <2>; @@ -436,6 +464,13 @@ >; }; + /* Verdin USB_1_EN */ + pinctrl_usb0_en: main-gpio1-50-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x0254, PIN_INPUT, 7) /* (C20) USB0_DRVVBUS.GPIO1_50 */ /* SODIMM 155 */ + >; + }; + /* On-module I2C - PMIC_I2C */ pinctrl_i2c0: main-i2c0-default-pins { pinctrl-single,pins = < @@ -660,13 +695,6 @@ >; }; - /* Verdin USB_1 */ - pinctrl_usb0: main-usb0-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x0254, PIN_OUTPUT, 0) /* (C20) USB0_DRVVBUS */ /* SODIMM 155 */ - >; - }; - /* Verdin USB_2 */ pinctrl_usb1: main-usb1-default-pins { pinctrl-single,pins = < @@ -1013,7 +1041,7 @@ "", "", "SODIMM_17", - "", /* 50 */ + "SODIMM_155", /* 50 */ "", "", "", @@ -1118,7 +1146,7 @@ regulator-always-on; regulator-boot-on; regulator-max-microvolt = <850000>; - regulator-min-microvolt = <850000>; + regulator-min-microvolt = <750000>; regulator-name = "+VDD_CORE (PMIC BUCK1)"; }; @@ -1407,7 +1435,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci0>; non-removable; - ti,driver-strength-ohm = <50>; status = "okay"; }; @@ -1416,7 +1443,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1>; disable-wp; - ti,driver-strength-ohm = <50>; vmmc-supply = <®_sdhc1_vmmc>; vqmmc-supply = <®_sdhc1_vqmmc>; status = "disabled"; @@ -1428,11 +1454,16 @@ status = "disabled"; }; -/* TODO: role swich using ID pin */ &usb0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb0_id>; + adp-disable; + usb-role-switch; status = "disabled"; + + port { + usb0_ep: endpoint { + remote-endpoint = <&usb_dr_connector>; + }; + }; }; /* Verdin USB_2 */ diff --git a/src/arm64/ti/k3-am62-wakeup.dtsi b/src/arm64/ti/k3-am62-wakeup.dtsi index fef76f5..23ce1bf 100644 --- a/src/arm64/ti/k3-am62-wakeup.dtsi +++ b/src/arm64/ti/k3-am62-wakeup.dtsi @@ -1,10 +1,12 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree Source for AM625 SoC Family Wakeup Domain peripherals * - * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/ */ +#include <dt-bindings/bus/ti-sysc.h> + &cbass_wakeup { wkup_conf: syscon@43000000 { bootph-all; @@ -21,14 +23,34 @@ }; }; - wkup_uart0: serial@2b300000 { - compatible = "ti,am64-uart", "ti,am654-uart"; - reg = <0x00 0x2b300000 0x00 0x100>; - interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; + target-module@2b300050 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x00 0x2b300050 0x00 0x4>, + <0x00 0x2b300054 0x00 0x4>, + <0x00 0x2b300058 0x00 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>, + <SYSC_IDLE_SMART_WKUP>; + ti,syss-mask = <1>; + ti,no-reset-on-init; power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 114 0>; - clock-names = "fclk"; - status = "disabled"; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x00 0x2b300000 0x100000>; + + wkup_uart0: serial@0 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x0 0x100>; + interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; }; wkup_i2c0: i2c@2b200000 { diff --git a/src/arm64/ti/k3-am62.dtsi b/src/arm64/ti/k3-am62.dtsi index f1e1520..f0781f2 100644 --- a/src/arm64/ti/k3-am62.dtsi +++ b/src/arm64/ti/k3-am62.dtsi @@ -1,8 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree Source for AM62 SoC Family * - * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/ */ #include <dt-bindings/gpio/gpio.h> diff --git a/src/arm64/ti/k3-am625-beagleplay-csi2-ov5640.dtso b/src/arm64/ti/k3-am625-beagleplay-csi2-ov5640.dtso index 5e80ca7..3b4643b 100644 --- a/src/arm64/ti/k3-am625-beagleplay-csi2-ov5640.dtso +++ b/src/arm64/ti/k3-am625-beagleplay-csi2-ov5640.dtso @@ -1,7 +1,7 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * ALINX AN5641 & Digilent PCam 5C - OV5640 camera module - * Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/src/arm64/ti/k3-am625-beagleplay-csi2-tevi-ov5640.dtso b/src/arm64/ti/k3-am625-beagleplay-csi2-tevi-ov5640.dtso index 5e1cbbc..81a2763 100644 --- a/src/arm64/ti/k3-am625-beagleplay-csi2-tevi-ov5640.dtso +++ b/src/arm64/ti/k3-am625-beagleplay-csi2-tevi-ov5640.dtso @@ -1,7 +1,7 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Technexion TEVI-OV5640-*-RPI - OV5640 camera module - * Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/src/arm64/ti/k3-am625-beagleplay.dts b/src/arm64/ti/k3-am625-beagleplay.dts index eadbdd9..a34e0df 100644 --- a/src/arm64/ti/k3-am625-beagleplay.dts +++ b/src/arm64/ti/k3-am625-beagleplay.dts @@ -1,9 +1,9 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * https://beagleplay.org/ * - * Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ - * Copyright (C) 2022-2023 Robert Nelson, BeagleBoard.org Foundation + * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2022-2024 Robert Nelson, BeagleBoard.org Foundation */ /dts-v1/; @@ -29,7 +29,6 @@ i2c3 = &main_i2c3; i2c4 = &wkup_i2c0; i2c5 = &mcu_i2c0; - mdio-gpio0 = &mdio0; mmc0 = &sdhci0; mmc1 = &sdhci1; mmc2 = &sdhci2; @@ -231,27 +230,6 @@ }; }; - /* Workaround for errata i2329 - just use mdio bitbang */ - mdio0: mdio { - compatible = "virtual,mdio-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&mdio0_pins_default>; - gpios = <&main_gpio0 86 GPIO_ACTIVE_HIGH>, /* MDC */ - <&main_gpio0 85 GPIO_ACTIVE_HIGH>; /* MDIO */ - #address-cells = <1>; - #size-cells = <0>; - - cpsw3g_phy0: ethernet-phy@0 { - reg = <0>; - }; - - cpsw3g_phy1: ethernet-phy@1 { - reg = <1>; - reset-gpios = <&main_gpio1 5 GPIO_ACTIVE_LOW>; - reset-assert-us = <25>; - reset-deassert-us = <60000>; /* T2 */ - }; - }; }; &main_pmx0 { @@ -312,8 +290,8 @@ mdio0_pins_default: mdio0-default-pins { pinctrl-single,pins = < - AM62X_IOPAD(0x0160, PIN_OUTPUT, 7) /* (AD24) MDIO0_MDC.GPIO0_86 */ - AM62X_IOPAD(0x015c, PIN_INPUT, 7) /* (AB22) MDIO0_MDIO.GPIO0_85 */ + AM62X_IOPAD(0x0160, PIN_OUTPUT, 0) /* (AD24) MDIO0_MDC */ + AM62X_IOPAD(0x015c, PIN_INPUT, 0) /* (AB22) MDIO0_MDIO */ >; }; @@ -573,11 +551,13 @@ }; &usbss0 { + bootph-all; ti,vbus-divider; status = "okay"; }; &usb0 { + bootph-all; dr_mode = "peripheral"; }; @@ -611,8 +591,20 @@ }; &cpsw3g_mdio { - /* Workaround for errata i2329 - Use mdio bitbang */ - status = "disabled"; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mdio0_pins_default>; + + cpsw3g_phy0: ethernet-phy@0 { + reg = <0>; + }; + + cpsw3g_phy1: ethernet-phy@1 { + reg = <1>; + reset-gpios = <&main_gpio1 5 GPIO_ACTIVE_LOW>; + reset-assert-us = <25>; + reset-deassert-us = <60000>; /* T2 */ + }; }; &main_gpio0 { @@ -827,7 +819,6 @@ bootph-all; pinctrl-names = "default"; pinctrl-0 = <&emmc_pins_default>; - ti,driver-strength-ohm = <50>; disable-wp; status = "okay"; }; @@ -840,7 +831,6 @@ vmmc-supply = <&vdd_3v3_sd>; vqmmc-supply = <&vdd_sd_dv>; - ti,driver-strength-ohm = <50>; disable-wp; cd-gpios = <&main_gpio1 48 GPIO_ACTIVE_LOW>; cd-debounce-delay-ms = <100>; @@ -852,12 +842,10 @@ vmmc-supply = <&wlan_en>; pinctrl-names = "default"; pinctrl-0 = <&wifi_pins_default>, <&wifi_32k_clk>; - bus-width = <4>; non-removable; ti,fails-without-test-cd; cap-power-off-card; keep-power-in-suspend; - ti,driver-strength-ohm = <50>; assigned-clocks = <&k3_clks 157 158>; assigned-clock-parents = <&k3_clks 157 160>; #address-cells = <1>; diff --git a/src/arm64/ti/k3-am625-phyboard-lyra-rdk.dts b/src/arm64/ti/k3-am625-phyboard-lyra-rdk.dts index 4bc0134..a83a904 100644 --- a/src/arm64/ti/k3-am625-phyboard-lyra-rdk.dts +++ b/src/arm64/ti/k3-am625-phyboard-lyra-rdk.dts @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* - * Copyright (C) 2022 - 2023 PHYTEC Messtechnik GmbH + * Copyright (C) 2022-2024 PHYTEC Messtechnik GmbH * Author: Wadim Egorov <w.egorov@phytec.de> * * Product homepage: @@ -222,6 +222,7 @@ cpsw3g_phy3: ethernet-phy@3 { compatible = "ethernet-phy-id2000.a231", "ethernet-phy-ieee802.3-c22"; reg = <3>; + ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; }; @@ -333,7 +334,6 @@ vqmmc-supply = <&vddshv5_sdio>; pinctrl-names = "default"; pinctrl-0 = <&main_mmc1_pins_default>; - ti,driver-strength-ohm = <50>; disable-wp; no-1-8-v; status = "okay"; diff --git a/src/arm64/ti/k3-am625-sk.dts b/src/arm64/ti/k3-am625-sk.dts index b180924..ae81ebb 100644 --- a/src/arm64/ti/k3-am625-sk.dts +++ b/src/arm64/ti/k3-am625-sk.dts @@ -1,8 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * AM625 SK: https://www.ti.com/lit/zip/sprr448 * - * Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/src/arm64/ti/k3-am625.dtsi b/src/arm64/ti/k3-am625.dtsi index 4193c2b..4014add 100644 --- a/src/arm64/ti/k3-am625.dtsi +++ b/src/arm64/ti/k3-am625.dtsi @@ -1,10 +1,10 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree Source for AM625 SoC family in Quad core configuration * * TRM: https://www.ti.com/lit/pdf/spruiv7 * - * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/src/arm64/ti/k3-am62a-main.dtsi b/src/arm64/ti/k3-am62a-main.dtsi index f0b8c9a..aa1e057 100644 --- a/src/arm64/ti/k3-am62a-main.dtsi +++ b/src/arm64/ti/k3-am62a-main.dtsi @@ -1,8 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree Source for AM62A SoC Family Main Domain peripherals * - * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/ */ &cbass_main { @@ -42,9 +42,8 @@ }; }; - main_conf: syscon@100000 { - compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; - reg = <0x00 0x00100000 0x00 0x20000>; + main_conf: bus@100000 { + compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00 0x00 0x00100000 0x20000>; @@ -536,6 +535,24 @@ status = "disabled"; }; + sdhci0: mmc@fa10000 { + compatible = "ti,am62-sdhci"; + reg = <0x00 0xfa10000 0x00 0x260>, <0x00 0xfa18000 0x00 0x134>; + interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 57 5>, <&k3_clks 57 6>; + clock-names = "clk_ahb", "clk_xin"; + assigned-clocks = <&k3_clks 57 6>; + assigned-clock-parents = <&k3_clks 57 8>; + bus-width = <8>; + mmc-hs200-1_8v; + ti,clkbuf-sel = <0x7>; + ti,otap-del-sel-legacy = <0x0>; + ti,otap-del-sel-mmc-hs = <0x0>; + ti,otap-del-sel-hs200 = <0x6>; + status = "disabled"; + }; + sdhci1: mmc@fa00000 { compatible = "ti,am62-sdhci"; reg = <0x00 0xfa00000 0x00 0x260>, <0x00 0xfa08000 0x00 0x134>; @@ -543,7 +560,8 @@ power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 58 5>, <&k3_clks 58 6>; clock-names = "clk_ahb", "clk_xin"; - ti,trm-icp = <0x2>; + bus-width = <4>; + ti,clkbuf-sel = <0x7>; ti,otap-del-sel-legacy = <0x0>; ti,otap-del-sel-sd-hs = <0x0>; ti,otap-del-sel-sdr12 = <0xf>; @@ -555,8 +573,30 @@ ti,itap-del-sel-sd-hs = <0x0>; ti,itap-del-sel-sdr12 = <0x0>; ti,itap-del-sel-sdr25 = <0x0>; - ti,clkbuf-sel = <0x7>; + no-1-8-v; + status = "disabled"; + }; + + sdhci2: mmc@fa20000 { + compatible = "ti,am62-sdhci"; + reg = <0x00 0xfa20000 0x00 0x260>, <0x00 0xfa28000 0x00 0x134>; + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 184 5>, <&k3_clks 184 6>; + clock-names = "clk_ahb", "clk_xin"; bus-width = <4>; + ti,clkbuf-sel = <0x7>; + ti,otap-del-sel-legacy = <0x0>; + ti,otap-del-sel-sd-hs = <0x0>; + ti,otap-del-sel-sdr12 = <0xf>; + ti,otap-del-sel-sdr25 = <0xf>; + ti,otap-del-sel-sdr50 = <0xc>; + ti,otap-del-sel-sdr104 = <0x6>; + ti,otap-del-sel-ddr50 = <0x9>; + ti,itap-del-sel-legacy = <0x0>; + ti,itap-del-sel-sd-hs = <0x0>; + ti,itap-del-sel-sdr12 = <0x0>; + ti,itap-del-sel-sdr25 = <0x0>; no-1-8-v; status = "disabled"; }; @@ -985,4 +1025,30 @@ power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>; status = "disabled"; }; + + dss: dss@30200000 { + compatible = "ti,am62a7-dss"; + reg = <0x00 0x30200000 0x00 0x1000>, /* common */ + <0x00 0x30202000 0x00 0x1000>, /* vidl1 */ + <0x00 0x30206000 0x00 0x1000>, /* vid */ + <0x00 0x30207000 0x00 0x1000>, /* ovr1 */ + <0x00 0x30208000 0x00 0x1000>, /* ovr2 */ + <0x00 0x3020a000 0x00 0x1000>, /* vp1: Tied OFF in the SoC */ + <0x00 0x3020b000 0x00 0x1000>, /* vp2: Used as DPI Out */ + <0x00 0x30201000 0x00 0x1000>; /* common1 */ + reg-names = "common", "vidl1", "vid", + "ovr1", "ovr2", "vp1", "vp2", "common1"; + power-domains = <&k3_pds 186 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 186 6>, + <&k3_clks 186 0>, + <&k3_clks 186 2>; + clock-names = "fck", "vp1", "vp2"; + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + + dss_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + }; + }; }; diff --git a/src/arm64/ti/k3-am62a-mcu.dtsi b/src/arm64/ti/k3-am62a-mcu.dtsi index a6d16a9..8c36e56 100644 --- a/src/arm64/ti/k3-am62a-mcu.dtsi +++ b/src/arm64/ti/k3-am62a-mcu.dtsi @@ -1,8 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree Source for AM625 SoC Family MCU Domain peripherals * - * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/ */ &cbass_mcu { diff --git a/src/arm64/ti/k3-am62a-thermal.dtsi b/src/arm64/ti/k3-am62a-thermal.dtsi index 85ce545..c7486fb 100644 --- a/src/arm64/ti/k3-am62a-thermal.dtsi +++ b/src/arm64/ti/k3-am62a-thermal.dtsi @@ -1,4 +1,7 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ + */ #include <dt-bindings/thermal/thermal.h> diff --git a/src/arm64/ti/k3-am62a-wakeup.dtsi b/src/arm64/ti/k3-am62a-wakeup.dtsi index 4e8279f..f7bec48 100644 --- a/src/arm64/ti/k3-am62a-wakeup.dtsi +++ b/src/arm64/ti/k3-am62a-wakeup.dtsi @@ -1,8 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree Source for AM62A SoC Family Wakeup Domain peripherals * - * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/ */ &cbass_wakeup { diff --git a/src/arm64/ti/k3-am62a.dtsi b/src/arm64/ti/k3-am62a.dtsi index 61a210e..b1b8846 100644 --- a/src/arm64/ti/k3-am62a.dtsi +++ b/src/arm64/ti/k3-am62a.dtsi @@ -1,8 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree Source for AM62A SoC Family * - * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/ */ #include <dt-bindings/gpio/gpio.h> diff --git a/src/arm64/ti/k3-am62a7-sk.dts b/src/arm64/ti/k3-am62a7-sk.dts index 7b71425..f241637 100644 --- a/src/arm64/ti/k3-am62a7-sk.dts +++ b/src/arm64/ti/k3-am62a7-sk.dts @@ -1,8 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * AM62A SK: https://www.ti.com/lit/zip/sprr459 * - * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; @@ -20,6 +20,7 @@ serial0 = &wkup_uart0; serial2 = &main_uart0; serial3 = &main_uart1; + mmc0 = &sdhci0; mmc1 = &sdhci1; }; @@ -132,6 +133,18 @@ clock-frequency = <12288000>; }; + hdmi0: connector-hdmi { + compatible = "hdmi-connector"; + label = "hdmi"; + type = "a"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&sii9022_out>; + }; + }; + }; + codec_audio: sound { compatible = "simple-audio-card"; simple-audio-card,name = "AM62Ax-SKEVM"; @@ -181,6 +194,39 @@ }; &main_pmx0 { + main_dss0_pins_default: main-dss0-default-pins { + pinctrl-single,pins = < + AM62AX_IOPAD(0x100, PIN_OUTPUT, 0) /* (V17) VOUT0_VSYNC */ + AM62AX_IOPAD(0x0f8, PIN_OUTPUT, 0) /* (T18) VOUT0_HSYNC */ + AM62AX_IOPAD(0x104, PIN_OUTPUT, 0) /* (AA22) VOUT0_PCLK */ + AM62AX_IOPAD(0x0fc, PIN_OUTPUT, 0) /* (U17) VOUT0_DE */ + AM62AX_IOPAD(0x0b8, PIN_OUTPUT, 0) /* (U22) VOUT0_DATA0 */ + AM62AX_IOPAD(0x0bc, PIN_OUTPUT, 0) /* (U21) VOUT0_DATA1 */ + AM62AX_IOPAD(0x0c0, PIN_OUTPUT, 0) /* (U20) VOUT0_DATA2 */ + AM62AX_IOPAD(0x0c4, PIN_OUTPUT, 0) /* (U19) VOUT0_DATA3 */ + AM62AX_IOPAD(0x0c8, PIN_OUTPUT, 0) /* (T19) VOUT0_DATA4 */ + AM62AX_IOPAD(0x0cc, PIN_OUTPUT, 0) /* (U18) VOUT0_DATA5 */ + AM62AX_IOPAD(0x0d0, PIN_OUTPUT, 0) /* (V22) VOUT0_DATA6 */ + AM62AX_IOPAD(0x0d4, PIN_OUTPUT, 0) /* (V21) VOUT0_DATA7 */ + AM62AX_IOPAD(0x0d8, PIN_OUTPUT, 0) /* (V19) VOUT0_DATA8 */ + AM62AX_IOPAD(0x0dc, PIN_OUTPUT, 0) /* (V18) VOUT0_DATA9 */ + AM62AX_IOPAD(0x0e0, PIN_OUTPUT, 0) /* (W22) VOUT0_DATA10 */ + AM62AX_IOPAD(0x0e4, PIN_OUTPUT, 0) /* (W21) VOUT0_DATA11 */ + AM62AX_IOPAD(0x0e8, PIN_OUTPUT, 0) /* (W20) VOUT0_DATA12 */ + AM62AX_IOPAD(0x0ec, PIN_OUTPUT, 0) /* (W19) VOUT0_DATA13 */ + AM62AX_IOPAD(0x0f0, PIN_OUTPUT, 0) /* (Y21) VOUT0_DATA14 */ + AM62AX_IOPAD(0x0f4, PIN_OUTPUT, 0) /* (Y22) VOUT0_DATA15 */ + AM62AX_IOPAD(0x05c, PIN_OUTPUT, 1) /* (P22) GPMC0_AD8.VOUT0_DATA16 */ + AM62AX_IOPAD(0x060, PIN_OUTPUT, 1) /* (R19) GPMC0_AD9.VOUT0_DATA17 */ + AM62AX_IOPAD(0x064, PIN_OUTPUT, 1) /* (R20) GPMC0_AD10.VOUT0_DATA18 */ + AM62AX_IOPAD(0x068, PIN_OUTPUT, 1) /* (R22) GPMC0_AD11.VOUT0_DATA19 */ + AM62AX_IOPAD(0x06c, PIN_OUTPUT, 1) /* (T22) GPMC0_AD12.VOUT0_DATA20 */ + AM62AX_IOPAD(0x070, PIN_OUTPUT, 1) /* (R21) GPMC0_AD13.VOUT0_DATA21 */ + AM62AX_IOPAD(0x074, PIN_OUTPUT, 1) /* (T20) GPMC0_AD14.VOUT0_DATA22 */ + AM62AX_IOPAD(0x078, PIN_OUTPUT, 1) /* (T21) GPMC0_AD15.VOUT0_DATA23 */ + >; + }; + main_uart0_pins_default: main-uart0-default-pins { pinctrl-single,pins = < AM62AX_IOPAD(0x1c8, PIN_INPUT, 0) /* (E14) UART0_RXD */ @@ -218,6 +264,22 @@ >; }; + main_mmc0_pins_default: main-mmc0-default-pins { + pinctrl-single,pins = < + AM62AX_IOPAD(0x220, PIN_INPUT, 0) /* (Y3) MMC0_CMD */ + AM62AX_IOPAD(0x218, PIN_INPUT, 0) /* (AB1) MMC0_CLKLB */ + AM62AX_IOPAD(0x21c, PIN_INPUT, 0) /* (AB1) MMC0_CLK */ + AM62AX_IOPAD(0x214, PIN_INPUT, 0) /* (AA2) MMC0_DAT0 */ + AM62AX_IOPAD(0x210, PIN_INPUT_PULLUP, 0) /* (AA1) MMC0_DAT1 */ + AM62AX_IOPAD(0x20c, PIN_INPUT_PULLUP, 0) /* (AA3) MMC0_DAT2 */ + AM62AX_IOPAD(0x208, PIN_INPUT_PULLUP, 0) /* (Y4) MMC0_DAT3 */ + AM62AX_IOPAD(0x204, PIN_INPUT_PULLUP, 0) /* (AB2) MMC0_DAT4 */ + AM62AX_IOPAD(0x200, PIN_INPUT_PULLUP, 0) /* (AC1) MMC0_DAT5 */ + AM62AX_IOPAD(0x1fc, PIN_INPUT_PULLUP, 0) /* (AD2) MMC0_DAT6 */ + AM62AX_IOPAD(0x1f8, PIN_INPUT_PULLUP, 0) /* (AC2) MMC0_DAT7 */ + >; + }; + main_mmc1_pins_default: main-mmc1-default-pins { pinctrl-single,pins = < AM62AX_IOPAD(0x23c, PIN_INPUT, 0) /* (A21) MMC1_CMD */ @@ -466,6 +528,36 @@ "CSI_EN", "AUTO_100M_1000M_CONFIG", "CSI_VLDO_SEL", "SoC_WLAN_SDIO_RST"; }; + + sii9022: bridge-hdmi@3b { + compatible = "sil,sii9022"; + reg = <0x3b>; + interrupt-parent = <&exp1>; + interrupts = <16 IRQ_TYPE_EDGE_FALLING>; + #sound-dai-cells = <0>; + sil,i2s-data-lanes = < 0 >; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + sii9022_in: endpoint { + remote-endpoint = <&dpi1_out>; + }; + }; + + port@1 { + reg = <1>; + + sii9022_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; + }; }; &main_i2c2 { @@ -475,13 +567,21 @@ clock-frequency = <400000>; }; +&sdhci0 { + /* eMMC */ + status = "okay"; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&main_mmc0_pins_default>; + disable-wp; +}; + &sdhci1 { /* SD/MMC */ status = "okay"; vmmc-supply = <&vdd_mmc1>; pinctrl-names = "default"; pinctrl-0 = <&main_mmc1_pins_default>; - ti,driver-strength-ohm = <50>; disable-wp; }; @@ -583,3 +683,20 @@ tx-num-evt = <32>; rx-num-evt = <32>; }; + +&dss { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_dss0_pins_default>; +}; + +&dss_ports { + /* VP2: DPI Output */ + port@1 { + reg = <1>; + + dpi1_out: endpoint { + remote-endpoint = <&sii9022_in>; + }; + }; +}; diff --git a/src/arm64/ti/k3-am62a7.dtsi b/src/arm64/ti/k3-am62a7.dtsi index 58f1c43..f86a234 100644 --- a/src/arm64/ti/k3-am62a7.dtsi +++ b/src/arm64/ti/k3-am62a7.dtsi @@ -1,10 +1,10 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree Source for AM62A7 SoC family in Quad core configuration * * TRM: https://www.ti.com/lit/zip/spruj16 * - * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/src/arm64/ti/k3-am62p-main.dtsi b/src/arm64/ti/k3-am62p-main.dtsi index 4c51bae..7337a9e 100644 --- a/src/arm64/ti/k3-am62p-main.dtsi +++ b/src/arm64/ti/k3-am62p-main.dtsi @@ -1,7 +1,7 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree file for the AM62P main domain peripherals - * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ */ &cbass_main { @@ -158,6 +158,43 @@ }; }; + dmss_csi: bus@4e000000 { + compatible = "simple-bus"; + ranges = <0x00 0x4e000000 0x00 0x4e000000 0x00 0x408000>; + #address-cells = <2>; + #size-cells = <2>; + dma-ranges; + ti,sci-dev-id = <198>; + + inta_main_dmss_csi: interrupt-controller@4e400000 { + compatible = "ti,sci-inta"; + reg = <0x00 0x4e400000 0x00 0x8000>; + #interrupt-cells = <0>; + interrupt-controller; + interrupt-parent = <&gic500>; + msi-controller; + power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>; + ti,sci = <&dmsc>; + ti,sci-dev-id = <200>; + ti,interrupt-ranges = <0 237 8>; + ti,unmapped-event-sources = <&main_bcdma_csi>; + }; + + main_bcdma_csi: dma-controller@4e230000 { + compatible = "ti,am62a-dmss-bcdma-csirx"; + reg = <0x00 0x4e230000 0x00 0x100>, + <0x00 0x4e180000 0x00 0x8000>, + <0x00 0x4e100000 0x00 0x10000>; + reg-names = "gcfg", "rchanrt", "ringrt"; + #dma-cells = <3>; + msi-parent = <&inta_main_dmss_csi>; + power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>; + ti,sci = <&dmsc>; + ti,sci-dev-id = <199>; + ti,sci-rm-range-rchan = <0x21>; + }; + }; + dmsc: system-controller@44043000 { compatible = "ti,k2g-sci"; ti,host-id = <12>; @@ -534,7 +571,21 @@ clock-names = "clk_ahb", "clk_xin"; assigned-clocks = <&k3_clks 57 2>; assigned-clock-parents = <&k3_clks 57 4>; - ti,otap-del-sel-legacy = <0x0>; + bus-width = <8>; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + ti,clkbuf-sel = <0x7>; + ti,strobe-sel = <0x77>; + ti,trm-icp = <0x8>; + ti,otap-del-sel-legacy = <0x1>; + ti,otap-del-sel-mmc-hs = <0x1>; + ti,otap-del-sel-ddr52 = <0x6>; + ti,otap-del-sel-hs200 = <0x8>; + ti,otap-del-sel-hs400 = <0x5>; + ti,itap-del-sel-legacy = <0x10>; + ti,itap-del-sel-mmc-hs = <0xa>; + ti,itap-del-sel-ddr52 = <0x3>; status = "disabled"; }; @@ -545,7 +596,19 @@ power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 58 5>, <&k3_clks 58 6>; clock-names = "clk_ahb", "clk_xin"; - ti,otap-del-sel-legacy = <0x8>; + bus-width = <4>; + ti,clkbuf-sel = <0x7>; + ti,otap-del-sel-legacy = <0x0>; + ti,otap-del-sel-sd-hs = <0x0>; + ti,otap-del-sel-sdr12 = <0xf>; + ti,otap-del-sel-sdr25 = <0xf>; + ti,otap-del-sel-sdr50 = <0xc>; + ti,otap-del-sel-ddr50 = <0x9>; + ti,otap-del-sel-sdr104 = <0x6>; + ti,itap-del-sel-legacy = <0x0>; + ti,itap-del-sel-sd-hs = <0x0>; + ti,itap-del-sel-sdr12 = <0x0>; + ti,itap-del-sel-sdr25 = <0x0>; status = "disabled"; }; @@ -556,7 +619,19 @@ power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 184 5>, <&k3_clks 184 6>; clock-names = "clk_ahb", "clk_xin"; - ti,otap-del-sel-legacy = <0x8>; + bus-width = <4>; + ti,clkbuf-sel = <0x7>; + ti,otap-del-sel-legacy = <0x0>; + ti,otap-del-sel-sd-hs = <0x0>; + ti,otap-del-sel-sdr12 = <0xf>; + ti,otap-del-sel-sdr25 = <0xf>; + ti,otap-del-sel-sdr50 = <0xc>; + ti,otap-del-sel-ddr50 = <0x9>; + ti,otap-del-sel-sdr104 = <0x6>; + ti,itap-del-sel-legacy = <0x0>; + ti,itap-del-sel-sd-hs = <0x0>; + ti,itap-del-sel-sdr12 = <0x0>; + ti,itap-del-sel-sdr25 = <0x0>; status = "disabled"; }; @@ -891,4 +966,73 @@ power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; status = "disabled"; }; + + ti_csi2rx0: ticsi2rx@30102000 { + compatible = "ti,j721e-csi2rx-shim"; + reg = <0x00 0x30102000 0x00 0x1000>; + ranges; + #address-cells = <2>; + #size-cells = <2>; + dmas = <&main_bcdma_csi 0 0x5000 0>; + dma-names = "rx0"; + power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + + cdns_csi2rx0: csi-bridge@30101000 { + compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; + reg = <0x00 0x30101000 0x00 0x1000>; + clocks = <&k3_clks 182 0>, <&k3_clks 182 3>, <&k3_clks 182 0>, + <&k3_clks 182 0>, <&k3_clks 182 4>, <&k3_clks 182 4>; + clock-names = "sys_clk", "p_clk", "pixel_if0_clk", + "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; + phys = <&dphy0>; + phy-names = "dphy"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi0_port0: port@0 { + reg = <0>; + status = "disabled"; + }; + + csi0_port1: port@1 { + reg = <1>; + status = "disabled"; + }; + + csi0_port2: port@2 { + reg = <2>; + status = "disabled"; + }; + + csi0_port3: port@3 { + reg = <3>; + status = "disabled"; + }; + + csi0_port4: port@4 { + reg = <4>; + status = "disabled"; + }; + }; + }; + }; + + dphy0: phy@30110000 { + compatible = "cdns,dphy-rx"; + reg = <0x00 0x30110000 0x00 0x1100>; + #phy-cells = <0>; + power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + + vpu: video-codec@30210000 { + compatible = "ti,j721s2-wave521c", "cnm,wave521c"; + reg = <0x00 0x30210000 0x00 0x10000>; + interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 204 2>; + power-domains = <&k3_pds 204 TI_SCI_PD_EXCLUSIVE>; + }; }; diff --git a/src/arm64/ti/k3-am62p-mcu.dtsi b/src/arm64/ti/k3-am62p-mcu.dtsi index c4b0b91..b973b55 100644 --- a/src/arm64/ti/k3-am62p-mcu.dtsi +++ b/src/arm64/ti/k3-am62p-mcu.dtsi @@ -1,7 +1,7 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree file for the AM62P MCU domain peripherals - * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ */ &cbass_mcu { @@ -187,6 +187,8 @@ ranges = <0x79000000 0x00 0x79000000 0x8000>, <0x79020000 0x00 0x79020000 0x8000>; power-domains = <&k3_pds 7 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + mcu_r5fss0_core0: r5f@79000000 { compatible = "ti,am62-r5f"; reg = <0x79000000 0x00008000>, diff --git a/src/arm64/ti/k3-am62p-thermal.dtsi b/src/arm64/ti/k3-am62p-thermal.dtsi index 85ce545..c7486fb 100644 --- a/src/arm64/ti/k3-am62p-thermal.dtsi +++ b/src/arm64/ti/k3-am62p-thermal.dtsi @@ -1,4 +1,7 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ + */ #include <dt-bindings/thermal/thermal.h> diff --git a/src/arm64/ti/k3-am62p-wakeup.dtsi b/src/arm64/ti/k3-am62p-wakeup.dtsi index 19f42b3..a84756c 100644 --- a/src/arm64/ti/k3-am62p-wakeup.dtsi +++ b/src/arm64/ti/k3-am62p-wakeup.dtsi @@ -1,7 +1,7 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree file for the AM62P wakeup domain peripherals - * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ */ &cbass_wakeup { @@ -78,6 +78,7 @@ ranges = <0x78000000 0x00 0x78000000 0x8000>, <0x78100000 0x00 0x78100000 0x8000>; power-domains = <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; wkup_r5fss0_core0: r5f@78000000 { compatible = "ti,am62-r5f"; diff --git a/src/arm64/ti/k3-am62p.dtsi b/src/arm64/ti/k3-am62p.dtsi index 84ffe7b..94babc4 100644 --- a/src/arm64/ti/k3-am62p.dtsi +++ b/src/arm64/ti/k3-am62p.dtsi @@ -1,8 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree Source for AM62P SoC Family * - * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ */ #include <dt-bindings/gpio/gpio.h> @@ -71,7 +71,7 @@ <0x00 0x43600000 0x00 0x43600000 0x00 0x00010000>, /* SA3 sproxy data */ <0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */ <0x00 0x44860000 0x00 0x44860000 0x00 0x00040000>, /* SA3 sproxy config */ - <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>, /* DMSS */ + <0x00 0x48000000 0x00 0x48000000 0x00 0x06408000>, /* DMSS */ <0x00 0x60000000 0x00 0x60000000 0x00 0x08000000>, /* FSS0 DAT1 */ <0x00 0x70000000 0x00 0x70000000 0x00 0x00010000>, /* OCSRAM */ <0x01 0x00000000 0x01 0x00000000 0x00 0x00310000>, /* A53 PERIPHBASE */ diff --git a/src/arm64/ti/k3-am62p5-sk.dts b/src/arm64/ti/k3-am62p5-sk.dts index 1773c05..e86f34e 100644 --- a/src/arm64/ti/k3-am62p5-sk.dts +++ b/src/arm64/ti/k3-am62p5-sk.dts @@ -1,7 +1,7 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree file for the AM62P5-SK - * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ * * Schematics: https://www.ti.com/lit/zip/sprr487 */ @@ -413,6 +413,7 @@ status = "okay"; ti,driver-strength-ohm = <50>; disable-wp; + bootph-all; }; &sdhci1 { @@ -422,9 +423,7 @@ vqmmc-supply = <&vddshv_sdio>; pinctrl-names = "default"; pinctrl-0 = <&main_mmc1_pins_default>; - ti,driver-strength-ohm = <50>; disable-wp; - no-1-8-v; bootph-all; }; @@ -445,6 +444,10 @@ }; &cpsw3g_mdio { + pinctrl-names = "default"; + pinctrl-0 = <&main_mdio1_pins_default>; + status = "okay"; + cpsw3g_phy0: ethernet-phy@0 { reg = <0>; ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; diff --git a/src/arm64/ti/k3-am62p5.dtsi b/src/arm64/ti/k3-am62p5.dtsi index 50147bb..41f479d 100644 --- a/src/arm64/ti/k3-am62p5.dtsi +++ b/src/arm64/ti/k3-am62p5.dtsi @@ -1,7 +1,7 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree file for the AM62P5 SoC family (quad core) - * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ * * TRM: https://www.ti.com/lit/pdf/spruj83 */ diff --git a/src/arm64/ti/k3-am62x-phyboard-lyra-gpio-fan.dtso b/src/arm64/ti/k3-am62x-phyboard-lyra-gpio-fan.dtso new file mode 100644 index 0000000..f0b2fd4 --- /dev/null +++ b/src/arm64/ti/k3-am62x-phyboard-lyra-gpio-fan.dtso @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Copyright (C) 2024 PHYTEC America LLC + * Author: Garrett Giordano <ggiordano@phytec.com> + */ + +/dts-v1/; +/plugin/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/thermal/thermal.h> +#include "k3-pinctrl.h" + +&{/} { + fan: gpio-fan { + compatible = "gpio-fan"; + gpio-fan,speed-map = <0 0 8600 1>; + gpios = <&main_gpio0 40 GPIO_ACTIVE_LOW>; + #cooling-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_fan_pins_default>; + }; +}; + +&main_pmx0 { + gpio_fan_pins_default: gpio-fan-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x0a4, PIN_OUTPUT, 7) /* (M22) GPMC0_DIR.GPIO0_40 */ + >; + }; +}; + +&thermal_zones { + main0_thermal: main0-thermal { + trips { + main0_thermal_trip0: main0-thermal-trip { + temperature = <65000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + }; + + cooling-maps { + map0 { + trip = <&main0_thermal_trip0>; + cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; +}; diff --git a/src/arm64/ti/k3-am62x-sk-common.dtsi b/src/arm64/ti/k3-am62x-sk-common.dtsi index 33768c0..3c45782 100644 --- a/src/arm64/ti/k3-am62x-sk-common.dtsi +++ b/src/arm64/ti/k3-am62x-sk-common.dtsi @@ -1,8 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Common dtsi for AM62x SK and derivatives * - * Copyright (C) 2021-2023 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/ */ #include <dt-bindings/leds/common.h> @@ -411,7 +411,6 @@ status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_mmc0_pins_default>; - ti,driver-strength-ohm = <50>; disable-wp; }; @@ -421,7 +420,6 @@ status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_mmc1_pins_default>; - ti,driver-strength-ohm = <50>; disable-wp; }; @@ -460,6 +458,7 @@ }; &usbss0 { + bootph-all; status = "okay"; ti,vbus-divider; }; @@ -470,6 +469,7 @@ }; &usb0 { + bootph-all; #address-cells = <1>; #size-cells = <0>; usb-role-switch; diff --git a/src/arm64/ti/k3-am62x-sk-csi2-imx219.dtso b/src/arm64/ti/k3-am62x-sk-csi2-imx219.dtso index 6f4cd73..76ca021 100644 --- a/src/arm64/ti/k3-am62x-sk-csi2-imx219.dtso +++ b/src/arm64/ti/k3-am62x-sk-csi2-imx219.dtso @@ -1,7 +1,7 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * IMX219 (RPi v2) Camera Module - * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/src/arm64/ti/k3-am62x-sk-csi2-ov5640.dtso b/src/arm64/ti/k3-am62x-sk-csi2-ov5640.dtso index 9323a4b..ccc7f5e 100644 --- a/src/arm64/ti/k3-am62x-sk-csi2-ov5640.dtso +++ b/src/arm64/ti/k3-am62x-sk-csi2-ov5640.dtso @@ -1,7 +1,7 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * ALINX AN5641 & Digilent PCam 5C - OV5640 camera module - * Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/src/arm64/ti/k3-am62x-sk-csi2-tevi-ov5640.dtso b/src/arm64/ti/k3-am62x-sk-csi2-tevi-ov5640.dtso index dcaa33a..4eaf9d7 100644 --- a/src/arm64/ti/k3-am62x-sk-csi2-tevi-ov5640.dtso +++ b/src/arm64/ti/k3-am62x-sk-csi2-tevi-ov5640.dtso @@ -1,7 +1,7 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Technexion TEVI-OV5640-*-RPI - OV5640 camera module - * Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/src/arm64/ti/k3-am62x-sk-hdmi-audio.dtso b/src/arm64/ti/k3-am62x-sk-hdmi-audio.dtso index 43a0ddc..18c3082 100644 --- a/src/arm64/ti/k3-am62x-sk-hdmi-audio.dtso +++ b/src/arm64/ti/k3-am62x-sk-hdmi-audio.dtso @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /** * Audio playback via HDMI for AM625-SK and AM62-LP SK. * @@ -6,7 +6,7 @@ * AM625 SK: https://www.ti.com/tool/SK-AM62 * AM62-LP SK: https://www.ti.com/tool/SK-AM62-LP * - * Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/src/arm64/ti/k3-am64-main.dtsi b/src/arm64/ti/k3-am64-main.dtsi index e348114..6f9aa5e 100644 --- a/src/arm64/ti/k3-am64-main.dtsi +++ b/src/arm64/ti/k3-am64-main.dtsi @@ -1,8 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree Source for AM642 SoC Family Main Domain peripherals * - * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/ */ #include <dt-bindings/phy/phy-cadence.h> @@ -51,10 +51,11 @@ reg = <0x00000014 0x4>; }; - serdes_ln_ctrl: mux-controller { - compatible = "mmio-mux"; + serdes_ln_ctrl: mux-controller@4080 { + compatible = "reg-mux"; + reg = <0x4080 0x4>; #mux-control-cells = <1>; - mux-reg-masks = <0x4080 0x3>; /* SERDES0 lane0 select */ + mux-reg-masks = <0x0 0x3>; /* SERDES0 lane0 select */ }; phy_gmii_sel: phy@4044 { @@ -626,13 +627,18 @@ power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 57 0>, <&k3_clks 57 1>; clock-names = "clk_ahb", "clk_xin"; + bus-width = <8>; mmc-ddr-1_8v; mmc-hs200-1_8v; + ti,clkbuf-sel = <0x7>; ti,trm-icp = <0x2>; ti,otap-del-sel-legacy = <0x0>; ti,otap-del-sel-mmc-hs = <0x0>; ti,otap-del-sel-ddr52 = <0x6>; ti,otap-del-sel-hs200 = <0x7>; + ti,itap-del-sel-legacy = <0x10>; + ti,itap-del-sel-mmc-hs = <0xa>; + ti,itap-del-sel-ddr52 = <0x3>; status = "disabled"; }; @@ -643,15 +649,19 @@ power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 58 3>, <&k3_clks 58 4>; clock-names = "clk_ahb", "clk_xin"; - ti,trm-icp = <0x2>; + bus-width = <4>; + ti,clkbuf-sel = <0x7>; ti,otap-del-sel-legacy = <0x0>; - ti,otap-del-sel-sd-hs = <0xf>; + ti,otap-del-sel-sd-hs = <0x0>; ti,otap-del-sel-sdr12 = <0xf>; ti,otap-del-sel-sdr25 = <0xf>; ti,otap-del-sel-sdr50 = <0xc>; ti,otap-del-sel-sdr104 = <0x6>; ti,otap-del-sel-ddr50 = <0x9>; - ti,clkbuf-sel = <0x7>; + ti,itap-del-sel-legacy = <0x0>; + ti,itap-del-sel-sd-hs = <0x0>; + ti,itap-del-sel-sdr12 = <0x0>; + ti,itap-del-sel-sdr25 = <0x0>; status = "disabled"; }; @@ -1041,25 +1051,6 @@ status = "disabled"; }; - pcie0_ep: pcie-ep@f102000 { - compatible = "ti,am64-pcie-ep", "ti,j721e-pcie-ep"; - reg = <0x00 0x0f102000 0x00 0x1000>, - <0x00 0x0f100000 0x00 0x400>, - <0x00 0x0d000000 0x00 0x00800000>, - <0x00 0x68000000 0x00 0x08000000>; - reg-names = "intd_cfg", "user_cfg", "reg", "mem"; - interrupt-names = "link_state"; - interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>; - ti,syscon-pcie-ctrl = <&main_conf 0x4070>; - max-link-speed = <2>; - num-lanes = <1>; - power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 114 0>; - clock-names = "fck"; - max-functions = /bits/ 8 <1>; - status = "disabled"; - }; - epwm0: pwm@23000000 { compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; #pwm-cells = <3>; @@ -1244,6 +1235,18 @@ }; }; + icssg0_iep0: iep@2e000 { + compatible = "ti,am654-icss-iep"; + reg = <0x2e000 0x1000>; + clocks = <&icssg0_iepclk_mux>; + }; + + icssg0_iep1: iep@2f000 { + compatible = "ti,am654-icss-iep"; + reg = <0x2f000 0x1000>; + clocks = <&icssg0_iepclk_mux>; + }; + icssg0_mii_rt: mii-rt@32000 { compatible = "ti,pruss-mii", "syscon"; reg = <0x32000 0x100>; @@ -1385,6 +1388,18 @@ }; }; + icssg1_iep0: iep@2e000 { + compatible = "ti,am654-icss-iep"; + reg = <0x2e000 0x1000>; + clocks = <&icssg1_iepclk_mux>; + }; + + icssg1_iep1: iep@2f000 { + compatible = "ti,am654-icss-iep"; + reg = <0x2f000 0x1000>; + clocks = <&icssg1_iepclk_mux>; + }; + icssg1_mii_rt: mii-rt@32000 { compatible = "ti,pruss-mii", "syscon"; reg = <0x32000 0x100>; diff --git a/src/arm64/ti/k3-am64-mcu.dtsi b/src/arm64/ti/k3-am64-mcu.dtsi index b950807..ec17285 100644 --- a/src/arm64/ti/k3-am64-mcu.dtsi +++ b/src/arm64/ti/k3-am64-mcu.dtsi @@ -1,8 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree Source for AM64 SoC Family MCU Domain peripherals * - * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/ */ &cbass_mcu { diff --git a/src/arm64/ti/k3-am64-phycore-som.dtsi b/src/arm64/ti/k3-am64-phycore-som.dtsi index 1678e74..125e507 100644 --- a/src/arm64/ti/k3-am64-phycore-som.dtsi +++ b/src/arm64/ti/k3-am64-phycore-som.dtsi @@ -1,9 +1,9 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* - * Copyright (C) 2021 PHYTEC America, LLC - https://www.phytec.com + * Copyright (C) 2021-2024 PHYTEC America, LLC - https://www.phytec.com * Author: Matt McKee <mmckee@phytec.com> * - * Copyright (C) 2022 PHYTEC Messtechnik GmbH + * Copyright (C) 2022-2024 PHYTEC Messtechnik GmbH * Author: Wadim Egorov <w.egorov@phytec.de> * * Product homepage: @@ -318,3 +318,10 @@ disable-wp; keep-power-in-suspend; }; + +&tscadc0 { + status = "okay"; + adc { + ti,adc-channels = <0 1 2 3 4 5 6 7>; + }; +}; diff --git a/src/arm64/ti/k3-am64-thermal.dtsi b/src/arm64/ti/k3-am64-thermal.dtsi index 036db56..b1cd554 100644 --- a/src/arm64/ti/k3-am64-thermal.dtsi +++ b/src/arm64/ti/k3-am64-thermal.dtsi @@ -1,4 +1,7 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ + */ #include <dt-bindings/thermal/thermal.h> diff --git a/src/arm64/ti/k3-am64.dtsi b/src/arm64/ti/k3-am64.dtsi index 0187c42..74e56cc 100644 --- a/src/arm64/ti/k3-am64.dtsi +++ b/src/arm64/ti/k3-am64.dtsi @@ -1,8 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree Source for AM642 SoC Family * - * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/ */ #include <dt-bindings/gpio/gpio.h> diff --git a/src/arm64/ti/k3-am642-evm-icssg1-dualemac.dtso b/src/arm64/ti/k3-am642-evm-icssg1-dualemac.dtso new file mode 100644 index 0000000..af2fd3e --- /dev/null +++ b/src/arm64/ti/k3-am642-evm-icssg1-dualemac.dtso @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/** + * DT overlay for enabling 2nd ICSSG1 port on AM642 EVM + * + * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include <dt-bindings/gpio/gpio.h> +#include "k3-pinctrl.h" + +&{/} { + aliases { + ethernet1 = "/icssg1-eth/ethernet-ports/port@1"; + }; + + mdio-mux-2 { + compatible = "mdio-mux-multiplexer"; + mux-controls = <&mdio_mux>; + mdio-parent-bus = <&icssg1_mdio>; + #address-cells = <1>; + #size-cells = <0>; + + mdio@0 { + reg = <0x0>; + #address-cells = <1>; + #size-cells = <0>; + + icssg1_phy2: ethernet-phy@3 { + reg = <3>; + tx-internal-delay-ps = <250>; + rx-internal-delay-ps = <2000>; + }; + }; + }; +}; + +&main_pmx0 { + icssg1_rgmii2_pins_default: icssg1-rgmii2-default-pins { + pinctrl-single,pins = < + AM64X_IOPAD(0x0108, PIN_INPUT, 2) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */ + AM64X_IOPAD(0x010c, PIN_INPUT, 2) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */ + AM64X_IOPAD(0x0110, PIN_INPUT, 2) /* (AA12) PRG1_PRU1_GPO2.RGMII2_RD2 */ + AM64X_IOPAD(0x0114, PIN_INPUT, 2) /* (Y12) PRG1_PRU1_GPO3.RGMII2_RD3 */ + AM64X_IOPAD(0x0120, PIN_INPUT, 2) /* (U11) PRG1_PRU1_GPO6.RGMII2_RXC */ + AM64X_IOPAD(0x0118, PIN_INPUT, 2) /* (W12) PRG1_PRU1_GPO4.RGMII2_RX_CTL */ + AM64X_IOPAD(0x0134, PIN_OUTPUT, 2) /* (AA10) PRG1_PRU1_GPO11.RGMII2_TD0 */ + AM64X_IOPAD(0x0138, PIN_OUTPUT, 2) /* (V10) PRG1_PRU1_GPO12.RGMII2_TD1 */ + AM64X_IOPAD(0x013c, PIN_OUTPUT, 2) /* (U10) PRG1_PRU1_GPO13.RGMII2_TD2 */ + AM64X_IOPAD(0x0140, PIN_OUTPUT, 2) /* (AA11) PRG1_PRU1_GPO14.RGMII2_TD3 */ + AM64X_IOPAD(0x0148, PIN_OUTPUT, 2) /* (Y10) PRG1_PRU1_GPO16.RGMII2_TXC */ + AM64X_IOPAD(0x0144, PIN_OUTPUT, 2) /* (Y11) PRG1_PRU1_GPO15.RGMII2_TX_CTL */ + >; + }; +}; + +&cpsw3g { + pinctrl-0 = <&rgmii1_pins_default>; +}; + +&cpsw_port2 { + status = "disabled"; +}; + +&mdio_mux_1 { + status = "disabled"; +}; + +&icssg1_eth { + pinctrl-0 = <&icssg1_rgmii1_pins_default>, <&icssg1_rgmii2_pins_default>; +}; + +&icssg1_emac1 { + status = "okay"; + phy-handle = <&icssg1_phy2>; + phy-mode = "rgmii-id"; +}; diff --git a/src/arm64/ti/k3-am642-evm.dts b/src/arm64/ti/k3-am642-evm.dts index 8c5651d..53fe1d0 100644 --- a/src/arm64/ti/k3-am642-evm.dts +++ b/src/arm64/ti/k3-am642-evm.dts @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* - * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; @@ -32,6 +32,7 @@ mmc1 = &sdhci1; ethernet0 = &cpsw_port1; ethernet1 = &cpsw_port2; + ethernet2 = &icssg1_emac0; }; memory@80000000 { @@ -198,7 +199,7 @@ mux-gpios = <&exp1 12 GPIO_ACTIVE_HIGH>; }; - mdio-mux-1 { + mdio_mux_1: mdio-mux-1 { compatible = "mdio-mux-multiplexer"; mux-controls = <&mdio_mux>; mdio-parent-bus = <&cpsw3g_mdio>; @@ -229,6 +230,64 @@ max-bitrate = <5000000>; standby-gpios = <&exp1 9 GPIO_ACTIVE_HIGH>; }; + + icssg1_eth: icssg1-eth { + compatible = "ti,am642-icssg-prueth"; + pinctrl-names = "default"; + pinctrl-0 = <&icssg1_rgmii1_pins_default>; + sram = <&oc_sram>; + ti,prus = <&pru1_0>, <&rtu1_0>, <&tx_pru1_0>, <&pru1_1>, <&rtu1_1>, <&tx_pru1_1>; + firmware-name = "ti-pruss/am64x-sr2-pru0-prueth-fw.elf", + "ti-pruss/am64x-sr2-rtu0-prueth-fw.elf", + "ti-pruss/am64x-sr2-txpru0-prueth-fw.elf", + "ti-pruss/am64x-sr2-pru1-prueth-fw.elf", + "ti-pruss/am64x-sr2-rtu1-prueth-fw.elf", + "ti-pruss/am64x-sr2-txpru1-prueth-fw.elf"; + + ti,pruss-gp-mux-sel = <2>, /* MII mode */ + <2>, + <2>, + <2>, /* MII mode */ + <2>, + <2>; + ti,mii-g-rt = <&icssg1_mii_g_rt>; + ti,mii-rt = <&icssg1_mii_rt>; + ti,iep = <&icssg1_iep0>, <&icssg1_iep1>; + interrupt-parent = <&icssg1_intc>; + interrupts = <24 0 2>, <25 1 3>; + interrupt-names = "tx_ts0", "tx_ts1"; + dmas = <&main_pktdma 0xc200 15>, /* egress slice 0 */ + <&main_pktdma 0xc201 15>, /* egress slice 0 */ + <&main_pktdma 0xc202 15>, /* egress slice 0 */ + <&main_pktdma 0xc203 15>, /* egress slice 0 */ + <&main_pktdma 0xc204 15>, /* egress slice 1 */ + <&main_pktdma 0xc205 15>, /* egress slice 1 */ + <&main_pktdma 0xc206 15>, /* egress slice 1 */ + <&main_pktdma 0xc207 15>, /* egress slice 1 */ + <&main_pktdma 0x4200 15>, /* ingress slice 0 */ + <&main_pktdma 0x4201 15>; /* ingress slice 1 */ + dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3", + "tx1-0", "tx1-1", "tx1-2", "tx1-3", + "rx0", "rx1"; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + icssg1_emac0: port@0 { + reg = <0>; + phy-handle = <&icssg1_phy1>; + phy-mode = "rgmii-id"; + /* Filled in by bootloader */ + local-mac-address = [00 00 00 00 00 00]; + }; + icssg1_emac1: port@1 { + reg = <1>; + /* Filled in by bootloader */ + local-mac-address = [00 00 00 00 00 00]; + status = "disabled"; + }; + }; + }; }; &main_pmx0 { @@ -383,6 +442,30 @@ AM64X_IOPAD(0x0030, PIN_OUTPUT_PULLUP, 7) /* (L18) OSPI0_CSN1.GPIO0_12 */ >; }; + + icssg1_mdio1_pins_default: icssg1-mdio1-default-pins { + pinctrl-single,pins = < + AM64X_IOPAD(0x015c, PIN_OUTPUT, 0) /* (Y6) PRG1_MDIO0_MDC */ + AM64X_IOPAD(0x0158, PIN_INPUT, 0) /* (AA6) PRG1_MDIO0_MDIO */ + >; + }; + + icssg1_rgmii1_pins_default: icssg1-rgmii1-default-pins{ + pinctrl-single,pins = < + AM64X_IOPAD(0x00b8, PIN_INPUT, 2) /* (Y7) PRG1_PRU0_GPO0.PRG1_RGMII1_RD0 */ + AM64X_IOPAD(0x00bc, PIN_INPUT, 2) /* (U8) PRG1_PRU0_GPO1.PRG1_RGMII1_RD1 */ + AM64X_IOPAD(0x00c0, PIN_INPUT, 2) /* (W8) PRG1_PRU0_GPO2.PRG1_RGMII1_RD2 */ + AM64X_IOPAD(0x00c4, PIN_INPUT, 2) /* (V8) PRG1_PRU0_GPO3.PRG1_RGMII1_RD3 */ + AM64X_IOPAD(0x00d0, PIN_INPUT, 2) /* (AA7) PRG1_PRU0_GPO6.PRG1_RGMII1_RXC */ + AM64X_IOPAD(0x00c8, PIN_INPUT, 2) /* (Y8) PRG1_PRU0_GPO4.PRG1_RGMII1_RX_CTL */ + AM64X_IOPAD(0x00e4, PIN_INPUT, 2) /* (AA8) PRG1_PRU0_GPO11.PRG1_RGMII1_TD0 */ + AM64X_IOPAD(0x00e8, PIN_INPUT, 2) /* (U9) PRG1_PRU0_GPO12.PRG1_RGMII1_TD1 */ + AM64X_IOPAD(0x00ec, PIN_INPUT, 2) /* (W9) PRG1_PRU0_GPO13.PRG1_RGMII1_TD2 */ + AM64X_IOPAD(0x00f0, PIN_INPUT, 2) /* (AA9) PRG1_PRU0_GPO14.PRG1_RGMII1_TD3 */ + AM64X_IOPAD(0x00f8, PIN_INPUT, 2) /* (V9) PRG1_PRU0_GPO16.PRG1_RGMII1_TXC */ + AM64X_IOPAD(0x00f4, PIN_INPUT, 2) /* (Y9) PRG1_PRU0_GPO15.PRG1_RGMII1_TX_CTL */ + >; + }; }; &main_uart0 { @@ -494,10 +577,10 @@ /* eMMC */ &sdhci0 { status = "okay"; - bus-width = <8>; non-removable; ti,driver-strength-ohm = <50>; disable-wp; + bootph-all; }; /* SD/MMC */ @@ -506,9 +589,7 @@ status = "okay"; vmmc-supply = <&vdd_mmc1>; pinctrl-names = "default"; - bus-width = <4>; pinctrl-0 = <&main_mmc1_pins_default>; - ti,driver-strength-ohm = <50>; disable-wp; }; @@ -660,25 +741,25 @@ }; &main_r5fss0_core0 { - mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss0_core0>; + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>; memory-region = <&main_r5fss0_core0_dma_memory_region>, <&main_r5fss0_core0_memory_region>; }; &main_r5fss0_core1 { - mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss0_core1>; + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>; memory-region = <&main_r5fss0_core1_dma_memory_region>, <&main_r5fss0_core1_memory_region>; }; &main_r5fss1_core0 { - mboxes = <&mailbox0_cluster4>, <&mbox_main_r5fss1_core0>; + mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>; memory-region = <&main_r5fss1_core0_dma_memory_region>, <&main_r5fss1_core0_memory_region>; }; &main_r5fss1_core1 { - mboxes = <&mailbox0_cluster4>, <&mbox_main_r5fss1_core1>; + mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>; memory-region = <&main_r5fss1_core1_dma_memory_region>, <&main_r5fss1_core1_memory_region>; }; @@ -705,12 +786,6 @@ num-lanes = <1>; }; -&pcie0_ep { - phys = <&serdes0_pcie_link>; - phy-names = "pcie-phy"; - num-lanes = <1>; -}; - &ecap0 { status = "okay"; /* PWM is available on Pin 1 of header J12 */ @@ -731,3 +806,15 @@ pinctrl-0 = <&main_mcan1_pins_default>; phys = <&transceiver2>; }; + +&icssg1_mdio { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&icssg1_mdio1_pins_default>; + + icssg1_phy1: ethernet-phy@f { + reg = <0xf>; + tx-internal-delay-ps = <250>; + rx-internal-delay-ps = <2000>; + }; +}; diff --git a/src/arm64/ti/k3-am642-hummingboard-t-pcie.dtso b/src/arm64/ti/k3-am642-hummingboard-t-pcie.dtso new file mode 100644 index 0000000..bd9a5ca --- /dev/null +++ b/src/arm64/ti/k3-am642-hummingboard-t-pcie.dtso @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2023 Josua Mayer <josua@solid-run.com> + * + * Overlay for SolidRun AM642 HummingBoard-T to enable PCI-E. + */ + +/dts-v1/; +/plugin/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/phy/phy.h> + +#include "k3-serdes.h" + +&pcie0_rc { + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_default_pins>; + reset-gpios = <&main_gpio1 15 GPIO_ACTIVE_HIGH>; + phys = <&serdes0_link>; + phy-names = "pcie-phy"; + num-lanes = <1>; + status = "okay"; +}; + +&serdes0 { + #address-cells = <1>; + #size-cells = <0>; + + serdes0_link: phy@0 { + reg = <0>; + cdns,num-lanes = <1>; + cdns,phy-type = <PHY_TYPE_PCIE>; + #phy-cells = <0>; + resets = <&serdes_wiz0 1>; + }; +}; + +&serdes_ln_ctrl { + idle-states = <AM64_SERDES0_LANE0_PCIE0>; +}; + +&serdes_mux { + idle-state = <1>; +}; diff --git a/src/arm64/ti/k3-am642-hummingboard-t-usb3.dtso b/src/arm64/ti/k3-am642-hummingboard-t-usb3.dtso new file mode 100644 index 0000000..ffcc3bd --- /dev/null +++ b/src/arm64/ti/k3-am642-hummingboard-t-usb3.dtso @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2023 Josua Mayer <josua@solid-run.com> + * + * Overlay for SolidRun AM642 HummingBoard-T to enable USB-3.1. + */ + +/dts-v1/; +/plugin/; + +#include <dt-bindings/phy/phy.h> + +#include "k3-serdes.h" + +&serdes0 { + #address-cells = <1>; + #size-cells = <0>; + + serdes0_link: phy@0 { + reg = <0>; + cdns,num-lanes = <1>; + cdns,phy-type = <PHY_TYPE_USB3>; + #phy-cells = <0>; + resets = <&serdes_wiz0 1>; + }; +}; + +&serdes_ln_ctrl { + idle-states = <AM64_SERDES0_LANE0_USB>; +}; + +&serdes_mux { + idle-state = <0>; +}; + +&usbss0 { + /delete-property/ ti,usb2-only; +}; + +&usb0 { + maximum-speed = "super-speed"; + phys = <&serdes0_link>; + phy-names = "cdns3,usb3-phy"; +}; diff --git a/src/arm64/ti/k3-am642-hummingboard-t.dts b/src/arm64/ti/k3-am642-hummingboard-t.dts new file mode 100644 index 0000000..234d76e --- /dev/null +++ b/src/arm64/ti/k3-am642-hummingboard-t.dts @@ -0,0 +1,292 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2023 Josua Mayer <josua@solid-run.com> + * + * DTS for SolidRun AM642 HummingBoard-T, + * running on Cortex A53. + * + */ + +/dts-v1/; + +#include <dt-bindings/leds/common.h> +#include <dt-bindings/phy/phy.h> + +#include "k3-am642.dtsi" +#include "k3-am642-sr-som.dtsi" + +/ { + model = "SolidRun AM642 HummingBoard-T"; + compatible = "solidrun,am642-hummingboard-t", "solidrun,am642-sr-som", "ti,am642"; + + aliases { + serial5 = &main_uart3; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&leds_default_pins>; + + /* D24 */ + led1: led-1 { + label = "led1"; + gpios = <&main_gpio0 29 GPIO_ACTIVE_HIGH>; + color = <LED_COLOR_ID_GREEN>; + }; + + /* D25 */ + led2: led-2 { + label = "led2"; + gpios = <&main_gpio0 30 GPIO_ACTIVE_HIGH>; + color = <LED_COLOR_ID_GREEN>; + }; + + /* D26 */ + led3: led-3 { + label = "led3"; + gpios = <&main_gpio0 33 GPIO_ACTIVE_HIGH>; + color = <LED_COLOR_ID_GREEN>; + }; + }; + + regulator-m2-3v3 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <®ulator_pcie_3v3_default_pins>; + regulator-name = "m2-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&main_gpio1 17 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + regulator-vpp-1v8 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <®ulator_vpp_1v8_default_pins>; + regulator-name = "vpp-1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&main_gpio1 78 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + serdes_mux: mux-controller { + compatible = "gpio-mux"; + pinctrl-names = "default"; + pinctrl-0 = <&serdes_mux_default_pins>; + #mux-control-cells = <0>; + /* + * Mux has 2 IOs: + * - select: 0 = USB-3 (M2); 1 = PCIE (M1) + * - shutdown: 0 = active; 1 = disabled (high impedance) + */ + mux-gpios = <&main_gpio1 40 GPIO_ACTIVE_HIGH>, <&main_gpio1 41 GPIO_ACTIVE_HIGH>; + /* default disabled */ + idle-state = <2>; + }; +}; + +&main_gpio0 { + m2-reset-hog { + gpio-hog; + gpios = <12 GPIO_ACTIVE_LOW>; + output-low; /* deasserted */ + line-name = "m2-reset"; + }; + + m1-m2-w-disable1-hog { + gpio-hog; + gpios = <32 GPIO_ACTIVE_LOW>; + output-low; /* deasserted */ + line-name = "m1-m2-pcie-w-disable1"; + }; + + m1-m2-w-disable2-hog { + gpio-hog; + gpios = <34 GPIO_ACTIVE_LOW>; + output-low; /* deasserted */ + line-name = "m1-m2-pcie-w-disable2"; + }; +}; + +&main_gpio1 { + m1-pcie-clkreq0-hog { + gpio-hog; + gpios = <11 GPIO_ACTIVE_LOW>; + input; + line-name = "m1-pcie-clkreq0"; + }; + + m2-pcie-clkreq-hog { + gpio-hog; + gpios = <35 GPIO_ACTIVE_LOW>; + input; + line-name = "m2-pcie-clkreq"; + }; +}; + +&main_i2c0 { + pinctrl-0 = <&main_i2c0_default_pins>, <&main_i2c0_int_default_pins>; + + humidity-sensor@41 { + compatible = "ti,hdc2010"; + reg = <0x41>; + interrupt-parent = <&main_gpio0>; + interrupts = <37 IRQ_TYPE_EDGE_FALLING>; + }; + + light-sensor@44 { + compatible = "ti,opt3001"; + reg = <0x44>; + interrupt-parent = <&main_gpio0>; + interrupts = <37 IRQ_TYPE_EDGE_FALLING>; + }; + + /* charger@6a */ +}; + +&main_i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c1_default_pins>; + status = "okay"; + + rtc@69 { + compatible = "abracon,abx80x"; + reg = <0x69>; + pinctrl-names = "default"; + pinctrl-0 = <&rtc_int_default_pins>; + abracon,tc-diode = "schottky"; + abracon,tc-resistor = <3>; + interrupt-parent = <&main_gpio0>; + interrupts = <44 IRQ_TYPE_EDGE_FALLING>; + }; +}; + +&main_mcan0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_mcan0_default_pins>; + status = "okay"; + + can-transceiver { + max-bitrate = <8000000>; + }; +}; + +&main_mcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&main_mcan1_default_pins>; + status = "okay"; + + can-transceiver { + max-bitrate = <8000000>; + }; +}; + +&main_pmx0 { + leds_default_pins: leds-default-pins { + pinctrl-single,pins = < + AM64X_IOPAD(0x0074, PIN_OUTPUT, 7) /* GPMC0_AD14.GPIO0_29 */ + AM64X_IOPAD(0x0078, PIN_OUTPUT, 7) /* GPMC0_AD15.GPIO0_30 */ + AM64X_IOPAD(0x0088, PIN_OUTPUT, 7) /* GPMC0_OEn_REn.GPIO0_33 */ + >; + }; + + main_i2c0_int_default_pins: main-i2c0-int-default-pins { + pinctrl-single,pins = < + /* external pull-up on Carrier */ + AM64X_IOPAD(0x0098, PIN_INPUT, 7) /* GPMC0_WAIT0.GPIO0_37 */ + >; + }; + + main_i2c1_default_pins: main-i2c1-default-pins { + pinctrl-single,pins = < + /* external pull-up on SoM */ + AM64X_IOPAD(0x0268, PIN_INPUT, 0) /* I2C1_SCL.I2C1_SCL */ + AM64X_IOPAD(0x026c, PIN_INPUT, 0) /* I2C1_SDA.I2C1_SDA */ + >; + }; + + main_mcan0_default_pins: main-mcan0-default-pins { + pinctrl-single,pins = < + AM64X_IOPAD(0x0254, PIN_INPUT, 0) /* MCAN0_RX.MCAN0_RX */ + AM64X_IOPAD(0x0250, PIN_OUTPUT, 0) /* MCAN0_TX.MCAN0_TX */ + >; + }; + + main_mcan1_default_pins: main-mcan1-default-pins { + pinctrl-single,pins = < + AM64X_IOPAD(0x025c, PIN_INPUT, 0) /* MCAN1_RX.MCAN1_RX */ + AM64X_IOPAD(0x0258, PIN_OUTPUT, 0) /* MCAN1_TX.MCAN1_TX */ + >; + }; + + main_uart3_default_pins: main-uart3-default-pins { + pinctrl-single,pins = < + AM64X_IOPAD(0x016c, PIN_INPUT, 10) /* PRG0_PRU0_GPO3.UART3_CTSn */ + AM64X_IOPAD(0x0170, PIN_OUTPUT, 10) /* PRG0_PRU0_GPO4.UART3_TXD */ + AM64X_IOPAD(0x0174, PIN_OUTPUT, 10) /* PRG0_PRU0_GPO5.UART3_RTSn */ + AM64X_IOPAD(0x01ac, PIN_INPUT, 10) /* PRG0_PRU0_GPO19.UART3_RXD */ + >; + }; + + pcie0_default_pins: pcie0-default-pins { + pinctrl-single,pins = < + /* connector M2 RESET */ + AM64X_IOPAD(0x0030, PIN_OUTPUT, 7) /* OSPI0_CSn1.GPIO0_12 */ + /* connectors M1 & M2 W_DISABLE1 */ + AM64X_IOPAD(0x0084, PIN_OUTPUT, 7) /* GPMC0_ADVN_ALE.GPIO0_32 */ + /* connectors M1 & M2 W_DISABLE2 */ + AM64X_IOPAD(0x008c, PIN_OUTPUT, 7) /* GPMC0_WEN.GPIO0_34 */ + /* connectors M1 & M2 PERST0 (PCI Reset) */ + AM64X_IOPAD(0x019c, PIN_OUTPUT, 7) /* PRG0_PRU0_GPO15.GPIO1_15 */ + /* connector M1 CLKREQ0 */ + AM64X_IOPAD(0x018c, PIN_INPUT, 7) /* PRG0_PRU0_GPO11.GPIO1_11 */ + /* connector M2 CLKREQ0 */ + AM64X_IOPAD(0x01ec, PIN_INPUT, 7) /* PRG0_PRU1_GPO15.GPIO1_35 */ + >; + }; + + regulator_pcie_3v3_default_pins: regulator-pcie-3v3-default-pins { + pinctrl-single,pins = < + AM64X_IOPAD(0x01a4, PIN_OUTPUT, 7) /* PRG0_PRU0_GPO17.GPIO1_17 */ + >; + }; + + regulator_vpp_1v8_default_pins: regulator-vpp-1v8-default-pins { + pinctrl-single,pins = < + AM64X_IOPAD(0x029c, PIN_OUTPUT, 7) /* MMC1_SDWP.GPIO1_78 */ + >; + }; + + rtc_int_default_pins: rtc-int-default-pins { + pinctrl-single,pins = < + /* external pull-up on Carrier */ + AM64X_IOPAD(0x00b4, PIN_INPUT, 7) /* GPMC0_CSn3.GPIO0_44 */ + >; + }; + + serdes_mux_default_pins: serdes-mux-default-pins { + pinctrl-single,pins = < + /* SEL, 10k pull-down on carrier, 2.2k pullup on SoM */ + AM64X_IOPAD(0x0200, PIN_OUTPUT, 7) /* PRG0_MDIO0_MDIO.GPIO1_40 */ + /* EN */ + AM64X_IOPAD(0x0204, PIN_OUTPUT, 7) /* PRG0_MDIO0_MDC.GPIO1_41 */ + >; + }; +}; + +&main_uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&main_uart3_default_pins>; + uart-has-rtscts; + rs485-rts-active-low; + linux,rs485-enabled-at-boot-time; + status = "okay"; +}; + +&usb0 { + dr_mode = "host"; +}; diff --git a/src/arm64/ti/k3-am642-phyboard-electra-rdk.dts b/src/arm64/ti/k3-am642-phyboard-electra-rdk.dts index 53b64e5..8237b8c 100644 --- a/src/arm64/ti/k3-am642-phyboard-electra-rdk.dts +++ b/src/arm64/ti/k3-am642-phyboard-electra-rdk.dts @@ -1,9 +1,9 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* - * Copyright (C) 2021 PHYTEC America, LLC - https://www.phytec.com + * Copyright (C) 2021-2024 PHYTEC America, LLC - https://www.phytec.com * Author: Matt McKee <mmckee@phytec.com> * - * Copyright (C) 2022 PHYTEC Messtechnik GmbH + * Copyright (C) 2022-2024 PHYTEC Messtechnik GmbH * Author: Wadim Egorov <w.egorov@phytec.de> * * Product homepage: @@ -159,6 +159,15 @@ >; }; + main_spi0_pins_default: main-spi0-default-pins { + pinctrl-single,pins = < + AM64X_IOPAD(0x020c, PIN_OUTPUT, 7) /* (C13) SPI0_CS1.GPIO1_43 */ + AM64X_IOPAD(0x0210, PIN_INPUT, 0) /* (D13) SPI0_CLK */ + AM64X_IOPAD(0x0214, PIN_OUTPUT, 0) /* (A13) SPI0_D0 */ + AM64X_IOPAD(0x0218, PIN_INPUT, 0) /* (A14) SPI0_D1 */ + >; + }; + main_uart0_pins_default: main-uart0-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x0230, PIN_INPUT, 0) /* (D15) UART0_RXD */ @@ -248,6 +257,20 @@ phys = <&can_tc2>; }; +&main_spi0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_spi0_pins_default>; + cs-gpios = <0>, <&main_gpio1 43 GPIO_ACTIVE_LOW>; + ti,pindir-d0-out-d1-in; + + tpm@1 { + compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; + reg = <1>; + spi-max-frequency = <10000000>; + }; +}; + &main_uart0 { status = "okay"; pinctrl-names = "default"; @@ -269,7 +292,6 @@ pinctrl-names = "default"; pinctrl-0 = <&main_mmc1_pins_default>; bus-width = <4>; - ti,driver-strength-ohm = <50>; disable-wp; no-1-8-v; }; diff --git a/src/arm64/ti/k3-am642-sk.dts b/src/arm64/ti/k3-am642-sk.dts index 1dddd6f..67cd41b 100644 --- a/src/arm64/ti/k3-am642-sk.dts +++ b/src/arm64/ti/k3-am642-sk.dts @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* - * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; @@ -469,9 +469,7 @@ status = "okay"; vmmc-supply = <&vdd_mmc1>; pinctrl-names = "default"; - bus-width = <4>; pinctrl-0 = <&main_mmc1_pins_default>; - ti,driver-strength-ohm = <50>; disable-wp; }; @@ -646,25 +644,25 @@ }; &main_r5fss0_core0 { - mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss0_core0>; + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>; memory-region = <&main_r5fss0_core0_dma_memory_region>, <&main_r5fss0_core0_memory_region>; }; &main_r5fss0_core1 { - mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss0_core1>; + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>; memory-region = <&main_r5fss0_core1_dma_memory_region>, <&main_r5fss0_core1_memory_region>; }; &main_r5fss1_core0 { - mboxes = <&mailbox0_cluster4>, <&mbox_main_r5fss1_core0>; + mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>; memory-region = <&main_r5fss1_core0_dma_memory_region>, <&main_r5fss1_core0_memory_region>; }; &main_r5fss1_core1 { - mboxes = <&mailbox0_cluster4>, <&mbox_main_r5fss1_core1>; + mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>; memory-region = <&main_r5fss1_core1_dma_memory_region>, <&main_r5fss1_core1_memory_region>; }; diff --git a/src/arm64/ti/k3-am642-sr-som.dtsi b/src/arm64/ti/k3-am642-sr-som.dtsi new file mode 100644 index 0000000..c19d0b8 --- /dev/null +++ b/src/arm64/ti/k3-am642-sr-som.dtsi @@ -0,0 +1,594 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2023 Josua Mayer <josua@solid-run.com> + * + */ + +#include <dt-bindings/net/ti-dp83869.h> + +/ { + model = "SolidRun AM642 SoM"; + compatible = "solidrun,am642-sr-som", "ti,am642"; + + aliases { + ethernet0 = &cpsw_port1; + ethernet1 = &icssg1_emac0; + ethernet2 = &icssg1_emac1; + mmc0 = &sdhci0; + mmc1 = &sdhci1; + serial2 = &main_uart0; + }; + + chosen { + /* SoC default UART console */ + stdout-path = "serial2:115200n8"; + }; + + /* PRU Ethernet Controller */ + ethernet { + compatible = "ti,am642-icssg-prueth"; + pinctrl-names = "default"; + pinctrl-0 = <&pru_rgmii1_default_pins>, <&pru_rgmii2_default_pins>; + + sram = <&oc_sram>; + ti,prus = <&pru1_0>, <&rtu1_0>, <&tx_pru1_0>, <&pru1_1>, <&rtu1_1>, <&tx_pru1_1>; + firmware-name = "ti-pruss/am65x-sr2-pru0-prueth-fw.elf", + "ti-pruss/am65x-sr2-rtu0-prueth-fw.elf", + "ti-pruss/am65x-sr2-txpru0-prueth-fw.elf", + "ti-pruss/am65x-sr2-pru1-prueth-fw.elf", + "ti-pruss/am65x-sr2-rtu1-prueth-fw.elf", + "ti-pruss/am65x-sr2-txpru1-prueth-fw.elf"; + + /* configure internal pinmux for mii mode */ + ti,pruss-gp-mux-sel = <2>, <2>, <2>, <2>, <2>, <2>; + + ti,mii-g-rt = <&icssg1_mii_g_rt>; + ti,mii-rt = <&icssg1_mii_rt>; + ti,iep = <&icssg1_iep0>, <&icssg1_iep1>; + + /* + * Configure icssg interrupt controller to map pru-internal + * interrupts 8/9 via channels 0/1 to host interrupts 0/1. + * + * For details see interrupt controller documentation: + * Documentation/devicetree/bindings/interrupt-controller/ti,pruss-intc.yaml + */ + interrupt-parent = <&icssg1_intc>; + interrupts = <24 0 2>, <25 1 3>; + interrupt-names = "tx_ts0", "tx_ts1"; + + dmas = <&main_pktdma 0xc200 15>, /* egress slice 0 */ + <&main_pktdma 0xc201 15>, /* egress slice 0 */ + <&main_pktdma 0xc202 15>, /* egress slice 0 */ + <&main_pktdma 0xc203 15>, /* egress slice 0 */ + <&main_pktdma 0xc204 15>, /* egress slice 1 */ + <&main_pktdma 0xc205 15>, /* egress slice 1 */ + <&main_pktdma 0xc206 15>, /* egress slice 1 */ + <&main_pktdma 0xc207 15>, /* egress slice 1 */ + <&main_pktdma 0x4200 15>, /* ingress slice 0 */ + <&main_pktdma 0x4201 15>; /* ingress slice 1 */ + dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3", + "tx1-0", "tx1-1", "tx1-2", "tx1-3", + "rx0", "rx1"; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + icssg1_emac0: port@0 { + reg = <0>; + ti,syscon-rgmii-delay = <&main_conf 0x4110>; + /* Filled in by bootloader */ + local-mac-address = [00 00 00 00 00 00]; + phy-handle = <ðernet_phy2>; + phy-mode = "rgmii-id"; + }; + + icssg1_emac1: port@1 { + reg = <1>; + ti,syscon-rgmii-delay = <&main_conf 0x4114>; + /* Filled in by bootloader */ + local-mac-address = [00 00 00 00 00 00]; + phy-handle = <ðernet_phy1>; + phy-mode = "rgmii-id"; + }; + }; + }; + + /* DDR16SS0: + * - Bank 1 @ 0x080000000-0x0FFFFFFFF: max. 2GB in 32-bit address space + * - Bank 2 @ 0x880000000-0x9FFFFFFFF: max. 6GB in 64-bit address space + */ + memory@80000000 { + reg = <0x00000000 0x80000000 0x00000000 0x80000000>, + <0x00000008 0x80000000 0x00000001 0x80000000>; + device_type = "memory"; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + secure_ddr: optee@9e800000 { + reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */ + no-map; + }; + + main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa0000000 0x00 0x100000>; + no-map; + }; + + main_r5fss0_core0_memory_region: r5f-memory@a0100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa0100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa1000000 0x00 0x100000>; + no-map; + }; + + main_r5fss0_core1_memory_region: r5f-memory@a1100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa1100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa2000000 0x00 0x100000>; + no-map; + }; + + main_r5fss1_core0_memory_region: r5f-memory@a2100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa2100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa3000000 0x00 0x100000>; + no-map; + }; + + main_r5fss1_core1_memory_region: r5f-memory@a3100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa3100000 0x00 0xf00000>; + no-map; + }; + }; + + vdd_mmc0: regulator-vdd-mmc0 { + compatible = "regulator-fixed"; + regulator-name = "vdd-mmc0"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; +}; + +&cpsw3g { + pinctrl-names = "default"; + pinctrl-0 = <&rgmii1_default_pins>; +}; + +&cpsw3g_mdio { + pinctrl-names = "default"; + pinctrl-0 = <&mdio0_default_pins>; + status = "okay"; + + ethernet_phy0: ethernet-phy@0 { + compatible = "ethernet-phy-id2000.a0f1"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <ðernet_phy0_default_pins>; + ti,clk-output-sel = <DP83869_CLK_O_SEL_REF_CLK>; + ti,op-mode = <DP83869_RGMII_COPPER_ETHERNET>; + /* + * Disable interrupts because ISR never clears 0x0040 + * + * interrupt-parent = <&main_gpio1>; + * interrupts = <70 IRQ_TYPE_LEVEL_LOW>; + */ + /* + * Disable HW Reset because clock signal is daisy-chained + * + * reset-gpios = <&main_gpio0 84 GPIO_ACTIVE_LOW>; + * reset-assert-us = <1>; + * reset-deassert-us = <30>; + */ + }; +}; + +&cpsw_port1 { + phy-mode = "rgmii-id"; + phy-handle = <ðernet_phy0>; +}; + +&cpsw_port2 { + status = "disabled"; +}; + +&icssg1_mdio { + pinctrl-names = "default"; + pinctrl-0 = <&pru1_mdio0_default_pins>; + status = "okay"; + + ethernet_phy1: ethernet-phy@3 { + compatible = "ethernet-phy-id2000.a0f1"; + reg = <3>; + pinctrl-names = "default"; + pinctrl-0 = <ðernet_phy1_default_pins>; + ti,clk-output-sel = <DP83869_CLK_O_SEL_REF_CLK>; + ti,op-mode = <DP83869_RGMII_COPPER_ETHERNET>; + /* + * Disable interrupts because ISR never clears 0x0040 + * + * interrupt-parent = <&main_gpio1>; + * interrupts = <70 IRQ_TYPE_LEVEL_LOW>; + */ + /* + * Disable HW Reset because clock signal is daisy-chained + * + * reset-gpios = <&main_gpio0 20 GPIO_ACTIVE_LOW>; + * reset-assert-us = <1>; + * reset-deassert-us = <30>; + */ + }; + + ethernet_phy2: ethernet-phy@f { + compatible = "ethernet-phy-id2000.a0f1"; + reg = <0xf>; + pinctrl-names = "default"; + pinctrl-0 = <ðernet_phy2_default_pins>; + ti,op-mode = <DP83869_RGMII_COPPER_ETHERNET>; + /* + * Disable interrupts because ISR never clears 0x0040 + * + * interrupt-parent = <&main_gpio1>; + * interrupts = <70 IRQ_TYPE_LEVEL_LOW>; + */ + /* + * Disable HW Reset because clock signal is daisy-chained + * + * reset-gpios = <&main_gpio0 52 GPIO_ACTIVE_LOW>; + * reset-assert-us = <1>; + * reset-deassert-us = <30>; + */ + }; +}; + +&mailbox0_cluster2 { + status = "okay"; + + mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { + ti,mbox-rx = <0 0 2>; + ti,mbox-tx = <1 0 2>; + }; + + mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { + ti,mbox-rx = <2 0 2>; + ti,mbox-tx = <3 0 2>; + }; +}; + +&mailbox0_cluster4 { + status = "okay"; + + mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { + ti,mbox-rx = <0 0 2>; + ti,mbox-tx = <1 0 2>; + }; + + mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { + ti,mbox-rx = <2 0 2>; + ti,mbox-tx = <3 0 2>; + }; +}; + +&main_i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c0_default_pins>; + status = "okay"; + + som_eeprom: eeprom@50 { + compatible = "atmel,24c01"; + reg = <0x50>; + pagesize = <8>; + }; +}; + +&main_pmx0 { + /* hog global functions */ + pinctrl-names = "default"; + pinctrl-0 = <ðernet_phy_default_pins>; + + ethernet_phy_default_pins: ethernet-phy-default-pins { + pinctrl-single,pins = < + /* interrupt / power-down, external pull-up on SoM */ + AM64X_IOPAD(0x0278, PIN_INPUT, 7) /* EXTINTn.GPIO1_70 */ + >; + }; + + ethernet_phy0_default_pins: ethernet-phy0-default-pins { + pinctrl-single,pins = < + /* reset */ + AM64X_IOPAD(0x0154, PIN_OUTPUT, 7) /* PRG1_PRU1_GPO19.GPIO0_84 */ + /* reference clock */ + AM64X_IOPAD(0x0274, PIN_OUTPUT, 5) /* EXT_REFCLK1.CLKOUT0 */ + >; + }; + + ethernet_phy1_default_pins: ethernet-phy1-default-pins { + pinctrl-single,pins = < + /* reset */ + AM64X_IOPAD(0x0150, PIN_OUTPUT, 7) /* PRG1_PRU1_GPO18.GPIO0_20 */ + /* led0, external pull-down on SoM */ + AM64X_IOPAD(0x0128, PIN_INPUT, 7) /* PRG1_PRU1_GPO8.GPIO0_73 */ + /* led1/rxer */ + AM64X_IOPAD(0x011c, PIN_INPUT, 7) /* PRG1_PRU1_GPO5.GPIO0_70 */ + >; + }; + + ethernet_phy2_default_pins: ethernet-phy2-default-pins { + pinctrl-single,pins = < + /* reset */ + AM64X_IOPAD(0x00d4, PIN_OUTPUT, 7) /* PRG1_PRU0_GPO7.GPIO0_52 */ + /* led0, external pull-down on SoM */ + AM64X_IOPAD(0x00d8, PIN_INPUT, 7) /* PRG1_PRU0_GPO8.GPIO0_53 */ + /* led1/rxer */ + AM64X_IOPAD(0x00cc, PIN_INPUT, 7) /* PRG1_PRU0_GPO5.GPIO0_50 */ + >; + }; + + main_i2c0_default_pins: main-i2c0-default-pins { + pinctrl-single,pins = < + /* external pull-up on SoM */ + AM64X_IOPAD(0x0260, PIN_INPUT, 0) /* I2C0_SCL.I2C0_SCL */ + AM64X_IOPAD(0x0264, PIN_INPUT, 0) /* I2C0_SDA.I2C0_SDA */ + >; + }; + + /* + * main_mmc0_default_pins: main-mmc0-default-pins + * + * MMC0_CMD: no padconfig + * MMC0_CLK: no padconfig, external pull-up on SoM + * MMC0_DAT0: no padconfig + * MMC0_DAT1: no padconfig + * MMC0_DAT2: no padconfig + * MMC0_DAT3: no padconfig + * MMC0_DAT4: no padconfig + * MMC0_DAT5: no padconfig + * MMC0_DAT6: no padconfig + * MMC0_DAT7: no padconfig + * MMC0_DS: no padconfig, external pull-down on SoM + */ + + main_mmc1_default_pins: main-mmc1-default-pins { + pinctrl-single,pins = < + AM64X_IOPAD(0x0294, PIN_INPUT_PULLUP, 0) /* (J19) MMC1_CMD */ + AM64X_IOPAD(0x028c, PIN_INPUT, 0) /* MMC1_CLK.MMC1_CLK */ + AM64X_IOPAD(0x0288, PIN_INPUT_PULLUP, 0) /* MMC1_DAT0.MMC1_DAT0 */ + AM64X_IOPAD(0x0284, PIN_INPUT_PULLUP, 0) /* MMC1_DAT1.MMC1_DAT1 */ + AM64X_IOPAD(0x0280, PIN_INPUT_PULLUP, 0) /* MMC1_DAT2.MMC1_DAT2 */ + AM64X_IOPAD(0x027c, PIN_INPUT_PULLUP, 0) /* MMC1_DAT3.MMC1_DAT3 */ + /* external pull-down on SoM & Carrier */ + AM64X_IOPAD(0x0298, PIN_INPUT_PULLUP, 0) /* MMC1_SDCD.MMC1_SDCD */ + AM64X_IOPAD(0x0290, PIN_INPUT, 0) /* MMC1_CLKLB: clock loopback */ + >; + }; + + main_uart0_default_pins: main-uart0-default-pins { + pinctrl-single,pins = < + AM64X_IOPAD(0x0230, PIN_INPUT, 0) /* UART0_RXD.UART0_RXD */ + AM64X_IOPAD(0x0234, PIN_OUTPUT, 0) /* UART0_TXD.UART0_TXD */ + >; + }; + + mdio0_default_pins: mdio0-default-pins { + pinctrl-single,pins = < + AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* PRG0_PRU1_GPO19.MDIO0_MDC */ + AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* PRG0_PRU1_GPO18.MDIO0_MDIO */ + >; + }; + + ospi0_default_pins: ospi0-default-pins { + pinctrl-single,pins = < + /* external pull-down on SoM */ + AM64X_IOPAD(0x0000, PIN_OUTPUT, 0) /* OSPI0_CLK.OSPI0_CLK */ + AM64X_IOPAD(0x0008, PIN_OUTPUT, 0) /* OSPI0_DQS.OSPI0_DQS */ + /* external pull-up on SoM */ + AM64X_IOPAD(0x002c, PIN_OUTPUT, 0) /* OSPI0_CSn0.OSPI0_CSn0 */ + AM64X_IOPAD(0x000c, PIN_INPUT, 0) /* OSPI0_D0.OSPI0_D0 */ + AM64X_IOPAD(0x0010, PIN_INPUT, 0) /* OSPI0_D1.OSPI0_D1 */ + AM64X_IOPAD(0x0014, PIN_INPUT, 0) /* OSPI0_D2.OSPI0_D2 */ + AM64X_IOPAD(0x0018, PIN_INPUT, 0) /* OSPI0_D3.OSPI0_D3 */ + AM64X_IOPAD(0x001c, PIN_INPUT, 0) /* OSPI0_D4.OSPI0_D4 */ + AM64X_IOPAD(0x0020, PIN_INPUT, 0) /* OSPI0_D5.OSPI0_D5 */ + AM64X_IOPAD(0x0024, PIN_INPUT, 0) /* OSPI0_D6.OSPI0_D6 */ + AM64X_IOPAD(0x0028, PIN_INPUT, 0) /* OSPI0_D7.OSPI0_D7 */ + >; + }; + + ospi0_flash0_default_pins: ospi0-flash0-default-pins { + pinctrl-single,pins = < + AM64X_IOPAD(0x0034, PIN_OUTPUT, 7) /* OSPI0_CSn2.GPIO0_13 */ + AM64X_IOPAD(0x0038, PIN_INPUT, 7) /* OSPI0_CSn3.GPIO0_14 */ + >; + }; + + pru1_mdio0_default_pins: pru1-mdio0-default-pins { + pinctrl-single,pins = < + AM64X_IOPAD(0x015c, PIN_OUTPUT, 0) /* PRG1_MDIO0_MDC.PRG1_MDIO0_MDC */ + AM64X_IOPAD(0x0158, PIN_INPUT, 0) /* PRG1_MDIO0_MDIO.PRG1_MDIO0_MDIO */ + >; + }; + + pru_rgmii1_default_pins: pru-rgmii1-default-pins { + pinctrl-single,pins = < + AM64X_IOPAD(0x00b8, PIN_INPUT, 2) /* (Y7) PRG1_PRU0_GPO0.PRG1_RGMII1_RD0 */ + AM64X_IOPAD(0x00bc, PIN_INPUT, 2) /* (U8) PRG1_PRU0_GPO1.PRG1_RGMII1_RD1 */ + AM64X_IOPAD(0x00c0, PIN_INPUT, 2) /* (W8) PRG1_PRU0_GPO2.PRG1_RGMII1_RD2 */ + AM64X_IOPAD(0x00c4, PIN_INPUT, 2) /* (V8) PRG1_PRU0_GPO3.PRG1_RGMII1_RD3 */ + AM64X_IOPAD(0x00d0, PIN_INPUT, 2) /* (AA7) PRG1_PRU0_GPO6.PRG1_RGMII1_RXC */ + AM64X_IOPAD(0x00c8, PIN_INPUT, 2) /* (Y8) PRG1_PRU0_GPO4.PRG1_RGMII1_RX_CTL */ + AM64X_IOPAD(0x00e4, PIN_OUTPUT, 2) /* (AA8) PRG1_PRU0_GPO11.PRG1_RGMII1_TD0 */ + AM64X_IOPAD(0x00e8, PIN_OUTPUT, 2) /* (U9) PRG1_PRU0_GPO12.PRG1_RGMII1_TD1 */ + AM64X_IOPAD(0x00ec, PIN_OUTPUT, 2) /* (W9) PRG1_PRU0_GPO13.PRG1_RGMII1_TD2 */ + AM64X_IOPAD(0x00f0, PIN_OUTPUT, 2) /* (AA9) PRG1_PRU0_GPO14.PRG1_RGMII1_TD3 */ + AM64X_IOPAD(0x00f8, PIN_INPUT, 2) /* (V9) PRG1_PRU0_GPO16.PRG1_RGMII1_TXC */ + AM64X_IOPAD(0x00f4, PIN_OUTPUT, 2) /* (Y9) PRG1_PRU0_GPO15.PRG1_RGMII1_TX_CTL */ + >; + }; + + pru_rgmii2_default_pins: pru-rgmii2-default-pins { + pinctrl-single,pins = < + AM64X_IOPAD(0x0108, PIN_INPUT, 2) /* PRG1_PRU1_GPO0.RGMII2_RD0 */ + AM64X_IOPAD(0x010c, PIN_INPUT, 2) /* PRG1_PRU1_GPO1.RGMII2_RD1 */ + AM64X_IOPAD(0x0110, PIN_INPUT, 2) /* PRG1_PRU1_GPO2.RGMII2_RD2 */ + AM64X_IOPAD(0x0114, PIN_INPUT, 2) /* PRG1_PRU1_GPO3.RGMII2_RD3 */ + AM64X_IOPAD(0x0120, PIN_INPUT, 2) /* PRG1_PRU1_GPO6.RGMII2_RXC */ + AM64X_IOPAD(0x0118, PIN_INPUT, 2) /* PRG1_PRU1_GPO4.RGMII2_RX_CTL */ + AM64X_IOPAD(0x0134, PIN_OUTPUT, 2) /* PRG1_PRU1_GPO11.RGMII2_TD0 */ + AM64X_IOPAD(0x0138, PIN_OUTPUT, 2) /* PRG1_PRU1_GPO12.RGMII2_TD1 */ + AM64X_IOPAD(0x013c, PIN_OUTPUT, 2) /* PRG1_PRU1_GPO13.RGMII2_TD2 */ + AM64X_IOPAD(0x0140, PIN_OUTPUT, 2) /* PRG1_PRU1_GPO14.RGMII2_TD3 */ + AM64X_IOPAD(0x0148, PIN_INPUT, 2) /* PRG1_PRU1_GPO16.RGMII2_TXC */ + AM64X_IOPAD(0x0144, PIN_OUTPUT, 2) /* PRG1_PRU1_GPO15.RGMII2_TX_CTL */ + >; + }; + + rgmii1_default_pins: rgmii1-default-pins { + pinctrl-single,pins = < + AM64X_IOPAD(0x01cc, PIN_INPUT, 4) /* PRG0_PRU1_GPO7.RGMII1_RD0 */ + AM64X_IOPAD(0x01d4, PIN_INPUT, 4) /* PRG0_PRU1_GPO9.RGMII1_RD1 */ + AM64X_IOPAD(0x01d8, PIN_INPUT, 4) /* PRG0_PRU1_GPO10.RGMII1_RD2 */ + AM64X_IOPAD(0x01f4, PIN_INPUT, 4) /* PRG0_PRU1_GPO17.RGMII1_RD3 */ + AM64X_IOPAD(0x0188, PIN_INPUT, 4) /* PRG0_PRU0_GPO10.RGMII1_RXC */ + AM64X_IOPAD(0x0184, PIN_INPUT, 4) /* PRG0_PRU0_GPO9.RGMII1_RX_CTL */ + AM64X_IOPAD(0x0124, PIN_OUTPUT, 4) /* PRG1_PRU1_GPO7.RGMII1_TD0 */ + AM64X_IOPAD(0x012c, PIN_OUTPUT, 4) /* PRG1_PRU1_GPO9.RGMII1_TD1 */ + AM64X_IOPAD(0x0130, PIN_OUTPUT, 4) /* PRG1_PRU1_GPO10.RGMII1_TD2 */ + AM64X_IOPAD(0x014c, PIN_OUTPUT, 4) /* PRG1_PRU1_GPO17.RGMII1_TD3 */ + AM64X_IOPAD(0x00e0, PIN_INPUT, 4) /* PRG1_PRU0_GPO10.RGMII1_TXC */ + AM64X_IOPAD(0x00dc, PIN_OUTPUT, 4) /* PRG1_PRU0_GPO9.RGMII1_TX_CTL */ + >; + }; + + usb0_default_pins: usb0-default-pins { + pinctrl-single,pins = < + AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* USB0_DRVVBUS.USB0_DRVVBUS */ + >; + }; +}; + +&main_r5fss0_core0 { + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>; + memory-region = <&main_r5fss0_core0_dma_memory_region>, + <&main_r5fss0_core0_memory_region>; +}; + +&main_r5fss0_core1 { + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>; + memory-region = <&main_r5fss0_core1_dma_memory_region>, + <&main_r5fss0_core1_memory_region>; +}; + +&main_r5fss1_core0 { + mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>; + memory-region = <&main_r5fss1_core0_dma_memory_region>, + <&main_r5fss1_core0_memory_region>; +}; + +&main_r5fss1_core1 { + mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>; + memory-region = <&main_r5fss1_core1_dma_memory_region>, + <&main_r5fss1_core1_memory_region>; +}; + +/* SoC default UART console */ +&main_uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_uart0_default_pins>; + status = "okay"; +}; + +&ospi0 { + pinctrl-names = "default"; + pinctrl-0 = <&ospi0_default_pins>; + num-cs = <1>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&ospi0_flash0_default_pins>; + spi-tx-bus-width = <8>; + spi-rx-bus-width = <8>; + spi-max-frequency = <200000000>; + cdns,tshsl-ns = <50>; + cdns,tsd2d-ns = <50>; + cdns,tchsh-ns = <4>; + cdns,tslch-ns = <4>; + cdns,read-delay = <0>; + interrupt-parent = <&main_gpio0>; + interrupts = <14 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&main_gpio0 13 GPIO_ACTIVE_LOW>; + }; +}; + +&sdhci0 { + /* mmc0 pins have no padconfig */ + bus-width = <8>; + ti,driver-strength-ohm = <50>; + disable-wp; + non-removable; + cap-mmc-hw-reset; + no-sd; + /* + * MMC controller supports switching between 1.8V and 3.3V signalling. + * However MMC0 (unlike MMC1) does not integrate an LDO. + * Explicitly link a regulator node for indicating to the driver which + * voltages are actually usable. + */ + vqmmc-supply = <&vdd_mmc0>; + status = "okay"; +}; + +/* + * microSD is on carrier - however since SoC can boot from it, + * configure it just in case. + */ +&sdhci1 { + pinctrl-names = "default"; + pinctrl-0 = <&main_mmc1_default_pins>; + bus-width = <4>; + ti,driver-strength-ohm = <50>; + disable-wp; + status = "okay"; +}; + +/* + * USB settings are a carrier choice - however since SoC can boot from it, + * configure as USB-2.0 OTG here, keeping USB-3 serdes disabled. + */ +&usb0 { + pinctrl-names = "default"; + pinctrl-0 = <&usb0_default_pins>; + dr_mode = "otg"; + maximum-speed = "high-speed"; +}; + +&usbss0 { + ti,vbus-divider; + ti,usb2-only; +}; diff --git a/src/arm64/ti/k3-am642-tqma64xxl-mbax4xxl.dts b/src/arm64/ti/k3-am642-tqma64xxl-mbax4xxl.dts index 55102d3..1f4dc5a 100644 --- a/src/arm64/ti/k3-am642-tqma64xxl-mbax4xxl.dts +++ b/src/arm64/ti/k3-am642-tqma64xxl-mbax4xxl.dts @@ -422,7 +422,6 @@ cd-gpios = <&main_gpio1 77 GPIO_ACTIVE_LOW>; disable-wp; no-mmc; - ti,driver-strength-ohm = <50>; ti,fails-without-test-cd; /* Enabled by overlay */ }; diff --git a/src/arm64/ti/k3-am642.dtsi b/src/arm64/ti/k3-am642.dtsi index 7a6eede..8589ee5 100644 --- a/src/arm64/ti/k3-am642.dtsi +++ b/src/arm64/ti/k3-am642.dtsi @@ -1,8 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree Source for AM642 SoC family in Dual core configuration * - * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/src/arm64/ti/k3-am65-iot2050-arduino-connector.dtsi b/src/arm64/ti/k3-am65-iot2050-arduino-connector.dtsi new file mode 100644 index 0000000..7ff0abd --- /dev/null +++ b/src/arm64/ti/k3-am65-iot2050-arduino-connector.dtsi @@ -0,0 +1,768 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Siemens AG, 2018-2023 + * + * Authors: + * Le Jin <le.jin@siemens.com> + * Jan Kiszka <jan.kiszka@siemens.com> + * + * Common bits for IOT2050 variants with Arduino connector + */ + +&wkup_pmx0 { + pinctrl-names = + "default", + "d0-uart0-rxd", "d0-gpio", "d0-gpio-pullup", "d0-gpio-pulldown", + "d1-uart0-txd", "d1-gpio", "d1-gpio-pullup", "d1-gpio-pulldown", + "d2-uart0-ctsn", "d2-gpio", "d2-gpio-pullup", "d2-gpio-pulldown", + "d3-uart0-rtsn", "d3-gpio", "d3-gpio-pullup", "d3-gpio-pulldown", + "d10-spi0-cs0", "d10-gpio", "d10-gpio-pullup", "d10-gpio-pulldown", + "d11-spi0-d0", "d11-gpio", "d11-gpio-pullup", "d11-gpio-pulldown", + "d12-spi0-d1", "d12-gpio", "d12-gpio-pullup", "d12-gpio-pulldown", + "d13-spi0-clk", "d13-gpio", "d13-gpio-pullup", "d13-gpio-pulldown", + "a0-gpio", "a0-gpio-pullup", "a0-gpio-pulldown", + "a1-gpio", "a1-gpio-pullup", "a1-gpio-pulldown", + "a2-gpio", "a2-gpio-pullup", "a2-gpio-pulldown", + "a3-gpio", "a3-gpio-pullup", "a3-gpio-pulldown", + "a4-gpio", "a4-gpio-pullup", "a4-gpio-pulldown", + "a5-gpio", "a5-gpio-pullup", "a5-gpio-pulldown"; + + pinctrl-0 = <&d0_uart0_rxd>; + pinctrl-1 = <&d0_uart0_rxd>; + pinctrl-2 = <&d0_gpio>; + pinctrl-3 = <&d0_gpio_pullup>; + pinctrl-4 = <&d0_gpio_pulldown>; + pinctrl-5 = <&d1_uart0_txd>; + pinctrl-6 = <&d1_gpio>; + pinctrl-7 = <&d1_gpio_pullup>; + pinctrl-8 = <&d1_gpio_pulldown>; + pinctrl-9 = <&d2_uart0_ctsn>; + pinctrl-10 = <&d2_gpio>; + pinctrl-11 = <&d2_gpio_pullup>; + pinctrl-12 = <&d2_gpio_pulldown>; + pinctrl-13 = <&d3_uart0_rtsn>; + pinctrl-14 = <&d3_gpio>; + pinctrl-15 = <&d3_gpio_pullup>; + pinctrl-16 = <&d3_gpio_pulldown>; + pinctrl-17 = <&d10_spi0_cs0>; + pinctrl-18 = <&d10_gpio>; + pinctrl-19 = <&d10_gpio_pullup>; + pinctrl-20 = <&d10_gpio_pulldown>; + pinctrl-21 = <&d11_spi0_d0>; + pinctrl-22 = <&d11_gpio>; + pinctrl-23 = <&d11_gpio_pullup>; + pinctrl-24 = <&d11_gpio_pulldown>; + pinctrl-25 = <&d12_spi0_d1>; + pinctrl-26 = <&d12_gpio>; + pinctrl-27 = <&d12_gpio_pullup>; + pinctrl-28 = <&d12_gpio_pulldown>; + pinctrl-29 = <&d13_spi0_clk>; + pinctrl-30 = <&d13_gpio>; + pinctrl-31 = <&d13_gpio_pullup>; + pinctrl-32 = <&d13_gpio_pulldown>; + pinctrl-33 = <&a0_gpio>; + pinctrl-34 = <&a0_gpio_pullup>; + pinctrl-35 = <&a0_gpio_pulldown>; + pinctrl-36 = <&a1_gpio>; + pinctrl-37 = <&a1_gpio_pullup>; + pinctrl-38 = <&a1_gpio_pulldown>; + pinctrl-39 = <&a2_gpio>; + pinctrl-40 = <&a2_gpio_pullup>; + pinctrl-41 = <&a2_gpio_pulldown>; + pinctrl-42 = <&a3_gpio>; + pinctrl-43 = <&a3_gpio_pullup>; + pinctrl-44 = <&a3_gpio_pulldown>; + pinctrl-45 = <&a4_gpio>; + pinctrl-46 = <&a4_gpio_pullup>; + pinctrl-47 = <&a4_gpio_pulldown>; + pinctrl-48 = <&a5_gpio>; + pinctrl-49 = <&a5_gpio_pullup>; + pinctrl-50 = <&a5_gpio_pulldown>; + + d0_uart0_rxd: d0-uart0-rxd-pins { + pinctrl-single,pins = < + /* (P4) MCU_UART0_RXD */ + AM65X_WKUP_IOPAD(0x0044, PIN_INPUT, 4) + >; + }; + + d0_gpio: d0-gpio-pins { + pinctrl-single,pins = < + /* (P4) WKUP_GPIO0_29 */ + AM65X_WKUP_IOPAD(0x0044, PIN_INPUT, 7) + >; + }; + + d0_gpio_pullup: d0-gpio-pullup-pins { + pinctrl-single,pins = < + /* (P4) WKUP_GPIO0_29 */ + AM65X_WKUP_IOPAD(0x0044, PIN_INPUT_PULLUP, 7) + >; + }; + + d0_gpio_pulldown: d0-gpio-pulldown-pins { + pinctrl-single,pins = < + /* (P4) WKUP_GPIO0_29 */ + AM65X_WKUP_IOPAD(0x0044, PIN_INPUT_PULLDOWN, 7) + >; + }; + + d1_uart0_txd: d1-uart0-txd-pins { + pinctrl-single,pins = < + /* (P5) MCU_UART0_TXD */ + AM65X_WKUP_IOPAD(0x0048, PIN_OUTPUT, 4) + >; + }; + + d1_gpio: d1-gpio-pins { + pinctrl-single,pins = < + /* (P5) WKUP_GPIO0_30 */ + AM65X_WKUP_IOPAD(0x0048, PIN_INPUT, 7) + >; + }; + + d1_gpio_pullup: d1-gpio-pullup-pins { + pinctrl-single,pins = < + /* (P5) WKUP_GPIO0_30 */ + AM65X_WKUP_IOPAD(0x0048, PIN_INPUT, 7) + >; + }; + + d1_gpio_pulldown: d1-gpio-pulldown-pins { + pinctrl-single,pins = < + /* (P5) WKUP_GPIO0_30 */ + AM65X_WKUP_IOPAD(0x0048, PIN_INPUT_PULLDOWN, 7) + >; + }; + + d2_uart0_ctsn: d2-uart0-ctsn-pins { + pinctrl-single,pins = < + /* (P1) MCU_UART0_CTSn */ + AM65X_WKUP_IOPAD(0x004C, PIN_INPUT, 4) + >; + }; + + d2_gpio: d2-gpio-pins { + pinctrl-single,pins = < + /* (P5) WKUP_GPIO0_31 */ + AM65X_WKUP_IOPAD(0x004C, PIN_INPUT, 7) + >; + }; + + d2_gpio_pullup: d2-gpio-pullup-pins { + pinctrl-single,pins = < + /* (P5) WKUP_GPIO0_31 */ + AM65X_WKUP_IOPAD(0x004C, PIN_INPUT, 7) + >; + }; + + d2_gpio_pulldown: d2-gpio-pulldown-pins { + pinctrl-single,pins = < + /* (P5) WKUP_GPIO0_31 */ + AM65X_WKUP_IOPAD(0x004C, PIN_INPUT_PULLDOWN, 7) + >; + }; + + d3_uart0_rtsn: d3-uart0-rtsn-pins { + pinctrl-single,pins = < + /* (N3) MCU_UART0_RTSn */ + AM65X_WKUP_IOPAD(0x0054, PIN_OUTPUT, 4) + >; + }; + + d3_gpio: d3-gpio-pins { + pinctrl-single,pins = < + /* (N3) WKUP_GPIO0_33 */ + AM65X_WKUP_IOPAD(0x0054, PIN_INPUT, 7) + >; + }; + + d3_gpio_pullup: d3-gpio-pullup-pins { + pinctrl-single,pins = < + /* (N3) WKUP_GPIO0_33 */ + AM65X_WKUP_IOPAD(0x0054, PIN_INPUT, 7) + >; + }; + + d3_gpio_pulldown: d3-gpio-pulldown-pins { + pinctrl-single,pins = < + /* (N3) WKUP_GPIO0_33 */ + AM65X_WKUP_IOPAD(0x0054, PIN_INPUT_PULLDOWN, 7) + >; + }; + + d10_spi0_cs0: d10-spi0-cs0-pins { + pinctrl-single,pins = < + /* (Y4) MCU_SPI0_CS0 */ + AM65X_WKUP_IOPAD(0x009c, PIN_OUTPUT, 0) + >; + }; + + d10_gpio: d10-gpio-pins { + pinctrl-single,pins = < + /* (Y4) WKUP_GPIO0_51 */ + AM65X_WKUP_IOPAD(0x009c, PIN_INPUT, 7) + >; + }; + + d10_gpio_pullup: d10-gpio-pullup-pins { + pinctrl-single,pins = < + /* (Y4) WKUP_GPIO0_51 */ + AM65X_WKUP_IOPAD(0x009c, PIN_INPUT, 7) + >; + }; + + d10_gpio_pulldown: d10-gpio-pulldown-pins { + pinctrl-single,pins = < + /* (Y4) WKUP_GPIO0_51 */ + AM65X_WKUP_IOPAD(0x009c, PIN_INPUT_PULLDOWN, 7) + >; + }; + + d11_spi0_d0: d11-spi0-d0-pins { + pinctrl-single,pins = < + /* (Y3) MCU_SPI0_D0 */ + AM65X_WKUP_IOPAD(0x0094, PIN_INPUT, 0) + >; + }; + + d11_gpio: d11-gpio-pins { + pinctrl-single,pins = < + /* (Y3) WKUP_GPIO0_49 */ + AM65X_WKUP_IOPAD(0x0094, PIN_INPUT, 7) + >; + }; + + d11_gpio_pullup: d11-gpio-pullup-pins { + pinctrl-single,pins = < + /* (Y3) WKUP_GPIO0_49 */ + AM65X_WKUP_IOPAD(0x0094, PIN_INPUT, 7) + >; + }; + + d11_gpio_pulldown: d11-gpio-pulldown-pins { + pinctrl-single,pins = < + /* (Y3) WKUP_GPIO0_49 */ + AM65X_WKUP_IOPAD(0x0094, PIN_INPUT_PULLDOWN, 7) + >; + }; + + d12_spi0_d1: d12-spi0-d1-pins { + pinctrl-single,pins = < + /* (Y2) MCU_SPI0_D1 */ + AM65X_WKUP_IOPAD(0x0098, PIN_INPUT, 0) + >; + }; + + d12_gpio: d12-gpio-pins { + pinctrl-single,pins = < + /* (Y2) WKUP_GPIO0_50 */ + AM65X_WKUP_IOPAD(0x0098, PIN_INPUT, 7) + >; + }; + + d12_gpio_pullup: d12-gpio-pullup-pins { + pinctrl-single,pins = < + /* (Y2) WKUP_GPIO0_50 */ + AM65X_WKUP_IOPAD(0x0098, PIN_INPUT, 7) + >; + }; + + d12_gpio_pulldown: d12-gpio-pulldown-pins { + pinctrl-single,pins = < + /* (Y2) WKUP_GPIO0_50 */ + AM65X_WKUP_IOPAD(0x0098, PIN_INPUT_PULLDOWN, 7) + >; + }; + + d13_spi0_clk: d13-spi0-clk-pins { + pinctrl-single,pins = < + /* (Y1) MCU_SPI0_CLK */ + AM65X_WKUP_IOPAD(0x0090, PIN_INPUT, 0) + >; + }; + + d13_gpio: d13-gpio-pins { + pinctrl-single,pins = < + /* (Y1) WKUP_GPIO0_48 */ + AM65X_WKUP_IOPAD(0x0090, PIN_INPUT, 7) + >; + }; + + d13_gpio_pullup: d13-gpio-pullup-pins { + pinctrl-single,pins = < + /* (Y1) WKUP_GPIO0_48 */ + AM65X_WKUP_IOPAD(0x0090, PIN_INPUT, 7) + >; + }; + + d13_gpio_pulldown: d13-gpio-pulldown-pins { + pinctrl-single,pins = < + /* (Y1) WKUP_GPIO0_48 */ + AM65X_WKUP_IOPAD(0x0090, PIN_INPUT_PULLDOWN, 7) + >; + }; + + a0_gpio: a0-gpio-pins { + pinctrl-single,pins = < + /* (L6) WKUP_GPIO0_45 */ + AM65X_WKUP_IOPAD(0x0084, PIN_INPUT, 7) + >; + }; + + a0_gpio_pullup: a0-gpio-pullup-pins { + pinctrl-single,pins = < + /* (L6) WKUP_GPIO0_45 */ + AM65X_WKUP_IOPAD(0x0084, PIN_INPUT, 7) + >; + }; + + a0_gpio_pulldown: a0-gpio-pulldown-pins { + pinctrl-single,pins = < + /* (L6) WKUP_GPIO0_45 */ + AM65X_WKUP_IOPAD(0x0084, PIN_INPUT_PULLDOWN, 7) + >; + }; + + a1_gpio: a1-gpio-pins { + pinctrl-single,pins = < + /* (M6) WKUP_GPIO0_44 */ + AM65X_WKUP_IOPAD(0x0080, PIN_INPUT, 7) + >; + }; + + a1_gpio_pullup: a1-gpio-pullup-pins { + pinctrl-single,pins = < + /* (M6) WKUP_GPIO0_44 */ + AM65X_WKUP_IOPAD(0x0080, PIN_INPUT, 7) + >; + }; + + a1_gpio_pulldown: a1-gpio-pulldown-pins { + pinctrl-single,pins = < + /* (M6) WKUP_GPIO0_44 */ + AM65X_WKUP_IOPAD(0x0080, PIN_INPUT_PULLDOWN, 7) + >; + }; + + a2_gpio: a2-gpio-pins { + pinctrl-single,pins = < + /* (L5) WKUP_GPIO0_43 */ + AM65X_WKUP_IOPAD(0x007C, PIN_INPUT, 7) + >; + }; + + a2_gpio_pullup: a2-gpio-pullup-pins { + pinctrl-single,pins = < + /* (L5) WKUP_GPIO0_43 */ + AM65X_WKUP_IOPAD(0x007C, PIN_INPUT, 7) + >; + }; + + a2_gpio_pulldown: a2-gpio-pulldown-pins { + pinctrl-single,pins = < + /* (L5) WKUP_GPIO0_43 */ + AM65X_WKUP_IOPAD(0x007C, PIN_INPUT_PULLDOWN, 7) + >; + }; + + a3_gpio: a3-gpio-pins { + pinctrl-single,pins = < + /* (M5) WKUP_GPIO0_39 */ + AM65X_WKUP_IOPAD(0x006C, PIN_INPUT, 7) + >; + }; + + a3_gpio_pullup: a3-gpio-pullup-pins { + pinctrl-single,pins = < + /* (M5) WKUP_GPIO0_39 */ + AM65X_WKUP_IOPAD(0x006C, PIN_INPUT, 7) + >; + }; + + a3_gpio_pulldown: a3-gpio-pulldown-pins { + pinctrl-single,pins = < + /* (M5) WKUP_GPIO0_39 */ + AM65X_WKUP_IOPAD(0x006C, PIN_INPUT_PULLDOWN, 7) + >; + }; + + a4_gpio: a4-gpio-pins { + pinctrl-single,pins = < + /* (L2) WKUP_GPIO0_42 */ + AM65X_WKUP_IOPAD(0x0078, PIN_INPUT, 7) + >; + }; + + a4_gpio_pullup: a4-gpio-pullup-pins { + pinctrl-single,pins = < + /* (L2) WKUP_GPIO0_42 */ + AM65X_WKUP_IOPAD(0x0078, PIN_INPUT, 7) + >; + }; + + a4_gpio_pulldown: a4-gpio-pulldown-pins { + pinctrl-single,pins = < + /* (L2) WKUP_GPIO0_42 */ + AM65X_WKUP_IOPAD(0x0078, PIN_INPUT_PULLDOWN, 7) + >; + }; + + a5_gpio: a5-gpio-pins { + pinctrl-single,pins = < + /* (N5) WKUP_GPIO0_35 */ + AM65X_WKUP_IOPAD(0x005C, PIN_INPUT, 7) + >; + }; + + a5_gpio_pullup: a5-gpio-pullup-pins { + pinctrl-single,pins = < + /* (N5) WKUP_GPIO0_35 */ + AM65X_WKUP_IOPAD(0x005C, PIN_INPUT_PULLUP, 7) + >; + }; + + a5_gpio_pulldown: a5-gpio-pulldown-pins { + pinctrl-single,pins = < + /* (N5) WKUP_GPIO0_35 */ + AM65X_WKUP_IOPAD(0x005C, PIN_INPUT_PULLDOWN, 7) + >; + }; + + wkup_i2c0_pins_default: wkup-i2c0-default-pins { + pinctrl-single,pins = < + /* (AC7) WKUP_I2C0_SCL */ + AM65X_WKUP_IOPAD(0x00e0, PIN_INPUT, 0) + /* (AD6) WKUP_I2C0_SDA */ + AM65X_WKUP_IOPAD(0x00e4, PIN_INPUT, 0) + >; + }; + + arduino_i2c_aio_switch_pins_default: arduino-i2c-aio-switch-default-pins { + pinctrl-single,pins = < + /* (R2) WKUP_GPIO0_21 */ + AM65X_WKUP_IOPAD(0x0024, PIN_OUTPUT, 7) + >; + }; + + arduino_io_oe_pins_default: arduino-io-oe-default-pins { + pinctrl-single,pins = < + /* (N4) WKUP_GPIO0_34 */ + AM65X_WKUP_IOPAD(0x0058, PIN_OUTPUT, 7) + /* (M2) WKUP_GPIO0_36 */ + AM65X_WKUP_IOPAD(0x0060, PIN_OUTPUT, 7) + /* (M3) WKUP_GPIO0_37 */ + AM65X_WKUP_IOPAD(0x0064, PIN_OUTPUT, 7) + /* (M4) WKUP_GPIO0_38 */ + AM65X_WKUP_IOPAD(0x0068, PIN_OUTPUT, 7) + /* (M1) WKUP_GPIO0_41 */ + AM65X_WKUP_IOPAD(0x0074, PIN_OUTPUT, 7) + >; + }; +}; + +&main_pmx0 { + pinctrl-names = + "default", + "d4-ehrpwm0-a", "d4-gpio", "d4-gpio-pullup", "d4-gpio-pulldown", + "d5-ehrpwm1-a", "d5-gpio", "d5-gpio-pullup", "d5-gpio-pulldown", + "d6-ehrpwm2-a", "d6-gpio", "d6-gpio-pullup", "d6-gpio-pulldown", + "d7-ehrpwm3-a", "d7-gpio", "d7-gpio-pullup", "d7-gpio-pulldown", + "d8-ehrpwm4-a", "d8-gpio", "d8-gpio-pullup", "d8-gpio-pulldown", + "d9-ehrpwm5-a", "d9-gpio", "d9-gpio-pullup", "d9-gpio-pulldown"; + + pinctrl-0 = <&d4_ehrpwm0_a>; + pinctrl-1 = <&d4_ehrpwm0_a>; + pinctrl-2 = <&d4_gpio>; + pinctrl-3 = <&d4_gpio_pullup>; + pinctrl-4 = <&d4_gpio_pulldown>; + + pinctrl-5 = <&d5_ehrpwm1_a>; + pinctrl-6 = <&d5_gpio>; + pinctrl-7 = <&d5_gpio_pullup>; + pinctrl-8 = <&d5_gpio_pulldown>; + + pinctrl-9 = <&d6_ehrpwm2_a>; + pinctrl-10 = <&d6_gpio>; + pinctrl-11 = <&d6_gpio_pullup>; + pinctrl-12 = <&d6_gpio_pulldown>; + + pinctrl-13 = <&d7_ehrpwm3_a>; + pinctrl-14 = <&d7_gpio>; + pinctrl-15 = <&d7_gpio_pullup>; + pinctrl-16 = <&d7_gpio_pulldown>; + + pinctrl-17 = <&d8_ehrpwm4_a>; + pinctrl-18 = <&d8_gpio>; + pinctrl-19 = <&d8_gpio_pullup>; + pinctrl-20 = <&d8_gpio_pulldown>; + + pinctrl-21 = <&d9_ehrpwm5_a>; + pinctrl-22 = <&d9_gpio>; + pinctrl-23 = <&d9_gpio_pullup>; + pinctrl-24 = <&d9_gpio_pulldown>; + + d4_ehrpwm0_a: d4-ehrpwm0-a-pins { + pinctrl-single,pins = < + /* (AG18) EHRPWM0_A */ + AM65X_IOPAD(0x0084, PIN_OUTPUT, 5) + >; + }; + + d4_gpio: d4-gpio-pins { + pinctrl-single,pins = < + /* (AG18) GPIO0_33 */ + AM65X_IOPAD(0x0084, PIN_INPUT, 7) + >; + }; + + d4_gpio_pullup: d4-gpio-pullup-pins { + pinctrl-single,pins = < + /* (AG18) GPIO0_33 */ + AM65X_IOPAD(0x0084, PIN_INPUT_PULLUP, 7) + >; + }; + + d4_gpio_pulldown: d4-gpio-pulldown-pins { + pinctrl-single,pins = < + /* (AG18) GPIO0_33 */ + AM65X_IOPAD(0x0084, PIN_INPUT_PULLDOWN, 7) + >; + }; + + d5_ehrpwm1_a: d5-ehrpwm1-a-pins { + pinctrl-single,pins = < + /* (AF17) EHRPWM1_A */ + AM65X_IOPAD(0x008C, PIN_OUTPUT, 5) + >; + }; + + d5_gpio: d5-gpio-pins { + pinctrl-single,pins = < + /* (AF17) GPIO0_35 */ + AM65X_IOPAD(0x008C, PIN_INPUT, 7) + >; + }; + + d5_gpio_pullup: d5-gpio-pullup-pins { + pinctrl-single,pins = < + /* (AF17) GPIO0_35 */ + AM65X_IOPAD(0x008C, PIN_INPUT_PULLUP, 7) + >; + }; + + d5_gpio_pulldown: d5-gpio-pulldown-pins { + pinctrl-single,pins = < + /* (AF17) GPIO0_35 */ + AM65X_IOPAD(0x008C, PIN_INPUT_PULLDOWN, 7) + >; + }; + + d6_ehrpwm2_a: d6-ehrpwm2-a-pins { + pinctrl-single,pins = < + /* (AH16) EHRPWM2_A */ + AM65X_IOPAD(0x0098, PIN_OUTPUT, 5) + >; + }; + + d6_gpio: d6-gpio-pins { + pinctrl-single,pins = < + /* (AH16) GPIO0_38 */ + AM65X_IOPAD(0x0098, PIN_INPUT, 7) + >; + }; + + d6_gpio_pullup: d6-gpio-pullup-pins { + pinctrl-single,pins = < + /* (AH16) GPIO0_38 */ + AM65X_IOPAD(0x0098, PIN_INPUT_PULLUP, 7) + >; + }; + + d6_gpio_pulldown: d6-gpio-pulldown-pins { + pinctrl-single,pins = < + /* (AH16) GPIO0_38 */ + AM65X_IOPAD(0x0098, PIN_INPUT_PULLDOWN, 7) + >; + }; + + d7_ehrpwm3_a: d7-ehrpwm3-a-pins { + pinctrl-single,pins = < + /* (AH15) EHRPWM3_A */ + AM65X_IOPAD(0x00AC, PIN_OUTPUT, 5) + >; + }; + + d7_gpio: d7-gpio-pins { + pinctrl-single,pins = < + /* (AH15) GPIO0_43 */ + AM65X_IOPAD(0x00AC, PIN_INPUT, 7) + >; + }; + + d7_gpio_pullup: d7-gpio-pullup-pins { + pinctrl-single,pins = < + /* (AH15) GPIO0_43 */ + AM65X_IOPAD(0x00AC, PIN_INPUT_PULLUP, 7) + >; + }; + + d7_gpio_pulldown: d7-gpio-pulldown-pins { + pinctrl-single,pins = < + /* (AH15) GPIO0_43 */ + AM65X_IOPAD(0x00AC, PIN_INPUT_PULLDOWN, 7) + >; + }; + + d8_ehrpwm4_a: d8-ehrpwm4-a-pins { + pinctrl-single,pins = < + /* (AG15) EHRPWM4_A */ + AM65X_IOPAD(0x00C0, PIN_OUTPUT, 5) + >; + }; + + d8_gpio: d8-gpio-pins { + pinctrl-single,pins = < + /* (AG15) GPIO0_48 */ + AM65X_IOPAD(0x00C0, PIN_INPUT, 7) + >; + }; + + d8_gpio_pullup: d8-gpio-pullup-pins { + pinctrl-single,pins = < + /* (AG15) GPIO0_48 */ + AM65X_IOPAD(0x00C0, PIN_INPUT_PULLUP, 7) + >; + }; + + d8_gpio_pulldown: d8-gpio-pulldown-pins { + pinctrl-single,pins = < + /* (AG15) GPIO0_48 */ + AM65X_IOPAD(0x00C0, PIN_INPUT_PULLDOWN, 7) + >; + }; + + d9_ehrpwm5_a: d9-ehrpwm5-a-pins { + pinctrl-single,pins = < + /* (AD15) EHRPWM5_A */ + AM65X_IOPAD(0x00CC, PIN_OUTPUT, 5) + >; + }; + + d9_gpio: d9-gpio-pins { + pinctrl-single,pins = < + /* (AD15) GPIO0_51 */ + AM65X_IOPAD(0x00CC, PIN_INPUT, 7) + >; + }; + + d9_gpio_pullup: d9-gpio-pullup-pins { + pinctrl-single,pins = < + /* (AD15) GPIO0_51 */ + AM65X_IOPAD(0x00CC, PIN_INPUT_PULLUP, 7) + >; + }; + + d9_gpio_pulldown: d9-gpio-pulldown-pins { + pinctrl-single,pins = < + /* (AD15) GPIO0_51 */ + AM65X_IOPAD(0x00CC, PIN_INPUT_PULLDOWN, 7) + >; + }; +}; + +&main_gpio0 { + gpio-line-names = + "main_gpio0-base", "", "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", "", "", + "", "", "", "IO4", "", "IO5", "", "", "IO6", "", + "", "", "", "IO7", "", "", "", "", "IO8", "", + "", "IO9"; +}; + +&wkup_gpio0 { + pinctrl-names = "default"; + pinctrl-0 = + <&arduino_i2c_aio_switch_pins_default>, + <&arduino_io_oe_pins_default>, + <&push_button_pins_default>, + <&db9_com_mode_pins_default>; + gpio-line-names = + /* 0..9 */ + "wkup_gpio0-base", "", "", "", "UART0-mode1", "UART0-mode0", + "UART0-enable", "UART0-terminate", "", "WIFI-disable", + /* 10..19 */ + "", "", "", "", "", "", "", "", "", "", + /* 20..29 */ + "", "A4A5-I2C-mux", "", "", "", "USER-button", "", "", "","IO0", + /* 30..39 */ + "IO1", "IO2", "", "IO3", "IO17-direction", "A5", + "IO16-direction", "IO15-direction", "IO14-direction", "A3", + /* 40..49 */ + "", "IO18-direction", "A4", "A2", "A1", "A0", "", "", "IO13", + "IO11", + /* 50..51 */ + "IO12", "IO10"; +}; + +&wkup_i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&wkup_i2c0_pins_default>; + clock-frequency = <400000>; +}; + +&mcu_i2c0 { + /* D4200 */ + pcal9535_1: gpio@20 { + compatible = "nxp,pcal9535"; + reg = <0x20>; + #gpio-cells = <2>; + gpio-controller; + gpio-line-names = + "A0-pull", "A1-pull", "A2-pull", "A3-pull", "A4-pull", + "A5-pull", "", "", + "IO14-enable", "IO15-enable", "IO16-enable", + "IO17-enable", "IO18-enable", "IO19-enable"; + }; + + /* D4201 */ + pcal9535_2: gpio@21 { + compatible = "nxp,pcal9535"; + reg = <0x21>; + #gpio-cells = <2>; + gpio-controller; + gpio-line-names = + "IO0-direction", "IO1-direction", "IO2-direction", + "IO3-direction", "IO4-direction", "IO5-direction", + "IO6-direction", "IO7-direction", + "IO8-direction", "IO9-direction", "IO10-direction", + "IO11-direction", "IO12-direction", "IO13-direction", + "IO19-direction"; + }; + + /* D4202 */ + pcal9535_3: gpio@25 { + compatible = "nxp,pcal9535"; + reg = <0x25>; + #gpio-cells = <2>; + gpio-controller; + gpio-line-names = + "IO0-pull", "IO1-pull", "IO2-pull", "IO3-pull", + "IO4-pull", "IO5-pull", "IO6-pull", "IO7-pull", + "IO8-pull", "IO9-pull", "IO10-pull", "IO11-pull", + "IO12-pull", "IO13-pull"; + }; +}; + +&mcu_uart0 { + status = "okay"; +}; + +&tscadc1 { + status = "okay"; + adc { + ti,adc-channels = <0 1 2 3 4 5>; + }; +}; diff --git a/src/arm64/ti/k3-am65-iot2050-common-pg1.dtsi b/src/arm64/ti/k3-am65-iot2050-common-pg1.dtsi index 1d19798..c50a585 100644 --- a/src/arm64/ti/k3-am65-iot2050-common-pg1.dtsi +++ b/src/arm64/ti/k3-am65-iot2050-common-pg1.dtsi @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) Siemens AG, 2021-2023 * @@ -8,10 +8,7 @@ * Common bits of the IOT2050 Basic and Advanced variants, PG1 */ -&dss { - assigned-clocks = <&k3_clks 67 2>; - assigned-clock-parents = <&k3_clks 67 5>; -}; +#include "k3-am65-iot2050-dp.dtsi" &serdes0 { status = "disabled"; diff --git a/src/arm64/ti/k3-am65-iot2050-common-pg2.dtsi b/src/arm64/ti/k3-am65-iot2050-common-pg2.dtsi index e9b57b8..e2584a5 100644 --- a/src/arm64/ti/k3-am65-iot2050-common-pg2.dtsi +++ b/src/arm64/ti/k3-am65-iot2050-common-pg2.dtsi @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) Siemens AG, 2021 + * Copyright (c) Siemens AG, 2021-2023 * * Authors: * Chao Zeng <chao.zeng@siemens.com> @@ -9,6 +9,11 @@ * Common bits of the IOT2050 Basic and Advanced variants, PG2 */ +&mcu_r5fss0 { + /* lock-step mode not supported on PG2 boards */ + ti,cluster-mode = <0>; +}; + &main_pmx0 { cp2102n_reset_pin_default: cp2102n-reset-default-pins { pinctrl-single,pins = < @@ -33,21 +38,3 @@ /* Workaround needed to get DP clock of 154Mhz */ assigned-clocks = <&k3_clks 67 0>; }; - -&serdes0 { - assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>; - assigned-clock-parents = <&k3_clks 153 7>, <&k3_clks 153 4>; -}; - -&dwc3_0 { - assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */ - <&k3_clks 151 8>; /* set PIPE3_TXB_CLK to WIZ8B2M4VSB */ - phys = <&serdes0 PHY_TYPE_USB3 0>; - phy-names = "usb3-phy"; -}; - -&usb0 { - maximum-speed = "super-speed"; - snps,dis-u1-entry-quirk; - snps,dis-u2-entry-quirk; -}; diff --git a/src/arm64/ti/k3-am65-iot2050-common.dtsi b/src/arm64/ti/k3-am65-iot2050-common.dtsi index 61a634a..ef34b85 100644 --- a/src/arm64/ti/k3-am65-iot2050-common.dtsi +++ b/src/arm64/ti/k3-am65-iot2050-common.dtsi @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) Siemens AG, 2018-2021 + * Copyright (c) Siemens AG, 2018-2024 * * Authors: * Le Jin <le.jin@siemens.com> @@ -9,6 +9,7 @@ * Common bits of the IOT2050 Basic and Advanced variants, PG1 and PG2 */ +#include <dt-bindings/leds/common.h> #include <dt-bindings/phy/phy.h> #include <dt-bindings/net/ti-dp83867.h> @@ -75,6 +76,12 @@ alignment = <0x1000>; no-map; }; + + /* To reserve the power-on(PON) reason for watchdog reset */ + wdt_reset_memory_region: wdt-memory@a2200000 { + reg = <0x00 0xa2200000 0x00 0x1000>; + no-map; + }; }; leds { @@ -82,28 +89,46 @@ pinctrl-names = "default"; pinctrl-0 = <&leds_pins_default>; - status-led-red { + led-0 { + color = <LED_COLOR_ID_RED>; + function = LED_FUNCTION_STATUS; + label = "status-led-red"; gpios = <&wkup_gpio0 32 GPIO_ACTIVE_HIGH>; panic-indicator; }; - status-led-green { + led-1 { + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_STATUS; + label = "status-led-green"; gpios = <&wkup_gpio0 24 GPIO_ACTIVE_HIGH>; }; - user-led1-red { + led-2 { + color = <LED_COLOR_ID_RED>; + function = LED_FUNCTION_INDICATOR; + label = "user-led1-red"; gpios = <&pcal9535_3 14 GPIO_ACTIVE_HIGH>; }; - user-led1-green { + led-3 { + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_INDICATOR; + label = "user-led1-green"; gpios = <&pcal9535_2 15 GPIO_ACTIVE_HIGH>; }; - user-led2-red { + led-4 { + color = <LED_COLOR_ID_RED>; + function = LED_FUNCTION_INDICATOR; + label = "user-led2-red"; gpios = <&wkup_gpio0 17 GPIO_ACTIVE_HIGH>; }; - user-led2-green { + led-5 { + color = <LED_COLOR_ID_RED>; + function = LED_FUNCTION_INDICATOR; + label = "user-led2-green"; gpios = <&wkup_gpio0 22 GPIO_ACTIVE_HIGH>; }; }; @@ -186,434 +211,6 @@ }; &wkup_pmx0 { - pinctrl-names = - "default", - "d0-uart0-rxd", "d0-gpio", "d0-gpio-pullup", "d0-gpio-pulldown", - "d1-uart0-txd", "d1-gpio", "d1-gpio-pullup", "d1-gpio-pulldown", - "d2-uart0-ctsn", "d2-gpio", "d2-gpio-pullup", "d2-gpio-pulldown", - "d3-uart0-rtsn", "d3-gpio", "d3-gpio-pullup", "d3-gpio-pulldown", - "d10-spi0-cs0", "d10-gpio", "d10-gpio-pullup", "d10-gpio-pulldown", - "d11-spi0-d0", "d11-gpio", "d11-gpio-pullup", "d11-gpio-pulldown", - "d12-spi0-d1", "d12-gpio", "d12-gpio-pullup", "d12-gpio-pulldown", - "d13-spi0-clk", "d13-gpio", "d13-gpio-pullup", "d13-gpio-pulldown", - "a0-gpio", "a0-gpio-pullup", "a0-gpio-pulldown", - "a1-gpio", "a1-gpio-pullup", "a1-gpio-pulldown", - "a2-gpio", "a2-gpio-pullup", "a2-gpio-pulldown", - "a3-gpio", "a3-gpio-pullup", "a3-gpio-pulldown", - "a4-gpio", "a4-gpio-pullup", "a4-gpio-pulldown", - "a5-gpio", "a5-gpio-pullup", "a5-gpio-pulldown"; - - pinctrl-0 = <&d0_uart0_rxd>; - pinctrl-1 = <&d0_uart0_rxd>; - pinctrl-2 = <&d0_gpio>; - pinctrl-3 = <&d0_gpio_pullup>; - pinctrl-4 = <&d0_gpio_pulldown>; - pinctrl-5 = <&d1_uart0_txd>; - pinctrl-6 = <&d1_gpio>; - pinctrl-7 = <&d1_gpio_pullup>; - pinctrl-8 = <&d1_gpio_pulldown>; - pinctrl-9 = <&d2_uart0_ctsn>; - pinctrl-10 = <&d2_gpio>; - pinctrl-11 = <&d2_gpio_pullup>; - pinctrl-12 = <&d2_gpio_pulldown>; - pinctrl-13 = <&d3_uart0_rtsn>; - pinctrl-14 = <&d3_gpio>; - pinctrl-15 = <&d3_gpio_pullup>; - pinctrl-16 = <&d3_gpio_pulldown>; - pinctrl-17 = <&d10_spi0_cs0>; - pinctrl-18 = <&d10_gpio>; - pinctrl-19 = <&d10_gpio_pullup>; - pinctrl-20 = <&d10_gpio_pulldown>; - pinctrl-21 = <&d11_spi0_d0>; - pinctrl-22 = <&d11_gpio>; - pinctrl-23 = <&d11_gpio_pullup>; - pinctrl-24 = <&d11_gpio_pulldown>; - pinctrl-25 = <&d12_spi0_d1>; - pinctrl-26 = <&d12_gpio>; - pinctrl-27 = <&d12_gpio_pullup>; - pinctrl-28 = <&d12_gpio_pulldown>; - pinctrl-29 = <&d13_spi0_clk>; - pinctrl-30 = <&d13_gpio>; - pinctrl-31 = <&d13_gpio_pullup>; - pinctrl-32 = <&d13_gpio_pulldown>; - pinctrl-33 = <&a0_gpio>; - pinctrl-34 = <&a0_gpio_pullup>; - pinctrl-35 = <&a0_gpio_pulldown>; - pinctrl-36 = <&a1_gpio>; - pinctrl-37 = <&a1_gpio_pullup>; - pinctrl-38 = <&a1_gpio_pulldown>; - pinctrl-39 = <&a2_gpio>; - pinctrl-40 = <&a2_gpio_pullup>; - pinctrl-41 = <&a2_gpio_pulldown>; - pinctrl-42 = <&a3_gpio>; - pinctrl-43 = <&a3_gpio_pullup>; - pinctrl-44 = <&a3_gpio_pulldown>; - pinctrl-45 = <&a4_gpio>; - pinctrl-46 = <&a4_gpio_pullup>; - pinctrl-47 = <&a4_gpio_pulldown>; - pinctrl-48 = <&a5_gpio>; - pinctrl-49 = <&a5_gpio_pullup>; - pinctrl-50 = <&a5_gpio_pulldown>; - - d0_uart0_rxd: d0-uart0-rxd-pins { - pinctrl-single,pins = < - /* (P4) MCU_UART0_RXD */ - AM65X_WKUP_IOPAD(0x0044, PIN_INPUT, 4) - >; - }; - - d0_gpio: d0-gpio-pins { - pinctrl-single,pins = < - /* (P4) WKUP_GPIO0_29 */ - AM65X_WKUP_IOPAD(0x0044, PIN_INPUT, 7) - >; - }; - - d0_gpio_pullup: d0-gpio-pullup-pins { - pinctrl-single,pins = < - /* (P4) WKUP_GPIO0_29 */ - AM65X_WKUP_IOPAD(0x0044, PIN_INPUT_PULLUP, 7) - >; - }; - - d0_gpio_pulldown: d0-gpio-pulldown-pins { - pinctrl-single,pins = < - /* (P4) WKUP_GPIO0_29 */ - AM65X_WKUP_IOPAD(0x0044, PIN_INPUT_PULLDOWN, 7) - >; - }; - - d1_uart0_txd: d1-uart0-txd-pins { - pinctrl-single,pins = < - /* (P5) MCU_UART0_TXD */ - AM65X_WKUP_IOPAD(0x0048, PIN_OUTPUT, 4) - >; - }; - - d1_gpio: d1-gpio-pins { - pinctrl-single,pins = < - /* (P5) WKUP_GPIO0_30 */ - AM65X_WKUP_IOPAD(0x0048, PIN_INPUT, 7) - >; - }; - - d1_gpio_pullup: d1-gpio-pullup-pins { - pinctrl-single,pins = < - /* (P5) WKUP_GPIO0_30 */ - AM65X_WKUP_IOPAD(0x0048, PIN_INPUT, 7) - >; - }; - - d1_gpio_pulldown: d1-gpio-pulldown-pins { - pinctrl-single,pins = < - /* (P5) WKUP_GPIO0_30 */ - AM65X_WKUP_IOPAD(0x0048, PIN_INPUT_PULLDOWN, 7) - >; - }; - - d2_uart0_ctsn: d2-uart0-ctsn-pins { - pinctrl-single,pins = < - /* (P1) MCU_UART0_CTSn */ - AM65X_WKUP_IOPAD(0x004C, PIN_INPUT, 4) - >; - }; - - d2_gpio: d2-gpio-pins { - pinctrl-single,pins = < - /* (P5) WKUP_GPIO0_31 */ - AM65X_WKUP_IOPAD(0x004C, PIN_INPUT, 7) - >; - }; - - d2_gpio_pullup: d2-gpio-pullup-pins { - pinctrl-single,pins = < - /* (P5) WKUP_GPIO0_31 */ - AM65X_WKUP_IOPAD(0x004C, PIN_INPUT, 7) - >; - }; - - d2_gpio_pulldown: d2-gpio-pulldown-pins { - pinctrl-single,pins = < - /* (P5) WKUP_GPIO0_31 */ - AM65X_WKUP_IOPAD(0x004C, PIN_INPUT_PULLDOWN, 7) - >; - }; - - d3_uart0_rtsn: d3-uart0-rtsn-pins { - pinctrl-single,pins = < - /* (N3) MCU_UART0_RTSn */ - AM65X_WKUP_IOPAD(0x0054, PIN_OUTPUT, 4) - >; - }; - - d3_gpio: d3-gpio-pins { - pinctrl-single,pins = < - /* (N3) WKUP_GPIO0_33 */ - AM65X_WKUP_IOPAD(0x0054, PIN_INPUT, 7) - >; - }; - - d3_gpio_pullup: d3-gpio-pullup-pins { - pinctrl-single,pins = < - /* (N3) WKUP_GPIO0_33 */ - AM65X_WKUP_IOPAD(0x0054, PIN_INPUT, 7) - >; - }; - - d3_gpio_pulldown: d3-gpio-pulldown-pins { - pinctrl-single,pins = < - /* (N3) WKUP_GPIO0_33 */ - AM65X_WKUP_IOPAD(0x0054, PIN_INPUT_PULLDOWN, 7) - >; - }; - - d10_spi0_cs0: d10-spi0-cs0-pins { - pinctrl-single,pins = < - /* (Y4) MCU_SPI0_CS0 */ - AM65X_WKUP_IOPAD(0x009c, PIN_OUTPUT, 0) - >; - }; - - d10_gpio: d10-gpio-pins { - pinctrl-single,pins = < - /* (Y4) WKUP_GPIO0_51 */ - AM65X_WKUP_IOPAD(0x009c, PIN_INPUT, 7) - >; - }; - - d10_gpio_pullup: d10-gpio-pullup-pins { - pinctrl-single,pins = < - /* (Y4) WKUP_GPIO0_51 */ - AM65X_WKUP_IOPAD(0x009c, PIN_INPUT, 7) - >; - }; - - d10_gpio_pulldown: d10-gpio-pulldown-pins { - pinctrl-single,pins = < - /* (Y4) WKUP_GPIO0_51 */ - AM65X_WKUP_IOPAD(0x009c, PIN_INPUT_PULLDOWN, 7) - >; - }; - - d11_spi0_d0: d11-spi0-d0-pins { - pinctrl-single,pins = < - /* (Y3) MCU_SPI0_D0 */ - AM65X_WKUP_IOPAD(0x0094, PIN_INPUT, 0) - >; - }; - - d11_gpio: d11-gpio-pins { - pinctrl-single,pins = < - /* (Y3) WKUP_GPIO0_49 */ - AM65X_WKUP_IOPAD(0x0094, PIN_INPUT, 7) - >; - }; - - d11_gpio_pullup: d11-gpio-pullup-pins { - pinctrl-single,pins = < - /* (Y3) WKUP_GPIO0_49 */ - AM65X_WKUP_IOPAD(0x0094, PIN_INPUT, 7) - >; - }; - - d11_gpio_pulldown: d11-gpio-pulldown-pins { - pinctrl-single,pins = < - /* (Y3) WKUP_GPIO0_49 */ - AM65X_WKUP_IOPAD(0x0094, PIN_INPUT_PULLDOWN, 7) - >; - }; - - d12_spi0_d1: d12-spi0-d1-pins { - pinctrl-single,pins = < - /* (Y2) MCU_SPI0_D1 */ - AM65X_WKUP_IOPAD(0x0098, PIN_INPUT, 0) - >; - }; - - d12_gpio: d12-gpio-pins { - pinctrl-single,pins = < - /* (Y2) WKUP_GPIO0_50 */ - AM65X_WKUP_IOPAD(0x0098, PIN_INPUT, 7) - >; - }; - - d12_gpio_pullup: d12-gpio-pullup-pins { - pinctrl-single,pins = < - /* (Y2) WKUP_GPIO0_50 */ - AM65X_WKUP_IOPAD(0x0098, PIN_INPUT, 7) - >; - }; - - d12_gpio_pulldown: d12-gpio-pulldown-pins { - pinctrl-single,pins = < - /* (Y2) WKUP_GPIO0_50 */ - AM65X_WKUP_IOPAD(0x0098, PIN_INPUT_PULLDOWN, 7) - >; - }; - - d13_spi0_clk: d13-spi0-clk-pins { - pinctrl-single,pins = < - /* (Y1) MCU_SPI0_CLK */ - AM65X_WKUP_IOPAD(0x0090, PIN_INPUT, 0) - >; - }; - - d13_gpio: d13-gpio-pins { - pinctrl-single,pins = < - /* (Y1) WKUP_GPIO0_48 */ - AM65X_WKUP_IOPAD(0x0090, PIN_INPUT, 7) - >; - }; - - d13_gpio_pullup: d13-gpio-pullup-pins { - pinctrl-single,pins = < - /* (Y1) WKUP_GPIO0_48 */ - AM65X_WKUP_IOPAD(0x0090, PIN_INPUT, 7) - >; - }; - - d13_gpio_pulldown: d13-gpio-pulldown-pins { - pinctrl-single,pins = < - /* (Y1) WKUP_GPIO0_48 */ - AM65X_WKUP_IOPAD(0x0090, PIN_INPUT_PULLDOWN, 7) - >; - }; - - a0_gpio: a0-gpio-pins { - pinctrl-single,pins = < - /* (L6) WKUP_GPIO0_45 */ - AM65X_WKUP_IOPAD(0x0084, PIN_INPUT, 7) - >; - }; - - a0_gpio_pullup: a0-gpio-pullup-pins { - pinctrl-single,pins = < - /* (L6) WKUP_GPIO0_45 */ - AM65X_WKUP_IOPAD(0x0084, PIN_INPUT, 7) - >; - }; - - a0_gpio_pulldown: a0-gpio-pulldown-pins { - pinctrl-single,pins = < - /* (L6) WKUP_GPIO0_45 */ - AM65X_WKUP_IOPAD(0x0084, PIN_INPUT_PULLDOWN, 7) - >; - }; - - a1_gpio: a1-gpio-pins { - pinctrl-single,pins = < - /* (M6) WKUP_GPIO0_44 */ - AM65X_WKUP_IOPAD(0x0080, PIN_INPUT, 7) - >; - }; - - a1_gpio_pullup: a1-gpio-pullup-pins { - pinctrl-single,pins = < - /* (M6) WKUP_GPIO0_44 */ - AM65X_WKUP_IOPAD(0x0080, PIN_INPUT, 7) - >; - }; - - a1_gpio_pulldown: a1-gpio-pulldown-pins { - pinctrl-single,pins = < - /* (M6) WKUP_GPIO0_44 */ - AM65X_WKUP_IOPAD(0x0080, PIN_INPUT_PULLDOWN, 7) - >; - }; - - a2_gpio: a2-gpio-pins { - pinctrl-single,pins = < - /* (L5) WKUP_GPIO0_43 */ - AM65X_WKUP_IOPAD(0x007C, PIN_INPUT, 7) - >; - }; - - a2_gpio_pullup: a2-gpio-pullup-pins { - pinctrl-single,pins = < - /* (L5) WKUP_GPIO0_43 */ - AM65X_WKUP_IOPAD(0x007C, PIN_INPUT, 7) - >; - }; - - a2_gpio_pulldown: a2-gpio-pulldown-pins { - pinctrl-single,pins = < - /* (L5) WKUP_GPIO0_43 */ - AM65X_WKUP_IOPAD(0x007C, PIN_INPUT_PULLDOWN, 7) - >; - }; - - a3_gpio: a3-gpio-pins { - pinctrl-single,pins = < - /* (M5) WKUP_GPIO0_39 */ - AM65X_WKUP_IOPAD(0x006C, PIN_INPUT, 7) - >; - }; - - a3_gpio_pullup: a3-gpio-pullup-pins { - pinctrl-single,pins = < - /* (M5) WKUP_GPIO0_39 */ - AM65X_WKUP_IOPAD(0x006C, PIN_INPUT, 7) - >; - }; - - a3_gpio_pulldown: a3-gpio-pulldown-pins { - pinctrl-single,pins = < - /* (M5) WKUP_GPIO0_39 */ - AM65X_WKUP_IOPAD(0x006C, PIN_INPUT_PULLDOWN, 7) - >; - }; - - a4_gpio: a4-gpio-pins { - pinctrl-single,pins = < - /* (L2) WKUP_GPIO0_42 */ - AM65X_WKUP_IOPAD(0x0078, PIN_INPUT, 7) - >; - }; - - a4_gpio_pullup: a4-gpio-pullup-pins { - pinctrl-single,pins = < - /* (L2) WKUP_GPIO0_42 */ - AM65X_WKUP_IOPAD(0x0078, PIN_INPUT, 7) - >; - }; - - a4_gpio_pulldown: a4-gpio-pulldown-pins { - pinctrl-single,pins = < - /* (L2) WKUP_GPIO0_42 */ - AM65X_WKUP_IOPAD(0x0078, PIN_INPUT_PULLDOWN, 7) - >; - }; - - a5_gpio: a5-gpio-pins { - pinctrl-single,pins = < - /* (N5) WKUP_GPIO0_35 */ - AM65X_WKUP_IOPAD(0x005C, PIN_INPUT, 7) - >; - }; - - a5_gpio_pullup: a5-gpio-pullup-pins { - pinctrl-single,pins = < - /* (N5) WKUP_GPIO0_35 */ - AM65X_WKUP_IOPAD(0x005C, PIN_INPUT_PULLUP, 7) - >; - }; - - a5_gpio_pulldown: a5-gpio-pulldown-pins { - pinctrl-single,pins = < - /* (N5) WKUP_GPIO0_35 */ - AM65X_WKUP_IOPAD(0x005C, PIN_INPUT_PULLDOWN, 7) - >; - }; - - wkup_i2c0_pins_default: wkup-i2c0-default-pins { - pinctrl-single,pins = < - /* (AC7) WKUP_I2C0_SCL */ - AM65X_WKUP_IOPAD(0x00e0, PIN_INPUT, 0) - /* (AD6) WKUP_I2C0_SDA */ - AM65X_WKUP_IOPAD(0x00e4, PIN_INPUT, 0) - >; - }; - mcu_i2c0_pins_default: mcu-i2c0-default-pins { pinctrl-single,pins = < /* (AD8) MCU_I2C0_SCL */ @@ -623,13 +220,6 @@ >; }; - arduino_i2c_aio_switch_pins_default: arduino-i2c-aio-switch-default-pins { - pinctrl-single,pins = < - /* (R2) WKUP_GPIO0_21 */ - AM65X_WKUP_IOPAD(0x0024, PIN_OUTPUT, 7) - >; - }; - push_button_pins_default: push-button-default-pins { pinctrl-single,pins = < /* (T1) MCU_OSPI1_CLK.WKUP_GPIO0_25 */ @@ -637,22 +227,6 @@ >; }; - - arduino_io_oe_pins_default: arduino-io-oe-default-pins { - pinctrl-single,pins = < - /* (N4) WKUP_GPIO0_34 */ - AM65X_WKUP_IOPAD(0x0058, PIN_OUTPUT, 7) - /* (M2) WKUP_GPIO0_36 */ - AM65X_WKUP_IOPAD(0x0060, PIN_OUTPUT, 7) - /* (M3) WKUP_GPIO0_37 */ - AM65X_WKUP_IOPAD(0x0064, PIN_OUTPUT, 7) - /* (M4) WKUP_GPIO0_38 */ - AM65X_WKUP_IOPAD(0x0068, PIN_OUTPUT, 7) - /* (M1) WKUP_GPIO0_41 */ - AM65X_WKUP_IOPAD(0x0074, PIN_OUTPUT, 7) - >; - }; - mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins { pinctrl-single,pins = < /* (V1) MCU_OSPI0_CLK */ @@ -716,214 +290,6 @@ }; &main_pmx0 { - pinctrl-names = - "default", - "d4-ehrpwm0-a", "d4-gpio", "d4-gpio-pullup", "d4-gpio-pulldown", - "d5-ehrpwm1-a", "d5-gpio", "d5-gpio-pullup", "d5-gpio-pulldown", - "d6-ehrpwm2-a", "d6-gpio", "d6-gpio-pullup", "d6-gpio-pulldown", - "d7-ehrpwm3-a", "d7-gpio", "d7-gpio-pullup", "d7-gpio-pulldown", - "d8-ehrpwm4-a", "d8-gpio", "d8-gpio-pullup", "d8-gpio-pulldown", - "d9-ehrpwm5-a", "d9-gpio", "d9-gpio-pullup", "d9-gpio-pulldown"; - - pinctrl-0 = <&d4_ehrpwm0_a>; - pinctrl-1 = <&d4_ehrpwm0_a>; - pinctrl-2 = <&d4_gpio>; - pinctrl-3 = <&d4_gpio_pullup>; - pinctrl-4 = <&d4_gpio_pulldown>; - - pinctrl-5 = <&d5_ehrpwm1_a>; - pinctrl-6 = <&d5_gpio>; - pinctrl-7 = <&d5_gpio_pullup>; - pinctrl-8 = <&d5_gpio_pulldown>; - - pinctrl-9 = <&d6_ehrpwm2_a>; - pinctrl-10 = <&d6_gpio>; - pinctrl-11 = <&d6_gpio_pullup>; - pinctrl-12 = <&d6_gpio_pulldown>; - - pinctrl-13 = <&d7_ehrpwm3_a>; - pinctrl-14 = <&d7_gpio>; - pinctrl-15 = <&d7_gpio_pullup>; - pinctrl-16 = <&d7_gpio_pulldown>; - - pinctrl-17 = <&d8_ehrpwm4_a>; - pinctrl-18 = <&d8_gpio>; - pinctrl-19 = <&d8_gpio_pullup>; - pinctrl-20 = <&d8_gpio_pulldown>; - - pinctrl-21 = <&d9_ehrpwm5_a>; - pinctrl-22 = <&d9_gpio>; - pinctrl-23 = <&d9_gpio_pullup>; - pinctrl-24 = <&d9_gpio_pulldown>; - - d4_ehrpwm0_a: d4-ehrpwm0-a-pins { - pinctrl-single,pins = < - /* (AG18) EHRPWM0_A */ - AM65X_IOPAD(0x0084, PIN_OUTPUT, 5) - >; - }; - - d4_gpio: d4-gpio-pins { - pinctrl-single,pins = < - /* (AG18) GPIO0_33 */ - AM65X_IOPAD(0x0084, PIN_INPUT, 7) - >; - }; - - d4_gpio_pullup: d4-gpio-pullup-pins { - pinctrl-single,pins = < - /* (AG18) GPIO0_33 */ - AM65X_IOPAD(0x0084, PIN_INPUT_PULLUP, 7) - >; - }; - - d4_gpio_pulldown: d4-gpio-pulldown-pins { - pinctrl-single,pins = < - /* (AG18) GPIO0_33 */ - AM65X_IOPAD(0x0084, PIN_INPUT_PULLDOWN, 7) - >; - }; - - d5_ehrpwm1_a: d5-ehrpwm1-a-pins { - pinctrl-single,pins = < - /* (AF17) EHRPWM1_A */ - AM65X_IOPAD(0x008C, PIN_OUTPUT, 5) - >; - }; - - d5_gpio: d5-gpio-pins { - pinctrl-single,pins = < - /* (AF17) GPIO0_35 */ - AM65X_IOPAD(0x008C, PIN_INPUT, 7) - >; - }; - - d5_gpio_pullup: d5-gpio-pullup-pins { - pinctrl-single,pins = < - /* (AF17) GPIO0_35 */ - AM65X_IOPAD(0x008C, PIN_INPUT_PULLUP, 7) - >; - }; - - d5_gpio_pulldown: d5-gpio-pulldown-pins { - pinctrl-single,pins = < - /* (AF17) GPIO0_35 */ - AM65X_IOPAD(0x008C, PIN_INPUT_PULLDOWN, 7) - >; - }; - - d6_ehrpwm2_a: d6-ehrpwm2-a-pins { - pinctrl-single,pins = < - /* (AH16) EHRPWM2_A */ - AM65X_IOPAD(0x0098, PIN_OUTPUT, 5) - >; - }; - - d6_gpio: d6-gpio-pins { - pinctrl-single,pins = < - /* (AH16) GPIO0_38 */ - AM65X_IOPAD(0x0098, PIN_INPUT, 7) - >; - }; - - d6_gpio_pullup: d6-gpio-pullup-pins { - pinctrl-single,pins = < - /* (AH16) GPIO0_38 */ - AM65X_IOPAD(0x0098, PIN_INPUT_PULLUP, 7) - >; - }; - - d6_gpio_pulldown: d6-gpio-pulldown-pins { - pinctrl-single,pins = < - /* (AH16) GPIO0_38 */ - AM65X_IOPAD(0x0098, PIN_INPUT_PULLDOWN, 7) - >; - }; - - d7_ehrpwm3_a: d7-ehrpwm3-a-pins { - pinctrl-single,pins = < - /* (AH15) EHRPWM3_A */ - AM65X_IOPAD(0x00AC, PIN_OUTPUT, 5) - >; - }; - - d7_gpio: d7-gpio-pins { - pinctrl-single,pins = < - /* (AH15) GPIO0_43 */ - AM65X_IOPAD(0x00AC, PIN_INPUT, 7) - >; - }; - - d7_gpio_pullup: d7-gpio-pullup-pins { - pinctrl-single,pins = < - /* (AH15) GPIO0_43 */ - AM65X_IOPAD(0x00AC, PIN_INPUT_PULLUP, 7) - >; - }; - - d7_gpio_pulldown: d7-gpio-pulldown-pins { - pinctrl-single,pins = < - /* (AH15) GPIO0_43 */ - AM65X_IOPAD(0x00AC, PIN_INPUT_PULLDOWN, 7) - >; - }; - - d8_ehrpwm4_a: d8-ehrpwm4-a-pins { - pinctrl-single,pins = < - /* (AG15) EHRPWM4_A */ - AM65X_IOPAD(0x00C0, PIN_OUTPUT, 5) - >; - }; - - d8_gpio: d8-gpio-pins { - pinctrl-single,pins = < - /* (AG15) GPIO0_48 */ - AM65X_IOPAD(0x00C0, PIN_INPUT, 7) - >; - }; - - d8_gpio_pullup: d8-gpio-pullup-pins { - pinctrl-single,pins = < - /* (AG15) GPIO0_48 */ - AM65X_IOPAD(0x00C0, PIN_INPUT_PULLUP, 7) - >; - }; - - d8_gpio_pulldown: d8-gpio-pulldown-pins { - pinctrl-single,pins = < - /* (AG15) GPIO0_48 */ - AM65X_IOPAD(0x00C0, PIN_INPUT_PULLDOWN, 7) - >; - }; - - d9_ehrpwm5_a: d9-ehrpwm5-a-pins { - pinctrl-single,pins = < - /* (AD15) EHRPWM5_A */ - AM65X_IOPAD(0x00CC, PIN_OUTPUT, 5) - >; - }; - - d9_gpio: d9-gpio-pins { - pinctrl-single,pins = < - /* (AD15) GPIO0_51 */ - AM65X_IOPAD(0x00CC, PIN_INPUT, 7) - >; - }; - - d9_gpio_pullup: d9-gpio-pullup-pins { - pinctrl-single,pins = < - /* (AD15) GPIO0_51 */ - AM65X_IOPAD(0x00CC, PIN_INPUT_PULLUP, 7) - >; - }; - - d9_gpio_pulldown: d9-gpio-pulldown-pins { - pinctrl-single,pins = < - /* (AD15) GPIO0_51 */ - AM65X_IOPAD(0x00CC, PIN_INPUT_PULLDOWN, 7) - >; - }; - main_pcie_enable_pins_default: main-pcie-enable-default-pins { pinctrl-single,pins = < AM65X_IOPAD(0x01c4, PIN_INPUT_PULLUP, 7) /* (AH13) GPIO1_17 */ @@ -971,45 +337,6 @@ >; }; - dss_vout1_pins_default: dss-vout1-default-pins { - pinctrl-single,pins = < - AM65X_IOPAD(0x0000, PIN_OUTPUT, 1) /* VOUT1_DATA0 */ - AM65X_IOPAD(0x0004, PIN_OUTPUT, 1) /* VOUT1_DATA1 */ - AM65X_IOPAD(0x0008, PIN_OUTPUT, 1) /* VOUT1_DATA2 */ - AM65X_IOPAD(0x000c, PIN_OUTPUT, 1) /* VOUT1_DATA3 */ - AM65X_IOPAD(0x0010, PIN_OUTPUT, 1) /* VOUT1_DATA4 */ - AM65X_IOPAD(0x0014, PIN_OUTPUT, 1) /* VOUT1_DATA5 */ - AM65X_IOPAD(0x0018, PIN_OUTPUT, 1) /* VOUT1_DATA6 */ - AM65X_IOPAD(0x001c, PIN_OUTPUT, 1) /* VOUT1_DATA7 */ - AM65X_IOPAD(0x0020, PIN_OUTPUT, 1) /* VOUT1_DATA8 */ - AM65X_IOPAD(0x0024, PIN_OUTPUT, 1) /* VOUT1_DATA9 */ - AM65X_IOPAD(0x0028, PIN_OUTPUT, 1) /* VOUT1_DATA10 */ - AM65X_IOPAD(0x002c, PIN_OUTPUT, 1) /* VOUT1_DATA11 */ - AM65X_IOPAD(0x0030, PIN_OUTPUT, 1) /* VOUT1_DATA12 */ - AM65X_IOPAD(0x0034, PIN_OUTPUT, 1) /* VOUT1_DATA13 */ - AM65X_IOPAD(0x0038, PIN_OUTPUT, 1) /* VOUT1_DATA14 */ - AM65X_IOPAD(0x003c, PIN_OUTPUT, 1) /* VOUT1_DATA15 */ - AM65X_IOPAD(0x0040, PIN_OUTPUT, 1) /* VOUT1_DATA16 */ - AM65X_IOPAD(0x0044, PIN_OUTPUT, 1) /* VOUT1_DATA17 */ - AM65X_IOPAD(0x0048, PIN_OUTPUT, 1) /* VOUT1_DATA18 */ - AM65X_IOPAD(0x004c, PIN_OUTPUT, 1) /* VOUT1_DATA19 */ - AM65X_IOPAD(0x0050, PIN_OUTPUT, 1) /* VOUT1_DATA20 */ - AM65X_IOPAD(0x0054, PIN_OUTPUT, 1) /* VOUT1_DATA21 */ - AM65X_IOPAD(0x0058, PIN_OUTPUT, 1) /* VOUT1_DATA22 */ - AM65X_IOPAD(0x005c, PIN_OUTPUT, 1) /* VOUT1_DATA23 */ - AM65X_IOPAD(0x0060, PIN_OUTPUT, 1) /* VOUT1_VSYNC */ - AM65X_IOPAD(0x0064, PIN_OUTPUT, 1) /* VOUT1_HSYNC */ - AM65X_IOPAD(0x0068, PIN_OUTPUT, 1) /* VOUT1_PCLK */ - AM65X_IOPAD(0x006c, PIN_OUTPUT, 1) /* VOUT1_DE */ - >; - }; - - dp_pins_default: dp-default-pins { - pinctrl-single,pins = < - AM65X_IOPAD(0x0078, PIN_OUTPUT, 7) /* (AF18) DP rst_n */ - >; - }; - main_i2c2_pins_default: main-i2c2-default-pins { pinctrl-single,pins = < AM65X_IOPAD(0x0074, PIN_INPUT, 5) /* (T27) I2C2_SCL */ @@ -1082,57 +409,11 @@ pinctrl-0 = <&main_uart1_pins_default>; }; -&mcu_uart0 { - status = "okay"; -}; - -&main_gpio0 { - gpio-line-names = - "main_gpio0-base", "", "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", "", "", - "", "", "", "IO4", "", "IO5", "", "", "IO6", "", - "", "", "", "IO7", "", "", "", "", "IO8", "", - "", "IO9"; -}; - &main_gpio1 { pinctrl-names = "default"; pinctrl-0 = <&main_pcie_enable_pins_default>; }; -&wkup_gpio0 { - pinctrl-names = "default"; - pinctrl-0 = - <&arduino_i2c_aio_switch_pins_default>, - <&arduino_io_oe_pins_default>, - <&push_button_pins_default>, - <&db9_com_mode_pins_default>; - gpio-line-names = - /* 0..9 */ - "wkup_gpio0-base", "", "", "", "UART0-mode1", "UART0-mode0", - "UART0-enable", "UART0-terminate", "", "WIFI-disable", - /* 10..19 */ - "", "", "", "", "", "", "", "", "", "", - /* 20..29 */ - "", "A4A5-I2C-mux", "", "", "", "USER-button", "", "", "","IO0", - /* 30..39 */ - "IO1", "IO2", "", "IO3", "IO17-direction", "A5", - "IO16-direction", "IO15-direction", "IO14-direction", "A3", - /* 40..49 */ - "", "IO18-direction", "A4", "A2", "A1", "A0", "", "", "IO13", - "IO11", - /* 50..51 */ - "IO12", "IO10"; -}; - -&wkup_i2c0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&wkup_i2c0_pins_default>; - clock-frequency = <400000>; -}; - &mcu_i2c0 { status = "okay"; pinctrl-names = "default"; @@ -1150,47 +431,6 @@ ti,vsel1-state-high; ti,enable-vout-discharge; }; - - /* D4200 */ - pcal9535_1: gpio@20 { - compatible = "nxp,pcal9535"; - reg = <0x20>; - #gpio-cells = <2>; - gpio-controller; - gpio-line-names = - "A0-pull", "A1-pull", "A2-pull", "A3-pull", "A4-pull", - "A5-pull", "", "", - "IO14-enable", "IO15-enable", "IO16-enable", - "IO17-enable", "IO18-enable", "IO19-enable"; - }; - - /* D4201 */ - pcal9535_2: gpio@21 { - compatible = "nxp,pcal9535"; - reg = <0x21>; - #gpio-cells = <2>; - gpio-controller; - gpio-line-names = - "IO0-direction", "IO1-direction", "IO2-direction", - "IO3-direction", "IO4-direction", "IO5-direction", - "IO6-direction", "IO7-direction", - "IO8-direction", "IO9-direction", "IO10-direction", - "IO11-direction", "IO12-direction", "IO13-direction", - "IO19-direction"; - }; - - /* D4202 */ - pcal9535_3: gpio@25 { - compatible = "nxp,pcal9535"; - reg = <0x25>; - #gpio-cells = <2>; - gpio-controller; - gpio-line-names = - "IO0-pull", "IO1-pull", "IO2-pull", "IO3-pull", - "IO4-pull", "IO5-pull", "IO6-pull", "IO7-pull", - "IO8-pull", "IO9-pull", "IO10-pull", "IO11-pull", - "IO12-pull", "IO13-pull"; - }; }; &main_i2c0 { @@ -1233,32 +473,6 @@ #address-cells = <1>; #size-cells = <0>; - - edp-bridge@f { - compatible = "toshiba,tc358767"; - reg = <0x0f>; - pinctrl-names = "default"; - pinctrl-0 = <&dp_pins_default>; - reset-gpios = <&main_gpio0 30 GPIO_ACTIVE_HIGH>; - - clock-names = "ref"; - clocks = <&dp_refclk>; - - toshiba,hpd-pin = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - - bridge_in: endpoint { - remote-endpoint = <&dpi_out>; - }; - }; - }; - }; }; &mcu_cpsw { @@ -1292,13 +506,6 @@ ti,pindir-d0-out-d1-in; }; -&tscadc1 { - status = "okay"; - adc { - ti,adc-channels = <0 1 2 3 4 5>; - }; -}; - &ospi0 { status = "okay"; pinctrl-names = "default"; @@ -1364,26 +571,6 @@ }; }; -&dss { - pinctrl-names = "default"; - pinctrl-0 = <&dss_vout1_pins_default>; - - assigned-clocks = <&k3_clks 67 2>; - assigned-clock-parents = <&k3_clks 67 5>; -}; - -&dss_ports { - #address-cells = <1>; - #size-cells = <0>; - port@1 { - reg = <1>; - - dpi_out: endpoint { - remote-endpoint = <&bridge_in>; - }; - }; -}; - &pcie1_rc { status = "okay"; pinctrl-names = "default"; @@ -1418,13 +605,17 @@ &mcu_r5fss0_core0 { memory-region = <&mcu_r5fss0_core0_dma_memory_region>, <&mcu_r5fss0_core0_memory_region>; - mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>; + mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; }; &mcu_r5fss0_core1 { memory-region = <&mcu_r5fss0_core1_dma_memory_region>, <&mcu_r5fss0_core1_memory_region>; - mboxes = <&mailbox0_cluster1>, <&mbox_mcu_r5fss0_core1>; + mboxes = <&mailbox0_cluster1 &mbox_mcu_r5fss0_core1>; +}; + +&mcu_rti1 { + memory-region = <&wdt_reset_memory_region>; }; &icssg0_mdio { diff --git a/src/arm64/ti/k3-am65-iot2050-dp.dtsi b/src/arm64/ti/k3-am65-iot2050-dp.dtsi new file mode 100644 index 0000000..984cc80 --- /dev/null +++ b/src/arm64/ti/k3-am65-iot2050-dp.dtsi @@ -0,0 +1,98 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Siemens AG, 2024 + * + * Authors: + * Jan Kiszka <jan.kiszka@siemens.com> + * + * Common bits for IOT2050 variants with Display Port + */ + +&main_pmx0 { + dss_vout1_pins_default: dss-vout1-default-pins { + pinctrl-single,pins = < + AM65X_IOPAD(0x0000, PIN_OUTPUT, 1) /* VOUT1_DATA0 */ + AM65X_IOPAD(0x0004, PIN_OUTPUT, 1) /* VOUT1_DATA1 */ + AM65X_IOPAD(0x0008, PIN_OUTPUT, 1) /* VOUT1_DATA2 */ + AM65X_IOPAD(0x000c, PIN_OUTPUT, 1) /* VOUT1_DATA3 */ + AM65X_IOPAD(0x0010, PIN_OUTPUT, 1) /* VOUT1_DATA4 */ + AM65X_IOPAD(0x0014, PIN_OUTPUT, 1) /* VOUT1_DATA5 */ + AM65X_IOPAD(0x0018, PIN_OUTPUT, 1) /* VOUT1_DATA6 */ + AM65X_IOPAD(0x001c, PIN_OUTPUT, 1) /* VOUT1_DATA7 */ + AM65X_IOPAD(0x0020, PIN_OUTPUT, 1) /* VOUT1_DATA8 */ + AM65X_IOPAD(0x0024, PIN_OUTPUT, 1) /* VOUT1_DATA9 */ + AM65X_IOPAD(0x0028, PIN_OUTPUT, 1) /* VOUT1_DATA10 */ + AM65X_IOPAD(0x002c, PIN_OUTPUT, 1) /* VOUT1_DATA11 */ + AM65X_IOPAD(0x0030, PIN_OUTPUT, 1) /* VOUT1_DATA12 */ + AM65X_IOPAD(0x0034, PIN_OUTPUT, 1) /* VOUT1_DATA13 */ + AM65X_IOPAD(0x0038, PIN_OUTPUT, 1) /* VOUT1_DATA14 */ + AM65X_IOPAD(0x003c, PIN_OUTPUT, 1) /* VOUT1_DATA15 */ + AM65X_IOPAD(0x0040, PIN_OUTPUT, 1) /* VOUT1_DATA16 */ + AM65X_IOPAD(0x0044, PIN_OUTPUT, 1) /* VOUT1_DATA17 */ + AM65X_IOPAD(0x0048, PIN_OUTPUT, 1) /* VOUT1_DATA18 */ + AM65X_IOPAD(0x004c, PIN_OUTPUT, 1) /* VOUT1_DATA19 */ + AM65X_IOPAD(0x0050, PIN_OUTPUT, 1) /* VOUT1_DATA20 */ + AM65X_IOPAD(0x0054, PIN_OUTPUT, 1) /* VOUT1_DATA21 */ + AM65X_IOPAD(0x0058, PIN_OUTPUT, 1) /* VOUT1_DATA22 */ + AM65X_IOPAD(0x005c, PIN_OUTPUT, 1) /* VOUT1_DATA23 */ + AM65X_IOPAD(0x0060, PIN_OUTPUT, 1) /* VOUT1_VSYNC */ + AM65X_IOPAD(0x0064, PIN_OUTPUT, 1) /* VOUT1_HSYNC */ + AM65X_IOPAD(0x0068, PIN_OUTPUT, 1) /* VOUT1_PCLK */ + AM65X_IOPAD(0x006c, PIN_OUTPUT, 1) /* VOUT1_DE */ + >; + }; + + dp_pins_default: dp-default-pins { + pinctrl-single,pins = < + AM65X_IOPAD(0x0078, PIN_OUTPUT, 7) /* (AF18) DP rst_n */ + >; + }; +}; + +&main_i2c3 { + edp-bridge@f { + compatible = "toshiba,tc358767"; + reg = <0x0f>; + pinctrl-names = "default"; + pinctrl-0 = <&dp_pins_default>; + reset-gpios = <&main_gpio0 30 GPIO_ACTIVE_HIGH>; + + clock-names = "ref"; + clocks = <&dp_refclk>; + + toshiba,hpd-pin = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + bridge_in: endpoint { + remote-endpoint = <&dpi_out>; + }; + }; + }; + }; +}; + +&dss { + pinctrl-names = "default"; + pinctrl-0 = <&dss_vout1_pins_default>; + + assigned-clocks = <&k3_clks 67 2>; + assigned-clock-parents = <&k3_clks 67 5>; +}; + +&dss_ports { + #address-cells = <1>; + #size-cells = <0>; + port@1 { + reg = <1>; + + dpi_out: endpoint { + remote-endpoint = <&bridge_in>; + }; + }; +}; diff --git a/src/arm64/ti/k3-am65-iot2050-usb3.dtsi b/src/arm64/ti/k3-am65-iot2050-usb3.dtsi new file mode 100644 index 0000000..e5bd7c3 --- /dev/null +++ b/src/arm64/ti/k3-am65-iot2050-usb3.dtsi @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Siemens AG, 2024 + * + * Authors: + * Jan Kiszka <jan.kiszka@siemens.com> + * + * Common bits for IOT2050 variants with USB3 support + */ + +&serdes0 { + assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>; + assigned-clock-parents = <&k3_clks 153 7>, <&k3_clks 153 4>; +}; + +&dwc3_0 { + assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */ + <&k3_clks 151 8>; /* set PIPE3_TXB_CLK to WIZ8B2M4VSB */ + phys = <&serdes0 PHY_TYPE_USB3 0>; + phy-names = "usb3-phy"; +}; + +&usb0 { + maximum-speed = "super-speed"; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; +}; diff --git a/src/arm64/ti/k3-am65-main.dtsi b/src/arm64/ti/k3-am65-main.dtsi index fcea544..ff85711 100644 --- a/src/arm64/ti/k3-am65-main.dtsi +++ b/src/arm64/ti/k3-am65-main.dtsi @@ -1,8 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree Source for AM6 SoC Family Main Domain peripherals * - * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/ */ #include <dt-bindings/phy/phy-am654-serdes.h> @@ -886,20 +886,6 @@ status = "disabled"; }; - pcie0_ep: pcie-ep@5500000 { - compatible = "ti,am654-pcie-ep"; - reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x8000000>, <0x0 0x5506000 0x0 0x1000>; - reg-names = "app", "dbics", "addr_space", "atu"; - power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>; - ti,syscon-pcie-mode = <&scm_conf 0x4060>; - num-ib-windows = <16>; - num-ob-windows = <16>; - max-link-speed = <2>; - dma-coherent; - interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>; - status = "disabled"; - }; - pcie1_rc: pcie@5600000 { compatible = "ti,am654-pcie-rc"; reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x2000>, <0x0 0x5606000 0x0 0x1000>; @@ -921,20 +907,6 @@ status = "disabled"; }; - pcie1_ep: pcie-ep@5600000 { - compatible = "ti,am654-pcie-ep"; - reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x4000000>, <0x0 0x5606000 0x0 0x1000>; - reg-names = "app", "dbics", "addr_space", "atu"; - power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>; - ti,syscon-pcie-mode = <&scm_conf 0x4070>; - num-ib-windows = <16>; - num-ob-windows = <16>; - max-link-speed = <2>; - dma-coherent; - interrupts = <GIC_SPI 355 IRQ_TYPE_EDGE_RISING>; - status = "disabled"; - }; - mcasp0: mcasp@2b00000 { compatible = "ti,am33xx-mcasp-audio"; reg = <0x0 0x02b00000 0x0 0x2000>, @@ -1019,9 +991,10 @@ <0x0 0x04a07000 0x0 0x1000>, /* ovr1 */ <0x0 0x04a08000 0x0 0x1000>, /* ovr2 */ <0x0 0x04a0a000 0x0 0x1000>, /* vp1 */ - <0x0 0x04a0b000 0x0 0x1000>; /* vp2 */ + <0x0 0x04a0b000 0x0 0x1000>, /* vp2 */ + <0x0 0x04a01000 0x0 0x1000>; /* common1 */ reg-names = "common", "vidl1", "vid", - "ovr1", "ovr2", "vp1", "vp2"; + "ovr1", "ovr2", "vp1", "vp2", "common1"; ti,am65x-oldi-io-ctrl = <&dss_oldi_io_ctrl>; @@ -1050,6 +1023,13 @@ }; }; + gpu: gpu@7000000 { + compatible = "ti,am6548-gpu", "img,powervr-sgx544"; + reg = <0x0 0x7000000 0x0 0x10000>; + interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&k3_pds 65 TI_SCI_PD_EXCLUSIVE>; + }; + ehrpwm0: pwm@3000000 { compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; #pwm-cells = <3>; diff --git a/src/arm64/ti/k3-am65-mcu.dtsi b/src/arm64/ti/k3-am65-mcu.dtsi index ecd7356..6ff3ccc 100644 --- a/src/arm64/ti/k3-am65-mcu.dtsi +++ b/src/arm64/ti/k3-am65-mcu.dtsi @@ -1,8 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree Source for AM6 SoC Family MCU Domain peripherals * - * Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/ */ &cbass_mcu { diff --git a/src/arm64/ti/k3-am65-wakeup.dtsi b/src/arm64/ti/k3-am65-wakeup.dtsi index f037b36..3752789 100644 --- a/src/arm64/ti/k3-am65-wakeup.dtsi +++ b/src/arm64/ti/k3-am65-wakeup.dtsi @@ -1,8 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree Source for AM6 SoC Family Wakeup Domain peripherals * - * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/ */ &cbass_wakeup { diff --git a/src/arm64/ti/k3-am65.dtsi b/src/arm64/ti/k3-am65.dtsi index 4d7b615..c59baeb 100644 --- a/src/arm64/ti/k3-am65.dtsi +++ b/src/arm64/ti/k3-am65.dtsi @@ -1,8 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree Source for AM6 SoC Family * - * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/ */ #include <dt-bindings/gpio/gpio.h> diff --git a/src/arm64/ti/k3-am652.dtsi b/src/arm64/ti/k3-am652.dtsi index 0f22e00..cbb3caa 100644 --- a/src/arm64/ti/k3-am652.dtsi +++ b/src/arm64/ti/k3-am652.dtsi @@ -1,8 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree Source for AM65 SoC family in Dual core configuration * - * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ */ #include "k3-am65.dtsi" diff --git a/src/arm64/ti/k3-am6528-iot2050-basic-common.dtsi b/src/arm64/ti/k3-am6528-iot2050-basic-common.dtsi index 1d6cddb..eed6fe7 100644 --- a/src/arm64/ti/k3-am6528-iot2050-basic-common.dtsi +++ b/src/arm64/ti/k3-am6528-iot2050-basic-common.dtsi @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) Siemens AG, 2018-2021 * @@ -11,6 +11,7 @@ #include "k3-am652.dtsi" #include "k3-am65-iot2050-common.dtsi" +#include "k3-am65-iot2050-arduino-connector.dtsi" / { memory@80000000 { @@ -40,8 +41,3 @@ pinctrl-names = "default"; pinctrl-0 = <&main_uart0_pins_default>; }; - -&mcu_r5fss0 { - /* lock-step mode not supported on Basic boards */ - ti,cluster-mode = <0>; -}; diff --git a/src/arm64/ti/k3-am6528-iot2050-basic-pg2.dts b/src/arm64/ti/k3-am6528-iot2050-basic-pg2.dts index c62549a..c1faf94 100644 --- a/src/arm64/ti/k3-am6528-iot2050-basic-pg2.dts +++ b/src/arm64/ti/k3-am6528-iot2050-basic-pg2.dts @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) Siemens AG, 2018-2021 * @@ -17,6 +17,8 @@ #include "k3-am6528-iot2050-basic-common.dtsi" #include "k3-am65-iot2050-common-pg2.dtsi" +#include "k3-am65-iot2050-dp.dtsi" +#include "k3-am65-iot2050-usb3.dtsi" / { compatible = "siemens,iot2050-basic-pg2", "ti,am654"; diff --git a/src/arm64/ti/k3-am6528-iot2050-basic.dts b/src/arm64/ti/k3-am6528-iot2050-basic.dts index 87928ff..29a3189 100644 --- a/src/arm64/ti/k3-am6528-iot2050-basic.dts +++ b/src/arm64/ti/k3-am6528-iot2050-basic.dts @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) Siemens AG, 2018-2021 * @@ -22,3 +22,8 @@ compatible = "siemens,iot2050-basic", "ti,am654"; model = "SIMATIC IOT2050 Basic"; }; + +&mcu_r5fss0 { + /* lock-step mode not supported on this board */ + ti,cluster-mode = <0>; +}; diff --git a/src/arm64/ti/k3-am654-base-board-rocktech-rk101-panel.dtso b/src/arm64/ti/k3-am654-base-board-rocktech-rk101-panel.dtso index 3be92c3..364c57b 100644 --- a/src/arm64/ti/k3-am654-base-board-rocktech-rk101-panel.dtso +++ b/src/arm64/ti/k3-am654-base-board-rocktech-rk101-panel.dtso @@ -1,10 +1,10 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /** * OLDI-LCD1EVM Rocktech integrated panel and touch DT overlay for AM654-EVM. * Panel Link: https://www.digimax.it/en/tft-lcd/20881-RK101II01D-CT * AM654 LCD EVM: https://www.ti.com/tool/TMDSLCD1EVM * - * Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/src/arm64/ti/k3-am654-base-board.dts b/src/arm64/ti/k3-am654-base-board.dts index 822c288..aba0c52 100644 --- a/src/arm64/ti/k3-am654-base-board.dts +++ b/src/arm64/ti/k3-am654-base-board.dts @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* - * Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; @@ -531,13 +531,13 @@ &mcu_r5fss0_core0 { memory-region = <&mcu_r5fss0_core0_dma_memory_region>, <&mcu_r5fss0_core0_memory_region>; - mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>; + mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; }; &mcu_r5fss0_core1 { memory-region = <&mcu_r5fss0_core1_dma_memory_region>, <&mcu_r5fss0_core1_memory_region>; - mboxes = <&mailbox0_cluster1>, <&mbox_mcu_r5fss0_core1>; + mboxes = <&mailbox0_cluster1 &mbox_mcu_r5fss0_core1>; }; &ospi0 { diff --git a/src/arm64/ti/k3-am654-icssg2.dtso b/src/arm64/ti/k3-am654-icssg2.dtso index ec8cf20..0a6e752 100644 --- a/src/arm64/ti/k3-am654-icssg2.dtso +++ b/src/arm64/ti/k3-am654-icssg2.dtso @@ -1,8 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /** * DT overlay for IDK application board on AM654 EVM * - * Copyright (C) 2018-2023 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2018-2024 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/src/arm64/ti/k3-am654-idk.dtso b/src/arm64/ti/k3-am654-idk.dtso index 150428d..8bdb87f 100644 --- a/src/arm64/ti/k3-am654-idk.dtso +++ b/src/arm64/ti/k3-am654-idk.dtso @@ -1,8 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /** * DT overlay for IDK application board on AM654 EVM * - * Copyright (C) 2018-2023 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2018-2024 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/src/arm64/ti/k3-am654-industrial-thermal.dtsi b/src/arm64/ti/k3-am654-industrial-thermal.dtsi index 9021c73..de5a2ed 100644 --- a/src/arm64/ti/k3-am654-industrial-thermal.dtsi +++ b/src/arm64/ti/k3-am654-industrial-thermal.dtsi @@ -1,4 +1,7 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/ + */ #include <dt-bindings/thermal/thermal.h> diff --git a/src/arm64/ti/k3-am654-pcie-usb2.dtso b/src/arm64/ti/k3-am654-pcie-usb2.dtso new file mode 100644 index 0000000..c3cb752 --- /dev/null +++ b/src/arm64/ti/k3-am654-pcie-usb2.dtso @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/** + * DT overlay for SERDES personality card: 2lane PCIe + USB2.0 Host on AM654 EVM + * + * Copyright (C) 2018-2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/phy/phy.h> +#include <dt-bindings/phy/phy-am654-serdes.h> +#include "k3-pinctrl.h" + +&serdes0 { + assigned-clocks = <&k3_clks 153 4>, + <&serdes0 AM654_SERDES_CMU_REFCLK>, + <&serdes0 AM654_SERDES_RO_REFCLK>; + assigned-clock-parents = <&k3_clks 153 8>, + <&k3_clks 153 4>, + <&k3_clks 153 4>; + status = "okay"; +}; + +&serdes1 { + assigned-clocks = <&serdes1 AM654_SERDES_CMU_REFCLK>; + assigned-clock-parents = <&serdes0 AM654_SERDES_RO_REFCLK>; + status = "okay"; +}; + +&pcie0_rc { + num-lanes = <2>; + phys = <&serdes0 PHY_TYPE_PCIE 1>, <&serdes1 PHY_TYPE_PCIE 1>; + phy-names = "pcie-phy0", "pcie-phy1"; + reset-gpios = <&pca9555 5 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&main_pmx0 { + usb0_pins_default: usb0-default-pins { + pinctrl-single,pins = < + AM65X_IOPAD(0x02bc, PIN_OUTPUT, 0) /* (AD9) USB0_DRVVBUS */ + >; + }; +}; + +&dwc3_0 { + status = "okay"; +}; + +&usb0_phy { + status = "okay"; +}; + +&usb0 { + pinctrl-names = "default"; + pinctrl-0 = <&usb0_pins_default>; + dr_mode = "host"; +}; diff --git a/src/arm64/ti/k3-am654-pcie-usb3.dtso b/src/arm64/ti/k3-am654-pcie-usb3.dtso new file mode 100644 index 0000000..333e423 --- /dev/null +++ b/src/arm64/ti/k3-am654-pcie-usb3.dtso @@ -0,0 +1,61 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/** + * DT overlay for SERDES personality card: 1lane PCIe + USB3.0 DRD on AM654 EVM + * + * Copyright (C) 2018-2024 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; +/plugin/; +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/phy/phy.h> +#include <dt-bindings/phy/phy-am654-serdes.h> + +#include "k3-pinctrl.h" + +&serdes1 { + status = "okay"; +}; + +&pcie1_rc { + num-lanes = <1>; + phys = <&serdes1 PHY_TYPE_PCIE 0>; + phy-names = "pcie-phy0"; + reset-gpios = <&pca9555 5 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&main_pmx0 { + usb0_pins_default: usb0-default-pins { + pinctrl-single,pins = < + AM65X_IOPAD(0x02bc, PIN_OUTPUT, 0) /* (AD9) USB0_DRVVBUS */ + >; + }; +}; + +&serdes0 { + status = "okay"; + assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>; + assigned-clock-parents = <&k3_clks 153 7>, <&k3_clks 153 4>; +}; + +&dwc3_0 { + status = "okay"; + assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */ + <&k3_clks 151 8>; /* set PIPE3_TXB_CLK to WIZ8B2M4VSB */ + phys = <&serdes0 PHY_TYPE_USB3 0>; + phy-names = "usb3-phy"; +}; + +&usb0 { + pinctrl-names = "default"; + pinctrl-0 = <&usb0_pins_default>; + dr_mode = "host"; + maximum-speed = "super-speed"; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; +}; + +&usb0_phy { + status = "okay"; +}; diff --git a/src/arm64/ti/k3-am654.dtsi b/src/arm64/ti/k3-am654.dtsi index 888567b..bb77c84 100644 --- a/src/arm64/ti/k3-am654.dtsi +++ b/src/arm64/ti/k3-am654.dtsi @@ -1,8 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree Source for AM6 SoC family in Quad core configuration * - * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/ */ #include "k3-am65.dtsi" diff --git a/src/arm64/ti/k3-am6548-iot2050-advanced-common.dtsi b/src/arm64/ti/k3-am6548-iot2050-advanced-common.dtsi index 3864ec5..ae842b8 100644 --- a/src/arm64/ti/k3-am6548-iot2050-advanced-common.dtsi +++ b/src/arm64/ti/k3-am6548-iot2050-advanced-common.dtsi @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) Siemens AG, 2018-2021 * diff --git a/src/arm64/ti/k3-am6548-iot2050-advanced-m2.dts b/src/arm64/ti/k3-am6548-iot2050-advanced-m2.dts index bd6f2e6..cc619bb 100644 --- a/src/arm64/ti/k3-am6548-iot2050-advanced-m2.dts +++ b/src/arm64/ti/k3-am6548-iot2050-advanced-m2.dts @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) Siemens AG, 2018-2023 * @@ -15,17 +15,14 @@ #include "k3-am6548-iot2050-advanced-common.dtsi" #include "k3-am65-iot2050-common-pg2.dtsi" +#include "k3-am65-iot2050-arduino-connector.dtsi" +#include "k3-am65-iot2050-dp.dtsi" / { compatible = "siemens,iot2050-advanced-m2", "ti,am654"; model = "SIMATIC IOT2050 Advanced M2"; }; -&mcu_r5fss0 { - /* lock-step mode not supported on this board */ - ti,cluster-mode = <0>; -}; - &main_pmx0 { main_bkey_pcie_reset: main-bkey-pcie-reset-default-pins { pinctrl-single,pins = < @@ -96,16 +93,3 @@ &pcie1_rc { status = "disabled"; }; - -&dwc3_0 { - assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */ - <&k3_clks 151 9>; /* set PIPE3_TXB_CLK to CLK_12M_RC/256 (for HS only) */ - /delete-property/ phys; - /delete-property/ phy-names; -}; - -&usb0 { - maximum-speed = "high-speed"; - /delete-property/ snps,dis-u1-entry-quirk; - /delete-property/ snps,dis-u2-entry-quirk; -}; diff --git a/src/arm64/ti/k3-am6548-iot2050-advanced-pg2.dts b/src/arm64/ti/k3-am6548-iot2050-advanced-pg2.dts index f00dc86..ec72127 100644 --- a/src/arm64/ti/k3-am6548-iot2050-advanced-pg2.dts +++ b/src/arm64/ti/k3-am6548-iot2050-advanced-pg2.dts @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) Siemens AG, 2018-2021 + * Copyright (c) Siemens AG, 2018-2023 * * Authors: * Le Jin <le.jin@siemens.com> @@ -17,13 +17,11 @@ #include "k3-am6548-iot2050-advanced-common.dtsi" #include "k3-am65-iot2050-common-pg2.dtsi" +#include "k3-am65-iot2050-arduino-connector.dtsi" +#include "k3-am65-iot2050-dp.dtsi" +#include "k3-am65-iot2050-usb3.dtsi" / { compatible = "siemens,iot2050-advanced-pg2", "ti,am654"; model = "SIMATIC IOT2050 Advanced PG2"; }; - -&mcu_r5fss0 { - /* lock-step mode not supported on this board */ - ti,cluster-mode = <0>; -}; diff --git a/src/arm64/ti/k3-am6548-iot2050-advanced-sm.dts b/src/arm64/ti/k3-am6548-iot2050-advanced-sm.dts new file mode 100644 index 0000000..b829f4b --- /dev/null +++ b/src/arm64/ti/k3-am6548-iot2050-advanced-sm.dts @@ -0,0 +1,189 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Siemens AG, 2023 + * + * Authors: + * Baocheng Su <baocheng.su@siemens.com> + * Chao Zeng <chao.zeng@siemens.com> + * Huaqian Li <huaqian.li@siemens.com> + * + * AM6548-based (quad-core) IOT2050 SM variant, Product Generation 2 + * 4 GB RAM, 16 GB eMMC, USB-serial converter on connector X30 + * + * Product homepage: + * https://new.siemens.com/global/en/products/automation/pc-based/iot-gateways/simatic-iot2050.html + */ + +/dts-v1/; + +#include "k3-am6548-iot2050-advanced-common.dtsi" +#include "k3-am65-iot2050-common-pg2.dtsi" + +/ { + compatible = "siemens,iot2050-advanced-sm", "ti,am654"; + model = "SIMATIC IOT2050 Advanced SM"; + + memory@80000000 { + device_type = "memory"; + /* 4G RAM */ + reg = <0x00000000 0x80000000 0x00000000 0x80000000>, + <0x00000008 0x80000000 0x00000000 0x80000000>; + }; + + aliases { + spi1 = &main_spi0; + }; + + leds { + pinctrl-0 = <&leds_pins_default>, <&user1_led_pins>; + + led-2 { + gpios = <&wkup_gpio0 52 GPIO_ACTIVE_HIGH>; + }; + + led-3 { + gpios = <&wkup_gpio0 53 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&main_pmx0 { + main_pcie_enable_pins_default: main-pcie-enable-default-pins { + pinctrl-single,pins = < + AM65X_IOPAD(0x01d8, PIN_OUTPUT, 7) /* (AH12) GPIO1_22 */ + >; + }; + + main_spi0_pins: main-spi0-default-pins { + pinctrl-single,pins = < + AM65X_IOPAD(0x01c4, PIN_INPUT, 0) /* (AH13) SPI0_CLK */ + AM65X_IOPAD(0x01c8, PIN_INPUT, 0) /* (AE13) SPI0_D0 */ + AM65X_IOPAD(0x01cc, PIN_INPUT, 0) /* (AD13) SPI0_D1 */ + AM65X_IOPAD(0x01bc, PIN_OUTPUT, 0) /* (AG13) SPI0_CS0 */ + >; + }; +}; + +&main_pmx1 { + asic_spi_mux_ctrl_pin: asic-spi-mux-ctrl-default-pins { + pinctrl-single,pins = < + AM65X_IOPAD(0x0010, PIN_OUTPUT, 7) /* (D21) GPIO1_86 */ + >; + }; +}; + +&wkup_pmx0 { + user1_led_pins: user1-led-default-pins { + pinctrl-single,pins = < + /* (AB1) WKUP_UART0_RXD:WKUP_GPIO0_52, as USER 1 led red */ + AM65X_WKUP_IOPAD(0x00a0, PIN_OUTPUT, 7) + /* (AB5) WKUP_UART0_TXD:WKUP_GPIO0_53, as USER 1 led green */ + AM65X_WKUP_IOPAD(0x00a4, PIN_OUTPUT, 7) + >; + }; + + soc_asic_pins: soc-asic-default-pins { + pinctrl-single,pins = < + AM65X_WKUP_IOPAD(0x0044, PIN_INPUT, 7) /* (P4) WKUP_GPIO0_29 */ + AM65X_WKUP_IOPAD(0x0048, PIN_INPUT, 7) /* (P5) WKUP_GPIO0_30 */ + AM65X_WKUP_IOPAD(0x004c, PIN_INPUT, 7) /* (P1) WKUP_GPIO0_31 */ + >; + }; +}; + +&main_gpio0 { + gpio-line-names = "main_gpio0-base"; +}; + +&main_gpio1 { + pinctrl-names = "default"; + pinctrl-0 = + <&cp2102n_reset_pin_default>, + <&main_pcie_enable_pins_default>, + <&asic_spi_mux_ctrl_pin>; + gpio-line-names = + /* 0..9 */ + "", "", "", "", "", "", "", "", "", "", + /* 10..19 */ + "", "", "", "", "", "", "", "", "", "", + /* 20..29 */ + "", "", "", "", "CP2102N-RESET", "", "", "", "", "", + /* 30..39 */ + "", "", "", "", "", "", "", "", "", "", + /* 40..49 */ + "", "", "", "", "", "", "", "", "", "", + /* 50..59 */ + "", "", "", "", "", "", "", "", "", "", + /* 60..69 */ + "", "", "", "", "", "", "", "", "", "", + /* 70..79 */ + "", "", "", "", "", "", "", "", "", "", + /* 80..86 */ + "", "", "", "", "", "", "ASIC-spi-mux-ctrl"; +}; + +&wkup_gpio0 { + pinctrl-names = "default"; + pinctrl-0 = + <&push_button_pins_default>, + <&db9_com_mode_pins_default>, + <&soc_asic_pins>; + gpio-line-names = + /* 0..9 */ + "wkup_gpio0-base", "", "", "", "UART0-mode1", "UART0-mode0", + "UART0-enable", "UART0-terminate", "", "WIFI-disable", + /* 10..19 */ + "", "", "", "", "", "", "", "", "", "", + /* 20..29 */ + "", "", "", "", "", "USER-button", "", "", "","ASIC-gpio-0", + /* 30..31 */ + "ASIC-gpio-1", "ASIC-gpio-2"; +}; + +&main_spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_spi0_pins>; + + #address-cells = <1>; + #size-cells= <0>; +}; + +&mcu_spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&mcu_spi0_pins_default>; +}; + +&main_i2c3 { + accelerometer: lsm6dso@6a { + compatible = "st,lsm6dso"; + reg = <0x6a>; + }; +}; + +&dss { + status = "disabled"; +}; + +&serdes0 { + assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>; + assigned-clock-parents = <&k3_clks 153 8>, <&k3_clks 153 4>; +}; + +&serdes1 { + status = "disabled"; +}; + +&pcie0_rc { + pinctrl-names = "default"; + pinctrl-0 = <&minipcie_pins_default>; + + num-lanes = <1>; + phys = <&serdes0 PHY_TYPE_PCIE 1>; + phy-names = "pcie-phy0"; + reset-gpios = <&wkup_gpio0 27 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&pcie1_rc { + status = "disabled"; +}; diff --git a/src/arm64/ti/k3-am6548-iot2050-advanced.dts b/src/arm64/ti/k3-am6548-iot2050-advanced.dts index 077f165..649652a 100644 --- a/src/arm64/ti/k3-am6548-iot2050-advanced.dts +++ b/src/arm64/ti/k3-am6548-iot2050-advanced.dts @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) Siemens AG, 2018-2021 * @@ -17,6 +17,7 @@ #include "k3-am6548-iot2050-advanced-common.dtsi" #include "k3-am65-iot2050-common-pg1.dtsi" +#include "k3-am65-iot2050-arduino-connector.dtsi" / { compatible = "siemens,iot2050-advanced", "ti,am654"; diff --git a/src/arm64/ti/k3-am68-sk-base-board.dts b/src/arm64/ti/k3-am68-sk-base-board.dts index d0cfdea..d743f02 100644 --- a/src/arm64/ti/k3-am68-sk-base-board.dts +++ b/src/arm64/ti/k3-am68-sk-base-board.dts @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* - * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ * * Base Board: https://www.ti.com/lit/zip/SPRR463 */ @@ -169,6 +169,13 @@ }; }; }; + + csi_mux: mux-controller { + compatible = "gpio-mux"; + #mux-state-cells = <1>; + mux-gpios = <&exp3 1 GPIO_ACTIVE_HIGH>; + idle-state = <0>; + }; }; &main_pmx0 { @@ -186,6 +193,13 @@ >; }; + main_i2c1_pins_default: main-i2c1-default-pins { + pinctrl-single,pins = < + J721S2_IOPAD(0x0ac, PIN_INPUT, 13) /* (AC25) MCASP0_AXR15.I2C1_SCL */ + J721S2_IOPAD(0x0b0, PIN_INPUT, 13) /* (AD26) MCASP1_AXR3.I2C1_SDA */ + >; + }; + main_mmc1_pins_default: main-mmc1-default-pins { pinctrl-single,pins = < J721S2_IOPAD(0x104, PIN_INPUT, 0) /* (P23) MMC1_CLK */ @@ -431,6 +445,42 @@ }; }; +&main_i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c1_pins_default>; + status = "okay"; + + exp3: gpio@20 { + compatible = "ti,tca6408"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "CSI_VIO_SEL", "CSI_SEL_FPC_EXPn", + "IO_EXP_CSI2_EXP_RSTz","CSI0_B_GPIO1", + "CSI1_B_GPIO1"; + }; + + i2c-mux@70 { + compatible = "nxp,pca9543"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + + cam0_i2c: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + cam1_i2c: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + }; +}; + &main_i2c4 { status = "okay"; pinctrl-names = "default"; diff --git a/src/arm64/ti/k3-am68-sk-som.dtsi b/src/arm64/ti/k3-am68-sk-som.dtsi index 20861a0..0f4a5da 100644 --- a/src/arm64/ti/k3-am68-sk-som.dtsi +++ b/src/arm64/ti/k3-am68-sk-som.dtsi @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* - * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; @@ -209,51 +209,51 @@ }; &mcu_r5fss0_core0 { - mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>; + mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; memory-region = <&mcu_r5fss0_core0_dma_memory_region>, <&mcu_r5fss0_core0_memory_region>; }; &mcu_r5fss0_core1 { - mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>; + mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; memory-region = <&mcu_r5fss0_core1_dma_memory_region>, <&mcu_r5fss0_core1_memory_region>; }; &main_r5fss0_core0 { - mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>; + mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; memory-region = <&main_r5fss0_core0_dma_memory_region>, <&main_r5fss0_core0_memory_region>; }; &main_r5fss0_core1 { - mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>; + mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; memory-region = <&main_r5fss0_core1_dma_memory_region>, <&main_r5fss0_core1_memory_region>; }; &main_r5fss1_core0 { - mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core0>; + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; memory-region = <&main_r5fss1_core0_dma_memory_region>, <&main_r5fss1_core0_memory_region>; }; &main_r5fss1_core1 { - mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core1>; + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; memory-region = <&main_r5fss1_core1_dma_memory_region>, <&main_r5fss1_core1_memory_region>; }; &c71_0 { status = "okay"; - mboxes = <&mailbox0_cluster4>, <&mbox_c71_0>; + mboxes = <&mailbox0_cluster4 &mbox_c71_0>; memory-region = <&c71_0_dma_memory_region>, <&c71_0_memory_region>; }; &c71_1 { status = "okay"; - mboxes = <&mailbox0_cluster4>, <&mbox_c71_1>; + mboxes = <&mailbox0_cluster4 &mbox_c71_1>; memory-region = <&c71_1_dma_memory_region>, <&c71_1_memory_region>; }; diff --git a/src/arm64/ti/k3-am69-sk.dts b/src/arm64/ti/k3-am69-sk.dts index 8da5915..50de2a4 100644 --- a/src/arm64/ti/k3-am69-sk.dts +++ b/src/arm64/ti/k3-am69-sk.dts @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* - * Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/ * * Design Files: https://www.ti.com/lit/zip/SPRR466 * TRM: https://www.ti.com/lit/zip/spruj52 @@ -33,6 +33,7 @@ memory@80000000 { device_type = "memory"; + bootph-all; /* 32G RAM */ reg = <0x00 0x80000000 0x00 0x80000000>, <0x08 0x80000000 0x07 0x80000000>; @@ -321,6 +322,38 @@ }; }; }; + + csi_mux: mux-controller { + compatible = "gpio-mux"; + #mux-state-cells = <1>; + mux-gpios = <&exp2 1 GPIO_ACTIVE_HIGH>; + idle-state = <0>; + }; + + transceiver1: can-phy0 { + compatible = "ti,tcan1042"; + #phy-cells = <0>; + max-bitrate = <5000000>; + }; + + transceiver2: can-phy1 { + compatible = "ti,tcan1042"; + #phy-cells = <0>; + max-bitrate = <5000000>; + }; + + transceiver3: can-phy2 { + compatible = "ti,tcan1042"; + #phy-cells = <0>; + max-bitrate = <5000000>; + }; + + transceiver4: can-phy3 { + compatible = "ti,tcan1042"; + #phy-cells = <0>; + max-bitrate = <5000000>; + }; + }; &main_pmx0 { @@ -340,6 +373,13 @@ >; }; + main_i2c1_pins_default: main-i2c1-default-pins { + pinctrl-single,pins = < + J784S4_IOPAD(0x0ac, PIN_INPUT_PULLUP, 13) /* (AE34) MCASP0_AXR15.I2C1_SCL */ + J784S4_IOPAD(0x0b0, PIN_INPUT_PULLUP, 13) /* (AL33) MCASP1_AXR3.I2C1_SDA */ + >; + }; + main_mmc1_pins_default: main-mmc1-default-pins { bootph-all; pinctrl-single,pins = < @@ -429,6 +469,40 @@ J784S4_IOPAD(0x000, PIN_INPUT, 7) /* (AN35) EXTINTN.GPIO0_0 */ >; }; + + main_mcan6_pins_default: main-mcan6-default-pins { + pinctrl-single,pins = < + J784S4_IOPAD(0x098, PIN_INPUT, 0) /* (AH36) MCAN6_RX */ + J784S4_IOPAD(0x094, PIN_OUTPUT, 0) /* (AG35) MCAN6_TX */ + >; + }; + + main_mcan7_pins_default: main-mcan7-default-pins { + pinctrl-single,pins = < + J784S4_IOPAD(0x0A0, PIN_INPUT, 0) /* (AD34) MCAN7_RX */ + J784S4_IOPAD(0x09C, PIN_OUTPUT, 0) /* (AF35) MCAN7_TX */ + >; + }; + +}; + +&wkup_pmx0 { + bootph-all; + mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (E32) MCU_OSPI0_CLK */ + J784S4_WKUP_IOPAD(0x02c, PIN_OUTPUT, 0) /* (A32) MCU_OSPI0_CSn0 */ + J784S4_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (B33) MCU_OSPI0_D0 */ + J784S4_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (B32) MCU_OSPI0_D1 */ + J784S4_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (C33) MCU_OSPI0_D2 */ + J784S4_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (C35) MCU_OSPI0_D3 */ + J784S4_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (D33) MCU_OSPI0_D4 */ + J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D34) MCU_OSPI0_D5 */ + J784S4_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (E34) MCU_OSPI0_D6 */ + J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (E33) MCU_OSPI0_D7 */ + J784S4_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (C34) MCU_OSPI0_DQS */ + >; + }; }; &wkup_pmx2 { @@ -525,6 +599,21 @@ J784S4_WKUP_IOPAD(0x090, PIN_INPUT, 7) /* (H37) WKUP_GPIO0_14 */ >; }; + + mcu_mcan0_pins_default: mcu-mcan0-default-pins { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x054, PIN_INPUT, 0) /* (F38) MCU_MCAN0_RX */ + J784S4_WKUP_IOPAD(0x050, PIN_OUTPUT, 0) /* (K33) MCU_MCAN0_TX */ + >; + }; + + mcu_mcan1_pins_default: mcu-mcan1-default-pins { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x06c, PIN_INPUT, 0) /* (K36) WKUP_GPIO0_5.MCU_MCAN1_RX */ + J784S4_WKUP_IOPAD(0x068, PIN_OUTPUT, 0)/* (H35) WKUP_GPIO0_4.MCU_MCAN1_TX */ + >; + }; + }; &wkup_pmx3 { @@ -646,7 +735,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pmic_irq_pins_default>; interrupt-parent = <&wkup_gpio0>; - interrupts = <39 IRQ_TYPE_EDGE_FALLING>; + interrupts = <83 IRQ_TYPE_EDGE_FALLING>; gpio-controller; #gpio-cells = <2>; ti,primary-pmic; @@ -774,6 +863,42 @@ }; }; +&main_i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c1_pins_default>; + clock-frequency = <400000>; + status = "okay"; + + exp2: gpio@21 { + compatible = "ti,tca6408"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "CSI_VIO_SEL", "CSI_MUX_SEL_2", "CSI2_RSTz", + "IO_EXP_CAM0_GPIO1", "IO_EXP_CAM1_GPIO1"; + }; + + i2c-mux@70 { + compatible = "nxp,pca9543"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + + cam0_i2c: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + cam1_i2c: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + }; +}; + &main_sdhci0 { bootph-all; /* eMMC */ @@ -822,77 +947,77 @@ }; &mcu_r5fss0_core0 { - mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>; + mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; memory-region = <&mcu_r5fss0_core0_dma_memory_region>, <&mcu_r5fss0_core0_memory_region>; }; &mcu_r5fss0_core1 { - mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>; + mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; memory-region = <&mcu_r5fss0_core1_dma_memory_region>, <&mcu_r5fss0_core1_memory_region>; }; &main_r5fss0_core0 { - mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>; + mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; memory-region = <&main_r5fss0_core0_dma_memory_region>, <&main_r5fss0_core0_memory_region>; }; &main_r5fss0_core1 { - mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>; + mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; memory-region = <&main_r5fss0_core1_dma_memory_region>, <&main_r5fss0_core1_memory_region>; }; &main_r5fss1_core0 { - mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core0>; + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; memory-region = <&main_r5fss1_core0_dma_memory_region>, <&main_r5fss1_core0_memory_region>; }; &main_r5fss1_core1 { - mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core1>; + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; memory-region = <&main_r5fss1_core1_dma_memory_region>, <&main_r5fss1_core1_memory_region>; }; &main_r5fss2_core0 { - mboxes = <&mailbox0_cluster3>, <&mbox_main_r5fss2_core0>; + mboxes = <&mailbox0_cluster3 &mbox_main_r5fss2_core0>; memory-region = <&main_r5fss2_core0_dma_memory_region>, <&main_r5fss2_core0_memory_region>; }; &main_r5fss2_core1 { - mboxes = <&mailbox0_cluster3>, <&mbox_main_r5fss2_core1>; + mboxes = <&mailbox0_cluster3 &mbox_main_r5fss2_core1>; memory-region = <&main_r5fss2_core1_dma_memory_region>, <&main_r5fss2_core1_memory_region>; }; &c71_0 { status = "okay"; - mboxes = <&mailbox0_cluster4>, <&mbox_c71_0>; + mboxes = <&mailbox0_cluster4 &mbox_c71_0>; memory-region = <&c71_0_dma_memory_region>, <&c71_0_memory_region>; }; &c71_1 { status = "okay"; - mboxes = <&mailbox0_cluster4>, <&mbox_c71_1>; + mboxes = <&mailbox0_cluster4 &mbox_c71_1>; memory-region = <&c71_1_dma_memory_region>, <&c71_1_memory_region>; }; &c71_2 { status = "okay"; - mboxes = <&mailbox0_cluster5>, <&mbox_c71_2>; + mboxes = <&mailbox0_cluster5 &mbox_c71_2>; memory-region = <&c71_2_dma_memory_region>, <&c71_2_memory_region>; }; &c71_3 { status = "okay"; - mboxes = <&mailbox0_cluster5>, <&mbox_c71_3>; + mboxes = <&mailbox0_cluster5 &mbox_c71_3>; memory-region = <&c71_3_dma_memory_region>, <&c71_3_memory_region>; }; @@ -918,13 +1043,9 @@ pinctrl-names = "default"; pinctrl-0 = <&dss_vout0_pins_default>; assigned-clocks = <&k3_clks 218 2>, - <&k3_clks 218 5>, - <&k3_clks 218 14>, - <&k3_clks 218 18>; + <&k3_clks 218 5>; assigned-clock-parents = <&k3_clks 218 3>, - <&k3_clks 218 7>, - <&k3_clks 218 16>, - <&k3_clks 218 22>; + <&k3_clks 218 7>; }; &serdes_wiz4 { @@ -992,3 +1113,93 @@ }; }; }; + +&mcu_mcan0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_mcan0_pins_default>; + phys = <&transceiver1>; +}; + +&mcu_mcan1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_mcan1_pins_default>; + phys = <&transceiver2>; +}; + +&main_mcan6 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_mcan6_pins_default>; + phys = <&transceiver3>; +}; + +&main_mcan7 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_mcan7_pins_default>; + phys = <&transceiver4>; +}; + +&ospi0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-tx-bus-width = <8>; + spi-rx-bus-width = <8>; + spi-max-frequency = <25000000>; + cdns,tshsl-ns = <60>; + cdns,tsd2d-ns = <60>; + cdns,tchsh-ns = <60>; + cdns,tslch-ns = <60>; + cdns,read-delay = <4>; + + partitions { + bootph-all; + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "ospi.tiboot3"; + reg = <0x0 0x100000>; + }; + + partition@100000 { + label = "ospi.tispl"; + reg = <0x100000 0x200000>; + }; + + partition@300000 { + label = "ospi.u-boot"; + reg = <0x300000 0x400000>; + }; + + partition@700000 { + label = "ospi.env"; + reg = <0x700000 0x40000>; + }; + + partition@740000 { + label = "ospi.env.backup"; + reg = <0x740000 0x40000>; + }; + + partition@800000 { + label = "ospi.rootfs"; + reg = <0x800000 0x37c0000>; + }; + + partition@3fc0000 { + bootph-pre-ram; + label = "ospi.phypattern"; + reg = <0x3fc0000 0x40000>; + }; + }; + }; +}; diff --git a/src/arm64/ti/k3-j7200-common-proc-board.dts b/src/arm64/ti/k3-j7200-common-proc-board.dts index cee2b4b..6593c5d 100644 --- a/src/arm64/ti/k3-j7200-common-proc-board.dts +++ b/src/arm64/ti/k3-j7200-common-proc-board.dts @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* - * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; @@ -88,27 +88,56 @@ states = <1800000 0x0>, <3300000 0x1>; }; + + transceiver1: can-phy1 { + compatible = "ti,tcan1043"; + #phy-cells = <0>; + max-bitrate = <5000000>; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_mcan0_gpio_pins_default>; + standby-gpios = <&wkup_gpio0 58 GPIO_ACTIVE_LOW>; + enable-gpios = <&wkup_gpio0 0 GPIO_ACTIVE_HIGH>; + }; + + transceiver2: can-phy2 { + compatible = "ti,tcan1042"; + #phy-cells = <0>; + max-bitrate = <5000000>; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_mcan1_gpio_pins_default>; + standby-gpios = <&wkup_gpio0 2 GPIO_ACTIVE_HIGH>; + }; + + transceiver3: can-phy3 { + compatible = "ti,tcan1043"; + #phy-cells = <0>; + max-bitrate = <5000000>; + standby-gpios = <&exp2 7 GPIO_ACTIVE_LOW>; + enable-gpios = <&exp2 6 GPIO_ACTIVE_HIGH>; + mux-states = <&mux0 1>; + }; }; &wkup_pmx0 { +}; + +&wkup_pmx2 { mcu_uart0_pins_default: mcu-uart0-default-pins { pinctrl-single,pins = < - J721E_WKUP_IOPAD(0xf4, PIN_INPUT, 0) /* (D20) MCU_UART0_RXD */ - J721E_WKUP_IOPAD(0xf0, PIN_OUTPUT, 0) /* (D19) MCU_UART0_TXD */ - J721E_WKUP_IOPAD(0xf8, PIN_INPUT, 0) /* (E20) MCU_UART0_CTSn */ - J721E_WKUP_IOPAD(0xfc, PIN_OUTPUT, 0) /* (E21) MCU_UART0_RTSn */ + J721E_WKUP_IOPAD(0x90, PIN_INPUT, 0) /* (E20) MCU_UART0_CTSn */ + J721E_WKUP_IOPAD(0x94, PIN_OUTPUT, 0) /* (E21) MCU_UART0_RTSn */ + J721E_WKUP_IOPAD(0x8c, PIN_INPUT, 0) /* (D20) MCU_UART0_RXD */ + J721E_WKUP_IOPAD(0x88, PIN_OUTPUT, 0) /* (D19) MCU_UART0_TXD */ >; }; wkup_uart0_pins_default: wkup-uart0-default-pins { pinctrl-single,pins = < - J721E_WKUP_IOPAD(0xb0, PIN_INPUT, 0) /* (B14) WKUP_UART0_RXD */ - J721E_WKUP_IOPAD(0xb4, PIN_OUTPUT, 0) /* (A14) WKUP_UART0_TXD */ + J721E_WKUP_IOPAD(0x48, PIN_INPUT, 0) /* (B14) WKUP_UART0_RXD */ + J721E_WKUP_IOPAD(0x4c, PIN_OUTPUT, 0) /* (A14) WKUP_UART0_TXD */ >; }; -}; -&wkup_pmx2 { mcu_cpsw_pins_default: mcu-cpsw-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_RGMII1_TX_CTL */ @@ -138,6 +167,33 @@ J721E_WKUP_IOPAD(0x0030, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */ >; }; + + mcu_mcan0_pins_default: mcu-mcan0-default-pins { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0x54, PIN_INPUT, 0) /* (A17) MCU_MCAN0_RX */ + J721E_WKUP_IOPAD(0x50, PIN_OUTPUT, 0) /* (A16) MCU_MCAN0_TX */ + >; + }; + + mcu_mcan1_pins_default: mcu-mcan1-default-pins { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0x6c, PIN_INPUT, 0) /* (B16) WKUP_GPIO0_5.MCU_MCAN1_RX */ + J721E_WKUP_IOPAD(0x68, PIN_OUTPUT, 0) /* (D13) WKUP_GPIO0_4.MCU_MCAN1_TX */ + >; + }; + + mcu_mcan0_gpio_pins_default: mcu-mcan0-gpio-default-pins { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0x58, PIN_INPUT, 7) /* (B18) WKUP_GPIO0_0 */ + J721E_WKUP_IOPAD(0x40, PIN_INPUT, 7) /* (B17) MCU_SPI0_D1 */ + >; + }; + + mcu_mcan1_gpio_pins_default: mcu-mcan1-gpio-default-pins { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0x60, PIN_INPUT, 7) /* (D14) WKUP_GPIO0_2 */ + >; + }; }; &main_pmx0 { @@ -189,6 +245,13 @@ J721E_IOPAD(0xd0, PIN_OUTPUT, 7) /* (T5) SPI0_D1.GPIO0_55 */ >; }; + + main_mcan3_pins_default: main-mcan3-default-pins { + pinctrl-single,pins = < + J721E_IOPAD(0x3c, PIN_INPUT, 0) /* (W16) MCAN3_RX */ + J721E_IOPAD(0x38, PIN_OUTPUT, 0) /* (Y21) MCAN3_TX */ + >; + }; }; &main_pmx1 { @@ -210,7 +273,6 @@ status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&mcu_uart0_pins_default>; - clock-frequency = <96000000>; }; &main_uart0 { @@ -382,15 +444,30 @@ }; &pcie1_rc { + status = "okay"; reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>; phys = <&serdes0_pcie_link>; phy-names = "pcie-phy"; num-lanes = <2>; }; -&pcie1_ep { - phys = <&serdes0_pcie_link>; - phy-names = "pcie-phy"; - num-lanes = <2>; - status = "disabled"; +&mcu_mcan0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_mcan0_pins_default>; + phys = <&transceiver1>; +}; + +&mcu_mcan1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_mcan1_pins_default>; + phys = <&transceiver2>; +}; + +&main_mcan3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_mcan3_pins_default>; + phys = <&transceiver3>; }; diff --git a/src/arm64/ti/k3-j7200-evm-quad-port-eth-exp.dtso b/src/arm64/ti/k3-j7200-evm-quad-port-eth-exp.dtso index 32d9052..6432ca0 100644 --- a/src/arm64/ti/k3-j7200-evm-quad-port-eth-exp.dtso +++ b/src/arm64/ti/k3-j7200-evm-quad-port-eth-exp.dtso @@ -1,9 +1,9 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /** * DT Overlay for CPSW5G in QSGMII mode using J7 Quad Port ETH EXP Add-On Ethernet Card with * J7200 board. * - * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/src/arm64/ti/k3-j7200-main.dtsi b/src/arm64/ti/k3-j7200-main.dtsi index da67bf8..657f9cc 100644 --- a/src/arm64/ti/k3-j7200-main.dtsi +++ b/src/arm64/ti/k3-j7200-main.dtsi @@ -1,8 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree Source for J7200 SoC Family Main Domain peripherals * - * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/ */ / { @@ -33,10 +33,11 @@ ranges = <0x00 0x00 0x00100000 0x1c000>; serdes_ln_ctrl: mux-controller@4080 { - compatible = "mmio-mux"; + compatible = "reg-mux"; + reg = <0x4080 0x20>; #mux-control-cells = <1>; - mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */ - <0x4088 0x3>, <0x408c 0x3>; /* SERDES0 lane2/3 select */ + mux-reg-masks = <0x0 0x3>, <0x4 0x3>, /* SERDES0 lane0/1 select */ + <0x8 0x3>, <0xc 0x3>; /* SERDES0 lane2/3 select */ }; cpsw0_phy_gmii_sel: phy@4044 { @@ -47,9 +48,10 @@ }; usb_serdes_mux: mux-controller@4000 { - compatible = "mmio-mux"; + compatible = "reg-mux"; + reg = <0x4000 0x4>; #mux-control-cells = <1>; - mux-reg-masks = <0x4000 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */ + mux-reg-masks = <0x0 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */ }; }; @@ -399,7 +401,7 @@ /* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */ main_timerio_input: pinctrl@104200 { - compatible = "pinctrl-single"; + compatible = "ti,j7200-padconf", "pinctrl-single"; reg = <0x0 0x104200 0x0 0x50>; #pinctrl-cells = <1>; pinctrl-single,register-width = <32>; @@ -408,7 +410,7 @@ /* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */ main_timerio_output: pinctrl@104280 { - compatible = "pinctrl-single"; + compatible = "ti,j7200-padconf", "pinctrl-single"; reg = <0x0 0x104280 0x0 0x20>; #pinctrl-cells = <1>; pinctrl-single,register-width = <32>; @@ -416,7 +418,7 @@ }; main_pmx0: pinctrl@11c000 { - compatible = "pinctrl-single"; + compatible = "ti,j7200-padconf", "pinctrl-single"; /* Proxy 0 addressing */ reg = <0x00 0x11c000 0x00 0x10c>; #pinctrl-cells = <1>; @@ -425,7 +427,7 @@ }; main_pmx1: pinctrl@11c11c { - compatible = "pinctrl-single"; + compatible = "ti,j7200-padconf", "pinctrl-single"; /* Proxy 0 addressing */ reg = <0x00 0x11c11c 0x00 0xc>; #pinctrl-cells = <1>; @@ -770,26 +772,7 @@ ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>, <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>; dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; - }; - - pcie1_ep: pcie-ep@2910000 { - compatible = "ti,j7200-pcie-ep", "ti,j721e-pcie-ep"; - reg = <0x00 0x02910000 0x00 0x1000>, - <0x00 0x02917000 0x00 0x400>, - <0x00 0x0d800000 0x00 0x00800000>, - <0x00 0x18000000 0x00 0x08000000>; - reg-names = "intd_cfg", "user_cfg", "reg", "mem"; - interrupt-names = "link_state"; - interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>; - ti,syscon-pcie-ctrl = <&scm_conf 0x4074>; - max-link-speed = <3>; - num-lanes = <4>; - power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 240 6>; - clock-names = "fck"; - max-functions = /bits/ 8 <6>; - max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>; - dma-coherent; + status = "disabled"; }; usbss0: cdns-usb@4104000 { @@ -895,6 +878,276 @@ status = "disabled"; }; + main_mcan0: can@2701000 { + compatible = "bosch,m_can"; + reg = <0x00 0x02701000 0x00 0x200>, + <0x00 0x02708000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 156 0>, <&k3_clks 156 2>; + clock-names = "hclk", "cclk"; + interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + main_mcan1: can@2711000 { + compatible = "bosch,m_can"; + reg = <0x00 0x02711000 0x00 0x200>, + <0x00 0x02718000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 158 0>, <&k3_clks 158 2>; + clock-names = "hclk", "cclk"; + interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + main_mcan2: can@2721000 { + compatible = "bosch,m_can"; + reg = <0x00 0x02721000 0x00 0x200>, + <0x00 0x02728000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 160 0>, <&k3_clks 160 2>; + clock-names = "hclk", "cclk"; + interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + main_mcan3: can@2731000 { + compatible = "bosch,m_can"; + reg = <0x00 0x02731000 0x00 0x200>, + <0x00 0x02738000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 161 0>, <&k3_clks 161 2>; + clock-names = "hclk", "cclk"; + interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + main_mcan4: can@2741000 { + compatible = "bosch,m_can"; + reg = <0x00 0x02741000 0x00 0x200>, + <0x00 0x02748000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 162 0>, <&k3_clks 162 2>; + clock-names = "hclk", "cclk"; + interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + main_mcan5: can@2751000 { + compatible = "bosch,m_can"; + reg = <0x00 0x02751000 0x00 0x200>, + <0x00 0x02758000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 163 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 163 0>, <&k3_clks 163 2>; + clock-names = "hclk", "cclk"; + interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + main_mcan6: can@2761000 { + compatible = "bosch,m_can"; + reg = <0x00 0x02761000 0x00 0x200>, + <0x00 0x02768000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 164 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 164 0>, <&k3_clks 164 2>; + clock-names = "hclk", "cclk"; + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + main_mcan7: can@2771000 { + compatible = "bosch,m_can"; + reg = <0x00 0x02771000 0x00 0x200>, + <0x00 0x02778000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 165 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 165 0>, <&k3_clks 165 2>; + clock-names = "hclk", "cclk"; + interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + main_mcan8: can@2781000 { + compatible = "bosch,m_can"; + reg = <0x00 0x02781000 0x00 0x200>, + <0x00 0x02788000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 166 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 166 0>, <&k3_clks 166 2>; + clock-names = "hclk", "cclk"; + interrupts = <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + main_mcan9: can@2791000 { + compatible = "bosch,m_can"; + reg = <0x00 0x02791000 0x00 0x200>, + <0x00 0x02798000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 167 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 167 0>, <&k3_clks 167 2>; + clock-names = "hclk", "cclk"; + interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + main_mcan10: can@27a1000 { + compatible = "bosch,m_can"; + reg = <0x00 0x027a1000 0x00 0x200>, + <0x00 0x027a8000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 168 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 168 0>, <&k3_clks 168 2>; + clock-names = "hclk", "cclk"; + interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + main_mcan11: can@27b1000 { + compatible = "bosch,m_can"; + reg = <0x00 0x027b1000 0x00 0x200>, + <0x00 0x027b8000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 169 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 169 0>, <&k3_clks 169 2>; + clock-names = "hclk", "cclk"; + interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + main_mcan12: can@27c1000 { + compatible = "bosch,m_can"; + reg = <0x00 0x027c1000 0x00 0x200>, + <0x00 0x027c8000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 170 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 170 0>, <&k3_clks 170 2>; + clock-names = "hclk", "cclk"; + interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + main_mcan13: can@27d1000 { + compatible = "bosch,m_can"; + reg = <0x00 0x027d1000 0x00 0x200>, + <0x00 0x027d8000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 171 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 171 0>, <&k3_clks 171 2>; + clock-names = "hclk", "cclk"; + interrupts = <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + main_mcan14: can@2681000 { + compatible = "bosch,m_can"; + reg = <0x00 0x02681000 0x00 0x200>, + <0x00 0x02688000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 150 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 150 0>, <&k3_clks 150 2>; + clock-names = "hclk", "cclk"; + interrupts = <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + main_mcan15: can@2691000 { + compatible = "bosch,m_can"; + reg = <0x00 0x02691000 0x00 0x200>, + <0x00 0x02698000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 151 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 151 0>, <&k3_clks 151 2>; + clock-names = "hclk", "cclk"; + interrupts = <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + main_mcan16: can@26a1000 { + compatible = "bosch,m_can"; + reg = <0x00 0x026a1000 0x00 0x200>, + <0x00 0x026a8000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 152 0>, <&k3_clks 152 2>; + clock-names = "hclk", "cclk"; + interrupts = <GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + main_mcan17: can@26b1000 { + compatible = "bosch,m_can"; + reg = <0x00 0x026b1000 0x00 0x200>, + <0x00 0x026b8000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 153 0>, <&k3_clks 153 2>; + clock-names = "hclk", "cclk"; + interrupts = <GIC_SPI 787 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 788 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; + main_spi0: spi@2100000 { compatible = "ti,am654-mcspi","ti,omap4-mcspi"; reg = <0x00 0x02100000 0x00 0x400>; diff --git a/src/arm64/ti/k3-j7200-mcu-wakeup.dtsi b/src/arm64/ti/k3-j7200-mcu-wakeup.dtsi index 60b2637..7cf21c9 100644 --- a/src/arm64/ti/k3-j7200-mcu-wakeup.dtsi +++ b/src/arm64/ti/k3-j7200-mcu-wakeup.dtsi @@ -1,8 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree Source for J7200 SoC Family MCU/WAKEUP Domain peripherals * - * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/ */ &cbass_mcu_wakeup { @@ -192,7 +192,7 @@ /* MCU_TIMERIO pad input CTRLMMR_MCU_TIMER*_CTRL registers */ mcu_timerio_input: pinctrl@40f04200 { - compatible = "pinctrl-single"; + compatible = "ti,j7200-padconf", "pinctrl-single"; reg = <0x0 0x40f04200 0x0 0x28>; #pinctrl-cells = <1>; pinctrl-single,register-width = <32>; @@ -202,7 +202,7 @@ /* MCU_TIMERIO pad output CTRLMMR_MCU_TIMERIO*_CTRL registers */ mcu_timerio_output: pinctrl@40f04280 { - compatible = "pinctrl-single"; + compatible = "ti,j7200-padconf", "pinctrl-single"; reg = <0x0 0x40f04280 0x0 0x28>; #pinctrl-cells = <1>; pinctrl-single,register-width = <32>; @@ -211,7 +211,7 @@ }; wkup_pmx0: pinctrl@4301c000 { - compatible = "pinctrl-single"; + compatible = "ti,j7200-padconf", "pinctrl-single"; /* Proxy 0 addressing */ reg = <0x00 0x4301c000 0x00 0x34>; #pinctrl-cells = <1>; @@ -220,7 +220,7 @@ }; wkup_pmx1: pinctrl@4301c038 { - compatible = "pinctrl-single"; + compatible = "ti,j7200-padconf", "pinctrl-single"; /* Proxy 0 addressing */ reg = <0x00 0x4301c038 0x00 0x8>; #pinctrl-cells = <1>; @@ -229,7 +229,7 @@ }; wkup_pmx2: pinctrl@4301c068 { - compatible = "pinctrl-single"; + compatible = "ti,j7200-padconf", "pinctrl-single"; /* Proxy 0 addressing */ reg = <0x00 0x4301c068 0x00 0xec>; #pinctrl-cells = <1>; @@ -238,7 +238,7 @@ }; wkup_pmx3: pinctrl@4301c174 { - compatible = "pinctrl-single"; + compatible = "ti,j7200-padconf", "pinctrl-single"; /* Proxy 0 addressing */ reg = <0x00 0x4301c174 0x00 0x20>; #pinctrl-cells = <1>; @@ -518,17 +518,18 @@ status = "disabled"; }; - fss: syscon@47000000 { - compatible = "syscon", "simple-mfd"; + fss: bus@47000000 { + compatible = "simple-bus"; reg = <0x00 0x47000000 0x00 0x100>; #address-cells = <2>; #size-cells = <2>; ranges; - hbmc_mux: hbmc-mux { - compatible = "mmio-mux"; + hbmc_mux: mux-controller@47000004 { + compatible = "reg-mux"; + reg = <0x00 0x47000004 0x00 0x4>; #mux-control-cells = <1>; - mux-reg-masks = <0x4 0x2>; /* HBMC select */ + mux-reg-masks = <0x0 0x2>; /* HBMC select */ }; hbmc: hyperbus@47034000 { @@ -655,4 +656,34 @@ ti,esm-pins = <95>; bootph-pre-ram; }; + + mcu_mcan0: can@40528000 { + compatible = "bosch,m_can"; + reg = <0x00 0x40528000 0x00 0x200>, + <0x00 0x40500000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 172 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 172 0>, <&k3_clks 172 2>; + clock-names = "hclk", "cclk"; + interrupts = <GIC_SPI 832 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + mcu_mcan1: can@40568000 { + compatible = "bosch,m_can"; + reg = <0x00 0x40568000 0x00 0x200>, + <0x00 0x40540000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 173 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 173 0>, <&k3_clks 173 2>; + clock-names = "hclk", "cclk"; + interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; }; diff --git a/src/arm64/ti/k3-j7200-som-p0.dtsi b/src/arm64/ti/k3-j7200-som-p0.dtsi index ea47f10..7e6a584 100644 --- a/src/arm64/ti/k3-j7200-som-p0.dtsi +++ b/src/arm64/ti/k3-j7200-som-p0.dtsi @@ -1,10 +1,12 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* - * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; +#include <dt-bindings/gpio/gpio.h> + #include "k3-j7200.dtsi" / { @@ -80,6 +82,25 @@ no-map; }; }; + + mux0: mux-controller { + compatible = "gpio-mux"; + #mux-state-cells = <1>; + mux-gpios = <&exp_som 1 GPIO_ACTIVE_HIGH>; + }; + + mux1: mux-controller { + compatible = "gpio-mux"; + #mux-state-cells = <1>; + mux-gpios = <&exp_som 2 GPIO_ACTIVE_HIGH>; + }; + + transceiver0: can-phy0 { + /* standby pin has been grounded by default */ + compatible = "ti,tcan1042"; + #phy-cells = <0>; + max-bitrate = <5000000>; + }; }; &wkup_pmx0 { @@ -142,6 +163,13 @@ J721E_IOPAD(0xd8, PIN_INPUT_PULLUP, 0) /* (W2) I2C0_SDA */ >; }; + + main_mcan0_pins_default: main-mcan0-default-pins { + pinctrl-single,pins = < + J721E_IOPAD(0x24, PIN_INPUT, 0) /* (V20) MCAN0_RX */ + J721E_IOPAD(0x20, PIN_OUTPUT, 0) /* (V18) MCAN0_TX */ + >; + }; }; &hbmc { @@ -222,25 +250,25 @@ }; &mcu_r5fss0_core0 { - mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>; + mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; memory-region = <&mcu_r5fss0_core0_dma_memory_region>, <&mcu_r5fss0_core0_memory_region>; }; &mcu_r5fss0_core1 { - mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>; + mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; memory-region = <&mcu_r5fss0_core1_dma_memory_region>, <&mcu_r5fss0_core1_memory_region>; }; &main_r5fss0_core0 { - mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>; + mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; memory-region = <&main_r5fss0_core0_dma_memory_region>, <&main_r5fss0_core0_memory_region>; }; &main_r5fss0_core1 { - mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>; + mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; memory-region = <&main_r5fss0_core1_dma_memory_region>, <&main_r5fss0_core1_memory_region>; }; @@ -478,3 +506,10 @@ }; }; }; + +&main_mcan0 { + status = "okay"; + pinctrl-0 = <&main_mcan0_pins_default>; + pinctrl-names = "default"; + phys = <&transceiver0>; +}; diff --git a/src/arm64/ti/k3-j7200-thermal.dtsi b/src/arm64/ti/k3-j7200-thermal.dtsi index e7e3a64..2d22a95 100644 --- a/src/arm64/ti/k3-j7200-thermal.dtsi +++ b/src/arm64/ti/k3-j7200-thermal.dtsi @@ -1,4 +1,7 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ + */ #include <dt-bindings/thermal/thermal.h> diff --git a/src/arm64/ti/k3-j7200.dtsi b/src/arm64/ti/k3-j7200.dtsi index ef73e6d..d411911 100644 --- a/src/arm64/ti/k3-j7200.dtsi +++ b/src/arm64/ti/k3-j7200.dtsi @@ -1,8 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree Source for J7200 SoC Family * - * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/ */ #include <dt-bindings/interrupt-controller/irq.h> diff --git a/src/arm64/ti/k3-j721e-beagleboneai64.dts b/src/arm64/ti/k3-j721e-beagleboneai64.dts index 2f95472..a292555 100644 --- a/src/arm64/ti/k3-j721e-beagleboneai64.dts +++ b/src/arm64/ti/k3-j721e-beagleboneai64.dts @@ -1,9 +1,9 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * https://beagleboard.org/ai-64 - * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ - * Copyright (C) 2022 Jason Kridner, BeagleBoard.org Foundation - * Copyright (C) 2022 Robert Nelson, BeagleBoard.org Foundation + * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2022-2024 Jason Kridner, BeagleBoard.org Foundation + * Copyright (C) 2022-2024 Robert Nelson, BeagleBoard.org Foundation */ /dts-v1/; @@ -936,58 +936,58 @@ }; &mcu_r5fss0_core0 { - mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>; + mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; memory-region = <&mcu_r5fss0_core0_dma_memory_region>, <&mcu_r5fss0_core0_memory_region>; }; &mcu_r5fss0_core1 { - mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>; + mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; memory-region = <&mcu_r5fss0_core1_dma_memory_region>, <&mcu_r5fss0_core1_memory_region>; }; &main_r5fss0_core0 { - mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>; + mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; memory-region = <&main_r5fss0_core0_dma_memory_region>, <&main_r5fss0_core0_memory_region>; }; &main_r5fss0_core1 { - mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>; + mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; memory-region = <&main_r5fss0_core1_dma_memory_region>, <&main_r5fss0_core1_memory_region>; }; &main_r5fss1_core0 { - mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core0>; + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; memory-region = <&main_r5fss1_core0_dma_memory_region>, <&main_r5fss1_core0_memory_region>; }; &main_r5fss1_core1 { - mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core1>; + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; memory-region = <&main_r5fss1_core1_dma_memory_region>, <&main_r5fss1_core1_memory_region>; }; &c66_0 { status = "okay"; - mboxes = <&mailbox0_cluster3>, <&mbox_c66_0>; + mboxes = <&mailbox0_cluster3 &mbox_c66_0>; memory-region = <&c66_0_dma_memory_region>, <&c66_0_memory_region>; }; &c66_1 { status = "okay"; - mboxes = <&mailbox0_cluster3>, <&mbox_c66_1>; + mboxes = <&mailbox0_cluster3 &mbox_c66_1>; memory-region = <&c66_1_dma_memory_region>, <&c66_1_memory_region>; }; &c71_0 { status = "okay"; - mboxes = <&mailbox0_cluster4>, <&mbox_c71_0>; + mboxes = <&mailbox0_cluster4 &mbox_c71_0>; memory-region = <&c71_0_dma_memory_region>, <&c71_0_memory_region>; }; diff --git a/src/arm64/ti/k3-j721e-common-proc-board.dts b/src/arm64/ti/k3-j721e-common-proc-board.dts index fe5207a..8230d53 100644 --- a/src/arm64/ti/k3-j721e-common-proc-board.dts +++ b/src/arm64/ti/k3-j721e-common-proc-board.dts @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* - * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2019-2024 Texas Instruments Incorporated - https://www.ti.com/ * * Product Link: https://www.ti.com/tool/J721EXCPXEVM */ diff --git a/src/arm64/ti/k3-j721e-evm-gesi-exp-board.dtso b/src/arm64/ti/k3-j721e-evm-gesi-exp-board.dtso index 6a7d375..f84aa9f 100644 --- a/src/arm64/ti/k3-j721e-evm-gesi-exp-board.dtso +++ b/src/arm64/ti/k3-j721e-evm-gesi-exp-board.dtso @@ -1,11 +1,11 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /** * DT Overlay for CPSW9G in RGMII mode using J7 GESI EXP BRD board with * J721E board. * * GESI Board Product Link: https://www.ti.com/tool/J7EXPCXEVM * - * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/src/arm64/ti/k3-j721e-evm-pcie0-ep.dtso b/src/arm64/ti/k3-j721e-evm-pcie0-ep.dtso index 0c82a13..4062709 100644 --- a/src/arm64/ti/k3-j721e-evm-pcie0-ep.dtso +++ b/src/arm64/ti/k3-j721e-evm-pcie0-ep.dtso @@ -1,11 +1,11 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /** * DT Overlay for enabling PCIE0 instance in Endpoint Configuration with the * J7 common processor board. * * J7 Common Processor Board Product Link: https://www.ti.com/tool/J721EXCPXEVM * - * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/src/arm64/ti/k3-j721e-evm-quad-port-eth-exp.dtso b/src/arm64/ti/k3-j721e-evm-quad-port-eth-exp.dtso index d4c51ff..8376fa4 100644 --- a/src/arm64/ti/k3-j721e-evm-quad-port-eth-exp.dtso +++ b/src/arm64/ti/k3-j721e-evm-quad-port-eth-exp.dtso @@ -1,9 +1,9 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /** * DT Overlay for CPSW9G in QSGMII mode using J7 Quad Port ETH EXP Add-On Ethernet Card with * J721E board. * - * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/src/arm64/ti/k3-j721e-main.dtsi b/src/arm64/ti/k3-j721e-main.dtsi index 2569b4c..c7eafbc 100644 --- a/src/arm64/ti/k3-j721e-main.dtsi +++ b/src/arm64/ti/k3-j721e-main.dtsi @@ -1,8 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree Source for J721E SoC Family Main Domain peripherals * - * Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/ */ #include <dt-bindings/phy/phy.h> #include <dt-bindings/phy/phy-ti.h> @@ -45,15 +45,15 @@ ranges = <0x0 0x0 0x00100000 0x1c000>; serdes_ln_ctrl: mux-controller@4080 { - compatible = "mmio-mux"; - reg = <0x00004080 0x50>; + compatible = "reg-mux"; + reg = <0x4080 0x50>; #mux-control-cells = <1>; - mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */ - <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */ - <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */ - <0x40b0 0x3>, <0x40b4 0x3>, /* SERDES3 lane0/1 select */ - <0x40c0 0x3>, <0x40c4 0x3>, <0x40c8 0x3>, <0x40cc 0x3>; - /* SERDES4 lane0/1/2/3 select */ + mux-reg-masks = <0x0 0x3>, <0x4 0x3>, /* SERDES0 lane0/1 select */ + <0x10 0x3>, <0x14 0x3>, /* SERDES1 lane0/1 select */ + <0x20 0x3>, <0x24 0x3>, /* SERDES2 lane0/1 select */ + <0x30 0x3>, <0x34 0x3>, /* SERDES3 lane0/1 select */ + <0x40 0x3>, <0x44 0x3>, /* SERDES4 lane0/1 select */ + <0x48 0x3>, <0x4c 0x3>; /* SERDES4 lane2/3 select */ idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_PCIE0_LANE1>, <J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>, <J721E_SERDES2_LANE0_PCIE2_LANE0>, <J721E_SERDES2_LANE1_PCIE2_LANE1>, @@ -70,10 +70,11 @@ }; usb_serdes_mux: mux-controller@4000 { - compatible = "mmio-mux"; + compatible = "reg-mux"; + reg = <0x4000 0x20>; #mux-control-cells = <1>; - mux-reg-masks = <0x4000 0x8000000>, /* USB0 to SERDES0/3 mux */ - <0x4010 0x8000000>; /* USB1 to SERDES1/2 mux */ + mux-reg-masks = <0x0 0x8000000>, /* USB0 to SERDES0/3 mux */ + <0x10 0x8000000>; /* USB1 to SERDES1/2 mux */ }; ehrpwm_tbclk: clock-controller@4140 { @@ -572,6 +573,128 @@ pinctrl-single,function-mask = <0x0000001f>; }; + ti_csi2rx0: ticsi2rx@4500000 { + compatible = "ti,j721e-csi2rx-shim"; + reg = <0x0 0x4500000 0x0 0x1000>; + ranges; + #address-cells = <2>; + #size-cells = <2>; + dmas = <&main_udmap 0x4940>; + dma-names = "rx0"; + power-domains = <&k3_pds 26 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + + cdns_csi2rx0: csi-bridge@4504000 { + compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; + reg = <0x0 0x4504000 0x0 0x1000>; + clocks = <&k3_clks 26 2>, <&k3_clks 26 0>, <&k3_clks 26 2>, + <&k3_clks 26 2>, <&k3_clks 26 3>, <&k3_clks 26 3>; + clock-names = "sys_clk", "p_clk", "pixel_if0_clk", + "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; + phys = <&dphy0>; + phy-names = "dphy"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi0_port0: port@0 { + reg = <0>; + status = "disabled"; + }; + + csi0_port1: port@1 { + reg = <1>; + status = "disabled"; + }; + + csi0_port2: port@2 { + reg = <2>; + status = "disabled"; + }; + + csi0_port3: port@3 { + reg = <3>; + status = "disabled"; + }; + + csi0_port4: port@4 { + reg = <4>; + status = "disabled"; + }; + }; + }; + }; + + ti_csi2rx1: ticsi2rx@4510000 { + compatible = "ti,j721e-csi2rx-shim"; + reg = <0x0 0x4510000 0x0 0x1000>; + ranges; + #address-cells = <2>; + #size-cells = <2>; + dmas = <&main_udmap 0x4960>; + dma-names = "rx0"; + power-domains = <&k3_pds 27 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + + cdns_csi2rx1: csi-bridge@4514000 { + compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; + reg = <0x0 0x4514000 0x0 0x1000>; + clocks = <&k3_clks 27 2>, <&k3_clks 27 0>, <&k3_clks 27 2>, + <&k3_clks 27 2>, <&k3_clks 27 3>, <&k3_clks 27 3>; + clock-names = "sys_clk", "p_clk", "pixel_if0_clk", + "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; + phys = <&dphy1>; + phy-names = "dphy"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi1_port0: port@0 { + reg = <0>; + status = "disabled"; + }; + + csi1_port1: port@1 { + reg = <1>; + status = "disabled"; + }; + + csi1_port2: port@2 { + reg = <2>; + status = "disabled"; + }; + + csi1_port3: port@3 { + reg = <3>; + status = "disabled"; + }; + + csi1_port4: port@4 { + reg = <4>; + status = "disabled"; + }; + }; + }; + }; + + dphy0: phy@4580000 { + compatible = "cdns,dphy-rx"; + reg = <0x0 0x4580000 0x0 0x1100>; + #phy-cells = <0>; + power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + + dphy1: phy@4590000 { + compatible = "cdns,dphy-rx"; + reg = <0x0 0x4590000 0x0 0x1100>; + #phy-cells = <0>; + power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + serdes_wiz0: wiz@5000000 { compatible = "ti,j721e-wiz-16g"; #address-cells = <1>; diff --git a/src/arm64/ti/k3-j721e-mcu-wakeup.dtsi b/src/arm64/ti/k3-j721e-mcu-wakeup.dtsi index a74912d..4618b69 100644 --- a/src/arm64/ti/k3-j721e-mcu-wakeup.dtsi +++ b/src/arm64/ti/k3-j721e-mcu-wakeup.dtsi @@ -1,8 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree Source for J721E SoC Family MCU/WAKEUP Domain peripherals * - * Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/ */ &cbass_mcu_wakeup { @@ -353,9 +353,9 @@ hbmc_mux: mux-controller@47000004 { compatible = "reg-mux"; - reg = <0x00 0x47000004 0x00 0x2>; + reg = <0x00 0x47000004 0x00 0x4>; #mux-control-cells = <1>; - mux-reg-masks = <0x4 0x2>; /* HBMC select */ + mux-reg-masks = <0x0 0x2>; /* HBMC select */ }; hbmc: hyperbus@47034000 { diff --git a/src/arm64/ti/k3-j721e-sk-csi2-dual-imx219.dtso b/src/arm64/ti/k3-j721e-sk-csi2-dual-imx219.dtso new file mode 100644 index 0000000..47bb548 --- /dev/null +++ b/src/arm64/ti/k3-j721e-sk-csi2-dual-imx219.dtso @@ -0,0 +1,165 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/** + * DT Overlay for dual RPi Camera V2.1 (Sony IMX219) interfaced with CSI2 + * on J721E SK, AM68 SK or AM69-SK board. + * https://datasheets.raspberrypi.org/camera/camera-v2-schematic.pdf + * + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include <dt-bindings/gpio/gpio.h> +#include "k3-pinctrl.h" + +&{/} { + clk_imx219_fixed: imx219-xclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; +}; + +&csi_mux { + idle-state = <1>; +}; + +/* CAM0 I2C */ +&cam0_i2c { + #address-cells = <1>; + #size-cells = <0>; + imx219_0: imx219-0@10 { + compatible = "sony,imx219"; + reg = <0x10>; + + clocks = <&clk_imx219_fixed>; + clock-names = "xclk"; + + port { + csi2_cam0: endpoint { + remote-endpoint = <&csi2rx0_in_sensor>; + link-frequencies = /bits/ 64 <456000000>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; +}; + +/* CAM1 I2C */ +&cam1_i2c { + #address-cells = <1>; + #size-cells = <0>; + imx219_1: imx219-1@10 { + compatible = "sony,imx219"; + reg = <0x10>; + + clocks = <&clk_imx219_fixed>; + clock-names = "xclk"; + + port { + csi2_cam1: endpoint { + remote-endpoint = <&csi2rx1_in_sensor>; + link-frequencies = /bits/ 64 <456000000>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; +}; + + +&cdns_csi2rx0 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi0_port0: port@0 { + reg = <0>; + status = "okay"; + + csi2rx0_in_sensor: endpoint { + remote-endpoint = <&csi2_cam0>; + bus-type = <4>; /* CSI2 DPHY. */ + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + + csi0_port1: port@1 { + reg = <1>; + status = "disabled"; + }; + + csi0_port2: port@2 { + reg = <2>; + status = "disabled"; + }; + + csi0_port3: port@3 { + reg = <3>; + status = "disabled"; + }; + + csi0_port4: port@4 { + reg = <4>; + status = "disabled"; + }; + }; +}; + +&dphy0 { + status = "okay"; +}; + +&ti_csi2rx0 { + status = "okay"; +}; + +&cdns_csi2rx1 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi1_port0: port@0 { + reg = <0>; + status = "okay"; + + csi2rx1_in_sensor: endpoint { + remote-endpoint = <&csi2_cam1>; + bus-type = <4>; /* CSI2 DPHY. */ + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + + csi1_port1: port@1 { + reg = <1>; + status = "disabled"; + }; + + csi1_port2: port@2 { + reg = <2>; + status = "disabled"; + }; + + csi1_port3: port@3 { + reg = <3>; + status = "disabled"; + }; + + csi1_port4: port@4 { + reg = <4>; + status = "disabled"; + }; + }; +}; + +&dphy1 { + status = "okay"; +}; + +&ti_csi2rx1 { + status = "okay"; +}; diff --git a/src/arm64/ti/k3-j721e-sk.dts b/src/arm64/ti/k3-j721e-sk.dts index 188dfe2..0c4575a 100644 --- a/src/arm64/ti/k3-j721e-sk.dts +++ b/src/arm64/ti/k3-j721e-sk.dts @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* - * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/ * * J721E SK URL: https://www.ti.com/tool/SK-TDA4VM */ @@ -286,6 +286,15 @@ }; }; }; + + csi_mux: mux-controller { + compatible = "gpio-mux"; + #mux-state-cells = <1>; + mux-gpios = <&main_gpio0 88 GPIO_ACTIVE_HIGH>; + idle-state = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&main_csi_mux_sel_pins_default>; + }; }; &main_pmx0 { @@ -352,6 +361,12 @@ >; }; + main_csi_mux_sel_pins_default: main-csi-mux-sel-default-pins { + pinctrl-single,pins = < + J721E_IOPAD(0x164, PIN_OUTPUT, 7) /* (V29) RGMII5_TD2 */ + >; + }; + dp0_pins_default: dp0-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x1c4, PIN_INPUT, 5) /* SPI0_CS1.DP0_HPD */ @@ -574,7 +589,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pmic_irq_pins_default>; interrupt-parent = <&wkup_gpio0>; - interrupts = <9 IRQ_TYPE_EDGE_FALLING>; + interrupts = <7 IRQ_TYPE_EDGE_FALLING>; gpio-controller; #gpio-cells = <2>; ti,primary-pmic; @@ -651,7 +666,7 @@ reg = <0x4c>; system-power-controller; interrupt-parent = <&wkup_gpio0>; - interrupts = <9 IRQ_TYPE_EDGE_FALLING>; + interrupts = <7 IRQ_TYPE_EDGE_FALLING>; gpio-controller; #gpio-cells = <2>; buck1234-supply = <&vsys_3v3>; @@ -858,14 +873,14 @@ reg = <0x70>; /* CSI0 I2C */ - i2c@0 { + cam0_i2c: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; }; /* CSI1 I2C */ - i2c@1 { + cam1_i2c: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; @@ -1168,58 +1183,58 @@ }; &mcu_r5fss0_core0 { - mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>; + mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; memory-region = <&mcu_r5fss0_core0_dma_memory_region>, <&mcu_r5fss0_core0_memory_region>; }; &mcu_r5fss0_core1 { - mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>; + mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; memory-region = <&mcu_r5fss0_core1_dma_memory_region>, <&mcu_r5fss0_core1_memory_region>; }; &main_r5fss0_core0 { - mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>; + mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; memory-region = <&main_r5fss0_core0_dma_memory_region>, <&main_r5fss0_core0_memory_region>; }; &main_r5fss0_core1 { - mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>; + mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; memory-region = <&main_r5fss0_core1_dma_memory_region>, <&main_r5fss0_core1_memory_region>; }; &main_r5fss1_core0 { - mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core0>; + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; memory-region = <&main_r5fss1_core0_dma_memory_region>, <&main_r5fss1_core0_memory_region>; }; &main_r5fss1_core1 { - mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core1>; + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; memory-region = <&main_r5fss1_core1_dma_memory_region>, <&main_r5fss1_core1_memory_region>; }; &c66_0 { status = "okay"; - mboxes = <&mailbox0_cluster3>, <&mbox_c66_0>; + mboxes = <&mailbox0_cluster3 &mbox_c66_0>; memory-region = <&c66_0_dma_memory_region>, <&c66_0_memory_region>; }; &c66_1 { status = "okay"; - mboxes = <&mailbox0_cluster3>, <&mbox_c66_1>; + mboxes = <&mailbox0_cluster3 &mbox_c66_1>; memory-region = <&c66_1_dma_memory_region>, <&c66_1_memory_region>; }; &c71_0 { status = "okay"; - mboxes = <&mailbox0_cluster4>, <&mbox_c71_0>; + mboxes = <&mailbox0_cluster4 &mbox_c71_0>; memory-region = <&c71_0_dma_memory_region>, <&c71_0_memory_region>; }; diff --git a/src/arm64/ti/k3-j721e-som-p0.dtsi b/src/arm64/ti/k3-j721e-som-p0.dtsi index a75611e..1fae649 100644 --- a/src/arm64/ti/k3-j721e-som-p0.dtsi +++ b/src/arm64/ti/k3-j721e-som-p0.dtsi @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* - * Copyright (C) 2019-2020 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2019-2024 Texas Instruments Incorporated - https://www.ti.com/ * * Product Link: https://www.ti.com/tool/J721EXSOMXEVM */ @@ -549,58 +549,58 @@ }; &mcu_r5fss0_core0 { - mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>; + mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; memory-region = <&mcu_r5fss0_core0_dma_memory_region>, <&mcu_r5fss0_core0_memory_region>; }; &mcu_r5fss0_core1 { - mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>; + mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; memory-region = <&mcu_r5fss0_core1_dma_memory_region>, <&mcu_r5fss0_core1_memory_region>; }; &main_r5fss0_core0 { - mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>; + mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; memory-region = <&main_r5fss0_core0_dma_memory_region>, <&main_r5fss0_core0_memory_region>; }; &main_r5fss0_core1 { - mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>; + mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; memory-region = <&main_r5fss0_core1_dma_memory_region>, <&main_r5fss0_core1_memory_region>; }; &main_r5fss1_core0 { - mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core0>; + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; memory-region = <&main_r5fss1_core0_dma_memory_region>, <&main_r5fss1_core0_memory_region>; }; &main_r5fss1_core1 { - mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core1>; + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; memory-region = <&main_r5fss1_core1_dma_memory_region>, <&main_r5fss1_core1_memory_region>; }; &c66_0 { status = "okay"; - mboxes = <&mailbox0_cluster3>, <&mbox_c66_0>; + mboxes = <&mailbox0_cluster3 &mbox_c66_0>; memory-region = <&c66_0_dma_memory_region>, <&c66_0_memory_region>; }; &c66_1 { status = "okay"; - mboxes = <&mailbox0_cluster3>, <&mbox_c66_1>; + mboxes = <&mailbox0_cluster3 &mbox_c66_1>; memory-region = <&c66_1_dma_memory_region>, <&c66_1_memory_region>; }; &c71_0 { status = "okay"; - mboxes = <&mailbox0_cluster4>, <&mbox_c71_0>; + mboxes = <&mailbox0_cluster4 &mbox_c71_0>; memory-region = <&c71_0_dma_memory_region>, <&c71_0_memory_region>; }; diff --git a/src/arm64/ti/k3-j721e-thermal.dtsi b/src/arm64/ti/k3-j721e-thermal.dtsi index c252327..927f761 100644 --- a/src/arm64/ti/k3-j721e-thermal.dtsi +++ b/src/arm64/ti/k3-j721e-thermal.dtsi @@ -1,4 +1,7 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ + */ #include <dt-bindings/thermal/thermal.h> diff --git a/src/arm64/ti/k3-j721e.dtsi b/src/arm64/ti/k3-j721e.dtsi index a200810..5a72c51 100644 --- a/src/arm64/ti/k3-j721e.dtsi +++ b/src/arm64/ti/k3-j721e.dtsi @@ -1,8 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree Source for J721E SoC Family * - * Copyright (C) 2016-2019 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/ */ #include <dt-bindings/interrupt-controller/irq.h> diff --git a/src/arm64/ti/k3-j721s2-common-proc-board.dts b/src/arm64/ti/k3-j721s2-common-proc-board.dts index c6b85bb..c5a0b7c 100644 --- a/src/arm64/ti/k3-j721s2-common-proc-board.dts +++ b/src/arm64/ti/k3-j721s2-common-proc-board.dts @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* - * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/ * * Common Processor Board: https://www.ti.com/tool/J721EXCPXEVM */ @@ -147,6 +147,13 @@ >; }; + main_i2c5_pins_default: main-i2c5-default-pins { + pinctrl-single,pins = < + J721S2_IOPAD(0x01c, PIN_INPUT, 8) /* (Y24) MCAN15_TX.I2C5_SCL */ + J721S2_IOPAD(0x018, PIN_INPUT, 8) /* (W23) MCAN14_RX.I2C5_SDA */ + >; + }; + main_mmc1_pins_default: main-mmc1-default-pins { pinctrl-single,pins = < J721S2_IOPAD(0x104, PIN_INPUT, 0) /* (P23) MMC1_CLK */ @@ -190,8 +197,6 @@ &wkup_pmx2 { wkup_uart0_pins_default: wkup-uart0-default-pins { pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x070, PIN_INPUT, 0) /* (E25) WKUP_GPIO0_6.WKUP_UART0_CTSn */ - J721S2_WKUP_IOPAD(0x074, PIN_OUTPUT, 0) /* (F28) WKUP_GPIO0_7.WKUP_UART0_RTSn */ J721S2_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (D28) WKUP_UART0_RXD */ J721S2_WKUP_IOPAD(0x04c, PIN_OUTPUT, 0) /* (D27) WKUP_UART0_TXD */ >; @@ -356,6 +361,24 @@ }; }; +&main_i2c5 { + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c5_pins_default>; + clock-frequency = <400000>; + status = "okay"; + + exp5: gpio@20 { + compatible = "ti,tca6408"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "CSI2_EXP_RSTZ", "CSI2_EXP_A_GPIO0", + "CSI2_EXP_A_GPIO1", "CSI2_EXP_A_GPIO2", + "CSI2_EXP_B_GPIO1", "CSI2_EXP_B_GPIO2", + "CSI2_EXP_B_GPIO3", "CSI2_EXP_B_GPIO4"; + }; +}; + &main_sdhci0 { /* eMMC */ status = "okay"; diff --git a/src/arm64/ti/k3-j721s2-evm-gesi-exp-board.dtso b/src/arm64/ti/k3-j721s2-evm-gesi-exp-board.dtso index b78feea..1be2828 100644 --- a/src/arm64/ti/k3-j721s2-evm-gesi-exp-board.dtso +++ b/src/arm64/ti/k3-j721s2-evm-gesi-exp-board.dtso @@ -1,10 +1,10 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /** * DT Overlay for MAIN CPSW2G using GESI Expansion Board with J7 common processor board. * * GESI Board Product Link: https://www.ti.com/tool/J7EXPCXEVM * - * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/src/arm64/ti/k3-j721s2-evm-pcie1-ep.dtso b/src/arm64/ti/k3-j721s2-evm-pcie1-ep.dtso index 43568eb..5ff3909 100644 --- a/src/arm64/ti/k3-j721s2-evm-pcie1-ep.dtso +++ b/src/arm64/ti/k3-j721s2-evm-pcie1-ep.dtso @@ -1,11 +1,11 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /** * DT Overlay for enabling PCIE1 instance in Endpoint Configuration with the * J7 common processor board. * * J7 Common Processor Board Product Link: https://www.ti.com/tool/J721EXCPXEVM * - * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/src/arm64/ti/k3-j721s2-main.dtsi b/src/arm64/ti/k3-j721s2-main.dtsi index ea7f2b2..b70c861 100644 --- a/src/arm64/ti/k3-j721s2-main.dtsi +++ b/src/arm64/ti/k3-j721s2-main.dtsi @@ -1,8 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree Source for J721S2 SoC Family Main Domain peripherals * - * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/ */ #include <dt-bindings/phy/phy-cadence.h> @@ -45,7 +45,7 @@ ranges = <0x00 0x00 0x00104000 0x18000>; usb_serdes_mux: mux-controller@0 { - compatible = "mmio-mux"; + compatible = "reg-mux"; reg = <0x0 0x4>; #mux-control-cells = <1>; mux-reg-masks = <0x0 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */ @@ -58,11 +58,11 @@ }; serdes_ln_ctrl: mux-controller@80 { - compatible = "mmio-mux"; + compatible = "reg-mux"; reg = <0x80 0x10>; #mux-control-cells = <1>; - mux-reg-masks = <0x80 0x3>, <0x84 0x3>, /* SERDES0 lane0/1 select */ - <0x88 0x3>, <0x8c 0x3>; /* SERDES0 lane2/3 select */ + mux-reg-masks = <0x0 0x3>, <0x4 0x3>, /* SERDES0 lane0/1 select */ + <0x8 0x3>, <0xc 0x3>; /* SERDES0 lane2/3 select */ }; ehrpwm_tbclk: clock-controller@140 { @@ -716,6 +716,14 @@ status = "disabled"; }; + vpu: video-codec@4210000 { + compatible = "ti,j721s2-wave521c", "cnm,wave521c"; + reg = <0x00 0x4210000 0x00 0x10000>; + interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 179 2>; + power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>; + }; + main_sdhci0: mmc@4f80000 { compatible = "ti,j721e-sdhci-8bit"; reg = <0x00 0x04f80000 0x00 0x1000>, @@ -1122,7 +1130,6 @@ ti,sci-dev-id = <225>; ti,sci-rm-range-rchan = <0x21>; ti,sci-rm-range-tchan = <0x22>; - status = "disabled"; }; cpts@310d0000 { @@ -1233,6 +1240,128 @@ }; }; + ti_csi2rx0: ticsi2rx@4500000 { + compatible = "ti,j721e-csi2rx-shim"; + reg = <0x00 0x04500000 0x00 0x1000>; + ranges; + #address-cells = <2>; + #size-cells = <2>; + dmas = <&main_bcdma_csi 0 0x4940 0>; + dma-names = "rx0"; + power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + + cdns_csi2rx0: csi-bridge@4504000 { + compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; + reg = <0x00 0x04504000 0x00 0x1000>; + clocks = <&k3_clks 38 3>, <&k3_clks 38 1>, <&k3_clks 38 3>, + <&k3_clks 38 3>, <&k3_clks 38 4>, <&k3_clks 38 4>; + clock-names = "sys_clk", "p_clk", "pixel_if0_clk", + "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; + phys = <&dphy0>; + phy-names = "dphy"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi0_port0: port@0 { + reg = <0>; + status = "disabled"; + }; + + csi0_port1: port@1 { + reg = <1>; + status = "disabled"; + }; + + csi0_port2: port@2 { + reg = <2>; + status = "disabled"; + }; + + csi0_port3: port@3 { + reg = <3>; + status = "disabled"; + }; + + csi0_port4: port@4 { + reg = <4>; + status = "disabled"; + }; + }; + }; + }; + + ti_csi2rx1: ticsi2rx@4510000 { + compatible = "ti,j721e-csi2rx-shim"; + reg = <0x00 0x04510000 0x00 0x1000>; + ranges; + #address-cells = <2>; + #size-cells = <2>; + dmas = <&main_bcdma_csi 0 0x4960 0>; + dma-names = "rx0"; + power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + + cdns_csi2rx1: csi-bridge@4514000 { + compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; + reg = <0x00 0x04514000 0x00 0x1000>; + clocks = <&k3_clks 39 3>, <&k3_clks 39 1>, <&k3_clks 39 3>, + <&k3_clks 39 3>, <&k3_clks 39 4>, <&k3_clks 39 4>; + clock-names = "sys_clk", "p_clk", "pixel_if0_clk", + "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; + phys = <&dphy1>; + phy-names = "dphy"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi1_port0: port@0 { + reg = <0>; + status = "disabled"; + }; + + csi1_port1: port@1 { + reg = <1>; + status = "disabled"; + }; + + csi1_port2: port@2 { + reg = <2>; + status = "disabled"; + }; + + csi1_port3: port@3 { + reg = <3>; + status = "disabled"; + }; + + csi1_port4: port@4 { + reg = <4>; + status = "disabled"; + }; + }; + }; + }; + + dphy0: phy@4580000 { + compatible = "cdns,dphy-rx"; + reg = <0x00 0x04580000 0x00 0x1100>; + #phy-cells = <0>; + power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + + dphy1: phy@4590000 { + compatible = "cdns,dphy-rx"; + reg = <0x00 0x04590000 0x00 0x1100>; + #phy-cells = <0>; + power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + serdes_wiz0: wiz@5060000 { compatible = "ti,j721s2-wiz-10g"; #address-cells = <1>; diff --git a/src/arm64/ti/k3-j721s2-mcu-wakeup.dtsi b/src/arm64/ti/k3-j721s2-mcu-wakeup.dtsi index 80aa33c..eaf7f70 100644 --- a/src/arm64/ti/k3-j721s2-mcu-wakeup.dtsi +++ b/src/arm64/ti/k3-j721s2-mcu-wakeup.dtsi @@ -1,8 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree Source for J721S2 SoC Family MCU/WAKEUP Domain peripherals * - * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/ */ &cbass_mcu_wakeup { @@ -663,7 +663,7 @@ compatible = "ti,j7200-vtm"; reg = <0x00 0x42040000 0x0 0x350>, <0x00 0x42050000 0x0 0x350>; - power-domains = <&k3_pds 154 TI_SCI_PD_SHARED>; + power-domains = <&k3_pds 180 TI_SCI_PD_SHARED>; #thermal-sensor-cells = <1>; }; diff --git a/src/arm64/ti/k3-j721s2-som-p0.dtsi b/src/arm64/ti/k3-j721s2-som-p0.dtsi index da3237b..623c842 100644 --- a/src/arm64/ti/k3-j721s2-som-p0.dtsi +++ b/src/arm64/ti/k3-j721s2-som-p0.dtsi @@ -1,8 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * SoM: https://www.ti.com/lit/zip/sprr439 * - * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; @@ -504,51 +504,51 @@ }; &mcu_r5fss0_core0 { - mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>; + mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; memory-region = <&mcu_r5fss0_core0_dma_memory_region>, <&mcu_r5fss0_core0_memory_region>; }; &mcu_r5fss0_core1 { - mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>; + mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; memory-region = <&mcu_r5fss0_core1_dma_memory_region>, <&mcu_r5fss0_core1_memory_region>; }; &main_r5fss0_core0 { - mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>; + mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; memory-region = <&main_r5fss0_core0_dma_memory_region>, <&main_r5fss0_core0_memory_region>; }; &main_r5fss0_core1 { - mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>; + mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; memory-region = <&main_r5fss0_core1_dma_memory_region>, <&main_r5fss0_core1_memory_region>; }; &main_r5fss1_core0 { - mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core0>; + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; memory-region = <&main_r5fss1_core0_dma_memory_region>, <&main_r5fss1_core0_memory_region>; }; &main_r5fss1_core1 { - mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core1>; + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; memory-region = <&main_r5fss1_core1_dma_memory_region>, <&main_r5fss1_core1_memory_region>; }; &c71_0 { status = "okay"; - mboxes = <&mailbox0_cluster4>, <&mbox_c71_0>; + mboxes = <&mailbox0_cluster4 &mbox_c71_0>; memory-region = <&c71_0_dma_memory_region>, <&c71_0_memory_region>; }; &c71_1 { status = "okay"; - mboxes = <&mailbox0_cluster4>, <&mbox_c71_1>; + mboxes = <&mailbox0_cluster4 &mbox_c71_1>; memory-region = <&c71_1_dma_memory_region>, <&c71_1_memory_region>; }; diff --git a/src/arm64/ti/k3-j721s2-thermal.dtsi b/src/arm64/ti/k3-j721s2-thermal.dtsi index f7b1a15..e3ef61c 100644 --- a/src/arm64/ti/k3-j721s2-thermal.dtsi +++ b/src/arm64/ti/k3-j721s2-thermal.dtsi @@ -1,4 +1,7 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ + */ #include <dt-bindings/thermal/thermal.h> diff --git a/src/arm64/ti/k3-j721s2.dtsi b/src/arm64/ti/k3-j721s2.dtsi index 1f636ac..be4502f 100644 --- a/src/arm64/ti/k3-j721s2.dtsi +++ b/src/arm64/ti/k3-j721s2.dtsi @@ -1,10 +1,10 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree Source for J721S2 SoC Family * * TRM (SPRUJ28 NOVEMBER 2021): https://www.ti.com/lit/pdf/spruj28 * - * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/ * */ diff --git a/src/arm64/ti/k3-j722s-evm.dts b/src/arm64/ti/k3-j722s-evm.dts new file mode 100644 index 0000000..cee3a86 --- /dev/null +++ b/src/arm64/ti/k3-j722s-evm.dts @@ -0,0 +1,383 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Device Tree file for the J722S EVM + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + * + * Schematics: https://www.ti.com/lit/zip/sprr495 + */ + +/dts-v1/; + +#include <dt-bindings/net/ti-dp83867.h> +#include "k3-j722s.dtsi" + +/ { + compatible = "ti,j722s-evm", "ti,j722s"; + model = "Texas Instruments J722S EVM"; + + aliases { + serial0 = &wkup_uart0; + serial2 = &main_uart0; + mmc0 = &sdhci0; + mmc1 = &sdhci1; + }; + + chosen { + stdout-path = &main_uart0; + }; + + memory@80000000 { + /* 8G RAM */ + reg = <0x00000000 0x80000000 0x00000000 0x80000000>, + <0x00000008 0x80000000 0x00000001 0x80000000>; + device_type = "memory"; + bootph-pre-ram; + }; + + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + secure_tfa_ddr: tfa@9e780000 { + reg = <0x00 0x9e780000 0x00 0x80000>; + no-map; + }; + + secure_ddr: optee@9e800000 { + reg = <0x00 0x9e800000 0x00 0x01800000>; + no-map; + }; + + wkup_r5fss0_core0_memory_region: r5f-memory@a0100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa0100000 0x00 0xf00000>; + no-map; + }; + + }; + + vmain_pd: regulator-0 { + /* TPS65988 PD CONTROLLER OUTPUT */ + compatible = "regulator-fixed"; + regulator-name = "vmain_pd"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + bootph-all; + }; + + vsys_5v0: regulator-vsys5v0 { + /* Output of LM5140 */ + compatible = "regulator-fixed"; + regulator-name = "vsys_5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vmain_pd>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_mmc1: regulator-mmc1 { + /* TPS22918DBVR */ + compatible = "regulator-fixed"; + regulator-name = "vdd_mmc1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + enable-active-high; + gpio = <&exp1 15 GPIO_ACTIVE_HIGH>; + bootph-all; + }; + + vdd_sd_dv: regulator-TLV71033 { + compatible = "regulator-gpio"; + regulator-name = "tlv71033"; + pinctrl-names = "default"; + pinctrl-0 = <&vdd_sd_dv_pins_default>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + vin-supply = <&vsys_5v0>; + gpios = <&main_gpio0 70 GPIO_ACTIVE_HIGH>; + states = <1800000 0x0>, + <3300000 0x1>; + }; + + vsys_io_1v8: regulator-vsys-io-1v8 { + compatible = "regulator-fixed"; + regulator-name = "vsys_io_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + vsys_io_1v2: regulator-vsys-io-1v2 { + compatible = "regulator-fixed"; + regulator-name = "vsys_io_1v2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + }; +}; + +&main_pmx0 { + + main_i2c0_pins_default: main-i2c0-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x01e0, PIN_INPUT_PULLUP, 0) /* (D23) I2C0_SCL */ + J722S_IOPAD(0x01e4, PIN_INPUT_PULLUP, 0) /* (B22) I2C0_SDA */ + >; + bootph-all; + }; + + main_uart0_pins_default: main-uart0-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x01c8, PIN_INPUT, 0) /* (A22) UART0_RXD */ + J722S_IOPAD(0x01cc, PIN_OUTPUT, 0) /* (B22) UART0_TXD */ + >; + bootph-all; + }; + + vdd_sd_dv_pins_default: vdd-sd-dv-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x0120, PIN_INPUT, 7) /* (F27) MMC2_CMD.GPIO0_70 */ + >; + bootph-all; + }; + + main_mmc1_pins_default: main-mmc1-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x023c, PIN_INPUT, 0) /* (H22) MMC1_CMD */ + J722S_IOPAD(0x0234, PIN_OUTPUT, 0) /* (H24) MMC1_CLK */ + J722S_IOPAD(0x0230, PIN_INPUT, 0) /* (H23) MMC1_DAT0 */ + J722S_IOPAD(0x022c, PIN_INPUT_PULLUP, 0) /* (H20) MMC1_DAT1 */ + J722S_IOPAD(0x0228, PIN_INPUT_PULLUP, 0) /* (J23) MMC1_DAT2 */ + J722S_IOPAD(0x0224, PIN_INPUT_PULLUP, 0) /* (H25) MMC1_DAT3 */ + J722S_IOPAD(0x0240, PIN_INPUT, 0) /* (B24) MMC1_SDCD */ + >; + bootph-all; + }; + + mdio_pins_default: mdio-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x0160, PIN_OUTPUT, 0) /* (AC24) MDIO0_MDC */ + J722S_IOPAD(0x015c, PIN_INPUT, 0) /* (AD25) MDIO0_MDIO */ + >; + }; + + ospi0_pins_default: ospi0-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x0000, PIN_OUTPUT, 0) /* (L24) OSPI0_CLK */ + J722S_IOPAD(0x002c, PIN_OUTPUT, 0) /* (K26) OSPI0_CSn0 */ + J722S_IOPAD(0x000c, PIN_INPUT, 0) /* (K27) OSPI0_D0 */ + J722S_IOPAD(0x0010, PIN_INPUT, 0) /* (L27) OSPI0_D1 */ + J722S_IOPAD(0x0014, PIN_INPUT, 0) /* (L26) OSPI0_D2 */ + J722S_IOPAD(0x0018, PIN_INPUT, 0) /* (L25) OSPI0_D3 */ + J722S_IOPAD(0x001c, PIN_INPUT, 0) /* (L21) OSPI0_D4 */ + J722S_IOPAD(0x0020, PIN_INPUT, 0) /* (M26) OSPI0_D5 */ + J722S_IOPAD(0x0024, PIN_INPUT, 0) /* (N27) OSPI0_D6 */ + J722S_IOPAD(0x0028, PIN_INPUT, 0) /* (M27) OSPI0_D7 */ + J722S_IOPAD(0x0008, PIN_INPUT, 0) /* (L22) OSPI0_DQS */ + >; + bootph-all; + }; + + rgmii1_pins_default: rgmii1-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x014c, PIN_INPUT, 0) /* (AC25) RGMII1_RD0 */ + J722S_IOPAD(0x0150, PIN_INPUT, 0) /* (AD27) RGMII1_RD1 */ + J722S_IOPAD(0x0154, PIN_INPUT, 0) /* (AE24) RGMII1_RD2 */ + J722S_IOPAD(0x0158, PIN_INPUT, 0) /* (AE26) RGMII1_RD3 */ + J722S_IOPAD(0x0148, PIN_INPUT, 0) /* (AE27) RGMII1_RXC */ + J722S_IOPAD(0x0144, PIN_INPUT, 0) /* (AD23) RGMII1_RX_CTL */ + J722S_IOPAD(0x0134, PIN_OUTPUT, 0) /* (AF27) RGMII1_TD0 */ + J722S_IOPAD(0x0138, PIN_OUTPUT, 0) /* (AE23) RGMII1_TD1 */ + J722S_IOPAD(0x013c, PIN_OUTPUT, 0) /* (AG25) RGMII1_TD2 */ + J722S_IOPAD(0x0140, PIN_OUTPUT, 0) /* (AF24) RGMII1_TD3 */ + J722S_IOPAD(0x0130, PIN_OUTPUT, 0) /* (AG26) RGMII1_TXC */ + J722S_IOPAD(0x012c, PIN_OUTPUT, 0) /* (AF25) RGMII1_TX_CTL */ + >; + }; +}; + +&cpsw3g { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii1_pins_default>; +}; + +&cpsw3g_mdio { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mdio_pins_default>; + + cpsw3g_phy0: ethernet-phy@0 { + reg = <0>; + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; + ti,min-output-impedance; + }; +}; + +&cpsw_port1 { + phy-mode = "rgmii-rxid"; + phy-handle = <&cpsw3g_phy0>; +}; + +&cpsw_port2 { + status = "disabled"; +}; + +&main_gpio1 { + status = "okay"; +}; + +&main_uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_uart0_pins_default>; + status = "okay"; + bootph-all; +}; + +&mcu_pmx0 { + + wkup_uart0_pins_default: wkup-uart0-default-pins { + pinctrl-single,pins = < + J722S_MCU_IOPAD(0x02c, PIN_INPUT, 0) /* (C7) WKUP_UART0_CTSn */ + J722S_MCU_IOPAD(0x030, PIN_OUTPUT, 0) /* (C6) WKUP_UART0_RTSn */ + J722S_MCU_IOPAD(0x024, PIN_INPUT, 0) /* (D8) WKUP_UART0_RXD */ + J722S_MCU_IOPAD(0x028, PIN_OUTPUT, 0) /* (D7) WKUP_UART0_TXD */ + >; + bootph-all; + }; + + wkup_i2c0_pins_default: wkup-i2c0-default-pins { + pinctrl-single,pins = < + J722S_MCU_IOPAD(0x04c, PIN_INPUT_PULLUP, 0) /* (C7) WKUP_I2C0_SCL */ + J722S_MCU_IOPAD(0x050, PIN_INPUT_PULLUP, 0) /* (C6) WKUP_I2C1_SDA */ + >; + bootph-all; + }; +}; + +&wkup_uart0 { + /* WKUP UART0 is used by Device Manager firmware */ + pinctrl-names = "default"; + pinctrl-0 = <&wkup_uart0_pins_default>; + status = "reserved"; + bootph-all; +}; + +&wkup_i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&wkup_i2c0_pins_default>; + clock-frequency = <400000>; + status = "okay"; + bootph-all; +}; + +&main_i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c0_pins_default>; + clock-frequency = <400000>; + status = "okay"; + bootph-all; + + exp1: gpio@23 { + compatible = "ti,tca6424"; + reg = <0x23>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "TRC_MUX_SEL", "OSPI/ONAND_MUX_SEL", + "MCASP1_FET_SEL", "CTRL_PM_I2C_OE#", + "CSI_VIO_SEL", "USB2.0_MUX_SEL", + "CSI01_MUX_SEL_2", "CSI23_MUX_SEL_2", + "LMK1_OE1", "LMK1_OE0", + "LMK2_OE0", "LMK2_OE1", + "GPIO_RGMII1_RST#", "GPIO_AUD_RSTn", + "GPIO_eMMC_RSTn", "GPIO_uSD_PWR_EN", + "USER_LED2", "MCAN0_STB", + "PCIe0_1L_RC_RSTz", "PCIe0_1L_PRSNT#", + "ENET1_EXP_SPARE2", "ENET1_EXP_PWRDN", + "PD_I2ENET1_I2CMUX_SELC_IRQ", "ENET1_EXP_RESETZ"; + }; +}; + +&ospi0 { + pinctrl-names = "default"; + pinctrl-0 = <&ospi0_pins_default>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-tx-bus-width = <8>; + spi-rx-bus-width = <8>; + spi-max-frequency = <25000000>; + cdns,tshsl-ns = <60>; + cdns,tsd2d-ns = <60>; + cdns,tchsh-ns = <60>; + cdns,tslch-ns = <60>; + cdns,read-delay = <4>; + bootph-all; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "ospi.tiboot3"; + reg = <0x00 0x80000>; + }; + + partition@80000 { + label = "ospi.tispl"; + reg = <0x80000 0x200000>; + }; + + partition@280000 { + label = "ospi.u-boot"; + reg = <0x280000 0x400000>; + }; + + partition@680000 { + label = "ospi.env"; + reg = <0x680000 0x40000>; + }; + + partition@6c0000 { + label = "ospi.env.backup"; + reg = <0x6c0000 0x40000>; + }; + + partition@800000 { + label = "ospi.rootfs"; + reg = <0x800000 0x37c0000>; + }; + + partition@3fc0000 { + label = "ospi.phypattern"; + reg = <0x3fc0000 0x40000>; + }; + }; + }; + +}; + +&sdhci1 { + /* SD/MMC */ + vmmc-supply = <&vdd_mmc1>; + vqmmc-supply = <&vdd_sd_dv>; + pinctrl-names = "default"; + pinctrl-0 = <&main_mmc1_pins_default>; + ti,driver-strength-ohm = <50>; + disable-wp; + no-1-8-v; + status = "okay"; + bootph-all; +}; diff --git a/src/arm64/ti/k3-j722s.dtsi b/src/arm64/ti/k3-j722s.dtsi new file mode 100644 index 0000000..c75744e --- /dev/null +++ b/src/arm64/ti/k3-j722s.dtsi @@ -0,0 +1,89 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Device Tree Source for J722S SoC Family + * + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/soc/ti,sci_pm_domain.h> + +#include "k3-am62p5.dtsi" + +/ { + model = "Texas Instruments K3 J722S SoC"; + compatible = "ti,j722s"; + + cbass_main: bus@f0000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + + ranges = <0x00 0x000f0000 0x00 0x000f0000 0x00 0x00030000>, /* Main MMRs */ + <0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */ + <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */ + <0x00 0x00703000 0x00 0x00703000 0x00 0x00000200>, /* USB0 debug trace */ + <0x00 0x0070c000 0x00 0x0070c000 0x00 0x00000200>, /* USB1 debug trace */ + <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */ + <0x00 0x01000000 0x00 0x01000000 0x00 0x01b28400>, /* First peripheral window */ + <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */ + <0x00 0x0d000000 0x00 0x0d000000 0x00 0x00800000>, /* PCIE_0 */ + <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01d20000>, /* Second peripheral window */ + <0x00 0x0fd80000 0x00 0x0fd80000 0x00 0x00080000>, /* GPU */ + <0x00 0x0fd20000 0x00 0x0fd20000 0x00 0x00000100>, /* JPEGENC0_CORE */ + <0x00 0x0fd20200 0x00 0x0fd20200 0x00 0x00000200>, /* JPEGENC0_CORE_MMU */ + <0x00 0x20000000 0x00 0x20000000 0x00 0x0a008000>, /* Third peripheral window */ + <0x00 0x30040000 0x00 0x30040000 0x00 0x00080000>, /* PRUSS-M */ + <0x00 0x301C0000 0x00 0x301C0000 0x00 0x00001000>, /* DPHY-TX */ + <0x00 0x30101000 0x00 0x30101000 0x00 0x00080100>, /* CSI window */ + <0x00 0x30200000 0x00 0x30200000 0x00 0x00010000>, /* DSS */ + <0x00 0x30210000 0x00 0x30210000 0x00 0x00010000>, /* VPU */ + <0x00 0x30220000 0x00 0x30220000 0x00 0x00010000>, /* DSS1 */ + <0x00 0x30270000 0x00 0x30270000 0x00 0x00010000>, /* DSI-base1 */ + <0x00 0x30500000 0x00 0x30500000 0x00 0x00100000>, /* DSI-base2 */ + <0x00 0x31000000 0x00 0x31000000 0x00 0x00050000>, /* USB0 DWC3 Core window */ + <0x00 0x31200000 0x00 0x31200000 0x00 0x00040000>, /* USB1 DWC3 Core window */ + <0x00 0x40900000 0x00 0x40900000 0x00 0x00030000>, /* SA3UL */ + <0x00 0x43600000 0x00 0x43600000 0x00 0x00010000>, /* SA3 sproxy data */ + <0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */ + <0x00 0x44860000 0x00 0x44860000 0x00 0x00040000>, /* SA3 sproxy config */ + <0x00 0x48000000 0x00 0x48000000 0x00 0x06408000>, /* DMSS */ + <0x00 0x60000000 0x00 0x60000000 0x00 0x08000000>, /* FSS0 DAT1 */ + <0x00 0x68000000 0x00 0x68000000 0x00 0x08000000>, /* PCIe0 DAT0 */ + <0x00 0x70000000 0x00 0x70000000 0x00 0x00040000>, /* OCSRAM */ + <0x00 0x78400000 0x00 0x78400000 0x00 0x00008000>, /* MAIN R5FSS0 ATCM */ + <0x00 0x78500000 0x00 0x78500000 0x00 0x00008000>, /* MAIN R5FSS0 BTCM */ + <0x00 0x7e000000 0x00 0x7e000000 0x00 0x00200000>, /* C7X_0 L2SRAM */ + <0x00 0x7e200000 0x00 0x7e200000 0x00 0x00200000>, /* C7X_1 L2SRAM */ + <0x01 0x00000000 0x01 0x00000000 0x00 0x00310000>, /* A53 PERIPHBASE */ + <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS0 DAT3 */ + <0x06 0x00000000 0x06 0x00000000 0x01 0x00000000>, /* PCIe0 DAT1 */ + + /* MCU Domain Range */ + <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>, + <0x00 0x79000000 0x00 0x79000000 0x00 0x00008000>, + <0x00 0x79020000 0x00 0x79020000 0x00 0x00008000>, + <0x00 0x79100000 0x00 0x79100000 0x00 0x00040000>, + <0x00 0x79140000 0x00 0x79140000 0x00 0x00040000>, + + /* Wakeup Domain Range */ + <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, + <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, + <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>, + <0x00 0x78000000 0x00 0x78000000 0x00 0x00008000>, + <0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>; + }; +}; + +/* Main domain overrides */ + +&inta_main_dmss { + ti,interrupt-ranges = <7 71 21>; +}; + +&oc_sram { + reg = <0x00 0x70000000 0x00 0x40000>; + ranges = <0x00 0x00 0x70000000 0x40000>; +}; diff --git a/src/arm64/ti/k3-j784s4-evm.dts b/src/arm64/ti/k3-j784s4-evm.dts index f34b92a..81fd7af 100644 --- a/src/arm64/ti/k3-j784s4-evm.dts +++ b/src/arm64/ti/k3-j784s4-evm.dts @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* - * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/ * * EVM Board Schematics: https://www.ti.com/lit/zip/sprr458 */ @@ -31,6 +31,7 @@ memory@80000000 { device_type = "memory"; + bootph-all; /* 32G RAM */ reg = <0x00 0x80000000 0x00 0x80000000>, <0x08 0x80000000 0x07 0x80000000>; @@ -296,6 +297,13 @@ >; }; + main_i2c5_pins_default: main-i2c5-default-pins { + pinctrl-single,pins = < + J784S4_IOPAD(0x01c, PIN_INPUT, 8) /* (AG34) MCAN15_TX.I2C5_SCL */ + J784S4_IOPAD(0x018, PIN_INPUT, 8) /* (AK36) MCAN14_RX.I2C5_SDA */ + >; + }; + main_mmc1_pins_default: main-mmc1-default-pins { bootph-all; pinctrl-single,pins = < @@ -335,8 +343,6 @@ wkup_uart0_pins_default: wkup-uart0-default-pins { bootph-all; pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x070, PIN_INPUT, 0) /* (L37) WKUP_GPIO0_6.WKUP_UART0_CTSn */ - J721S2_WKUP_IOPAD(0x074, PIN_INPUT, 0) /* (L36) WKUP_GPIO0_7.WKUP_UART0_RTSn */ J721S2_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (K35) WKUP_UART0_RXD */ J721S2_WKUP_IOPAD(0x04c, PIN_INPUT, 0) /* (K34) WKUP_UART0_TXD */ >; @@ -760,6 +766,24 @@ }; }; +&main_i2c5 { + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c5_pins_default>; + clock-frequency = <400000>; + status = "okay"; + + exp5: gpio@20 { + compatible = "ti,tca6408"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "CSI2_EXP_RSTZ", "CSI2_EXP_A_GPIO0", + "CSI2_EXP_A_GPIO1", "CSI2_EXP_A_GPIO3", + "CSI2_EXP_B_GPIO1", "CSI2_EXP_B_GPIO2", + "CSI2_EXP_B_GPIO3", "CSI2_EXP_B_GPIO4"; + }; +}; + &main_sdhci0 { bootph-all; /* eMMC */ diff --git a/src/arm64/ti/k3-j784s4-main.dtsi b/src/arm64/ti/k3-j784s4-main.dtsi index f2b720e..b67c374 100644 --- a/src/arm64/ti/k3-j784s4-main.dtsi +++ b/src/arm64/ti/k3-j784s4-main.dtsi @@ -1,8 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree Source for J784S4 SoC Family Main Domain peripherals * - * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/ */ #include <dt-bindings/mux/mux.h> @@ -52,12 +52,12 @@ compatible = "reg-mux"; reg = <0x00004080 0x30>; #mux-control-cells = <1>; - mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */ - <0x4088 0x3>, <0x408c 0x3>, /* SERDES0 lane2/3 select */ - <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */ - <0x4098 0x3>, <0x409c 0x3>, /* SERDES1 lane2/3 select */ - <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */ - <0x40a8 0x3>, <0x40ac 0x3>; /* SERDES2 lane2/3 select */ + mux-reg-masks = <0x0 0x3>, <0x4 0x3>, /* SERDES0 lane0/1 select */ + <0x8 0x3>, <0xc 0x3>, /* SERDES0 lane2/3 select */ + <0x10 0x3>, <0x14 0x3>, /* SERDES1 lane0/1 select */ + <0x18 0x3>, <0x1c 0x3>, /* SERDES1 lane2/3 select */ + <0x20 0x3>, <0x24 0x3>, /* SERDES2 lane0/1 select */ + <0x28 0x3>, <0x2c 0x3>; /* SERDES2 lane2/3 select */ idle-states = <J784S4_SERDES0_LANE0_PCIE1_LANE0>, <J784S4_SERDES0_LANE1_PCIE1_LANE1>, <J784S4_SERDES0_LANE2_IP3_UNUSED>, @@ -662,6 +662,204 @@ status = "disabled"; }; + ti_csi2rx0: ticsi2rx@4500000 { + compatible = "ti,j721e-csi2rx-shim"; + reg = <0x00 0x04500000 0x00 0x00001000>; + ranges; + #address-cells = <2>; + #size-cells = <2>; + dmas = <&main_bcdma_csi 0 0x4940 0>; + dma-names = "rx0"; + power-domains = <&k3_pds 72 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + + cdns_csi2rx0: csi-bridge@4504000 { + compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; + reg = <0x00 0x04504000 0x00 0x00001000>; + clocks = <&k3_clks 72 2>, <&k3_clks 72 0>, <&k3_clks 72 2>, + <&k3_clks 72 2>, <&k3_clks 72 3>, <&k3_clks 72 3>; + clock-names = "sys_clk", "p_clk", "pixel_if0_clk", + "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; + phys = <&dphy0>; + phy-names = "dphy"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi0_port0: port@0 { + reg = <0>; + status = "disabled"; + }; + + csi0_port1: port@1 { + reg = <1>; + status = "disabled"; + }; + + csi0_port2: port@2 { + reg = <2>; + status = "disabled"; + }; + + csi0_port3: port@3 { + reg = <3>; + status = "disabled"; + }; + + csi0_port4: port@4 { + reg = <4>; + status = "disabled"; + }; + }; + }; + }; + + ti_csi2rx1: ticsi2rx@4510000 { + compatible = "ti,j721e-csi2rx-shim"; + reg = <0x00 0x04510000 0x00 0x1000>; + ranges; + #address-cells = <2>; + #size-cells = <2>; + dmas = <&main_bcdma_csi 0 0x4960 0>; + dma-names = "rx0"; + power-domains = <&k3_pds 73 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + + cdns_csi2rx1: csi-bridge@4514000 { + compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; + reg = <0x00 0x04514000 0x00 0x00001000>; + clocks = <&k3_clks 73 2>, <&k3_clks 73 0>, <&k3_clks 73 2>, + <&k3_clks 73 2>, <&k3_clks 73 3>, <&k3_clks 73 3>; + clock-names = "sys_clk", "p_clk", "pixel_if0_clk", + "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; + phys = <&dphy1>; + phy-names = "dphy"; + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi1_port0: port@0 { + reg = <0>; + status = "disabled"; + }; + + csi1_port1: port@1 { + reg = <1>; + status = "disabled"; + }; + + csi1_port2: port@2 { + reg = <2>; + status = "disabled"; + }; + + csi1_port3: port@3 { + reg = <3>; + status = "disabled"; + }; + + csi1_port4: port@4 { + reg = <4>; + status = "disabled"; + }; + }; + }; + }; + + ti_csi2rx2: ticsi2rx@4520000 { + compatible = "ti,j721e-csi2rx-shim"; + reg = <0x00 0x04520000 0x00 0x00001000>; + ranges; + #address-cells = <2>; + #size-cells = <2>; + dmas = <&main_bcdma_csi 0 0x4980 0>; + dma-names = "rx0"; + power-domains = <&k3_pds 74 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + + cdns_csi2rx2: csi-bridge@4524000 { + compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; + reg = <0x00 0x04524000 0x00 0x00001000>; + clocks = <&k3_clks 74 2>, <&k3_clks 74 0>, <&k3_clks 74 2>, + <&k3_clks 74 2>, <&k3_clks 74 3>, <&k3_clks 74 3>; + clock-names = "sys_clk", "p_clk", "pixel_if0_clk", + "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; + phys = <&dphy2>; + phy-names = "dphy"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi2_port0: port@0 { + reg = <0>; + status = "disabled"; + }; + + csi2_port1: port@1 { + reg = <1>; + status = "disabled"; + }; + + csi2_port2: port@2 { + reg = <2>; + status = "disabled"; + }; + + csi2_port3: port@3 { + reg = <3>; + status = "disabled"; + }; + + csi2_port4: port@4 { + reg = <4>; + status = "disabled"; + }; + }; + }; + }; + + dphy0: phy@4580000 { + compatible = "cdns,dphy-rx"; + reg = <0x00 0x04580000 0x00 0x00001100>; + #phy-cells = <0>; + power-domains = <&k3_pds 212 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + + dphy1: phy@4590000 { + compatible = "cdns,dphy-rx"; + reg = <0x00 0x04590000 0x00 0x00001100>; + #phy-cells = <0>; + power-domains = <&k3_pds 213 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + + dphy2: phy@45a0000 { + compatible = "cdns,dphy-rx"; + reg = <0x00 0x045a0000 0x00 0x00001100>; + #phy-cells = <0>; + power-domains = <&k3_pds 214 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + + vpu0: video-codec@4210000 { + compatible = "ti,j721s2-wave521c", "cnm,wave521c"; + reg = <0x00 0x4210000 0x00 0x10000>; + interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 241 2>; + power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>; + }; + + vpu1: video-codec@4220000 { + compatible = "ti,j721s2-wave521c", "cnm,wave521c"; + reg = <0x00 0x4220000 0x00 0x10000>; + interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 242 2>; + power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>; + }; + main_sdhci0: mmc@4f80000 { compatible = "ti,j721e-sdhci-8bit"; reg = <0x00 0x04f80000 0x00 0x1000>, @@ -1224,7 +1422,6 @@ ti,sci-dev-id = <281>; ti,sci-rm-range-rchan = <0x21>; ti,sci-rm-range-tchan = <0x22>; - status = "disabled"; }; cpts@310d0000 { diff --git a/src/arm64/ti/k3-j784s4-mcu-wakeup.dtsi b/src/arm64/ti/k3-j784s4-mcu-wakeup.dtsi index 3902a92..77a8d99 100644 --- a/src/arm64/ti/k3-j784s4-mcu-wakeup.dtsi +++ b/src/arm64/ti/k3-j784s4-mcu-wakeup.dtsi @@ -1,8 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree Source for J784S4 SoC Family MCU/WAKEUP Domain peripherals * - * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/ */ &cbass_mcu_wakeup { @@ -628,7 +628,7 @@ compatible = "ti,j7200-vtm"; reg = <0x00 0x42040000 0x00 0x350>, <0x00 0x42050000 0x00 0x350>; - power-domains = <&k3_pds 154 TI_SCI_PD_SHARED>; + power-domains = <&k3_pds 243 TI_SCI_PD_SHARED>; #thermal-sensor-cells = <1>; }; diff --git a/src/arm64/ti/k3-j784s4-thermal.dtsi b/src/arm64/ti/k3-j784s4-thermal.dtsi index f7b1a15..e3ef61c 100644 --- a/src/arm64/ti/k3-j784s4-thermal.dtsi +++ b/src/arm64/ti/k3-j784s4-thermal.dtsi @@ -1,4 +1,7 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ + */ #include <dt-bindings/thermal/thermal.h> diff --git a/src/arm64/ti/k3-j784s4.dtsi b/src/arm64/ti/k3-j784s4.dtsi index 4398c3a..6e2e92f 100644 --- a/src/arm64/ti/k3-j784s4.dtsi +++ b/src/arm64/ti/k3-j784s4.dtsi @@ -1,10 +1,10 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree Source for J784S4 SoC Family * * TRM (SPRUJ43 JULY 2022): https://www.ti.com/lit/zip/spruj52 * - * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/ * */ @@ -235,6 +235,8 @@ ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */ <0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */ <0x00 0x01000000 0x00 0x01000000 0x00 0x0d000000>, /* Most peripherals */ + <0x00 0x04210000 0x00 0x04210000 0x00 0x00010000>, /* VPU0 */ + <0x00 0x04220000 0x00 0x04220000 0x00 0x00010000>, /* VPU1 */ <0x00 0x0d000000 0x00 0x0d000000 0x00 0x01000000>, /* PCIe Core*/ <0x00 0x10000000 0x00 0x10000000 0x00 0x08000000>, /* PCIe0 DAT0 */ <0x00 0x18000000 0x00 0x18000000 0x00 0x08000000>, /* PCIe1 DAT0 */ diff --git a/src/arm64/ti/k3-pinctrl.h b/src/arm64/ti/k3-pinctrl.h index 2a4e0e0..4cd2df4 100644 --- a/src/arm64/ti/k3-pinctrl.h +++ b/src/arm64/ti/k3-pinctrl.h @@ -1,9 +1,9 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ /* * This header provides constants for pinctrl bindings for TI's K3 SoC * family. * - * Copyright (C) 2018-2023 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2018-2024 Texas Instruments Incorporated - https://www.ti.com/ */ #ifndef DTS_ARM64_TI_K3_PINCTRL_H #define DTS_ARM64_TI_K3_PINCTRL_H @@ -59,6 +59,9 @@ #define J721S2_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) #define J721S2_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) +#define J722S_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) +#define J722S_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) + #define J784S4_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) #define J784S4_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) diff --git a/src/arm64/ti/k3-serdes.h b/src/arm64/ti/k3-serdes.h index 21b4886..a011ad8 100644 --- a/src/arm64/ti/k3-serdes.h +++ b/src/arm64/ti/k3-serdes.h @@ -1,8 +1,8 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ /* * This header provides constants for SERDES MUX for TI SoCs * - * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ */ #ifndef DTS_ARM64_TI_K3_SERDES_H |