diff options
author | Marek Szyprowski <m.szyprowski@samsung.com> | 2020-06-03 14:43:40 +0200 |
---|---|---|
committer | Tom Rini <trini@konsulko.com> | 2020-07-10 14:10:43 -0400 |
commit | 69be8fd1649aaa02087cfe86add1bb34ec0850ec (patch) | |
tree | f33030eb766004da7e455e5ef301436890dcd491 /include | |
parent | 506d52308a2f5de48c2b9a08229fee9a0ee2842a (diff) | |
download | u-boot-69be8fd1649aaa02087cfe86add1bb34ec0850ec.zip u-boot-69be8fd1649aaa02087cfe86add1bb34ec0850ec.tar.gz u-boot-69be8fd1649aaa02087cfe86add1bb34ec0850ec.tar.bz2 |
powerpc: move ADDR_MAP to Kconfig
Move ADDR_MAP related config options from include/configs/*.h to the
proper place in lib/Kconfig. This has been done using
./tools/moveconfig.py and manual inspection of the generated changes.
This is a preparation to use ADDR_MAP helper on ARM 32bit Raspberry Pi4
board for mapping the PCIe XHCI MMIO, which is above the 4GiB identity
mapping limit.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'include')
-rw-r--r-- | include/configs/MPC8548CDS.h | 5 | ||||
-rw-r--r-- | include/configs/MPC8572DS.h | 5 | ||||
-rw-r--r-- | include/configs/MPC8641HPCN.h | 2 | ||||
-rw-r--r-- | include/configs/P1010RDB.h | 5 | ||||
-rw-r--r-- | include/configs/P2041RDB.h | 5 | ||||
-rw-r--r-- | include/configs/T102xRDB.h | 5 | ||||
-rw-r--r-- | include/configs/T104xRDB.h | 3 | ||||
-rw-r--r-- | include/configs/T208xQDS.h | 5 | ||||
-rw-r--r-- | include/configs/T208xRDB.h | 5 | ||||
-rw-r--r-- | include/configs/T4240RDB.h | 3 | ||||
-rw-r--r-- | include/configs/controlcenterd.h | 5 | ||||
-rw-r--r-- | include/configs/corenet_ds.h | 5 | ||||
-rw-r--r-- | include/configs/cyrus.h | 5 | ||||
-rw-r--r-- | include/configs/kmp204x.h | 3 | ||||
-rw-r--r-- | include/configs/p1_p2_rdb_pc.h | 5 | ||||
-rw-r--r-- | include/configs/qemu-ppce500.h | 3 | ||||
-rw-r--r-- | include/configs/t4qds.h | 3 |
17 files changed, 0 insertions, 72 deletions
diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index 1cb62ae..4b40129 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -43,11 +43,6 @@ extern unsigned long get_clock_freq(void); */ #define CONFIG_ENABLE_36BIT_PHYS 1 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_ADDR_MAP -#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ -#endif - #define CONFIG_SYS_CCSRBAR 0xe0000000 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index b4e5e3b..429dae1 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -45,11 +45,6 @@ #define CONFIG_ENABLE_36BIT_PHYS 1 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_ADDR_MAP 1 -#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ -#endif - /* * Config the L2 Cache as L2 SRAM */ diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index a7f02ae..1560b61 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -19,7 +19,6 @@ /* High Level Configuration Options */ #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ -#define CONFIG_ADDR_MAP 1 /* Use addr map */ /* * default CCSRBAR is at 0xff700000 @@ -47,7 +46,6 @@ #define CONFIG_ENV_OVERWRITE #define CONFIG_BAT_RW 1 /* Use common BAT rw code */ -#define CONFIG_SYS_NUM_ADDR_MAP 8 /* Number of addr map slots = 8 dbats */ #define CONFIG_ALTIVEC 1 diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index 8f709a6..fc74d57 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -196,11 +196,6 @@ #define CONFIG_ENABLE_36BIT_PHYS -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_ADDR_MAP 1 -#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ -#endif - /* DDR Setup */ #define CONFIG_SYS_DDR_RAW_TIMING #define CONFIG_DDR_SPD diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index 94cbe10..c6a64ee 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -70,11 +70,6 @@ unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_ENABLE_36BIT_PHYS -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_ADDR_MAP -#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ -#endif - #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ /* diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index f5d9657..efd9b6b 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -17,11 +17,6 @@ #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ #define CONFIG_ENABLE_36BIT_PHYS -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_ADDR_MAP 1 -#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ -#endif - #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index 4237dfc..8f9de56 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -186,9 +186,6 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg #define CONFIG_ENABLE_36BIT_PHYS -#define CONFIG_ADDR_MAP -#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ - /* * Config the L3 Cache as L3 SRAM */ diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index c54f7f5..f32e668 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -26,11 +26,6 @@ #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ #define CONFIG_ENABLE_36BIT_PHYS -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_ADDR_MAP 1 -#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ -#endif - #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS #define CONFIG_ENV_OVERWRITE diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index 70eafc3..e666e4f 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -20,11 +20,6 @@ #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ #define CONFIG_ENABLE_36BIT_PHYS -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_ADDR_MAP 1 -#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ -#endif - #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS #define CONFIG_ENV_OVERWRITE diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index 9832f85..ebe7a9c 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -80,9 +80,6 @@ #define CONFIG_ENABLE_36BIT_PHYS -#define CONFIG_ADDR_MAP -#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ - /* * Config the L3 Cache as L3 SRAM */ diff --git a/include/configs/controlcenterd.h b/include/configs/controlcenterd.h index 823586c..512d8e1 100644 --- a/include/configs/controlcenterd.h +++ b/include/configs/controlcenterd.h @@ -41,11 +41,6 @@ #define CONFIG_ENABLE_36BIT_PHYS -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_ADDR_MAP -#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ -#endif - #define CONFIG_L2_CACHE #define CONFIG_BTB diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index a49f905..d7812bd 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -84,11 +84,6 @@ #define CONFIG_ENABLE_36BIT_PHYS -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_ADDR_MAP -#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ -#endif - #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ /* diff --git a/include/configs/cyrus.h b/include/configs/cyrus.h index 052e601..b587cb8 100644 --- a/include/configs/cyrus.h +++ b/include/configs/cyrus.h @@ -70,11 +70,6 @@ #define CONFIG_ENABLE_36BIT_PHYS -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_ADDR_MAP -#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ -#endif - /* test POST memory test */ #undef CONFIG_POST diff --git a/include/configs/kmp204x.h b/include/configs/kmp204x.h index e43b2f7..6cd77ed 100644 --- a/include/configs/kmp204x.h +++ b/include/configs/kmp204x.h @@ -64,9 +64,6 @@ unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_ENABLE_36BIT_PHYS -#define CONFIG_ADDR_MAP -#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ - #define CONFIG_POST CONFIG_SYS_POST_MEM_REGIONS /* POST memory regions test */ /* diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 6b57be9..a33f2f3 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -233,11 +233,6 @@ #define CONFIG_ENABLE_36BIT_PHYS -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_ADDR_MAP 1 -#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ -#endif - #define CONFIG_SYS_CCSRBAR 0xffe00000 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR diff --git a/include/configs/qemu-ppce500.h b/include/configs/qemu-ppce500.h index 03b0896..b3ec430 100644 --- a/include/configs/qemu-ppce500.h +++ b/include/configs/qemu-ppce500.h @@ -21,9 +21,6 @@ #define CONFIG_ENABLE_36BIT_PHYS -#define CONFIG_ADDR_MAP -#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ - /* Needed to fill the ccsrbar pointer */ /* Virtual address to CCSRBAR */ diff --git a/include/configs/t4qds.h b/include/configs/t4qds.h index 3da7ee7..1f6ae46 100644 --- a/include/configs/t4qds.h +++ b/include/configs/t4qds.h @@ -42,9 +42,6 @@ #define CONFIG_ENABLE_36BIT_PHYS -#define CONFIG_ADDR_MAP -#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ - /* * Config the L3 Cache as L3 SRAM */ |