diff options
author | Tom Rini <trini@konsulko.com> | 2022-04-27 09:19:41 -0400 |
---|---|---|
committer | Tom Rini <trini@konsulko.com> | 2022-04-27 09:19:41 -0400 |
commit | 8b2b125e95c44bb007b4573945f4aedb8a56222c (patch) | |
tree | 0eed8a3f6e53131583134e00258984f144845f31 /include | |
parent | 24df831cd4ab70fe526e561b07ca37c8b8aa544c (diff) | |
parent | 182d45ddff8944e291c805d94a01d7dd29d0d3b6 (diff) | |
download | u-boot-WIP/27Apr2022.zip u-boot-WIP/27Apr2022.tar.gz u-boot-WIP/27Apr2022.tar.bz2 |
Merge https://gitlab.denx.de/u-boot/custodians/u-boot-mpc85xxWIP/27Apr2022
fsl-qoriq: Fixes and updates on fsl-layerscape
mpc85xx: fixes and code cleanup
Diffstat (limited to 'include')
-rw-r--r-- | include/configs/P1010RDB.h | 4 | ||||
-rw-r--r-- | include/configs/T102xRDB.h | 3 | ||||
-rw-r--r-- | include/configs/T104xRDB.h | 3 | ||||
-rw-r--r-- | include/configs/T208xQDS.h | 3 | ||||
-rw-r--r-- | include/configs/T208xRDB.h | 3 | ||||
-rw-r--r-- | include/configs/ls1012a2g5rdb.h | 1 | ||||
-rw-r--r-- | include/configs/ls1012afrdm.h | 2 | ||||
-rw-r--r-- | include/configs/ls1012afrwy.h | 1 | ||||
-rw-r--r-- | include/configs/ls1012aqds.h | 1 | ||||
-rw-r--r-- | include/configs/ls1012ardb.h | 1 | ||||
-rw-r--r-- | include/configs/ls1021atsn.h | 1 | ||||
-rw-r--r-- | include/configs/ls1021atwr.h | 4 | ||||
-rw-r--r-- | include/configs/ls1028aqds.h | 3 | ||||
-rw-r--r-- | include/configs/ls1028ardb.h | 3 | ||||
-rw-r--r-- | include/configs/ls1043a_common.h | 1 | ||||
-rw-r--r-- | include/configs/ls1046a_common.h | 1 | ||||
-rw-r--r-- | include/configs/ls1088ardb.h | 2 | ||||
-rw-r--r-- | include/configs/ls2080ardb.h | 2 | ||||
-rw-r--r-- | include/configs/lx2160a_common.h | 1 | ||||
-rw-r--r-- | include/configs/p1_p2_rdb_pc.h | 48 | ||||
-rw-r--r-- | include/fsl_esdhc.h | 1 |
21 files changed, 54 insertions, 35 deletions
diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index 0d8f13e..0c19b92 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -81,6 +81,10 @@ #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) #define CONFIG_SYS_NAND_U_BOOT_DST 0xD0000000 #define CONFIG_SYS_NAND_U_BOOT_START 0xD0000000 +#else +#ifndef CONFIG_MPC85XX_HAVE_RESET_VECTOR +#define CONFIG_SYS_MPC85XX_NO_RESETVEC +#endif #endif #define CONFIG_SPL_PAD_TO 0x20000 #define CONFIG_TPL_PAD_TO 0x20000 diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index bedd931..e7cc39e 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -36,6 +36,9 @@ #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000 +#ifndef CONFIG_MPC85XX_HAVE_RESET_VECTOR +#define CONFIG_SYS_MPC85XX_NO_RESETVEC +#endif #endif #ifdef CONFIG_SPIFLASH diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index 8ef6068..de31f69 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -40,6 +40,9 @@ #endif #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000 +#ifndef CONFIG_MPC85XX_HAVE_RESET_VECTOR +#define CONFIG_SYS_MPC85XX_NO_RESETVEC +#endif #endif #ifdef CONFIG_SPIFLASH diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 5a338f7..82e0fc4 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -44,6 +44,9 @@ #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 +#ifndef CONFIG_MPC85XX_HAVE_RESET_VECTOR +#define CONFIG_SYS_MPC85XX_NO_RESETVEC +#endif #endif #ifdef CONFIG_SPIFLASH diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index 3c13905..9438544 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -39,6 +39,9 @@ #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 +#ifndef CONFIG_MPC85XX_HAVE_RESET_VECTOR +#define CONFIG_SYS_MPC85XX_NO_RESETVEC +#endif #endif #ifdef CONFIG_SPIFLASH diff --git a/include/configs/ls1012a2g5rdb.h b/include/configs/ls1012a2g5rdb.h index 835eca7..f0248e6 100644 --- a/include/configs/ls1012a2g5rdb.h +++ b/include/configs/ls1012a2g5rdb.h @@ -19,7 +19,6 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "verify=no\0" \ "initrd_high=0xffffffffffffffff\0" \ - "fdt_addr=0x00f00000\0" \ "kernel_addr=0x01000000\0" \ "kernelheader_addr=0x800000\0" \ "scriptaddr=0x80000000\0" \ diff --git a/include/configs/ls1012afrdm.h b/include/configs/ls1012afrdm.h index 44518cd..cb79d63 100644 --- a/include/configs/ls1012afrdm.h +++ b/include/configs/ls1012afrdm.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2021 NXP */ #ifndef __LS1012ARDB_H__ @@ -21,7 +22,6 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "verify=no\0" \ "fdt_high=0xffffffffffffffff\0" \ - "fdt_addr=0x00f00000\0" \ "kernel_addr=0x01000000\0" \ "scriptaddr=0x80000000\0" \ "fdtheader_addr_r=0x80100000\0" \ diff --git a/include/configs/ls1012afrwy.h b/include/configs/ls1012afrwy.h index 16ce892..a1d23b6 100644 --- a/include/configs/ls1012afrwy.h +++ b/include/configs/ls1012afrwy.h @@ -35,7 +35,6 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "verify=no\0" \ "initrd_high=0xffffffffffffffff\0" \ - "fdt_addr=0x00f00000\0" \ "kernel_addr=0x01000000\0" \ "kernel_size_sd=0x16000\0" \ "kernelhdr_size_sd=0x10\0" \ diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h index e7a0294..b599236 100644 --- a/include/configs/ls1012aqds.h +++ b/include/configs/ls1012aqds.h @@ -89,7 +89,6 @@ #undef CONFIG_EXTRA_ENV_SETTINGS #define CONFIG_EXTRA_ENV_SETTINGS \ "verify=no\0" \ - "fdt_addr=0x00f00000\0" \ "kernel_addr=0x01000000\0" \ "kernelheader_addr=0x600000\0" \ "scriptaddr=0x80000000\0" \ diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h index 2490ba3..c57b598 100644 --- a/include/configs/ls1012ardb.h +++ b/include/configs/ls1012ardb.h @@ -44,7 +44,6 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "verify=no\0" \ "initrd_high=0xffffffffffffffff\0" \ - "fdt_addr=0x00f00000\0" \ "kernel_addr=0x01000000\0" \ "kernelheader_addr=0x600000\0" \ "scriptaddr=0x80000000\0" \ diff --git a/include/configs/ls1021atsn.h b/include/configs/ls1021atsn.h index 546c4fc..09168a2 100644 --- a/include/configs/ls1021atsn.h +++ b/include/configs/ls1021atsn.h @@ -114,7 +114,6 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ "initrd_high=0xffffffff\0" \ - "fdt_addr=0x64f00000\0" \ "kernel_addr=0x61000000\0" \ "kernelheader_addr=0x60800000\0" \ "scriptaddr=0x80000000\0" \ diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index b4383d4..b36c8dc 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2014 Freescale Semiconductor, Inc. - * Copyright 2019 NXP + * Copyright 2019, 2021 NXP */ #ifndef __CONFIG_H @@ -209,7 +209,6 @@ "bootargs=root=/dev/ram0 rw console=ttyLP0,115200 " \ "cma=64M@0x0-0xb0000000\0" \ "initrd_high=0xffffffff\0" \ - "fdt_addr=0x64f00000\0" \ "kernel_addr=0x65000000\0" \ "scriptaddr=0x80000000\0" \ "scripthdraddr=0x80080000\0" \ @@ -266,7 +265,6 @@ "bootargs=root=/dev/ram0 rw console=ttyS0,115200 " \ "cma=64M@0x0-0xb0000000\0" \ "initrd_high=0xffffffff\0" \ - "fdt_addr=0x64f00000\0" \ "kernel_addr=0x61000000\0" \ "kernelheader_addr=0x60800000\0" \ "scriptaddr=0x80000000\0" \ diff --git a/include/configs/ls1028aqds.h b/include/configs/ls1028aqds.h index b9c0594..35363cc 100644 --- a/include/configs/ls1028aqds.h +++ b/include/configs/ls1028aqds.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright 2019-2020 NXP + * Copyright 2019-2021 NXP */ #ifndef __LS1028A_QDS_H @@ -68,7 +68,6 @@ "hwconfig=fsl_ddr:bank_intlv=auto\0" \ "ramdisk_addr=0x800000\0" \ "ramdisk_size=0x2000000\0" \ - "fdt_addr=0x00f00000\0" \ "kernel_addr=0x01000000\0" \ "scriptaddr=0x80000000\0" \ "scripthdraddr=0x80080000\0" \ diff --git a/include/configs/ls1028ardb.h b/include/configs/ls1028ardb.h index 15ac1f5..9122378 100644 --- a/include/configs/ls1028ardb.h +++ b/include/configs/ls1028ardb.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright 2019 NXP + * Copyright 2019, 2021 NXP */ #ifndef __LS1028A_RDB_H @@ -64,7 +64,6 @@ "ramdisk_addr=0x800000\0" \ "ramdisk_size=0x2000000\0" \ "bootm_size=0x10000000\0" \ - "fdt_addr=0x00f00000\0" \ "kernel_addr=0x01000000\0" \ "scriptaddr=0x80000000\0" \ "scripthdraddr=0x80080000\0" \ diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index 61c6d45..26db8ff 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -173,7 +173,6 @@ "hwconfig=fsl_ddr:bank_intlv=auto\0" \ "fdt_high=0xffffffffffffffff\0" \ "initrd_high=0xffffffffffffffff\0" \ - "fdt_addr=0x64f00000\0" \ "kernel_addr=0x61000000\0" \ "scriptaddr=0x80000000\0" \ "scripthdraddr=0x80080000\0" \ diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h index f9279e4..fb2011a 100644 --- a/include/configs/ls1046a_common.h +++ b/include/configs/ls1046a_common.h @@ -165,7 +165,6 @@ "ramdisk_addr=0x800000\0" \ "ramdisk_size=0x2000000\0" \ "bootm_size=0x10000000\0" \ - "fdt_addr=0x64f00000\0" \ "kernel_addr=0x61000000\0" \ "scriptaddr=0x80000000\0" \ "scripthdraddr=0x80080000\0" \ diff --git a/include/configs/ls1088ardb.h b/include/configs/ls1088ardb.h index 693a2f6..c690030 100644 --- a/include/configs/ls1088ardb.h +++ b/include/configs/ls1088ardb.h @@ -271,7 +271,6 @@ "ramdisk_size=0x2000000\0" \ "fdt_high=0xa0000000\0" \ "initrd_high=0xffffffffffffffff\0" \ - "fdt_addr=0x64f00000\0" \ "kernel_addr=0x1000000\0" \ "kernel_addr_sd=0x8000\0" \ "kernelhdr_addr_sd=0x3000\0" \ @@ -340,7 +339,6 @@ "ramdisk_size=0x2000000\0" \ "fdt_high=0xa0000000\0" \ "initrd_high=0xffffffffffffffff\0" \ - "fdt_addr=0x64f00000\0" \ "kernel_addr=0x1000000\0" \ "kernel_addr_sd=0x8000\0" \ "kernelhdr_addr_sd=0x3000\0" \ diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h index de269f4..52a48bd 100644 --- a/include/configs/ls2080ardb.h +++ b/include/configs/ls2080ardb.h @@ -323,7 +323,6 @@ "ramdisk_size=0x2000000\0" \ "fdt_high=0xa0000000\0" \ "initrd_high=0xffffffffffffffff\0" \ - "fdt_addr=0x64f00000\0" \ "kernel_addr=0x581000000\0" \ "kernel_start=0x1000000\0" \ "kernelheader_start=0x800000\0" \ @@ -386,7 +385,6 @@ "ramdisk_size=0x2000000\0" \ "fdt_high=0xa0000000\0" \ "initrd_high=0xffffffffffffffff\0" \ - "fdt_addr=0x64f00000\0" \ "kernel_addr=0x581000000\0" \ "kernel_start=0x1000000\0" \ "kernelheader_start=0x600000\0" \ diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h index d569014..aaba8fc 100644 --- a/include/configs/lx2160a_common.h +++ b/include/configs/lx2160a_common.h @@ -164,7 +164,6 @@ "ramdisk_size=0x2000000\0" \ "fdt_high=0xa0000000\0" \ "initrd_high=0xffffffffffffffff\0" \ - "fdt_addr=0x64f00000\0" \ "kernel_start=0x1000000\0" \ "kernelheader_start=0x600000\0" \ "scriptaddr=0x80000000\0" \ diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 17b9021..f6ecf2a 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -21,6 +21,9 @@ #define __SW_BOOT_SD 0x9c #define __SW_BOOT_NAND 0xec #define __SW_BOOT_PCIE 0x6c +#define __SW_NOR_BANK_MASK 0xfd +#define __SW_NOR_BANK_UP 0x00 +#define __SW_NOR_BANK_LO 0x02 #define CONFIG_SYS_L2_SIZE (256 << 10) #endif @@ -46,6 +49,9 @@ #define __SW_BOOT_SD 0x24 #define __SW_BOOT_NAND 0x44 #define __SW_BOOT_PCIE 0x74 +#define __SW_NOR_BANK_MASK 0xfd +#define __SW_NOR_BANK_UP 0x00 +#define __SW_NOR_BANK_LO 0x02 #define CONFIG_SYS_L2_SIZE (256 << 10) /* * Dynamic MTD Partition support with mtdparts @@ -57,9 +63,13 @@ #define __SW_BOOT_MASK 0x03 #define __SW_BOOT_NOR 0xc8 #define __SW_BOOT_SPI 0x28 -#define __SW_BOOT_SD 0x68 /* or 0x18 */ +#define __SW_BOOT_SD 0x68 +#define __SW_BOOT_SD2 0x18 #define __SW_BOOT_NAND 0xe8 #define __SW_BOOT_PCIE 0xa8 +#define __SW_NOR_BANK_MASK 0xfd +#define __SW_NOR_BANK_UP 0x00 +#define __SW_NOR_BANK_LO 0x02 #define CONFIG_SYS_L2_SIZE (512 << 10) /* * Dynamic MTD Partition support with mtdparts @@ -111,6 +121,10 @@ #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000 #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000 +#else +#ifndef CONFIG_MPC85XX_HAVE_RESET_VECTOR +#define CONFIG_SYS_MPC85XX_NO_RESETVEC +#endif #endif /* not CONFIG_TPL_BUILD */ #define CONFIG_SPL_PAD_TO 0x20000 @@ -320,7 +334,7 @@ /* Vsc7385 switch */ #ifdef CONFIG_VSC7385_ENET -#define __VSCFW_ADDR "vscfw_addr=ef000000" +#define __VSCFW_ADDR "vscfw_addr=ef000000\0" #define CONFIG_SYS_VSC7385_BASE 0xffb00000 #ifdef CONFIG_PHYS_64BIT @@ -339,6 +353,10 @@ #define CONFIG_VSC7385_IMAGE_SIZE 8192 #endif +#ifndef __VSCFW_ADDR +#define __VSCFW_ADDR "" +#endif + /* * Config the L2 Cache as L2 SRAM */ @@ -526,28 +544,28 @@ #ifdef __SW_BOOT_NOR #define __NOR_RST_CMD \ -norboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NOR 1; \ -i2c mw 18 3 __SW_BOOT_MASK 1; reset +norboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_NOR 1; \ +i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset #endif #ifdef __SW_BOOT_SPI #define __SPI_RST_CMD \ -spiboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SPI 1; \ -i2c mw 18 3 __SW_BOOT_MASK 1; reset +spiboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_SPI 1; \ +i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset #endif #ifdef __SW_BOOT_SD #define __SD_RST_CMD \ -sdboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SD 1; \ -i2c mw 18 3 __SW_BOOT_MASK 1; reset +sdboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_SD 1; \ +i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset #endif #ifdef __SW_BOOT_NAND #define __NAND_RST_CMD \ -nandboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NAND 1; \ -i2c mw 18 3 __SW_BOOT_MASK 1; reset +nandboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_NAND 1; \ +i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset #endif #ifdef __SW_BOOT_PCIE #define __PCIE_RST_CMD \ -pciboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_PCIE 1; \ -i2c mw 18 3 __SW_BOOT_MASK 1; reset +pciboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_PCIE 1; \ +i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset #endif #define CONFIG_EXTRA_ENV_SETTINGS \ @@ -574,9 +592,9 @@ i2c mw 18 3 __SW_BOOT_MASK 1; reset "nandbootaddr=100000\0" \ "nandfdtaddr=80000\0" \ "ramdisk_size=120000\0" \ -"map_lowernorbank=i2c dev 1; i2c mw 18 1 02 1; i2c mw 18 3 fd 1\0" \ -"map_uppernorbank=i2c dev 1; i2c mw 18 1 00 1; i2c mw 18 3 fd 1\0" \ -__stringify(__VSCFW_ADDR)"\0" \ +__VSCFW_ADDR \ +"map_lowernorbank=i2c dev "__stringify(CONFIG_SYS_SPD_BUS_NUM)"; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 1 "__stringify(__SW_NOR_BANK_LO)" 1; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 3 "__stringify(__SW_NOR_BANK_MASK)" 1\0" \ +"map_uppernorbank=i2c dev "__stringify(CONFIG_SYS_SPD_BUS_NUM)"; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 1 "__stringify(__SW_NOR_BANK_UP)" 1; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 3 "__stringify(__SW_NOR_BANK_MASK)" 1\0" \ __stringify(__NOR_RST_CMD)"\0" \ __stringify(__SPI_RST_CMD)"\0" \ __stringify(__SD_RST_CMD)"\0" \ diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h index f86afe5..7ab1460 100644 --- a/include/fsl_esdhc.h +++ b/include/fsl_esdhc.h @@ -76,6 +76,7 @@ /* eSDHC control register */ #define ESDHCCTL 0x0002e40c +#define ESDHCCTL_SNOOP (0x00000040) #define ESDHCCTL_PCS (0x00080000) #define ESDHCCTL_FAF (0x00040000) |