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author | Weijie Gao <weijie.gao@mediatek.com> | 2019-09-25 17:45:21 +0800 |
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committer | Daniel Schwierzeck <daniel.schwierzeck@gmail.com> | 2019-10-25 17:20:44 +0200 |
commit | 77ed3c42fee219fb50bca154b1ae36dbca8fc2e0 (patch) | |
tree | b1b6f3d6f40f170bcddad517b207bcf057583149 /include | |
parent | 5fcea8d3f9efe9db0196fba98cf0c5fc7afb942b (diff) | |
download | u-boot-77ed3c42fee219fb50bca154b1ae36dbca8fc2e0.zip u-boot-77ed3c42fee219fb50bca154b1ae36dbca8fc2e0.tar.gz u-boot-77ed3c42fee219fb50bca154b1ae36dbca8fc2e0.tar.bz2 |
clk: add clock driver for MediaTek MT76x8 platform
This patch adds a clock driver for MediaTek MT7628/7688 SoC.
It provides clock gate control as well as getting clock frequency for
CPU/SYS/XTAL and some peripherals.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
Diffstat (limited to 'include')
-rw-r--r-- | include/dt-bindings/clock/mt7628-clk.h | 37 |
1 files changed, 37 insertions, 0 deletions
diff --git a/include/dt-bindings/clock/mt7628-clk.h b/include/dt-bindings/clock/mt7628-clk.h new file mode 100644 index 0000000..b5866fd --- /dev/null +++ b/include/dt-bindings/clock/mt7628-clk.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2019 MediaTek Inc. + * + * Author: Weijie Gao <weijie.gao@mediatek.com> + */ + +#ifndef _DT_BINDINGS_MT7628_CLK_H_ +#define _DT_BINDINGS_MT7628_CLK_H_ + +/* Base clocks */ +#define CLK_SYS 34 +#define CLK_CPU 33 +#define CLK_XTAL 32 + +/* Peripheral clocks */ +#define CLK_PWM 31 +#define CLK_SDXC 30 +#define CLK_CRYPTO 29 +#define CLK_MIPS_CNT 28 +#define CLK_PCIE 26 +#define CLK_UPHY 25 +#define CLK_ETH 23 +#define CLK_UART2 20 +#define CLK_UART1 19 +#define CLK_SPI 18 +#define CLK_I2S 17 +#define CLK_I2C 16 +#define CLK_GDMA 14 +#define CLK_PIO 13 +#define CLK_UART0 12 +#define CLK_PCM 11 +#define CLK_MC 10 +#define CLK_INTC 9 +#define CLK_TIMER 8 + +#endif /* _DT_BINDINGS_MT7628_CLK_H_ */ |