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authorLaurentiu Tudor <laurentiu.tudor@nxp.com>2020-09-10 12:42:18 +0300
committerPriyanka Jain <priyanka.jain@nxp.com>2020-10-23 16:52:09 +0530
commit284d062ef1edda752eadd5aa8cb1df37c76dd272 (patch)
tree0013473adeacb72511b7c295b26f8eebb06cc8e0 /include
parentf4cd963325d2ed73a928ddf096da2471fdceeb55 (diff)
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pci: add a few ARI related defines
Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Diffstat (limited to 'include')
-rw-r--r--include/pci.h6
1 files changed, 6 insertions, 0 deletions
diff --git a/include/pci.h b/include/pci.h
index 1c5b366..d1ccf6c 100644
--- a/include/pci.h
+++ b/include/pci.h
@@ -495,12 +495,18 @@
#define PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */
#define PCI_EXP_SLTCAP 20 /* Slot Capabilities */
#define PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */
+#define PCI_EXP_DEVCAP2 36 /* Device Capabilities 2 */
+#define PCI_EXP_DEVCAP2_ARI 0x00000020 /* ARI Forwarding Supported */
+#define PCI_EXP_DEVCTL2 40 /* Device Control 2 */
+#define PCI_EXP_DEVCTL2_ARI 0x0020 /* Alternative Routing-ID */
+
#define PCI_EXP_LNKCTL2 48 /* Link Control 2 */
/* Single Root I/O Virtualization Registers */
#define PCI_SRIOV_CAP 0x04 /* SR-IOV Capabilities */
#define PCI_SRIOV_CTRL 0x08 /* SR-IOV Control */
#define PCI_SRIOV_CTRL_VFE 0x01 /* VF Enable */
#define PCI_SRIOV_CTRL_MSE 0x08 /* VF Memory Space Enable */
+#define PCI_SRIOV_CTRL_ARI 0x10 /* ARI Capable Hierarchy */
#define PCI_SRIOV_INITIAL_VF 0x0c /* Initial VFs */
#define PCI_SRIOV_TOTAL_VF 0x0e /* Total VFs */
#define PCI_SRIOV_NUM_VF 0x10 /* Number of VFs */