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authorCamelia Groza <camelia.groza@nxp.com>2022-07-28 17:28:11 +0300
committerPeng Fan <peng.fan@nxp.com>2022-08-16 17:07:33 +0800
commitdfea459f20133c89d666f3778e551b50c7e966f0 (patch)
tree655abd75a777a938e5156a97d8a1b9adc3d58ffb /include
parent47465877a5b9d6dbc3a068faf24551e2cb3a4911 (diff)
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board: ls1043ardb: fdt fixups for revision v7.0 boards
The LS1043ARDB rev v7.0 board replaces the AQR105 PHY on MAC9 with an AQR113C PHY. The address of the PHY on the MDIO bus changes from 0x1 to 0x8. Enable CONFIG_OF_BOARD_FIXUP and update both u-boot and Linux device trees to reflect this change. Signed-off-by: Camelia Groza <camelia.groza@nxp.com>
Diffstat (limited to 'include')
-rw-r--r--include/configs/ls1043ardb.h5
1 files changed, 4 insertions, 1 deletions
diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h
index d36b2c7..ff5da5d 100644
--- a/include/configs/ls1043ardb.h
+++ b/include/configs/ls1043ardb.h
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2015 Freescale Semiconductor
+ * Copyright 2022 NXP
*/
#ifndef __LS1043ARDB_H__
@@ -206,7 +207,9 @@
#define QSGMII_PORT3_PHY_ADDR 0x6
#define QSGMII_PORT4_PHY_ADDR 0x7
-#define FM1_10GEC1_PHY_ADDR 0x1
+/* The AQR PHY model and MDIO address differ between board revisions */
+#define FM1_10GEC1_PHY_ADDR 0x1 /* AQR105 on boards up to v6.0 */
+#define AQR113C_PHY_ADDR 0x8 /* AQR113C on boards v7.0 and up */
#endif
#endif