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| author | Chris Packham <judge.packham@gmail.com> | 2022-11-05 17:24:00 +1300 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2022-11-07 07:46:28 +0100 |
| commit | 6cc8b5db40b4d5fc23086a5116bdf1f0a3d3265a (patch) | |
| tree | f5d23fbb3154e990063229e819c1b46dfb399241 /include | |
| parent | 7d7bb99e22783cfee4ecd078d054fcc4cd2948cb (diff) | |
| download | u-boot-6cc8b5db40b4d5fc23086a5116bdf1f0a3d3265a.zip u-boot-6cc8b5db40b4d5fc23086a5116bdf1f0a3d3265a.tar.gz u-boot-6cc8b5db40b4d5fc23086a5116bdf1f0a3d3265a.tar.bz2 | |
arm: mvebu: Add RD-AC5X board
The RD-AC5X-32G16HVG6HLG-A0 development board main components and
features include:
* Main 12V/54V power supply
* 270 Gbps throughput packet processor on the main board
* DDR4:
* SR1: 2GB DDR4 2400MT/S(1GB x 2 pcs ) with ECC(1GB x 1 pcs)
* SR2: 4GB DDR4 2400MT/S(2GB x 2 pcs ) with ECC(2GB x 1 pcs)
* PCB co-layout with 4GB device to support 8GB (Dual CS) requirement
* 16GB eMMC (Samsung KLMAG1JETD-B041006)
* 16MB SPI NOR(GD25Q127C)
* 32 x 1000 Base-T interfaces
* 16 x 2500 Base-T interfaces
* SR1: 88E2540*4
* SR2: 88E2580*1+88E2540*2
* Six (6) x 25G Base-R SFP28 interfaces
* One (1) x RJ-45 console connector, interfacing to the on board UART
* One (1) x USB Type-A connector, interfacing to the USB 2.0 port (0)
* One (1) x USB Type-mini B connector, interfacing to the USB 2.0 port (1)
* One (1) x RJ-45 1G Base-T Management port, interfacing to the host
port (shared with PCIe) Connected to 88E1512 Gigabit Ethernet Phy
* One (1) x Oculink port, interfacing to the PCIe port for external CPU
connection
* POE 802.3AT support on Port 1 ~ Port 32, 802.3BT support on Port 33 ~
Port 48 (Microsemi PD69208T4, PD69208M or TI TPS2388,TPS23881
solution)
* POE total power budget 780W
* LED interfaces per network port/POE
* LED interfaces (common) showing system status
* PTP TC mode Supported (Reserved M.2 connector to support BC mode)
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/configs/mvebu_alleycat-5.h | 42 |
1 files changed, 42 insertions, 0 deletions
diff --git a/include/configs/mvebu_alleycat-5.h b/include/configs/mvebu_alleycat-5.h new file mode 100644 index 0000000..41bdfae --- /dev/null +++ b/include/configs/mvebu_alleycat-5.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2018 Marvell International Ltd + */ + +#ifndef _CONFIG_MVEBU_ALLEYCAY_5_H +#define _CONFIG_MVEBU_ALLEYCAY_5_H + +#include <asm/arch/soc.h> + +/* additions for new ARM relocation support */ +#define CONFIG_SYS_SDRAM_BASE 0x200000000 + +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \ + 115200, 230400, 460800, 921600 } + +/* Default Env vars */ +#define CONFIG_IPADDR 0.0.0.0 /* In order to cause an error */ +#define CONFIG_SERVERIP 0.0.0.0 /* In order to cause an error */ +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_GATEWAYIP 0.0.0.0 +#define CONFIG_ROOTPATH "/srv/nfs/" /* Default Dir for NFS */ + +#define BOOT_TARGET_DEVICES(func) \ + func(USB, usb, 0) \ + func(DHCP, dhcp, na) + +#include <config_distro_bootcmd.h> + +#define CONFIG_EXTRA_ENV_SETTINGS \ + BOOTENV \ + "kernel_addr_r=0x202000000\0" \ + "fdt_addr_r=0x201000000\0" \ + "ramdisk_addr_r=0x206000000\0" \ + "fdtfile=marvell/" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" + +/* + * High Level Configuration Options (easy to change) + */ +#define CONFIG_SYS_TCLK 325000000 + +#endif /* _CONFIG_MVEBU_ALLEYCAY_5_H */ |