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| author | Mario Six <mario.six@gdsys.cc> | 2019-01-21 09:18:16 +0100 |
|---|---|---|
| committer | Mario Six <mario.six@gdsys.cc> | 2019-05-21 07:52:33 +0200 |
| commit | 133ec602846d28a7915a7b3149d05d1c8a270873 (patch) | |
| tree | 507157ce06ed8113cb03196d664e5d28eecac486 /include | |
| parent | 8a81bfd271f9122933c865c790780024f5e2d576 (diff) | |
| download | u-boot-133ec602846d28a7915a7b3149d05d1c8a270873.zip u-boot-133ec602846d28a7915a7b3149d05d1c8a270873.tar.gz u-boot-133ec602846d28a7915a7b3149d05d1c8a270873.tar.bz2 | |
mpc83xx: Get rid of CONFIG_SYS_DDR_SDRAM_BASE
CONFIG_SYS_DDR_SDRAM_BASE is set to the same value as
CONFIG_SYS_SDRAM_BASE on all existing boards. Just use
CONFIG_SYS_SDRAM_BASE instead.
Signed-off-by: Mario Six <mario.six@gdsys.cc>
Diffstat (limited to 'include')
30 files changed, 0 insertions, 30 deletions
diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h index d9361fd..5d31d4a 100644 --- a/include/configs/MPC8308RDB.h +++ b/include/configs/MPC8308RDB.h @@ -37,7 +37,6 @@ * DDR Setup */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ | DDRCDR_PZ_LOZ \ diff --git a/include/configs/MPC8313ERDB_NAND.h b/include/configs/MPC8313ERDB_NAND.h index 08c8399..6f100fc 100644 --- a/include/configs/MPC8313ERDB_NAND.h +++ b/include/configs/MPC8313ERDB_NAND.h @@ -87,7 +87,6 @@ * DDR Setup */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE /* * Manually set up DDR parameters, as this board does not diff --git a/include/configs/MPC8313ERDB_NOR.h b/include/configs/MPC8313ERDB_NOR.h index 169cc09..0f246dc 100644 --- a/include/configs/MPC8313ERDB_NOR.h +++ b/include/configs/MPC8313ERDB_NOR.h @@ -59,7 +59,6 @@ * DDR Setup */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE /* * Manually set up DDR parameters, as this board does not diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h index c5a229d..0b94b0c 100644 --- a/include/configs/MPC8315ERDB.h +++ b/include/configs/MPC8315ERDB.h @@ -35,7 +35,6 @@ * DDR Setup */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ | DDRCDR_PZ_LOZ \ diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h index 3e6febf..a90a9a8 100644 --- a/include/configs/MPC8323ERDB.h +++ b/include/configs/MPC8323ERDB.h @@ -24,7 +24,6 @@ * DDR Setup */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #undef CONFIG_SPD_EEPROM #if defined(CONFIG_SPD_EEPROM) diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h index 4b3f70c..88b6f87 100644 --- a/include/configs/MPC832XEMDS.h +++ b/include/configs/MPC832XEMDS.h @@ -21,7 +21,6 @@ * DDR Setup */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDRCDR 0x73000002 /* DDR II voltage is 1.8V */ #undef CONFIG_SPD_EEPROM diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index 1a96be0..fdbd15e 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -53,7 +53,6 @@ #undef CONFIG_DDR_32BIT #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) #undef CONFIG_DDR_2T_TIMING diff --git a/include/configs/MPC8349EMDS_SDRAM.h b/include/configs/MPC8349EMDS_SDRAM.h index 311f87b..1e0e297 100644 --- a/include/configs/MPC8349EMDS_SDRAM.h +++ b/include/configs/MPC8349EMDS_SDRAM.h @@ -53,7 +53,6 @@ #undef CONFIG_DDR_32BIT #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) #undef CONFIG_DDR_2T_TIMING diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index bb3bcfc..388910a 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -143,7 +143,6 @@ * DDR Setup */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_83XX_DDR_USES_CS0 #define CONFIG_SYS_MEMTEST_START 0x1000 /* memtest region */ #define CONFIG_SYS_MEMTEST_END 0x2000 diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index e34a36c..61f9eaf 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -36,7 +36,6 @@ * DDR Setup */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 #define CONFIG_SYS_83XX_DDR_USES_CS0 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN \ diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index 33d4ced..07b206f 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -59,7 +59,6 @@ * DDR Setup */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x03000000 #define CONFIG_SYS_83XX_DDR_USES_CS0 diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h index 53fac4d..0da34d0 100644 --- a/include/configs/TQM834x.h +++ b/include/configs/TQM834x.h @@ -25,7 +25,6 @@ */ /* DDR is system memory*/ #define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define DDR_CASLAT_25 /* CASLAT set to 2.5 */ #undef CONFIG_DDR_ECC /* only for ECC DDR module */ #undef CONFIG_SPD_EEPROM /* do not use SPD EEPROM for DDR setup */ diff --git a/include/configs/caddy2.h b/include/configs/caddy2.h index f14e5fa..928136f 100644 --- a/include/configs/caddy2.h +++ b/include/configs/caddy2.h @@ -52,7 +52,6 @@ #undef CONFIG_DDR_32BIT #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is sys memory*/ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075) #define CONFIG_DDR_2T_TIMING diff --git a/include/configs/hrcon.h b/include/configs/hrcon.h index ae3fcfd..d73e848 100644 --- a/include/configs/hrcon.h +++ b/include/configs/hrcon.h @@ -25,7 +25,6 @@ * DDR Setup */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ | DDRCDR_PZ_LOZ \ diff --git a/include/configs/ids8313.h b/include/configs/ids8313.h index 504a136..155815a 100644 --- a/include/configs/ids8313.h +++ b/include/configs/ids8313.h @@ -52,7 +52,6 @@ * DDR Setup */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE /* * Manually set up DDR parameters, diff --git a/include/configs/kmcoge5ne.h b/include/configs/kmcoge5ne.h index 5c4df18..847996f 100644 --- a/include/configs/kmcoge5ne.h +++ b/include/configs/kmcoge5ne.h @@ -46,7 +46,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h index 2e8affb..290108d 100644 --- a/include/configs/kmeter1.h +++ b/include/configs/kmeter1.h @@ -31,7 +31,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) diff --git a/include/configs/kmopti2.h b/include/configs/kmopti2.h index 3be5328..0759604 100644 --- a/include/configs/kmopti2.h +++ b/include/configs/kmopti2.h @@ -51,7 +51,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) diff --git a/include/configs/kmsupx5.h b/include/configs/kmsupx5.h index 74e719c..319e3bc 100644 --- a/include/configs/kmsupx5.h +++ b/include/configs/kmsupx5.h @@ -51,7 +51,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) diff --git a/include/configs/kmtegr1.h b/include/configs/kmtegr1.h index c691383..85e9101 100644 --- a/include/configs/kmtegr1.h +++ b/include/configs/kmtegr1.h @@ -58,7 +58,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) diff --git a/include/configs/kmtepr2.h b/include/configs/kmtepr2.h index 4af8619..6ec944f 100644 --- a/include/configs/kmtepr2.h +++ b/include/configs/kmtepr2.h @@ -51,7 +51,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) diff --git a/include/configs/kmvect1.h b/include/configs/kmvect1.h index d8f4d26..d7cbdde 100644 --- a/include/configs/kmvect1.h +++ b/include/configs/kmvect1.h @@ -50,7 +50,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) diff --git a/include/configs/mpc8308_p1m.h b/include/configs/mpc8308_p1m.h index 8836b70..0392c3e 100644 --- a/include/configs/mpc8308_p1m.h +++ b/include/configs/mpc8308_p1m.h @@ -40,7 +40,6 @@ * DDR Setup */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ | DDRCDR_PZ_LOZ \ diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index 709387e..b4ae7b7 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -47,7 +47,6 @@ #undef CONFIG_DDR_32BIT #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075) #define CONFIG_DDR_2T_TIMING diff --git a/include/configs/strider.h b/include/configs/strider.h index c01531c..e92bd1e 100644 --- a/include/configs/strider.h +++ b/include/configs/strider.h @@ -25,7 +25,6 @@ * DDR Setup */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ | DDRCDR_PZ_LOZ \ diff --git a/include/configs/suvd3.h b/include/configs/suvd3.h index 3521de8..8b3b454 100644 --- a/include/configs/suvd3.h +++ b/include/configs/suvd3.h @@ -48,7 +48,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) diff --git a/include/configs/tuge1.h b/include/configs/tuge1.h index 86e402a..5dc9e89 100644 --- a/include/configs/tuge1.h +++ b/include/configs/tuge1.h @@ -51,7 +51,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) diff --git a/include/configs/tuxx1.h b/include/configs/tuxx1.h index ec1ac39..9f8c855 100644 --- a/include/configs/tuxx1.h +++ b/include/configs/tuxx1.h @@ -51,7 +51,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) diff --git a/include/configs/ve8313.h b/include/configs/ve8313.h index cd6c686..2116d6b 100644 --- a/include/configs/ve8313.h +++ b/include/configs/ve8313.h @@ -35,7 +35,6 @@ * DDR Setup */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE /* * Manually set up DDR parameters, as this board does not diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h index 14a84fa..1bce6c7 100644 --- a/include/configs/vme8349.h +++ b/include/configs/vme8349.h @@ -52,7 +52,6 @@ #undef CONFIG_DDR_32BIT #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is sys memory*/ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075) #define CONFIG_DDR_2T_TIMING |