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| author | Sylwester Nawrocki <s.nawrocki@samsung.com> | 2020-05-25 13:39:53 +0200 |
|---|---|---|
| committer | Matthias Brugger <mbrugger@suse.com> | 2020-07-09 15:46:12 +0200 |
| commit | b6687e19f9d3fdd33e76991df3dfcba60961ce35 (patch) | |
| tree | a1d307d9910c05fe42a74b24cbb5aa83c91c1fb9 /include/pci.h | |
| parent | 8e2ab05000ab91daea63022665d2b0c86f5cba3c (diff) | |
| download | u-boot-b6687e19f9d3fdd33e76991df3dfcba60961ce35.zip u-boot-b6687e19f9d3fdd33e76991df3dfcba60961ce35.tar.gz u-boot-b6687e19f9d3fdd33e76991df3dfcba60961ce35.tar.bz2 | |
pci: Move some PCIe register offset definitions to a common header
Some PCI Express register offsets are currently defined in multiple
drivers, move them to a common header to avoid re-definitions and
as a pre-requisite for adding new PCIe driver.
While at it replace some spaces with tabs.
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
Diffstat (limited to 'include/pci.h')
| -rw-r--r-- | include/pci.h | 13 |
1 files changed, 11 insertions, 2 deletions
diff --git a/include/pci.h b/include/pci.h index 19c9244..9cd8564 100644 --- a/include/pci.h +++ b/include/pci.h @@ -471,10 +471,19 @@ #define PCI_EA_FIELD_MASK 0xfffffffc /* For Base & Max Offset */ /* PCI Express capabilities */ +#define PCI_EXP_FLAGS 2 /* Capabilities register */ +#define PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */ +#define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */ #define PCI_EXP_DEVCAP 4 /* Device capabilities */ -#define PCI_EXP_DEVCAP_FLR 0x10000000 /* Function Level Reset */ +#define PCI_EXP_DEVCAP_FLR 0x10000000 /* Function Level Reset */ #define PCI_EXP_DEVCTL 8 /* Device Control */ -#define PCI_EXP_DEVCTL_BCR_FLR 0x8000 /* Bridge Configuration Retry / FLR */ +#define PCI_EXP_DEVCTL_BCR_FLR 0x8000 /* Bridge Configuration Retry / FLR */ +#define PCI_EXP_LNKCAP 12 /* Link Capabilities */ +#define PCI_EXP_LNKCAP_DLLLARC 0x00100000 /* Data Link Layer Link Active Reporting Capable */ +#define PCI_EXP_LNKSTA 18 /* Link Status */ +#define PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */ +#define PCI_EXP_SLTCAP 20 /* Slot Capabilities */ +#define PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */ /* Include the ID list */ |