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| author | Simon Glass <sjg@chromium.org> | 2019-09-25 08:56:18 -0600 |
|---|---|---|
| committer | Bin Meng <bmeng.cn@gmail.com> | 2019-10-08 13:57:43 +0800 |
| commit | 4e8de068a3b210c0fea2b29372b25c60c7b6dc9e (patch) | |
| tree | 088b6b365552bc67f2d8813252f8f43c564b9547 /include/ns16550.h | |
| parent | 33c215af4b9de32e5052bb716411dc34ce9b63ac (diff) | |
| download | u-boot-4e8de068a3b210c0fea2b29372b25c60c7b6dc9e.zip u-boot-4e8de068a3b210c0fea2b29372b25c60c7b6dc9e.tar.gz u-boot-4e8de068a3b210c0fea2b29372b25c60c7b6dc9e.tar.bz2 | |
serial: ns16550: Add a PCI device/function field
When this UART is used early in boot (before PCI is set up) it is
convenient to store the PCI BDF of the UART so that it can be manually
configured. This is useful when it is used as a debug UART, for example.
Add a new field to hold this information, so that drivers can simply use
the existing platform data.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Diffstat (limited to 'include/ns16550.h')
| -rw-r--r-- | include/ns16550.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/include/ns16550.h b/include/ns16550.h index 22b89e4..701efee 100644 --- a/include/ns16550.h +++ b/include/ns16550.h @@ -52,6 +52,7 @@ * @reg_width: IO accesses size of registers (in bytes) * @reg_shift: Shift size of registers (0=byte, 1=16bit, 2=32bit...) * @clock: UART base clock speed in Hz + * @bdf: PCI slot/function (pci_dev_t) */ struct ns16550_platdata { unsigned long base; @@ -60,6 +61,9 @@ struct ns16550_platdata { int reg_offset; int clock; u32 fcr; +#if defined(CONFIG_PCI) && defined(CONFIG_SPL) + int bdf; +#endif }; struct udevice; |