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| author | Pratyush Yadav <p.yadav@ti.com> | 2021-06-26 00:47:29 +0530 |
|---|---|---|
| committer | Jagan Teki <jagan@amarulasolutions.com> | 2021-06-28 12:06:57 +0530 |
| commit | f6adec1af4b2f5d3012480c6cdce7743b74a6156 (patch) | |
| tree | 6a85481238bd6871baecb81ac74d76399c44c4cb /include/linux | |
| parent | ea9a22f7e79cbc951a2aca204b3eec6948837827 (diff) | |
| download | u-boot-f6adec1af4b2f5d3012480c6cdce7743b74a6156.zip u-boot-f6adec1af4b2f5d3012480c6cdce7743b74a6156.tar.gz u-boot-f6adec1af4b2f5d3012480c6cdce7743b74a6156.tar.bz2 | |
mtd: spi-nor-core: Allow using Micron mt35xu512aba in Octal DTR mode
Since this flash doesn't have a Profile 1.0 table, the Octal DTR
capabilities are enabled in the post SFDP fixup, along with the 8D-8D-8D
fast read settings.
Enable Octal DTR mode with 20 dummy cycles to allow running at the
maximum supported frequency of 200Mhz.
Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Diffstat (limited to 'include/linux')
| -rw-r--r-- | include/linux/mtd/spi-nor.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index 6ece401..d68e48f 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -126,6 +126,12 @@ /* Used for Micron flashes only. */ #define SPINOR_OP_RD_EVCR 0x65 /* Read EVCR register */ #define SPINOR_OP_WD_EVCR 0x61 /* Write EVCR register */ +#define SPINOR_OP_MT_DTR_RD 0xfd /* Fast Read opcode in DTR mode */ +#define SPINOR_OP_MT_RD_ANY_REG 0x85 /* Read volatile register */ +#define SPINOR_OP_MT_WR_ANY_REG 0x81 /* Write volatile register */ +#define SPINOR_REG_MT_CFR0V 0x00 /* For setting octal DTR mode */ +#define SPINOR_REG_MT_CFR1V 0x01 /* For setting dummy cycles */ +#define SPINOR_MT_OCT_DTR 0xe7 /* Enable Octal DTR with DQS. */ /* Status Register bits. */ #define SR_WIP BIT(0) /* Write in progress */ |