diff options
| author | Pratyush Yadav <p.yadav@ti.com> | 2021-06-26 00:47:28 +0530 |
|---|---|---|
| committer | Jagan Teki <jagan@amarulasolutions.com> | 2021-06-28 12:06:43 +0530 |
| commit | ea9a22f7e79cbc951a2aca204b3eec6948837827 (patch) | |
| tree | 6c554f748128f6ee223283cc59e363602b97abe1 /include/linux/mtd/spi-nor.h | |
| parent | ee52b0b764d3eaa69f20f7e142945d56fe3f6fdb (diff) | |
| download | u-boot-ea9a22f7e79cbc951a2aca204b3eec6948837827.zip u-boot-ea9a22f7e79cbc951a2aca204b3eec6948837827.tar.gz u-boot-ea9a22f7e79cbc951a2aca204b3eec6948837827.tar.bz2 | |
mtd: spi-nor-core: Add support for Cypress Semper flash
The Cypress Semper flash is an xSPI compliant octal DTR flash. Add
support for using it in octal DTR mode.
The flash by default boots in a hybrid sector mode. Switch to uniform
sector mode on boot. Use the default 20 dummy cycles for a read fast
command.
The SFDP programming on some older versions of the flash was incorrect.
Fixes for that are included in the fixup hooks.
Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Diffstat (limited to 'include/linux/mtd/spi-nor.h')
| -rw-r--r-- | include/linux/mtd/spi-nor.h | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index 29ce175..6ece401 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -157,6 +157,19 @@ /* Status Register 2 bits. */ #define SR2_QUAD_EN_BIT7 BIT(7) +/* For Cypress flash. */ +#define SPINOR_OP_RD_ANY_REG 0x65 /* Read any register */ +#define SPINOR_OP_WR_ANY_REG 0x71 /* Write any register */ +#define SPINOR_OP_S28_SE_4K 0x21 +#define SPINOR_REG_CYPRESS_CFR2V 0x00800003 +#define SPINOR_REG_CYPRESS_CFR2V_MEMLAT_11_24 0xb +#define SPINOR_REG_CYPRESS_CFR3V 0x00800004 +#define SPINOR_REG_CYPRESS_CFR3V_PGSZ BIT(4) /* Page size. */ +#define SPINOR_REG_CYPRESS_CFR3V_UNISECT BIT(3) /* Uniform sector mode */ +#define SPINOR_REG_CYPRESS_CFR5V 0x00800006 +#define SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_EN 0x3 +#define SPINOR_OP_CYPRESS_RD_FAST 0xee + /* Supported SPI protocols */ #define SNOR_PROTO_INST_MASK GENMASK(23, 16) #define SNOR_PROTO_INST_SHIFT 16 |