diff options
| author | Rajesh Bhagat <rajesh.bhagat@nxp.com> | 2018-11-05 18:01:19 +0000 |
|---|---|---|
| committer | York Sun <york.sun@nxp.com> | 2018-12-06 14:37:07 -0800 |
| commit | 088d52cfa8ec515316e20a6168dc2dd163c799b9 (patch) | |
| tree | 3dbee60f1868458e8d86ccf72f5acfc6f5cfe00a /include/fsl_ifc.h | |
| parent | 119c01c2a571bb901dd0170b85924f74e362b75c (diff) | |
| download | u-boot-088d52cfa8ec515316e20a6168dc2dd163c799b9.zip u-boot-088d52cfa8ec515316e20a6168dc2dd163c799b9.tar.gz u-boot-088d52cfa8ec515316e20a6168dc2dd163c799b9.tar.bz2 | |
driver/ifc: replace __ilog2 with LOG2 macro
Replaces __ilog2 function call with LOG2 macro, required to
use macros in global variables.
Also, corrects the value passed in LOG2 for some PowerPC
platforms. Minimum value that can be configured is is 64K
for IFC IP.
Signed-off-by: Pankit Garg <pankit.garg@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
[YS: fix white space around operator]
Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'include/fsl_ifc.h')
| -rw-r--r-- | include/fsl_ifc.h | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/include/fsl_ifc.h b/include/fsl_ifc.h index 8120ca0..17697c7 100644 --- a/include/fsl_ifc.h +++ b/include/fsl_ifc.h @@ -70,7 +70,7 @@ #define IFC_AMASK_MASK 0xFFFF0000 #define IFC_AMASK_SHIFT 16 #define IFC_AMASK(n) (IFC_AMASK_MASK << \ - (__ilog2(n) - IFC_AMASK_SHIFT)) + (LOG2(n) - IFC_AMASK_SHIFT)) /* * Chip Select Option Register IFC_NAND Machine @@ -111,7 +111,7 @@ /* Pages Per Block */ #define CSOR_NAND_PB_MASK 0x00000700 #define CSOR_NAND_PB_SHIFT 8 -#define CSOR_NAND_PB(n) ((__ilog2(n) - 5) << CSOR_NAND_PB_SHIFT) +#define CSOR_NAND_PB(n) ((LOG2(n) - 5) << CSOR_NAND_PB_SHIFT) /* Time for Read Enable High to Output High Impedance */ #define CSOR_NAND_TRHZ_MASK 0x0000001C #define CSOR_NAND_TRHZ_SHIFT 2 @@ -164,7 +164,7 @@ /* GPCM Timeout Count */ #define CSOR_GPCM_GPTO_MASK 0x0F000000 #define CSOR_GPCM_GPTO_SHIFT 24 -#define CSOR_GPCM_GPTO(n) ((__ilog2(n) - 8) << CSOR_GPCM_GPTO_SHIFT) +#define CSOR_GPCM_GPTO(n) ((LOG2(n) - 8) << CSOR_GPCM_GPTO_SHIFT) /* GPCM External Access Termination mode for read access */ #define CSOR_GPCM_RGETA_EXT 0x00080000 /* GPCM External Access Termination mode for write access */ @@ -644,7 +644,7 @@ enum ifc_nand_fir_opcodes { */ #define IFC_NAND_NCR_FTOCNT_MASK 0x1E000000 #define IFC_NAND_NCR_FTOCNT_SHIFT 25 -#define IFC_NAND_NCR_FTOCNT(n) ((_ilog2(n) - 8) << IFC_NAND_NCR_FTOCNT_SHIFT) +#define IFC_NAND_NCR_FTOCNT(n) ((LOG2(n) - 8) << IFC_NAND_NCR_FTOCNT_SHIFT) /* * NAND_AUTOBOOT_TRGR @@ -727,7 +727,7 @@ enum ifc_nand_fir_opcodes { /* Sequence Timeout Count */ #define IFC_NORCR_STOCNT_MASK 0x000F0000 #define IFC_NORCR_STOCNT_SHIFT 16 -#define IFC_NORCR_STOCNT(n) ((__ilog2(n) - 8) << IFC_NORCR_STOCNT_SHIFT) +#define IFC_NORCR_STOCNT(n) ((LOG2(n) - 8) << IFC_NORCR_STOCNT_SHIFT) /* * GPCM Machine specific registers |