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author | Ley Foon Tan <ley.foon.tan@intel.com> | 2018-12-20 17:55:41 +0800 |
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committer | Marek Vasut <marex@denx.de> | 2019-02-18 13:00:54 +0100 |
commit | 7997599e2df64c8fb450bc03f2d618adbde05f6e (patch) | |
tree | 6316acdb2f882c04b7f079424a28b061db6ff585 /include/dwmmc.h | |
parent | 473f55676a65e068ba82096f54cd1e9f16ecc006 (diff) | |
download | u-boot-7997599e2df64c8fb450bc03f2d618adbde05f6e.zip u-boot-7997599e2df64c8fb450bc03f2d618adbde05f6e.tar.gz u-boot-7997599e2df64c8fb450bc03f2d618adbde05f6e.tar.bz2 |
mmc: dwmmc: Poll for iDMAC TX/RX interrupt
Poll for iDMAC TX/RX interrupt before disable DMA.
This to prevent disable DMA before data is transfer
completed.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Diffstat (limited to 'include/dwmmc.h')
-rw-r--r-- | include/dwmmc.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/include/dwmmc.h b/include/dwmmc.h index 4ceda5e..f06720d 100644 --- a/include/dwmmc.h +++ b/include/dwmmc.h @@ -130,6 +130,13 @@ /* UHS register */ #define DWMCI_DDR_MODE (1 << 16) +/* Internal IDMAC interrupt defines */ +#define DWMCI_IDINTEN_RI BIT(1) +#define DWMCI_IDINTEN_TI BIT(0) + +#define DWMCI_IDINTEN_MASK (DWMCI_IDINTEN_TI | \ + DWMCI_IDINTEN_RI) + /* quirks */ #define DWMCI_QUIRK_DISABLE_SMU (1 << 0) |