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author | Icenowy Zheng <icenowy@aosc.io> | 2018-07-21 16:20:31 +0800 |
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committer | Jagan Teki <jagan@amarulasolutions.com> | 2018-07-31 11:38:13 +0530 |
commit | 6f796a9bb4b49f6680580672e9210e810b275f00 (patch) | |
tree | 43d0d80bb47c3349dfa74d694a677b18cb6d1b0a /include/dt-bindings/reset | |
parent | da2616543aa57cad2b2d884af9d88ff0bfd4776a (diff) | |
download | u-boot-6f796a9bb4b49f6680580672e9210e810b275f00.zip u-boot-6f796a9bb4b49f6680580672e9210e810b275f00.tar.gz u-boot-6f796a9bb4b49f6680580672e9210e810b275f00.tar.bz2 |
sunxi: add support for Allwinner H6 SoC
Allwinner H6 is a new SoC from Allwinner features USB3 and PCIe
interfaces.
This patch adds support for it.
The corresponding DTSI file, from Linux next-20180720, is also
introduced.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
Diffstat (limited to 'include/dt-bindings/reset')
-rw-r--r-- | include/dt-bindings/reset/sun50i-h6-ccu.h | 73 | ||||
-rw-r--r-- | include/dt-bindings/reset/sun50i-h6-r-ccu.h | 17 |
2 files changed, 90 insertions, 0 deletions
diff --git a/include/dt-bindings/reset/sun50i-h6-ccu.h b/include/dt-bindings/reset/sun50i-h6-ccu.h new file mode 100644 index 0000000..81106f4 --- /dev/null +++ b/include/dt-bindings/reset/sun50i-h6-ccu.h @@ -0,0 +1,73 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +/* + * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io> + */ + +#ifndef _DT_BINDINGS_RESET_SUN50I_H6_H_ +#define _DT_BINDINGS_RESET_SUN50I_H6_H_ + +#define RST_MBUS 0 +#define RST_BUS_DE 1 +#define RST_BUS_DEINTERLACE 2 +#define RST_BUS_GPU 3 +#define RST_BUS_CE 4 +#define RST_BUS_VE 5 +#define RST_BUS_EMCE 6 +#define RST_BUS_VP9 7 +#define RST_BUS_DMA 8 +#define RST_BUS_MSGBOX 9 +#define RST_BUS_SPINLOCK 10 +#define RST_BUS_HSTIMER 11 +#define RST_BUS_DBG 12 +#define RST_BUS_PSI 13 +#define RST_BUS_PWM 14 +#define RST_BUS_IOMMU 15 +#define RST_BUS_DRAM 16 +#define RST_BUS_NAND 17 +#define RST_BUS_MMC0 18 +#define RST_BUS_MMC1 19 +#define RST_BUS_MMC2 20 +#define RST_BUS_UART0 21 +#define RST_BUS_UART1 22 +#define RST_BUS_UART2 23 +#define RST_BUS_UART3 24 +#define RST_BUS_I2C0 25 +#define RST_BUS_I2C1 26 +#define RST_BUS_I2C2 27 +#define RST_BUS_I2C3 28 +#define RST_BUS_SCR0 29 +#define RST_BUS_SCR1 30 +#define RST_BUS_SPI0 31 +#define RST_BUS_SPI1 32 +#define RST_BUS_EMAC 33 +#define RST_BUS_TS 34 +#define RST_BUS_IR_TX 35 +#define RST_BUS_THS 36 +#define RST_BUS_I2S0 37 +#define RST_BUS_I2S1 38 +#define RST_BUS_I2S2 39 +#define RST_BUS_I2S3 40 +#define RST_BUS_SPDIF 41 +#define RST_BUS_DMIC 42 +#define RST_BUS_AUDIO_HUB 43 +#define RST_USB_PHY0 44 +#define RST_USB_PHY1 45 +#define RST_USB_PHY3 46 +#define RST_USB_HSIC 47 +#define RST_BUS_OHCI0 48 +#define RST_BUS_OHCI3 49 +#define RST_BUS_EHCI0 50 +#define RST_BUS_XHCI 51 +#define RST_BUS_EHCI3 52 +#define RST_BUS_OTG 53 +#define RST_BUS_PCIE 54 +#define RST_PCIE_POWERUP 55 +#define RST_BUS_HDMI 56 +#define RST_BUS_HDMI_SUB 57 +#define RST_BUS_TCON_TOP 58 +#define RST_BUS_TCON_LCD0 59 +#define RST_BUS_TCON_TV0 60 +#define RST_BUS_CSI 61 +#define RST_BUS_HDCP 62 + +#endif /* _DT_BINDINGS_RESET_SUN50I_H6_H_ */ diff --git a/include/dt-bindings/reset/sun50i-h6-r-ccu.h b/include/dt-bindings/reset/sun50i-h6-r-ccu.h new file mode 100644 index 0000000..01c84db --- /dev/null +++ b/include/dt-bindings/reset/sun50i-h6-r-ccu.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ +/* + * Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz> + */ + +#ifndef _DT_BINDINGS_RST_SUN50I_H6_R_CCU_H_ +#define _DT_BINDINGS_RST_SUN50I_H6_R_CCU_H_ + +#define RST_R_APB1_TIMER 0 +#define RST_R_APB1_TWD 1 +#define RST_R_APB1_PWM 2 +#define RST_R_APB2_UART 3 +#define RST_R_APB2_I2C 4 +#define RST_R_APB1_IR 5 +#define RST_R_APB1_W1 6 + +#endif /* _DT_BINDINGS_RST_SUN50I_H6_R_CCU_H_ */ |