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| author | Weijie Gao <weijie.gao@mediatek.com> | 2020-11-12 16:36:19 +0800 |
|---|---|---|
| committer | Daniel Schwierzeck <daniel.schwierzeck@gmail.com> | 2021-01-24 21:39:26 +0100 |
| commit | 4075928c3691228bd69f40538efa578b52602c84 (patch) | |
| tree | e7357d9e6544b87ed597801607d942bca21f509e /include/dt-bindings/reset | |
| parent | d9a5da72d790758dbad47787ab963c3ef2ee0cff (diff) | |
| download | u-boot-4075928c3691228bd69f40538efa578b52602c84.zip u-boot-4075928c3691228bd69f40538efa578b52602c84.tar.gz u-boot-4075928c3691228bd69f40538efa578b52602c84.tar.bz2 | |
reset: mtmips: add reset controller support for MediaTek MT7620 SoC
This patch adds reset controller bits definition header file for MediaTek
MT7620 SoC
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
Diffstat (limited to 'include/dt-bindings/reset')
| -rw-r--r-- | include/dt-bindings/reset/mt7620-reset.h | 35 |
1 files changed, 35 insertions, 0 deletions
diff --git a/include/dt-bindings/reset/mt7620-reset.h b/include/dt-bindings/reset/mt7620-reset.h new file mode 100644 index 0000000..3096b29 --- /dev/null +++ b/include/dt-bindings/reset/mt7620-reset.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2020 MediaTek Inc. + * + * Author: Weijie Gao <weijie.gao@mediatek.com> + */ + +#ifndef _DT_BINDINGS_MT7620_RESET_H_ +#define _DT_BINDINGS_MT7620_RESET_H_ + +#define PPE_RST 31 +#define SDHC_RST 30 +#define MIPS_CNT_RST 28 +#define PCIE_RST 26 +#define UHST_RST 25 +#define EPHY_RST 24 +#define ESW_RST 23 +#define UDEV_RST 22 +#define FE_RST 21 +#define WLAN_RST 20 +#define UARTL_RST 19 +#define SPI_RST 18 +#define I2S_RST 17 +#define I2C_RST 16 +#define NAND_RST 15 +#define DMA_RST 14 +#define PIO_RST 13 +#define UARTF_RST 12 +#define PCM_RST 11 +#define MC_RST 10 +#define INTC_RST 9 +#define TIMER_RST 8 +#define SYS_RST 0 + +#endif /* _DT_BINDINGS_MT7620_RESET_H_ */ |