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| author | Simon Glass <sjg@chromium.org> | 2021-10-21 21:08:47 -0600 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2021-11-16 14:35:08 -0500 |
| commit | f501bb4c2aa8ba6dd6260f961e788eb46c0a36b3 (patch) | |
| tree | 6dadd857d824b58f2a1f964dd023fbcf5a85eea4 /include/configs | |
| parent | 86b9c3e4e48ba47ef28781d06b97846aca74bc8e (diff) | |
| download | u-boot-f501bb4c2aa8ba6dd6260f961e788eb46c0a36b3.zip u-boot-f501bb4c2aa8ba6dd6260f961e788eb46c0a36b3.tar.gz u-boot-f501bb4c2aa8ba6dd6260f961e788eb46c0a36b3.tar.bz2 | |
sandbox: Use a text-based environment
Use a text file for the environment instead of the #define settings.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
Diffstat (limited to 'include/configs')
| -rw-r--r-- | include/configs/sandbox.h | 29 |
1 files changed, 0 insertions, 29 deletions
diff --git a/include/configs/sandbox.h b/include/configs/sandbox.h index 0da0cf5..cc3a7ff 100644 --- a/include/configs/sandbox.h +++ b/include/configs/sandbox.h @@ -54,37 +54,8 @@ #define CONFIG_LCD_BMP_RLE8 #define CONFIG_KEYBOARD - -#define SANDBOX_SERIAL_SETTINGS "stdin=serial,cros-ec-keyb,usbkbd\0" \ - "stdout=serial,vidconsole\0" \ - "stderr=serial,vidconsole\0" -#else -#define SANDBOX_SERIAL_SETTINGS "stdin=serial\0" \ - "stdout=serial,vidconsole\0" \ - "stderr=serial,vidconsole\0" #endif -#define SANDBOX_ETH_SETTINGS "ethaddr=00:00:11:22:33:44\0" \ - "eth2addr=00:00:11:22:33:48\0" \ - "eth3addr=00:00:11:22:33:45\0" \ - "eth4addr=00:00:11:22:33:48\0" \ - "eth5addr=00:00:11:22:33:46\0" \ - "eth6addr=00:00:11:22:33:47\0" \ - "ipaddr=1.2.3.4\0" - -#define MEM_LAYOUT_ENV_SETTINGS \ - "bootm_size=0x10000000\0" \ - "kernel_addr_r=0x1000000\0" \ - "fdt_addr_r=0xc00000\0" \ - "ramdisk_addr_r=0x2000000\0" \ - "scriptaddr=0x1000\0" \ - "pxefile_addr_r=0x2000\0" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - SANDBOX_SERIAL_SETTINGS \ - SANDBOX_ETH_SETTINGS \ - MEM_LAYOUT_ENV_SETTINGS - #ifndef CONFIG_SPL_BUILD #define CONFIG_SYS_IDE_MAXBUS 1 #define CONFIG_SYS_ATA_IDE0_OFFSET 0 |