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authorTom Rini <trini@konsulko.com>2019-08-10 17:57:58 -0400
committerTom Rini <trini@konsulko.com>2019-08-10 17:57:58 -0400
commitfeb5a02f869d5678190dfc915ef6c2781b4f7a6c (patch)
tree406786a9d076fd98ed4192bb5fe84215218797d4 /include/configs
parent31d136926b739b58eca0b12237481d666da66427 (diff)
parent3ebb91914f4831df4db42675c4dd1f9a0b7548c7 (diff)
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Merge branch 'master' of git://git.denx.de/u-boot-sh
- R8A77980 V3H support
Diffstat (limited to 'include/configs')
-rw-r--r--include/configs/condor.h41
1 files changed, 41 insertions, 0 deletions
diff --git a/include/configs/condor.h b/include/configs/condor.h
new file mode 100644
index 0000000..e3c146e
--- /dev/null
+++ b/include/configs/condor.h
@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * include/configs/condor.h
+ * This file is Condor board configuration.
+ *
+ * Copyright (C) 2019 Renesas Electronics Corporation
+ */
+
+#ifndef __CONDOR_H
+#define __CONDOR_H
+
+#include "rcar-gen3-common.h"
+
+/* Ethernet RAVB */
+#define CONFIG_BITBANGMII
+#define CONFIG_BITBANGMII_MULTI
+
+/* Environment compatibility */
+#undef CONFIG_ENV_SIZE_REDUND
+#undef CONFIG_ENV_SECT_SIZE
+#define CONFIG_ENV_SECT_SIZE (256 * 1024)
+#define CONFIG_ENV_OFFSET 0x700000
+
+/* SH Ether */
+#define CONFIG_SH_ETHER_USE_PORT 0
+#define CONFIG_SH_ETHER_PHY_ADDR 0x1
+#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
+#define CONFIG_SH_ETHER_CACHE_WRITEBACK
+#define CONFIG_SH_ETHER_CACHE_INVALIDATE
+#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
+#define CONFIG_BITBANGMII
+#define CONFIG_BITBANGMII_MULTI
+
+/* Board Clock */
+/* XTAL_CLK : 33.33MHz */
+#define CONFIG_SYS_CLK_FREQ 33333333u
+
+/* Generic Timer Definitions (use in assembler source) */
+#define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */
+
+#endif /* __CONDOR_H */