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| author | Mario Six <mario.six@gdsys.cc> | 2019-01-21 09:17:53 +0100 |
|---|---|---|
| committer | Mario Six <mario.six@gdsys.cc> | 2019-05-21 07:52:06 +0200 |
| commit | ff3bb0c435e0d10ccb61a8fd2dada3ae72f1f97e (patch) | |
| tree | dad255071cc1ca17121a6dd44ee66688e09ac0fe /include/configs/sbc8349.h | |
| parent | 0f06f57c280eaec528c76ebfca9b22aa181ca8be (diff) | |
| download | u-boot-ff3bb0c435e0d10ccb61a8fd2dada3ae72f1f97e.zip u-boot-ff3bb0c435e0d10ccb61a8fd2dada3ae72f1f97e.tar.gz u-boot-ff3bb0c435e0d10ccb61a8fd2dada3ae72f1f97e.tar.bz2 | |
mpc83xx: Get rid of CONFIG_83XX_CLKIN
MPC83xx uses CONFIG_83XX_CLKIN instead of CONFIG_SYS_CLK_FREQ to set the
system clock. To migrate the architecture, we can replace
CONFIG_83XX_CLKIN with CONFIG_SYS_CLK_FREQ.
To do this
* replace all occurrences of CONFIG_83XX_CLKIN with CONFIG_SYS_CLK_FREQ
* set CONFIG_SYS_CLK_FREQ to the old value of CONFIG_83XX_CLKIN in all
MPC83xx config files
Signed-off-by: Mario Six <mario.six@gdsys.cc>
Diffstat (limited to 'include/configs/sbc8349.h')
| -rw-r--r-- | include/configs/sbc8349.h | 16 |
1 files changed, 0 insertions, 16 deletions
diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index 60eb2cf..2520a77 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -22,27 +22,11 @@ /* Don't enable PCI2 on sbc834x - it doesn't exist physically. */ #undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */ -/* - * The default if PCI isn't enabled, or if no PCI clk setting is given - * is 66MHz; this is what the board defaults to when the PCI slot is - * physically empty. The board will automatically (i.e w/o jumpers) - * clock down to 33MHz if you insert a 33MHz PCI card. - */ #ifdef CONFIG_PCI_33M -#define CONFIG_83XX_CLKIN 33000000 /* in Hz */ -#else /* 66M */ -#define CONFIG_83XX_CLKIN 66000000 /* in Hz */ -#endif - -#ifndef CONFIG_SYS_CLK_FREQ -#ifdef CONFIG_PCI_33M -#define CONFIG_SYS_CLK_FREQ 33000000 #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1 #else /* 66M */ -#define CONFIG_SYS_CLK_FREQ 66000000 #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1 #endif -#endif #define CONFIG_SYS_IMMR 0xE0000000 |